2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
28 #include "archop.h" /* we need this for Min and Max nodes */
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
40 #include "ia32_optimize.h"
41 #include "ia32_util.h"
43 #include "gen_ia32_regalloc_if.h"
45 #define SFP_SIGN "0x80000000"
46 #define DFP_SIGN "0x8000000000000000"
47 #define SFP_ABS "0x7FFFFFFF"
48 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
50 #define TP_SFP_SIGN "ia32_sfp_sign"
51 #define TP_DFP_SIGN "ia32_dfp_sign"
52 #define TP_SFP_ABS "ia32_sfp_abs"
53 #define TP_DFP_ABS "ia32_dfp_abs"
55 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
56 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
57 #define ENT_SFP_ABS "IA32_SFP_ABS"
58 #define ENT_DFP_ABS "IA32_DFP_ABS"
60 extern ir_op *get_op_Mulh(void);
62 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
63 ir_node *op1, ir_node *op2, ir_node *mem);
65 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
66 ir_node *op, ir_node *mem);
69 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
72 /****************************************************************************************************
74 * | | | | / _| | | (_)
75 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
76 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
77 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
78 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
80 ****************************************************************************************************/
83 * Returns 1 if irn is a Const representing 0, 0 otherwise
85 static INLINE int is_ia32_Const_0(ir_node *irn) {
86 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
90 * Returns 1 if irn is a Const representing 1, 0 otherwise
92 static INLINE int is_ia32_Const_1(ir_node *irn) {
93 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
97 * Returns the Proj representing the UNKNOWN register for given mode.
99 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
100 be_abi_irg_t *babi = cg->birg->abi;
101 const arch_register_t *unknwn_reg = NULL;
103 if (mode_is_float(mode)) {
104 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
107 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
110 return be_abi_get_callee_save_irn(babi, unknwn_reg);
114 * Gets the Proj with number pn from irn.
116 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
117 const ir_edge_t *edge;
119 assert(get_irn_mode(irn) == mode_T && "need mode_T");
121 foreach_out_edge(irn, edge) {
122 proj = get_edge_src_irn(edge);
124 if (get_Proj_proj(proj) == pn)
132 * SSE convert of an integer node into a floating point node.
134 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
135 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
137 ir_node *noreg = ia32_new_NoReg_gp(cg);
138 ir_node *nomem = new_rd_NoMem(irg);
140 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
141 set_ia32_src_mode(conv, get_irn_mode(in));
142 set_ia32_tgt_mode(conv, tgt_mode);
143 set_ia32_am_support(conv, ia32_am_Source);
144 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
146 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
149 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
150 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
151 static const struct {
153 const char *ent_name;
154 const char *cnst_str;
155 } names [ia32_known_const_max] = {
156 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
157 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
158 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
159 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
161 static struct entity *ent_cache[ia32_known_const_max];
163 const char *tp_name, *ent_name, *cnst_str;
170 ent_name = names[kct].ent_name;
171 if (! ent_cache[kct]) {
172 tp_name = names[kct].tp_name;
173 cnst_str = names[kct].cnst_str;
175 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
176 tp = new_type_primitive(new_id_from_str(tp_name), mode);
177 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
179 set_entity_ld_ident(ent, get_entity_ident(ent));
180 set_entity_visibility(ent, visibility_local);
181 set_entity_variability(ent, variability_constant);
182 set_entity_allocation(ent, allocation_static);
184 /* we create a new entity here: It's initialization must resist on the
186 rem = current_ir_graph;
187 current_ir_graph = get_const_code_irg();
188 cnst = new_Const(mode, tv);
189 current_ir_graph = rem;
191 set_atomic_ent_value(ent, cnst);
193 /* cache the entry */
194 ent_cache[kct] = ent;
197 return get_entity_ident(ent_cache[kct]);
202 * Prints the old node name on cg obst and returns a pointer to it.
204 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
205 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
207 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
208 obstack_1grow(isa->name_obst, 0);
209 isa->name_obst_size += obstack_object_size(isa->name_obst);
210 return obstack_finish(isa->name_obst);
214 /* determine if one operator is an Imm */
215 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
217 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
218 else return is_ia32_Cnst(op2) ? op2 : NULL;
221 /* determine if one operator is not an Imm */
222 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
223 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
228 * Construct a standard binary operation, set AM and immediate if required.
230 * @param env The transformation environment
231 * @param op1 The first operand
232 * @param op2 The second operand
233 * @param func The node constructor function
234 * @return The constructed ia32 node.
236 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
237 ir_node *new_op = NULL;
238 ir_mode *mode = env->mode;
239 dbg_info *dbg = env->dbg;
240 ir_graph *irg = env->irg;
241 ir_node *block = env->block;
242 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
243 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
244 ir_node *nomem = new_NoMem();
245 ir_node *expr_op, *imm_op;
246 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
248 /* Check if immediate optimization is on and */
249 /* if it's an operation with immediate. */
250 /* MulS and Mulh don't support immediates */
251 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
252 func == new_rd_ia32_Mulh ||
253 func == new_rd_ia32_MulS)
258 else if (is_op_commutative(get_irn_op(env->irn))) {
259 imm_op = get_immediate_op(op1, op2);
260 expr_op = get_expr_op(op1, op2);
263 imm_op = get_immediate_op(NULL, op2);
264 expr_op = get_expr_op(op1, op2);
267 assert((expr_op || imm_op) && "invalid operands");
270 /* We have two consts here: not yet supported */
274 if (mode_is_float(mode)) {
275 /* floating point operations */
277 DB((mod, LEVEL_1, "FP with immediate ..."));
278 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
279 set_ia32_Immop_attr(new_op, imm_op);
280 set_ia32_am_support(new_op, ia32_am_None);
283 DB((mod, LEVEL_1, "FP binop ..."));
284 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
285 set_ia32_am_support(new_op, ia32_am_Source);
287 set_ia32_ls_mode(new_op, mode);
290 /* integer operations */
292 /* This is expr + const */
293 DB((mod, LEVEL_1, "INT with immediate ..."));
294 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
295 set_ia32_Immop_attr(new_op, imm_op);
298 set_ia32_am_support(new_op, ia32_am_Dest);
301 DB((mod, LEVEL_1, "INT binop ..."));
302 /* This is a normal operation */
303 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
306 set_ia32_am_support(new_op, ia32_am_Full);
310 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
312 set_ia32_res_mode(new_op, mode);
314 if (is_op_commutative(get_irn_op(env->irn))) {
315 set_ia32_commutative(new_op);
318 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
324 * Construct a shift/rotate binary operation, sets AM and immediate if required.
326 * @param env The transformation environment
327 * @param op1 The first operand
328 * @param op2 The second operand
329 * @param func The node constructor function
330 * @return The constructed ia32 node.
332 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
333 ir_node *new_op = NULL;
334 ir_mode *mode = env->mode;
335 dbg_info *dbg = env->dbg;
336 ir_graph *irg = env->irg;
337 ir_node *block = env->block;
338 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
339 ir_node *nomem = new_NoMem();
340 ir_node *expr_op, *imm_op;
342 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
344 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
346 /* Check if immediate optimization is on and */
347 /* if it's an operation with immediate. */
348 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
349 expr_op = get_expr_op(op1, op2);
351 assert((expr_op || imm_op) && "invalid operands");
354 /* We have two consts here: not yet supported */
358 /* Limit imm_op within range imm8 */
360 tv = get_ia32_Immop_tarval(imm_op);
363 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
364 set_ia32_Immop_tarval(imm_op, tv);
371 /* integer operations */
373 /* This is shift/rot with const */
374 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
376 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
377 set_ia32_Immop_attr(new_op, imm_op);
380 /* This is a normal shift/rot */
381 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
382 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
386 set_ia32_am_support(new_op, ia32_am_Dest);
388 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
390 set_ia32_res_mode(new_op, mode);
391 set_ia32_emit_cl(new_op);
393 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
398 * Construct a standard unary operation, set AM and immediate if required.
400 * @param env The transformation environment
401 * @param op The operand
402 * @param func The node constructor function
403 * @return The constructed ia32 node.
405 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
406 ir_node *new_op = NULL;
407 ir_mode *mode = env->mode;
408 dbg_info *dbg = env->dbg;
409 ir_graph *irg = env->irg;
410 ir_node *block = env->block;
411 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
412 ir_node *nomem = new_NoMem();
413 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
415 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
417 if (mode_is_float(mode)) {
418 DB((mod, LEVEL_1, "FP unop ..."));
419 /* floating point operations don't support implicit store */
420 set_ia32_am_support(new_op, ia32_am_None);
423 DB((mod, LEVEL_1, "INT unop ..."));
424 set_ia32_am_support(new_op, ia32_am_Dest);
427 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
429 set_ia32_res_mode(new_op, mode);
431 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
437 * Creates an ia32 Add with immediate.
439 * @param env The transformation environment
440 * @param expr_op The expression operator
441 * @param const_op The constant
442 * @return the created ia32 Add node
444 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
445 ir_node *new_op = NULL;
446 tarval *tv = get_ia32_Immop_tarval(const_op);
447 dbg_info *dbg = env->dbg;
448 ir_graph *irg = env->irg;
449 ir_node *block = env->block;
450 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
451 ir_node *nomem = new_NoMem();
453 tarval_classification_t class_tv, class_negtv;
454 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
456 /* try to optimize to inc/dec */
457 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
458 /* optimize tarvals */
459 class_tv = classify_tarval(tv);
460 class_negtv = classify_tarval(tarval_neg(tv));
462 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
463 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
464 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
467 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
468 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
469 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
475 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
476 set_ia32_Immop_attr(new_op, const_op);
477 set_ia32_commutative(new_op);
484 * Creates an ia32 Add.
486 * @param env The transformation environment
487 * @return the created ia32 Add node
489 static ir_node *gen_Add(ia32_transform_env_t *env) {
490 ir_node *new_op = NULL;
491 dbg_info *dbg = env->dbg;
492 ir_mode *mode = env->mode;
493 ir_graph *irg = env->irg;
494 ir_node *block = env->block;
495 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
496 ir_node *nomem = new_NoMem();
497 ir_node *expr_op, *imm_op;
498 ir_node *op1 = get_Add_left(env->irn);
499 ir_node *op2 = get_Add_right(env->irn);
501 /* Check if immediate optimization is on and */
502 /* if it's an operation with immediate. */
503 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
504 expr_op = get_expr_op(op1, op2);
506 assert((expr_op || imm_op) && "invalid operands");
508 if (mode_is_float(mode)) {
510 if (USE_SSE2(env->cg))
511 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
513 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
518 /* No expr_op means, that we have two const - one symconst and */
519 /* one tarval or another symconst - because this case is not */
520 /* covered by constant folding */
521 /* We need to check for: */
522 /* 1) symconst + const -> becomes a LEA */
523 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
524 /* linker doesn't support two symconsts */
526 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
527 /* this is the 2nd case */
528 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
529 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
530 set_ia32_am_flavour(new_op, ia32_am_OB);
532 DBG_OPT_LEA1(op2, new_op);
535 /* this is the 1st case */
536 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
538 DBG_OPT_LEA2(op1, op2, new_op);
540 if (get_ia32_op_type(op1) == ia32_SymConst) {
541 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
542 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
545 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
546 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
548 set_ia32_am_flavour(new_op, ia32_am_O);
552 set_ia32_am_support(new_op, ia32_am_Source);
553 set_ia32_op_type(new_op, ia32_AddrModeS);
555 /* Lea doesn't need a Proj */
559 /* This is expr + const */
560 new_op = gen_imm_Add(env, expr_op, imm_op);
563 set_ia32_am_support(new_op, ia32_am_Dest);
566 /* This is a normal add */
567 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
570 set_ia32_am_support(new_op, ia32_am_Full);
571 set_ia32_commutative(new_op);
575 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
577 set_ia32_res_mode(new_op, mode);
579 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
585 * Creates an ia32 Mul.
587 * @param env The transformation environment
588 * @return the created ia32 Mul node
590 static ir_node *gen_Mul(ia32_transform_env_t *env) {
591 ir_node *op1 = get_Mul_left(env->irn);
592 ir_node *op2 = get_Mul_right(env->irn);
595 if (mode_is_float(env->mode)) {
597 if (USE_SSE2(env->cg))
598 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
600 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
603 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
612 * Creates an ia32 Mulh.
613 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
614 * this result while Mul returns the lower 32 bit.
616 * @param env The transformation environment
617 * @return the created ia32 Mulh node
619 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
620 ir_node *op1 = get_irn_n(env->irn, 0);
621 ir_node *op2 = get_irn_n(env->irn, 1);
622 ir_node *proj_EAX, *proj_EDX, *mulh;
625 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
626 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
627 mulh = get_Proj_pred(proj_EAX);
628 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
630 /* to be on the save side */
631 set_Proj_proj(proj_EAX, pn_EAX);
633 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
634 /* Mulh with const cannot have AM */
635 set_ia32_am_support(mulh, ia32_am_None);
638 /* Mulh cannot have AM for destination */
639 set_ia32_am_support(mulh, ia32_am_Source);
645 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
653 * Creates an ia32 And.
655 * @param env The transformation environment
656 * @return The created ia32 And node
658 static ir_node *gen_And(ia32_transform_env_t *env) {
659 ir_node *op1 = get_And_left(env->irn);
660 ir_node *op2 = get_And_right(env->irn);
662 assert (! mode_is_float(env->mode));
663 return gen_binop(env, op1, op2, new_rd_ia32_And);
669 * Creates an ia32 Or.
671 * @param env The transformation environment
672 * @return The created ia32 Or node
674 static ir_node *gen_Or(ia32_transform_env_t *env) {
675 ir_node *op1 = get_Or_left(env->irn);
676 ir_node *op2 = get_Or_right(env->irn);
678 assert (! mode_is_float(env->mode));
679 return gen_binop(env, op1, op2, new_rd_ia32_Or);
685 * Creates an ia32 Eor.
687 * @param env The transformation environment
688 * @return The created ia32 Eor node
690 static ir_node *gen_Eor(ia32_transform_env_t *env) {
691 ir_node *op1 = get_Eor_left(env->irn);
692 ir_node *op2 = get_Eor_right(env->irn);
694 assert(! mode_is_float(env->mode));
695 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
701 * Creates an ia32 Max.
703 * @param env The transformation environment
704 * @return the created ia32 Max node
706 static ir_node *gen_Max(ia32_transform_env_t *env) {
707 ir_node *op1 = get_irn_n(env->irn, 0);
708 ir_node *op2 = get_irn_n(env->irn, 1);
711 if (mode_is_float(env->mode)) {
713 if (USE_SSE2(env->cg))
714 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
720 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
721 set_ia32_am_support(new_op, ia32_am_None);
722 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
731 * Creates an ia32 Min.
733 * @param env The transformation environment
734 * @return the created ia32 Min node
736 static ir_node *gen_Min(ia32_transform_env_t *env) {
737 ir_node *op1 = get_irn_n(env->irn, 0);
738 ir_node *op2 = get_irn_n(env->irn, 1);
741 if (mode_is_float(env->mode)) {
743 if (USE_SSE2(env->cg))
744 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
750 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
751 set_ia32_am_support(new_op, ia32_am_None);
752 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
761 * Creates an ia32 Sub with immediate.
763 * @param env The transformation environment
764 * @param expr_op The first operator
765 * @param const_op The constant operator
766 * @return The created ia32 Sub node
768 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
769 ir_node *new_op = NULL;
770 tarval *tv = get_ia32_Immop_tarval(const_op);
771 dbg_info *dbg = env->dbg;
772 ir_graph *irg = env->irg;
773 ir_node *block = env->block;
774 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
775 ir_node *nomem = new_NoMem();
777 tarval_classification_t class_tv, class_negtv;
778 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
780 /* try to optimize to inc/dec */
781 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
782 /* optimize tarvals */
783 class_tv = classify_tarval(tv);
784 class_negtv = classify_tarval(tarval_neg(tv));
786 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
787 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
788 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
791 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
792 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
793 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
799 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
800 set_ia32_Immop_attr(new_op, const_op);
807 * Creates an ia32 Sub.
809 * @param env The transformation environment
810 * @return The created ia32 Sub node
812 static ir_node *gen_Sub(ia32_transform_env_t *env) {
813 ir_node *new_op = NULL;
814 dbg_info *dbg = env->dbg;
815 ir_mode *mode = env->mode;
816 ir_graph *irg = env->irg;
817 ir_node *block = env->block;
818 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
819 ir_node *nomem = new_NoMem();
820 ir_node *op1 = get_Sub_left(env->irn);
821 ir_node *op2 = get_Sub_right(env->irn);
822 ir_node *expr_op, *imm_op;
824 /* Check if immediate optimization is on and */
825 /* if it's an operation with immediate. */
826 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
827 expr_op = get_expr_op(op1, op2);
829 assert((expr_op || imm_op) && "invalid operands");
831 if (mode_is_float(mode)) {
833 if (USE_SSE2(env->cg))
834 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
836 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
841 /* No expr_op means, that we have two const - one symconst and */
842 /* one tarval or another symconst - because this case is not */
843 /* covered by constant folding */
844 /* We need to check for: */
845 /* 1) symconst + const -> becomes a LEA */
846 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
847 /* linker doesn't support two symconsts */
849 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
850 /* this is the 2nd case */
851 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
852 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
853 set_ia32_am_sc_sign(new_op);
854 set_ia32_am_flavour(new_op, ia32_am_OB);
856 DBG_OPT_LEA1(op2, new_op);
859 /* this is the 1st case */
860 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
862 DBG_OPT_LEA2(op1, op2, new_op);
864 if (get_ia32_op_type(op1) == ia32_SymConst) {
865 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
866 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
869 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
870 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
871 set_ia32_am_sc_sign(new_op);
873 set_ia32_am_flavour(new_op, ia32_am_O);
877 set_ia32_am_support(new_op, ia32_am_Source);
878 set_ia32_op_type(new_op, ia32_AddrModeS);
880 /* Lea doesn't need a Proj */
884 /* This is expr - const */
885 new_op = gen_imm_Sub(env, expr_op, imm_op);
888 set_ia32_am_support(new_op, ia32_am_Dest);
891 /* This is a normal sub */
892 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
895 set_ia32_am_support(new_op, ia32_am_Full);
899 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
901 set_ia32_res_mode(new_op, mode);
903 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
909 * Generates an ia32 DivMod with additional infrastructure for the
910 * register allocator if needed.
912 * @param env The transformation environment
913 * @param dividend -no comment- :)
914 * @param divisor -no comment- :)
915 * @param dm_flav flavour_Div/Mod/DivMod
916 * @return The created ia32 DivMod node
918 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
920 ir_node *edx_node, *cltd;
922 dbg_info *dbg = env->dbg;
923 ir_graph *irg = env->irg;
924 ir_node *block = env->block;
925 ir_mode *mode = env->mode;
926 ir_node *irn = env->irn;
932 mem = get_Div_mem(irn);
933 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
936 mem = get_Mod_mem(irn);
937 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
940 mem = get_DivMod_mem(irn);
941 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
947 if (mode_is_signed(mode)) {
948 /* in signed mode, we need to sign extend the dividend */
949 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
950 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
951 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
954 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
955 set_ia32_Const_type(edx_node, ia32_Const);
956 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
959 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
961 set_ia32_n_res(res, 2);
963 /* Only one proj is used -> We must add a second proj and */
964 /* connect this one to a Keep node to eat up the second */
965 /* destroyed register. */
966 n = get_irn_n_edges(irn);
969 proj = ia32_get_proj_for_mode(irn, mode_M);
971 /* in case of two projs, one must be the memory proj */
972 if (n == 1 || (n == 2 && proj)) {
973 proj = ia32_get_res_proj(irn);
974 assert(proj && "Result proj expected");
976 if (get_irn_op(irn) == op_Div) {
977 set_Proj_proj(proj, pn_DivMod_res_div);
978 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
981 set_Proj_proj(proj, pn_DivMod_res_mod);
982 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
985 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
988 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
990 set_ia32_res_mode(res, mode);
997 * Wrapper for generate_DivMod. Sets flavour_Mod.
999 * @param env The transformation environment
1001 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1002 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1006 * Wrapper for generate_DivMod. Sets flavour_Div.
1008 * @param env The transformation environment
1010 static ir_node *gen_Div(ia32_transform_env_t *env) {
1011 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1015 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1017 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1018 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1024 * Creates an ia32 floating Div.
1026 * @param env The transformation environment
1027 * @return The created ia32 xDiv node
1029 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1030 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1032 ir_node *nomem = new_rd_NoMem(env->irg);
1033 ir_node *op1 = get_Quot_left(env->irn);
1034 ir_node *op2 = get_Quot_right(env->irn);
1037 if (USE_SSE2(env->cg)) {
1038 if (is_ia32_xConst(op2)) {
1039 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1040 set_ia32_am_support(new_op, ia32_am_None);
1041 set_ia32_Immop_attr(new_op, op2);
1044 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1045 set_ia32_am_support(new_op, ia32_am_Source);
1049 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1050 set_ia32_am_support(new_op, ia32_am_Source);
1052 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1053 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1061 * Creates an ia32 Shl.
1063 * @param env The transformation environment
1064 * @return The created ia32 Shl node
1066 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1067 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1073 * Creates an ia32 Shr.
1075 * @param env The transformation environment
1076 * @return The created ia32 Shr node
1078 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1079 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1085 * Creates an ia32 Shrs.
1087 * @param env The transformation environment
1088 * @return The created ia32 Shrs node
1090 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1091 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1097 * Creates an ia32 RotL.
1099 * @param env The transformation environment
1100 * @param op1 The first operator
1101 * @param op2 The second operator
1102 * @return The created ia32 RotL node
1104 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1105 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1111 * Creates an ia32 RotR.
1112 * NOTE: There is no RotR with immediate because this would always be a RotL
1113 * "imm-mode_size_bits" which can be pre-calculated.
1115 * @param env The transformation environment
1116 * @param op1 The first operator
1117 * @param op2 The second operator
1118 * @return The created ia32 RotR node
1120 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1121 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1127 * Creates an ia32 RotR or RotL (depending on the found pattern).
1129 * @param env The transformation environment
1130 * @return The created ia32 RotL or RotR node
1132 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1133 ir_node *rotate = NULL;
1134 ir_node *op1 = get_Rot_left(env->irn);
1135 ir_node *op2 = get_Rot_right(env->irn);
1137 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1138 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1139 that means we can create a RotR instead of an Add and a RotL */
1142 ir_node *pred = get_Proj_pred(op2);
1144 if (is_ia32_Add(pred)) {
1145 ir_node *pred_pred = get_irn_n(pred, 2);
1146 tarval *tv = get_ia32_Immop_tarval(pred);
1147 long bits = get_mode_size_bits(env->mode);
1149 if (is_Proj(pred_pred)) {
1150 pred_pred = get_Proj_pred(pred_pred);
1153 if (is_ia32_Minus(pred_pred) &&
1154 tarval_is_long(tv) &&
1155 get_tarval_long(tv) == bits)
1157 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1158 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1165 rotate = gen_RotL(env, op1, op2);
1174 * Transforms a Minus node.
1176 * @param env The transformation environment
1177 * @param op The Minus operand
1178 * @return The created ia32 Minus node
1180 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1185 if (mode_is_float(env->mode)) {
1187 if (USE_SSE2(env->cg)) {
1188 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1189 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1190 ir_node *nomem = new_rd_NoMem(env->irg);
1192 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1194 size = get_mode_size_bits(env->mode);
1195 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1197 set_ia32_sc(new_op, name);
1199 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1201 set_ia32_res_mode(new_op, env->mode);
1202 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1204 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1207 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1208 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1212 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1219 * Transforms a Minus node.
1221 * @param env The transformation environment
1222 * @return The created ia32 Minus node
1224 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1225 return gen_Minus_ex(env, get_Minus_op(env->irn));
1230 * Transforms a Not node.
1232 * @param env The transformation environment
1233 * @return The created ia32 Not node
1235 static ir_node *gen_Not(ia32_transform_env_t *env) {
1236 assert (! mode_is_float(env->mode));
1237 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1243 * Transforms an Abs node.
1245 * @param env The transformation environment
1246 * @return The created ia32 Abs node
1248 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1249 ir_node *res, *p_eax, *p_edx;
1250 dbg_info *dbg = env->dbg;
1251 ir_mode *mode = env->mode;
1252 ir_graph *irg = env->irg;
1253 ir_node *block = env->block;
1254 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1255 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1256 ir_node *nomem = new_NoMem();
1257 ir_node *op = get_Abs_op(env->irn);
1261 if (mode_is_float(mode)) {
1263 if (USE_SSE2(env->cg)) {
1264 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1266 size = get_mode_size_bits(mode);
1267 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1269 set_ia32_sc(res, name);
1271 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1273 set_ia32_res_mode(res, mode);
1274 set_ia32_immop_type(res, ia32_ImmSymConst);
1276 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1279 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1284 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1286 set_ia32_res_mode(res, mode);
1288 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1289 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1291 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1292 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1293 set_ia32_res_mode(res, mode);
1295 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1297 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1298 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1299 set_ia32_res_mode(res, mode);
1301 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1310 * Transforms a Load.
1312 * @param env The transformation environment
1313 * @return the created ia32 Load node
1315 static ir_node *gen_Load(ia32_transform_env_t *env) {
1316 ir_node *node = env->irn;
1317 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1318 ir_node *ptr = get_Load_ptr(node);
1319 ir_node *lptr = ptr;
1320 ir_mode *mode = get_Load_mode(node);
1323 ia32_am_flavour_t am_flav = ia32_am_B;
1325 /* address might be a constant (symconst or absolute address) */
1326 if (is_ia32_Const(ptr)) {
1331 if (mode_is_float(mode)) {
1333 if (USE_SSE2(env->cg))
1334 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1336 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1339 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1342 /* base is an constant address */
1344 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1345 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1346 am_flav = ia32_am_N;
1349 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1350 am_flav = ia32_am_O;
1354 set_ia32_am_support(new_op, ia32_am_Source);
1355 set_ia32_op_type(new_op, ia32_AddrModeS);
1356 set_ia32_am_flavour(new_op, am_flav);
1357 set_ia32_ls_mode(new_op, mode);
1360 check for special case: the loaded value might not be used (optimized, volatile, ...)
1361 we add a Proj + Keep for volatile loads and ignore all other cases
1363 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1364 /* add a result proj and a Keep to produce a pseudo use */
1365 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1366 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1369 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1377 * Transforms a Store.
1379 * @param env The transformation environment
1380 * @return the created ia32 Store node
1382 static ir_node *gen_Store(ia32_transform_env_t *env) {
1383 ir_node *node = env->irn;
1384 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1385 ir_node *val = get_Store_value(node);
1386 ir_node *ptr = get_Store_ptr(node);
1387 ir_node *sptr = ptr;
1388 ir_node *mem = get_Store_mem(node);
1389 ir_mode *mode = get_irn_link(node);
1390 ir_node *sval = val;
1393 ia32_am_flavour_t am_flav = ia32_am_B;
1394 ia32_immop_type_t immop = ia32_ImmNone;
1396 if (! mode_is_float(mode)) {
1397 /* in case of storing a const (but not a symconst) -> make it an attribute */
1398 if (is_ia32_Cnst(val)) {
1399 switch (get_ia32_op_type(val)) {
1401 immop = ia32_ImmConst;
1404 immop = ia32_ImmSymConst;
1407 assert(0 && "unsupported Const type");
1413 /* address might be a constant (symconst or absolute address) */
1414 if (is_ia32_Const(ptr)) {
1419 if (mode_is_float(mode)) {
1421 if (USE_SSE2(env->cg))
1422 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1424 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1426 else if (get_mode_size_bits(mode) == 8) {
1427 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1430 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1433 /* stored const is an attribute (saves a register) */
1434 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1435 set_ia32_Immop_attr(new_op, val);
1438 /* base is an constant address */
1440 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1441 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1442 am_flav = ia32_am_N;
1445 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1446 am_flav = ia32_am_O;
1450 set_ia32_am_support(new_op, ia32_am_Dest);
1451 set_ia32_op_type(new_op, ia32_AddrModeD);
1452 set_ia32_am_flavour(new_op, am_flav);
1453 set_ia32_ls_mode(new_op, mode);
1454 set_ia32_immop_type(new_op, immop);
1456 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1464 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1466 * @param env The transformation environment
1467 * @return The transformed node.
1469 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1470 dbg_info *dbg = env->dbg;
1471 ir_graph *irg = env->irg;
1472 ir_node *block = env->block;
1473 ir_node *node = env->irn;
1474 ir_node *sel = get_Cond_selector(node);
1475 ir_mode *sel_mode = get_irn_mode(sel);
1476 ir_node *res = NULL;
1477 ir_node *pred = NULL;
1478 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1479 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1481 if (is_Proj(sel) && sel_mode == mode_b) {
1482 ir_node *nomem = new_NoMem();
1484 pred = get_Proj_pred(sel);
1486 /* get both compare operators */
1487 cmp_a = get_Cmp_left(pred);
1488 cmp_b = get_Cmp_right(pred);
1490 /* check if we can use a CondJmp with immediate */
1491 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1492 expr = get_expr_op(cmp_a, cmp_b);
1495 pn_Cmp pnc = get_Proj_proj(sel);
1497 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1498 if (get_ia32_op_type(cnst) == ia32_Const &&
1499 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1501 /* a Cmp A =/!= 0 */
1502 ir_node *op1 = expr;
1503 ir_node *op2 = expr;
1504 ir_node *and = skip_Proj(expr);
1505 const char *cnst = NULL;
1507 /* check, if expr is an only once used And operation */
1508 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1509 op1 = get_irn_n(and, 2);
1510 op2 = get_irn_n(and, 3);
1512 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1514 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1515 set_ia32_pncode(res, get_Proj_proj(sel));
1516 set_ia32_res_mode(res, get_irn_mode(op1));
1519 copy_ia32_Immop_attr(res, and);
1522 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1527 if (mode_is_float(get_irn_mode(expr))) {
1529 if (USE_SSE2(env->cg))
1530 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1536 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1538 set_ia32_Immop_attr(res, cnst);
1539 set_ia32_res_mode(res, get_irn_mode(expr));
1542 if (mode_is_float(get_irn_mode(cmp_a))) {
1544 if (USE_SSE2(env->cg))
1545 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1548 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1549 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1550 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1554 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1555 set_ia32_commutative(res);
1557 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1560 set_ia32_pncode(res, get_Proj_proj(sel));
1561 //set_ia32_am_support(res, ia32_am_Source);
1564 /* determine the smallest switch case value */
1565 int switch_min = INT_MAX;
1566 const ir_edge_t *edge;
1569 foreach_out_edge(node, edge) {
1570 int pn = get_Proj_proj(get_edge_src_irn(edge));
1571 switch_min = pn < switch_min ? pn : switch_min;
1575 /* if smallest switch case is not 0 we need an additional sub */
1576 snprintf(buf, sizeof(buf), "%d", switch_min);
1577 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1578 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1579 sub_ia32_am_offs(res, buf);
1580 set_ia32_am_flavour(res, ia32_am_OB);
1581 set_ia32_am_support(res, ia32_am_Source);
1582 set_ia32_op_type(res, ia32_AddrModeS);
1585 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1586 set_ia32_pncode(res, get_Cond_defaultProj(node));
1587 set_ia32_res_mode(res, get_irn_mode(sel));
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1597 * Transforms a CopyB node.
1599 * @param env The transformation environment
1600 * @return The transformed node.
1602 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1603 ir_node *res = NULL;
1604 dbg_info *dbg = env->dbg;
1605 ir_graph *irg = env->irg;
1606 ir_mode *mode = env->mode;
1607 ir_node *block = env->block;
1608 ir_node *node = env->irn;
1609 ir_node *src = get_CopyB_src(node);
1610 ir_node *dst = get_CopyB_dst(node);
1611 ir_node *mem = get_CopyB_mem(node);
1612 int size = get_type_size_bytes(get_CopyB_type(node));
1615 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1616 /* then we need the size explicitly in ECX. */
1617 if (size >= 16 * 4) {
1618 rem = size & 0x3; /* size % 4 */
1621 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1622 set_ia32_op_type(res, ia32_Const);
1623 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1625 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1626 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1629 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1630 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1631 set_ia32_immop_type(res, ia32_ImmConst);
1634 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1642 * Transforms a Mux node into CMov.
1644 * @param env The transformation environment
1645 * @return The transformed node.
1647 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1649 ir_node *node = env->irn;
1650 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1651 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1653 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1660 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1661 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1664 * Transforms a Psi node into CMov.
1666 * @param env The transformation environment
1667 * @return The transformed node.
1669 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1670 ia32_code_gen_t *cg = env->cg;
1671 dbg_info *dbg = env->dbg;
1672 ir_graph *irg = env->irg;
1673 ir_mode *mode = env->mode;
1674 ir_node *block = env->block;
1675 ir_node *node = env->irn;
1676 ir_node *cmp_proj = get_Mux_sel(node);
1677 ir_node *psi_true = get_Psi_val(node, 0);
1678 ir_node *psi_default = get_Psi_default(node);
1679 ir_node *noreg = ia32_new_NoReg_gp(cg);
1680 ir_node *nomem = new_rd_NoMem(irg);
1681 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1684 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1686 cmp = get_Proj_pred(cmp_proj);
1687 cmp_a = get_Cmp_left(cmp);
1688 cmp_b = get_Cmp_right(cmp);
1689 pnc = get_Proj_proj(cmp_proj);
1691 if (mode_is_float(mode)) {
1692 /* floating point psi */
1695 /* 1st case: compare operands are float too */
1697 /* psi(cmp(a, b), t, f) can be done as: */
1698 /* tmp = cmp a, b */
1699 /* tmp2 = t and tmp */
1700 /* tmp3 = f and not tmp */
1701 /* res = tmp2 or tmp3 */
1703 /* in case the compare operands are int, we move them into xmm register */
1704 if (! mode_is_float(get_irn_mode(cmp_a))) {
1705 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1706 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1708 pnc |= 8; /* transform integer compare to fp compare */
1711 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1712 set_ia32_pncode(new_op, pnc);
1713 set_ia32_am_support(new_op, ia32_am_Source);
1714 set_ia32_res_mode(new_op, mode);
1715 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1716 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1718 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1719 set_ia32_am_support(and1, ia32_am_None);
1720 set_ia32_res_mode(and1, mode);
1721 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1722 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1724 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1725 set_ia32_am_support(and2, ia32_am_None);
1726 set_ia32_res_mode(and2, mode);
1727 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1728 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1730 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1731 set_ia32_am_support(new_op, ia32_am_None);
1732 set_ia32_res_mode(new_op, mode);
1733 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1734 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1738 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1739 set_ia32_pncode(new_op, pnc);
1740 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1745 construct_binop_func *set_func = NULL;
1746 cmov_func_t *cmov_func = NULL;
1748 if (mode_is_float(get_irn_mode(cmp_a))) {
1749 /* 1st case: compare operands are floats */
1754 set_func = new_rd_ia32_xCmpSet;
1755 cmov_func = new_rd_ia32_xCmpCMov;
1759 set_func = new_rd_ia32_vfCmpSet;
1760 cmov_func = new_rd_ia32_vfCmpCMov;
1763 pnc &= 7; /* fp compare -> int compare */
1766 /* 2nd case: compare operand are integer too */
1767 set_func = new_rd_ia32_CmpSet;
1768 cmov_func = new_rd_ia32_CmpCMov;
1771 /* create the nodes */
1773 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1774 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1775 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1776 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1777 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1778 set_ia32_pncode(new_op, pnc);
1780 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1781 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1782 /* we invert condition and set default to 0 */
1783 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1784 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1787 /* otherwise: use CMOVcc */
1788 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1789 set_ia32_pncode(new_op, pnc);
1792 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1796 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1797 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1798 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1799 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1800 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1802 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1803 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1804 /* we invert condition and set default to 0 */
1805 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1806 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1807 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1810 /* otherwise: use CMOVcc */
1811 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1812 set_ia32_pncode(new_op, pnc);
1813 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1823 * Following conversion rules apply:
1827 * 1) n bit -> m bit n > m (downscale)
1828 * a) target is signed: movsx
1829 * b) target is unsigned: and with lower bits sets
1830 * 2) n bit -> m bit n == m (sign change)
1832 * 3) n bit -> m bit n < m (upscale)
1833 * a) source is signed: movsx
1834 * b) source is unsigned: and with lower bits sets
1838 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1842 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1843 * if target mode < 32bit: additional INT -> INT conversion (see above)
1847 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1848 * x87 is mode_E internally, conversions happen only at load and store
1849 * in non-strict semantic
1853 * Create a conversion from x87 state register to general purpose.
1855 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1856 ia32_code_gen_t *cg = env->cg;
1857 entity *ent = cg->fp_to_gp;
1858 ir_graph *irg = env->irg;
1859 ir_node *block = env->block;
1860 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1861 ir_node *op = get_Conv_op(env->irn);
1862 ir_node *fist, *mem, *load;
1865 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1866 ent = cg->fp_to_gp =
1867 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1871 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1873 set_ia32_frame_ent(fist, ent);
1874 set_ia32_use_frame(fist);
1875 set_ia32_am_support(fist, ia32_am_Dest);
1876 set_ia32_op_type(fist, ia32_AddrModeD);
1877 set_ia32_am_flavour(fist, ia32_B);
1878 set_ia32_ls_mode(fist, mode_F);
1880 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1883 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1885 set_ia32_frame_ent(load, ent);
1886 set_ia32_use_frame(load);
1887 set_ia32_am_support(load, ia32_am_Source);
1888 set_ia32_op_type(load, ia32_AddrModeS);
1889 set_ia32_am_flavour(load, ia32_B);
1890 set_ia32_ls_mode(load, tgt_mode);
1892 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1896 * Create a conversion from x87 state register to general purpose.
1898 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1899 ia32_code_gen_t *cg = env->cg;
1900 entity *ent = cg->gp_to_fp;
1901 ir_graph *irg = env->irg;
1902 ir_node *block = env->block;
1903 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1904 ir_node *nomem = get_irg_no_mem(irg);
1905 ir_node *op = get_Conv_op(env->irn);
1906 ir_node *fild, *store, *mem;
1910 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1911 ent = cg->gp_to_fp =
1912 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1915 /* first convert to 32 bit */
1916 src_bits = get_mode_size_bits(src_mode);
1917 if (src_bits == 8) {
1918 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1919 op = new_r_Proj(irg, block, op, mode_Is, 0);
1921 else if (src_bits < 32) {
1922 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1923 op = new_r_Proj(irg, block, op, mode_Is, 0);
1927 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1929 set_ia32_frame_ent(store, ent);
1930 set_ia32_use_frame(store);
1932 set_ia32_am_support(store, ia32_am_Dest);
1933 set_ia32_op_type(store, ia32_AddrModeD);
1934 set_ia32_am_flavour(store, ia32_B);
1935 set_ia32_ls_mode(store, mode_Is);
1937 mem = new_r_Proj(irg, block, store, mode_M, 0);
1940 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1942 set_ia32_frame_ent(fild, ent);
1943 set_ia32_use_frame(fild);
1944 set_ia32_am_support(fild, ia32_am_Source);
1945 set_ia32_op_type(fild, ia32_AddrModeS);
1946 set_ia32_am_flavour(fild, ia32_B);
1947 set_ia32_ls_mode(fild, mode_F);
1949 return new_r_Proj(irg, block, fild, mode_F, 0);
1953 * Transforms a Conv node.
1955 * @param env The transformation environment
1956 * @return The created ia32 Conv node
1958 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1959 dbg_info *dbg = env->dbg;
1960 ir_graph *irg = env->irg;
1961 ir_node *op = get_Conv_op(env->irn);
1962 ir_mode *src_mode = get_irn_mode(op);
1963 ir_mode *tgt_mode = env->mode;
1964 int src_bits = get_mode_size_bits(src_mode);
1965 int tgt_bits = get_mode_size_bits(tgt_mode);
1967 ir_node *block = env->block;
1968 ir_node *new_op = NULL;
1969 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1970 ir_node *nomem = new_rd_NoMem(irg);
1972 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1974 if (src_mode == tgt_mode) {
1975 /* this can happen when changing mode_P to mode_Is */
1976 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1977 edges_reroute(env->irn, op, irg);
1979 else if (mode_is_float(src_mode)) {
1980 /* we convert from float ... */
1981 if (mode_is_float(tgt_mode)) {
1983 if (USE_SSE2(env->cg)) {
1984 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1985 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1986 pn = pn_ia32_Conv_FP2FP_res;
1989 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1990 edges_reroute(env->irn, op, irg);
1995 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1996 if (USE_SSE2(env->cg)) {
1997 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1998 pn = pn_ia32_Conv_FP2I_res;
2001 return gen_x87_fp_to_gp(env, tgt_mode);
2003 /* if target mode is not int: add an additional downscale convert */
2004 if (tgt_bits < 32) {
2005 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2006 set_ia32_am_support(new_op, ia32_am_Source);
2007 set_ia32_tgt_mode(new_op, tgt_mode);
2008 set_ia32_src_mode(new_op, src_mode);
2010 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2012 if (tgt_bits == 8 || src_bits == 8) {
2013 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2014 pn = pn_ia32_Conv_I2I8Bit_res;
2017 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2018 pn = pn_ia32_Conv_I2I_res;
2024 /* we convert from int ... */
2025 if (mode_is_float(tgt_mode)) {
2028 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2029 if (USE_SSE2(env->cg)) {
2030 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2031 pn = pn_ia32_Conv_I2FP_res;
2034 return gen_x87_gp_to_fp(env, src_mode);
2038 if (get_mode_size_bits(src_mode) == tgt_bits) {
2039 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2040 edges_reroute(env->irn, op, irg);
2043 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2044 if (tgt_bits == 8 || src_bits == 8) {
2045 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2046 pn = pn_ia32_Conv_I2I8Bit_res;
2049 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2050 pn = pn_ia32_Conv_I2I_res;
2057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2058 set_ia32_tgt_mode(new_op, tgt_mode);
2059 set_ia32_src_mode(new_op, src_mode);
2061 set_ia32_am_support(new_op, ia32_am_Source);
2063 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2071 /********************************************
2074 * | |__ ___ _ __ ___ __| | ___ ___
2075 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2076 * | |_) | __/ | | | (_) | (_| | __/\__ \
2077 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2079 ********************************************/
2082 * Decides in which block the transformed StackParam should be placed.
2083 * If the StackParam has more than one user, the dominator block of
2084 * the users will be returned. In case of only one user, this is either
2085 * the user block or, in case of a Phi, the predecessor block of the Phi.
2087 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2088 ir_node *dom_bl = NULL;
2090 if (get_irn_n_edges(irn) == 1) {
2091 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2093 if (! is_Phi(src)) {
2094 dom_bl = get_nodes_block(src);
2097 /* Determine on which in position of the Phi the irn is */
2098 /* and get the corresponding cfg predecessor block. */
2100 int i = get_irn_pred_pos(src, irn);
2101 assert(i >= 0 && "kaputt");
2102 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2106 dom_bl = node_users_smallest_common_dominator(irn, 1);
2109 assert(dom_bl && "dominator block not found");
2114 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2115 ir_node *new_op = NULL;
2116 ir_node *node = env->irn;
2117 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2118 ir_node *mem = new_rd_NoMem(env->irg);
2119 ir_node *ptr = get_irn_n(node, 0);
2120 entity *ent = be_get_frame_entity(node);
2121 ir_mode *mode = env->mode;
2123 /* choose the block where to place the load */
2124 env->block = get_block_transformed_stack_param(node);
2126 if (mode_is_float(mode)) {
2128 if (USE_SSE2(env->cg))
2129 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2131 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2134 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2137 set_ia32_frame_ent(new_op, ent);
2138 set_ia32_use_frame(new_op);
2140 set_ia32_am_support(new_op, ia32_am_Source);
2141 set_ia32_op_type(new_op, ia32_AddrModeS);
2142 set_ia32_am_flavour(new_op, ia32_B);
2143 set_ia32_ls_mode(new_op, mode);
2145 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2147 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2151 * Transforms a FrameAddr into an ia32 Add.
2153 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2154 ir_node *new_op = NULL;
2155 ir_node *node = env->irn;
2156 ir_node *op = get_irn_n(node, 0);
2157 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2158 ir_node *nomem = new_rd_NoMem(env->irg);
2160 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2161 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2162 set_ia32_am_support(new_op, ia32_am_Full);
2163 set_ia32_use_frame(new_op);
2164 set_ia32_immop_type(new_op, ia32_ImmConst);
2165 set_ia32_commutative(new_op);
2167 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2169 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2173 * Transforms a FrameLoad into an ia32 Load.
2175 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2176 ir_node *new_op = NULL;
2177 ir_node *node = env->irn;
2178 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2179 ir_node *mem = get_irn_n(node, 0);
2180 ir_node *ptr = get_irn_n(node, 1);
2181 entity *ent = be_get_frame_entity(node);
2182 ir_mode *mode = get_type_mode(get_entity_type(ent));
2184 if (mode_is_float(mode)) {
2186 if (USE_SSE2(env->cg))
2187 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2189 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2192 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2194 set_ia32_frame_ent(new_op, ent);
2195 set_ia32_use_frame(new_op);
2197 set_ia32_am_support(new_op, ia32_am_Source);
2198 set_ia32_op_type(new_op, ia32_AddrModeS);
2199 set_ia32_am_flavour(new_op, ia32_B);
2200 set_ia32_ls_mode(new_op, mode);
2202 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2209 * Transforms a FrameStore into an ia32 Store.
2211 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2212 ir_node *new_op = NULL;
2213 ir_node *node = env->irn;
2214 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2215 ir_node *mem = get_irn_n(node, 0);
2216 ir_node *ptr = get_irn_n(node, 1);
2217 ir_node *val = get_irn_n(node, 2);
2218 entity *ent = be_get_frame_entity(node);
2219 ir_mode *mode = get_irn_mode(val);
2221 if (mode_is_float(mode)) {
2223 if (USE_SSE2(env->cg))
2224 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2226 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2228 else if (get_mode_size_bits(mode) == 8) {
2229 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2232 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2235 set_ia32_frame_ent(new_op, ent);
2236 set_ia32_use_frame(new_op);
2238 set_ia32_am_support(new_op, ia32_am_Dest);
2239 set_ia32_op_type(new_op, ia32_AddrModeD);
2240 set_ia32_am_flavour(new_op, ia32_B);
2241 set_ia32_ls_mode(new_op, mode);
2243 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2249 * This function just sets the register for the Unknown node
2250 * as this is not done during register allocation because Unknown
2251 * is an "ignore" node.
2253 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2254 ir_mode *mode = env->mode;
2255 ir_node *irn = env->irn;
2257 if (mode_is_float(mode)) {
2258 if (USE_SSE2(env->cg))
2259 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2261 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2263 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2264 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2267 assert(0 && "unsupported Unknown-Mode");
2273 /**********************************************************************
2276 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2277 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2278 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2279 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2281 **********************************************************************/
2283 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2285 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2288 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2289 ir_node *val, ir_node *mem);
2292 * Transforms a lowered Load into a "real" one.
2294 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2295 ir_node *node = env->irn;
2296 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2297 ir_mode *mode = get_ia32_ls_mode(node);
2300 ia32_am_flavour_t am_flav = ia32_B;
2303 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2304 lowering we have x87 nodes, so we need to enforce simulation.
2306 if (mode_is_float(mode)) {
2308 if (fp_unit == fp_x87)
2312 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2313 am_offs = get_ia32_am_offs(node);
2317 add_ia32_am_offs(new_op, am_offs);
2320 set_ia32_am_support(new_op, ia32_am_Source);
2321 set_ia32_op_type(new_op, ia32_AddrModeS);
2322 set_ia32_am_flavour(new_op, am_flav);
2323 set_ia32_ls_mode(new_op, mode);
2324 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2325 set_ia32_use_frame(new_op);
2327 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2333 * Transforms a lowered Store into a "real" one.
2335 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2336 ir_node *node = env->irn;
2337 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2338 ir_mode *mode = get_ia32_ls_mode(node);
2341 ia32_am_flavour_t am_flav = ia32_B;
2344 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2345 lowering we have x87 nodes, so we need to enforce simulation.
2347 if (mode_is_float(mode)) {
2349 if (fp_unit == fp_x87)
2353 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2355 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2357 add_ia32_am_offs(new_op, am_offs);
2360 set_ia32_am_support(new_op, ia32_am_Dest);
2361 set_ia32_op_type(new_op, ia32_AddrModeD);
2362 set_ia32_am_flavour(new_op, am_flav);
2363 set_ia32_ls_mode(new_op, mode);
2364 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2365 set_ia32_use_frame(new_op);
2367 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2374 * Transforms an ia32_l_XXX into a "real" XXX node
2376 * @param env The transformation environment
2377 * @return the created ia32 XXX node
2379 #define GEN_LOWERED_OP(op) \
2380 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2381 if (mode_is_float(env->mode)) \
2383 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2386 #define GEN_LOWERED_x87_OP(op) \
2387 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2389 FORCE_x87(env->cg); \
2390 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2391 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2395 #define GEN_LOWERED_UNOP(op) \
2396 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2397 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2400 #define GEN_LOWERED_SHIFT_OP(op) \
2401 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2402 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2405 #define GEN_LOWERED_LOAD(op, fp_unit) \
2406 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2407 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2410 #define GEN_LOWERED_STORE(op, fp_unit) \
2411 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2412 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2415 GEN_LOWERED_OP(AddC)
2417 GEN_LOWERED_OP(SubC)
2421 GEN_LOWERED_x87_OP(vfdiv)
2422 GEN_LOWERED_x87_OP(vfmul)
2423 GEN_LOWERED_x87_OP(vfsub)
2425 GEN_LOWERED_UNOP(Minus)
2427 GEN_LOWERED_LOAD(vfild, fp_x87)
2428 GEN_LOWERED_LOAD(Load, fp_none)
2429 GEN_LOWERED_STORE(vfist, fp_x87)
2430 GEN_LOWERED_STORE(Store, fp_none)
2433 * Transforms a l_MulS into a "real" MulS node.
2435 * @param env The transformation environment
2436 * @return the created ia32 MulS node
2438 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2440 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2441 /* and then skip the result Proj, because all needed Projs are already there. */
2443 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2444 ir_node *muls = get_Proj_pred(new_op);
2446 /* MulS cannot have AM for destination */
2447 if (get_ia32_am_support(muls) != ia32_am_None)
2448 set_ia32_am_support(muls, ia32_am_Source);
2453 GEN_LOWERED_SHIFT_OP(Shl)
2454 GEN_LOWERED_SHIFT_OP(Shr)
2455 GEN_LOWERED_SHIFT_OP(Shrs)
2458 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2459 * op1 - target to be shifted
2460 * op2 - contains bits to be shifted into target
2462 * Only op3 can be an immediate.
2464 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2465 ir_node *new_op = NULL;
2466 ir_mode *mode = env->mode;
2467 dbg_info *dbg = env->dbg;
2468 ir_graph *irg = env->irg;
2469 ir_node *block = env->block;
2470 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2471 ir_node *nomem = new_NoMem();
2474 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2476 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2478 /* Check if immediate optimization is on and */
2479 /* if it's an operation with immediate. */
2480 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2482 /* Limit imm_op within range imm8 */
2484 tv = get_ia32_Immop_tarval(imm_op);
2487 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2488 set_ia32_Immop_tarval(imm_op, tv);
2495 /* integer operations */
2497 /* This is ShiftD with const */
2498 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2500 if (is_ia32_l_ShlD(env->irn))
2501 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2503 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2504 set_ia32_Immop_attr(new_op, imm_op);
2507 /* This is a normal ShiftD */
2508 DB((mod, LEVEL_1, "ShiftD binop ..."));
2509 if (is_ia32_l_ShlD(env->irn))
2510 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2512 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2515 /* set AM support */
2516 set_ia32_am_support(new_op, ia32_am_Dest);
2518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2520 set_ia32_res_mode(new_op, mode);
2521 set_ia32_emit_cl(new_op);
2523 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2526 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2527 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2530 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2531 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2535 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2537 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2538 ia32_code_gen_t *cg = env->cg;
2539 ir_node *res = NULL;
2540 ir_node *ptr = get_irn_n(env->irn, 0);
2541 ir_node *val = get_irn_n(env->irn, 1);
2542 ir_node *mem = get_irn_n(env->irn, 2);
2545 ir_node *noreg = ia32_new_NoReg_gp(cg);
2547 /* Store x87 -> MEM */
2548 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2549 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2550 set_ia32_use_frame(res);
2551 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2552 set_ia32_am_support(res, ia32_am_Dest);
2553 set_ia32_am_flavour(res, ia32_B);
2554 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2556 /* Load MEM -> SSE */
2557 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2558 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2559 set_ia32_use_frame(res);
2560 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2561 set_ia32_am_support(res, ia32_am_Source);
2562 set_ia32_am_flavour(res, ia32_B);
2563 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2566 /* SSE unit is not used -> skip this node. */
2569 edges_reroute(env->irn, val, env->irg);
2570 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2571 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2578 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2580 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2581 ia32_code_gen_t *cg = env->cg;
2582 ir_node *res = NULL;
2583 ir_node *ptr = get_irn_n(env->irn, 0);
2584 ir_node *val = get_irn_n(env->irn, 1);
2585 ir_node *mem = get_irn_n(env->irn, 2);
2588 ir_node *noreg = ia32_new_NoReg_gp(cg);
2590 /* Store SSE -> MEM */
2591 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2592 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2593 set_ia32_use_frame(res);
2594 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2595 set_ia32_am_support(res, ia32_am_Dest);
2596 set_ia32_am_flavour(res, ia32_B);
2597 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2599 /* Load MEM -> x87 */
2600 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2601 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2602 set_ia32_use_frame(res);
2603 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2604 set_ia32_am_support(res, ia32_am_Source);
2605 set_ia32_am_flavour(res, ia32_B);
2606 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2609 /* SSE unit is not used -> skip this node. */
2612 edges_reroute(env->irn, val, env->irg);
2613 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2614 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2620 /*********************************************************
2623 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2624 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2625 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2626 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2628 *********************************************************/
2631 * the BAD transformer.
2633 static ir_node *bad_transform(ia32_transform_env_t *env) {
2634 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2640 * Enters all transform functions into the generic pointer
2642 void ia32_register_transformers(void) {
2643 ir_op *op_Max, *op_Min, *op_Mulh;
2645 /* first clear the generic function pointer for all ops */
2646 clear_irp_opcodes_generic_func();
2648 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2649 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2683 /* transform ops from intrinsic lowering */
2704 GEN(ia32_l_X87toSSE);
2705 GEN(ia32_l_SSEtoX87);
2720 /* constant transformation happens earlier */
2744 /* set the register for all Unknown nodes */
2747 op_Max = get_op_Max();
2750 op_Min = get_op_Min();
2753 op_Mulh = get_op_Mulh();
2762 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2765 * Transforms the given firm node (and maybe some other related nodes)
2766 * into one or more assembler nodes.
2768 * @param node the firm node
2769 * @param env the debug module
2771 void ia32_transform_node(ir_node *node, void *env) {
2772 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2773 ir_op *op = get_irn_op(node);
2774 ir_node *asm_node = NULL;
2780 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2781 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2782 if (is_Unknown(get_irn_n(node, i)))
2783 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2786 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2787 if (op->ops.generic) {
2788 ia32_transform_env_t tenv;
2789 transform_func *transform = (transform_func *)op->ops.generic;
2791 tenv.block = get_nodes_block(node);
2792 tenv.dbg = get_irn_dbg_info(node);
2793 tenv.irg = current_ir_graph;
2795 tenv.mode = get_irn_mode(node);
2797 DEBUG_ONLY(tenv.mod = cg->mod;)
2799 asm_node = (*transform)(&tenv);
2802 /* exchange nodes if a new one was generated */
2804 exchange(node, asm_node);
2805 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2808 DB((cg->mod, LEVEL_1, "ignored\n"));
2813 * Transforms a psi condition.
2815 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2818 /* if the mode is target mode, we have already seen this part of the tree */
2819 if (get_irn_mode(cond) == mode)
2822 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2824 set_irn_mode(cond, mode);
2826 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2827 ir_node *in = get_irn_n(cond, i);
2829 /* if in is a compare: transform into Set/xCmp */
2831 ir_node *new_op = NULL;
2832 ir_node *cmp = get_Proj_pred(in);
2833 ir_node *cmp_a = get_Cmp_left(cmp);
2834 ir_node *cmp_b = get_Cmp_right(cmp);
2835 dbg_info *dbg = get_irn_dbg_info(cmp);
2836 ir_graph *irg = get_irn_irg(cmp);
2837 ir_node *block = get_nodes_block(cmp);
2838 ir_node *noreg = ia32_new_NoReg_gp(cg);
2839 ir_node *nomem = new_rd_NoMem(irg);
2840 int pnc = get_Proj_proj(in);
2842 /* this is a compare */
2843 if (mode_is_float(mode)) {
2844 /* Psi is float, we need a floating point compare */
2848 if (! mode_is_float(get_irn_mode(cmp_a))) {
2849 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2850 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2854 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2855 set_ia32_pncode(new_op, pnc);
2856 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2865 ia32_transform_env_t tenv;
2866 construct_binop_func *set_func = NULL;
2868 if (mode_is_float(get_irn_mode(cmp_a))) {
2869 /* 1st case: compare operands are floats */
2874 set_func = new_rd_ia32_xCmpSet;
2878 set_func = new_rd_ia32_vfCmpSet;
2881 pnc &= 7; /* fp compare -> int compare */
2884 /* 2nd case: compare operand are integer too */
2885 set_func = new_rd_ia32_CmpSet;
2896 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2897 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2898 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2901 /* the the new compare as in */
2902 set_irn_n(cond, i, new_op);
2905 /* another complex condition */
2906 transform_psi_cond(in, mode, cg);
2912 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2913 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2914 * compare, which causes the compare result to be stores in a register. The
2915 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2917 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2918 ia32_code_gen_t *cg = env;
2919 ir_node *psi_sel, *new_cmp, *block;
2924 if (get_irn_opcode(node) != iro_Psi)
2927 psi_sel = get_Psi_cond(node, 0);
2929 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2930 if (is_Proj(psi_sel))
2933 mode = get_irn_mode(node);
2935 transform_psi_cond(psi_sel, mode, cg);
2937 irg = get_irn_irg(node);
2938 block = get_nodes_block(node);
2940 /* we need to compare the evaluated condition tree with 0 */
2942 /* BEWARE: new_r_Const_long works for floating point as well */
2943 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2944 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2946 set_Psi_cond(node, 0, new_cmp);