2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
102 /****************************************************************************************************
104 * | | | | / _| | | (_)
105 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
106 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
107 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
108 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
110 ****************************************************************************************************/
112 static ir_node *try_create_Immediate(ir_node *node,
113 char immediate_constraint_type);
116 * Return true if a mode can be stored in the GP register set
118 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
119 if(mode == mode_fpcw)
121 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
125 * Returns 1 if irn is a Const representing 0, 0 otherwise
127 static INLINE int is_ia32_Const_0(ir_node *irn) {
128 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
129 && tarval_is_null(get_ia32_Immop_tarval(irn));
133 * Returns 1 if irn is a Const representing 1, 0 otherwise
135 static INLINE int is_ia32_Const_1(ir_node *irn) {
136 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
137 && tarval_is_one(get_ia32_Immop_tarval(irn));
141 * Collects all Projs of a node into the node array. Index is the projnum.
142 * BEWARE: The caller has to assure the appropriate array size!
144 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
145 const ir_edge_t *edge;
146 assert(get_irn_mode(irn) == mode_T && "need mode_T");
148 memset(projs, 0, size * sizeof(projs[0]));
150 foreach_out_edge(irn, edge) {
151 ir_node *proj = get_edge_src_irn(edge);
152 int proj_proj = get_Proj_proj(proj);
153 assert(proj_proj < size);
154 projs[proj_proj] = proj;
159 * Renumbers the proj having pn_old in the array tp pn_new
160 * and removes the proj from the array.
162 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
163 fprintf(stderr, "Warning: renumber_Proj used!\n");
165 set_Proj_proj(projs[pn_old], pn_new);
166 projs[pn_old] = NULL;
171 * creates a unique ident by adding a number to a tag
173 * @param tag the tag string, must contain a %d if a number
176 static ident *unique_id(const char *tag)
178 static unsigned id = 0;
181 snprintf(str, sizeof(str), tag, ++id);
182 return new_id_from_str(str);
186 * Get a primitive type for a mode.
188 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
190 pmap_entry *e = pmap_find(types, mode);
195 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
196 res = new_type_primitive(new_id_from_str(buf), mode);
197 set_type_alignment_bytes(res, 16);
198 pmap_insert(types, mode, res);
206 * Get an entity that is initialized with a tarval
208 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
210 tarval *tv = get_Const_tarval(cnst);
211 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
216 ir_mode *mode = get_irn_mode(cnst);
217 ir_type *tp = get_Const_type(cnst);
218 if (tp == firm_unknown_type)
219 tp = get_prim_type(cg->isa->types, mode);
221 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
223 set_entity_ld_ident(res, get_entity_ident(res));
224 set_entity_visibility(res, visibility_local);
225 set_entity_variability(res, variability_constant);
226 set_entity_allocation(res, allocation_static);
228 /* we create a new entity here: It's initialization must resist on the
230 rem = current_ir_graph;
231 current_ir_graph = get_const_code_irg();
232 set_atomic_ent_value(res, new_Const_type(tv, tp));
233 current_ir_graph = rem;
235 pmap_insert(cg->isa->tv_ent, tv, res);
243 static int is_Const_0(ir_node *node) {
247 return classify_Const(node) == CNST_NULL;
250 static int is_Const_1(ir_node *node) {
254 return classify_Const(node) == CNST_ONE;
258 * Transforms a Const.
260 static ir_node *gen_Const(ir_node *node) {
261 ir_graph *irg = current_ir_graph;
262 ir_node *block = be_transform_node(get_nodes_block(node));
263 dbg_info *dbgi = get_irn_dbg_info(node);
264 ir_mode *mode = get_irn_mode(node);
266 if (mode_is_float(mode)) {
268 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
269 ir_node *nomem = new_NoMem();
274 if (! USE_SSE2(env_cg)) {
275 cnst_classify_t clss = classify_Const(node);
277 if (clss == CNST_NULL) {
278 load = new_rd_ia32_vfldz(dbgi, irg, block);
280 } else if (clss == CNST_ONE) {
281 load = new_rd_ia32_vfld1(dbgi, irg, block);
284 floatent = get_entity_for_tv(env_cg, node);
286 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
287 set_ia32_am_support(load, ia32_am_Source);
288 set_ia32_op_type(load, ia32_AddrModeS);
289 set_ia32_am_flavour(load, ia32_am_N);
290 set_ia32_am_sc(load, floatent);
291 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
293 set_ia32_ls_mode(load, mode);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
298 set_ia32_am_support(load, ia32_am_Source);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 set_ia32_ls_mode(load, mode);
304 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
307 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
309 /* Const Nodes before the initial IncSP are a bad idea, because
310 * they could be spilled and we have no SP ready at that point yet.
311 * So add a dependency to the initial frame pointer calculation to
312 * avoid that situation.
314 if (get_irg_start_block(irg) == block) {
315 add_irn_dep(load, get_irg_frame(irg));
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
324 if (get_irg_start_block(irg) == block) {
325 add_irn_dep(cnst, get_irg_frame(irg));
328 set_ia32_Const_attr(cnst, node);
329 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
334 return new_r_Bad(irg);
338 * Transforms a SymConst.
340 static ir_node *gen_SymConst(ir_node *node) {
341 ir_graph *irg = current_ir_graph;
342 ir_node *block = be_transform_node(get_nodes_block(node));
343 dbg_info *dbgi = get_irn_dbg_info(node);
344 ir_mode *mode = get_irn_mode(node);
347 if (mode_is_float(mode)) {
349 if (USE_SSE2(env_cg))
350 cnst = new_rd_ia32_xConst(dbgi, irg, block);
352 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
353 //set_ia32_ls_mode(cnst, mode);
354 set_ia32_ls_mode(cnst, mode_E);
356 cnst = new_rd_ia32_Const(dbgi, irg, block);
359 /* Const Nodes before the initial IncSP are a bad idea, because
360 * they could be spilled and we have no SP ready at that point yet
362 if (get_irg_start_block(irg) == block) {
363 add_irn_dep(cnst, get_irg_frame(irg));
366 set_ia32_Const_attr(cnst, node);
367 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 * SSE convert of an integer node into a floating point node.
376 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
377 ir_graph *irg, ir_node *block,
378 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
380 ir_node *noreg = ia32_new_NoReg_gp(cg);
381 ir_node *nomem = new_rd_NoMem(irg);
382 ir_node *old_pred = get_Cmp_left(old_node);
383 ir_mode *in_mode = get_irn_mode(old_pred);
384 int in_bits = get_mode_size_bits(in_mode);
385 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
387 set_ia32_ls_mode(conv, tgt_mode);
389 set_ia32_am_support(conv, ia32_am_Source);
391 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 * SSE convert of an float node into a double node.
399 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
400 ir_graph *irg, ir_node *block,
401 ir_node *in, ir_node *old_node)
403 ir_node *noreg = ia32_new_NoReg_gp(cg);
404 ir_node *nomem = new_rd_NoMem(irg);
405 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
407 set_ia32_am_support(conv, ia32_am_Source);
408 set_ia32_ls_mode(conv, mode_xmm);
409 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
415 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
416 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
417 static const struct {
419 const char *ent_name;
420 const char *cnst_str;
421 } names [ia32_known_const_max] = {
422 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
423 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
424 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
425 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
427 static ir_entity *ent_cache[ia32_known_const_max];
429 const char *tp_name, *ent_name, *cnst_str;
437 ent_name = names[kct].ent_name;
438 if (! ent_cache[kct]) {
439 tp_name = names[kct].tp_name;
440 cnst_str = names[kct].cnst_str;
442 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
444 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
445 tp = new_type_primitive(new_id_from_str(tp_name), mode);
446 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
448 set_entity_ld_ident(ent, get_entity_ident(ent));
449 set_entity_visibility(ent, visibility_local);
450 set_entity_variability(ent, variability_constant);
451 set_entity_allocation(ent, allocation_static);
453 /* we create a new entity here: It's initialization must resist on the
455 rem = current_ir_graph;
456 current_ir_graph = get_const_code_irg();
457 cnst = new_Const(mode, tv);
458 current_ir_graph = rem;
460 set_atomic_ent_value(ent, cnst);
462 /* cache the entry */
463 ent_cache[kct] = ent;
466 return ent_cache[kct];
471 * Prints the old node name on cg obst and returns a pointer to it.
473 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
474 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
476 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
477 obstack_1grow(isa->name_obst, 0);
478 return obstack_finish(isa->name_obst);
482 /* determine if one operator is an Imm */
483 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
485 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
487 return is_ia32_Cnst(op2) ? op2 : NULL;
491 /* determine if one operator is not an Imm */
492 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
493 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
496 static void fold_immediate(ir_node *node, int in1, int in2) {
500 if (!(env_cg->opt & IA32_OPT_IMMOPS))
503 left = get_irn_n(node, in1);
504 right = get_irn_n(node, in2);
505 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
506 /* we can only set right operand to immediate */
507 if(!is_ia32_commutative(node))
509 /* exchange left/right */
510 set_irn_n(node, in1, right);
511 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
512 copy_ia32_Immop_attr(node, left);
513 } else if(is_ia32_Cnst(right)) {
514 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
515 copy_ia32_Immop_attr(node, right);
520 clear_ia32_commutative(node);
521 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
525 * Construct a standard binary operation, set AM and immediate if required.
527 * @param op1 The first operand
528 * @param op2 The second operand
529 * @param func The node constructor function
530 * @return The constructed ia32 node.
532 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
533 construct_binop_func *func, int commutative)
535 ir_node *block = be_transform_node(get_nodes_block(node));
536 ir_node *new_op1 = NULL;
537 ir_node *new_op2 = NULL;
538 ir_node *new_node = NULL;
539 ir_graph *irg = current_ir_graph;
540 dbg_info *dbgi = get_irn_dbg_info(node);
541 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
542 ir_node *nomem = new_NoMem();
545 new_op2 = try_create_Immediate(op1, 0);
546 if(new_op2 != NULL) {
547 new_op1 = be_transform_node(op2);
552 if(new_op2 == NULL) {
553 new_op2 = try_create_Immediate(op2, 0);
554 if(new_op2 != NULL) {
555 new_op1 = be_transform_node(op1);
560 if(new_op2 == NULL) {
561 new_op1 = be_transform_node(op1);
562 new_op2 = be_transform_node(op2);
565 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
566 if (func == new_rd_ia32_IMul) {
567 set_ia32_am_support(new_node, ia32_am_Source);
569 set_ia32_am_support(new_node, ia32_am_Full);
572 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
574 set_ia32_commutative(new_node);
581 * Construct a standard binary operation, set AM and immediate if required.
583 * @param op1 The first operand
584 * @param op2 The second operand
585 * @param func The node constructor function
586 * @return The constructed ia32 node.
588 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
589 construct_binop_func *func)
591 ir_node *block = be_transform_node(get_nodes_block(node));
592 ir_node *new_op1 = be_transform_node(op1);
593 ir_node *new_op2 = be_transform_node(op2);
594 ir_node *new_node = NULL;
595 dbg_info *dbgi = get_irn_dbg_info(node);
596 ir_graph *irg = current_ir_graph;
597 ir_mode *mode = get_irn_mode(node);
598 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
599 ir_node *nomem = new_NoMem();
601 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
602 set_ia32_am_support(new_node, ia32_am_Source);
603 if (is_op_commutative(get_irn_op(node))) {
604 set_ia32_commutative(new_node);
606 if (USE_SSE2(env_cg)) {
607 set_ia32_ls_mode(new_node, mode);
610 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
617 * Construct a shift/rotate binary operation, sets AM and immediate if required.
619 * @param op1 The first operand
620 * @param op2 The second operand
621 * @param func The node constructor function
622 * @return The constructed ia32 node.
624 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
625 construct_binop_func *func)
627 ir_node *block = be_transform_node(get_nodes_block(node));
628 ir_node *new_op1 = be_transform_node(op1);
629 ir_node *new_op2 = be_transform_node(op2);
630 ir_node *new_op = NULL;
631 dbg_info *dbgi = get_irn_dbg_info(node);
632 ir_graph *irg = current_ir_graph;
633 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
634 ir_node *nomem = new_NoMem();
639 assert(! mode_is_float(get_irn_mode(node))
640 && "Shift/Rotate with float not supported");
642 /* Check if immediate optimization is on and */
643 /* if it's an operation with immediate. */
644 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
645 expr_op = get_expr_op(new_op1, new_op2);
647 assert((expr_op || imm_op) && "invalid operands");
650 /* We have two consts here: not yet supported */
654 /* Limit imm_op within range imm8 */
656 tv = get_ia32_Immop_tarval(imm_op);
659 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
660 set_ia32_Immop_tarval(imm_op, tv);
667 /* integer operations */
669 /* This is shift/rot with const */
670 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
672 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
673 copy_ia32_Immop_attr(new_op, imm_op);
675 /* This is a normal shift/rot */
676 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
677 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
681 set_ia32_am_support(new_op, ia32_am_Dest);
683 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
685 set_ia32_emit_cl(new_op);
692 * Construct a standard unary operation, set AM and immediate if required.
694 * @param op The operand
695 * @param func The node constructor function
696 * @return The constructed ia32 node.
698 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
700 ir_node *block = be_transform_node(get_nodes_block(node));
701 ir_node *new_op = be_transform_node(op);
702 ir_node *new_node = NULL;
703 ir_graph *irg = current_ir_graph;
704 dbg_info *dbgi = get_irn_dbg_info(node);
705 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
706 ir_node *nomem = new_NoMem();
708 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
709 DB((dbg, LEVEL_1, "INT unop ..."));
710 set_ia32_am_support(new_node, ia32_am_Dest);
712 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
718 * Creates an ia32 Add.
720 * @return the created ia32 Add node
722 static ir_node *gen_Add(ir_node *node) {
723 ir_node *block = be_transform_node(get_nodes_block(node));
724 ir_node *op1 = get_Add_left(node);
725 ir_node *new_op1 = be_transform_node(op1);
726 ir_node *op2 = get_Add_right(node);
727 ir_node *new_op2 = be_transform_node(op2);
728 ir_node *new_op = NULL;
729 ir_graph *irg = current_ir_graph;
730 dbg_info *dbgi = get_irn_dbg_info(node);
731 ir_mode *mode = get_irn_mode(node);
732 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
733 ir_node *nomem = new_NoMem();
734 ir_node *expr_op, *imm_op;
736 /* Check if immediate optimization is on and */
737 /* if it's an operation with immediate. */
738 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
739 expr_op = get_expr_op(new_op1, new_op2);
741 assert((expr_op || imm_op) && "invalid operands");
743 if (mode_is_float(mode)) {
745 if (USE_SSE2(env_cg))
746 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
748 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
753 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
754 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
756 /* No expr_op means, that we have two const - one symconst and */
757 /* one tarval or another symconst - because this case is not */
758 /* covered by constant folding */
759 /* We need to check for: */
760 /* 1) symconst + const -> becomes a LEA */
761 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
762 /* linker doesn't support two symconsts */
764 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
765 /* this is the 2nd case */
766 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
767 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
768 set_ia32_am_flavour(new_op, ia32_am_B);
769 set_ia32_am_support(new_op, ia32_am_Source);
770 set_ia32_op_type(new_op, ia32_AddrModeS);
772 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
773 } else if (tp1 == ia32_ImmSymConst) {
774 tarval *tv = get_ia32_Immop_tarval(new_op2);
775 long offs = get_tarval_long(tv);
777 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
778 add_irn_dep(new_op, get_irg_frame(irg));
779 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
781 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
782 add_ia32_am_offs_int(new_op, offs);
783 set_ia32_am_flavour(new_op, ia32_am_OB);
784 set_ia32_am_support(new_op, ia32_am_Source);
785 set_ia32_op_type(new_op, ia32_AddrModeS);
786 } else if (tp2 == ia32_ImmSymConst) {
787 tarval *tv = get_ia32_Immop_tarval(new_op1);
788 long offs = get_tarval_long(tv);
790 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
791 add_irn_dep(new_op, get_irg_frame(irg));
792 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
794 add_ia32_am_offs_int(new_op, offs);
795 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
796 set_ia32_am_flavour(new_op, ia32_am_OB);
797 set_ia32_am_support(new_op, ia32_am_Source);
798 set_ia32_op_type(new_op, ia32_AddrModeS);
800 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
801 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
802 tarval *restv = tarval_add(tv1, tv2);
804 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
806 new_op = new_rd_ia32_Const(dbgi, irg, block);
807 set_ia32_Const_tarval(new_op, restv);
808 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
811 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
814 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
815 tarval_classification_t class_tv, class_negtv;
816 tarval *tv = get_ia32_Immop_tarval(imm_op);
818 /* optimize tarvals */
819 class_tv = classify_tarval(tv);
820 class_negtv = classify_tarval(tarval_neg(tv));
822 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
823 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
824 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
825 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
827 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
828 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
829 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
830 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
836 /* This is a normal add */
837 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
840 set_ia32_am_support(new_op, ia32_am_Full);
841 set_ia32_commutative(new_op);
843 fold_immediate(new_op, 2, 3);
845 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
851 static ir_node *create_ia32_Mul(ir_node *node) {
852 ir_graph *irg = current_ir_graph;
853 dbg_info *dbgi = get_irn_dbg_info(node);
854 ir_node *block = be_transform_node(get_nodes_block(node));
855 ir_node *op1 = get_Mul_left(node);
856 ir_node *op2 = get_Mul_right(node);
857 ir_node *new_op1 = be_transform_node(op1);
858 ir_node *new_op2 = be_transform_node(op2);
859 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
860 ir_node *proj_EAX, *proj_EDX, *res;
863 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
864 set_ia32_commutative(res);
865 set_ia32_am_support(res, ia32_am_Source);
867 /* imediates are not supported, so no fold_immediate */
868 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
869 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
873 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
881 * Creates an ia32 Mul.
883 * @return the created ia32 Mul node
885 static ir_node *gen_Mul(ir_node *node) {
886 ir_node *op1 = get_Mul_left(node);
887 ir_node *op2 = get_Mul_right(node);
888 ir_mode *mode = get_irn_mode(node);
890 if (mode_is_float(mode)) {
892 if (USE_SSE2(env_cg))
893 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
895 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
899 for the lower 32bit of the result it doesn't matter whether we use
900 signed or unsigned multiplication so we use IMul as it has fewer
903 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
907 * Creates an ia32 Mulh.
908 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
909 * this result while Mul returns the lower 32 bit.
911 * @return the created ia32 Mulh node
913 static ir_node *gen_Mulh(ir_node *node) {
914 ir_node *block = be_transform_node(get_nodes_block(node));
915 ir_node *op1 = get_irn_n(node, 0);
916 ir_node *new_op1 = be_transform_node(op1);
917 ir_node *op2 = get_irn_n(node, 1);
918 ir_node *new_op2 = be_transform_node(op2);
919 ir_graph *irg = current_ir_graph;
920 dbg_info *dbgi = get_irn_dbg_info(node);
921 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
922 ir_mode *mode = get_irn_mode(node);
923 ir_node *proj_EAX, *proj_EDX, *res;
926 assert(!mode_is_float(mode) && "Mulh with float not supported");
927 if (mode_is_signed(mode)) {
928 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
930 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
933 set_ia32_commutative(res);
934 set_ia32_am_support(res, ia32_am_Source);
936 set_ia32_am_support(res, ia32_am_Source);
938 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
939 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
943 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
951 * Creates an ia32 And.
953 * @return The created ia32 And node
955 static ir_node *gen_And(ir_node *node) {
956 ir_node *op1 = get_And_left(node);
957 ir_node *op2 = get_And_right(node);
959 assert (! mode_is_float(get_irn_mode(node)));
960 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
966 * Creates an ia32 Or.
968 * @return The created ia32 Or node
970 static ir_node *gen_Or(ir_node *node) {
971 ir_node *op1 = get_Or_left(node);
972 ir_node *op2 = get_Or_right(node);
974 assert (! mode_is_float(get_irn_mode(node)));
975 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
981 * Creates an ia32 Eor.
983 * @return The created ia32 Eor node
985 static ir_node *gen_Eor(ir_node *node) {
986 ir_node *op1 = get_Eor_left(node);
987 ir_node *op2 = get_Eor_right(node);
989 assert(! mode_is_float(get_irn_mode(node)));
990 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
996 * Creates an ia32 Max.
998 * @return the created ia32 Max node
1000 static ir_node *gen_Max(ir_node *node) {
1001 ir_node *block = be_transform_node(get_nodes_block(node));
1002 ir_node *op1 = get_irn_n(node, 0);
1003 ir_node *new_op1 = be_transform_node(op1);
1004 ir_node *op2 = get_irn_n(node, 1);
1005 ir_node *new_op2 = be_transform_node(op2);
1006 ir_graph *irg = current_ir_graph;
1007 ir_mode *mode = get_irn_mode(node);
1008 dbg_info *dbgi = get_irn_dbg_info(node);
1009 ir_mode *op_mode = get_irn_mode(op1);
1012 assert(get_mode_size_bits(mode) == 32);
1014 if (mode_is_float(mode)) {
1016 if (USE_SSE2(env_cg)) {
1017 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1019 panic("Can't create Max node");
1022 long pnc = pn_Cmp_Gt;
1023 if (! mode_is_signed(op_mode)) {
1024 pnc |= ia32_pn_Cmp_Unsigned;
1026 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1027 new_op1, new_op2, pnc);
1029 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1035 * Creates an ia32 Min.
1037 * @return the created ia32 Min node
1039 static ir_node *gen_Min(ir_node *node) {
1040 ir_node *block = be_transform_node(get_nodes_block(node));
1041 ir_node *op1 = get_irn_n(node, 0);
1042 ir_node *new_op1 = be_transform_node(op1);
1043 ir_node *op2 = get_irn_n(node, 1);
1044 ir_node *new_op2 = be_transform_node(op2);
1045 ir_graph *irg = current_ir_graph;
1046 ir_mode *mode = get_irn_mode(node);
1047 dbg_info *dbgi = get_irn_dbg_info(node);
1048 ir_mode *op_mode = get_irn_mode(op1);
1051 assert(get_mode_size_bits(mode) == 32);
1053 if (mode_is_float(mode)) {
1055 if (USE_SSE2(env_cg)) {
1056 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1058 panic("can't create Min node");
1061 long pnc = pn_Cmp_Lt;
1062 if (! mode_is_signed(op_mode)) {
1063 pnc |= ia32_pn_Cmp_Unsigned;
1065 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1066 new_op1, new_op2, pnc);
1068 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1075 * Creates an ia32 Sub.
1077 * @return The created ia32 Sub node
1079 static ir_node *gen_Sub(ir_node *node) {
1080 ir_node *block = be_transform_node(get_nodes_block(node));
1081 ir_node *op1 = get_Sub_left(node);
1082 ir_node *new_op1 = be_transform_node(op1);
1083 ir_node *op2 = get_Sub_right(node);
1084 ir_node *new_op2 = be_transform_node(op2);
1085 ir_node *new_op = NULL;
1086 ir_graph *irg = current_ir_graph;
1087 dbg_info *dbgi = get_irn_dbg_info(node);
1088 ir_mode *mode = get_irn_mode(node);
1089 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1090 ir_node *nomem = new_NoMem();
1091 ir_node *expr_op, *imm_op;
1093 /* Check if immediate optimization is on and */
1094 /* if it's an operation with immediate. */
1095 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1096 expr_op = get_expr_op(new_op1, new_op2);
1098 assert((expr_op || imm_op) && "invalid operands");
1100 if (mode_is_float(mode)) {
1102 if (USE_SSE2(env_cg))
1103 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1105 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1110 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1111 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1113 /* No expr_op means, that we have two const - one symconst and */
1114 /* one tarval or another symconst - because this case is not */
1115 /* covered by constant folding */
1116 /* We need to check for: */
1117 /* 1) symconst - const -> becomes a LEA */
1118 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1119 /* linker doesn't support two symconsts */
1120 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1121 /* this is the 2nd case */
1122 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1123 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1124 set_ia32_am_sc_sign(new_op);
1125 set_ia32_am_flavour(new_op, ia32_am_B);
1127 DBG_OPT_LEA3(op1, op2, node, new_op);
1128 } else if (tp1 == ia32_ImmSymConst) {
1129 tarval *tv = get_ia32_Immop_tarval(new_op2);
1130 long offs = get_tarval_long(tv);
1132 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1133 add_irn_dep(new_op, get_irg_frame(irg));
1134 DBG_OPT_LEA3(op1, op2, node, new_op);
1136 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1137 add_ia32_am_offs_int(new_op, -offs);
1138 set_ia32_am_flavour(new_op, ia32_am_OB);
1139 set_ia32_am_support(new_op, ia32_am_Source);
1140 set_ia32_op_type(new_op, ia32_AddrModeS);
1141 } else if (tp2 == ia32_ImmSymConst) {
1142 tarval *tv = get_ia32_Immop_tarval(new_op1);
1143 long offs = get_tarval_long(tv);
1145 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1146 add_irn_dep(new_op, get_irg_frame(irg));
1147 DBG_OPT_LEA3(op1, op2, node, new_op);
1149 add_ia32_am_offs_int(new_op, offs);
1150 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1151 set_ia32_am_sc_sign(new_op);
1152 set_ia32_am_flavour(new_op, ia32_am_OB);
1153 set_ia32_am_support(new_op, ia32_am_Source);
1154 set_ia32_op_type(new_op, ia32_AddrModeS);
1156 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1157 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1158 tarval *restv = tarval_sub(tv1, tv2);
1160 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1162 new_op = new_rd_ia32_Const(dbgi, irg, block);
1163 set_ia32_Const_tarval(new_op, restv);
1164 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1167 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1169 } else if (imm_op) {
1170 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1171 tarval_classification_t class_tv, class_negtv;
1172 tarval *tv = get_ia32_Immop_tarval(imm_op);
1174 /* optimize tarvals */
1175 class_tv = classify_tarval(tv);
1176 class_negtv = classify_tarval(tarval_neg(tv));
1178 if (class_tv == TV_CLASSIFY_ONE) {
1179 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1180 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1181 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1183 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1184 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1185 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1186 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1192 /* This is a normal sub */
1193 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1195 /* set AM support */
1196 set_ia32_am_support(new_op, ia32_am_Full);
1198 fold_immediate(new_op, 2, 3);
1200 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1208 * Generates an ia32 DivMod with additional infrastructure for the
1209 * register allocator if needed.
1211 * @param dividend -no comment- :)
1212 * @param divisor -no comment- :)
1213 * @param dm_flav flavour_Div/Mod/DivMod
1214 * @return The created ia32 DivMod node
1216 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1217 ir_node *divisor, ia32_op_flavour_t dm_flav)
1219 ir_node *block = be_transform_node(get_nodes_block(node));
1220 ir_node *new_dividend = be_transform_node(dividend);
1221 ir_node *new_divisor = be_transform_node(divisor);
1222 ir_graph *irg = current_ir_graph;
1223 dbg_info *dbgi = get_irn_dbg_info(node);
1224 ir_mode *mode = get_irn_mode(node);
1225 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1226 ir_node *res, *proj_div, *proj_mod;
1227 ir_node *edx_node, *cltd;
1228 ir_node *in_keep[2];
1229 ir_node *mem, *new_mem;
1230 ir_node *projs[pn_DivMod_max];
1233 ia32_collect_Projs(node, projs, pn_DivMod_max);
1235 proj_div = proj_mod = NULL;
1239 mem = get_Div_mem(node);
1240 mode = get_Div_resmode(node);
1241 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1242 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1245 mem = get_Mod_mem(node);
1246 mode = get_Mod_resmode(node);
1247 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1248 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1250 case flavour_DivMod:
1251 mem = get_DivMod_mem(node);
1252 mode = get_DivMod_resmode(node);
1253 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1254 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1255 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1258 panic("invalid divmod flavour!");
1260 new_mem = be_transform_node(mem);
1262 if (mode_is_signed(mode)) {
1263 /* in signed mode, we need to sign extend the dividend */
1264 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1265 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1266 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1268 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1269 add_irn_dep(edx_node, be_abi_get_start_barrier(env_cg->birg->abi));
1270 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1273 if (mode_is_signed(mode)) {
1274 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1276 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1279 set_ia32_exc_label(res, has_exc);
1281 /* Matze: code can't handle this at the moment... */
1283 /* set AM support */
1284 set_ia32_am_support(res, ia32_am_Source);
1287 /* check, which Proj-Keep, we need to add */
1289 if (proj_div == NULL) {
1290 /* We have only mod result: add div res Proj-Keep */
1291 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1294 if (proj_mod == NULL) {
1295 /* We have only div result: add mod res Proj-Keep */
1296 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1300 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1302 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1309 * Wrapper for generate_DivMod. Sets flavour_Mod.
1312 static ir_node *gen_Mod(ir_node *node) {
1313 return generate_DivMod(node, get_Mod_left(node),
1314 get_Mod_right(node), flavour_Mod);
1318 * Wrapper for generate_DivMod. Sets flavour_Div.
1321 static ir_node *gen_Div(ir_node *node) {
1322 return generate_DivMod(node, get_Div_left(node),
1323 get_Div_right(node), flavour_Div);
1327 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1329 static ir_node *gen_DivMod(ir_node *node) {
1330 return generate_DivMod(node, get_DivMod_left(node),
1331 get_DivMod_right(node), flavour_DivMod);
1337 * Creates an ia32 floating Div.
1339 * @return The created ia32 xDiv node
1341 static ir_node *gen_Quot(ir_node *node) {
1342 ir_node *block = be_transform_node(get_nodes_block(node));
1343 ir_node *op1 = get_Quot_left(node);
1344 ir_node *new_op1 = be_transform_node(op1);
1345 ir_node *op2 = get_Quot_right(node);
1346 ir_node *new_op2 = be_transform_node(op2);
1347 ir_graph *irg = current_ir_graph;
1348 dbg_info *dbgi = get_irn_dbg_info(node);
1349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1350 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1354 if (USE_SSE2(env_cg)) {
1355 ir_mode *mode = get_irn_mode(op1);
1356 if (is_ia32_xConst(new_op2)) {
1357 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1358 set_ia32_am_support(new_op, ia32_am_None);
1359 copy_ia32_Immop_attr(new_op, new_op2);
1361 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1362 // Matze: disabled for now, spillslot coalescer fails
1363 //set_ia32_am_support(new_op, ia32_am_Source);
1365 set_ia32_ls_mode(new_op, mode);
1367 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1368 // Matze: disabled for now (spillslot coalescer fails)
1369 //set_ia32_am_support(new_op, ia32_am_Source);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1377 * Creates an ia32 Shl.
1379 * @return The created ia32 Shl node
1381 static ir_node *gen_Shl(ir_node *node) {
1382 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1389 * Creates an ia32 Shr.
1391 * @return The created ia32 Shr node
1393 static ir_node *gen_Shr(ir_node *node) {
1394 return gen_shift_binop(node, get_Shr_left(node),
1395 get_Shr_right(node), new_rd_ia32_Shr);
1401 * Creates an ia32 Sar.
1403 * @return The created ia32 Shrs node
1405 static ir_node *gen_Shrs(ir_node *node) {
1406 return gen_shift_binop(node, get_Shrs_left(node),
1407 get_Shrs_right(node), new_rd_ia32_Sar);
1413 * Creates an ia32 RotL.
1415 * @param op1 The first operator
1416 * @param op2 The second operator
1417 * @return The created ia32 RotL node
1419 static ir_node *gen_RotL(ir_node *node,
1420 ir_node *op1, ir_node *op2) {
1421 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1427 * Creates an ia32 RotR.
1428 * NOTE: There is no RotR with immediate because this would always be a RotL
1429 * "imm-mode_size_bits" which can be pre-calculated.
1431 * @param op1 The first operator
1432 * @param op2 The second operator
1433 * @return The created ia32 RotR node
1435 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1437 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1443 * Creates an ia32 RotR or RotL (depending on the found pattern).
1445 * @return The created ia32 RotL or RotR node
1447 static ir_node *gen_Rot(ir_node *node) {
1448 ir_node *rotate = NULL;
1449 ir_node *op1 = get_Rot_left(node);
1450 ir_node *op2 = get_Rot_right(node);
1452 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1453 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1454 that means we can create a RotR instead of an Add and a RotL */
1456 if (get_irn_op(op2) == op_Add) {
1458 ir_node *left = get_Add_left(add);
1459 ir_node *right = get_Add_right(add);
1460 if (is_Const(right)) {
1461 tarval *tv = get_Const_tarval(right);
1462 ir_mode *mode = get_irn_mode(node);
1463 long bits = get_mode_size_bits(mode);
1465 if (get_irn_op(left) == op_Minus &&
1466 tarval_is_long(tv) &&
1467 get_tarval_long(tv) == bits)
1469 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1470 rotate = gen_RotR(node, op1, get_Minus_op(left));
1475 if (rotate == NULL) {
1476 rotate = gen_RotL(node, op1, op2);
1485 * Transforms a Minus node.
1487 * @param op The Minus operand
1488 * @return The created ia32 Minus node
1490 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1491 ir_node *block = be_transform_node(get_nodes_block(node));
1492 ir_graph *irg = current_ir_graph;
1493 dbg_info *dbgi = get_irn_dbg_info(node);
1494 ir_mode *mode = get_irn_mode(node);
1499 if (mode_is_float(mode)) {
1500 ir_node *new_op = be_transform_node(op);
1502 if (USE_SSE2(env_cg)) {
1503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1504 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1505 ir_node *nomem = new_rd_NoMem(irg);
1507 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1509 size = get_mode_size_bits(mode);
1510 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1512 set_ia32_am_sc(res, ent);
1513 set_ia32_op_type(res, ia32_AddrModeS);
1514 set_ia32_ls_mode(res, mode);
1516 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1519 res = gen_unop(node, op, new_rd_ia32_Neg);
1522 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1528 * Transforms a Minus node.
1530 * @return The created ia32 Minus node
1532 static ir_node *gen_Minus(ir_node *node) {
1533 return gen_Minus_ex(node, get_Minus_op(node));
1538 * Transforms a Not node.
1540 * @return The created ia32 Not node
1542 static ir_node *gen_Not(ir_node *node) {
1543 ir_node *op = get_Not_op(node);
1545 assert (! mode_is_float(get_irn_mode(node)));
1546 return gen_unop(node, op, new_rd_ia32_Not);
1552 * Transforms an Abs node.
1554 * @return The created ia32 Abs node
1556 static ir_node *gen_Abs(ir_node *node) {
1557 ir_node *block = be_transform_node(get_nodes_block(node));
1558 ir_node *op = get_Abs_op(node);
1559 ir_node *new_op = be_transform_node(op);
1560 ir_graph *irg = current_ir_graph;
1561 dbg_info *dbgi = get_irn_dbg_info(node);
1562 ir_mode *mode = get_irn_mode(node);
1563 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1564 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1565 ir_node *nomem = new_NoMem();
1566 ir_node *res, *p_eax, *p_edx;
1570 if (mode_is_float(mode)) {
1572 if (USE_SSE2(env_cg)) {
1573 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1575 size = get_mode_size_bits(mode);
1576 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1578 set_ia32_am_sc(res, ent);
1580 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1582 set_ia32_op_type(res, ia32_AddrModeS);
1583 set_ia32_ls_mode(res, mode);
1586 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1591 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1592 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1594 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1595 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1597 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1600 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1601 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1610 * Transforms a Load.
1612 * @return the created ia32 Load node
1614 static ir_node *gen_Load(ir_node *node) {
1615 ir_node *block = be_transform_node(get_nodes_block(node));
1616 ir_node *ptr = get_Load_ptr(node);
1617 ir_node *new_ptr = be_transform_node(ptr);
1618 ir_node *mem = get_Load_mem(node);
1619 ir_node *new_mem = be_transform_node(mem);
1620 ir_graph *irg = current_ir_graph;
1621 dbg_info *dbgi = get_irn_dbg_info(node);
1622 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1623 ir_mode *mode = get_Load_mode(node);
1625 ir_node *lptr = new_ptr;
1628 ir_node *projs[pn_Load_max];
1629 ia32_am_flavour_t am_flav = ia32_am_B;
1631 ia32_collect_Projs(node, projs, pn_Load_max);
1633 /* address might be a constant (symconst or absolute address) */
1634 if (is_ia32_Const(new_ptr)) {
1639 if (mode_is_float(mode)) {
1641 if (USE_SSE2(env_cg)) {
1642 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1643 res_mode = mode_xmm;
1645 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1646 res_mode = mode_vfp;
1649 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1654 check for special case: the loaded value might not be used
1656 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1657 /* add a result proj and a Keep to produce a pseudo use */
1658 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1660 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1663 /* base is a constant address */
1665 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1666 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1667 am_flav = ia32_am_N;
1669 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1670 long offs = get_tarval_long(tv);
1672 add_ia32_am_offs_int(new_op, offs);
1673 am_flav = ia32_am_O;
1677 set_irn_pinned(new_op, get_irn_pinned(node));
1678 set_ia32_am_support(new_op, ia32_am_Source);
1679 set_ia32_op_type(new_op, ia32_AddrModeS);
1680 set_ia32_am_flavour(new_op, am_flav);
1681 set_ia32_ls_mode(new_op, mode);
1683 /* make sure we are scheduled behind the initial IncSP/Barrier
1684 * to avoid spills being placed before it
1686 if (block == get_irg_start_block(irg)) {
1687 add_irn_dep(new_op, get_irg_frame(irg));
1690 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1691 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1699 * Transforms a Store.
1701 * @return the created ia32 Store node
1703 static ir_node *gen_Store(ir_node *node) {
1704 ir_node *block = be_transform_node(get_nodes_block(node));
1705 ir_node *ptr = get_Store_ptr(node);
1706 ir_node *new_ptr = be_transform_node(ptr);
1707 ir_node *val = get_Store_value(node);
1708 ir_node *new_val = be_transform_node(val);
1709 ir_node *mem = get_Store_mem(node);
1710 ir_node *new_mem = be_transform_node(mem);
1711 ir_graph *irg = current_ir_graph;
1712 dbg_info *dbgi = get_irn_dbg_info(node);
1713 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1714 ir_node *sptr = new_ptr;
1715 ir_mode *mode = get_irn_mode(val);
1716 ir_node *sval = new_val;
1719 ia32_am_flavour_t am_flav = ia32_am_B;
1721 if (is_ia32_Const(new_val)) {
1722 assert(!mode_is_float(mode));
1726 /* address might be a constant (symconst or absolute address) */
1727 if (is_ia32_Const(new_ptr)) {
1732 if (mode_is_float(mode)) {
1734 if (USE_SSE2(env_cg)) {
1735 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1737 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem, mode);
1739 } else if (get_mode_size_bits(mode) == 8) {
1740 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1742 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1745 /* stored const is an immediate value */
1746 if (is_ia32_Const(new_val)) {
1747 assert(!mode_is_float(mode));
1748 copy_ia32_Immop_attr(new_op, new_val);
1751 /* base is an constant address */
1753 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1754 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1755 am_flav = ia32_am_N;
1757 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1758 long offs = get_tarval_long(tv);
1760 add_ia32_am_offs_int(new_op, offs);
1761 am_flav = ia32_am_O;
1765 set_irn_pinned(new_op, get_irn_pinned(node));
1766 set_ia32_am_support(new_op, ia32_am_Dest);
1767 set_ia32_op_type(new_op, ia32_AddrModeD);
1768 set_ia32_am_flavour(new_op, am_flav);
1769 set_ia32_ls_mode(new_op, mode);
1771 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1772 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1780 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1782 * @return The transformed node.
1784 static ir_node *gen_Cond(ir_node *node) {
1785 ir_node *block = be_transform_node(get_nodes_block(node));
1786 ir_graph *irg = current_ir_graph;
1787 dbg_info *dbgi = get_irn_dbg_info(node);
1788 ir_node *sel = get_Cond_selector(node);
1789 ir_mode *sel_mode = get_irn_mode(sel);
1790 ir_node *res = NULL;
1791 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1792 ir_node *cnst, *expr;
1794 if (is_Proj(sel) && sel_mode == mode_b) {
1795 ir_node *pred = get_Proj_pred(sel);
1796 ir_node *cmp_a = get_Cmp_left(pred);
1797 ir_node *new_cmp_a = be_transform_node(cmp_a);
1798 ir_node *cmp_b = get_Cmp_right(pred);
1799 ir_node *new_cmp_b = be_transform_node(cmp_b);
1800 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1801 ir_node *nomem = new_NoMem();
1803 int pnc = get_Proj_proj(sel);
1804 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1805 pnc |= ia32_pn_Cmp_Unsigned;
1808 /* check if we can use a CondJmp with immediate */
1809 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1810 expr = get_expr_op(new_cmp_a, new_cmp_b);
1812 if (cnst != NULL && expr != NULL) {
1813 /* immop has to be the right operand, we might need to flip pnc */
1814 if(cnst != new_cmp_b) {
1815 pnc = get_inversed_pnc(pnc);
1818 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1819 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1820 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1822 /* a Cmp A =/!= 0 */
1823 ir_node *op1 = expr;
1824 ir_node *op2 = expr;
1827 /* check, if expr is an only once used And operation */
1828 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1829 op1 = get_irn_n(expr, 2);
1830 op2 = get_irn_n(expr, 3);
1832 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1834 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1835 set_ia32_pncode(res, pnc);
1838 copy_ia32_Immop_attr(res, expr);
1841 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1846 if (mode_is_float(cmp_mode)) {
1848 if (USE_SSE2(env_cg)) {
1849 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1850 set_ia32_ls_mode(res, cmp_mode);
1856 assert(get_mode_size_bits(cmp_mode) == 32);
1857 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1859 copy_ia32_Immop_attr(res, cnst);
1862 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1864 if (mode_is_float(cmp_mode)) {
1866 if (USE_SSE2(env_cg)) {
1867 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1868 set_ia32_ls_mode(res, cmp_mode);
1871 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1873 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1877 assert(get_mode_size_bits(cmp_mode) == 32);
1878 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1879 set_ia32_commutative(res);
1883 set_ia32_pncode(res, pnc);
1884 // Matze: disabled for now, because the default collect_spills_walker
1885 // is not able to detect the mode of the spilled value
1886 // moreover, the lea optimize phase freely exchanges left/right
1887 // without updating the pnc
1888 //set_ia32_am_support(res, ia32_am_Source);
1891 /* determine the smallest switch case value */
1892 ir_node *new_sel = be_transform_node(sel);
1893 int switch_min = INT_MAX;
1894 const ir_edge_t *edge;
1896 foreach_out_edge(node, edge) {
1897 int pn = get_Proj_proj(get_edge_src_irn(edge));
1898 switch_min = pn < switch_min ? pn : switch_min;
1902 /* if smallest switch case is not 0 we need an additional sub */
1903 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1904 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1905 add_ia32_am_offs_int(res, -switch_min);
1906 set_ia32_am_flavour(res, ia32_am_OB);
1907 set_ia32_am_support(res, ia32_am_Source);
1908 set_ia32_op_type(res, ia32_AddrModeS);
1911 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1912 set_ia32_pncode(res, get_Cond_defaultProj(node));
1915 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1922 * Transforms a CopyB node.
1924 * @return The transformed node.
1926 static ir_node *gen_CopyB(ir_node *node) {
1927 ir_node *block = be_transform_node(get_nodes_block(node));
1928 ir_node *src = get_CopyB_src(node);
1929 ir_node *new_src = be_transform_node(src);
1930 ir_node *dst = get_CopyB_dst(node);
1931 ir_node *new_dst = be_transform_node(dst);
1932 ir_node *mem = get_CopyB_mem(node);
1933 ir_node *new_mem = be_transform_node(mem);
1934 ir_node *res = NULL;
1935 ir_graph *irg = current_ir_graph;
1936 dbg_info *dbgi = get_irn_dbg_info(node);
1937 int size = get_type_size_bytes(get_CopyB_type(node));
1938 ir_mode *dst_mode = get_irn_mode(dst);
1939 ir_mode *src_mode = get_irn_mode(src);
1943 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1944 /* then we need the size explicitly in ECX. */
1945 if (size >= 32 * 4) {
1946 rem = size & 0x3; /* size % 4 */
1949 res = new_rd_ia32_Const(dbgi, irg, block);
1950 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1953 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1954 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1956 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1957 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1958 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1959 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1960 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1963 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1964 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1966 /* ok: now attach Proj's because movsd will destroy esi and edi */
1967 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1968 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1969 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1972 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1978 ir_node *gen_be_Copy(ir_node *node)
1980 ir_node *result = be_duplicate_node(node);
1981 ir_mode *mode = get_irn_mode(result);
1983 if (mode_needs_gp_reg(mode)) {
1984 set_irn_mode(result, mode_Iu);
1993 * Transforms a Mux node into CMov.
1995 * @return The transformed node.
1997 static ir_node *gen_Mux(ir_node *node) {
1998 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1999 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
2001 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2007 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2008 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2009 ir_node *psi_default);
2012 * Transforms a Psi node into CMov.
2014 * @return The transformed node.
2016 static ir_node *gen_Psi(ir_node *node) {
2017 ir_node *block = be_transform_node(get_nodes_block(node));
2018 ir_node *psi_true = get_Psi_val(node, 0);
2019 ir_node *psi_default = get_Psi_default(node);
2020 ia32_code_gen_t *cg = env_cg;
2021 ir_graph *irg = current_ir_graph;
2022 dbg_info *dbgi = get_irn_dbg_info(node);
2023 ir_node *cond = get_Psi_cond(node, 0);
2024 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2025 ir_node *nomem = new_NoMem();
2027 ir_node *cmp, *cmp_a, *cmp_b;
2028 ir_node *new_cmp_a, *new_cmp_b;
2032 assert(get_Psi_n_conds(node) == 1);
2033 assert(get_irn_mode(cond) == mode_b);
2035 if(is_And(cond) || is_Or(cond)) {
2036 ir_node *new_cond = be_transform_node(cond);
2037 tarval *tv_zero = new_tarval_from_long(0, mode_Iu);
2038 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0,
2040 arch_set_irn_register(env_cg->arch_env, zero,
2041 &ia32_gp_regs[REG_GP_NOREG]);
2043 /* we have to compare the result against zero */
2044 new_cmp_a = new_cond;
2049 cmp = get_Proj_pred(cond);
2050 cmp_a = get_Cmp_left(cmp);
2051 cmp_b = get_Cmp_right(cmp);
2052 cmp_mode = get_irn_mode(cmp_a);
2053 pnc = get_Proj_proj(cond);
2055 new_cmp_b = try_create_Immediate(cmp_b, 0);
2056 if(new_cmp_b == NULL) {
2057 new_cmp_b = try_create_Immediate(cmp_a, 0);
2058 if(new_cmp_b != NULL) {
2059 pnc = get_inversed_pnc(pnc);
2060 new_cmp_a = be_transform_node(cmp_b);
2063 new_cmp_a = be_transform_node(cmp_a);
2065 if(new_cmp_b == NULL) {
2066 new_cmp_a = be_transform_node(cmp_a);
2067 new_cmp_b = be_transform_node(cmp_b);
2070 if (!mode_is_signed(cmp_mode)) {
2071 pnc |= ia32_pn_Cmp_Unsigned;
2075 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2076 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2077 new_cmp_a, new_cmp_b, nomem, pnc);
2078 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2079 pnc = get_negated_pnc(pnc, cmp_mode);
2080 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2081 new_cmp_a, new_cmp_b, nomem, pnc);
2083 ir_node *new_psi_true = be_transform_node(psi_true);
2084 ir_node *new_psi_default = be_transform_node(psi_default);
2085 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2086 new_psi_true, new_psi_default, pnc);
2088 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2094 * Following conversion rules apply:
2098 * 1) n bit -> m bit n > m (downscale)
2100 * 2) n bit -> m bit n == m (sign change)
2102 * 3) n bit -> m bit n < m (upscale)
2103 * a) source is signed: movsx
2104 * b) source is unsigned: and with lower bits sets
2108 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2112 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2116 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2117 * x87 is mode_E internally, conversions happen only at load and store
2118 * in non-strict semantic
2122 * Create a conversion from x87 state register to general purpose.
2124 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2125 ir_node *block = be_transform_node(get_nodes_block(node));
2126 ir_node *op = get_Conv_op(node);
2127 ir_node *new_op = be_transform_node(op);
2128 ia32_code_gen_t *cg = env_cg;
2129 ir_graph *irg = current_ir_graph;
2130 dbg_info *dbgi = get_irn_dbg_info(node);
2131 ir_node *noreg = ia32_new_NoReg_gp(cg);
2132 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2133 ir_node *fist, *load;
2136 fist = new_rd_ia32_vfist(dbgi, irg, block,
2137 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2139 set_irn_pinned(fist, op_pin_state_floats);
2140 set_ia32_use_frame(fist);
2141 set_ia32_am_support(fist, ia32_am_Dest);
2142 set_ia32_op_type(fist, ia32_AddrModeD);
2143 set_ia32_am_flavour(fist, ia32_am_B);
2144 set_ia32_ls_mode(fist, mode_Iu);
2145 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2148 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2150 set_irn_pinned(load, op_pin_state_floats);
2151 set_ia32_use_frame(load);
2152 set_ia32_am_support(load, ia32_am_Source);
2153 set_ia32_op_type(load, ia32_AddrModeS);
2154 set_ia32_am_flavour(load, ia32_am_B);
2155 set_ia32_ls_mode(load, mode_Iu);
2156 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2158 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2162 * Create a conversion from general purpose to x87 register
2164 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2165 ir_node *block = be_transform_node(get_nodes_block(node));
2166 ir_node *op = get_Conv_op(node);
2167 ir_node *new_op = be_transform_node(op);
2168 ir_graph *irg = current_ir_graph;
2169 dbg_info *dbgi = get_irn_dbg_info(node);
2170 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2171 ir_node *nomem = new_NoMem();
2172 ir_node *fild, *store;
2175 /* first convert to 32 bit if necessary */
2176 src_bits = get_mode_size_bits(src_mode);
2177 if (src_bits == 8) {
2178 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2179 set_ia32_am_support(new_op, ia32_am_Source);
2180 set_ia32_ls_mode(new_op, src_mode);
2181 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2182 } else if (src_bits < 32) {
2183 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2184 set_ia32_am_support(new_op, ia32_am_Source);
2185 set_ia32_ls_mode(new_op, src_mode);
2186 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2190 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2192 set_ia32_use_frame(store);
2193 set_ia32_am_support(store, ia32_am_Dest);
2194 set_ia32_op_type(store, ia32_AddrModeD);
2195 set_ia32_am_flavour(store, ia32_am_OB);
2196 set_ia32_ls_mode(store, mode_Iu);
2199 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2201 set_ia32_use_frame(fild);
2202 set_ia32_am_support(fild, ia32_am_Source);
2203 set_ia32_op_type(fild, ia32_AddrModeS);
2204 set_ia32_am_flavour(fild, ia32_am_OB);
2205 set_ia32_ls_mode(fild, mode_Iu);
2207 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2210 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2213 ir_node *block = get_nodes_block(node);
2214 ir_graph *irg = current_ir_graph;
2215 dbg_info *dbgi = get_irn_dbg_info(node);
2216 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2217 ir_node *nomem = new_NoMem();
2218 int src_bits = get_mode_size_bits(src_mode);
2219 int tgt_bits = get_mode_size_bits(tgt_mode);
2220 ir_node *frame = get_irg_frame(irg);
2221 ir_mode *smaller_mode;
2222 ir_node *store, *load;
2225 if(src_bits <= tgt_bits)
2226 smaller_mode = src_mode;
2228 smaller_mode = tgt_mode;
2230 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2232 set_ia32_use_frame(store);
2233 set_ia32_am_support(store, ia32_am_Dest);
2234 set_ia32_op_type(store, ia32_AddrModeD);
2235 set_ia32_am_flavour(store, ia32_am_OB);
2237 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2239 set_ia32_use_frame(load);
2240 set_ia32_am_support(load, ia32_am_Source);
2241 set_ia32_op_type(load, ia32_AddrModeS);
2242 set_ia32_am_flavour(load, ia32_am_OB);
2244 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2249 * Transforms a Conv node.
2251 * @return The created ia32 Conv node
2253 static ir_node *gen_Conv(ir_node *node) {
2254 ir_node *block = be_transform_node(get_nodes_block(node));
2255 ir_node *op = get_Conv_op(node);
2256 ir_node *new_op = be_transform_node(op);
2257 ir_graph *irg = current_ir_graph;
2258 dbg_info *dbgi = get_irn_dbg_info(node);
2259 ir_mode *src_mode = get_irn_mode(op);
2260 ir_mode *tgt_mode = get_irn_mode(node);
2261 int src_bits = get_mode_size_bits(src_mode);
2262 int tgt_bits = get_mode_size_bits(tgt_mode);
2263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2264 ir_node *nomem = new_rd_NoMem(irg);
2267 if (src_mode == tgt_mode) {
2268 if (get_Conv_strict(node)) {
2269 if (USE_SSE2(env_cg)) {
2270 /* when we are in SSE mode, we can kill all strict no-op conversion */
2274 /* this should be optimized already, but who knows... */
2275 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2276 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2281 if (mode_is_float(src_mode)) {
2282 /* we convert from float ... */
2283 if (mode_is_float(tgt_mode)) {
2284 if(src_mode == mode_E && tgt_mode == mode_D
2285 && !get_Conv_strict(node)) {
2286 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2291 if (USE_SSE2(env_cg)) {
2292 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2293 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2294 set_ia32_ls_mode(res, tgt_mode);
2296 // Matze: TODO what about strict convs?
2297 if(get_Conv_strict(node)) {
2298 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2299 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2302 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2307 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2308 if (USE_SSE2(env_cg)) {
2309 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2310 set_ia32_ls_mode(res, src_mode);
2312 return gen_x87_fp_to_gp(node);
2316 /* we convert from int ... */
2317 if (mode_is_float(tgt_mode)) {
2320 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2321 if (USE_SSE2(env_cg)) {
2322 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2323 set_ia32_ls_mode(res, tgt_mode);
2324 if(src_bits == 32) {
2325 set_ia32_am_support(res, ia32_am_Source);
2328 return gen_x87_gp_to_fp(node, src_mode);
2332 ir_mode *smaller_mode;
2335 if (src_bits == tgt_bits) {
2336 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2340 if (src_bits < tgt_bits) {
2341 smaller_mode = src_mode;
2342 smaller_bits = src_bits;
2344 smaller_mode = tgt_mode;
2345 smaller_bits = tgt_bits;
2348 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2349 if (smaller_bits == 8) {
2350 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2351 set_ia32_ls_mode(res, smaller_mode);
2353 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2354 set_ia32_ls_mode(res, smaller_mode);
2356 set_ia32_am_support(res, ia32_am_Source);
2360 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2366 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2370 assert(tarval_is_long(tv));
2371 val = get_tarval_long(tv);
2373 switch (immediate_constraint_type) {
2377 return val >= 0 && val <= 32;
2379 return val >= 0 && val <= 63;
2381 return val >= -128 && val <= 127;
2383 return val == 0xff || val == 0xffff;
2385 return val >= 0 && val <= 3;
2387 return val >= 0 && val <= 255;
2389 return val >= 0 && val <= 127;
2393 panic("Invalid immediate constraint found");
2398 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2401 tarval *offset = NULL;
2402 int offset_sign = 0;
2403 ir_entity *symconst_ent = NULL;
2404 int symconst_sign = 0;
2406 ir_node *cnst = NULL;
2407 ir_node *symconst = NULL;
2413 mode = get_irn_mode(node);
2414 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2415 !mode_is_reference(mode)) {
2419 if(is_Minus(node)) {
2421 node = get_Minus_op(node);
2424 if(is_Const(node)) {
2427 offset_sign = minus;
2428 } else if(is_SymConst(node)) {
2431 symconst_sign = minus;
2432 } else if(is_Add(node)) {
2433 ir_node *left = get_Add_left(node);
2434 ir_node *right = get_Add_right(node);
2435 if(is_Const(left) && is_SymConst(right)) {
2438 symconst_sign = minus;
2439 offset_sign = minus;
2440 } else if(is_SymConst(left) && is_Const(right)) {
2443 symconst_sign = minus;
2444 offset_sign = minus;
2446 } else if(is_Sub(node)) {
2447 ir_node *left = get_Sub_left(node);
2448 ir_node *right = get_Sub_right(node);
2449 if(is_Const(left) && is_SymConst(right)) {
2452 symconst_sign = !minus;
2453 offset_sign = minus;
2454 } else if(is_SymConst(left) && is_Const(right)) {
2457 symconst_sign = minus;
2458 offset_sign = !minus;
2465 offset = get_Const_tarval(cnst);
2466 if(!tarval_is_long(offset)) {
2467 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2472 if(!check_immediate_constraint(offset, immediate_constraint_type))
2475 if(symconst != NULL) {
2476 if(immediate_constraint_type != 0) {
2477 /* we need full 32bits for symconsts */
2481 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2483 symconst_ent = get_SymConst_entity(symconst);
2485 if(cnst == NULL && symconst == NULL)
2488 if(offset_sign && offset != NULL) {
2489 offset = tarval_neg(offset);
2492 irg = current_ir_graph;
2493 dbgi = get_irn_dbg_info(node);
2494 block = get_irg_start_block(irg);
2495 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2497 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2499 /* make sure we don't schedule stuff before the barrier */
2500 add_irn_dep(res, get_irg_frame(irg));
2505 typedef struct constraint_t constraint_t;
2506 struct constraint_t {
2509 const arch_register_req_t **out_reqs;
2511 const arch_register_req_t *req;
2512 unsigned immediate_possible;
2513 char immediate_type;
2516 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2518 int immediate_possible = 0;
2519 char immediate_type = 0;
2520 unsigned limited = 0;
2521 const arch_register_class_t *cls = NULL;
2523 struct obstack *obst;
2524 arch_register_req_t *req;
2525 unsigned *limited_ptr;
2529 /* TODO: replace all the asserts with nice error messages */
2531 printf("Constraint: %s\n", c);
2541 assert(cls == NULL ||
2542 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2543 cls = &ia32_reg_classes[CLASS_ia32_gp];
2544 limited |= 1 << REG_EAX;
2547 assert(cls == NULL ||
2548 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2549 cls = &ia32_reg_classes[CLASS_ia32_gp];
2550 limited |= 1 << REG_EBX;
2553 assert(cls == NULL ||
2554 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2555 cls = &ia32_reg_classes[CLASS_ia32_gp];
2556 limited |= 1 << REG_ECX;
2559 assert(cls == NULL ||
2560 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2561 cls = &ia32_reg_classes[CLASS_ia32_gp];
2562 limited |= 1 << REG_EDX;
2565 assert(cls == NULL ||
2566 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2567 cls = &ia32_reg_classes[CLASS_ia32_gp];
2568 limited |= 1 << REG_EDI;
2571 assert(cls == NULL ||
2572 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2573 cls = &ia32_reg_classes[CLASS_ia32_gp];
2574 limited |= 1 << REG_ESI;
2577 case 'q': /* q means lower part of the regs only, this makes no
2578 * difference to Q for us (we only assigne whole registers) */
2579 assert(cls == NULL ||
2580 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2581 cls = &ia32_reg_classes[CLASS_ia32_gp];
2582 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2586 assert(cls == NULL ||
2587 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2588 cls = &ia32_reg_classes[CLASS_ia32_gp];
2589 limited |= 1 << REG_EAX | 1 << REG_EDX;
2592 assert(cls == NULL ||
2593 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2594 cls = &ia32_reg_classes[CLASS_ia32_gp];
2595 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2596 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2603 assert(cls == NULL);
2604 cls = &ia32_reg_classes[CLASS_ia32_gp];
2610 /* TODO: mark values so the x87 simulator knows about t and u */
2611 assert(cls == NULL);
2612 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2617 assert(cls == NULL);
2618 /* TODO: check that sse2 is supported */
2619 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2629 assert(!immediate_possible);
2630 immediate_possible = 1;
2631 immediate_type = *c;
2635 assert(!immediate_possible);
2636 immediate_possible = 1;
2640 assert(!immediate_possible && cls == NULL);
2641 immediate_possible = 1;
2642 cls = &ia32_reg_classes[CLASS_ia32_gp];
2655 assert(constraint->is_in && "can only specify same constraint "
2658 sscanf(c, "%d%n", &same_as, &p);
2665 case 'E': /* no float consts yet */
2666 case 'F': /* no float consts yet */
2667 case 's': /* makes no sense on x86 */
2668 case 'X': /* we can't support that in firm */
2672 case '<': /* no autodecrement on x86 */
2673 case '>': /* no autoincrement on x86 */
2674 case 'C': /* sse constant not supported yet */
2675 case 'G': /* 80387 constant not supported yet */
2676 case 'y': /* we don't support mmx registers yet */
2677 case 'Z': /* not available in 32 bit mode */
2678 case 'e': /* not available in 32 bit mode */
2679 assert(0 && "asm constraint not supported");
2682 assert(0 && "unknown asm constraint found");
2689 const arch_register_req_t *other_constr;
2691 assert(cls == NULL && "same as and register constraint not supported");
2692 assert(!immediate_possible && "same as and immediate constraint not "
2694 assert(same_as < constraint->n_outs && "wrong constraint number in "
2695 "same_as constraint");
2697 other_constr = constraint->out_reqs[same_as];
2699 req = obstack_alloc(obst, sizeof(req[0]));
2700 req->cls = other_constr->cls;
2701 req->type = arch_register_req_type_should_be_same;
2702 req->limited = NULL;
2703 req->other_same = pos;
2704 req->other_different = -1;
2706 /* switch constraints. This is because in firm we have same_as
2707 * constraints on the output constraints while in the gcc asm syntax
2708 * they are specified on the input constraints */
2709 constraint->req = other_constr;
2710 constraint->out_reqs[same_as] = req;
2711 constraint->immediate_possible = 0;
2715 if(immediate_possible && cls == NULL) {
2716 cls = &ia32_reg_classes[CLASS_ia32_gp];
2718 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2719 assert(cls != NULL);
2721 if(immediate_possible) {
2722 assert(constraint->is_in
2723 && "imeediates make no sense for output constraints");
2725 /* todo: check types (no float input on 'r' constrainted in and such... */
2727 irg = current_ir_graph;
2728 obst = get_irg_obstack(irg);
2731 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2732 limited_ptr = (unsigned*) (req+1);
2734 req = obstack_alloc(obst, sizeof(req[0]));
2736 memset(req, 0, sizeof(req[0]));
2739 req->type = arch_register_req_type_limited;
2740 *limited_ptr = limited;
2741 req->limited = limited_ptr;
2743 req->type = arch_register_req_type_normal;
2747 constraint->req = req;
2748 constraint->immediate_possible = immediate_possible;
2749 constraint->immediate_type = immediate_type;
2753 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2760 panic("Clobbers not supported yet");
2763 ir_node *gen_ASM(ir_node *node)
2766 ir_graph *irg = current_ir_graph;
2767 ir_node *block = be_transform_node(get_nodes_block(node));
2768 dbg_info *dbgi = get_irn_dbg_info(node);
2775 ia32_asm_attr_t *attr;
2776 const arch_register_req_t **out_reqs;
2777 const arch_register_req_t **in_reqs;
2778 struct obstack *obst;
2779 constraint_t parsed_constraint;
2781 /* assembler could contain float statements */
2784 /* transform inputs */
2785 arity = get_irn_arity(node);
2786 in = alloca(arity * sizeof(in[0]));
2787 memset(in, 0, arity * sizeof(in[0]));
2789 n_outs = get_ASM_n_output_constraints(node);
2790 n_clobbers = get_ASM_n_clobbers(node);
2791 out_arity = n_outs + n_clobbers;
2793 /* construct register constraints */
2794 obst = get_irg_obstack(irg);
2795 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2796 parsed_constraint.out_reqs = out_reqs;
2797 parsed_constraint.n_outs = n_outs;
2798 parsed_constraint.is_in = 0;
2799 for(i = 0; i < out_arity; ++i) {
2803 const ir_asm_constraint *constraint;
2804 constraint = & get_ASM_output_constraints(node) [i];
2805 c = get_id_str(constraint->constraint);
2806 parse_asm_constraint(i, &parsed_constraint, c);
2808 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2809 c = get_id_str(glob_id);
2810 parse_clobber(node, i, &parsed_constraint, c);
2812 out_reqs[i] = parsed_constraint.req;
2815 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2816 parsed_constraint.is_in = 1;
2817 for(i = 0; i < arity; ++i) {
2818 const ir_asm_constraint *constraint;
2822 constraint = & get_ASM_input_constraints(node) [i];
2823 constr_id = constraint->constraint;
2824 c = get_id_str(constr_id);
2825 parse_asm_constraint(i, &parsed_constraint, c);
2826 in_reqs[i] = parsed_constraint.req;
2828 if(parsed_constraint.immediate_possible) {
2829 ir_node *pred = get_irn_n(node, i);
2830 char imm_type = parsed_constraint.immediate_type;
2831 ir_node *immediate = try_create_Immediate(pred, imm_type);
2833 if(immediate != NULL) {
2839 /* transform inputs */
2840 for(i = 0; i < arity; ++i) {
2842 ir_node *transformed;
2847 pred = get_irn_n(node, i);
2848 transformed = be_transform_node(pred);
2849 in[i] = transformed;
2852 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2854 generic_attr = get_irn_generic_attr(res);
2855 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2856 attr->asm_text = get_ASM_text(node);
2857 set_ia32_out_req_all(res, out_reqs);
2858 set_ia32_in_req_all(res, in_reqs);
2860 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2865 /********************************************
2868 * | |__ ___ _ __ ___ __| | ___ ___
2869 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2870 * | |_) | __/ | | | (_) | (_| | __/\__ \
2871 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2873 ********************************************/
2875 static ir_node *gen_be_StackParam(ir_node *node) {
2876 ir_node *block = be_transform_node(get_nodes_block(node));
2877 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2878 ir_node *new_ptr = be_transform_node(ptr);
2879 ir_node *new_op = NULL;
2880 ir_graph *irg = current_ir_graph;
2881 dbg_info *dbgi = get_irn_dbg_info(node);
2882 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2883 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2884 ir_mode *load_mode = get_irn_mode(node);
2885 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2889 if (mode_is_float(load_mode)) {
2891 if (USE_SSE2(env_cg)) {
2892 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2893 pn_res = pn_ia32_xLoad_res;
2894 proj_mode = mode_xmm;
2896 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2897 pn_res = pn_ia32_vfld_res;
2898 proj_mode = mode_vfp;
2901 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2902 proj_mode = mode_Iu;
2903 pn_res = pn_ia32_Load_res;
2906 set_irn_pinned(new_op, op_pin_state_floats);
2907 set_ia32_frame_ent(new_op, ent);
2908 set_ia32_use_frame(new_op);
2910 set_ia32_am_support(new_op, ia32_am_Source);
2911 set_ia32_op_type(new_op, ia32_AddrModeS);
2912 set_ia32_am_flavour(new_op, ia32_am_B);
2913 set_ia32_ls_mode(new_op, load_mode);
2914 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2916 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2918 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2922 * Transforms a FrameAddr into an ia32 Add.
2924 static ir_node *gen_be_FrameAddr(ir_node *node) {
2925 ir_node *block = be_transform_node(get_nodes_block(node));
2926 ir_node *op = be_get_FrameAddr_frame(node);
2927 ir_node *new_op = be_transform_node(op);
2928 ir_graph *irg = current_ir_graph;
2929 dbg_info *dbgi = get_irn_dbg_info(node);
2930 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2933 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2934 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2935 set_ia32_am_support(res, ia32_am_Full);
2936 set_ia32_use_frame(res);
2937 set_ia32_am_flavour(res, ia32_am_OB);
2939 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2945 * Transforms a FrameLoad into an ia32 Load.
2947 static ir_node *gen_be_FrameLoad(ir_node *node) {
2948 ir_node *block = be_transform_node(get_nodes_block(node));
2949 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2950 ir_node *new_mem = be_transform_node(mem);
2951 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2952 ir_node *new_ptr = be_transform_node(ptr);
2953 ir_node *new_op = NULL;
2954 ir_graph *irg = current_ir_graph;
2955 dbg_info *dbgi = get_irn_dbg_info(node);
2956 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2957 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2958 ir_mode *mode = get_type_mode(get_entity_type(ent));
2959 ir_node *projs[pn_Load_max];
2961 ia32_collect_Projs(node, projs, pn_Load_max);
2963 if (mode_is_float(mode)) {
2965 if (USE_SSE2(env_cg)) {
2966 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2969 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2973 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2976 set_irn_pinned(new_op, op_pin_state_floats);
2977 set_ia32_frame_ent(new_op, ent);
2978 set_ia32_use_frame(new_op);
2980 set_ia32_am_support(new_op, ia32_am_Source);
2981 set_ia32_op_type(new_op, ia32_AddrModeS);
2982 set_ia32_am_flavour(new_op, ia32_am_B);
2983 set_ia32_ls_mode(new_op, mode);
2985 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2992 * Transforms a FrameStore into an ia32 Store.
2994 static ir_node *gen_be_FrameStore(ir_node *node) {
2995 ir_node *block = be_transform_node(get_nodes_block(node));
2996 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2997 ir_node *new_mem = be_transform_node(mem);
2998 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2999 ir_node *new_ptr = be_transform_node(ptr);
3000 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3001 ir_node *new_val = be_transform_node(val);
3002 ir_node *new_op = NULL;
3003 ir_graph *irg = current_ir_graph;
3004 dbg_info *dbgi = get_irn_dbg_info(node);
3005 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3006 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3007 ir_mode *mode = get_irn_mode(val);
3009 if (mode_is_float(mode)) {
3011 if (USE_SSE2(env_cg)) {
3012 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3014 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3016 } else if (get_mode_size_bits(mode) == 8) {
3017 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3019 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3022 set_ia32_frame_ent(new_op, ent);
3023 set_ia32_use_frame(new_op);
3025 set_ia32_am_support(new_op, ia32_am_Dest);
3026 set_ia32_op_type(new_op, ia32_AddrModeD);
3027 set_ia32_am_flavour(new_op, ia32_am_B);
3028 set_ia32_ls_mode(new_op, mode);
3030 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3036 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3038 static ir_node *gen_be_Return(ir_node *node) {
3039 ir_graph *irg = current_ir_graph;
3040 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3041 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3042 ir_entity *ent = get_irg_entity(irg);
3043 ir_type *tp = get_entity_type(ent);
3048 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3049 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3052 int pn_ret_val, pn_ret_mem, arity, i;
3054 assert(ret_val != NULL);
3055 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3056 return be_duplicate_node(node);
3059 res_type = get_method_res_type(tp, 0);
3061 if (! is_Primitive_type(res_type)) {
3062 return be_duplicate_node(node);
3065 mode = get_type_mode(res_type);
3066 if (! mode_is_float(mode)) {
3067 return be_duplicate_node(node);
3070 assert(get_method_n_ress(tp) == 1);
3072 pn_ret_val = get_Proj_proj(ret_val);
3073 pn_ret_mem = get_Proj_proj(ret_mem);
3075 /* get the Barrier */
3076 barrier = get_Proj_pred(ret_val);
3078 /* get result input of the Barrier */
3079 ret_val = get_irn_n(barrier, pn_ret_val);
3080 new_ret_val = be_transform_node(ret_val);
3082 /* get memory input of the Barrier */
3083 ret_mem = get_irn_n(barrier, pn_ret_mem);
3084 new_ret_mem = be_transform_node(ret_mem);
3086 frame = get_irg_frame(irg);
3088 dbgi = get_irn_dbg_info(barrier);
3089 block = be_transform_node(get_nodes_block(barrier));
3091 noreg = ia32_new_NoReg_gp(env_cg);
3093 /* store xmm0 onto stack */
3094 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3095 set_ia32_ls_mode(sse_store, mode);
3096 set_ia32_op_type(sse_store, ia32_AddrModeD);
3097 set_ia32_use_frame(sse_store);
3098 set_ia32_am_flavour(sse_store, ia32_am_B);
3099 set_ia32_am_support(sse_store, ia32_am_Dest);
3102 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3103 set_ia32_ls_mode(fld, mode);
3104 set_ia32_op_type(fld, ia32_AddrModeS);
3105 set_ia32_use_frame(fld);
3106 set_ia32_am_flavour(fld, ia32_am_B);
3107 set_ia32_am_support(fld, ia32_am_Source);
3109 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3110 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3111 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3113 /* create a new barrier */
3114 arity = get_irn_arity(barrier);
3115 in = alloca(arity * sizeof(in[0]));
3116 for (i = 0; i < arity; ++i) {
3119 if (i == pn_ret_val) {
3121 } else if (i == pn_ret_mem) {
3124 ir_node *in = get_irn_n(barrier, i);
3125 new_in = be_transform_node(in);
3130 new_barrier = new_ir_node(dbgi, irg, block,
3131 get_irn_op(barrier), get_irn_mode(barrier),
3133 copy_node_attr(barrier, new_barrier);
3134 be_duplicate_deps(barrier, new_barrier);
3135 be_set_transformed_node(barrier, new_barrier);
3136 mark_irn_visited(barrier);
3138 /* transform normally */
3139 return be_duplicate_node(node);
3143 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3145 static ir_node *gen_be_AddSP(ir_node *node) {
3146 ir_node *block = be_transform_node(get_nodes_block(node));
3147 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3148 ir_node *new_sz = be_transform_node(sz);
3149 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3150 ir_node *new_sp = be_transform_node(sp);
3151 ir_graph *irg = current_ir_graph;
3152 dbg_info *dbgi = get_irn_dbg_info(node);
3153 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3154 ir_node *nomem = new_NoMem();
3157 /* ia32 stack grows in reverse direction, make a SubSP */
3158 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3159 set_ia32_am_support(new_op, ia32_am_Source);
3160 fold_immediate(new_op, 2, 3);
3162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3168 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3170 static ir_node *gen_be_SubSP(ir_node *node) {
3171 ir_node *block = be_transform_node(get_nodes_block(node));
3172 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3173 ir_node *new_sz = be_transform_node(sz);
3174 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3175 ir_node *new_sp = be_transform_node(sp);
3176 ir_graph *irg = current_ir_graph;
3177 dbg_info *dbgi = get_irn_dbg_info(node);
3178 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3179 ir_node *nomem = new_NoMem();
3182 /* ia32 stack grows in reverse direction, make an AddSP */
3183 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3184 set_ia32_am_support(new_op, ia32_am_Source);
3185 fold_immediate(new_op, 2, 3);
3187 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3193 * This function just sets the register for the Unknown node
3194 * as this is not done during register allocation because Unknown
3195 * is an "ignore" node.
3197 static ir_node *gen_Unknown(ir_node *node) {
3198 ir_mode *mode = get_irn_mode(node);
3200 if (mode_is_float(mode)) {
3201 if (USE_SSE2(env_cg))
3202 return ia32_new_Unknown_xmm(env_cg);
3204 return ia32_new_Unknown_vfp(env_cg);
3205 } else if (mode_needs_gp_reg(mode)) {
3206 return ia32_new_Unknown_gp(env_cg);
3208 assert(0 && "unsupported Unknown-Mode");
3215 * Change some phi modes
3217 static ir_node *gen_Phi(ir_node *node) {
3218 ir_node *block = be_transform_node(get_nodes_block(node));
3219 ir_graph *irg = current_ir_graph;
3220 dbg_info *dbgi = get_irn_dbg_info(node);
3221 ir_mode *mode = get_irn_mode(node);
3224 if(mode_needs_gp_reg(mode)) {
3225 /* we shouldn't have any 64bit stuff around anymore */
3226 assert(get_mode_size_bits(mode) <= 32);
3227 /* all integer operations are on 32bit registers now */
3229 } else if(mode_is_float(mode)) {
3230 if (USE_SSE2(env_cg)) {
3237 /* phi nodes allow loops, so we use the old arguments for now
3238 * and fix this later */
3239 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3240 copy_node_attr(node, phi);
3241 be_duplicate_deps(node, phi);
3243 be_set_transformed_node(node, phi);
3244 be_enqueue_preds(node);
3249 /**********************************************************************
3252 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3253 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3254 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3255 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3257 **********************************************************************/
3259 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3261 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3264 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3265 ir_node *val, ir_node *mem);
3268 * Transforms a lowered Load into a "real" one.
3270 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3271 ir_node *block = be_transform_node(get_nodes_block(node));
3272 ir_node *ptr = get_irn_n(node, 0);
3273 ir_node *new_ptr = be_transform_node(ptr);
3274 ir_node *mem = get_irn_n(node, 1);
3275 ir_node *new_mem = be_transform_node(mem);
3276 ir_graph *irg = current_ir_graph;
3277 dbg_info *dbgi = get_irn_dbg_info(node);
3278 ir_mode *mode = get_ia32_ls_mode(node);
3279 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3283 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3284 lowering we have x87 nodes, so we need to enforce simulation.
3286 if (mode_is_float(mode)) {
3288 if (fp_unit == fp_x87)
3292 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3294 set_ia32_am_support(new_op, ia32_am_Source);
3295 set_ia32_op_type(new_op, ia32_AddrModeS);
3296 set_ia32_am_flavour(new_op, ia32_am_OB);
3297 set_ia32_am_offs_int(new_op, 0);
3298 set_ia32_am_scale(new_op, 1);
3299 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3300 if (is_ia32_am_sc_sign(node))
3301 set_ia32_am_sc_sign(new_op);
3302 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3303 if (is_ia32_use_frame(node)) {
3304 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3305 set_ia32_use_frame(new_op);
3308 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3314 * Transforms a lowered Store into a "real" one.
3316 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3317 ir_node *block = be_transform_node(get_nodes_block(node));
3318 ir_node *ptr = get_irn_n(node, 0);
3319 ir_node *new_ptr = be_transform_node(ptr);
3320 ir_node *val = get_irn_n(node, 1);
3321 ir_node *new_val = be_transform_node(val);
3322 ir_node *mem = get_irn_n(node, 2);
3323 ir_node *new_mem = be_transform_node(mem);
3324 ir_graph *irg = current_ir_graph;
3325 dbg_info *dbgi = get_irn_dbg_info(node);
3326 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3327 ir_mode *mode = get_ia32_ls_mode(node);
3330 ia32_am_flavour_t am_flav = ia32_B;
3333 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3334 lowering we have x87 nodes, so we need to enforce simulation.
3336 if (mode_is_float(mode)) {
3338 if (fp_unit == fp_x87)
3342 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3344 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3346 add_ia32_am_offs_int(new_op, am_offs);
3349 set_ia32_am_support(new_op, ia32_am_Dest);
3350 set_ia32_op_type(new_op, ia32_AddrModeD);
3351 set_ia32_am_flavour(new_op, am_flav);
3352 set_ia32_ls_mode(new_op, mode);
3353 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3354 set_ia32_use_frame(new_op);
3356 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3363 * Transforms an ia32_l_XXX into a "real" XXX node
3365 * @param env The transformation environment
3366 * @return the created ia32 XXX node
3368 #define GEN_LOWERED_OP(op) \
3369 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3370 ir_mode *mode = get_irn_mode(node); \
3371 if (mode_is_float(mode)) \
3373 return gen_binop(node, get_binop_left(node), \
3374 get_binop_right(node), new_rd_ia32_##op,0); \
3377 #define GEN_LOWERED_x87_OP(op) \
3378 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3380 FORCE_x87(env_cg); \
3381 new_op = gen_binop_float(node, get_binop_left(node), \
3382 get_binop_right(node), new_rd_ia32_##op); \
3386 #define GEN_LOWERED_UNOP(op) \
3387 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3388 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3391 #define GEN_LOWERED_SHIFT_OP(op) \
3392 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3393 return gen_shift_binop(node, get_binop_left(node), \
3394 get_binop_right(node), new_rd_ia32_##op); \
3397 #define GEN_LOWERED_LOAD(op, fp_unit) \
3398 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3399 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3402 #define GEN_LOWERED_STORE(op, fp_unit) \
3403 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3404 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3411 GEN_LOWERED_OP(IMul)
3413 GEN_LOWERED_x87_OP(vfprem)
3414 GEN_LOWERED_x87_OP(vfmul)
3415 GEN_LOWERED_x87_OP(vfsub)
3417 GEN_LOWERED_UNOP(Neg)
3419 GEN_LOWERED_LOAD(vfild, fp_x87)
3420 GEN_LOWERED_LOAD(Load, fp_none)
3421 /*GEN_LOWERED_STORE(vfist, fp_x87)
3424 GEN_LOWERED_STORE(Store, fp_none)
3426 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3427 ir_node *block = be_transform_node(get_nodes_block(node));
3428 ir_node *left = get_binop_left(node);
3429 ir_node *new_left = be_transform_node(left);
3430 ir_node *right = get_binop_right(node);
3431 ir_node *new_right = be_transform_node(right);
3432 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3433 ir_graph *irg = current_ir_graph;
3434 dbg_info *dbgi = get_irn_dbg_info(node);
3437 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3438 clear_ia32_commutative(vfdiv);
3439 set_ia32_am_support(vfdiv, ia32_am_Source);
3440 fold_immediate(vfdiv, 2, 3);
3442 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3450 * Transforms a l_MulS into a "real" MulS node.
3452 * @param env The transformation environment
3453 * @return the created ia32 Mul node
3455 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3456 ir_node *block = be_transform_node(get_nodes_block(node));
3457 ir_node *left = get_binop_left(node);
3458 ir_node *new_left = be_transform_node(left);
3459 ir_node *right = get_binop_right(node);
3460 ir_node *new_right = be_transform_node(right);
3461 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3462 ir_graph *irg = current_ir_graph;
3463 dbg_info *dbgi = get_irn_dbg_info(node);
3466 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3467 /* and then skip the result Proj, because all needed Projs are already there. */
3468 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3469 clear_ia32_commutative(muls);
3470 set_ia32_am_support(muls, ia32_am_Source);
3471 fold_immediate(muls, 2, 3);
3473 /* check if EAX and EDX proj exist, add missing one */
3474 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3475 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3476 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3478 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3483 GEN_LOWERED_SHIFT_OP(Shl)
3484 GEN_LOWERED_SHIFT_OP(Shr)
3485 GEN_LOWERED_SHIFT_OP(Sar)
3488 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3489 * op1 - target to be shifted
3490 * op2 - contains bits to be shifted into target
3492 * Only op3 can be an immediate.
3494 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3495 ir_node *op2, ir_node *count)
3497 ir_node *block = be_transform_node(get_nodes_block(node));
3498 ir_node *new_op1 = be_transform_node(op1);
3499 ir_node *new_op2 = be_transform_node(op2);
3500 ir_node *new_count = be_transform_node(count);
3501 ir_node *new_op = NULL;
3502 ir_graph *irg = current_ir_graph;
3503 dbg_info *dbgi = get_irn_dbg_info(node);
3504 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3505 ir_node *nomem = new_NoMem();
3509 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3511 /* Check if immediate optimization is on and */
3512 /* if it's an operation with immediate. */
3513 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3515 /* Limit imm_op within range imm8 */
3517 tv = get_ia32_Immop_tarval(imm_op);
3520 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3521 set_ia32_Immop_tarval(imm_op, tv);
3528 /* integer operations */
3530 /* This is ShiftD with const */
3531 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3533 if (is_ia32_l_ShlD(node))
3534 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3535 new_op1, new_op2, noreg, nomem);
3537 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3538 new_op1, new_op2, noreg, nomem);
3539 copy_ia32_Immop_attr(new_op, imm_op);
3542 /* This is a normal ShiftD */
3543 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3544 if (is_ia32_l_ShlD(node))
3545 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3546 new_op1, new_op2, new_count, nomem);
3548 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3549 new_op1, new_op2, new_count, nomem);
3552 /* set AM support */
3553 // Matze: node has unsupported format (6inputs)
3554 //set_ia32_am_support(new_op, ia32_am_Dest);
3556 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3558 set_ia32_emit_cl(new_op);
3563 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3564 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3565 get_irn_n(node, 1), get_irn_n(node, 2));
3568 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3569 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3570 get_irn_n(node, 1), get_irn_n(node, 2));
3574 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3576 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3577 ir_node *block = be_transform_node(get_nodes_block(node));
3578 ir_node *val = get_irn_n(node, 1);
3579 ir_node *new_val = be_transform_node(val);
3580 ia32_code_gen_t *cg = env_cg;
3581 ir_node *res = NULL;
3582 ir_graph *irg = current_ir_graph;
3584 ir_node *noreg, *new_ptr, *new_mem;
3591 mem = get_irn_n(node, 2);
3592 new_mem = be_transform_node(mem);
3593 ptr = get_irn_n(node, 0);
3594 new_ptr = be_transform_node(ptr);
3595 noreg = ia32_new_NoReg_gp(cg);
3596 dbgi = get_irn_dbg_info(node);
3598 /* Store x87 -> MEM */
3599 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3600 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3601 set_ia32_use_frame(res);
3602 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3603 set_ia32_am_support(res, ia32_am_Dest);
3604 set_ia32_am_flavour(res, ia32_B);
3605 set_ia32_op_type(res, ia32_AddrModeD);
3607 /* Load MEM -> SSE */
3608 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3609 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3610 set_ia32_use_frame(res);
3611 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3612 set_ia32_am_support(res, ia32_am_Source);
3613 set_ia32_am_flavour(res, ia32_B);
3614 set_ia32_op_type(res, ia32_AddrModeS);
3615 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3621 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3623 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3624 ir_node *block = be_transform_node(get_nodes_block(node));
3625 ir_node *val = get_irn_n(node, 1);
3626 ir_node *new_val = be_transform_node(val);
3627 ia32_code_gen_t *cg = env_cg;
3628 ir_graph *irg = current_ir_graph;
3629 ir_node *res = NULL;
3630 ir_entity *fent = get_ia32_frame_ent(node);
3631 ir_mode *lsmode = get_ia32_ls_mode(node);
3633 ir_node *noreg, *new_ptr, *new_mem;
3637 if (! USE_SSE2(cg)) {
3638 /* SSE unit is not used -> skip this node. */
3642 ptr = get_irn_n(node, 0);
3643 new_ptr = be_transform_node(ptr);
3644 mem = get_irn_n(node, 2);
3645 new_mem = be_transform_node(mem);
3646 noreg = ia32_new_NoReg_gp(cg);
3647 dbgi = get_irn_dbg_info(node);
3649 /* Store SSE -> MEM */
3650 if (is_ia32_xLoad(skip_Proj(new_val))) {
3651 ir_node *ld = skip_Proj(new_val);
3653 /* we can vfld the value directly into the fpu */
3654 fent = get_ia32_frame_ent(ld);
3655 ptr = get_irn_n(ld, 0);
3656 offs = get_ia32_am_offs_int(ld);
3658 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3659 set_ia32_frame_ent(res, fent);
3660 set_ia32_use_frame(res);
3661 set_ia32_ls_mode(res, lsmode);
3662 set_ia32_am_support(res, ia32_am_Dest);
3663 set_ia32_am_flavour(res, ia32_B);
3664 set_ia32_op_type(res, ia32_AddrModeD);
3668 /* Load MEM -> x87 */
3669 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3670 set_ia32_frame_ent(res, fent);
3671 set_ia32_use_frame(res);
3672 add_ia32_am_offs_int(res, offs);
3673 set_ia32_am_support(res, ia32_am_Source);
3674 set_ia32_am_flavour(res, ia32_B);
3675 set_ia32_op_type(res, ia32_AddrModeS);
3676 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3681 /*********************************************************
3684 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3685 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3686 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3687 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3689 *********************************************************/
3692 * the BAD transformer.
3694 static ir_node *bad_transform(ir_node *node) {
3695 panic("No transform function for %+F available.\n", node);
3700 * Transform the Projs of an AddSP.
3702 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3703 ir_node *block = be_transform_node(get_nodes_block(node));
3704 ir_node *pred = get_Proj_pred(node);
3705 ir_node *new_pred = be_transform_node(pred);
3706 ir_graph *irg = current_ir_graph;
3707 dbg_info *dbgi = get_irn_dbg_info(node);
3708 long proj = get_Proj_proj(node);
3710 if (proj == pn_be_AddSP_res) {
3711 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3712 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3714 } else if (proj == pn_be_AddSP_M) {
3715 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3719 return new_rd_Unknown(irg, get_irn_mode(node));
3723 * Transform the Projs of a SubSP.
3725 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3726 ir_node *block = be_transform_node(get_nodes_block(node));
3727 ir_node *pred = get_Proj_pred(node);
3728 ir_node *new_pred = be_transform_node(pred);
3729 ir_graph *irg = current_ir_graph;
3730 dbg_info *dbgi = get_irn_dbg_info(node);
3731 long proj = get_Proj_proj(node);
3733 if (proj == pn_be_SubSP_res) {
3734 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3735 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3737 } else if (proj == pn_be_SubSP_M) {
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3742 return new_rd_Unknown(irg, get_irn_mode(node));
3746 * Transform and renumber the Projs from a Load.
3748 static ir_node *gen_Proj_Load(ir_node *node) {
3749 ir_node *block = be_transform_node(get_nodes_block(node));
3750 ir_node *pred = get_Proj_pred(node);
3751 ir_node *new_pred = be_transform_node(pred);
3752 ir_graph *irg = current_ir_graph;
3753 dbg_info *dbgi = get_irn_dbg_info(node);
3754 long proj = get_Proj_proj(node);
3756 /* renumber the proj */
3757 if (is_ia32_Load(new_pred)) {
3758 if (proj == pn_Load_res) {
3759 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3760 } else if (proj == pn_Load_M) {
3761 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3763 } else if (is_ia32_xLoad(new_pred)) {
3764 if (proj == pn_Load_res) {
3765 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3766 } else if (proj == pn_Load_M) {
3767 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3769 } else if (is_ia32_vfld(new_pred)) {
3770 if (proj == pn_Load_res) {
3771 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3772 } else if (proj == pn_Load_M) {
3773 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3778 return new_rd_Unknown(irg, get_irn_mode(node));
3782 * Transform and renumber the Projs from a DivMod like instruction.
3784 static ir_node *gen_Proj_DivMod(ir_node *node) {
3785 ir_node *block = be_transform_node(get_nodes_block(node));
3786 ir_node *pred = get_Proj_pred(node);
3787 ir_node *new_pred = be_transform_node(pred);
3788 ir_graph *irg = current_ir_graph;
3789 dbg_info *dbgi = get_irn_dbg_info(node);
3790 ir_mode *mode = get_irn_mode(node);
3791 long proj = get_Proj_proj(node);
3793 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3795 switch (get_irn_opcode(pred)) {
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3801 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3809 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3811 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3819 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3820 case pn_DivMod_res_div:
3821 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3822 case pn_DivMod_res_mod:
3823 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3833 return new_rd_Unknown(irg, mode);
3837 * Transform and renumber the Projs from a CopyB.
3839 static ir_node *gen_Proj_CopyB(ir_node *node) {
3840 ir_node *block = be_transform_node(get_nodes_block(node));
3841 ir_node *pred = get_Proj_pred(node);
3842 ir_node *new_pred = be_transform_node(pred);
3843 ir_graph *irg = current_ir_graph;
3844 dbg_info *dbgi = get_irn_dbg_info(node);
3845 ir_mode *mode = get_irn_mode(node);
3846 long proj = get_Proj_proj(node);
3849 case pn_CopyB_M_regular:
3850 if (is_ia32_CopyB_i(new_pred)) {
3851 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3852 } else if (is_ia32_CopyB(new_pred)) {
3853 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3861 return new_rd_Unknown(irg, mode);
3865 * Transform and renumber the Projs from a vfdiv.
3867 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3868 ir_node *block = be_transform_node(get_nodes_block(node));
3869 ir_node *pred = get_Proj_pred(node);
3870 ir_node *new_pred = be_transform_node(pred);
3871 ir_graph *irg = current_ir_graph;
3872 dbg_info *dbgi = get_irn_dbg_info(node);
3873 ir_mode *mode = get_irn_mode(node);
3874 long proj = get_Proj_proj(node);
3877 case pn_ia32_l_vfdiv_M:
3878 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3879 case pn_ia32_l_vfdiv_res:
3880 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3885 return new_rd_Unknown(irg, mode);
3889 * Transform and renumber the Projs from a Quot.
3891 static ir_node *gen_Proj_Quot(ir_node *node) {
3892 ir_node *block = be_transform_node(get_nodes_block(node));
3893 ir_node *pred = get_Proj_pred(node);
3894 ir_node *new_pred = be_transform_node(pred);
3895 ir_graph *irg = current_ir_graph;
3896 dbg_info *dbgi = get_irn_dbg_info(node);
3897 ir_mode *mode = get_irn_mode(node);
3898 long proj = get_Proj_proj(node);
3902 if (is_ia32_xDiv(new_pred)) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3904 } else if (is_ia32_vfdiv(new_pred)) {
3905 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3909 if (is_ia32_xDiv(new_pred)) {
3910 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3911 } else if (is_ia32_vfdiv(new_pred)) {
3912 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3920 return new_rd_Unknown(irg, mode);
3924 * Transform the Thread Local Storage Proj.
3926 static ir_node *gen_Proj_tls(ir_node *node) {
3927 ir_node *block = be_transform_node(get_nodes_block(node));
3928 ir_graph *irg = current_ir_graph;
3929 dbg_info *dbgi = NULL;
3930 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3936 * Transform the Projs from a be_Call.
3938 static ir_node *gen_Proj_be_Call(ir_node *node) {
3939 ir_node *block = be_transform_node(get_nodes_block(node));
3940 ir_node *call = get_Proj_pred(node);
3941 ir_node *new_call = be_transform_node(call);
3942 ir_graph *irg = current_ir_graph;
3943 dbg_info *dbgi = get_irn_dbg_info(node);
3944 long proj = get_Proj_proj(node);
3945 ir_mode *mode = get_irn_mode(node);
3947 const arch_register_class_t *cls;
3949 /* The following is kinda tricky: If we're using SSE, then we have to
3950 * move the result value of the call in floating point registers to an
3951 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3952 * after the call, we have to make sure to correctly make the
3953 * MemProj and the result Proj use these 2 nodes
3955 if (proj == pn_be_Call_M_regular) {
3956 // get new node for result, are we doing the sse load/store hack?
3957 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3958 ir_node *call_res_new;
3959 ir_node *call_res_pred = NULL;
3961 if (call_res != NULL) {
3962 call_res_new = be_transform_node(call_res);
3963 call_res_pred = get_Proj_pred(call_res_new);
3966 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3967 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3969 assert(is_ia32_xLoad(call_res_pred));
3970 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3973 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3975 ir_node *frame = get_irg_frame(irg);
3976 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3978 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3980 const arch_register_class_t *cls;
3982 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3983 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3985 /* store st(0) onto stack */
3986 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3988 set_ia32_ls_mode(fstp, mode);
3989 set_ia32_op_type(fstp, ia32_AddrModeD);
3990 set_ia32_use_frame(fstp);
3991 set_ia32_am_flavour(fstp, ia32_am_B);
3992 set_ia32_am_support(fstp, ia32_am_Dest);
3994 /* load into SSE register */
3995 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3996 set_ia32_ls_mode(sse_load, mode);
3997 set_ia32_op_type(sse_load, ia32_AddrModeS);
3998 set_ia32_use_frame(sse_load);
3999 set_ia32_am_flavour(sse_load, ia32_am_B);
4000 set_ia32_am_support(sse_load, ia32_am_Source);
4002 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
4004 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4006 /* get a Proj representing a caller save register */
4007 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4008 assert(is_Proj(p) && "Proj expected.");
4010 /* user of the the proj is the Keep */
4011 p = get_edge_src_irn(get_irn_out_edge_first(p));
4012 assert(be_is_Keep(p) && "Keep expected.");
4014 /* keep the result */
4015 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
4016 keepin[0] = sse_load;
4017 be_new_Keep(cls, irg, block, 1, keepin);
4022 /* transform call modes */
4023 if (mode_is_data(mode)) {
4024 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4028 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4032 * Transform the Projs from a Cmp.
4034 static ir_node *gen_Proj_Cmp(ir_node *node)
4036 /* normally Cmps are processed when looking at Cond nodes, but this case
4037 * can happen in complicated Psi conditions */
4039 ir_graph *irg = current_ir_graph;
4040 dbg_info *dbgi = get_irn_dbg_info(node);
4041 ir_node *block = be_transform_node(get_nodes_block(node));
4042 ir_node *cmp = get_Proj_pred(node);
4043 long pnc = get_Proj_proj(node);
4044 ir_node *cmp_left = get_Cmp_left(cmp);
4045 ir_node *cmp_right = get_Cmp_right(cmp);
4046 ir_node *new_cmp_left;
4047 ir_node *new_cmp_right;
4048 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4049 ir_node *nomem = new_rd_NoMem(irg);
4050 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4053 assert(!mode_is_float(cmp_mode));
4055 /* (a != b) -> (a ^ b) */
4056 if(pnc == pn_Cmp_Lg) {
4057 if(is_Const_0(cmp_left)) {
4058 new_op = be_transform_node(cmp_right);
4059 } else if(is_Const_0(cmp_right)) {
4060 new_op = be_transform_node(cmp_left);
4062 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4068 * (a == b) -> !(a ^ b)
4069 * (a < 0) -> (a & 0x80000000)
4070 * (a <= 0) -> !(a & 0x7fffffff)
4071 * (a > 0) -> (a & 0x7fffffff)
4072 * (a >= 0) -> !(a & 0x80000000)
4075 if(!mode_is_signed(cmp_mode)) {
4076 pnc |= ia32_pn_Cmp_Unsigned;
4079 new_cmp_right = try_create_Immediate(cmp_right, 0);
4080 if(new_cmp_right == NULL) {
4081 new_cmp_right = try_create_Immediate(cmp_left, 0);
4082 if(new_cmp_right != NULL) {
4083 pnc = get_inversed_pnc(pnc);
4084 new_cmp_left = be_transform_node(cmp_right);
4087 new_cmp_left = be_transform_node(cmp_left);
4089 if(new_cmp_right == NULL) {
4090 new_cmp_left = be_transform_node(cmp_left);
4091 new_cmp_right = be_transform_node(cmp_right);
4094 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4095 new_cmp_right, nomem, pnc);
4096 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4102 * Transform and potentially renumber Proj nodes.
4104 static ir_node *gen_Proj(ir_node *node) {
4105 ir_graph *irg = current_ir_graph;
4106 dbg_info *dbgi = get_irn_dbg_info(node);
4107 ir_node *pred = get_Proj_pred(node);
4108 long proj = get_Proj_proj(node);
4110 if (is_Store(pred) || be_is_FrameStore(pred)) {
4111 if (proj == pn_Store_M) {
4112 return be_transform_node(pred);
4115 return new_r_Bad(irg);
4117 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4118 return gen_Proj_Load(node);
4119 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4120 return gen_Proj_DivMod(node);
4121 } else if (is_CopyB(pred)) {
4122 return gen_Proj_CopyB(node);
4123 } else if (is_Quot(pred)) {
4124 return gen_Proj_Quot(node);
4125 } else if (is_ia32_l_vfdiv(pred)) {
4126 return gen_Proj_l_vfdiv(node);
4127 } else if (be_is_SubSP(pred)) {
4128 return gen_Proj_be_SubSP(node);
4129 } else if (be_is_AddSP(pred)) {
4130 return gen_Proj_be_AddSP(node);
4131 } else if (be_is_Call(pred)) {
4132 return gen_Proj_be_Call(node);
4133 } else if (is_Cmp(pred)) {
4134 return gen_Proj_Cmp(node);
4135 } else if (get_irn_op(pred) == op_Start) {
4136 if (proj == pn_Start_X_initial_exec) {
4137 ir_node *block = get_nodes_block(pred);
4140 /* we exchange the ProjX with a jump */
4141 block = be_transform_node(block);
4142 jump = new_rd_Jmp(dbgi, irg, block);
4145 if (node == be_get_old_anchor(anchor_tls)) {
4146 return gen_Proj_tls(node);
4149 ir_node *new_pred = be_transform_node(pred);
4150 ir_node *block = be_transform_node(get_nodes_block(node));
4151 ir_mode *mode = get_irn_mode(node);
4152 if (mode_needs_gp_reg(mode)) {
4153 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4154 get_Proj_proj(node));
4155 #ifdef DEBUG_libfirm
4156 new_proj->node_nr = node->node_nr;
4162 return be_duplicate_node(node);
4166 * Enters all transform functions into the generic pointer
4168 static void register_transformers(void) {
4169 ir_op *op_Max, *op_Min, *op_Mulh;
4171 /* first clear the generic function pointer for all ops */
4172 clear_irp_opcodes_generic_func();
4174 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4175 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4212 /* transform ops from intrinsic lowering */
4232 /* GEN(ia32_l_vfist); TODO */
4234 GEN(ia32_l_X87toSSE);
4235 GEN(ia32_l_SSEtoX87);
4240 /* we should never see these nodes */
4255 /* handle generic backend nodes */
4266 /* set the register for all Unknown nodes */
4269 op_Max = get_op_Max();
4272 op_Min = get_op_Min();
4275 op_Mulh = get_op_Mulh();
4284 * Pre-transform all unknown and noreg nodes.
4286 static void ia32_pretransform_node(void *arch_cg) {
4287 ia32_code_gen_t *cg = arch_cg;
4289 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4290 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4291 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4292 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4293 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4294 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4297 /* do the transformation */
4298 void ia32_transform_graph(ia32_code_gen_t *cg) {
4299 register_transformers();
4301 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4304 void ia32_init_transform(void)
4306 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");