2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
493 /* don't do AM if other node inputs depend on the load (via mem-proj) */
494 if(other != NULL && get_nodes_block(other) == block
495 && heights_reachable_in_block(heights, other, load))
501 typedef struct ia32_address_mode_t ia32_address_mode_t;
502 struct ia32_address_mode_t {
506 ia32_op_type_t op_type;
510 unsigned commutative:1;
511 unsigned ins_permuted:1;
514 static void build_address(ia32_address_mode_t *am, ir_node *node)
516 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
517 ia32_address_t *addr = &am->addr;
526 ir_entity *entity = create_float_const_entity(node);
527 addr->base = noreg_gp;
528 addr->index = noreg_gp;
529 addr->mem = new_NoMem();
530 addr->symconst_ent = entity;
532 am->ls_mode = get_irn_mode(node);
533 am->pinned = op_pin_state_floats;
537 load = get_Proj_pred(node);
538 ptr = get_Load_ptr(load);
539 mem = get_Load_mem(load);
540 new_mem = be_transform_node(mem);
541 am->pinned = get_irn_pinned(load);
542 am->ls_mode = get_Load_mode(load);
543 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
545 /* construct load address */
546 ia32_create_address_mode(addr, ptr, /*force=*/0);
553 base = be_transform_node(base);
559 index = be_transform_node(index);
567 static void set_address(ir_node *node, ia32_address_t *addr)
569 set_ia32_am_scale(node, addr->scale);
570 set_ia32_am_sc(node, addr->symconst_ent);
571 set_ia32_am_offs_int(node, addr->offset);
572 if(addr->symconst_sign)
573 set_ia32_am_sc_sign(node);
575 set_ia32_use_frame(node);
576 set_ia32_frame_ent(node, addr->frame_entity);
579 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
581 set_address(node, &am->addr);
583 set_ia32_op_type(node, am->op_type);
584 set_ia32_ls_mode(node, am->ls_mode);
585 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
586 set_irn_pinned(node, am->pinned);
589 set_ia32_commutative(node);
593 * Check, if a given node is a Down-Conv, ie. a integer Conv
594 * from a mode with a mode with more bits to a mode with lesser bits.
595 * Moreover, we return only true if the node has not more than 1 user.
597 * @param node the node
598 * @return non-zero if node is a Down-Conv
600 static int is_downconv(const ir_node *node)
608 /* we only want to skip the conv when we're the only user
609 * (not optimal but for now...)
611 if(get_irn_n_edges(node) > 1)
614 src_mode = get_irn_mode(get_Conv_op(node));
615 dest_mode = get_irn_mode(node);
616 return mode_needs_gp_reg(src_mode)
617 && mode_needs_gp_reg(dest_mode)
618 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
621 /* Skip all Down-Conv's on a given node and return the resulting node. */
622 ir_node *ia32_skip_downconv(ir_node *node) {
623 while (is_downconv(node))
624 node = get_Conv_op(node);
631 match_commutative = 1 << 0,
632 match_am_and_immediates = 1 << 1,
633 match_no_am = 1 << 2,
634 match_8_bit_am = 1 << 3,
635 match_16_bit_am = 1 << 4,
636 match_no_immediate = 1 << 5,
637 match_force_32bit_op = 1 << 6,
638 match_skip_input_conv = 1 << 7
641 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
642 ir_node *op1, ir_node *op2, match_flags_t flags)
644 ia32_address_t *addr = &am->addr;
645 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
648 ir_mode *mode = get_irn_mode(op2);
650 unsigned commutative;
651 int use_am_and_immediates;
654 int mode_bits = get_mode_size_bits(mode);
656 memset(am, 0, sizeof(am[0]));
658 commutative = (flags & match_commutative) != 0;
659 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
660 use_am = ! (flags & match_no_am);
661 use_immediate = !(flags & match_no_immediate);
662 skip_input_conv = (flags & match_skip_input_conv) != 0;
665 assert(!commutative || op1 != NULL);
667 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
669 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
673 op2 = ia32_skip_downconv(op2);
675 op1 = ia32_skip_downconv(op1);
677 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
678 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
679 build_address(am, op2);
680 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
681 if(mode_is_float(mode)) {
682 new_op2 = ia32_new_NoReg_vfp(env_cg);
686 am->op_type = ia32_AddrModeS;
687 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
688 use_am && ia32_use_source_address_mode(block, op1, op2)) {
690 build_address(am, op1);
692 if(mode_is_float(mode)) {
693 noreg = ia32_new_NoReg_vfp(env_cg);
698 if(new_op2 != NULL) {
701 new_op1 = be_transform_node(op2);
703 am->ins_permuted = 1;
705 am->op_type = ia32_AddrModeS;
707 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
709 new_op2 = be_transform_node(op2);
710 am->op_type = ia32_Normal;
711 if(flags & match_force_32bit_op) {
712 am->ls_mode = mode_Iu;
714 am->ls_mode = get_irn_mode(op2);
717 if(addr->base == NULL)
718 addr->base = noreg_gp;
719 if(addr->index == NULL)
720 addr->index = noreg_gp;
721 if(addr->mem == NULL)
722 addr->mem = new_NoMem();
724 am->new_op1 = new_op1;
725 am->new_op2 = new_op2;
726 am->commutative = commutative;
729 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
731 ir_graph *irg = current_ir_graph;
735 if(am->mem_proj == NULL)
738 /* we have to create a mode_T so the old MemProj can attach to us */
739 mode = get_irn_mode(node);
740 load = get_Proj_pred(am->mem_proj);
742 mark_irn_visited(load);
743 be_set_transformed_node(load, node);
746 set_irn_mode(node, mode_T);
747 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
754 * Construct a standard binary operation, set AM and immediate if required.
756 * @param op1 The first operand
757 * @param op2 The second operand
758 * @param func The node constructor function
759 * @return The constructed ia32 node.
761 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
762 construct_binop_func *func, match_flags_t flags)
764 ir_node *block = get_nodes_block(node);
765 ir_node *new_block = be_transform_node(block);
766 ir_graph *irg = current_ir_graph;
767 dbg_info *dbgi = get_irn_dbg_info(node);
769 ia32_address_mode_t am;
770 ia32_address_t *addr = &am.addr;
772 flags |= match_force_32bit_op;
774 match_arguments(&am, block, op1, op2, flags);
776 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
777 am.new_op1, am.new_op2);
778 set_am_attributes(new_node, &am);
779 /* we can't use source address mode anymore when using immediates */
780 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
781 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
782 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
784 new_node = fix_mem_proj(new_node, &am);
791 n_ia32_l_binop_right,
792 n_ia32_l_binop_eflags
794 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
795 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
796 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
797 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
798 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
799 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
802 * Construct a binary operation which also consumes the eflags.
804 * @param node The node to transform
805 * @param func The node constructor function
806 * @param flags The match flags
807 * @return The constructor ia32 node
809 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
812 ir_node *src_block = get_nodes_block(node);
813 ir_node *block = be_transform_node(src_block);
814 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
815 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
816 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
817 ir_node *new_eflags = be_transform_node(eflags);
818 ir_graph *irg = current_ir_graph;
819 dbg_info *dbgi = get_irn_dbg_info(node);
821 ia32_address_mode_t am;
822 ia32_address_t *addr = &am.addr;
824 match_arguments(&am, src_block, op1, op2, flags);
826 new_node = func(dbgi, irg, block, addr->base, addr->index,
827 addr->mem, am.new_op1, am.new_op2, new_eflags);
828 set_am_attributes(new_node, &am);
829 /* we can't use source address mode anymore when using immediates */
830 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
831 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
832 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
834 new_node = fix_mem_proj(new_node, &am);
840 * Construct a standard binary operation, set AM and immediate if required.
842 * @param op1 The first operand
843 * @param op2 The second operand
844 * @param func The node constructor function
845 * @return The constructed ia32 node.
847 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
848 construct_binop_func *func,
851 ir_node *block = get_nodes_block(node);
852 ir_node *new_block = be_transform_node(block);
853 dbg_info *dbgi = get_irn_dbg_info(node);
854 ir_graph *irg = current_ir_graph;
856 ia32_address_mode_t am;
857 ia32_address_t *addr = &am.addr;
859 match_arguments(&am, block, op1, op2, flags);
861 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
862 am.new_op1, am.new_op2);
863 set_am_attributes(new_node, &am);
865 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
867 new_node = fix_mem_proj(new_node, &am);
872 static ir_node *get_fpcw(void)
875 if(initial_fpcw != NULL)
878 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
879 &ia32_fp_cw_regs[REG_FPCW]);
880 initial_fpcw = be_transform_node(fpcw);
886 * Construct a standard binary operation, set AM and immediate if required.
888 * @param op1 The first operand
889 * @param op2 The second operand
890 * @param func The node constructor function
891 * @return The constructed ia32 node.
893 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
894 construct_binop_float_func *func,
897 ir_graph *irg = current_ir_graph;
898 dbg_info *dbgi = get_irn_dbg_info(node);
899 ir_node *block = get_nodes_block(node);
900 ir_node *new_block = be_transform_node(block);
902 ia32_address_mode_t am;
903 ia32_address_t *addr = &am.addr;
905 match_arguments(&am, block, op1, op2, flags);
907 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
908 am.new_op1, am.new_op2, get_fpcw());
909 set_am_attributes(new_node, &am);
911 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
913 new_node = fix_mem_proj(new_node, &am);
919 * Construct a shift/rotate binary operation, sets AM and immediate if required.
921 * @param op1 The first operand
922 * @param op2 The second operand
923 * @param func The node constructor function
924 * @return The constructed ia32 node.
926 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
927 construct_shift_func *func)
929 dbg_info *dbgi = get_irn_dbg_info(node);
930 ir_graph *irg = current_ir_graph;
931 ir_node *block = get_nodes_block(node);
932 ir_node *new_block = be_transform_node(block);
933 ir_node *new_op1 = be_transform_node(op1);
937 assert(! mode_is_float(get_irn_mode(node))
938 && "Shift/Rotate with float not supported");
940 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
941 op2 = get_Conv_op(op2);
942 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
944 new_op2 = create_immediate_or_transform(op2, 0);
946 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
947 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
949 /* lowered shift instruction may have a dependency operand, handle it here */
950 if (get_irn_arity(node) == 3) {
951 /* we have a dependency */
952 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
953 add_irn_dep(new_node, new_dep);
961 * Construct a standard unary operation, set AM and immediate if required.
963 * @param op The operand
964 * @param func The node constructor function
965 * @return The constructed ia32 node.
967 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
969 ir_node *block = be_transform_node(get_nodes_block(node));
970 ir_node *new_op = be_transform_node(op);
971 ir_node *new_node = NULL;
972 ir_graph *irg = current_ir_graph;
973 dbg_info *dbgi = get_irn_dbg_info(node);
975 new_node = func(dbgi, irg, block, new_op);
977 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
982 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
983 ia32_address_t *addr)
985 ir_graph *irg = current_ir_graph;
986 ir_node *base = addr->base;
987 ir_node *index = addr->index;
991 base = ia32_new_NoReg_gp(env_cg);
993 base = be_transform_node(base);
997 index = ia32_new_NoReg_gp(env_cg);
999 index = be_transform_node(index);
1002 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1003 set_address(res, addr);
1008 static int am_has_immediates(const ia32_address_t *addr)
1010 return addr->offset != 0 || addr->symconst_ent != NULL
1011 || addr->frame_entity || addr->use_frame;
1015 * Creates an ia32 Add.
1017 * @return the created ia32 Add node
1019 static ir_node *gen_Add(ir_node *node) {
1020 ir_graph *irg = current_ir_graph;
1021 dbg_info *dbgi = get_irn_dbg_info(node);
1022 ir_node *block = get_nodes_block(node);
1023 ir_node *new_block = be_transform_node(block);
1024 ir_node *op1 = get_Add_left(node);
1025 ir_node *op2 = get_Add_right(node);
1026 ir_mode *mode = get_irn_mode(node);
1028 ir_node *add_immediate_op;
1029 ia32_address_t addr;
1030 ia32_address_mode_t am;
1032 if (mode_is_float(mode)) {
1033 if (USE_SSE2(env_cg))
1034 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
1036 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
1039 op2 = ia32_skip_downconv(op2);
1040 op1 = ia32_skip_downconv(op1);
1044 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1045 * 1. Add with immediate -> Lea
1046 * 2. Add with possible source address mode -> Add
1047 * 3. Otherwise -> Lea
1049 memset(&addr, 0, sizeof(addr));
1050 ia32_create_address_mode(&addr, node, /*force=*/1);
1051 add_immediate_op = NULL;
1053 if(addr.base == NULL && addr.index == NULL) {
1054 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1055 addr.symconst_sign, addr.offset);
1056 add_irn_dep(new_node, get_irg_frame(irg));
1057 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1060 /* add with immediate? */
1061 if(addr.index == NULL) {
1062 add_immediate_op = addr.base;
1063 } else if(addr.base == NULL && addr.scale == 0) {
1064 add_immediate_op = addr.index;
1067 if(add_immediate_op != NULL) {
1068 if(!am_has_immediates(&addr)) {
1069 #ifdef DEBUG_libfirm
1070 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1073 return be_transform_node(add_immediate_op);
1076 new_node = create_lea_from_address(dbgi, new_block, &addr);
1077 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1081 /* test if we can use source address mode */
1082 match_arguments(&am, block, op1, op2,
1083 match_commutative | match_force_32bit_op | match_skip_input_conv);
1085 /* construct an Add with source address mode */
1086 if (am.op_type == ia32_AddrModeS) {
1087 ia32_address_t *am_addr = &am.addr;
1088 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1089 am_addr->index, am_addr->mem, am.new_op1,
1091 set_am_attributes(new_node, &am);
1092 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1094 new_node = fix_mem_proj(new_node, &am);
1099 /* otherwise construct a lea */
1100 new_node = create_lea_from_address(dbgi, new_block, &addr);
1101 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1106 * Creates an ia32 Mul.
1108 * @return the created ia32 Mul node
1110 static ir_node *gen_Mul(ir_node *node) {
1111 ir_node *op1 = get_Mul_left(node);
1112 ir_node *op2 = get_Mul_right(node);
1113 ir_mode *mode = get_irn_mode(node);
1115 if (mode_is_float(mode)) {
1116 if (USE_SSE2(env_cg))
1117 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1119 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1123 for the lower 32bit of the result it doesn't matter whether we use
1124 signed or unsigned multiplication so we use IMul as it has fewer
1127 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1128 match_commutative | match_skip_input_conv | match_force_32bit_op);
1132 * Creates an ia32 Mulh.
1133 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1134 * this result while Mul returns the lower 32 bit.
1136 * @return the created ia32 Mulh node
1138 static ir_node *gen_Mulh(ir_node *node)
1140 ir_node *block = get_nodes_block(node);
1141 ir_node *new_block = be_transform_node(block);
1142 ir_graph *irg = current_ir_graph;
1143 dbg_info *dbgi = get_irn_dbg_info(node);
1144 ir_mode *mode = get_irn_mode(node);
1145 ir_node *op1 = get_Mulh_left(node);
1146 ir_node *op2 = get_Mulh_right(node);
1149 match_flags_t flags;
1150 ia32_address_mode_t am;
1151 ia32_address_t *addr = &am.addr;
1153 flags = match_force_32bit_op | match_commutative | match_no_immediate;
1155 assert(!mode_is_float(mode) && "Mulh with float not supported");
1157 match_arguments(&am, block, op1, op2, flags);
1159 if (mode_is_signed(mode)) {
1160 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1161 addr->index, addr->mem, am.new_op1,
1164 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1165 addr->index, addr->mem, am.new_op1,
1169 set_am_attributes(new_node, &am);
1170 /* we can't use source address mode anymore when using immediates */
1171 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1172 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1173 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1175 assert(get_irn_mode(new_node) == mode_T);
1177 fix_mem_proj(new_node, &am);
1179 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1180 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1181 mode_Iu, pn_ia32_IMul1OP_EDX);
1189 * Creates an ia32 And.
1191 * @return The created ia32 And node
1193 static ir_node *gen_And(ir_node *node) {
1194 ir_node *op1 = get_And_left(node);
1195 ir_node *op2 = get_And_right(node);
1196 assert(! mode_is_float(get_irn_mode(node)));
1198 /* is it a zero extension? */
1199 if (is_Const(op2)) {
1200 tarval *tv = get_Const_tarval(op2);
1201 long v = get_tarval_long(tv);
1203 if (v == 0xFF || v == 0xFFFF) {
1204 dbg_info *dbgi = get_irn_dbg_info(node);
1205 ir_node *block = get_nodes_block(node);
1212 assert(v == 0xFFFF);
1215 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1221 return gen_binop(node, op1, op2, new_rd_ia32_And,
1222 match_commutative | match_force_32bit_op | match_skip_input_conv);
1228 * Creates an ia32 Or.
1230 * @return The created ia32 Or node
1232 static ir_node *gen_Or(ir_node *node) {
1233 ir_node *op1 = get_Or_left(node);
1234 ir_node *op2 = get_Or_right(node);
1236 assert (! mode_is_float(get_irn_mode(node)));
1237 return gen_binop(node, op1, op2, new_rd_ia32_Or,
1238 match_commutative | match_skip_input_conv | match_force_32bit_op);
1244 * Creates an ia32 Eor.
1246 * @return The created ia32 Eor node
1248 static ir_node *gen_Eor(ir_node *node) {
1249 ir_node *op1 = get_Eor_left(node);
1250 ir_node *op2 = get_Eor_right(node);
1252 assert(! mode_is_float(get_irn_mode(node)));
1253 return gen_binop(node, op1, op2, new_rd_ia32_Xor,
1254 match_commutative | match_skip_input_conv | match_force_32bit_op);
1259 * Creates an ia32 Sub.
1261 * @return The created ia32 Sub node
1263 static ir_node *gen_Sub(ir_node *node) {
1264 ir_node *op1 = get_Sub_left(node);
1265 ir_node *op2 = get_Sub_right(node);
1266 ir_mode *mode = get_irn_mode(node);
1268 if (mode_is_float(mode)) {
1269 if (USE_SSE2(env_cg))
1270 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1272 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1276 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1280 return gen_binop(node, op1, op2, new_rd_ia32_Sub,
1281 match_force_32bit_op | match_skip_input_conv);
1284 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1287 * Generates an ia32 DivMod with additional infrastructure for the
1288 * register allocator if needed.
1290 * @param dividend -no comment- :)
1291 * @param divisor -no comment- :)
1292 * @param dm_flav flavour_Div/Mod/DivMod
1293 * @return The created ia32 DivMod node
1295 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1296 ir_node *divisor, ia32_op_flavour_t dm_flav)
1298 ir_node *block = be_transform_node(get_nodes_block(node));
1299 ir_node *new_dividend = be_transform_node(dividend);
1300 ir_node *new_divisor = be_transform_node(divisor);
1301 ir_graph *irg = current_ir_graph;
1302 dbg_info *dbgi = get_irn_dbg_info(node);
1303 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1304 ir_node *res, *proj_div, *proj_mod;
1306 ir_node *sign_extension;
1307 ir_node *mem, *new_mem;
1310 /* the upper bits have random contents for smaller modes */
1312 proj_div = proj_mod = NULL;
1316 mem = get_Div_mem(node);
1317 mode = get_Div_resmode(node);
1318 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1319 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1322 mem = get_Mod_mem(node);
1323 mode = get_Mod_resmode(node);
1324 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1325 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1327 case flavour_DivMod:
1328 mem = get_DivMod_mem(node);
1329 mode = get_DivMod_resmode(node);
1330 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1331 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1332 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1335 panic("invalid divmod flavour!");
1337 new_mem = be_transform_node(mem);
1339 assert(get_mode_size_bits(mode) == 32);
1341 if (mode_is_signed(mode)) {
1342 /* in signed mode, we need to sign extend the dividend */
1343 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1344 add_irn_dep(produceval, get_irg_frame(irg));
1345 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1348 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1349 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1350 add_irn_dep(sign_extension, get_irg_frame(irg));
1353 if (mode_is_signed(mode)) {
1354 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1355 new_dividend, sign_extension, new_divisor);
1357 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1358 new_dividend, sign_extension, new_divisor);
1361 set_ia32_exc_label(res, has_exc);
1362 set_irn_pinned(res, get_irn_pinned(node));
1364 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1371 * Wrapper for generate_DivMod. Sets flavour_Mod.
1374 static ir_node *gen_Mod(ir_node *node) {
1375 return generate_DivMod(node, get_Mod_left(node),
1376 get_Mod_right(node), flavour_Mod);
1380 * Wrapper for generate_DivMod. Sets flavour_Div.
1383 static ir_node *gen_Div(ir_node *node) {
1384 return generate_DivMod(node, get_Div_left(node),
1385 get_Div_right(node), flavour_Div);
1389 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1391 static ir_node *gen_DivMod(ir_node *node) {
1392 return generate_DivMod(node, get_DivMod_left(node),
1393 get_DivMod_right(node), flavour_DivMod);
1399 * Creates an ia32 floating Div.
1401 * @return The created ia32 xDiv node
1403 static ir_node *gen_Quot(ir_node *node)
1405 ir_node *op1 = get_Quot_left(node);
1406 ir_node *op2 = get_Quot_right(node);
1408 if (USE_SSE2(env_cg)) {
1409 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1411 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1417 * Creates an ia32 Shl.
1419 * @return The created ia32 Shl node
1421 static ir_node *gen_Shl(ir_node *node) {
1422 ir_node *left = get_Shl_left(node);
1423 ir_node *right = get_Shl_right(node);
1425 left = ia32_skip_downconv(left);
1426 return gen_shift_binop(node, left, right, new_rd_ia32_Shl);
1432 * Creates an ia32 Shr.
1434 * @return The created ia32 Shr node
1436 static ir_node *gen_Shr(ir_node *node) {
1437 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1438 return gen_shift_binop(node, get_Shr_left(node),
1439 get_Shr_right(node), new_rd_ia32_Shr);
1445 * Creates an ia32 Sar.
1447 * @return The created ia32 Shrs node
1449 static ir_node *gen_Shrs(ir_node *node) {
1450 ir_node *left = get_Shrs_left(node);
1451 ir_node *right = get_Shrs_right(node);
1452 ir_mode *mode = get_irn_mode(node);
1454 assert(get_mode_size_bits(mode) == 32);
1456 if(is_Const(right) && mode == mode_Is) {
1457 tarval *tv = get_Const_tarval(right);
1458 long val = get_tarval_long(tv);
1460 /* this is a sign extension */
1461 ir_graph *irg = current_ir_graph;
1462 dbg_info *dbgi = get_irn_dbg_info(node);
1463 ir_node *block = be_transform_node(get_nodes_block(node));
1465 ir_node *new_op = be_transform_node(op);
1466 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1467 add_irn_dep(pval, get_irg_frame(irg));
1469 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1473 /* 8 or 16 bit sign extension? */
1474 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1475 ir_node *shl_left = get_Shl_left(left);
1476 ir_node *shl_right = get_Shl_right(left);
1477 if(is_Const(shl_right)) {
1478 tarval *tv1 = get_Const_tarval(right);
1479 tarval *tv2 = get_Const_tarval(shl_right);
1480 if(tv1 == tv2 && tarval_is_long(tv1)) {
1481 long val = get_tarval_long(tv1);
1482 if(val == 16 || val == 24) {
1483 dbg_info *dbgi = get_irn_dbg_info(node);
1484 ir_node *block = get_nodes_block(node);
1494 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1503 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1509 * Creates an ia32 RotL.
1511 * @param op1 The first operator
1512 * @param op2 The second operator
1513 * @return The created ia32 RotL node
1515 static ir_node *gen_RotL(ir_node *node,
1516 ir_node *op1, ir_node *op2) {
1517 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1518 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1524 * Creates an ia32 RotR.
1525 * NOTE: There is no RotR with immediate because this would always be a RotL
1526 * "imm-mode_size_bits" which can be pre-calculated.
1528 * @param op1 The first operator
1529 * @param op2 The second operator
1530 * @return The created ia32 RotR node
1532 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1534 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1535 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1541 * Creates an ia32 RotR or RotL (depending on the found pattern).
1543 * @return The created ia32 RotL or RotR node
1545 static ir_node *gen_Rot(ir_node *node) {
1546 ir_node *rotate = NULL;
1547 ir_node *op1 = get_Rot_left(node);
1548 ir_node *op2 = get_Rot_right(node);
1550 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1551 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1552 that means we can create a RotR instead of an Add and a RotL */
1554 if (get_irn_op(op2) == op_Add) {
1556 ir_node *left = get_Add_left(add);
1557 ir_node *right = get_Add_right(add);
1558 if (is_Const(right)) {
1559 tarval *tv = get_Const_tarval(right);
1560 ir_mode *mode = get_irn_mode(node);
1561 long bits = get_mode_size_bits(mode);
1563 if (get_irn_op(left) == op_Minus &&
1564 tarval_is_long(tv) &&
1565 get_tarval_long(tv) == bits &&
1568 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1569 rotate = gen_RotR(node, op1, get_Minus_op(left));
1574 if (rotate == NULL) {
1575 rotate = gen_RotL(node, op1, op2);
1584 * Transforms a Minus node.
1586 * @return The created ia32 Minus node
1588 static ir_node *gen_Minus(ir_node *node)
1590 ir_node *op = get_Minus_op(node);
1591 ir_node *block = be_transform_node(get_nodes_block(node));
1592 ir_graph *irg = current_ir_graph;
1593 dbg_info *dbgi = get_irn_dbg_info(node);
1594 ir_mode *mode = get_irn_mode(node);
1599 if (mode_is_float(mode)) {
1600 ir_node *new_op = be_transform_node(op);
1601 if (USE_SSE2(env_cg)) {
1602 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1603 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1604 ir_node *nomem = new_rd_NoMem(irg);
1606 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1609 size = get_mode_size_bits(mode);
1610 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1612 set_ia32_am_sc(res, ent);
1613 set_ia32_op_type(res, ia32_AddrModeS);
1614 set_ia32_ls_mode(res, mode);
1616 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1619 op = ia32_skip_downconv(op);
1620 res = gen_unop(node, op, new_rd_ia32_Neg);
1623 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1629 * Transforms a Not node.
1631 * @return The created ia32 Not node
1633 static ir_node *gen_Not(ir_node *node) {
1634 ir_node *op = get_Not_op(node);
1636 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1637 assert (! mode_is_float(get_irn_mode(node)));
1639 node = ia32_skip_downconv(node);
1640 return gen_unop(node, op, new_rd_ia32_Not);
1646 * Transforms an Abs node.
1648 * @return The created ia32 Abs node
1650 static ir_node *gen_Abs(ir_node *node)
1652 ir_node *block = be_transform_node(get_nodes_block(node));
1653 ir_node *op = get_Abs_op(node);
1654 ir_node *new_op = be_transform_node(op);
1655 ir_graph *irg = current_ir_graph;
1656 dbg_info *dbgi = get_irn_dbg_info(node);
1657 ir_mode *mode = get_irn_mode(node);
1658 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1659 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1660 ir_node *nomem = new_NoMem();
1665 if (mode_is_float(mode)) {
1666 if (USE_SSE2(env_cg)) {
1667 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1669 size = get_mode_size_bits(mode);
1670 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1672 set_ia32_am_sc(res, ent);
1674 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1676 set_ia32_op_type(res, ia32_AddrModeS);
1677 set_ia32_ls_mode(res, mode);
1679 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1680 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1684 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1685 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1688 add_irn_dep(pval, get_irg_frame(irg));
1689 SET_IA32_ORIG_NODE(sign_extension,
1690 ia32_get_old_node_name(env_cg, node));
1692 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1694 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1696 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1698 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1705 * Transforms a Load.
1707 * @return the created ia32 Load node
1709 static ir_node *gen_Load(ir_node *node) {
1710 ir_node *old_block = get_nodes_block(node);
1711 ir_node *block = be_transform_node(old_block);
1712 ir_node *ptr = get_Load_ptr(node);
1713 ir_node *mem = get_Load_mem(node);
1714 ir_node *new_mem = be_transform_node(mem);
1717 ir_graph *irg = current_ir_graph;
1718 dbg_info *dbgi = get_irn_dbg_info(node);
1719 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1720 ir_mode *mode = get_Load_mode(node);
1723 ia32_address_t addr;
1725 /* construct load address */
1726 memset(&addr, 0, sizeof(addr));
1727 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1734 base = be_transform_node(base);
1740 index = be_transform_node(index);
1743 if (mode_is_float(mode)) {
1744 if (USE_SSE2(env_cg)) {
1745 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1747 res_mode = mode_xmm;
1749 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1751 res_mode = mode_vfp;
1757 /* create a conv node with address mode for smaller modes */
1758 if(get_mode_size_bits(mode) < 32) {
1759 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1760 new_mem, noreg, mode);
1762 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1767 set_irn_pinned(new_op, get_irn_pinned(node));
1768 set_ia32_op_type(new_op, ia32_AddrModeS);
1769 set_ia32_ls_mode(new_op, mode);
1770 set_address(new_op, &addr);
1772 /* make sure we are scheduled behind the initial IncSP/Barrier
1773 * to avoid spills being placed before it
1775 if (block == get_irg_start_block(irg)) {
1776 add_irn_dep(new_op, get_irg_frame(irg));
1779 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1780 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1785 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1786 ir_node *ptr, ir_node *other)
1793 /* we only use address mode if we're the only user of the load */
1794 if(get_irn_n_edges(node) > 1)
1797 load = get_Proj_pred(node);
1800 if(get_nodes_block(load) != block)
1803 /* Store should be attached to the load */
1804 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1806 /* store should have the same pointer as the load */
1807 if(get_Load_ptr(load) != ptr)
1810 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1811 if(other != NULL && get_nodes_block(other) == block
1812 && heights_reachable_in_block(heights, other, load))
1818 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1819 ir_node *mem, ir_node *ptr, ir_mode *mode,
1820 construct_binop_dest_func *func,
1821 construct_binop_dest_func *func8bit,
1824 ir_node *src_block = get_nodes_block(node);
1826 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1827 ir_graph *irg = current_ir_graph;
1831 ia32_address_mode_t am;
1832 ia32_address_t *addr = &am.addr;
1833 memset(&am, 0, sizeof(am));
1835 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1836 build_address(&am, op1);
1837 new_op = create_immediate_or_transform(op2, 0);
1838 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1839 build_address(&am, op2);
1840 new_op = create_immediate_or_transform(op1, 0);
1845 if(addr->base == NULL)
1846 addr->base = noreg_gp;
1847 if(addr->index == NULL)
1848 addr->index = noreg_gp;
1849 if(addr->mem == NULL)
1850 addr->mem = new_NoMem();
1852 dbgi = get_irn_dbg_info(node);
1853 block = be_transform_node(src_block);
1854 if(get_mode_size_bits(mode) == 8) {
1855 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1858 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1861 set_address(new_node, addr);
1862 set_ia32_op_type(new_node, ia32_AddrModeD);
1863 set_ia32_ls_mode(new_node, mode);
1864 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1869 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1870 ir_node *ptr, ir_mode *mode,
1871 construct_unop_dest_func *func)
1873 ir_node *src_block = get_nodes_block(node);
1875 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1876 ir_graph *irg = current_ir_graph;
1879 ia32_address_mode_t am;
1880 ia32_address_t *addr = &am.addr;
1881 memset(&am, 0, sizeof(am));
1883 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1886 build_address(&am, op);
1888 if(addr->base == NULL)
1889 addr->base = noreg_gp;
1890 if(addr->index == NULL)
1891 addr->index = noreg_gp;
1892 if(addr->mem == NULL)
1893 addr->mem = new_NoMem();
1895 dbgi = get_irn_dbg_info(node);
1896 block = be_transform_node(src_block);
1897 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1898 set_address(new_node, addr);
1899 set_ia32_op_type(new_node, ia32_AddrModeD);
1900 set_ia32_ls_mode(new_node, mode);
1901 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1906 static ir_node *try_create_dest_am(ir_node *node) {
1907 ir_node *val = get_Store_value(node);
1908 ir_node *mem = get_Store_mem(node);
1909 ir_node *ptr = get_Store_ptr(node);
1910 ir_mode *mode = get_irn_mode(val);
1915 /* handle only GP modes for now... */
1916 if(!mode_needs_gp_reg(mode))
1919 /* store must be the only user of the val node */
1920 if(get_irn_n_edges(val) > 1)
1923 switch(get_irn_opcode(val)) {
1925 op1 = get_Add_left(val);
1926 op2 = get_Add_right(val);
1927 if(is_Const_1(op2)) {
1928 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1929 new_rd_ia32_IncMem);
1931 } else if(is_Const_Minus_1(op2)) {
1932 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1933 new_rd_ia32_DecMem);
1936 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1937 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1940 op1 = get_Sub_left(val);
1941 op2 = get_Sub_right(val);
1943 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1946 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1947 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1950 op1 = get_And_left(val);
1951 op2 = get_And_right(val);
1952 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1953 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1956 op1 = get_Or_left(val);
1957 op2 = get_Or_right(val);
1958 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1959 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1962 op1 = get_Eor_left(val);
1963 op2 = get_Eor_right(val);
1964 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1965 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1968 op1 = get_Shl_left(val);
1969 op2 = get_Shl_right(val);
1970 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1971 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1974 op1 = get_Shr_left(val);
1975 op2 = get_Shr_right(val);
1976 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1977 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1980 op1 = get_Shrs_left(val);
1981 op2 = get_Shrs_right(val);
1982 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1983 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1986 op1 = get_Rot_left(val);
1987 op2 = get_Rot_right(val);
1988 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1989 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1991 /* TODO: match ROR patterns... */
1993 op1 = get_Minus_op(val);
1994 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1997 /* should be lowered already */
1998 assert(mode != mode_b);
1999 op1 = get_Not_op(val);
2000 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2010 * Transforms a Store.
2012 * @return the created ia32 Store node
2014 static ir_node *gen_Store(ir_node *node) {
2015 ir_node *block = be_transform_node(get_nodes_block(node));
2016 ir_node *ptr = get_Store_ptr(node);
2019 ir_node *val = get_Store_value(node);
2021 ir_node *mem = get_Store_mem(node);
2022 ir_node *new_mem = be_transform_node(mem);
2023 ir_graph *irg = current_ir_graph;
2024 dbg_info *dbgi = get_irn_dbg_info(node);
2025 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2026 ir_mode *mode = get_irn_mode(val);
2028 ia32_address_t addr;
2030 /* check for destination address mode */
2031 new_op = try_create_dest_am(node);
2035 /* construct store address */
2036 memset(&addr, 0, sizeof(addr));
2037 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2044 base = be_transform_node(base);
2050 index = be_transform_node(index);
2053 if (mode_is_float(mode)) {
2054 /* convs (and strict-convs) before stores are unnecessary if the mode
2056 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2057 val = get_Conv_op(val);
2059 new_val = be_transform_node(val);
2060 if (USE_SSE2(env_cg)) {
2061 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
2064 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
2068 new_val = create_immediate_or_transform(val, 0);
2072 if (get_mode_size_bits(mode) == 8) {
2073 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
2076 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
2081 set_irn_pinned(new_op, get_irn_pinned(node));
2082 set_ia32_op_type(new_op, ia32_AddrModeD);
2083 set_ia32_ls_mode(new_op, mode);
2085 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2086 set_address(new_op, &addr);
2087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2092 static ir_node *create_Switch(ir_node *node)
2094 ir_graph *irg = current_ir_graph;
2095 dbg_info *dbgi = get_irn_dbg_info(node);
2096 ir_node *block = be_transform_node(get_nodes_block(node));
2097 ir_node *sel = get_Cond_selector(node);
2098 ir_node *new_sel = be_transform_node(sel);
2100 int switch_min = INT_MAX;
2101 const ir_edge_t *edge;
2103 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2105 /* determine the smallest switch case value */
2106 foreach_out_edge(node, edge) {
2107 ir_node *proj = get_edge_src_irn(edge);
2108 int pn = get_Proj_proj(proj);
2113 if (switch_min != 0) {
2114 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2116 /* if smallest switch case is not 0 we need an additional sub */
2117 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2118 add_ia32_am_offs_int(new_sel, -switch_min);
2119 set_ia32_op_type(new_sel, ia32_AddrModeS);
2121 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2124 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2125 set_ia32_pncode(res, get_Cond_defaultProj(node));
2127 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2132 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2134 ir_graph *irg = current_ir_graph;
2142 /* we have a Cmp as input */
2144 ir_node *pred = get_Proj_pred(node);
2146 flags = be_transform_node(pred);
2147 *pnc_out = get_Proj_proj(node);
2152 /* a mode_b value, we have to compare it against 0 */
2153 dbgi = get_irn_dbg_info(node);
2154 new_block = be_transform_node(get_nodes_block(node));
2155 new_op = be_transform_node(node);
2156 noreg = ia32_new_NoReg_gp(env_cg);
2157 nomem = new_NoMem();
2158 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2159 new_op, new_op, 0, 0);
2160 *pnc_out = pn_Cmp_Lg;
2164 static ir_node *gen_Cond(ir_node *node) {
2165 ir_node *block = get_nodes_block(node);
2166 ir_node *new_block = be_transform_node(block);
2167 ir_graph *irg = current_ir_graph;
2168 dbg_info *dbgi = get_irn_dbg_info(node);
2169 ir_node *sel = get_Cond_selector(node);
2170 ir_mode *sel_mode = get_irn_mode(sel);
2172 ir_node *flags = NULL;
2175 if (sel_mode != mode_b) {
2176 return create_Switch(node);
2179 /* we get flags from a cmp */
2180 flags = get_flags_node(sel, &pnc);
2182 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2183 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2191 * Transforms a CopyB node.
2193 * @return The transformed node.
2195 static ir_node *gen_CopyB(ir_node *node) {
2196 ir_node *block = be_transform_node(get_nodes_block(node));
2197 ir_node *src = get_CopyB_src(node);
2198 ir_node *new_src = be_transform_node(src);
2199 ir_node *dst = get_CopyB_dst(node);
2200 ir_node *new_dst = be_transform_node(dst);
2201 ir_node *mem = get_CopyB_mem(node);
2202 ir_node *new_mem = be_transform_node(mem);
2203 ir_node *res = NULL;
2204 ir_graph *irg = current_ir_graph;
2205 dbg_info *dbgi = get_irn_dbg_info(node);
2206 int size = get_type_size_bytes(get_CopyB_type(node));
2209 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2210 /* then we need the size explicitly in ECX. */
2211 if (size >= 32 * 4) {
2212 rem = size & 0x3; /* size % 4 */
2215 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2217 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2219 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2221 add_irn_dep(res, get_irg_frame(irg));
2223 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2224 /* we misuse the pncode field for the copyb size */
2225 set_ia32_pncode(res, rem);
2227 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2228 set_ia32_pncode(res, size);
2231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2236 static ir_node *gen_be_Copy(ir_node *node)
2238 ir_node *result = be_duplicate_node(node);
2239 ir_mode *mode = get_irn_mode(result);
2241 if (mode_needs_gp_reg(mode)) {
2242 set_irn_mode(result, mode_Iu);
2249 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2250 * to fold an and into a test node
2252 static int can_fold_test_and(ir_node *node)
2254 const ir_edge_t *edge;
2256 /** we can only have eq and lg projs */
2257 foreach_out_edge(node, edge) {
2258 ir_node *proj = get_edge_src_irn(edge);
2259 pn_Cmp pnc = get_Proj_proj(proj);
2260 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2267 static ir_node *try_create_Test(ir_node *node)
2269 ir_graph *irg = current_ir_graph;
2270 dbg_info *dbgi = get_irn_dbg_info(node);
2271 ir_node *block = get_nodes_block(node);
2272 ir_node *new_block = be_transform_node(block);
2273 ir_node *cmp_left = get_Cmp_left(node);
2274 ir_node *cmp_right = get_Cmp_right(node);
2279 ia32_address_mode_t am;
2280 ia32_address_t *addr = &am.addr;
2283 /* can we use a test instruction? */
2284 if(!is_Const_0(cmp_right))
2287 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2288 can_fold_test_and(node)) {
2289 ir_node *and_left = get_And_left(cmp_left);
2290 ir_node *and_right = get_And_right(cmp_left);
2292 mode = get_irn_mode(and_left);
2296 mode = get_irn_mode(cmp_left);
2301 assert(get_mode_size_bits(mode) <= 32);
2303 match_arguments(&am, block, left, right, match_commutative |
2304 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2306 cmp_unsigned = !mode_is_signed(mode);
2307 if(get_mode_size_bits(mode) == 8) {
2308 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2309 addr->index, addr->mem, am.new_op1,
2310 am.new_op2, am.ins_permuted, cmp_unsigned);
2312 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2313 addr->mem, am.new_op1, am.new_op2,
2314 am.ins_permuted, cmp_unsigned);
2316 set_am_attributes(res, &am);
2317 assert(mode != NULL);
2318 set_ia32_ls_mode(res, mode);
2320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2322 res = fix_mem_proj(res, &am);
2326 static ir_node *create_Fucom(ir_node *node)
2328 ir_graph *irg = current_ir_graph;
2329 dbg_info *dbgi = get_irn_dbg_info(node);
2330 ir_node *block = get_nodes_block(node);
2331 ir_node *new_block = be_transform_node(block);
2332 ir_node *left = get_Cmp_left(node);
2333 ir_node *new_left = be_transform_node(left);
2334 ir_node *right = get_Cmp_right(node);
2338 if(transform_config.use_fucomi) {
2339 new_right = be_transform_node(right);
2340 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2341 set_ia32_commutative(res);
2342 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2344 if(transform_config.use_ftst && is_Const_null(right)) {
2345 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2347 new_right = be_transform_node(right);
2348 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2352 set_ia32_commutative(res);
2354 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2356 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2357 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2363 static ir_node *create_Ucomi(ir_node *node)
2365 ir_graph *irg = current_ir_graph;
2366 dbg_info *dbgi = get_irn_dbg_info(node);
2367 ir_node *src_block = get_nodes_block(node);
2368 ir_node *new_block = be_transform_node(src_block);
2369 ir_node *left = get_Cmp_left(node);
2370 ir_node *right = get_Cmp_right(node);
2372 ia32_address_mode_t am;
2373 ia32_address_t *addr = &am.addr;
2375 match_arguments(&am, src_block, left, right, match_commutative);
2377 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2378 addr->mem, am.new_op1, am.new_op2,
2380 set_am_attributes(new_node, &am);
2382 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2384 new_node = fix_mem_proj(new_node, &am);
2389 static ir_node *gen_Cmp(ir_node *node)
2391 ir_graph *irg = current_ir_graph;
2392 dbg_info *dbgi = get_irn_dbg_info(node);
2393 ir_node *block = get_nodes_block(node);
2394 ir_node *new_block = be_transform_node(block);
2395 ir_node *left = get_Cmp_left(node);
2396 ir_node *right = get_Cmp_right(node);
2397 ir_mode *cmp_mode = get_irn_mode(left);
2399 ia32_address_mode_t am;
2400 ia32_address_t *addr = &am.addr;
2403 if(mode_is_float(cmp_mode)) {
2404 if (USE_SSE2(env_cg)) {
2405 return create_Ucomi(node);
2407 return create_Fucom(node);
2411 assert(mode_needs_gp_reg(cmp_mode));
2413 /* we prefer the Test instruction where possible except cases where
2414 * we can use SourceAM */
2415 if(!ia32_use_source_address_mode(block, left, right) &&
2416 !ia32_use_source_address_mode(block, right, left)) {
2417 res = try_create_Test(node);
2422 match_arguments(&am, block, left, right,
2423 match_commutative | match_8_bit_am | match_16_bit_am |
2424 match_am_and_immediates);
2426 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2427 if(get_mode_size_bits(cmp_mode) == 8) {
2428 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2429 addr->mem, am.new_op1, am.new_op2,
2430 am.ins_permuted, cmp_unsigned);
2432 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2433 addr->mem, am.new_op1, am.new_op2,
2434 am.ins_permuted, cmp_unsigned);
2436 set_am_attributes(res, &am);
2437 assert(cmp_mode != NULL);
2438 set_ia32_ls_mode(res, cmp_mode);
2440 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2442 res = fix_mem_proj(res, &am);
2447 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2449 ir_graph *irg = current_ir_graph;
2450 dbg_info *dbgi = get_irn_dbg_info(node);
2451 ir_node *block = get_nodes_block(node);
2452 ir_node *new_block = be_transform_node(block);
2453 ir_node *val_true = get_Psi_val(node, 0);
2454 ir_node *val_false = get_Psi_default(node);
2456 match_flags_t match_flags;
2457 ia32_address_mode_t am;
2458 ia32_address_t *addr;
2460 assert(transform_config.use_cmov);
2461 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2465 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2466 | match_force_32bit_op;
2468 match_arguments(&am, block, val_false, val_true, match_flags);
2470 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2471 addr->mem, am.new_op1, am.new_op2, new_flags,
2472 am.ins_permuted, pnc);
2473 set_am_attributes(new_node, &am);
2475 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2477 new_node = fix_mem_proj(new_node, &am);
2484 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2485 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2488 ir_graph *irg = current_ir_graph;
2489 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2490 ir_node *nomem = new_NoMem();
2493 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2494 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2495 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2496 nomem, res, mode_Bu);
2497 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2504 * Transforms a Psi node into CMov.
2506 * @return The transformed node.
2508 static ir_node *gen_Psi(ir_node *node)
2510 dbg_info *dbgi = get_irn_dbg_info(node);
2511 ir_node *block = get_nodes_block(node);
2512 ir_node *new_block = be_transform_node(block);
2513 ir_node *psi_true = get_Psi_val(node, 0);
2514 ir_node *psi_default = get_Psi_default(node);
2515 ir_node *cond = get_Psi_cond(node, 0);
2516 ir_node *flags = NULL;
2520 assert(get_Psi_n_conds(node) == 1);
2521 assert(get_irn_mode(cond) == mode_b);
2522 assert(mode_needs_gp_reg(get_irn_mode(node)));
2524 flags = get_flags_node(cond, &pnc);
2526 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2527 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2528 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2529 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2531 res = create_CMov(node, flags, pnc);
2538 * Create a conversion from x87 state register to general purpose.
2540 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2541 ir_node *block = be_transform_node(get_nodes_block(node));
2542 ir_node *op = get_Conv_op(node);
2543 ir_node *new_op = be_transform_node(op);
2544 ia32_code_gen_t *cg = env_cg;
2545 ir_graph *irg = current_ir_graph;
2546 dbg_info *dbgi = get_irn_dbg_info(node);
2547 ir_node *noreg = ia32_new_NoReg_gp(cg);
2548 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2549 ir_mode *mode = get_irn_mode(node);
2550 ir_node *fist, *load;
2553 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2554 new_NoMem(), new_op, trunc_mode);
2556 set_irn_pinned(fist, op_pin_state_floats);
2557 set_ia32_use_frame(fist);
2558 set_ia32_op_type(fist, ia32_AddrModeD);
2560 assert(get_mode_size_bits(mode) <= 32);
2561 /* exception we can only store signed 32 bit integers, so for unsigned
2562 we store a 64bit (signed) integer and load the lower bits */
2563 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2564 set_ia32_ls_mode(fist, mode_Ls);
2566 set_ia32_ls_mode(fist, mode_Is);
2568 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2571 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2573 set_irn_pinned(load, op_pin_state_floats);
2574 set_ia32_use_frame(load);
2575 set_ia32_op_type(load, ia32_AddrModeS);
2576 set_ia32_ls_mode(load, mode_Is);
2577 if(get_ia32_ls_mode(fist) == mode_Ls) {
2578 ia32_attr_t *attr = get_ia32_attr(load);
2579 attr->data.need_64bit_stackent = 1;
2581 ia32_attr_t *attr = get_ia32_attr(load);
2582 attr->data.need_32bit_stackent = 1;
2584 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2586 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2590 * Creates a x87 strict Conv by placing a Sore and a Load
2592 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2594 ir_node *block = get_nodes_block(node);
2595 ir_graph *irg = current_ir_graph;
2596 dbg_info *dbgi = get_irn_dbg_info(node);
2597 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2598 ir_node *nomem = new_NoMem();
2599 ir_node *frame = get_irg_frame(irg);
2600 ir_node *store, *load;
2603 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2605 set_ia32_use_frame(store);
2606 set_ia32_op_type(store, ia32_AddrModeD);
2607 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2609 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2611 set_ia32_use_frame(load);
2612 set_ia32_op_type(load, ia32_AddrModeS);
2613 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2615 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2619 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2621 ir_graph *irg = current_ir_graph;
2622 ir_node *start_block = get_irg_start_block(irg);
2623 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2624 symconst, symconst_sign, val);
2625 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2631 * Create a conversion from general purpose to x87 register
2633 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2634 ir_node *src_block = get_nodes_block(node);
2635 ir_node *block = be_transform_node(src_block);
2636 ir_graph *irg = current_ir_graph;
2637 dbg_info *dbgi = get_irn_dbg_info(node);
2638 ir_node *op = get_Conv_op(node);
2643 ir_mode *store_mode;
2649 /* fild can use source AM if the operand is a signed 32bit integer */
2650 if (src_mode == mode_Is) {
2651 ia32_address_mode_t am;
2653 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2654 if (am.op_type == ia32_AddrModeS) {
2655 ia32_address_t *addr = &am.addr;
2657 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2658 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2660 set_am_attributes(fild, &am);
2661 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2663 fix_mem_proj(fild, &am);
2667 new_op = am.new_op2;
2669 new_op = be_transform_node(op);
2672 noreg = ia32_new_NoReg_gp(env_cg);
2673 nomem = new_NoMem();
2674 mode = get_irn_mode(op);
2676 /* first convert to 32 bit signed if necessary */
2677 src_bits = get_mode_size_bits(src_mode);
2678 if (src_bits == 8) {
2679 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2681 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2683 } else if (src_bits < 32) {
2684 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2686 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2690 assert(get_mode_size_bits(mode) == 32);
2693 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2696 set_ia32_use_frame(store);
2697 set_ia32_op_type(store, ia32_AddrModeD);
2698 set_ia32_ls_mode(store, mode_Iu);
2700 /* exception for 32bit unsigned, do a 64bit spill+load */
2701 if(!mode_is_signed(mode)) {
2704 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2706 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2707 get_irg_frame(irg), noreg, nomem,
2710 set_ia32_use_frame(zero_store);
2711 set_ia32_op_type(zero_store, ia32_AddrModeD);
2712 add_ia32_am_offs_int(zero_store, 4);
2713 set_ia32_ls_mode(zero_store, mode_Iu);
2718 store = new_rd_Sync(dbgi, irg, block, 2, in);
2719 store_mode = mode_Ls;
2721 store_mode = mode_Is;
2725 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2727 set_ia32_use_frame(fild);
2728 set_ia32_op_type(fild, ia32_AddrModeS);
2729 set_ia32_ls_mode(fild, store_mode);
2731 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2737 * Create a conversion from one integer mode into another one
2739 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2740 dbg_info *dbgi, ir_node *block, ir_node *op,
2743 ir_graph *irg = current_ir_graph;
2744 int src_bits = get_mode_size_bits(src_mode);
2745 int tgt_bits = get_mode_size_bits(tgt_mode);
2746 ir_node *new_block = be_transform_node(block);
2748 ir_mode *smaller_mode;
2750 ia32_address_mode_t am;
2751 ia32_address_t *addr = &am.addr;
2753 if (src_bits < tgt_bits) {
2754 smaller_mode = src_mode;
2755 smaller_bits = src_bits;
2757 smaller_mode = tgt_mode;
2758 smaller_bits = tgt_bits;
2761 match_arguments(&am, block, NULL, op, match_8_bit_am | match_16_bit_am);
2762 if (smaller_bits == 8 && am.op_type == ia32_Normal) {
2763 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2764 addr->index, addr->mem, am.new_op2,
2767 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2768 addr->index, addr->mem, am.new_op2,
2771 set_am_attributes(res, &am);
2772 set_ia32_ls_mode(res, smaller_mode);
2773 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2774 res = fix_mem_proj(res, &am);
2779 * Transforms a Conv node.
2781 * @return The created ia32 Conv node
2783 static ir_node *gen_Conv(ir_node *node) {
2784 ir_node *block = get_nodes_block(node);
2785 ir_node *new_block = be_transform_node(block);
2786 ir_node *op = get_Conv_op(node);
2787 ir_node *new_op = NULL;
2788 ir_graph *irg = current_ir_graph;
2789 dbg_info *dbgi = get_irn_dbg_info(node);
2790 ir_mode *src_mode = get_irn_mode(op);
2791 ir_mode *tgt_mode = get_irn_mode(node);
2792 int src_bits = get_mode_size_bits(src_mode);
2793 int tgt_bits = get_mode_size_bits(tgt_mode);
2794 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2795 ir_node *nomem = new_rd_NoMem(irg);
2796 ir_node *res = NULL;
2798 if (src_mode == mode_b) {
2799 assert(mode_is_int(tgt_mode));
2800 /* nothing to do, we already model bools as 0/1 ints */
2801 return be_transform_node(op);
2804 if (src_mode == tgt_mode) {
2805 if (get_Conv_strict(node)) {
2806 if (USE_SSE2(env_cg)) {
2807 /* when we are in SSE mode, we can kill all strict no-op conversion */
2808 return be_transform_node(op);
2811 /* this should be optimized already, but who knows... */
2812 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2813 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2814 return be_transform_node(op);
2818 if (mode_is_float(src_mode)) {
2819 new_op = be_transform_node(op);
2820 /* we convert from float ... */
2821 if (mode_is_float(tgt_mode)) {
2822 if(src_mode == mode_E && tgt_mode == mode_D
2823 && !get_Conv_strict(node)) {
2824 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2829 if (USE_SSE2(env_cg)) {
2830 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2831 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2833 set_ia32_ls_mode(res, tgt_mode);
2835 if(get_Conv_strict(node)) {
2836 res = gen_x87_strict_conv(tgt_mode, new_op);
2837 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2840 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2845 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2846 if (USE_SSE2(env_cg)) {
2847 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2849 set_ia32_ls_mode(res, src_mode);
2851 return gen_x87_fp_to_gp(node);
2855 /* we convert from int ... */
2856 if (mode_is_float(tgt_mode)) {
2858 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2859 if (USE_SSE2(env_cg)) {
2860 new_op = be_transform_node(op);
2861 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2863 set_ia32_ls_mode(res, tgt_mode);
2865 res = gen_x87_gp_to_fp(node, src_mode);
2866 if(get_Conv_strict(node)) {
2867 res = gen_x87_strict_conv(tgt_mode, res);
2868 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2869 ia32_get_old_node_name(env_cg, node));
2873 } else if(tgt_mode == mode_b) {
2874 /* mode_b lowering already took care that we only have 0/1 values */
2875 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2876 src_mode, tgt_mode));
2877 return be_transform_node(op);
2880 if (src_bits == tgt_bits) {
2881 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2882 src_mode, tgt_mode));
2883 return be_transform_node(op);
2886 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2894 static int check_immediate_constraint(long val, char immediate_constraint_type)
2896 switch (immediate_constraint_type) {
2900 return val >= 0 && val <= 32;
2902 return val >= 0 && val <= 63;
2904 return val >= -128 && val <= 127;
2906 return val == 0xff || val == 0xffff;
2908 return val >= 0 && val <= 3;
2910 return val >= 0 && val <= 255;
2912 return val >= 0 && val <= 127;
2916 panic("Invalid immediate constraint found");
2920 static ir_node *try_create_Immediate(ir_node *node,
2921 char immediate_constraint_type)
2924 tarval *offset = NULL;
2925 int offset_sign = 0;
2927 ir_entity *symconst_ent = NULL;
2928 int symconst_sign = 0;
2930 ir_node *cnst = NULL;
2931 ir_node *symconst = NULL;
2934 mode = get_irn_mode(node);
2935 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2939 if(is_Minus(node)) {
2941 node = get_Minus_op(node);
2944 if(is_Const(node)) {
2947 offset_sign = minus;
2948 } else if(is_SymConst(node)) {
2951 symconst_sign = minus;
2952 } else if(is_Add(node)) {
2953 ir_node *left = get_Add_left(node);
2954 ir_node *right = get_Add_right(node);
2955 if(is_Const(left) && is_SymConst(right)) {
2958 symconst_sign = minus;
2959 offset_sign = minus;
2960 } else if(is_SymConst(left) && is_Const(right)) {
2963 symconst_sign = minus;
2964 offset_sign = minus;
2966 } else if(is_Sub(node)) {
2967 ir_node *left = get_Sub_left(node);
2968 ir_node *right = get_Sub_right(node);
2969 if(is_Const(left) && is_SymConst(right)) {
2972 symconst_sign = !minus;
2973 offset_sign = minus;
2974 } else if(is_SymConst(left) && is_Const(right)) {
2977 symconst_sign = minus;
2978 offset_sign = !minus;
2985 offset = get_Const_tarval(cnst);
2986 if(tarval_is_long(offset)) {
2987 val = get_tarval_long(offset);
2989 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2994 if(!check_immediate_constraint(val, immediate_constraint_type))
2997 if(symconst != NULL) {
2998 if(immediate_constraint_type != 0) {
2999 /* we need full 32bits for symconsts */
3003 /* unfortunately the assembler/linker doesn't support -symconst */
3007 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3009 symconst_ent = get_SymConst_entity(symconst);
3011 if(cnst == NULL && symconst == NULL)
3014 if(offset_sign && offset != NULL) {
3015 offset = tarval_neg(offset);
3018 res = create_Immediate(symconst_ent, symconst_sign, val);
3023 static ir_node *create_immediate_or_transform(ir_node *node,
3024 char immediate_constraint_type)
3026 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3027 if (new_node == NULL) {
3028 new_node = be_transform_node(node);
3033 static const arch_register_req_t no_register_req = {
3034 arch_register_req_type_none,
3035 NULL, /* regclass */
3036 NULL, /* limit bitset */
3037 { -1, -1 }, /* same pos */
3038 -1 /* different pos */
3042 * An assembler constraint.
3044 typedef struct constraint_t constraint_t;
3045 struct constraint_t {
3048 const arch_register_req_t **out_reqs;
3050 const arch_register_req_t *req;
3051 unsigned immediate_possible;
3052 char immediate_type;
3055 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3057 int immediate_possible = 0;
3058 char immediate_type = 0;
3059 unsigned limited = 0;
3060 const arch_register_class_t *cls = NULL;
3061 ir_graph *irg = current_ir_graph;
3062 struct obstack *obst = get_irg_obstack(irg);
3063 arch_register_req_t *req;
3064 unsigned *limited_ptr;
3068 /* TODO: replace all the asserts with nice error messages */
3071 /* a memory constraint: no need to do anything in backend about it
3072 * (the dependencies are already respected by the memory edge of
3074 constraint->req = &no_register_req;
3086 assert(cls == NULL ||
3087 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3088 cls = &ia32_reg_classes[CLASS_ia32_gp];
3089 limited |= 1 << REG_EAX;
3092 assert(cls == NULL ||
3093 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3094 cls = &ia32_reg_classes[CLASS_ia32_gp];
3095 limited |= 1 << REG_EBX;
3098 assert(cls == NULL ||
3099 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3100 cls = &ia32_reg_classes[CLASS_ia32_gp];
3101 limited |= 1 << REG_ECX;
3104 assert(cls == NULL ||
3105 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3106 cls = &ia32_reg_classes[CLASS_ia32_gp];
3107 limited |= 1 << REG_EDX;
3110 assert(cls == NULL ||
3111 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3112 cls = &ia32_reg_classes[CLASS_ia32_gp];
3113 limited |= 1 << REG_EDI;
3116 assert(cls == NULL ||
3117 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3118 cls = &ia32_reg_classes[CLASS_ia32_gp];
3119 limited |= 1 << REG_ESI;
3122 case 'q': /* q means lower part of the regs only, this makes no
3123 * difference to Q for us (we only assigne whole registers) */
3124 assert(cls == NULL ||
3125 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3126 cls = &ia32_reg_classes[CLASS_ia32_gp];
3127 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3131 assert(cls == NULL ||
3132 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3133 cls = &ia32_reg_classes[CLASS_ia32_gp];
3134 limited |= 1 << REG_EAX | 1 << REG_EDX;
3137 assert(cls == NULL ||
3138 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3139 cls = &ia32_reg_classes[CLASS_ia32_gp];
3140 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3141 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3148 assert(cls == NULL);
3149 cls = &ia32_reg_classes[CLASS_ia32_gp];
3155 /* TODO: mark values so the x87 simulator knows about t and u */
3156 assert(cls == NULL);
3157 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3162 assert(cls == NULL);
3163 /* TODO: check that sse2 is supported */
3164 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3174 assert(!immediate_possible);
3175 immediate_possible = 1;
3176 immediate_type = *c;
3180 assert(!immediate_possible);
3181 immediate_possible = 1;
3185 assert(!immediate_possible && cls == NULL);
3186 immediate_possible = 1;
3187 cls = &ia32_reg_classes[CLASS_ia32_gp];
3200 assert(constraint->is_in && "can only specify same constraint "
3203 sscanf(c, "%d%n", &same_as, &p);
3211 /* memory constraint no need to do anything in backend about it
3212 * (the dependencies are already respected by the memory edge of
3214 constraint->req = &no_register_req;
3217 case 'E': /* no float consts yet */
3218 case 'F': /* no float consts yet */
3219 case 's': /* makes no sense on x86 */
3220 case 'X': /* we can't support that in firm */
3223 case '<': /* no autodecrement on x86 */
3224 case '>': /* no autoincrement on x86 */
3225 case 'C': /* sse constant not supported yet */
3226 case 'G': /* 80387 constant not supported yet */
3227 case 'y': /* we don't support mmx registers yet */
3228 case 'Z': /* not available in 32 bit mode */
3229 case 'e': /* not available in 32 bit mode */
3230 panic("unsupported asm constraint '%c' found in (%+F)",
3231 *c, current_ir_graph);
3234 panic("unknown asm constraint '%c' found in (%+F)", *c,
3242 const arch_register_req_t *other_constr;
3244 assert(cls == NULL && "same as and register constraint not supported");
3245 assert(!immediate_possible && "same as and immediate constraint not "
3247 assert(same_as < constraint->n_outs && "wrong constraint number in "
3248 "same_as constraint");
3250 other_constr = constraint->out_reqs[same_as];
3252 req = obstack_alloc(obst, sizeof(req[0]));
3253 req->cls = other_constr->cls;
3254 req->type = arch_register_req_type_should_be_same;
3255 req->limited = NULL;
3256 req->other_same[0] = pos;
3257 req->other_same[1] = -1;
3258 req->other_different = -1;
3260 /* switch constraints. This is because in firm we have same_as
3261 * constraints on the output constraints while in the gcc asm syntax
3262 * they are specified on the input constraints */
3263 constraint->req = other_constr;
3264 constraint->out_reqs[same_as] = req;
3265 constraint->immediate_possible = 0;
3269 if(immediate_possible && cls == NULL) {
3270 cls = &ia32_reg_classes[CLASS_ia32_gp];
3272 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3273 assert(cls != NULL);
3275 if(immediate_possible) {
3276 assert(constraint->is_in
3277 && "immediate make no sense for output constraints");
3279 /* todo: check types (no float input on 'r' constrained in and such... */
3282 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3283 limited_ptr = (unsigned*) (req+1);
3285 req = obstack_alloc(obst, sizeof(req[0]));
3287 memset(req, 0, sizeof(req[0]));
3290 req->type = arch_register_req_type_limited;
3291 *limited_ptr = limited;
3292 req->limited = limited_ptr;
3294 req->type = arch_register_req_type_normal;
3298 constraint->req = req;
3299 constraint->immediate_possible = immediate_possible;
3300 constraint->immediate_type = immediate_type;
3303 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3310 panic("Clobbers not supported yet");
3313 static int is_memory_op(const ir_asm_constraint *constraint)
3315 ident *id = constraint->constraint;
3316 const char *str = get_id_str(id);
3319 for(c = str; *c != '\0'; ++c) {
3328 * generates code for a ASM node
3330 static ir_node *gen_ASM(ir_node *node)
3333 ir_graph *irg = current_ir_graph;
3334 ir_node *block = get_nodes_block(node);
3335 ir_node *new_block = be_transform_node(block);
3336 dbg_info *dbgi = get_irn_dbg_info(node);
3340 int n_out_constraints;
3342 const arch_register_req_t **out_reg_reqs;
3343 const arch_register_req_t **in_reg_reqs;
3344 ia32_asm_reg_t *register_map;
3345 unsigned reg_map_size = 0;
3346 struct obstack *obst;
3347 const ir_asm_constraint *in_constraints;
3348 const ir_asm_constraint *out_constraints;
3350 constraint_t parsed_constraint;
3352 arity = get_irn_arity(node);
3353 in = alloca(arity * sizeof(in[0]));
3354 memset(in, 0, arity * sizeof(in[0]));
3356 n_out_constraints = get_ASM_n_output_constraints(node);
3357 n_clobbers = get_ASM_n_clobbers(node);
3358 out_arity = n_out_constraints + n_clobbers;
3360 in_constraints = get_ASM_input_constraints(node);
3361 out_constraints = get_ASM_output_constraints(node);
3362 clobbers = get_ASM_clobbers(node);
3364 /* construct output constraints */
3365 obst = get_irg_obstack(irg);
3366 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3367 parsed_constraint.out_reqs = out_reg_reqs;
3368 parsed_constraint.n_outs = n_out_constraints;
3369 parsed_constraint.is_in = 0;
3371 for(i = 0; i < out_arity; ++i) {
3374 if(i < n_out_constraints) {
3375 const ir_asm_constraint *constraint = &out_constraints[i];
3376 c = get_id_str(constraint->constraint);
3377 parse_asm_constraint(i, &parsed_constraint, c);
3379 if(constraint->pos > reg_map_size)
3380 reg_map_size = constraint->pos;
3382 ident *glob_id = clobbers [i - n_out_constraints];
3383 c = get_id_str(glob_id);
3384 parse_clobber(node, i, &parsed_constraint, c);
3387 out_reg_reqs[i] = parsed_constraint.req;
3390 /* construct input constraints */
3391 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3392 parsed_constraint.is_in = 1;
3393 for(i = 0; i < arity; ++i) {
3394 const ir_asm_constraint *constraint = &in_constraints[i];
3395 ident *constr_id = constraint->constraint;
3396 const char *c = get_id_str(constr_id);
3398 parse_asm_constraint(i, &parsed_constraint, c);
3399 in_reg_reqs[i] = parsed_constraint.req;
3401 if(constraint->pos > reg_map_size)
3402 reg_map_size = constraint->pos;
3404 if(parsed_constraint.immediate_possible) {
3405 ir_node *pred = get_irn_n(node, i);
3406 char imm_type = parsed_constraint.immediate_type;
3407 ir_node *immediate = try_create_Immediate(pred, imm_type);
3409 if(immediate != NULL) {
3416 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3417 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3419 for(i = 0; i < n_out_constraints; ++i) {
3420 const ir_asm_constraint *constraint = &out_constraints[i];
3421 unsigned pos = constraint->pos;
3423 assert(pos < reg_map_size);
3424 register_map[pos].use_input = 0;
3425 register_map[pos].valid = 1;
3426 register_map[pos].memory = is_memory_op(constraint);
3427 register_map[pos].inout_pos = i;
3428 register_map[pos].mode = constraint->mode;
3431 /* transform inputs */
3432 for(i = 0; i < arity; ++i) {
3433 const ir_asm_constraint *constraint = &in_constraints[i];
3434 unsigned pos = constraint->pos;
3435 ir_node *pred = get_irn_n(node, i);
3436 ir_node *transformed;
3438 assert(pos < reg_map_size);
3439 register_map[pos].use_input = 1;
3440 register_map[pos].valid = 1;
3441 register_map[pos].memory = is_memory_op(constraint);
3442 register_map[pos].inout_pos = i;
3443 register_map[pos].mode = constraint->mode;
3448 transformed = be_transform_node(pred);
3449 in[i] = transformed;
3452 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3453 get_ASM_text(node), register_map);
3455 set_ia32_out_req_all(res, out_reg_reqs);
3456 set_ia32_in_req_all(res, in_reg_reqs);
3458 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3463 /********************************************
3466 * | |__ ___ _ __ ___ __| | ___ ___
3467 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3468 * | |_) | __/ | | | (_) | (_| | __/\__ \
3469 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3471 ********************************************/
3474 * Transforms a FrameAddr into an ia32 Add.
3476 static ir_node *gen_be_FrameAddr(ir_node *node) {
3477 ir_node *block = be_transform_node(get_nodes_block(node));
3478 ir_node *op = be_get_FrameAddr_frame(node);
3479 ir_node *new_op = be_transform_node(op);
3480 ir_graph *irg = current_ir_graph;
3481 dbg_info *dbgi = get_irn_dbg_info(node);
3482 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3485 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3486 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3487 set_ia32_use_frame(res);
3489 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3495 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3497 static ir_node *gen_be_Return(ir_node *node) {
3498 ir_graph *irg = current_ir_graph;
3499 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3500 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3501 ir_entity *ent = get_irg_entity(irg);
3502 ir_type *tp = get_entity_type(ent);
3507 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3508 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3511 int pn_ret_val, pn_ret_mem, arity, i;
3513 assert(ret_val != NULL);
3514 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3515 return be_duplicate_node(node);
3518 res_type = get_method_res_type(tp, 0);
3520 if (! is_Primitive_type(res_type)) {
3521 return be_duplicate_node(node);
3524 mode = get_type_mode(res_type);
3525 if (! mode_is_float(mode)) {
3526 return be_duplicate_node(node);
3529 assert(get_method_n_ress(tp) == 1);
3531 pn_ret_val = get_Proj_proj(ret_val);
3532 pn_ret_mem = get_Proj_proj(ret_mem);
3534 /* get the Barrier */
3535 barrier = get_Proj_pred(ret_val);
3537 /* get result input of the Barrier */
3538 ret_val = get_irn_n(barrier, pn_ret_val);
3539 new_ret_val = be_transform_node(ret_val);
3541 /* get memory input of the Barrier */
3542 ret_mem = get_irn_n(barrier, pn_ret_mem);
3543 new_ret_mem = be_transform_node(ret_mem);
3545 frame = get_irg_frame(irg);
3547 dbgi = get_irn_dbg_info(barrier);
3548 block = be_transform_node(get_nodes_block(barrier));
3550 noreg = ia32_new_NoReg_gp(env_cg);
3552 /* store xmm0 onto stack */
3553 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3554 new_ret_mem, new_ret_val);
3555 set_ia32_ls_mode(sse_store, mode);
3556 set_ia32_op_type(sse_store, ia32_AddrModeD);
3557 set_ia32_use_frame(sse_store);
3559 /* load into x87 register */
3560 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3561 set_ia32_op_type(fld, ia32_AddrModeS);
3562 set_ia32_use_frame(fld);
3564 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3565 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3567 /* create a new barrier */
3568 arity = get_irn_arity(barrier);
3569 in = alloca(arity * sizeof(in[0]));
3570 for (i = 0; i < arity; ++i) {
3573 if (i == pn_ret_val) {
3575 } else if (i == pn_ret_mem) {
3578 ir_node *in = get_irn_n(barrier, i);
3579 new_in = be_transform_node(in);
3584 new_barrier = new_ir_node(dbgi, irg, block,
3585 get_irn_op(barrier), get_irn_mode(barrier),
3587 copy_node_attr(barrier, new_barrier);
3588 be_duplicate_deps(barrier, new_barrier);
3589 be_set_transformed_node(barrier, new_barrier);
3590 mark_irn_visited(barrier);
3592 /* transform normally */
3593 return be_duplicate_node(node);
3597 * Transform a be_AddSP into an ia32_SubSP.
3599 static ir_node *gen_be_AddSP(ir_node *node)
3601 ir_node *src_block = get_nodes_block(node);
3602 ir_node *new_block = be_transform_node(src_block);
3603 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3604 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3605 ir_graph *irg = current_ir_graph;
3606 dbg_info *dbgi = get_irn_dbg_info(node);
3608 ia32_address_mode_t am;
3609 ia32_address_t *addr = &am.addr;
3610 match_flags_t flags = 0;
3612 match_arguments(&am, src_block, sp, sz, flags);
3614 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3615 addr->mem, am.new_op1, am.new_op2);
3616 set_am_attributes(new_node, &am);
3617 /* we can't use source address mode anymore when using immediates */
3618 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3619 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3620 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3622 new_node = fix_mem_proj(new_node, &am);
3628 * Transform a be_SubSP into an ia32_AddSP
3630 static ir_node *gen_be_SubSP(ir_node *node)
3632 ir_node *src_block = get_nodes_block(node);
3633 ir_node *new_block = be_transform_node(src_block);
3634 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3635 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3636 ir_graph *irg = current_ir_graph;
3637 dbg_info *dbgi = get_irn_dbg_info(node);
3639 ia32_address_mode_t am;
3640 ia32_address_t *addr = &am.addr;
3641 match_flags_t flags = 0;
3643 match_arguments(&am, src_block, sp, sz, flags);
3645 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3646 addr->mem, am.new_op1, am.new_op2);
3647 set_am_attributes(new_node, &am);
3648 /* we can't use source address mode anymore when using immediates */
3649 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3650 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3651 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3653 new_node = fix_mem_proj(new_node, &am);
3659 * This function just sets the register for the Unknown node
3660 * as this is not done during register allocation because Unknown
3661 * is an "ignore" node.
3663 static ir_node *gen_Unknown(ir_node *node) {
3664 ir_mode *mode = get_irn_mode(node);
3666 if (mode_is_float(mode)) {
3667 if (USE_SSE2(env_cg)) {
3668 return ia32_new_Unknown_xmm(env_cg);
3670 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3671 ir_graph *irg = current_ir_graph;
3672 dbg_info *dbgi = get_irn_dbg_info(node);
3673 ir_node *block = get_irg_start_block(irg);
3674 return new_rd_ia32_vfldz(dbgi, irg, block);
3676 } else if (mode_needs_gp_reg(mode)) {
3677 return ia32_new_Unknown_gp(env_cg);
3679 assert(0 && "unsupported Unknown-Mode");
3686 * Change some phi modes
3688 static ir_node *gen_Phi(ir_node *node) {
3689 ir_node *block = be_transform_node(get_nodes_block(node));
3690 ir_graph *irg = current_ir_graph;
3691 dbg_info *dbgi = get_irn_dbg_info(node);
3692 ir_mode *mode = get_irn_mode(node);
3695 if(mode_needs_gp_reg(mode)) {
3696 /* we shouldn't have any 64bit stuff around anymore */
3697 assert(get_mode_size_bits(mode) <= 32);
3698 /* all integer operations are on 32bit registers now */
3700 } else if(mode_is_float(mode)) {
3701 if (USE_SSE2(env_cg)) {
3708 /* phi nodes allow loops, so we use the old arguments for now
3709 * and fix this later */
3710 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3711 get_irn_in(node) + 1);
3712 copy_node_attr(node, phi);
3713 be_duplicate_deps(node, phi);
3715 be_set_transformed_node(node, phi);
3716 be_enqueue_preds(node);
3724 static ir_node *gen_IJmp(ir_node *node)
3726 ir_node *block = get_nodes_block(node);
3727 ir_node *new_block = be_transform_node(block);
3728 ir_graph *irg = current_ir_graph;
3729 dbg_info *dbgi = get_irn_dbg_info(node);
3730 ir_node *op = get_IJmp_target(node);
3732 ia32_address_mode_t am;
3733 ia32_address_t *addr = &am.addr;
3734 match_flags_t flags;
3736 flags = match_force_32bit_op | match_no_immediate;
3738 match_arguments(&am, block, NULL, op, flags);
3740 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3741 addr->mem, am.new_op2);
3742 set_am_attributes(new_node, &am);
3743 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3745 new_node = fix_mem_proj(new_node, &am);
3751 /**********************************************************************
3754 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3755 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3756 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3757 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3759 **********************************************************************/
3761 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3763 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3766 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3767 ir_node *val, ir_node *mem);
3770 * Transforms a lowered Load into a "real" one.
3772 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3774 ir_node *block = be_transform_node(get_nodes_block(node));
3775 ir_node *ptr = get_irn_n(node, 0);
3776 ir_node *new_ptr = be_transform_node(ptr);
3777 ir_node *mem = get_irn_n(node, 1);
3778 ir_node *new_mem = be_transform_node(mem);
3779 ir_graph *irg = current_ir_graph;
3780 dbg_info *dbgi = get_irn_dbg_info(node);
3781 ir_mode *mode = get_ia32_ls_mode(node);
3782 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3785 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3787 set_ia32_op_type(new_op, ia32_AddrModeS);
3788 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3789 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3790 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3791 if (is_ia32_am_sc_sign(node))
3792 set_ia32_am_sc_sign(new_op);
3793 set_ia32_ls_mode(new_op, mode);
3794 if (is_ia32_use_frame(node)) {
3795 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3796 set_ia32_use_frame(new_op);
3799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3805 * Transforms a lowered Store into a "real" one.
3807 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3809 ir_node *block = be_transform_node(get_nodes_block(node));
3810 ir_node *ptr = get_irn_n(node, 0);
3811 ir_node *new_ptr = be_transform_node(ptr);
3812 ir_node *val = get_irn_n(node, 1);
3813 ir_node *new_val = be_transform_node(val);
3814 ir_node *mem = get_irn_n(node, 2);
3815 ir_node *new_mem = be_transform_node(mem);
3816 ir_graph *irg = current_ir_graph;
3817 dbg_info *dbgi = get_irn_dbg_info(node);
3818 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3819 ir_mode *mode = get_ia32_ls_mode(node);
3823 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3825 am_offs = get_ia32_am_offs_int(node);
3826 add_ia32_am_offs_int(new_op, am_offs);
3828 set_ia32_op_type(new_op, ia32_AddrModeD);
3829 set_ia32_ls_mode(new_op, mode);
3830 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3831 set_ia32_use_frame(new_op);
3833 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3840 * Transforms an ia32_l_XXX into a "real" XXX node
3842 * @param node The node to transform
3843 * @return the created ia32 XXX node
3845 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3846 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3847 return gen_shift_binop(node, get_irn_n(node, 0), \
3848 get_irn_n(node, 1), new_rd_ia32_##op); \
3851 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3852 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3853 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3855 static ir_node *gen_ia32_l_Add(ir_node *node) {
3856 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3857 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3858 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3860 if(is_Proj(lowered)) {
3861 lowered = get_Proj_pred(lowered);
3863 assert(is_ia32_Add(lowered));
3864 set_irn_mode(lowered, mode_T);
3870 static ir_node *gen_ia32_l_Adc(ir_node *node)
3872 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3876 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3878 * @param node The node to transform
3879 * @return the created ia32 Neg node
3881 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3882 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3886 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3888 * @param node The node to transform
3889 * @return the created ia32 vfild node
3891 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3892 return gen_lowered_Load(node, new_rd_ia32_vfild);
3896 * Transforms an ia32_l_Load into a "real" ia32_Load node
3898 * @param node The node to transform
3899 * @return the created ia32 Load node
3901 static ir_node *gen_ia32_l_Load(ir_node *node) {
3902 return gen_lowered_Load(node, new_rd_ia32_Load);
3906 * Transforms an ia32_l_Store into a "real" ia32_Store node
3908 * @param node The node to transform
3909 * @return the created ia32 Store node
3911 static ir_node *gen_ia32_l_Store(ir_node *node) {
3912 return gen_lowered_Store(node, new_rd_ia32_Store);
3916 * Transforms a l_vfist into a "real" vfist node.
3918 * @param node The node to transform
3919 * @return the created ia32 vfist node
3921 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3922 ir_node *block = be_transform_node(get_nodes_block(node));
3923 ir_node *ptr = get_irn_n(node, 0);
3924 ir_node *new_ptr = be_transform_node(ptr);
3925 ir_node *val = get_irn_n(node, 1);
3926 ir_node *new_val = be_transform_node(val);
3927 ir_node *mem = get_irn_n(node, 2);
3928 ir_node *new_mem = be_transform_node(mem);
3929 ir_graph *irg = current_ir_graph;
3930 dbg_info *dbgi = get_irn_dbg_info(node);
3931 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3932 ir_mode *mode = get_ia32_ls_mode(node);
3933 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3937 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3938 new_val, trunc_mode);
3940 am_offs = get_ia32_am_offs_int(node);
3941 add_ia32_am_offs_int(new_op, am_offs);
3943 set_ia32_op_type(new_op, ia32_AddrModeD);
3944 set_ia32_ls_mode(new_op, mode);
3945 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3946 set_ia32_use_frame(new_op);
3948 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3954 * Transforms a l_MulS into a "real" MulS node.
3956 * @return the created ia32 Mul node
3958 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3959 ir_node *left = get_binop_left(node);
3960 ir_node *right = get_binop_right(node);
3962 return gen_binop(node, left, right, new_rd_ia32_Mul,
3963 match_commutative | match_no_immediate);
3967 * Transforms a l_IMulS into a "real" IMul1OPS node.
3969 * @return the created ia32 IMul1OP node
3971 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3972 ir_node *left = get_binop_left(node);
3973 ir_node *right = get_binop_right(node);
3975 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3976 match_commutative | match_no_immediate);
3979 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3980 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3981 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3982 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3984 if(is_Proj(lowered)) {
3985 lowered = get_Proj_pred(lowered);
3987 assert(is_ia32_Sub(lowered));
3988 set_irn_mode(lowered, mode_T);
3994 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3995 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
3999 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4000 * op1 - target to be shifted
4001 * op2 - contains bits to be shifted into target
4003 * Only op3 can be an immediate.
4005 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
4006 ir_node *op2, ir_node *count)
4008 ir_node *block = be_transform_node(get_nodes_block(node));
4009 ir_node *new_op = NULL;
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = get_irn_dbg_info(node);
4012 ir_node *new_op1 = be_transform_node(op1);
4013 ir_node *new_op2 = be_transform_node(op2);
4014 ir_node *new_count = create_immediate_or_transform(count, 'I');
4016 /* TODO proper AM support */
4018 if (is_ia32_l_ShlD(node))
4019 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
4021 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
4023 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4028 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
4029 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4030 get_irn_n(node, 1), get_irn_n(node, 2));
4033 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
4034 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4035 get_irn_n(node, 1), get_irn_n(node, 2));
4039 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4041 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4042 ir_node *block = be_transform_node(get_nodes_block(node));
4043 ir_node *val = get_irn_n(node, 1);
4044 ir_node *new_val = be_transform_node(val);
4045 ia32_code_gen_t *cg = env_cg;
4046 ir_node *res = NULL;
4047 ir_graph *irg = current_ir_graph;
4049 ir_node *noreg, *new_ptr, *new_mem;
4056 mem = get_irn_n(node, 2);
4057 new_mem = be_transform_node(mem);
4058 ptr = get_irn_n(node, 0);
4059 new_ptr = be_transform_node(ptr);
4060 noreg = ia32_new_NoReg_gp(cg);
4061 dbgi = get_irn_dbg_info(node);
4063 /* Store x87 -> MEM */
4064 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4065 get_ia32_ls_mode(node));
4066 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4067 set_ia32_use_frame(res);
4068 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4069 set_ia32_op_type(res, ia32_AddrModeD);
4071 /* Load MEM -> SSE */
4072 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4073 get_ia32_ls_mode(node));
4074 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4075 set_ia32_use_frame(res);
4076 set_ia32_op_type(res, ia32_AddrModeS);
4077 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4083 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4085 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4086 ir_node *block = be_transform_node(get_nodes_block(node));
4087 ir_node *val = get_irn_n(node, 1);
4088 ir_node *new_val = be_transform_node(val);
4089 ia32_code_gen_t *cg = env_cg;
4090 ir_graph *irg = current_ir_graph;
4091 ir_node *res = NULL;
4092 ir_entity *fent = get_ia32_frame_ent(node);
4093 ir_mode *lsmode = get_ia32_ls_mode(node);
4095 ir_node *noreg, *new_ptr, *new_mem;
4099 if (! USE_SSE2(cg)) {
4100 /* SSE unit is not used -> skip this node. */
4104 ptr = get_irn_n(node, 0);
4105 new_ptr = be_transform_node(ptr);
4106 mem = get_irn_n(node, 2);
4107 new_mem = be_transform_node(mem);
4108 noreg = ia32_new_NoReg_gp(cg);
4109 dbgi = get_irn_dbg_info(node);
4111 /* Store SSE -> MEM */
4112 if (is_ia32_xLoad(skip_Proj(new_val))) {
4113 ir_node *ld = skip_Proj(new_val);
4115 /* we can vfld the value directly into the fpu */
4116 fent = get_ia32_frame_ent(ld);
4117 ptr = get_irn_n(ld, 0);
4118 offs = get_ia32_am_offs_int(ld);
4120 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4122 set_ia32_frame_ent(res, fent);
4123 set_ia32_use_frame(res);
4124 set_ia32_ls_mode(res, lsmode);
4125 set_ia32_op_type(res, ia32_AddrModeD);
4129 /* Load MEM -> x87 */
4130 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4131 set_ia32_frame_ent(res, fent);
4132 set_ia32_use_frame(res);
4133 add_ia32_am_offs_int(res, offs);
4134 set_ia32_op_type(res, ia32_AddrModeS);
4135 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4140 /*********************************************************
4143 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4144 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4145 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4146 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4148 *********************************************************/
4151 * the BAD transformer.
4153 static ir_node *bad_transform(ir_node *node) {
4154 panic("No transform function for %+F available.\n", node);
4159 * Transform the Projs of an AddSP.
4161 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4162 ir_node *block = be_transform_node(get_nodes_block(node));
4163 ir_node *pred = get_Proj_pred(node);
4164 ir_node *new_pred = be_transform_node(pred);
4165 ir_graph *irg = current_ir_graph;
4166 dbg_info *dbgi = get_irn_dbg_info(node);
4167 long proj = get_Proj_proj(node);
4169 if (proj == pn_be_AddSP_sp) {
4170 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4171 pn_ia32_SubSP_stack);
4172 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4174 } else if(proj == pn_be_AddSP_res) {
4175 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4176 pn_ia32_SubSP_addr);
4177 } else if (proj == pn_be_AddSP_M) {
4178 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4182 return new_rd_Unknown(irg, get_irn_mode(node));
4186 * Transform the Projs of a SubSP.
4188 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4189 ir_node *block = be_transform_node(get_nodes_block(node));
4190 ir_node *pred = get_Proj_pred(node);
4191 ir_node *new_pred = be_transform_node(pred);
4192 ir_graph *irg = current_ir_graph;
4193 dbg_info *dbgi = get_irn_dbg_info(node);
4194 long proj = get_Proj_proj(node);
4196 if (proj == pn_be_SubSP_sp) {
4197 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4198 pn_ia32_AddSP_stack);
4199 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4201 } else if (proj == pn_be_SubSP_M) {
4202 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4206 return new_rd_Unknown(irg, get_irn_mode(node));
4210 * Transform and renumber the Projs from a Load.
4212 static ir_node *gen_Proj_Load(ir_node *node) {
4214 ir_node *block = be_transform_node(get_nodes_block(node));
4215 ir_node *pred = get_Proj_pred(node);
4216 ir_graph *irg = current_ir_graph;
4217 dbg_info *dbgi = get_irn_dbg_info(node);
4218 long proj = get_Proj_proj(node);
4221 /* loads might be part of source address mode matches, so we don't
4222 transform the ProjMs yet (with the exception of loads whose result is
4225 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4228 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4230 /* this is needed, because sometimes we have loops that are only
4231 reachable through the ProjM */
4232 be_enqueue_preds(node);
4233 /* do it in 2 steps, to silence firm verifier */
4234 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4235 set_Proj_proj(res, pn_ia32_Load_M);
4239 /* renumber the proj */
4240 new_pred = be_transform_node(pred);
4241 if (is_ia32_Load(new_pred)) {
4242 if (proj == pn_Load_res) {
4243 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4245 } else if (proj == pn_Load_M) {
4246 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4249 } else if(is_ia32_Conv_I2I(new_pred)
4250 || is_ia32_Conv_I2I8Bit(new_pred)) {
4251 set_irn_mode(new_pred, mode_T);
4252 if (proj == pn_Load_res) {
4253 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4254 } else if (proj == pn_Load_M) {
4255 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4257 } else if (is_ia32_xLoad(new_pred)) {
4258 if (proj == pn_Load_res) {
4259 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4261 } else if (proj == pn_Load_M) {
4262 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4265 } else if (is_ia32_vfld(new_pred)) {
4266 if (proj == pn_Load_res) {
4267 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4269 } else if (proj == pn_Load_M) {
4270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4274 /* can happen for ProJMs when source address mode happened for the
4277 /* however it should not be the result proj, as that would mean the
4278 load had multiple users and should not have been used for
4280 if(proj != pn_Load_M) {
4281 panic("internal error: transformed node not a Load");
4283 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4287 return new_rd_Unknown(irg, get_irn_mode(node));
4291 * Transform and renumber the Projs from a DivMod like instruction.
4293 static ir_node *gen_Proj_DivMod(ir_node *node) {
4294 ir_node *block = be_transform_node(get_nodes_block(node));
4295 ir_node *pred = get_Proj_pred(node);
4296 ir_node *new_pred = be_transform_node(pred);
4297 ir_graph *irg = current_ir_graph;
4298 dbg_info *dbgi = get_irn_dbg_info(node);
4299 ir_mode *mode = get_irn_mode(node);
4300 long proj = get_Proj_proj(node);
4302 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4304 switch (get_irn_opcode(pred)) {
4308 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4310 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4318 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4320 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4328 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4329 case pn_DivMod_res_div:
4330 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4331 case pn_DivMod_res_mod:
4332 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4342 return new_rd_Unknown(irg, mode);
4346 * Transform and renumber the Projs from a CopyB.
4348 static ir_node *gen_Proj_CopyB(ir_node *node) {
4349 ir_node *block = be_transform_node(get_nodes_block(node));
4350 ir_node *pred = get_Proj_pred(node);
4351 ir_node *new_pred = be_transform_node(pred);
4352 ir_graph *irg = current_ir_graph;
4353 dbg_info *dbgi = get_irn_dbg_info(node);
4354 ir_mode *mode = get_irn_mode(node);
4355 long proj = get_Proj_proj(node);
4358 case pn_CopyB_M_regular:
4359 if (is_ia32_CopyB_i(new_pred)) {
4360 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4361 } else if (is_ia32_CopyB(new_pred)) {
4362 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4370 return new_rd_Unknown(irg, mode);
4374 * Transform and renumber the Projs from a Quot.
4376 static ir_node *gen_Proj_Quot(ir_node *node) {
4377 ir_node *block = be_transform_node(get_nodes_block(node));
4378 ir_node *pred = get_Proj_pred(node);
4379 ir_node *new_pred = be_transform_node(pred);
4380 ir_graph *irg = current_ir_graph;
4381 dbg_info *dbgi = get_irn_dbg_info(node);
4382 ir_mode *mode = get_irn_mode(node);
4383 long proj = get_Proj_proj(node);
4387 if (is_ia32_xDiv(new_pred)) {
4388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4389 } else if (is_ia32_vfdiv(new_pred)) {
4390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4394 if (is_ia32_xDiv(new_pred)) {
4395 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4396 } else if (is_ia32_vfdiv(new_pred)) {
4397 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4405 return new_rd_Unknown(irg, mode);
4409 * Transform the Thread Local Storage Proj.
4411 static ir_node *gen_Proj_tls(ir_node *node) {
4412 ir_node *block = be_transform_node(get_nodes_block(node));
4413 ir_graph *irg = current_ir_graph;
4414 dbg_info *dbgi = NULL;
4415 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4420 static ir_node *gen_be_Call(ir_node *node) {
4421 ir_node *res = be_duplicate_node(node);
4422 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4427 static ir_node *gen_be_IncSP(ir_node *node) {
4428 ir_node *res = be_duplicate_node(node);
4429 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4435 * Transform the Projs from a be_Call.
4437 static ir_node *gen_Proj_be_Call(ir_node *node) {
4438 ir_node *block = be_transform_node(get_nodes_block(node));
4439 ir_node *call = get_Proj_pred(node);
4440 ir_node *new_call = be_transform_node(call);
4441 ir_graph *irg = current_ir_graph;
4442 dbg_info *dbgi = get_irn_dbg_info(node);
4443 ir_type *method_type = be_Call_get_type(call);
4444 int n_res = get_method_n_ress(method_type);
4445 long proj = get_Proj_proj(node);
4446 ir_mode *mode = get_irn_mode(node);
4448 const arch_register_class_t *cls;
4450 /* The following is kinda tricky: If we're using SSE, then we have to
4451 * move the result value of the call in floating point registers to an
4452 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4453 * after the call, we have to make sure to correctly make the
4454 * MemProj and the result Proj use these 2 nodes
4456 if (proj == pn_be_Call_M_regular) {
4457 // get new node for result, are we doing the sse load/store hack?
4458 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4459 ir_node *call_res_new;
4460 ir_node *call_res_pred = NULL;
4462 if (call_res != NULL) {
4463 call_res_new = be_transform_node(call_res);
4464 call_res_pred = get_Proj_pred(call_res_new);
4467 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4468 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4469 pn_be_Call_M_regular);
4471 assert(is_ia32_xLoad(call_res_pred));
4472 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4476 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4477 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4478 && USE_SSE2(env_cg)) {
4480 ir_node *frame = get_irg_frame(irg);
4481 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4483 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4486 /* in case there is no memory output: create one to serialize the copy
4488 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4489 pn_be_Call_M_regular);
4490 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4491 pn_be_Call_first_res);
4493 /* store st(0) onto stack */
4494 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4496 set_ia32_op_type(fstp, ia32_AddrModeD);
4497 set_ia32_use_frame(fstp);
4499 /* load into SSE register */
4500 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4502 set_ia32_op_type(sse_load, ia32_AddrModeS);
4503 set_ia32_use_frame(sse_load);
4505 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4511 /* transform call modes */
4512 if (mode_is_data(mode)) {
4513 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4517 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4521 * Transform the Projs from a Cmp.
4523 static ir_node *gen_Proj_Cmp(ir_node *node)
4525 /* normally Cmps are processed when looking at Cond nodes, but this case
4526 * can happen in complicated Psi conditions */
4527 dbg_info *dbgi = get_irn_dbg_info(node);
4528 ir_node *block = get_nodes_block(node);
4529 ir_node *new_block = be_transform_node(block);
4530 ir_node *cmp = get_Proj_pred(node);
4531 ir_node *new_cmp = be_transform_node(cmp);
4532 long pnc = get_Proj_proj(node);
4535 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4541 * Transform and potentially renumber Proj nodes.
4543 static ir_node *gen_Proj(ir_node *node) {
4544 ir_graph *irg = current_ir_graph;
4545 dbg_info *dbgi = get_irn_dbg_info(node);
4546 ir_node *pred = get_Proj_pred(node);
4547 long proj = get_Proj_proj(node);
4549 if (is_Store(pred)) {
4550 if (proj == pn_Store_M) {
4551 return be_transform_node(pred);
4554 return new_r_Bad(irg);
4556 } else if (is_Load(pred)) {
4557 return gen_Proj_Load(node);
4558 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4559 return gen_Proj_DivMod(node);
4560 } else if (is_CopyB(pred)) {
4561 return gen_Proj_CopyB(node);
4562 } else if (is_Quot(pred)) {
4563 return gen_Proj_Quot(node);
4564 } else if (be_is_SubSP(pred)) {
4565 return gen_Proj_be_SubSP(node);
4566 } else if (be_is_AddSP(pred)) {
4567 return gen_Proj_be_AddSP(node);
4568 } else if (be_is_Call(pred)) {
4569 return gen_Proj_be_Call(node);
4570 } else if (is_Cmp(pred)) {
4571 return gen_Proj_Cmp(node);
4572 } else if (get_irn_op(pred) == op_Start) {
4573 if (proj == pn_Start_X_initial_exec) {
4574 ir_node *block = get_nodes_block(pred);
4577 /* we exchange the ProjX with a jump */
4578 block = be_transform_node(block);
4579 jump = new_rd_Jmp(dbgi, irg, block);
4582 if (node == be_get_old_anchor(anchor_tls)) {
4583 return gen_Proj_tls(node);
4586 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4590 ir_node *new_pred = be_transform_node(pred);
4591 ir_node *block = be_transform_node(get_nodes_block(node));
4592 ir_mode *mode = get_irn_mode(node);
4593 if (mode_needs_gp_reg(mode)) {
4594 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4595 get_Proj_proj(node));
4596 #ifdef DEBUG_libfirm
4597 new_proj->node_nr = node->node_nr;
4603 return be_duplicate_node(node);
4607 * Enters all transform functions into the generic pointer
4609 static void register_transformers(void)
4613 /* first clear the generic function pointer for all ops */
4614 clear_irp_opcodes_generic_func();
4616 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4617 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4655 /* transform ops from intrinsic lowering */
4672 GEN(ia32_l_X87toSSE);
4673 GEN(ia32_l_SSEtoX87);
4679 /* we should never see these nodes */
4694 /* handle generic backend nodes */
4703 op_Mulh = get_op_Mulh();
4712 * Pre-transform all unknown and noreg nodes.
4714 static void ia32_pretransform_node(void *arch_cg) {
4715 ia32_code_gen_t *cg = arch_cg;
4717 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4718 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4719 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4720 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4721 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4722 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4727 * Walker, checks if all ia32 nodes producing more than one result have
4728 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4730 static void add_missing_keep_walker(ir_node *node, void *data)
4733 unsigned found_projs = 0;
4734 const ir_edge_t *edge;
4735 ir_mode *mode = get_irn_mode(node);
4740 if(!is_ia32_irn(node))
4743 n_outs = get_ia32_n_res(node);
4746 if(is_ia32_SwitchJmp(node))
4749 assert(n_outs < (int) sizeof(unsigned) * 8);
4750 foreach_out_edge(node, edge) {
4751 ir_node *proj = get_edge_src_irn(edge);
4752 int pn = get_Proj_proj(proj);
4754 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4755 found_projs |= 1 << pn;
4759 /* are keeps missing? */
4761 for(i = 0; i < n_outs; ++i) {
4764 const arch_register_req_t *req;
4765 const arch_register_class_t *class;
4767 if(found_projs & (1 << i)) {
4771 req = get_ia32_out_req(node, i);
4776 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4780 block = get_nodes_block(node);
4781 in[0] = new_r_Proj(current_ir_graph, block, node,
4782 arch_register_class_mode(class), i);
4783 if(last_keep != NULL) {
4784 be_Keep_add_node(last_keep, class, in[0]);
4786 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4787 if(sched_is_scheduled(node)) {
4788 sched_add_after(node, last_keep);
4795 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4798 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4800 ir_graph *irg = be_get_birg_irg(cg->birg);
4801 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4804 /* do the transformation */
4805 void ia32_transform_graph(ia32_code_gen_t *cg) {
4807 ir_graph *irg = cg->irg;
4809 /* TODO: look at cpu and fill transform config in with that... */
4810 transform_config.use_incdec = 1;
4811 transform_config.use_sse2 = 0;
4812 transform_config.use_ffreep = 0;
4813 transform_config.use_ftst = 0;
4814 transform_config.use_femms = 0;
4815 transform_config.use_fucomi = 1;
4816 transform_config.use_cmov = 1;
4818 register_transformers();
4820 initial_fpcw = NULL;
4822 heights = heights_new(irg);
4823 calculate_non_address_mode_nodes(irg);
4825 /* the transform phase is not safe for CSE (yet) because several nodes get
4826 * attributes set after their creation */
4827 cse_last = get_opt_cse();
4830 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4832 set_opt_cse(cse_last);
4834 free_non_address_mode_nodes();
4835 heights_free(heights);
4839 void ia32_init_transform(void)
4841 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");