2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
120 * Return true if a mode can be stored in the GP register set
122 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
123 if(mode == mode_fpcw)
125 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
129 * Returns 1 if irn is a Const representing 0, 0 otherwise
131 static INLINE int is_ia32_Const_0(ir_node *irn) {
132 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
133 && tarval_is_null(get_ia32_Immop_tarval(irn));
137 * Returns 1 if irn is a Const representing 1, 0 otherwise
139 static INLINE int is_ia32_Const_1(ir_node *irn) {
140 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
141 && tarval_is_one(get_ia32_Immop_tarval(irn));
145 * Collects all Projs of a node into the node array. Index is the projnum.
146 * BEWARE: The caller has to assure the appropriate array size!
148 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
149 const ir_edge_t *edge;
150 assert(get_irn_mode(irn) == mode_T && "need mode_T");
152 memset(projs, 0, size * sizeof(projs[0]));
154 foreach_out_edge(irn, edge) {
155 ir_node *proj = get_edge_src_irn(edge);
156 int proj_proj = get_Proj_proj(proj);
157 assert(proj_proj < size);
158 projs[proj_proj] = proj;
163 * Renumbers the proj having pn_old in the array tp pn_new
164 * and removes the proj from the array.
166 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
167 fprintf(stderr, "Warning: renumber_Proj used!\n");
169 set_Proj_proj(projs[pn_old], pn_new);
170 projs[pn_old] = NULL;
175 * creates a unique ident by adding a number to a tag
177 * @param tag the tag string, must contain a %d if a number
180 static ident *unique_id(const char *tag)
182 static unsigned id = 0;
185 snprintf(str, sizeof(str), tag, ++id);
186 return new_id_from_str(str);
190 * Get a primitive type for a mode.
192 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
194 pmap_entry *e = pmap_find(types, mode);
199 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
200 res = new_type_primitive(new_id_from_str(buf), mode);
201 set_type_alignment_bytes(res, 16);
202 pmap_insert(types, mode, res);
210 * Get an entity that is initialized with a tarval
212 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
214 tarval *tv = get_Const_tarval(cnst);
215 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
220 ir_mode *mode = get_irn_mode(cnst);
221 ir_type *tp = get_Const_type(cnst);
222 if (tp == firm_unknown_type)
223 tp = get_prim_type(cg->isa->types, mode);
225 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
227 set_entity_ld_ident(res, get_entity_ident(res));
228 set_entity_visibility(res, visibility_local);
229 set_entity_variability(res, variability_constant);
230 set_entity_allocation(res, allocation_static);
232 /* we create a new entity here: It's initialization must resist on the
234 rem = current_ir_graph;
235 current_ir_graph = get_const_code_irg();
236 set_atomic_ent_value(res, new_Const_type(tv, tp));
237 current_ir_graph = rem;
239 pmap_insert(cg->isa->tv_ent, tv, res);
247 static int is_Const_0(ir_node *node) {
251 return classify_Const(node) == CNST_NULL;
254 static int is_Const_1(ir_node *node) {
258 return classify_Const(node) == CNST_ONE;
262 * Transforms a Const.
264 static ir_node *gen_Const(ir_node *node) {
265 ir_graph *irg = current_ir_graph;
266 ir_node *block = be_transform_node(get_nodes_block(node));
267 dbg_info *dbgi = get_irn_dbg_info(node);
268 ir_mode *mode = get_irn_mode(node);
270 if (mode_is_float(mode)) {
272 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
273 ir_node *nomem = new_NoMem();
278 if (! USE_SSE2(env_cg)) {
279 cnst_classify_t clss = classify_Const(node);
281 if (clss == CNST_NULL) {
282 load = new_rd_ia32_vfldz(dbgi, irg, block);
284 } else if (clss == CNST_ONE) {
285 load = new_rd_ia32_vfld1(dbgi, irg, block);
288 floatent = get_entity_for_tv(env_cg, node);
290 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
291 set_ia32_op_type(load, ia32_AddrModeS);
292 set_ia32_am_flavour(load, ia32_am_N);
293 set_ia32_am_sc(load, floatent);
294 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
295 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
297 set_ia32_ls_mode(load, mode);
299 floatent = get_entity_for_tv(env_cg, node);
301 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
302 set_ia32_op_type(load, ia32_AddrModeS);
303 set_ia32_am_flavour(load, ia32_am_N);
304 set_ia32_am_sc(load, floatent);
305 set_ia32_ls_mode(load, mode);
306 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
308 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
311 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
313 /* Const Nodes before the initial IncSP are a bad idea, because
314 * they could be spilled and we have no SP ready at that point yet.
315 * So add a dependency to the initial frame pointer calculation to
316 * avoid that situation.
318 if (get_irg_start_block(irg) == block) {
319 add_irn_dep(load, get_irg_frame(irg));
322 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
325 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
328 if (get_irg_start_block(irg) == block) {
329 add_irn_dep(cnst, get_irg_frame(irg));
332 set_ia32_Const_attr(cnst, node);
333 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
338 return new_r_Bad(irg);
342 * Transforms a SymConst.
344 static ir_node *gen_SymConst(ir_node *node) {
345 ir_graph *irg = current_ir_graph;
346 ir_node *block = be_transform_node(get_nodes_block(node));
347 dbg_info *dbgi = get_irn_dbg_info(node);
348 ir_mode *mode = get_irn_mode(node);
351 if (mode_is_float(mode)) {
353 if (USE_SSE2(env_cg))
354 cnst = new_rd_ia32_xConst(dbgi, irg, block);
356 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
357 //set_ia32_ls_mode(cnst, mode);
358 set_ia32_ls_mode(cnst, mode_E);
360 cnst = new_rd_ia32_Const(dbgi, irg, block);
363 /* Const Nodes before the initial IncSP are a bad idea, because
364 * they could be spilled and we have no SP ready at that point yet
366 if (get_irg_start_block(irg) == block) {
367 add_irn_dep(cnst, get_irg_frame(irg));
370 set_ia32_Const_attr(cnst, node);
371 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
376 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
377 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
378 static const struct {
380 const char *ent_name;
381 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
388 static ir_entity *ent_cache[ia32_known_const_max];
390 const char *tp_name, *ent_name, *cnst_str;
398 ent_name = names[kct].ent_name;
399 if (! ent_cache[kct]) {
400 tp_name = names[kct].tp_name;
401 cnst_str = names[kct].cnst_str;
403 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
405 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
406 tp = new_type_primitive(new_id_from_str(tp_name), mode);
407 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
409 set_entity_ld_ident(ent, get_entity_ident(ent));
410 set_entity_visibility(ent, visibility_local);
411 set_entity_variability(ent, variability_constant);
412 set_entity_allocation(ent, allocation_static);
414 /* we create a new entity here: It's initialization must resist on the
416 rem = current_ir_graph;
417 current_ir_graph = get_const_code_irg();
418 cnst = new_Const(mode, tv);
419 current_ir_graph = rem;
421 set_atomic_ent_value(ent, cnst);
423 /* cache the entry */
424 ent_cache[kct] = ent;
427 return ent_cache[kct];
432 * Prints the old node name on cg obst and returns a pointer to it.
434 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
435 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
437 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
438 obstack_1grow(isa->name_obst, 0);
439 return obstack_finish(isa->name_obst);
443 /* determine if one operator is an Imm */
444 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
446 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
448 return is_ia32_Cnst(op2) ? op2 : NULL;
452 /* determine if one operator is not an Imm */
453 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
454 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
457 static void fold_immediate(ir_node *node, int in1, int in2) {
461 if (!(env_cg->opt & IA32_OPT_IMMOPS))
464 left = get_irn_n(node, in1);
465 right = get_irn_n(node, in2);
466 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
467 /* we can only set right operand to immediate */
468 if(!is_ia32_commutative(node))
470 /* exchange left/right */
471 set_irn_n(node, in1, right);
472 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
473 copy_ia32_Immop_attr(node, left);
474 } else if(is_ia32_Cnst(right)) {
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, right);
481 clear_ia32_commutative(node);
482 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
483 get_ia32_am_arity(node));
487 * Construct a standard binary operation, set AM and immediate if required.
489 * @param op1 The first operand
490 * @param op2 The second operand
491 * @param func The node constructor function
492 * @return The constructed ia32 node.
494 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
495 construct_binop_func *func, int commutative)
497 ir_node *block = be_transform_node(get_nodes_block(node));
498 ir_node *new_op1 = NULL;
499 ir_node *new_op2 = NULL;
500 ir_node *new_node = NULL;
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 new_op2 = try_create_Immediate(op1, 0);
508 if(new_op2 != NULL) {
509 new_op1 = be_transform_node(op2);
514 if(new_op2 == NULL) {
515 new_op2 = try_create_Immediate(op2, 0);
516 if(new_op2 != NULL) {
517 new_op1 = be_transform_node(op1);
522 if(new_op2 == NULL) {
523 new_op1 = be_transform_node(op1);
524 new_op2 = be_transform_node(op2);
527 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
528 if (func == new_rd_ia32_IMul) {
529 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
531 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
534 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
536 set_ia32_commutative(new_node);
543 * Construct a standard binary operation, set AM and immediate if required.
545 * @param op1 The first operand
546 * @param op2 The second operand
547 * @param func The node constructor function
548 * @return The constructed ia32 node.
550 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
551 construct_binop_func *func)
553 ir_node *block = be_transform_node(get_nodes_block(node));
554 ir_node *new_op1 = be_transform_node(op1);
555 ir_node *new_op2 = be_transform_node(op2);
556 ir_node *new_node = NULL;
557 dbg_info *dbgi = get_irn_dbg_info(node);
558 ir_graph *irg = current_ir_graph;
559 ir_mode *mode = get_irn_mode(node);
560 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
561 ir_node *nomem = new_NoMem();
563 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
565 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
566 if (is_op_commutative(get_irn_op(node))) {
567 set_ia32_commutative(new_node);
569 if (USE_SSE2(env_cg)) {
570 set_ia32_ls_mode(new_node, mode);
573 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
579 * Construct a standard binary operation, set AM and immediate if required.
581 * @param op1 The first operand
582 * @param op2 The second operand
583 * @param func The node constructor function
584 * @return The constructed ia32 node.
586 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
587 construct_binop_float_func *func)
589 ir_node *block = be_transform_node(get_nodes_block(node));
590 ir_node *new_op1 = be_transform_node(op1);
591 ir_node *new_op2 = be_transform_node(op2);
592 ir_node *new_node = NULL;
593 dbg_info *dbgi = get_irn_dbg_info(node);
594 ir_graph *irg = current_ir_graph;
595 ir_mode *mode = get_irn_mode(node);
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
598 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
599 &ia32_fp_cw_regs[REG_FPCW]);
601 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
603 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
604 if (is_op_commutative(get_irn_op(node))) {
605 set_ia32_commutative(new_node);
607 if (USE_SSE2(env_cg)) {
608 set_ia32_ls_mode(new_node, mode);
611 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
617 * Construct a shift/rotate binary operation, sets AM and immediate if required.
619 * @param op1 The first operand
620 * @param op2 The second operand
621 * @param func The node constructor function
622 * @return The constructed ia32 node.
624 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
625 construct_binop_func *func)
627 ir_node *block = be_transform_node(get_nodes_block(node));
628 ir_node *new_op1 = be_transform_node(op1);
630 ir_node *new_op = NULL;
631 dbg_info *dbgi = get_irn_dbg_info(node);
632 ir_graph *irg = current_ir_graph;
633 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
634 ir_node *nomem = new_NoMem();
636 assert(! mode_is_float(get_irn_mode(node))
637 && "Shift/Rotate with float not supported");
639 new_op2 = try_create_Immediate(op2, 'N');
640 if(new_op2 == NULL) {
641 new_op2 = be_transform_node(op2);
644 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
647 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
649 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
651 set_ia32_emit_cl(new_op);
658 * Construct a standard unary operation, set AM and immediate if required.
660 * @param op The operand
661 * @param func The node constructor function
662 * @return The constructed ia32 node.
664 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *new_op = be_transform_node(op);
668 ir_node *new_node = NULL;
669 ir_graph *irg = current_ir_graph;
670 dbg_info *dbgi = get_irn_dbg_info(node);
671 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
672 ir_node *nomem = new_NoMem();
674 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
675 DB((dbg, LEVEL_1, "INT unop ..."));
676 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
678 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
684 * Creates an ia32 Add.
686 * @return the created ia32 Add node
688 static ir_node *gen_Add(ir_node *node) {
689 ir_node *block = be_transform_node(get_nodes_block(node));
690 ir_node *op1 = get_Add_left(node);
691 ir_node *new_op1 = be_transform_node(op1);
692 ir_node *op2 = get_Add_right(node);
693 ir_node *new_op2 = be_transform_node(op2);
694 ir_node *new_op = NULL;
695 ir_graph *irg = current_ir_graph;
696 dbg_info *dbgi = get_irn_dbg_info(node);
697 ir_mode *mode = get_irn_mode(node);
698 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
699 ir_node *nomem = new_NoMem();
700 ir_node *expr_op, *imm_op;
702 /* Check if immediate optimization is on and */
703 /* if it's an operation with immediate. */
704 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
705 expr_op = get_expr_op(new_op1, new_op2);
707 assert((expr_op || imm_op) && "invalid operands");
709 if (mode_is_float(mode)) {
711 if (USE_SSE2(env_cg))
712 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
714 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
719 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
720 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
722 /* No expr_op means, that we have two const - one symconst and */
723 /* one tarval or another symconst - because this case is not */
724 /* covered by constant folding */
725 /* We need to check for: */
726 /* 1) symconst + const -> becomes a LEA */
727 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
728 /* linker doesn't support two symconsts */
730 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
731 /* this is the 2nd case */
732 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
733 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
734 set_ia32_am_flavour(new_op, ia32_am_B);
735 set_ia32_op_type(new_op, ia32_AddrModeS);
737 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
738 } else if (tp1 == ia32_ImmSymConst) {
739 tarval *tv = get_ia32_Immop_tarval(new_op2);
740 long offs = get_tarval_long(tv);
742 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
743 add_irn_dep(new_op, get_irg_frame(irg));
744 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
746 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
747 add_ia32_am_offs_int(new_op, offs);
748 set_ia32_am_flavour(new_op, ia32_am_OB);
749 set_ia32_op_type(new_op, ia32_AddrModeS);
750 } else if (tp2 == ia32_ImmSymConst) {
751 tarval *tv = get_ia32_Immop_tarval(new_op1);
752 long offs = get_tarval_long(tv);
754 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
755 add_irn_dep(new_op, get_irg_frame(irg));
756 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
758 add_ia32_am_offs_int(new_op, offs);
759 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
760 set_ia32_am_flavour(new_op, ia32_am_OB);
761 set_ia32_op_type(new_op, ia32_AddrModeS);
763 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
764 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
765 tarval *restv = tarval_add(tv1, tv2);
767 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
769 new_op = new_rd_ia32_Const(dbgi, irg, block);
770 set_ia32_Const_tarval(new_op, restv);
771 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
774 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
778 tarval_classification_t class_tv, class_negtv;
779 tarval *tv = get_ia32_Immop_tarval(imm_op);
781 /* optimize tarvals */
782 class_tv = classify_tarval(tv);
783 class_negtv = classify_tarval(tarval_neg(tv));
785 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
786 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
787 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
788 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
791 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
792 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
793 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
799 /* This is a normal add */
800 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
803 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
804 set_ia32_commutative(new_op);
806 fold_immediate(new_op, 2, 3);
808 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
814 static ir_node *create_ia32_Mul(ir_node *node) {
815 ir_graph *irg = current_ir_graph;
816 dbg_info *dbgi = get_irn_dbg_info(node);
817 ir_node *block = be_transform_node(get_nodes_block(node));
818 ir_node *op1 = get_Mul_left(node);
819 ir_node *op2 = get_Mul_right(node);
820 ir_node *new_op1 = be_transform_node(op1);
821 ir_node *new_op2 = be_transform_node(op2);
822 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
823 ir_node *proj_EAX, *proj_EDX, *res;
826 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
827 set_ia32_commutative(res);
828 set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
830 /* imediates are not supported, so no fold_immediate */
831 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
832 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
836 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
844 * Creates an ia32 Mul.
846 * @return the created ia32 Mul node
848 static ir_node *gen_Mul(ir_node *node) {
849 ir_node *op1 = get_Mul_left(node);
850 ir_node *op2 = get_Mul_right(node);
851 ir_mode *mode = get_irn_mode(node);
853 if (mode_is_float(mode)) {
855 if (USE_SSE2(env_cg))
856 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
858 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
862 for the lower 32bit of the result it doesn't matter whether we use
863 signed or unsigned multiplication so we use IMul as it has fewer
866 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
870 * Creates an ia32 Mulh.
871 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
872 * this result while Mul returns the lower 32 bit.
874 * @return the created ia32 Mulh node
876 static ir_node *gen_Mulh(ir_node *node) {
877 ir_node *block = be_transform_node(get_nodes_block(node));
878 ir_node *op1 = get_irn_n(node, 0);
879 ir_node *new_op1 = be_transform_node(op1);
880 ir_node *op2 = get_irn_n(node, 1);
881 ir_node *new_op2 = be_transform_node(op2);
882 ir_graph *irg = current_ir_graph;
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
885 ir_mode *mode = get_irn_mode(node);
886 ir_node *proj_EAX, *proj_EDX, *res;
889 assert(!mode_is_float(mode) && "Mulh with float not supported");
890 if (mode_is_signed(mode)) {
891 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
893 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
896 set_ia32_commutative(res);
897 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
899 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
900 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
904 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
912 * Creates an ia32 And.
914 * @return The created ia32 And node
916 static ir_node *gen_And(ir_node *node) {
917 ir_node *op1 = get_And_left(node);
918 ir_node *op2 = get_And_right(node);
920 assert (! mode_is_float(get_irn_mode(node)));
921 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
927 * Creates an ia32 Or.
929 * @return The created ia32 Or node
931 static ir_node *gen_Or(ir_node *node) {
932 ir_node *op1 = get_Or_left(node);
933 ir_node *op2 = get_Or_right(node);
935 assert (! mode_is_float(get_irn_mode(node)));
936 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
942 * Creates an ia32 Eor.
944 * @return The created ia32 Eor node
946 static ir_node *gen_Eor(ir_node *node) {
947 ir_node *op1 = get_Eor_left(node);
948 ir_node *op2 = get_Eor_right(node);
950 assert(! mode_is_float(get_irn_mode(node)));
951 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
957 * Creates an ia32 Max.
959 * @return the created ia32 Max node
961 static ir_node *gen_Max(ir_node *node) {
962 ir_node *block = be_transform_node(get_nodes_block(node));
963 ir_node *op1 = get_irn_n(node, 0);
964 ir_node *new_op1 = be_transform_node(op1);
965 ir_node *op2 = get_irn_n(node, 1);
966 ir_node *new_op2 = be_transform_node(op2);
967 ir_graph *irg = current_ir_graph;
968 ir_mode *mode = get_irn_mode(node);
969 dbg_info *dbgi = get_irn_dbg_info(node);
970 ir_mode *op_mode = get_irn_mode(op1);
973 assert(get_mode_size_bits(mode) == 32);
975 if (mode_is_float(mode)) {
977 if (USE_SSE2(env_cg)) {
978 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
980 panic("Can't create Max node");
983 long pnc = pn_Cmp_Gt;
984 if (! mode_is_signed(op_mode)) {
985 pnc |= ia32_pn_Cmp_Unsigned;
987 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
988 new_op1, new_op2, pnc);
990 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
996 * Creates an ia32 Min.
998 * @return the created ia32 Min node
1000 static ir_node *gen_Min(ir_node *node) {
1001 ir_node *block = be_transform_node(get_nodes_block(node));
1002 ir_node *op1 = get_irn_n(node, 0);
1003 ir_node *new_op1 = be_transform_node(op1);
1004 ir_node *op2 = get_irn_n(node, 1);
1005 ir_node *new_op2 = be_transform_node(op2);
1006 ir_graph *irg = current_ir_graph;
1007 ir_mode *mode = get_irn_mode(node);
1008 dbg_info *dbgi = get_irn_dbg_info(node);
1009 ir_mode *op_mode = get_irn_mode(op1);
1012 assert(get_mode_size_bits(mode) == 32);
1014 if (mode_is_float(mode)) {
1016 if (USE_SSE2(env_cg)) {
1017 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
1019 panic("can't create Min node");
1022 long pnc = pn_Cmp_Lt;
1023 if (! mode_is_signed(op_mode)) {
1024 pnc |= ia32_pn_Cmp_Unsigned;
1026 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1027 new_op1, new_op2, pnc);
1029 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1036 * Creates an ia32 Sub.
1038 * @return The created ia32 Sub node
1040 static ir_node *gen_Sub(ir_node *node) {
1041 ir_node *block = be_transform_node(get_nodes_block(node));
1042 ir_node *op1 = get_Sub_left(node);
1043 ir_node *new_op1 = be_transform_node(op1);
1044 ir_node *op2 = get_Sub_right(node);
1045 ir_node *new_op2 = be_transform_node(op2);
1046 ir_node *new_op = NULL;
1047 ir_graph *irg = current_ir_graph;
1048 dbg_info *dbgi = get_irn_dbg_info(node);
1049 ir_mode *mode = get_irn_mode(node);
1050 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1051 ir_node *nomem = new_NoMem();
1052 ir_node *expr_op, *imm_op;
1054 /* Check if immediate optimization is on and */
1055 /* if it's an operation with immediate. */
1056 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1057 expr_op = get_expr_op(new_op1, new_op2);
1059 assert((expr_op || imm_op) && "invalid operands");
1061 if (mode_is_float(mode)) {
1063 if (USE_SSE2(env_cg))
1064 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1066 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1071 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1072 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1074 /* No expr_op means, that we have two const - one symconst and */
1075 /* one tarval or another symconst - because this case is not */
1076 /* covered by constant folding */
1077 /* We need to check for: */
1078 /* 1) symconst - const -> becomes a LEA */
1079 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1080 /* linker doesn't support two symconsts */
1081 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1082 /* this is the 2nd case */
1083 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1084 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1085 set_ia32_am_sc_sign(new_op);
1086 set_ia32_am_flavour(new_op, ia32_am_B);
1088 DBG_OPT_LEA3(op1, op2, node, new_op);
1089 } else if (tp1 == ia32_ImmSymConst) {
1090 tarval *tv = get_ia32_Immop_tarval(new_op2);
1091 long offs = get_tarval_long(tv);
1093 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1094 add_irn_dep(new_op, get_irg_frame(irg));
1095 DBG_OPT_LEA3(op1, op2, node, new_op);
1097 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1098 add_ia32_am_offs_int(new_op, -offs);
1099 set_ia32_am_flavour(new_op, ia32_am_OB);
1100 set_ia32_op_type(new_op, ia32_AddrModeS);
1101 } else if (tp2 == ia32_ImmSymConst) {
1102 tarval *tv = get_ia32_Immop_tarval(new_op1);
1103 long offs = get_tarval_long(tv);
1105 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1106 add_irn_dep(new_op, get_irg_frame(irg));
1107 DBG_OPT_LEA3(op1, op2, node, new_op);
1109 add_ia32_am_offs_int(new_op, offs);
1110 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1111 set_ia32_am_sc_sign(new_op);
1112 set_ia32_am_flavour(new_op, ia32_am_OB);
1113 set_ia32_op_type(new_op, ia32_AddrModeS);
1115 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1116 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1117 tarval *restv = tarval_sub(tv1, tv2);
1119 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1121 new_op = new_rd_ia32_Const(dbgi, irg, block);
1122 set_ia32_Const_tarval(new_op, restv);
1123 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1126 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1128 } else if (imm_op) {
1129 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1130 tarval_classification_t class_tv, class_negtv;
1131 tarval *tv = get_ia32_Immop_tarval(imm_op);
1133 /* optimize tarvals */
1134 class_tv = classify_tarval(tv);
1135 class_negtv = classify_tarval(tarval_neg(tv));
1137 if (class_tv == TV_CLASSIFY_ONE) {
1138 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1139 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1140 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1142 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1143 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1144 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1145 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1151 /* This is a normal sub */
1152 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1154 /* set AM support */
1155 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1157 fold_immediate(new_op, 2, 3);
1159 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1167 * Generates an ia32 DivMod with additional infrastructure for the
1168 * register allocator if needed.
1170 * @param dividend -no comment- :)
1171 * @param divisor -no comment- :)
1172 * @param dm_flav flavour_Div/Mod/DivMod
1173 * @return The created ia32 DivMod node
1175 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1176 ir_node *divisor, ia32_op_flavour_t dm_flav)
1178 ir_node *block = be_transform_node(get_nodes_block(node));
1179 ir_node *new_dividend = be_transform_node(dividend);
1180 ir_node *new_divisor = be_transform_node(divisor);
1181 ir_graph *irg = current_ir_graph;
1182 dbg_info *dbgi = get_irn_dbg_info(node);
1183 ir_mode *mode = get_irn_mode(node);
1184 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1185 ir_node *res, *proj_div, *proj_mod;
1186 ir_node *sign_extension;
1187 ir_node *in_keep[2];
1188 ir_node *mem, *new_mem;
1189 ir_node *projs[pn_DivMod_max];
1192 ia32_collect_Projs(node, projs, pn_DivMod_max);
1194 proj_div = proj_mod = NULL;
1198 mem = get_Div_mem(node);
1199 mode = get_Div_resmode(node);
1200 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1201 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1204 mem = get_Mod_mem(node);
1205 mode = get_Mod_resmode(node);
1206 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1207 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1209 case flavour_DivMod:
1210 mem = get_DivMod_mem(node);
1211 mode = get_DivMod_resmode(node);
1212 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1213 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1214 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1217 panic("invalid divmod flavour!");
1219 new_mem = be_transform_node(mem);
1221 if (mode_is_signed(mode)) {
1222 /* in signed mode, we need to sign extend the dividend */
1223 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1225 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1226 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1228 add_irn_dep(sign_extension, get_irg_frame(irg));
1231 if (mode_is_signed(mode)) {
1232 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1233 sign_extension, new_divisor, new_mem, dm_flav);
1235 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1236 sign_extension, new_divisor, new_mem, dm_flav);
1239 set_ia32_exc_label(res, has_exc);
1240 set_irn_pinned(res, get_irn_pinned(node));
1242 /* Matze: code can't handle this at the moment... */
1244 /* set AM support */
1245 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1248 /* check, which Proj-Keep, we need to add */
1250 if (proj_div == NULL) {
1251 /* We have only mod result: add div res Proj-Keep */
1252 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1255 if (proj_mod == NULL) {
1256 /* We have only div result: add mod res Proj-Keep */
1257 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1261 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1263 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1270 * Wrapper for generate_DivMod. Sets flavour_Mod.
1273 static ir_node *gen_Mod(ir_node *node) {
1274 return generate_DivMod(node, get_Mod_left(node),
1275 get_Mod_right(node), flavour_Mod);
1279 * Wrapper for generate_DivMod. Sets flavour_Div.
1282 static ir_node *gen_Div(ir_node *node) {
1283 return generate_DivMod(node, get_Div_left(node),
1284 get_Div_right(node), flavour_Div);
1288 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1290 static ir_node *gen_DivMod(ir_node *node) {
1291 return generate_DivMod(node, get_DivMod_left(node),
1292 get_DivMod_right(node), flavour_DivMod);
1298 * Creates an ia32 floating Div.
1300 * @return The created ia32 xDiv node
1302 static ir_node *gen_Quot(ir_node *node) {
1303 ir_node *block = be_transform_node(get_nodes_block(node));
1304 ir_node *op1 = get_Quot_left(node);
1305 ir_node *new_op1 = be_transform_node(op1);
1306 ir_node *op2 = get_Quot_right(node);
1307 ir_node *new_op2 = be_transform_node(op2);
1308 ir_graph *irg = current_ir_graph;
1309 dbg_info *dbgi = get_irn_dbg_info(node);
1310 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1311 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1315 if (USE_SSE2(env_cg)) {
1316 ir_mode *mode = get_irn_mode(op1);
1317 if (is_ia32_xConst(new_op2)) {
1318 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1319 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1320 copy_ia32_Immop_attr(new_op, new_op2);
1322 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1323 // Matze: disabled for now, spillslot coalescer fails
1324 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1326 set_ia32_ls_mode(new_op, mode);
1328 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1329 &ia32_fp_cw_regs[REG_FPCW]);
1330 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1331 new_op2, nomem, fpcw);
1332 // Matze: disabled for now (spillslot coalescer fails)
1333 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1335 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1341 * Creates an ia32 Shl.
1343 * @return The created ia32 Shl node
1345 static ir_node *gen_Shl(ir_node *node) {
1346 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1353 * Creates an ia32 Shr.
1355 * @return The created ia32 Shr node
1357 static ir_node *gen_Shr(ir_node *node) {
1358 return gen_shift_binop(node, get_Shr_left(node),
1359 get_Shr_right(node), new_rd_ia32_Shr);
1365 * Creates an ia32 Sar.
1367 * @return The created ia32 Shrs node
1369 static ir_node *gen_Shrs(ir_node *node) {
1370 ir_node *left = get_Shrs_left(node);
1371 ir_node *right = get_Shrs_right(node);
1372 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1373 tarval *tv = get_Const_tarval(right);
1374 long val = get_tarval_long(tv);
1376 /* this is a sign extension */
1377 ir_graph *irg = current_ir_graph;
1378 dbg_info *dbgi = get_irn_dbg_info(node);
1379 ir_node *block = be_transform_node(get_nodes_block(node));
1381 ir_node *new_op = be_transform_node(op);
1383 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1387 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1393 * Creates an ia32 RotL.
1395 * @param op1 The first operator
1396 * @param op2 The second operator
1397 * @return The created ia32 RotL node
1399 static ir_node *gen_RotL(ir_node *node,
1400 ir_node *op1, ir_node *op2) {
1401 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1407 * Creates an ia32 RotR.
1408 * NOTE: There is no RotR with immediate because this would always be a RotL
1409 * "imm-mode_size_bits" which can be pre-calculated.
1411 * @param op1 The first operator
1412 * @param op2 The second operator
1413 * @return The created ia32 RotR node
1415 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1417 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1423 * Creates an ia32 RotR or RotL (depending on the found pattern).
1425 * @return The created ia32 RotL or RotR node
1427 static ir_node *gen_Rot(ir_node *node) {
1428 ir_node *rotate = NULL;
1429 ir_node *op1 = get_Rot_left(node);
1430 ir_node *op2 = get_Rot_right(node);
1432 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1433 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1434 that means we can create a RotR instead of an Add and a RotL */
1436 if (get_irn_op(op2) == op_Add) {
1438 ir_node *left = get_Add_left(add);
1439 ir_node *right = get_Add_right(add);
1440 if (is_Const(right)) {
1441 tarval *tv = get_Const_tarval(right);
1442 ir_mode *mode = get_irn_mode(node);
1443 long bits = get_mode_size_bits(mode);
1445 if (get_irn_op(left) == op_Minus &&
1446 tarval_is_long(tv) &&
1447 get_tarval_long(tv) == bits)
1449 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1450 rotate = gen_RotR(node, op1, get_Minus_op(left));
1455 if (rotate == NULL) {
1456 rotate = gen_RotL(node, op1, op2);
1465 * Transforms a Minus node.
1467 * @param op The Minus operand
1468 * @return The created ia32 Minus node
1470 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1471 ir_node *block = be_transform_node(get_nodes_block(node));
1472 ir_graph *irg = current_ir_graph;
1473 dbg_info *dbgi = get_irn_dbg_info(node);
1474 ir_mode *mode = get_irn_mode(node);
1479 if (mode_is_float(mode)) {
1480 ir_node *new_op = be_transform_node(op);
1482 if (USE_SSE2(env_cg)) {
1483 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1484 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1485 ir_node *nomem = new_rd_NoMem(irg);
1487 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1489 size = get_mode_size_bits(mode);
1490 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1492 set_ia32_am_sc(res, ent);
1493 set_ia32_op_type(res, ia32_AddrModeS);
1494 set_ia32_ls_mode(res, mode);
1496 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1499 res = gen_unop(node, op, new_rd_ia32_Neg);
1502 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1508 * Transforms a Minus node.
1510 * @return The created ia32 Minus node
1512 static ir_node *gen_Minus(ir_node *node) {
1513 return gen_Minus_ex(node, get_Minus_op(node));
1518 * Transforms a Not node.
1520 * @return The created ia32 Not node
1522 static ir_node *gen_Not(ir_node *node) {
1523 ir_node *op = get_Not_op(node);
1525 assert (! mode_is_float(get_irn_mode(node)));
1526 return gen_unop(node, op, new_rd_ia32_Not);
1532 * Transforms an Abs node.
1534 * @return The created ia32 Abs node
1536 static ir_node *gen_Abs(ir_node *node) {
1537 ir_node *block = be_transform_node(get_nodes_block(node));
1538 ir_node *op = get_Abs_op(node);
1539 ir_node *new_op = be_transform_node(op);
1540 ir_graph *irg = current_ir_graph;
1541 dbg_info *dbgi = get_irn_dbg_info(node);
1542 ir_mode *mode = get_irn_mode(node);
1543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1544 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1545 ir_node *nomem = new_NoMem();
1550 if (mode_is_float(mode)) {
1552 if (USE_SSE2(env_cg)) {
1553 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1555 size = get_mode_size_bits(mode);
1556 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1558 set_ia32_am_sc(res, ent);
1560 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1562 set_ia32_op_type(res, ia32_AddrModeS);
1563 set_ia32_ls_mode(res, mode);
1566 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1567 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1571 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1572 SET_IA32_ORIG_NODE(sign_extension,
1573 ia32_get_old_node_name(env_cg, node));
1575 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1576 sign_extension, nomem);
1577 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1579 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1580 sign_extension, nomem);
1581 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1590 * Transforms a Load.
1592 * @return the created ia32 Load node
1594 static ir_node *gen_Load(ir_node *node) {
1595 ir_node *block = be_transform_node(get_nodes_block(node));
1596 ir_node *ptr = get_Load_ptr(node);
1597 ir_node *new_ptr = be_transform_node(ptr);
1598 ir_node *mem = get_Load_mem(node);
1599 ir_node *new_mem = be_transform_node(mem);
1600 ir_graph *irg = current_ir_graph;
1601 dbg_info *dbgi = get_irn_dbg_info(node);
1602 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1603 ir_mode *mode = get_Load_mode(node);
1605 ir_node *lptr = new_ptr;
1608 ir_node *projs[pn_Load_max];
1609 ia32_am_flavour_t am_flav = ia32_am_B;
1611 ia32_collect_Projs(node, projs, pn_Load_max);
1613 /* address might be a constant (symconst or absolute address) */
1614 if (is_ia32_Const(new_ptr)) {
1619 if (mode_is_float(mode)) {
1621 if (USE_SSE2(env_cg)) {
1622 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1623 res_mode = mode_xmm;
1625 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1626 res_mode = mode_vfp;
1629 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1634 check for special case: the loaded value might not be used
1636 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1637 /* add a result proj and a Keep to produce a pseudo use */
1638 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1640 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1643 /* base is a constant address */
1645 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1646 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1647 am_flav = ia32_am_N;
1649 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1650 long offs = get_tarval_long(tv);
1652 add_ia32_am_offs_int(new_op, offs);
1653 am_flav = ia32_am_O;
1657 set_irn_pinned(new_op, get_irn_pinned(node));
1658 set_ia32_op_type(new_op, ia32_AddrModeS);
1659 set_ia32_am_flavour(new_op, am_flav);
1660 set_ia32_ls_mode(new_op, mode);
1662 /* make sure we are scheduled behind the initial IncSP/Barrier
1663 * to avoid spills being placed before it
1665 if (block == get_irg_start_block(irg)) {
1666 add_irn_dep(new_op, get_irg_frame(irg));
1669 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1670 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1678 * Transforms a Store.
1680 * @return the created ia32 Store node
1682 static ir_node *gen_Store(ir_node *node) {
1683 ir_node *block = be_transform_node(get_nodes_block(node));
1684 ir_node *ptr = get_Store_ptr(node);
1685 ir_node *new_ptr = be_transform_node(ptr);
1686 ir_node *val = get_Store_value(node);
1688 ir_node *mem = get_Store_mem(node);
1689 ir_node *new_mem = be_transform_node(mem);
1690 ir_graph *irg = current_ir_graph;
1691 dbg_info *dbgi = get_irn_dbg_info(node);
1692 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1693 ir_node *sptr = new_ptr;
1694 ir_mode *mode = get_irn_mode(val);
1697 ia32_am_flavour_t am_flav = ia32_am_B;
1699 /* address might be a constant (symconst or absolute address) */
1700 if (is_ia32_Const(new_ptr)) {
1705 if (mode_is_float(mode)) {
1708 new_val = be_transform_node(val);
1709 if (USE_SSE2(env_cg)) {
1710 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1713 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1717 new_val = try_create_Immediate(val, 0);
1718 if(new_val == NULL) {
1719 new_val = be_transform_node(val);
1722 if (get_mode_size_bits(mode) == 8) {
1723 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1726 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1731 /* base is an constant address */
1733 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1734 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1735 am_flav = ia32_am_N;
1737 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1738 long offs = get_tarval_long(tv);
1740 add_ia32_am_offs_int(new_op, offs);
1741 am_flav = ia32_am_O;
1745 set_irn_pinned(new_op, get_irn_pinned(node));
1746 set_ia32_op_type(new_op, ia32_AddrModeD);
1747 set_ia32_am_flavour(new_op, am_flav);
1748 set_ia32_ls_mode(new_op, mode);
1750 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1759 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1761 * @return The transformed node.
1763 static ir_node *gen_Cond(ir_node *node) {
1764 ir_node *block = be_transform_node(get_nodes_block(node));
1765 ir_graph *irg = current_ir_graph;
1766 dbg_info *dbgi = get_irn_dbg_info(node);
1767 ir_node *sel = get_Cond_selector(node);
1768 ir_mode *sel_mode = get_irn_mode(sel);
1769 ir_node *res = NULL;
1770 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1771 ir_node *cnst, *expr;
1773 if (is_Proj(sel) && sel_mode == mode_b) {
1774 ir_node *pred = get_Proj_pred(sel);
1775 ir_node *cmp_a = get_Cmp_left(pred);
1776 ir_node *new_cmp_a = be_transform_node(cmp_a);
1777 ir_node *cmp_b = get_Cmp_right(pred);
1778 ir_node *new_cmp_b = be_transform_node(cmp_b);
1779 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1780 ir_node *nomem = new_NoMem();
1782 int pnc = get_Proj_proj(sel);
1783 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1784 pnc |= ia32_pn_Cmp_Unsigned;
1787 /* check if we can use a CondJmp with immediate */
1788 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1789 expr = get_expr_op(new_cmp_a, new_cmp_b);
1791 if (cnst != NULL && expr != NULL) {
1792 /* immop has to be the right operand, we might need to flip pnc */
1793 if(cnst != new_cmp_b) {
1794 pnc = get_inversed_pnc(pnc);
1797 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1798 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1799 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1801 /* a Cmp A =/!= 0 */
1802 ir_node *op1 = expr;
1803 ir_node *op2 = expr;
1806 /* check, if expr is an only once used And operation */
1807 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1808 op1 = get_irn_n(expr, 2);
1809 op2 = get_irn_n(expr, 3);
1811 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1813 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1814 set_ia32_pncode(res, pnc);
1817 copy_ia32_Immop_attr(res, expr);
1820 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1825 if (mode_is_float(cmp_mode)) {
1827 if (USE_SSE2(env_cg)) {
1828 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1829 set_ia32_ls_mode(res, cmp_mode);
1835 assert(get_mode_size_bits(cmp_mode) == 32);
1836 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1838 copy_ia32_Immop_attr(res, cnst);
1841 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1843 if (mode_is_float(cmp_mode)) {
1845 if (USE_SSE2(env_cg)) {
1846 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1847 set_ia32_ls_mode(res, cmp_mode);
1850 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1851 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1852 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1856 assert(get_mode_size_bits(cmp_mode) == 32);
1857 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1858 set_ia32_commutative(res);
1862 set_ia32_pncode(res, pnc);
1863 // Matze: disabled for now, because the default collect_spills_walker
1864 // is not able to detect the mode of the spilled value
1865 // moreover, the lea optimize phase freely exchanges left/right
1866 // without updating the pnc
1867 //set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
1870 /* determine the smallest switch case value */
1871 ir_node *new_sel = be_transform_node(sel);
1872 int switch_min = INT_MAX;
1873 const ir_edge_t *edge;
1875 foreach_out_edge(node, edge) {
1876 int pn = get_Proj_proj(get_edge_src_irn(edge));
1877 switch_min = pn < switch_min ? pn : switch_min;
1881 /* if smallest switch case is not 0 we need an additional sub */
1882 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1883 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1884 add_ia32_am_offs_int(res, -switch_min);
1885 set_ia32_am_flavour(res, ia32_am_OB);
1886 set_ia32_op_type(res, ia32_AddrModeS);
1889 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1890 set_ia32_pncode(res, get_Cond_defaultProj(node));
1893 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1900 * Transforms a CopyB node.
1902 * @return The transformed node.
1904 static ir_node *gen_CopyB(ir_node *node) {
1905 ir_node *block = be_transform_node(get_nodes_block(node));
1906 ir_node *src = get_CopyB_src(node);
1907 ir_node *new_src = be_transform_node(src);
1908 ir_node *dst = get_CopyB_dst(node);
1909 ir_node *new_dst = be_transform_node(dst);
1910 ir_node *mem = get_CopyB_mem(node);
1911 ir_node *new_mem = be_transform_node(mem);
1912 ir_node *res = NULL;
1913 ir_graph *irg = current_ir_graph;
1914 dbg_info *dbgi = get_irn_dbg_info(node);
1915 int size = get_type_size_bytes(get_CopyB_type(node));
1916 ir_mode *dst_mode = get_irn_mode(dst);
1917 ir_mode *src_mode = get_irn_mode(src);
1921 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1922 /* then we need the size explicitly in ECX. */
1923 if (size >= 32 * 4) {
1924 rem = size & 0x3; /* size % 4 */
1927 res = new_rd_ia32_Const(dbgi, irg, block);
1928 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1929 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1931 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1932 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1934 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1935 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1936 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1937 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1938 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1941 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1942 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1944 /* ok: now attach Proj's because movsd will destroy esi and edi */
1945 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1946 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1947 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1950 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1956 ir_node *gen_be_Copy(ir_node *node)
1958 ir_node *result = be_duplicate_node(node);
1959 ir_mode *mode = get_irn_mode(result);
1961 if (mode_needs_gp_reg(mode)) {
1962 set_irn_mode(result, mode_Iu);
1971 * Transforms a Mux node into CMov.
1973 * @return The transformed node.
1975 static ir_node *gen_Mux(ir_node *node) {
1976 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1977 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1979 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1985 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1986 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1987 ir_node *psi_default);
1990 * Transforms a Psi node into CMov.
1992 * @return The transformed node.
1994 static ir_node *gen_Psi(ir_node *node) {
1995 ir_node *block = be_transform_node(get_nodes_block(node));
1996 ir_node *psi_true = get_Psi_val(node, 0);
1997 ir_node *psi_default = get_Psi_default(node);
1998 ia32_code_gen_t *cg = env_cg;
1999 ir_graph *irg = current_ir_graph;
2000 dbg_info *dbgi = get_irn_dbg_info(node);
2001 ir_node *cond = get_Psi_cond(node, 0);
2002 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2003 ir_node *nomem = new_NoMem();
2005 ir_node *cmp, *cmp_a, *cmp_b;
2006 ir_node *new_cmp_a, *new_cmp_b;
2010 assert(get_Psi_n_conds(node) == 1);
2011 assert(get_irn_mode(cond) == mode_b);
2013 if(is_And(cond) || is_Or(cond)) {
2014 ir_node *new_cond = be_transform_node(cond);
2015 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
2016 arch_set_irn_register(env_cg->arch_env, zero,
2017 &ia32_gp_regs[REG_GP_NOREG]);
2019 /* we have to compare the result against zero */
2020 new_cmp_a = new_cond;
2025 cmp = get_Proj_pred(cond);
2026 cmp_a = get_Cmp_left(cmp);
2027 cmp_b = get_Cmp_right(cmp);
2028 cmp_mode = get_irn_mode(cmp_a);
2029 pnc = get_Proj_proj(cond);
2031 new_cmp_b = try_create_Immediate(cmp_b, 0);
2032 if(new_cmp_b == NULL) {
2033 new_cmp_b = try_create_Immediate(cmp_a, 0);
2034 if(new_cmp_b != NULL) {
2035 pnc = get_inversed_pnc(pnc);
2036 new_cmp_a = be_transform_node(cmp_b);
2039 new_cmp_a = be_transform_node(cmp_a);
2041 if(new_cmp_b == NULL) {
2042 new_cmp_a = be_transform_node(cmp_a);
2043 new_cmp_b = be_transform_node(cmp_b);
2046 if (!mode_is_signed(cmp_mode)) {
2047 pnc |= ia32_pn_Cmp_Unsigned;
2051 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2052 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2053 new_cmp_a, new_cmp_b, nomem, pnc);
2054 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2055 pnc = get_negated_pnc(pnc, cmp_mode);
2056 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2057 new_cmp_a, new_cmp_b, nomem, pnc);
2059 ir_node *new_psi_true = be_transform_node(psi_true);
2060 ir_node *new_psi_default = be_transform_node(psi_default);
2061 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2062 new_psi_true, new_psi_default, pnc);
2064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2070 * Following conversion rules apply:
2074 * 1) n bit -> m bit n > m (downscale)
2076 * 2) n bit -> m bit n == m (sign change)
2078 * 3) n bit -> m bit n < m (upscale)
2079 * a) source is signed: movsx
2080 * b) source is unsigned: and with lower bits sets
2084 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2088 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2092 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2093 * x87 is mode_E internally, conversions happen only at load and store
2094 * in non-strict semantic
2098 * Create a conversion from x87 state register to general purpose.
2100 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2101 ir_node *block = be_transform_node(get_nodes_block(node));
2102 ir_node *op = get_Conv_op(node);
2103 ir_node *new_op = be_transform_node(op);
2104 ia32_code_gen_t *cg = env_cg;
2105 ir_graph *irg = current_ir_graph;
2106 dbg_info *dbgi = get_irn_dbg_info(node);
2107 ir_node *noreg = ia32_new_NoReg_gp(cg);
2108 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2109 ir_node *fist, *load;
2112 fist = new_rd_ia32_vfist(dbgi, irg, block,
2113 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2115 set_irn_pinned(fist, op_pin_state_floats);
2116 set_ia32_use_frame(fist);
2117 set_ia32_op_type(fist, ia32_AddrModeD);
2118 set_ia32_am_flavour(fist, ia32_am_B);
2119 set_ia32_ls_mode(fist, mode_Iu);
2120 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2123 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2125 set_irn_pinned(load, op_pin_state_floats);
2126 set_ia32_use_frame(load);
2127 set_ia32_op_type(load, ia32_AddrModeS);
2128 set_ia32_am_flavour(load, ia32_am_B);
2129 set_ia32_ls_mode(load, mode_Iu);
2130 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2132 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2136 * Create a conversion from general purpose to x87 register
2138 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2139 ir_node *block = be_transform_node(get_nodes_block(node));
2140 ir_node *op = get_Conv_op(node);
2141 ir_node *new_op = be_transform_node(op);
2142 ir_graph *irg = current_ir_graph;
2143 dbg_info *dbgi = get_irn_dbg_info(node);
2144 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2145 ir_node *nomem = new_NoMem();
2146 ir_node *fild, *store;
2149 /* first convert to 32 bit if necessary */
2150 src_bits = get_mode_size_bits(src_mode);
2151 if (src_bits == 8) {
2152 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2153 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2154 set_ia32_ls_mode(new_op, src_mode);
2155 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2156 } else if (src_bits < 32) {
2157 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2158 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2159 set_ia32_ls_mode(new_op, src_mode);
2160 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2164 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2166 set_ia32_use_frame(store);
2167 set_ia32_op_type(store, ia32_AddrModeD);
2168 set_ia32_am_flavour(store, ia32_am_OB);
2169 set_ia32_ls_mode(store, mode_Iu);
2172 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2174 set_ia32_use_frame(fild);
2175 set_ia32_op_type(fild, ia32_AddrModeS);
2176 set_ia32_am_flavour(fild, ia32_am_OB);
2177 set_ia32_ls_mode(fild, mode_Iu);
2179 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2182 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2185 ir_node *block = get_nodes_block(node);
2186 ir_graph *irg = current_ir_graph;
2187 dbg_info *dbgi = get_irn_dbg_info(node);
2188 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2189 ir_node *nomem = new_NoMem();
2190 int src_bits = get_mode_size_bits(src_mode);
2191 int tgt_bits = get_mode_size_bits(tgt_mode);
2192 ir_node *frame = get_irg_frame(irg);
2193 ir_mode *smaller_mode;
2194 ir_node *store, *load;
2197 if(src_bits <= tgt_bits)
2198 smaller_mode = src_mode;
2200 smaller_mode = tgt_mode;
2202 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2204 set_ia32_use_frame(store);
2205 set_ia32_op_type(store, ia32_AddrModeD);
2206 set_ia32_am_flavour(store, ia32_am_OB);
2208 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2210 set_ia32_use_frame(load);
2211 set_ia32_op_type(load, ia32_AddrModeS);
2212 set_ia32_am_flavour(load, ia32_am_OB);
2214 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2219 * Transforms a Conv node.
2221 * @return The created ia32 Conv node
2223 static ir_node *gen_Conv(ir_node *node) {
2224 ir_node *block = be_transform_node(get_nodes_block(node));
2225 ir_node *op = get_Conv_op(node);
2226 ir_node *new_op = be_transform_node(op);
2227 ir_graph *irg = current_ir_graph;
2228 dbg_info *dbgi = get_irn_dbg_info(node);
2229 ir_mode *src_mode = get_irn_mode(op);
2230 ir_mode *tgt_mode = get_irn_mode(node);
2231 int src_bits = get_mode_size_bits(src_mode);
2232 int tgt_bits = get_mode_size_bits(tgt_mode);
2233 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2234 ir_node *nomem = new_rd_NoMem(irg);
2237 if (src_mode == tgt_mode) {
2238 if (get_Conv_strict(node)) {
2239 if (USE_SSE2(env_cg)) {
2240 /* when we are in SSE mode, we can kill all strict no-op conversion */
2244 /* this should be optimized already, but who knows... */
2245 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2246 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2251 if (mode_is_float(src_mode)) {
2252 /* we convert from float ... */
2253 if (mode_is_float(tgt_mode)) {
2254 if(src_mode == mode_E && tgt_mode == mode_D
2255 && !get_Conv_strict(node)) {
2256 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2261 if (USE_SSE2(env_cg)) {
2262 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2263 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2264 set_ia32_ls_mode(res, tgt_mode);
2266 // Matze: TODO what about strict convs?
2267 if(get_Conv_strict(node)) {
2268 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2269 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2272 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2277 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2278 if (USE_SSE2(env_cg)) {
2279 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2280 set_ia32_ls_mode(res, src_mode);
2282 return gen_x87_fp_to_gp(node);
2286 /* we convert from int ... */
2287 if (mode_is_float(tgt_mode)) {
2290 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2291 if (USE_SSE2(env_cg)) {
2292 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2293 set_ia32_ls_mode(res, tgt_mode);
2294 if(src_bits == 32) {
2295 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2298 return gen_x87_gp_to_fp(node, src_mode);
2302 ir_mode *smaller_mode;
2305 if (src_bits == tgt_bits) {
2306 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2310 if (src_bits < tgt_bits) {
2311 smaller_mode = src_mode;
2312 smaller_bits = src_bits;
2314 smaller_mode = tgt_mode;
2315 smaller_bits = tgt_bits;
2318 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2319 if (smaller_bits == 8) {
2320 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2321 set_ia32_ls_mode(res, smaller_mode);
2323 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2324 set_ia32_ls_mode(res, smaller_mode);
2326 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2330 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2336 int check_immediate_constraint(long val, char immediate_constraint_type)
2338 switch (immediate_constraint_type) {
2342 return val >= 0 && val <= 32;
2344 return val >= 0 && val <= 63;
2346 return val >= -128 && val <= 127;
2348 return val == 0xff || val == 0xffff;
2350 return val >= 0 && val <= 3;
2352 return val >= 0 && val <= 255;
2354 return val >= 0 && val <= 127;
2358 panic("Invalid immediate constraint found");
2363 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2366 tarval *offset = NULL;
2367 int offset_sign = 0;
2369 ir_entity *symconst_ent = NULL;
2370 int symconst_sign = 0;
2372 ir_node *cnst = NULL;
2373 ir_node *symconst = NULL;
2379 mode = get_irn_mode(node);
2380 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2381 !mode_is_reference(mode)) {
2385 if(is_Minus(node)) {
2387 node = get_Minus_op(node);
2390 if(is_Const(node)) {
2393 offset_sign = minus;
2394 } else if(is_SymConst(node)) {
2397 symconst_sign = minus;
2398 } else if(is_Add(node)) {
2399 ir_node *left = get_Add_left(node);
2400 ir_node *right = get_Add_right(node);
2401 if(is_Const(left) && is_SymConst(right)) {
2404 symconst_sign = minus;
2405 offset_sign = minus;
2406 } else if(is_SymConst(left) && is_Const(right)) {
2409 symconst_sign = minus;
2410 offset_sign = minus;
2412 } else if(is_Sub(node)) {
2413 ir_node *left = get_Sub_left(node);
2414 ir_node *right = get_Sub_right(node);
2415 if(is_Const(left) && is_SymConst(right)) {
2418 symconst_sign = !minus;
2419 offset_sign = minus;
2420 } else if(is_SymConst(left) && is_Const(right)) {
2423 symconst_sign = minus;
2424 offset_sign = !minus;
2431 offset = get_Const_tarval(cnst);
2432 if(tarval_is_long(offset)) {
2433 val = get_tarval_long(offset);
2434 } else if(tarval_is_null(offset)) {
2437 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2442 if(!check_immediate_constraint(val, immediate_constraint_type))
2445 if(symconst != NULL) {
2446 if(immediate_constraint_type != 0) {
2447 /* we need full 32bits for symconsts */
2451 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2453 symconst_ent = get_SymConst_entity(symconst);
2455 if(cnst == NULL && symconst == NULL)
2458 if(offset_sign && offset != NULL) {
2459 offset = tarval_neg(offset);
2462 irg = current_ir_graph;
2463 dbgi = get_irn_dbg_info(node);
2464 block = get_irg_start_block(irg);
2465 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2467 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2469 /* make sure we don't schedule stuff before the barrier */
2470 add_irn_dep(res, get_irg_frame(irg));
2475 typedef struct constraint_t constraint_t;
2476 struct constraint_t {
2479 const arch_register_req_t **out_reqs;
2481 const arch_register_req_t *req;
2482 unsigned immediate_possible;
2483 char immediate_type;
2486 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2488 int immediate_possible = 0;
2489 char immediate_type = 0;
2490 unsigned limited = 0;
2491 const arch_register_class_t *cls = NULL;
2493 struct obstack *obst;
2494 arch_register_req_t *req;
2495 unsigned *limited_ptr;
2499 /* TODO: replace all the asserts with nice error messages */
2501 printf("Constraint: %s\n", c);
2511 assert(cls == NULL ||
2512 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2513 cls = &ia32_reg_classes[CLASS_ia32_gp];
2514 limited |= 1 << REG_EAX;
2517 assert(cls == NULL ||
2518 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2519 cls = &ia32_reg_classes[CLASS_ia32_gp];
2520 limited |= 1 << REG_EBX;
2523 assert(cls == NULL ||
2524 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2525 cls = &ia32_reg_classes[CLASS_ia32_gp];
2526 limited |= 1 << REG_ECX;
2529 assert(cls == NULL ||
2530 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2531 cls = &ia32_reg_classes[CLASS_ia32_gp];
2532 limited |= 1 << REG_EDX;
2535 assert(cls == NULL ||
2536 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2537 cls = &ia32_reg_classes[CLASS_ia32_gp];
2538 limited |= 1 << REG_EDI;
2541 assert(cls == NULL ||
2542 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2543 cls = &ia32_reg_classes[CLASS_ia32_gp];
2544 limited |= 1 << REG_ESI;
2547 case 'q': /* q means lower part of the regs only, this makes no
2548 * difference to Q for us (we only assigne whole registers) */
2549 assert(cls == NULL ||
2550 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2551 cls = &ia32_reg_classes[CLASS_ia32_gp];
2552 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2556 assert(cls == NULL ||
2557 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2558 cls = &ia32_reg_classes[CLASS_ia32_gp];
2559 limited |= 1 << REG_EAX | 1 << REG_EDX;
2562 assert(cls == NULL ||
2563 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2564 cls = &ia32_reg_classes[CLASS_ia32_gp];
2565 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2566 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2573 assert(cls == NULL);
2574 cls = &ia32_reg_classes[CLASS_ia32_gp];
2580 /* TODO: mark values so the x87 simulator knows about t and u */
2581 assert(cls == NULL);
2582 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2587 assert(cls == NULL);
2588 /* TODO: check that sse2 is supported */
2589 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2599 assert(!immediate_possible);
2600 immediate_possible = 1;
2601 immediate_type = *c;
2605 assert(!immediate_possible);
2606 immediate_possible = 1;
2610 assert(!immediate_possible && cls == NULL);
2611 immediate_possible = 1;
2612 cls = &ia32_reg_classes[CLASS_ia32_gp];
2625 assert(constraint->is_in && "can only specify same constraint "
2628 sscanf(c, "%d%n", &same_as, &p);
2635 case 'E': /* no float consts yet */
2636 case 'F': /* no float consts yet */
2637 case 's': /* makes no sense on x86 */
2638 case 'X': /* we can't support that in firm */
2642 case '<': /* no autodecrement on x86 */
2643 case '>': /* no autoincrement on x86 */
2644 case 'C': /* sse constant not supported yet */
2645 case 'G': /* 80387 constant not supported yet */
2646 case 'y': /* we don't support mmx registers yet */
2647 case 'Z': /* not available in 32 bit mode */
2648 case 'e': /* not available in 32 bit mode */
2649 assert(0 && "asm constraint not supported");
2652 assert(0 && "unknown asm constraint found");
2659 const arch_register_req_t *other_constr;
2661 assert(cls == NULL && "same as and register constraint not supported");
2662 assert(!immediate_possible && "same as and immediate constraint not "
2664 assert(same_as < constraint->n_outs && "wrong constraint number in "
2665 "same_as constraint");
2667 other_constr = constraint->out_reqs[same_as];
2669 req = obstack_alloc(obst, sizeof(req[0]));
2670 req->cls = other_constr->cls;
2671 req->type = arch_register_req_type_should_be_same;
2672 req->limited = NULL;
2673 req->other_same = pos;
2674 req->other_different = -1;
2676 /* switch constraints. This is because in firm we have same_as
2677 * constraints on the output constraints while in the gcc asm syntax
2678 * they are specified on the input constraints */
2679 constraint->req = other_constr;
2680 constraint->out_reqs[same_as] = req;
2681 constraint->immediate_possible = 0;
2685 if(immediate_possible && cls == NULL) {
2686 cls = &ia32_reg_classes[CLASS_ia32_gp];
2688 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2689 assert(cls != NULL);
2691 if(immediate_possible) {
2692 assert(constraint->is_in
2693 && "imeediates make no sense for output constraints");
2695 /* todo: check types (no float input on 'r' constrainted in and such... */
2697 irg = current_ir_graph;
2698 obst = get_irg_obstack(irg);
2701 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2702 limited_ptr = (unsigned*) (req+1);
2704 req = obstack_alloc(obst, sizeof(req[0]));
2706 memset(req, 0, sizeof(req[0]));
2709 req->type = arch_register_req_type_limited;
2710 *limited_ptr = limited;
2711 req->limited = limited_ptr;
2713 req->type = arch_register_req_type_normal;
2717 constraint->req = req;
2718 constraint->immediate_possible = immediate_possible;
2719 constraint->immediate_type = immediate_type;
2723 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2730 panic("Clobbers not supported yet");
2733 ir_node *gen_ASM(ir_node *node)
2736 ir_graph *irg = current_ir_graph;
2737 ir_node *block = be_transform_node(get_nodes_block(node));
2738 dbg_info *dbgi = get_irn_dbg_info(node);
2745 ia32_asm_attr_t *attr;
2746 const arch_register_req_t **out_reqs;
2747 const arch_register_req_t **in_reqs;
2748 struct obstack *obst;
2749 constraint_t parsed_constraint;
2751 /* assembler could contain float statements */
2754 /* transform inputs */
2755 arity = get_irn_arity(node);
2756 in = alloca(arity * sizeof(in[0]));
2757 memset(in, 0, arity * sizeof(in[0]));
2759 n_outs = get_ASM_n_output_constraints(node);
2760 n_clobbers = get_ASM_n_clobbers(node);
2761 out_arity = n_outs + n_clobbers;
2763 /* construct register constraints */
2764 obst = get_irg_obstack(irg);
2765 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2766 parsed_constraint.out_reqs = out_reqs;
2767 parsed_constraint.n_outs = n_outs;
2768 parsed_constraint.is_in = 0;
2769 for(i = 0; i < out_arity; ++i) {
2773 const ir_asm_constraint *constraint;
2774 constraint = & get_ASM_output_constraints(node) [i];
2775 c = get_id_str(constraint->constraint);
2776 parse_asm_constraint(i, &parsed_constraint, c);
2778 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2779 c = get_id_str(glob_id);
2780 parse_clobber(node, i, &parsed_constraint, c);
2782 out_reqs[i] = parsed_constraint.req;
2785 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2786 parsed_constraint.is_in = 1;
2787 for(i = 0; i < arity; ++i) {
2788 const ir_asm_constraint *constraint;
2792 constraint = & get_ASM_input_constraints(node) [i];
2793 constr_id = constraint->constraint;
2794 c = get_id_str(constr_id);
2795 parse_asm_constraint(i, &parsed_constraint, c);
2796 in_reqs[i] = parsed_constraint.req;
2798 if(parsed_constraint.immediate_possible) {
2799 ir_node *pred = get_irn_n(node, i);
2800 char imm_type = parsed_constraint.immediate_type;
2801 ir_node *immediate = try_create_Immediate(pred, imm_type);
2803 if(immediate != NULL) {
2809 /* transform inputs */
2810 for(i = 0; i < arity; ++i) {
2812 ir_node *transformed;
2817 pred = get_irn_n(node, i);
2818 transformed = be_transform_node(pred);
2819 in[i] = transformed;
2822 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2824 generic_attr = get_irn_generic_attr(res);
2825 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2826 attr->asm_text = get_ASM_text(node);
2827 set_ia32_out_req_all(res, out_reqs);
2828 set_ia32_in_req_all(res, in_reqs);
2830 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2835 /********************************************
2838 * | |__ ___ _ __ ___ __| | ___ ___
2839 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2840 * | |_) | __/ | | | (_) | (_| | __/\__ \
2841 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2843 ********************************************/
2845 static ir_node *gen_be_StackParam(ir_node *node) {
2846 ir_node *block = be_transform_node(get_nodes_block(node));
2847 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2848 ir_node *new_ptr = be_transform_node(ptr);
2849 ir_node *new_op = NULL;
2850 ir_graph *irg = current_ir_graph;
2851 dbg_info *dbgi = get_irn_dbg_info(node);
2852 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2853 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2854 ir_mode *load_mode = get_irn_mode(node);
2855 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2859 if (mode_is_float(load_mode)) {
2861 if (USE_SSE2(env_cg)) {
2862 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2863 pn_res = pn_ia32_xLoad_res;
2864 proj_mode = mode_xmm;
2866 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2867 pn_res = pn_ia32_vfld_res;
2868 proj_mode = mode_vfp;
2871 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2872 proj_mode = mode_Iu;
2873 pn_res = pn_ia32_Load_res;
2876 set_irn_pinned(new_op, op_pin_state_floats);
2877 set_ia32_frame_ent(new_op, ent);
2878 set_ia32_use_frame(new_op);
2880 set_ia32_op_type(new_op, ia32_AddrModeS);
2881 set_ia32_am_flavour(new_op, ia32_am_B);
2882 set_ia32_ls_mode(new_op, load_mode);
2883 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2885 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2887 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2891 * Transforms a FrameAddr into an ia32 Add.
2893 static ir_node *gen_be_FrameAddr(ir_node *node) {
2894 ir_node *block = be_transform_node(get_nodes_block(node));
2895 ir_node *op = be_get_FrameAddr_frame(node);
2896 ir_node *new_op = be_transform_node(op);
2897 ir_graph *irg = current_ir_graph;
2898 dbg_info *dbgi = get_irn_dbg_info(node);
2899 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2902 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2903 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2904 set_ia32_use_frame(res);
2905 set_ia32_am_flavour(res, ia32_am_OB);
2907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2913 * Transforms a FrameLoad into an ia32 Load.
2915 static ir_node *gen_be_FrameLoad(ir_node *node) {
2916 ir_node *block = be_transform_node(get_nodes_block(node));
2917 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2918 ir_node *new_mem = be_transform_node(mem);
2919 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2920 ir_node *new_ptr = be_transform_node(ptr);
2921 ir_node *new_op = NULL;
2922 ir_graph *irg = current_ir_graph;
2923 dbg_info *dbgi = get_irn_dbg_info(node);
2924 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2925 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2926 ir_mode *mode = get_type_mode(get_entity_type(ent));
2927 ir_node *projs[pn_Load_max];
2929 ia32_collect_Projs(node, projs, pn_Load_max);
2931 if (mode_is_float(mode)) {
2933 if (USE_SSE2(env_cg)) {
2934 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2937 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2941 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2944 set_irn_pinned(new_op, op_pin_state_floats);
2945 set_ia32_frame_ent(new_op, ent);
2946 set_ia32_use_frame(new_op);
2948 set_ia32_op_type(new_op, ia32_AddrModeS);
2949 set_ia32_am_flavour(new_op, ia32_am_B);
2950 set_ia32_ls_mode(new_op, mode);
2951 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2953 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2960 * Transforms a FrameStore into an ia32 Store.
2962 static ir_node *gen_be_FrameStore(ir_node *node) {
2963 ir_node *block = be_transform_node(get_nodes_block(node));
2964 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2965 ir_node *new_mem = be_transform_node(mem);
2966 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2967 ir_node *new_ptr = be_transform_node(ptr);
2968 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2969 ir_node *new_val = be_transform_node(val);
2970 ir_node *new_op = NULL;
2971 ir_graph *irg = current_ir_graph;
2972 dbg_info *dbgi = get_irn_dbg_info(node);
2973 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2974 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2975 ir_mode *mode = get_irn_mode(val);
2977 if (mode_is_float(mode)) {
2979 if (USE_SSE2(env_cg)) {
2980 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2982 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2984 } else if (get_mode_size_bits(mode) == 8) {
2985 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2987 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2990 set_ia32_frame_ent(new_op, ent);
2991 set_ia32_use_frame(new_op);
2993 set_ia32_op_type(new_op, ia32_AddrModeD);
2994 set_ia32_am_flavour(new_op, ia32_am_B);
2995 set_ia32_ls_mode(new_op, mode);
2997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3003 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3005 static ir_node *gen_be_Return(ir_node *node) {
3006 ir_graph *irg = current_ir_graph;
3007 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3008 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3009 ir_entity *ent = get_irg_entity(irg);
3010 ir_type *tp = get_entity_type(ent);
3015 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3016 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3019 int pn_ret_val, pn_ret_mem, arity, i;
3021 assert(ret_val != NULL);
3022 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3023 return be_duplicate_node(node);
3026 res_type = get_method_res_type(tp, 0);
3028 if (! is_Primitive_type(res_type)) {
3029 return be_duplicate_node(node);
3032 mode = get_type_mode(res_type);
3033 if (! mode_is_float(mode)) {
3034 return be_duplicate_node(node);
3037 assert(get_method_n_ress(tp) == 1);
3039 pn_ret_val = get_Proj_proj(ret_val);
3040 pn_ret_mem = get_Proj_proj(ret_mem);
3042 /* get the Barrier */
3043 barrier = get_Proj_pred(ret_val);
3045 /* get result input of the Barrier */
3046 ret_val = get_irn_n(barrier, pn_ret_val);
3047 new_ret_val = be_transform_node(ret_val);
3049 /* get memory input of the Barrier */
3050 ret_mem = get_irn_n(barrier, pn_ret_mem);
3051 new_ret_mem = be_transform_node(ret_mem);
3053 frame = get_irg_frame(irg);
3055 dbgi = get_irn_dbg_info(barrier);
3056 block = be_transform_node(get_nodes_block(barrier));
3058 noreg = ia32_new_NoReg_gp(env_cg);
3060 /* store xmm0 onto stack */
3061 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3062 set_ia32_ls_mode(sse_store, mode);
3063 set_ia32_op_type(sse_store, ia32_AddrModeD);
3064 set_ia32_use_frame(sse_store);
3065 set_ia32_am_flavour(sse_store, ia32_am_B);
3068 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3069 set_ia32_ls_mode(fld, mode);
3070 set_ia32_op_type(fld, ia32_AddrModeS);
3071 set_ia32_use_frame(fld);
3072 set_ia32_am_flavour(fld, ia32_am_B);
3074 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3075 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3076 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3078 /* create a new barrier */
3079 arity = get_irn_arity(barrier);
3080 in = alloca(arity * sizeof(in[0]));
3081 for (i = 0; i < arity; ++i) {
3084 if (i == pn_ret_val) {
3086 } else if (i == pn_ret_mem) {
3089 ir_node *in = get_irn_n(barrier, i);
3090 new_in = be_transform_node(in);
3095 new_barrier = new_ir_node(dbgi, irg, block,
3096 get_irn_op(barrier), get_irn_mode(barrier),
3098 copy_node_attr(barrier, new_barrier);
3099 be_duplicate_deps(barrier, new_barrier);
3100 be_set_transformed_node(barrier, new_barrier);
3101 mark_irn_visited(barrier);
3103 /* transform normally */
3104 return be_duplicate_node(node);
3108 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3110 static ir_node *gen_be_AddSP(ir_node *node) {
3111 ir_node *block = be_transform_node(get_nodes_block(node));
3112 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3114 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3115 ir_node *new_sp = be_transform_node(sp);
3116 ir_graph *irg = current_ir_graph;
3117 dbg_info *dbgi = get_irn_dbg_info(node);
3118 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3119 ir_node *nomem = new_NoMem();
3122 new_sz = try_create_Immediate(sz, 0);
3123 if(new_sz == NULL) {
3124 new_sz = be_transform_node(sz);
3127 /* ia32 stack grows in reverse direction, make a SubSP */
3128 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3130 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3131 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3137 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3139 static ir_node *gen_be_SubSP(ir_node *node) {
3140 ir_node *block = be_transform_node(get_nodes_block(node));
3141 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3143 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3144 ir_node *new_sp = be_transform_node(sp);
3145 ir_graph *irg = current_ir_graph;
3146 dbg_info *dbgi = get_irn_dbg_info(node);
3147 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3148 ir_node *nomem = new_NoMem();
3151 new_sz = try_create_Immediate(sz, 0);
3152 if(new_sz == NULL) {
3153 new_sz = be_transform_node(sz);
3156 /* ia32 stack grows in reverse direction, make an AddSP */
3157 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3158 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3159 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3165 * This function just sets the register for the Unknown node
3166 * as this is not done during register allocation because Unknown
3167 * is an "ignore" node.
3169 static ir_node *gen_Unknown(ir_node *node) {
3170 ir_mode *mode = get_irn_mode(node);
3172 if (mode_is_float(mode)) {
3173 if (USE_SSE2(env_cg))
3174 return ia32_new_Unknown_xmm(env_cg);
3176 return ia32_new_Unknown_vfp(env_cg);
3177 } else if (mode_needs_gp_reg(mode)) {
3178 return ia32_new_Unknown_gp(env_cg);
3180 assert(0 && "unsupported Unknown-Mode");
3187 * Change some phi modes
3189 static ir_node *gen_Phi(ir_node *node) {
3190 ir_node *block = be_transform_node(get_nodes_block(node));
3191 ir_graph *irg = current_ir_graph;
3192 dbg_info *dbgi = get_irn_dbg_info(node);
3193 ir_mode *mode = get_irn_mode(node);
3196 if(mode_needs_gp_reg(mode)) {
3197 /* we shouldn't have any 64bit stuff around anymore */
3198 assert(get_mode_size_bits(mode) <= 32);
3199 /* all integer operations are on 32bit registers now */
3201 } else if(mode_is_float(mode)) {
3202 if (USE_SSE2(env_cg)) {
3209 /* phi nodes allow loops, so we use the old arguments for now
3210 * and fix this later */
3211 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3212 copy_node_attr(node, phi);
3213 be_duplicate_deps(node, phi);
3215 be_set_transformed_node(node, phi);
3216 be_enqueue_preds(node);
3221 /**********************************************************************
3224 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3225 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3226 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3227 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3229 **********************************************************************/
3231 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3233 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3236 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3237 ir_node *val, ir_node *mem);
3240 * Transforms a lowered Load into a "real" one.
3242 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3243 ir_node *block = be_transform_node(get_nodes_block(node));
3244 ir_node *ptr = get_irn_n(node, 0);
3245 ir_node *new_ptr = be_transform_node(ptr);
3246 ir_node *mem = get_irn_n(node, 1);
3247 ir_node *new_mem = be_transform_node(mem);
3248 ir_graph *irg = current_ir_graph;
3249 dbg_info *dbgi = get_irn_dbg_info(node);
3250 ir_mode *mode = get_ia32_ls_mode(node);
3251 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3255 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3256 lowering we have x87 nodes, so we need to enforce simulation.
3258 if (mode_is_float(mode)) {
3260 if (fp_unit == fp_x87)
3264 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3266 set_ia32_op_type(new_op, ia32_AddrModeS);
3267 set_ia32_am_flavour(new_op, ia32_am_OB);
3268 set_ia32_am_offs_int(new_op, 0);
3269 set_ia32_am_scale(new_op, 1);
3270 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3271 if (is_ia32_am_sc_sign(node))
3272 set_ia32_am_sc_sign(new_op);
3273 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3274 if (is_ia32_use_frame(node)) {
3275 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3276 set_ia32_use_frame(new_op);
3279 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3285 * Transforms a lowered Store into a "real" one.
3287 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3288 ir_node *block = be_transform_node(get_nodes_block(node));
3289 ir_node *ptr = get_irn_n(node, 0);
3290 ir_node *new_ptr = be_transform_node(ptr);
3291 ir_node *val = get_irn_n(node, 1);
3292 ir_node *new_val = be_transform_node(val);
3293 ir_node *mem = get_irn_n(node, 2);
3294 ir_node *new_mem = be_transform_node(mem);
3295 ir_graph *irg = current_ir_graph;
3296 dbg_info *dbgi = get_irn_dbg_info(node);
3297 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3298 ir_mode *mode = get_ia32_ls_mode(node);
3301 ia32_am_flavour_t am_flav = ia32_B;
3304 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3305 lowering we have x87 nodes, so we need to enforce simulation.
3307 if (mode_is_float(mode)) {
3309 if (fp_unit == fp_x87)
3313 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3315 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3317 add_ia32_am_offs_int(new_op, am_offs);
3320 set_ia32_op_type(new_op, ia32_AddrModeD);
3321 set_ia32_am_flavour(new_op, am_flav);
3322 set_ia32_ls_mode(new_op, mode);
3323 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3324 set_ia32_use_frame(new_op);
3326 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3333 * Transforms an ia32_l_XXX into a "real" XXX node
3335 * @param env The transformation environment
3336 * @return the created ia32 XXX node
3338 #define GEN_LOWERED_OP(op) \
3339 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3340 ir_mode *mode = get_irn_mode(node); \
3341 if (mode_is_float(mode)) \
3343 return gen_binop(node, get_binop_left(node), \
3344 get_binop_right(node), new_rd_ia32_##op,0); \
3347 #define GEN_LOWERED_x87_OP(op) \
3348 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3350 FORCE_x87(env_cg); \
3351 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3352 get_binop_right(node), new_rd_ia32_##op); \
3356 #define GEN_LOWERED_UNOP(op) \
3357 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3358 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3361 #define GEN_LOWERED_SHIFT_OP(op) \
3362 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3363 return gen_shift_binop(node, get_binop_left(node), \
3364 get_binop_right(node), new_rd_ia32_##op); \
3367 #define GEN_LOWERED_LOAD(op, fp_unit) \
3368 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3369 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3372 #define GEN_LOWERED_STORE(op, fp_unit) \
3373 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3374 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3381 GEN_LOWERED_OP(IMul)
3383 GEN_LOWERED_x87_OP(vfprem)
3384 GEN_LOWERED_x87_OP(vfmul)
3385 GEN_LOWERED_x87_OP(vfsub)
3387 GEN_LOWERED_UNOP(Neg)
3389 GEN_LOWERED_LOAD(vfild, fp_x87)
3390 GEN_LOWERED_LOAD(Load, fp_none)
3391 /*GEN_LOWERED_STORE(vfist, fp_x87)
3394 GEN_LOWERED_STORE(Store, fp_none)
3396 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3397 ir_node *block = be_transform_node(get_nodes_block(node));
3398 ir_node *left = get_binop_left(node);
3399 ir_node *new_left = be_transform_node(left);
3400 ir_node *right = get_binop_right(node);
3401 ir_node *new_right = be_transform_node(right);
3402 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3403 ir_graph *irg = current_ir_graph;
3404 dbg_info *dbgi = get_irn_dbg_info(node);
3405 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3406 &ia32_fp_cw_regs[REG_FPCW]);
3409 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3410 new_right, new_NoMem(), fpcw);
3411 clear_ia32_commutative(vfdiv);
3412 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3414 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3422 * Transforms a l_MulS into a "real" MulS node.
3424 * @param env The transformation environment
3425 * @return the created ia32 Mul node
3427 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3428 ir_node *block = be_transform_node(get_nodes_block(node));
3429 ir_node *left = get_binop_left(node);
3430 ir_node *new_left = be_transform_node(left);
3431 ir_node *right = get_binop_right(node);
3432 ir_node *new_right = be_transform_node(right);
3433 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3434 ir_graph *irg = current_ir_graph;
3435 dbg_info *dbgi = get_irn_dbg_info(node);
3438 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3439 /* and then skip the result Proj, because all needed Projs are already there. */
3440 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3441 new_right, new_NoMem());
3442 clear_ia32_commutative(muls);
3443 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3445 /* check if EAX and EDX proj exist, add missing one */
3446 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3447 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3448 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3450 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3455 GEN_LOWERED_SHIFT_OP(Shl)
3456 GEN_LOWERED_SHIFT_OP(Shr)
3457 GEN_LOWERED_SHIFT_OP(Sar)
3460 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3461 * op1 - target to be shifted
3462 * op2 - contains bits to be shifted into target
3464 * Only op3 can be an immediate.
3466 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3467 ir_node *op2, ir_node *count)
3469 ir_node *block = be_transform_node(get_nodes_block(node));
3470 ir_node *new_op1 = be_transform_node(op1);
3471 ir_node *new_op2 = be_transform_node(op2);
3472 ir_node *new_count = be_transform_node(count);
3473 ir_node *new_op = NULL;
3474 ir_graph *irg = current_ir_graph;
3475 dbg_info *dbgi = get_irn_dbg_info(node);
3476 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3477 ir_node *nomem = new_NoMem();
3481 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3483 /* Check if immediate optimization is on and */
3484 /* if it's an operation with immediate. */
3485 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3487 /* Limit imm_op within range imm8 */
3489 tv = get_ia32_Immop_tarval(imm_op);
3492 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3493 set_ia32_Immop_tarval(imm_op, tv);
3500 /* integer operations */
3502 /* This is ShiftD with const */
3503 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3505 if (is_ia32_l_ShlD(node))
3506 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3507 new_op1, new_op2, noreg, nomem);
3509 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3510 new_op1, new_op2, noreg, nomem);
3511 copy_ia32_Immop_attr(new_op, imm_op);
3514 /* This is a normal ShiftD */
3515 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3516 if (is_ia32_l_ShlD(node))
3517 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3518 new_op1, new_op2, new_count, nomem);
3520 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3521 new_op1, new_op2, new_count, nomem);
3524 /* set AM support */
3525 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3527 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3529 set_ia32_emit_cl(new_op);
3534 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3535 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3536 get_irn_n(node, 1), get_irn_n(node, 2));
3539 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3540 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3541 get_irn_n(node, 1), get_irn_n(node, 2));
3545 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3547 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3548 ir_node *block = be_transform_node(get_nodes_block(node));
3549 ir_node *val = get_irn_n(node, 1);
3550 ir_node *new_val = be_transform_node(val);
3551 ia32_code_gen_t *cg = env_cg;
3552 ir_node *res = NULL;
3553 ir_graph *irg = current_ir_graph;
3555 ir_node *noreg, *new_ptr, *new_mem;
3562 mem = get_irn_n(node, 2);
3563 new_mem = be_transform_node(mem);
3564 ptr = get_irn_n(node, 0);
3565 new_ptr = be_transform_node(ptr);
3566 noreg = ia32_new_NoReg_gp(cg);
3567 dbgi = get_irn_dbg_info(node);
3569 /* Store x87 -> MEM */
3570 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3571 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3572 set_ia32_use_frame(res);
3573 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3574 set_ia32_am_flavour(res, ia32_B);
3575 set_ia32_op_type(res, ia32_AddrModeD);
3577 /* Load MEM -> SSE */
3578 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3579 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3580 set_ia32_use_frame(res);
3581 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3582 set_ia32_am_flavour(res, ia32_B);
3583 set_ia32_op_type(res, ia32_AddrModeS);
3584 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3590 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3592 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3593 ir_node *block = be_transform_node(get_nodes_block(node));
3594 ir_node *val = get_irn_n(node, 1);
3595 ir_node *new_val = be_transform_node(val);
3596 ia32_code_gen_t *cg = env_cg;
3597 ir_graph *irg = current_ir_graph;
3598 ir_node *res = NULL;
3599 ir_entity *fent = get_ia32_frame_ent(node);
3600 ir_mode *lsmode = get_ia32_ls_mode(node);
3602 ir_node *noreg, *new_ptr, *new_mem;
3606 if (! USE_SSE2(cg)) {
3607 /* SSE unit is not used -> skip this node. */
3611 ptr = get_irn_n(node, 0);
3612 new_ptr = be_transform_node(ptr);
3613 mem = get_irn_n(node, 2);
3614 new_mem = be_transform_node(mem);
3615 noreg = ia32_new_NoReg_gp(cg);
3616 dbgi = get_irn_dbg_info(node);
3618 /* Store SSE -> MEM */
3619 if (is_ia32_xLoad(skip_Proj(new_val))) {
3620 ir_node *ld = skip_Proj(new_val);
3622 /* we can vfld the value directly into the fpu */
3623 fent = get_ia32_frame_ent(ld);
3624 ptr = get_irn_n(ld, 0);
3625 offs = get_ia32_am_offs_int(ld);
3627 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3628 set_ia32_frame_ent(res, fent);
3629 set_ia32_use_frame(res);
3630 set_ia32_ls_mode(res, lsmode);
3631 set_ia32_am_flavour(res, ia32_B);
3632 set_ia32_op_type(res, ia32_AddrModeD);
3636 /* Load MEM -> x87 */
3637 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3638 set_ia32_frame_ent(res, fent);
3639 set_ia32_use_frame(res);
3640 add_ia32_am_offs_int(res, offs);
3641 set_ia32_am_flavour(res, ia32_B);
3642 set_ia32_op_type(res, ia32_AddrModeS);
3643 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3648 /*********************************************************
3651 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3652 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3653 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3654 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3656 *********************************************************/
3659 * the BAD transformer.
3661 static ir_node *bad_transform(ir_node *node) {
3662 panic("No transform function for %+F available.\n", node);
3667 * Transform the Projs of an AddSP.
3669 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3670 ir_node *block = be_transform_node(get_nodes_block(node));
3671 ir_node *pred = get_Proj_pred(node);
3672 ir_node *new_pred = be_transform_node(pred);
3673 ir_graph *irg = current_ir_graph;
3674 dbg_info *dbgi = get_irn_dbg_info(node);
3675 long proj = get_Proj_proj(node);
3677 if (proj == pn_be_AddSP_res) {
3678 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3679 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3681 } else if (proj == pn_be_AddSP_M) {
3682 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3686 return new_rd_Unknown(irg, get_irn_mode(node));
3690 * Transform the Projs of a SubSP.
3692 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3693 ir_node *block = be_transform_node(get_nodes_block(node));
3694 ir_node *pred = get_Proj_pred(node);
3695 ir_node *new_pred = be_transform_node(pred);
3696 ir_graph *irg = current_ir_graph;
3697 dbg_info *dbgi = get_irn_dbg_info(node);
3698 long proj = get_Proj_proj(node);
3700 if (proj == pn_be_SubSP_res) {
3701 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3702 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3704 } else if (proj == pn_be_SubSP_M) {
3705 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3709 return new_rd_Unknown(irg, get_irn_mode(node));
3713 * Transform and renumber the Projs from a Load.
3715 static ir_node *gen_Proj_Load(ir_node *node) {
3716 ir_node *block = be_transform_node(get_nodes_block(node));
3717 ir_node *pred = get_Proj_pred(node);
3718 ir_node *new_pred = be_transform_node(pred);
3719 ir_graph *irg = current_ir_graph;
3720 dbg_info *dbgi = get_irn_dbg_info(node);
3721 long proj = get_Proj_proj(node);
3723 /* renumber the proj */
3724 if (is_ia32_Load(new_pred)) {
3725 if (proj == pn_Load_res) {
3726 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3727 } else if (proj == pn_Load_M) {
3728 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3730 } else if (is_ia32_xLoad(new_pred)) {
3731 if (proj == pn_Load_res) {
3732 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3733 } else if (proj == pn_Load_M) {
3734 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3736 } else if (is_ia32_vfld(new_pred)) {
3737 if (proj == pn_Load_res) {
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3739 } else if (proj == pn_Load_M) {
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3745 return new_rd_Unknown(irg, get_irn_mode(node));
3749 * Transform and renumber the Projs from a DivMod like instruction.
3751 static ir_node *gen_Proj_DivMod(ir_node *node) {
3752 ir_node *block = be_transform_node(get_nodes_block(node));
3753 ir_node *pred = get_Proj_pred(node);
3754 ir_node *new_pred = be_transform_node(pred);
3755 ir_graph *irg = current_ir_graph;
3756 dbg_info *dbgi = get_irn_dbg_info(node);
3757 ir_mode *mode = get_irn_mode(node);
3758 long proj = get_Proj_proj(node);
3760 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3762 switch (get_irn_opcode(pred)) {
3766 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3768 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3776 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3778 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3786 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3787 case pn_DivMod_res_div:
3788 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3789 case pn_DivMod_res_mod:
3790 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3800 return new_rd_Unknown(irg, mode);
3804 * Transform and renumber the Projs from a CopyB.
3806 static ir_node *gen_Proj_CopyB(ir_node *node) {
3807 ir_node *block = be_transform_node(get_nodes_block(node));
3808 ir_node *pred = get_Proj_pred(node);
3809 ir_node *new_pred = be_transform_node(pred);
3810 ir_graph *irg = current_ir_graph;
3811 dbg_info *dbgi = get_irn_dbg_info(node);
3812 ir_mode *mode = get_irn_mode(node);
3813 long proj = get_Proj_proj(node);
3816 case pn_CopyB_M_regular:
3817 if (is_ia32_CopyB_i(new_pred)) {
3818 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3819 } else if (is_ia32_CopyB(new_pred)) {
3820 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3828 return new_rd_Unknown(irg, mode);
3832 * Transform and renumber the Projs from a vfdiv.
3834 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3835 ir_node *block = be_transform_node(get_nodes_block(node));
3836 ir_node *pred = get_Proj_pred(node);
3837 ir_node *new_pred = be_transform_node(pred);
3838 ir_graph *irg = current_ir_graph;
3839 dbg_info *dbgi = get_irn_dbg_info(node);
3840 ir_mode *mode = get_irn_mode(node);
3841 long proj = get_Proj_proj(node);
3844 case pn_ia32_l_vfdiv_M:
3845 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3846 case pn_ia32_l_vfdiv_res:
3847 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3852 return new_rd_Unknown(irg, mode);
3856 * Transform and renumber the Projs from a Quot.
3858 static ir_node *gen_Proj_Quot(ir_node *node) {
3859 ir_node *block = be_transform_node(get_nodes_block(node));
3860 ir_node *pred = get_Proj_pred(node);
3861 ir_node *new_pred = be_transform_node(pred);
3862 ir_graph *irg = current_ir_graph;
3863 dbg_info *dbgi = get_irn_dbg_info(node);
3864 ir_mode *mode = get_irn_mode(node);
3865 long proj = get_Proj_proj(node);
3869 if (is_ia32_xDiv(new_pred)) {
3870 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3871 } else if (is_ia32_vfdiv(new_pred)) {
3872 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3876 if (is_ia32_xDiv(new_pred)) {
3877 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3878 } else if (is_ia32_vfdiv(new_pred)) {
3879 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3887 return new_rd_Unknown(irg, mode);
3891 * Transform the Thread Local Storage Proj.
3893 static ir_node *gen_Proj_tls(ir_node *node) {
3894 ir_node *block = be_transform_node(get_nodes_block(node));
3895 ir_graph *irg = current_ir_graph;
3896 dbg_info *dbgi = NULL;
3897 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3903 * Transform the Projs from a be_Call.
3905 static ir_node *gen_Proj_be_Call(ir_node *node) {
3906 ir_node *block = be_transform_node(get_nodes_block(node));
3907 ir_node *call = get_Proj_pred(node);
3908 ir_node *new_call = be_transform_node(call);
3909 ir_graph *irg = current_ir_graph;
3910 dbg_info *dbgi = get_irn_dbg_info(node);
3911 long proj = get_Proj_proj(node);
3912 ir_mode *mode = get_irn_mode(node);
3914 const arch_register_class_t *cls;
3916 /* The following is kinda tricky: If we're using SSE, then we have to
3917 * move the result value of the call in floating point registers to an
3918 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3919 * after the call, we have to make sure to correctly make the
3920 * MemProj and the result Proj use these 2 nodes
3922 if (proj == pn_be_Call_M_regular) {
3923 // get new node for result, are we doing the sse load/store hack?
3924 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3925 ir_node *call_res_new;
3926 ir_node *call_res_pred = NULL;
3928 if (call_res != NULL) {
3929 call_res_new = be_transform_node(call_res);
3930 call_res_pred = get_Proj_pred(call_res_new);
3933 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3934 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3936 assert(is_ia32_xLoad(call_res_pred));
3937 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3940 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3942 ir_node *frame = get_irg_frame(irg);
3943 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3945 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3947 const arch_register_class_t *cls;
3949 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3950 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3952 /* store st(0) onto stack */
3953 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3955 set_ia32_ls_mode(fstp, mode);
3956 set_ia32_op_type(fstp, ia32_AddrModeD);
3957 set_ia32_use_frame(fstp);
3958 set_ia32_am_flavour(fstp, ia32_am_B);
3960 /* load into SSE register */
3961 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3962 set_ia32_ls_mode(sse_load, mode);
3963 set_ia32_op_type(sse_load, ia32_AddrModeS);
3964 set_ia32_use_frame(sse_load);
3965 set_ia32_am_flavour(sse_load, ia32_am_B);
3967 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3969 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3971 /* get a Proj representing a caller save register */
3972 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3973 assert(is_Proj(p) && "Proj expected.");
3975 /* user of the the proj is the Keep */
3976 p = get_edge_src_irn(get_irn_out_edge_first(p));
3977 assert(be_is_Keep(p) && "Keep expected.");
3979 /* keep the result */
3980 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3981 keepin[0] = sse_load;
3982 be_new_Keep(cls, irg, block, 1, keepin);
3987 /* transform call modes */
3988 if (mode_is_data(mode)) {
3989 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3993 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3997 * Transform the Projs from a Cmp.
3999 static ir_node *gen_Proj_Cmp(ir_node *node)
4001 /* normally Cmps are processed when looking at Cond nodes, but this case
4002 * can happen in complicated Psi conditions */
4004 ir_graph *irg = current_ir_graph;
4005 dbg_info *dbgi = get_irn_dbg_info(node);
4006 ir_node *block = be_transform_node(get_nodes_block(node));
4007 ir_node *cmp = get_Proj_pred(node);
4008 long pnc = get_Proj_proj(node);
4009 ir_node *cmp_left = get_Cmp_left(cmp);
4010 ir_node *cmp_right = get_Cmp_right(cmp);
4011 ir_node *new_cmp_left;
4012 ir_node *new_cmp_right;
4013 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4014 ir_node *nomem = new_rd_NoMem(irg);
4015 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4018 assert(!mode_is_float(cmp_mode));
4020 /* (a != b) -> (a ^ b) */
4021 if(pnc == pn_Cmp_Lg) {
4022 if(is_Const_0(cmp_left)) {
4023 new_op = be_transform_node(cmp_right);
4024 } else if(is_Const_0(cmp_right)) {
4025 new_op = be_transform_node(cmp_left);
4027 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4033 * (a == b) -> !(a ^ b)
4034 * (a < 0) -> (a & 0x80000000) oder a >> 31
4035 * (a >= 0) -> (a >> 31) ^ 1
4038 if(!mode_is_signed(cmp_mode)) {
4039 pnc |= ia32_pn_Cmp_Unsigned;
4042 new_cmp_right = try_create_Immediate(cmp_right, 0);
4043 if(new_cmp_right == NULL) {
4044 new_cmp_right = try_create_Immediate(cmp_left, 0);
4045 if(new_cmp_right != NULL) {
4046 pnc = get_inversed_pnc(pnc);
4047 new_cmp_left = be_transform_node(cmp_right);
4050 new_cmp_left = be_transform_node(cmp_left);
4052 if(new_cmp_right == NULL) {
4053 new_cmp_left = be_transform_node(cmp_left);
4054 new_cmp_right = be_transform_node(cmp_right);
4057 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4058 new_cmp_right, nomem, pnc);
4059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4065 * Transform and potentially renumber Proj nodes.
4067 static ir_node *gen_Proj(ir_node *node) {
4068 ir_graph *irg = current_ir_graph;
4069 dbg_info *dbgi = get_irn_dbg_info(node);
4070 ir_node *pred = get_Proj_pred(node);
4071 long proj = get_Proj_proj(node);
4073 if (is_Store(pred) || be_is_FrameStore(pred)) {
4074 if (proj == pn_Store_M) {
4075 return be_transform_node(pred);
4078 return new_r_Bad(irg);
4080 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4081 return gen_Proj_Load(node);
4082 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4083 return gen_Proj_DivMod(node);
4084 } else if (is_CopyB(pred)) {
4085 return gen_Proj_CopyB(node);
4086 } else if (is_Quot(pred)) {
4087 return gen_Proj_Quot(node);
4088 } else if (is_ia32_l_vfdiv(pred)) {
4089 return gen_Proj_l_vfdiv(node);
4090 } else if (be_is_SubSP(pred)) {
4091 return gen_Proj_be_SubSP(node);
4092 } else if (be_is_AddSP(pred)) {
4093 return gen_Proj_be_AddSP(node);
4094 } else if (be_is_Call(pred)) {
4095 return gen_Proj_be_Call(node);
4096 } else if (is_Cmp(pred)) {
4097 return gen_Proj_Cmp(node);
4098 } else if (get_irn_op(pred) == op_Start) {
4099 if (proj == pn_Start_X_initial_exec) {
4100 ir_node *block = get_nodes_block(pred);
4103 /* we exchange the ProjX with a jump */
4104 block = be_transform_node(block);
4105 jump = new_rd_Jmp(dbgi, irg, block);
4108 if (node == be_get_old_anchor(anchor_tls)) {
4109 return gen_Proj_tls(node);
4112 ir_node *new_pred = be_transform_node(pred);
4113 ir_node *block = be_transform_node(get_nodes_block(node));
4114 ir_mode *mode = get_irn_mode(node);
4115 if (mode_needs_gp_reg(mode)) {
4116 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4117 get_Proj_proj(node));
4118 #ifdef DEBUG_libfirm
4119 new_proj->node_nr = node->node_nr;
4125 return be_duplicate_node(node);
4129 * Enters all transform functions into the generic pointer
4131 static void register_transformers(void) {
4132 ir_op *op_Max, *op_Min, *op_Mulh;
4134 /* first clear the generic function pointer for all ops */
4135 clear_irp_opcodes_generic_func();
4137 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4138 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4175 /* transform ops from intrinsic lowering */
4195 /* GEN(ia32_l_vfist); TODO */
4197 GEN(ia32_l_X87toSSE);
4198 GEN(ia32_l_SSEtoX87);
4203 /* we should never see these nodes */
4218 /* handle generic backend nodes */
4229 /* set the register for all Unknown nodes */
4232 op_Max = get_op_Max();
4235 op_Min = get_op_Min();
4238 op_Mulh = get_op_Mulh();
4247 * Pre-transform all unknown and noreg nodes.
4249 static void ia32_pretransform_node(void *arch_cg) {
4250 ia32_code_gen_t *cg = arch_cg;
4252 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4253 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4254 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4255 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4256 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4257 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4260 /* do the transformation */
4261 void ia32_transform_graph(ia32_code_gen_t *cg) {
4262 register_transformers();
4264 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4267 void ia32_init_transform(void)
4269 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");