2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define TP_SFP_SIGN "ia32_sfp_sign"
77 #define TP_DFP_SIGN "ia32_dfp_sign"
78 #define TP_SFP_ABS "ia32_sfp_abs"
79 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
82 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
83 #define ENT_SFP_ABS "IA32_SFP_ABS"
84 #define ENT_DFP_ABS "IA32_DFP_ABS"
86 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
87 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
89 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
91 /** hold the current code generator during transformation */
92 static ia32_code_gen_t *env_cg = NULL;
93 static ir_node *initial_fpcw = NULL;
94 static heights_t *heights = NULL;
96 extern ir_op *get_op_Mulh(void);
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem);
102 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
109 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
112 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
114 ir_node *op2, ir_node *mem, ir_node *fpcw);
116 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *op);
119 /****************************************************************************************************
121 * | | | | / _| | | (_)
122 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
123 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
124 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
125 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
127 ****************************************************************************************************/
129 static ir_node *try_create_Immediate(ir_node *node,
130 char immediate_constraint_type);
132 static ir_node *create_immediate_or_transform(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
136 dbg_info *dbgi, ir_node *new_block,
140 * Return true if a mode can be stored in the GP register set
142 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
143 if(mode == mode_fpcw)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an atomic entity that is initialized with a tarval
186 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
188 tarval *tv = get_Const_tarval(cnst);
189 pmap_entry *e = pmap_find(isa->tv_ent, tv);
194 ir_mode *mode = get_irn_mode(cnst);
195 ir_type *tp = get_Const_type(cnst);
196 if (tp == firm_unknown_type)
197 tp = get_prim_type(isa->types, mode);
199 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
201 set_entity_ld_ident(res, get_entity_ident(res));
202 set_entity_visibility(res, visibility_local);
203 set_entity_variability(res, variability_constant);
204 set_entity_allocation(res, allocation_static);
206 /* we create a new entity here: It's initialization must resist on the
208 rem = current_ir_graph;
209 current_ir_graph = get_const_code_irg();
210 set_atomic_ent_value(res, new_Const_type(tv, tp));
211 current_ir_graph = rem;
213 pmap_insert(isa->tv_ent, tv, res);
221 static int is_Const_0(ir_node *node) {
225 return classify_Const(node) == CNST_NULL;
228 static int is_Const_1(ir_node *node) {
232 return classify_Const(node) == CNST_ONE;
235 static int is_Const_Minus_1(ir_node *node) {
241 mode = get_irn_mode(node);
242 if(!mode_is_signed(mode))
245 tv = get_Const_tarval(node);
248 return classify_tarval(tv) == CNST_ONE;
252 * Transforms a Const.
254 static ir_node *gen_Const(ir_node *node) {
255 ir_graph *irg = current_ir_graph;
256 ir_node *old_block = get_nodes_block(node);
257 ir_node *block = be_transform_node(old_block);
258 dbg_info *dbgi = get_irn_dbg_info(node);
259 ir_mode *mode = get_irn_mode(node);
261 if (mode_is_float(mode)) {
263 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
264 ir_node *nomem = new_NoMem();
267 cnst_classify_t clss = classify_Const(node);
269 if (USE_SSE2(env_cg)) {
270 if (clss == CNST_NULL) {
271 load = new_rd_ia32_xZero(dbgi, irg, block);
272 set_ia32_ls_mode(load, mode);
275 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
277 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
279 set_ia32_op_type(load, ia32_AddrModeS);
280 set_ia32_am_sc(load, floatent);
281 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
282 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
285 if (clss == CNST_NULL) {
286 load = new_rd_ia32_vfldz(dbgi, irg, block);
288 } else if (clss == CNST_ONE) {
289 load = new_rd_ia32_vfld1(dbgi, irg, block);
292 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
294 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
295 set_ia32_op_type(load, ia32_AddrModeS);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
303 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
305 /* Const Nodes before the initial IncSP are a bad idea, because
306 * they could be spilled and we have no SP ready at that point yet.
307 * So add a dependency to the initial frame pointer calculation to
308 * avoid that situation.
310 if (get_irg_start_block(irg) == block) {
311 add_irn_dep(load, get_irg_frame(irg));
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
318 tarval *tv = get_Const_tarval(node);
321 tv = tarval_convert_to(tv, mode_Iu);
323 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
325 panic("couldn't convert constant tarval (%+F)", node);
327 val = get_tarval_long(tv);
329 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
330 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
342 * Transforms a SymConst.
344 static ir_node *gen_SymConst(ir_node *node) {
345 ir_graph *irg = current_ir_graph;
346 ir_node *old_block = get_nodes_block(node);
347 ir_node *block = be_transform_node(old_block);
348 dbg_info *dbgi = get_irn_dbg_info(node);
349 ir_mode *mode = get_irn_mode(node);
352 if (mode_is_float(mode)) {
353 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
354 ir_node *nomem = new_NoMem();
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
359 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
360 set_ia32_am_sc(cnst, get_SymConst_entity(node));
361 set_ia32_use_frame(cnst);
365 if(get_SymConst_kind(node) != symconst_addr_ent) {
366 panic("backend only support symconst_addr_ent (at %+F)", node);
368 entity = get_SymConst_entity(node);
369 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
372 /* Const Nodes before the initial IncSP are a bad idea, because
373 * they could be spilled and we have no SP ready at that point yet
375 if (get_irg_start_block(irg) == block) {
376 add_irn_dep(cnst, get_irg_frame(irg));
379 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
384 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
385 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
386 static const struct {
388 const char *ent_name;
389 const char *cnst_str;
390 } names [ia32_known_const_max] = {
391 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
392 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
393 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
394 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
396 static ir_entity *ent_cache[ia32_known_const_max];
398 const char *tp_name, *ent_name, *cnst_str;
406 ent_name = names[kct].ent_name;
407 if (! ent_cache[kct]) {
408 tp_name = names[kct].tp_name;
409 cnst_str = names[kct].cnst_str;
411 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
413 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
414 tp = new_type_primitive(new_id_from_str(tp_name), mode);
415 /* these constants are loaded as part of an instruction, so they must be aligned
417 set_type_alignment_bytes(tp, 16);
418 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
420 set_entity_ld_ident(ent, get_entity_ident(ent));
421 set_entity_visibility(ent, visibility_local);
422 set_entity_variability(ent, variability_constant);
423 set_entity_allocation(ent, allocation_static);
425 /* we create a new entity here: It's initialization must resist on the
427 rem = current_ir_graph;
428 current_ir_graph = get_const_code_irg();
429 cnst = new_Const(mode, tv);
430 current_ir_graph = rem;
432 set_atomic_ent_value(ent, cnst);
434 /* cache the entry */
435 ent_cache[kct] = ent;
438 return ent_cache[kct];
443 * Prints the old node name on cg obst and returns a pointer to it.
445 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
446 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
448 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
449 obstack_1grow(isa->name_obst, 0);
450 return obstack_finish(isa->name_obst);
454 static int use_source_address_mode(ir_node *block, ir_node *node,
463 load = get_Proj_pred(node);
464 pn = get_Proj_proj(node);
465 if(!is_Load(load) || pn != pn_Load_res)
467 if(get_nodes_block(load) != block)
469 /* we only use address mode if we're the only user of the load */
470 if(get_irn_n_edges(node) > 1)
473 mode = get_irn_mode(node);
474 if(!mode_needs_gp_reg(mode))
476 if(get_mode_size_bits(mode) != 32)
479 /* don't do AM if other node inputs depend on the load (via mem-proj) */
480 if(other != NULL && get_nodes_block(other) == block
481 && heights_reachable_in_block(heights, other, load))
487 typedef struct ia32_address_mode_t ia32_address_mode_t;
488 struct ia32_address_mode_t {
492 ia32_op_type_t op_type;
499 static void build_address(ia32_address_mode_t *am, ir_node *node)
501 ia32_address_t *addr = &am->addr;
502 ir_node *load = get_Proj_pred(node);
503 ir_node *ptr = get_Load_ptr(load);
504 ir_node *mem = get_Load_mem(load);
505 ir_node *new_mem = be_transform_node(mem);
509 am->ls_mode = get_Load_mode(load);
510 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
512 /* construct load address */
513 ia32_create_address_mode(addr, ptr, 0);
518 base = ia32_new_NoReg_gp(env_cg);
520 base = be_transform_node(base);
524 index = ia32_new_NoReg_gp(env_cg);
526 index = be_transform_node(index);
534 static void set_address(ir_node *node, ia32_address_t *addr)
536 set_ia32_am_scale(node, addr->scale);
537 set_ia32_am_sc(node, addr->symconst_ent);
538 set_ia32_am_offs_int(node, addr->offset);
539 if(addr->symconst_sign)
540 set_ia32_am_sc_sign(node);
542 set_ia32_use_frame(node);
543 set_ia32_frame_ent(node, addr->frame_entity);
546 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
548 set_address(node, &am->addr);
550 set_ia32_op_type(node, am->op_type);
551 set_ia32_ls_mode(node, am->ls_mode);
553 set_ia32_commutative(node);
556 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
557 ir_node *op1, ir_node *op2, int commutative,
558 int use_am_and_immediates, int use_am)
560 ia32_address_t *addr = &am->addr;
561 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
565 memset(am, 0, sizeof(am[0]));
567 new_op2 = try_create_Immediate(op2, 0);
568 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
569 build_address(am, op2);
570 new_op1 = be_transform_node(op1);
572 am->op_type = ia32_AddrModeS;
573 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
574 use_am && use_source_address_mode(block, op1, op2)) {
575 build_address(am, op1);
576 if(new_op2 != NULL) {
579 new_op1 = be_transform_node(op2);
583 am->op_type = ia32_AddrModeS;
585 new_op1 = be_transform_node(op1);
587 new_op2 = be_transform_node(op2);
588 am->op_type = ia32_Normal;
590 if(addr->base == NULL)
591 addr->base = noreg_gp;
592 if(addr->index == NULL)
593 addr->index = noreg_gp;
594 if(addr->mem == NULL)
595 addr->mem = new_NoMem();
597 am->new_op1 = new_op1;
598 am->new_op2 = new_op2;
599 am->commutative = commutative;
602 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
604 ir_graph *irg = current_ir_graph;
608 if(am->mem_proj == NULL)
611 /* we have to create a mode_T so the old MemProj can attach to us */
612 mode = get_irn_mode(node);
613 load = get_Proj_pred(am->mem_proj);
615 mark_irn_visited(load);
616 be_set_transformed_node(load, node);
619 set_irn_mode(node, mode_T);
620 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
627 * Construct a standard binary operation, set AM and immediate if required.
629 * @param op1 The first operand
630 * @param op2 The second operand
631 * @param func The node constructor function
632 * @return The constructed ia32 node.
634 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
635 construct_binop_func *func, int commutative)
637 ir_node *src_block = get_nodes_block(node);
638 ir_node *block = be_transform_node(src_block);
639 ir_graph *irg = current_ir_graph;
640 dbg_info *dbgi = get_irn_dbg_info(node);
642 ia32_address_mode_t am;
643 ia32_address_t *addr = &am.addr;
645 match_arguments(&am, src_block, op1, op2, commutative, 0, 1);
647 new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
648 am.new_op2, addr->mem);
649 set_am_attributes(new_node, &am);
650 /* we can't use source address mode anymore when using immediates */
651 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
652 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
653 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
655 new_node = fix_mem_proj(new_node, &am);
661 * Construct a standard binary operation, set AM and immediate if required.
663 * @param op1 The first operand
664 * @param op2 The second operand
665 * @param func The node constructor function
666 * @return The constructed ia32 node.
668 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
669 construct_binop_func *func)
671 ir_node *block = be_transform_node(get_nodes_block(node));
672 ir_node *new_op1 = be_transform_node(op1);
673 ir_node *new_op2 = be_transform_node(op2);
674 ir_node *new_node = NULL;
675 dbg_info *dbgi = get_irn_dbg_info(node);
676 ir_graph *irg = current_ir_graph;
677 ir_mode *mode = get_irn_mode(node);
678 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
679 ir_node *nomem = new_NoMem();
681 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
683 if (is_op_commutative(get_irn_op(node))) {
684 set_ia32_commutative(new_node);
686 set_ia32_ls_mode(new_node, mode);
688 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
693 static ir_node *get_fpcw(void)
696 if(initial_fpcw != NULL)
699 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
700 &ia32_fp_cw_regs[REG_FPCW]);
701 initial_fpcw = be_transform_node(fpcw);
707 * Construct a standard binary operation, set AM and immediate if required.
709 * @param op1 The first operand
710 * @param op2 The second operand
711 * @param func The node constructor function
712 * @return The constructed ia32 node.
714 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
715 construct_binop_float_func *func)
717 ir_node *block = be_transform_node(get_nodes_block(node));
718 ir_node *new_op1 = be_transform_node(op1);
719 ir_node *new_op2 = be_transform_node(op2);
720 ir_node *new_node = NULL;
721 dbg_info *dbgi = get_irn_dbg_info(node);
722 ir_graph *irg = current_ir_graph;
723 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
724 ir_node *nomem = new_NoMem();
726 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
728 if (is_op_commutative(get_irn_op(node))) {
729 set_ia32_commutative(new_node);
732 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
738 * Construct a shift/rotate binary operation, sets AM and immediate if required.
740 * @param op1 The first operand
741 * @param op2 The second operand
742 * @param func The node constructor function
743 * @return The constructed ia32 node.
745 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
746 construct_shift_func *func)
748 dbg_info *dbgi = get_irn_dbg_info(node);
749 ir_graph *irg = current_ir_graph;
750 ir_node *block = get_nodes_block(node);
751 ir_node *new_block = be_transform_node(block);
752 ir_node *new_op1 = be_transform_node(op1);
753 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
756 assert(! mode_is_float(get_irn_mode(node))
757 && "Shift/Rotate with float not supported");
759 res = func(dbgi, irg, new_block, new_op1, new_op2);
760 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
762 /* lowered shift instruction may have a dependency operand, handle it here */
763 if (get_irn_arity(node) == 3) {
764 /* we have a dependency */
765 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
766 add_irn_dep(res, new_dep);
774 * Construct a standard unary operation, set AM and immediate if required.
776 * @param op The operand
777 * @param func The node constructor function
778 * @return The constructed ia32 node.
780 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
782 ir_node *block = be_transform_node(get_nodes_block(node));
783 ir_node *new_op = be_transform_node(op);
784 ir_node *new_node = NULL;
785 ir_graph *irg = current_ir_graph;
786 dbg_info *dbgi = get_irn_dbg_info(node);
788 new_node = func(dbgi, irg, block, new_op);
790 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
795 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
796 ia32_address_t *addr)
798 ir_graph *irg = current_ir_graph;
799 ir_node *base = addr->base;
800 ir_node *index = addr->index;
804 base = ia32_new_NoReg_gp(env_cg);
806 base = be_transform_node(base);
810 index = ia32_new_NoReg_gp(env_cg);
812 index = be_transform_node(index);
815 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
816 set_address(res, addr);
821 static int am_has_immediates(const ia32_address_t *addr)
823 return addr->offset != 0 || addr->symconst_ent != NULL
824 || addr->frame_entity || addr->use_frame;
828 * Creates an ia32 Add.
830 * @return the created ia32 Add node
832 static ir_node *gen_Add(ir_node *node) {
833 ir_node *block = be_transform_node(get_nodes_block(node));
834 ir_node *op1 = get_Add_left(node);
835 ir_node *op2 = get_Add_right(node);
838 ir_graph *irg = current_ir_graph;
839 dbg_info *dbgi = get_irn_dbg_info(node);
840 ir_mode *mode = get_irn_mode(node);
841 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
842 ir_node *src_block = get_nodes_block(node);
843 ir_node *add_immediate_op;
845 ia32_address_mode_t am;
847 if (mode_is_float(mode)) {
848 if (USE_SSE2(env_cg))
849 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
851 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
856 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
857 * 1. Add with immediate -> Lea
858 * 2. Add with possible source address mode -> Add
859 * 3. Otherwise -> Lea
861 memset(&addr, 0, sizeof(addr));
862 ia32_create_address_mode(&addr, node, 1);
863 add_immediate_op = NULL;
865 if(addr.base == NULL && addr.index == NULL) {
866 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
867 addr.symconst_sign, addr.offset);
868 add_irn_dep(new_op, get_irg_frame(irg));
869 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
872 /* add with immediate? */
873 if(addr.index == NULL) {
874 add_immediate_op = addr.base;
875 } else if(addr.base == NULL && addr.scale == 0) {
876 add_immediate_op = addr.index;
879 if(add_immediate_op != NULL) {
880 if(!am_has_immediates(&addr)) {
882 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
885 return be_transform_node(add_immediate_op);
888 new_op = create_lea_from_address(dbgi, block, &addr);
889 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
893 /* test if we can use source address mode */
894 memset(&am, 0, sizeof(am));
896 if(use_source_address_mode(src_block, op2, op1)) {
897 build_address(&am, op2);
898 new_op1 = be_transform_node(op1);
899 } else if(use_source_address_mode(src_block, op1, op2)) {
900 build_address(&am, op1);
901 new_op1 = be_transform_node(op2);
903 /* construct an Add with source address mode */
904 if(new_op1 != NULL) {
905 ia32_address_t *am_addr = &am.addr;
906 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
907 am_addr->index, new_op1, noreg, am_addr->mem);
908 set_address(new_op, am_addr);
909 set_ia32_op_type(new_op, ia32_AddrModeS);
910 set_ia32_ls_mode(new_op, am.ls_mode);
911 set_ia32_commutative(new_op);
912 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
914 new_op = fix_mem_proj(new_op, &am);
919 /* otherwise construct a lea */
920 new_op = create_lea_from_address(dbgi, block, &addr);
921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
926 * Creates an ia32 Mul.
928 * @return the created ia32 Mul node
930 static ir_node *gen_Mul(ir_node *node) {
931 ir_node *op1 = get_Mul_left(node);
932 ir_node *op2 = get_Mul_right(node);
933 ir_mode *mode = get_irn_mode(node);
935 if (mode_is_float(mode)) {
936 if (USE_SSE2(env_cg))
937 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
939 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
943 for the lower 32bit of the result it doesn't matter whether we use
944 signed or unsigned multiplication so we use IMul as it has fewer
947 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
951 * Creates an ia32 Mulh.
952 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
953 * this result while Mul returns the lower 32 bit.
955 * @return the created ia32 Mulh node
957 static ir_node *gen_Mulh(ir_node *node) {
958 ir_node *block = be_transform_node(get_nodes_block(node));
959 ir_node *op1 = get_irn_n(node, 0);
960 ir_node *new_op1 = be_transform_node(op1);
961 ir_node *op2 = get_irn_n(node, 1);
962 ir_node *new_op2 = be_transform_node(op2);
963 ir_graph *irg = current_ir_graph;
964 dbg_info *dbgi = get_irn_dbg_info(node);
965 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
966 ir_mode *mode = get_irn_mode(node);
967 ir_node *proj_EDX, *res;
969 assert(!mode_is_float(mode) && "Mulh with float not supported");
970 if (mode_is_signed(mode)) {
971 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
972 new_op2, new_NoMem());
974 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
978 set_ia32_commutative(res);
980 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
988 * Creates an ia32 And.
990 * @return The created ia32 And node
992 static ir_node *gen_And(ir_node *node) {
993 ir_node *op1 = get_And_left(node);
994 ir_node *op2 = get_And_right(node);
995 assert(! mode_is_float(get_irn_mode(node)));
997 /* is it a zero extension? */
999 tarval *tv = get_Const_tarval(op2);
1000 long v = get_tarval_long(tv);
1002 if (v == 0xFF || v == 0xFFFF) {
1003 dbg_info *dbgi = get_irn_dbg_info(node);
1004 ir_node *block = be_transform_node(get_nodes_block(node));
1005 ir_node *new_op = be_transform_node(op1);
1012 assert(v == 0xFFFF);
1015 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
1016 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1022 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1028 * Creates an ia32 Or.
1030 * @return The created ia32 Or node
1032 static ir_node *gen_Or(ir_node *node) {
1033 ir_node *op1 = get_Or_left(node);
1034 ir_node *op2 = get_Or_right(node);
1036 assert (! mode_is_float(get_irn_mode(node)));
1037 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1043 * Creates an ia32 Eor.
1045 * @return The created ia32 Eor node
1047 static ir_node *gen_Eor(ir_node *node) {
1048 ir_node *op1 = get_Eor_left(node);
1049 ir_node *op2 = get_Eor_right(node);
1051 assert(! mode_is_float(get_irn_mode(node)));
1052 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1057 * Creates an ia32 Sub.
1059 * @return The created ia32 Sub node
1061 static ir_node *gen_Sub(ir_node *node) {
1062 ir_node *op1 = get_Sub_left(node);
1063 ir_node *op2 = get_Sub_right(node);
1064 ir_mode *mode = get_irn_mode(node);
1066 if (mode_is_float(mode)) {
1067 if (USE_SSE2(env_cg))
1068 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1070 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1074 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1078 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1084 * Generates an ia32 DivMod with additional infrastructure for the
1085 * register allocator if needed.
1087 * @param dividend -no comment- :)
1088 * @param divisor -no comment- :)
1089 * @param dm_flav flavour_Div/Mod/DivMod
1090 * @return The created ia32 DivMod node
1092 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1093 ir_node *divisor, ia32_op_flavour_t dm_flav)
1095 ir_node *block = be_transform_node(get_nodes_block(node));
1096 ir_node *new_dividend = be_transform_node(dividend);
1097 ir_node *new_divisor = be_transform_node(divisor);
1098 ir_graph *irg = current_ir_graph;
1099 dbg_info *dbgi = get_irn_dbg_info(node);
1100 ir_mode *mode = get_irn_mode(node);
1101 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1102 ir_node *res, *proj_div, *proj_mod;
1103 ir_node *sign_extension;
1104 ir_node *mem, *new_mem;
1107 proj_div = proj_mod = NULL;
1111 mem = get_Div_mem(node);
1112 mode = get_Div_resmode(node);
1113 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1114 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1117 mem = get_Mod_mem(node);
1118 mode = get_Mod_resmode(node);
1119 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1120 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1122 case flavour_DivMod:
1123 mem = get_DivMod_mem(node);
1124 mode = get_DivMod_resmode(node);
1125 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1126 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1127 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1130 panic("invalid divmod flavour!");
1132 new_mem = be_transform_node(mem);
1134 if (mode_is_signed(mode)) {
1135 /* in signed mode, we need to sign extend the dividend */
1136 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1137 add_irn_dep(produceval, get_irg_frame(irg));
1138 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1141 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1142 add_irn_dep(sign_extension, get_irg_frame(irg));
1145 if (mode_is_signed(mode)) {
1146 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1147 sign_extension, new_divisor, new_mem, dm_flav);
1149 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1150 sign_extension, new_divisor, new_mem, dm_flav);
1153 set_ia32_exc_label(res, has_exc);
1154 set_irn_pinned(res, get_irn_pinned(node));
1156 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1163 * Wrapper for generate_DivMod. Sets flavour_Mod.
1166 static ir_node *gen_Mod(ir_node *node) {
1167 return generate_DivMod(node, get_Mod_left(node),
1168 get_Mod_right(node), flavour_Mod);
1172 * Wrapper for generate_DivMod. Sets flavour_Div.
1175 static ir_node *gen_Div(ir_node *node) {
1176 return generate_DivMod(node, get_Div_left(node),
1177 get_Div_right(node), flavour_Div);
1181 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1183 static ir_node *gen_DivMod(ir_node *node) {
1184 return generate_DivMod(node, get_DivMod_left(node),
1185 get_DivMod_right(node), flavour_DivMod);
1191 * Creates an ia32 floating Div.
1193 * @return The created ia32 xDiv node
1195 static ir_node *gen_Quot(ir_node *node) {
1196 ir_node *block = be_transform_node(get_nodes_block(node));
1197 ir_node *op1 = get_Quot_left(node);
1198 ir_node *new_op1 = be_transform_node(op1);
1199 ir_node *op2 = get_Quot_right(node);
1200 ir_node *new_op2 = be_transform_node(op2);
1201 ir_graph *irg = current_ir_graph;
1202 dbg_info *dbgi = get_irn_dbg_info(node);
1203 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1204 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1207 if (USE_SSE2(env_cg)) {
1208 ir_mode *mode = get_irn_mode(op1);
1209 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
1211 set_ia32_ls_mode(new_op, mode);
1213 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1214 new_op2, nomem, get_fpcw());
1216 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1222 * Creates an ia32 Shl.
1224 * @return The created ia32 Shl node
1226 static ir_node *gen_Shl(ir_node *node) {
1227 ir_node *right = get_Shl_right(node);
1229 /* test whether we can build a lea */
1230 if(is_Const(right)) {
1231 tarval *tv = get_Const_tarval(right);
1232 if(tarval_is_long(tv)) {
1233 long val = get_tarval_long(tv);
1234 if(val >= 0 && val <= 3) {
1235 ir_graph *irg = current_ir_graph;
1236 dbg_info *dbgi = get_irn_dbg_info(node);
1237 ir_node *block = be_transform_node(get_nodes_block(node));
1238 ir_node *base = ia32_new_NoReg_gp(env_cg);
1239 ir_node *index = be_transform_node(get_Shl_left(node));
1242 = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1243 set_ia32_am_scale(res, val);
1244 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1250 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1257 * Creates an ia32 Shr.
1259 * @return The created ia32 Shr node
1261 static ir_node *gen_Shr(ir_node *node) {
1262 return gen_shift_binop(node, get_Shr_left(node),
1263 get_Shr_right(node), new_rd_ia32_Shr);
1269 * Creates an ia32 Sar.
1271 * @return The created ia32 Shrs node
1273 static ir_node *gen_Shrs(ir_node *node) {
1274 ir_node *left = get_Shrs_left(node);
1275 ir_node *right = get_Shrs_right(node);
1276 ir_mode *mode = get_irn_mode(node);
1277 if(is_Const(right) && mode == mode_Is) {
1278 tarval *tv = get_Const_tarval(right);
1279 long val = get_tarval_long(tv);
1281 /* this is a sign extension */
1282 ir_graph *irg = current_ir_graph;
1283 dbg_info *dbgi = get_irn_dbg_info(node);
1284 ir_node *block = be_transform_node(get_nodes_block(node));
1286 ir_node *new_op = be_transform_node(op);
1287 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1288 add_irn_dep(pval, get_irg_frame(irg));
1290 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1294 /* 8 or 16 bit sign extension? */
1295 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1296 ir_node *shl_left = get_Shl_left(left);
1297 ir_node *shl_right = get_Shl_right(left);
1298 if(is_Const(shl_right)) {
1299 tarval *tv1 = get_Const_tarval(right);
1300 tarval *tv2 = get_Const_tarval(shl_right);
1301 if(tv1 == tv2 && tarval_is_long(tv1)) {
1302 long val = get_tarval_long(tv1);
1303 if(val == 16 || val == 24) {
1304 dbg_info *dbgi = get_irn_dbg_info(node);
1305 ir_node *block = be_transform_node(get_nodes_block(node));
1306 ir_node *new_op = be_transform_node(shl_left);
1316 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1318 SET_IA32_ORIG_NODE(res,
1319 ia32_get_old_node_name(env_cg, node));
1327 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1333 * Creates an ia32 RotL.
1335 * @param op1 The first operator
1336 * @param op2 The second operator
1337 * @return The created ia32 RotL node
1339 static ir_node *gen_RotL(ir_node *node,
1340 ir_node *op1, ir_node *op2) {
1341 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1347 * Creates an ia32 RotR.
1348 * NOTE: There is no RotR with immediate because this would always be a RotL
1349 * "imm-mode_size_bits" which can be pre-calculated.
1351 * @param op1 The first operator
1352 * @param op2 The second operator
1353 * @return The created ia32 RotR node
1355 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1357 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1363 * Creates an ia32 RotR or RotL (depending on the found pattern).
1365 * @return The created ia32 RotL or RotR node
1367 static ir_node *gen_Rot(ir_node *node) {
1368 ir_node *rotate = NULL;
1369 ir_node *op1 = get_Rot_left(node);
1370 ir_node *op2 = get_Rot_right(node);
1372 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1373 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1374 that means we can create a RotR instead of an Add and a RotL */
1376 if (get_irn_op(op2) == op_Add) {
1378 ir_node *left = get_Add_left(add);
1379 ir_node *right = get_Add_right(add);
1380 if (is_Const(right)) {
1381 tarval *tv = get_Const_tarval(right);
1382 ir_mode *mode = get_irn_mode(node);
1383 long bits = get_mode_size_bits(mode);
1385 if (get_irn_op(left) == op_Minus &&
1386 tarval_is_long(tv) &&
1387 get_tarval_long(tv) == bits)
1389 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1390 rotate = gen_RotR(node, op1, get_Minus_op(left));
1395 if (rotate == NULL) {
1396 rotate = gen_RotL(node, op1, op2);
1405 * Transforms a Minus node.
1407 * @param op The Minus operand
1408 * @return The created ia32 Minus node
1410 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1411 ir_node *block = be_transform_node(get_nodes_block(node));
1412 ir_graph *irg = current_ir_graph;
1413 dbg_info *dbgi = get_irn_dbg_info(node);
1414 ir_mode *mode = get_irn_mode(node);
1419 if (mode_is_float(mode)) {
1420 ir_node *new_op = be_transform_node(op);
1421 if (USE_SSE2(env_cg)) {
1422 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1423 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1424 ir_node *nomem = new_rd_NoMem(irg);
1426 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1428 size = get_mode_size_bits(mode);
1429 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1431 set_ia32_am_sc(res, ent);
1432 set_ia32_op_type(res, ia32_AddrModeS);
1433 set_ia32_ls_mode(res, mode);
1435 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1438 res = gen_unop(node, op, new_rd_ia32_Neg);
1441 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1447 * Transforms a Minus node.
1449 * @return The created ia32 Minus node
1451 static ir_node *gen_Minus(ir_node *node) {
1452 return gen_Minus_ex(node, get_Minus_op(node));
1455 static ir_node *create_Immediate_from_int(int val)
1457 ir_graph *irg = current_ir_graph;
1458 ir_node *start_block = get_irg_start_block(irg);
1459 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1460 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1465 static ir_node *gen_bin_Not(ir_node *node)
1467 ir_graph *irg = current_ir_graph;
1468 dbg_info *dbgi = get_irn_dbg_info(node);
1469 ir_node *block = be_transform_node(get_nodes_block(node));
1470 ir_node *op = get_Not_op(node);
1471 ir_node *new_op = be_transform_node(op);
1472 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1473 ir_node *nomem = new_NoMem();
1474 ir_node *one = create_Immediate_from_int(1);
1476 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1480 * Transforms a Not node.
1482 * @return The created ia32 Not node
1484 static ir_node *gen_Not(ir_node *node) {
1485 ir_node *op = get_Not_op(node);
1486 ir_mode *mode = get_irn_mode(node);
1488 if(mode == mode_b) {
1489 return gen_bin_Not(node);
1492 assert (! mode_is_float(get_irn_mode(node)));
1493 return gen_unop(node, op, new_rd_ia32_Not);
1499 * Transforms an Abs node.
1501 * @return The created ia32 Abs node
1503 static ir_node *gen_Abs(ir_node *node) {
1504 ir_node *block = be_transform_node(get_nodes_block(node));
1505 ir_node *op = get_Abs_op(node);
1506 ir_node *new_op = be_transform_node(op);
1507 ir_graph *irg = current_ir_graph;
1508 dbg_info *dbgi = get_irn_dbg_info(node);
1509 ir_mode *mode = get_irn_mode(node);
1510 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1511 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1512 ir_node *nomem = new_NoMem();
1517 if (mode_is_float(mode)) {
1518 if (USE_SSE2(env_cg)) {
1519 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1521 size = get_mode_size_bits(mode);
1522 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1524 set_ia32_am_sc(res, ent);
1526 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1528 set_ia32_op_type(res, ia32_AddrModeS);
1529 set_ia32_ls_mode(res, mode);
1532 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1533 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1538 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1541 add_irn_dep(pval, get_irg_frame(irg));
1542 SET_IA32_ORIG_NODE(sign_extension,
1543 ia32_get_old_node_name(env_cg, node));
1545 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1546 sign_extension, nomem);
1547 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1549 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1550 sign_extension, nomem);
1551 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1558 * Transforms a Load.
1560 * @return the created ia32 Load node
1562 static ir_node *gen_Load(ir_node *node) {
1563 ir_node *old_block = get_nodes_block(node);
1564 ir_node *block = be_transform_node(old_block);
1565 ir_node *ptr = get_Load_ptr(node);
1566 ir_node *mem = get_Load_mem(node);
1567 ir_node *new_mem = be_transform_node(mem);
1570 ir_graph *irg = current_ir_graph;
1571 dbg_info *dbgi = get_irn_dbg_info(node);
1572 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1573 ir_mode *mode = get_Load_mode(node);
1576 ia32_address_t addr;
1578 /* construct load address */
1579 memset(&addr, 0, sizeof(addr));
1580 ia32_create_address_mode(&addr, ptr, 0);
1587 base = be_transform_node(base);
1593 index = be_transform_node(index);
1596 if (mode_is_float(mode)) {
1597 if (USE_SSE2(env_cg)) {
1598 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1600 res_mode = mode_xmm;
1602 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1604 res_mode = mode_vfp;
1610 /* create a conv node with address mode for smaller modes */
1611 if(get_mode_size_bits(mode) < 32) {
1612 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
1615 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1620 set_irn_pinned(new_op, get_irn_pinned(node));
1621 set_ia32_op_type(new_op, ia32_AddrModeS);
1622 set_ia32_ls_mode(new_op, mode);
1623 set_address(new_op, &addr);
1625 /* make sure we are scheduled behind the initial IncSP/Barrier
1626 * to avoid spills being placed before it
1628 if (block == get_irg_start_block(irg)) {
1629 add_irn_dep(new_op, get_irg_frame(irg));
1632 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1633 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1638 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1639 ir_node *ptr, ir_mode *mode, ir_node *other)
1646 /* we only use address mode if we're the only user of the load */
1647 if(get_irn_n_edges(node) > 1)
1650 load = get_Proj_pred(node);
1653 if(get_nodes_block(load) != block)
1656 /* Store should be attached to the load */
1657 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1659 /* store should have the same pointer as the load */
1660 if(get_Load_ptr(load) != ptr)
1663 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1664 if(other != NULL && get_nodes_block(other) == block
1665 && heights_reachable_in_block(heights, other, load))
1668 assert(get_Load_mode(load) == mode);
1673 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1674 ir_node *mem, ir_node *ptr, ir_mode *mode,
1675 construct_binop_dest_func *func, int commutative)
1677 ir_node *src_block = get_nodes_block(node);
1679 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1680 ir_graph *irg = current_ir_graph;
1684 ia32_address_mode_t am;
1685 ia32_address_t *addr = &am.addr;
1686 memset(&am, 0, sizeof(am));
1688 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1689 build_address(&am, op1);
1690 new_op = create_immediate_or_transform(op2, 0);
1691 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1692 build_address(&am, op2);
1693 new_op = create_immediate_or_transform(op1, 0);
1698 if(addr->base == NULL)
1699 addr->base = noreg_gp;
1700 if(addr->index == NULL)
1701 addr->index = noreg_gp;
1702 if(addr->mem == NULL)
1703 addr->mem = new_NoMem();
1705 dbgi = get_irn_dbg_info(node);
1706 block = be_transform_node(src_block);
1707 new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
1709 set_address(new_node, addr);
1710 set_ia32_op_type(new_node, ia32_AddrModeD);
1711 set_ia32_ls_mode(new_node, mode);
1712 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1717 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1718 ir_node *ptr, ir_mode *mode,
1719 construct_unop_dest_func *func)
1721 ir_node *src_block = get_nodes_block(node);
1723 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1724 ir_graph *irg = current_ir_graph;
1727 ia32_address_mode_t am;
1728 ia32_address_t *addr = &am.addr;
1729 memset(&am, 0, sizeof(am));
1731 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1734 build_address(&am, op);
1736 if(addr->base == NULL)
1737 addr->base = noreg_gp;
1738 if(addr->index == NULL)
1739 addr->index = noreg_gp;
1740 if(addr->mem == NULL)
1741 addr->mem = new_NoMem();
1743 dbgi = get_irn_dbg_info(node);
1744 block = be_transform_node(src_block);
1745 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1746 set_address(new_node, addr);
1747 set_ia32_op_type(new_node, ia32_AddrModeD);
1748 set_ia32_ls_mode(new_node, mode);
1749 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1754 static ir_node *try_create_dest_am(ir_node *node) {
1755 ir_node *val = get_Store_value(node);
1756 ir_node *mem = get_Store_mem(node);
1757 ir_node *ptr = get_Store_ptr(node);
1758 ir_mode *mode = get_irn_mode(val);
1763 /* handle only GP modes for now... */
1764 if(!mode_needs_gp_reg(mode))
1766 if(get_mode_size_bits(mode) != 32)
1769 /* store must be the only user of the val node */
1770 if(get_irn_n_edges(val) > 1)
1773 switch(get_irn_opcode(val)) {
1775 op1 = get_Add_left(val);
1776 op2 = get_Add_right(val);
1777 if(is_Const_1(op2)) {
1778 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1779 new_rd_ia32_IncMem);
1781 } else if(is_Const_Minus_1(op2)) {
1782 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1783 new_rd_ia32_DecMem);
1786 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1787 new_rd_ia32_AddMem, 1);
1790 op1 = get_Sub_left(val);
1791 op2 = get_Sub_right(val);
1792 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1793 new_rd_ia32_SubMem, 0);
1796 op1 = get_And_left(val);
1797 op2 = get_And_right(val);
1798 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1799 new_rd_ia32_AndMem, 1);
1802 op1 = get_Or_left(val);
1803 op2 = get_Or_right(val);
1804 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1805 new_rd_ia32_OrMem, 1);
1808 op1 = get_Eor_left(val);
1809 op2 = get_Eor_right(val);
1810 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1811 new_rd_ia32_XorMem, 1);
1814 op1 = get_Shl_left(val);
1815 op2 = get_Shl_right(val);
1816 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1817 new_rd_ia32_ShlMem, 0);
1820 op1 = get_Shr_left(val);
1821 op2 = get_Shr_right(val);
1822 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1823 new_rd_ia32_ShrMem, 0);
1826 op1 = get_Shrs_left(val);
1827 op2 = get_Shrs_right(val);
1828 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1829 new_rd_ia32_SarMem, 0);
1832 op1 = get_Rot_left(val);
1833 op2 = get_Rot_right(val);
1834 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1835 new_rd_ia32_RolMem, 0);
1837 /* TODO: match ROR patterns... */
1839 op1 = get_Minus_op(val);
1840 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1843 /* TODO this would be ^ 1 with DestAM */
1846 op1 = get_Not_op(val);
1847 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1857 * Transforms a Store.
1859 * @return the created ia32 Store node
1861 static ir_node *gen_Store(ir_node *node) {
1862 ir_node *block = be_transform_node(get_nodes_block(node));
1863 ir_node *ptr = get_Store_ptr(node);
1866 ir_node *val = get_Store_value(node);
1868 ir_node *mem = get_Store_mem(node);
1869 ir_node *new_mem = be_transform_node(mem);
1870 ir_graph *irg = current_ir_graph;
1871 dbg_info *dbgi = get_irn_dbg_info(node);
1872 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1873 ir_mode *mode = get_irn_mode(val);
1875 ia32_address_t addr;
1877 /* check for destination address mode */
1878 new_op = try_create_dest_am(node);
1882 /* construct store address */
1883 memset(&addr, 0, sizeof(addr));
1884 ia32_create_address_mode(&addr, ptr, 0);
1891 base = be_transform_node(base);
1897 index = be_transform_node(index);
1900 if (mode_is_float(mode)) {
1901 new_val = be_transform_node(val);
1902 if (USE_SSE2(env_cg)) {
1903 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
1906 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
1910 new_val = create_immediate_or_transform(val, 0);
1914 if (get_mode_size_bits(mode) == 8) {
1915 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
1918 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
1923 set_irn_pinned(new_op, get_irn_pinned(node));
1924 set_ia32_op_type(new_op, ia32_AddrModeD);
1925 set_ia32_ls_mode(new_op, mode);
1927 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1928 set_address(new_op, &addr);
1929 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1934 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1935 ir_node *cmp_left, ir_node *cmp_right,
1942 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1943 ia32_address_mode_t am;
1944 ia32_address_t *addr = &am.addr;
1946 if(cmp_right != NULL && !is_Const_0(cmp_right))
1949 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1950 mode = get_irn_mode(cmp_left);
1951 arg_left = get_And_left(cmp_left);
1952 arg_right = get_And_right(cmp_left);
1954 mode = get_irn_mode(cmp_left);
1955 arg_left = cmp_left;
1956 arg_right = cmp_left;
1962 assert(get_mode_size_bits(mode) <= 32);
1963 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
1965 pnc = get_inversed_pnc(pnc);
1967 if(get_mode_size_bits(mode) == 8) {
1968 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1969 addr->index, am.new_op1, am.new_op2,
1972 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1973 addr->index, am.new_op1, am.new_op2,
1976 set_am_attributes(res, &am);
1977 set_ia32_ls_mode(res, mode);
1979 res = fix_mem_proj(res, &am);
1984 static ir_node *create_Switch(ir_node *node)
1986 ir_graph *irg = current_ir_graph;
1987 dbg_info *dbgi = get_irn_dbg_info(node);
1988 ir_node *block = be_transform_node(get_nodes_block(node));
1989 ir_node *sel = get_Cond_selector(node);
1990 ir_node *new_sel = be_transform_node(sel);
1992 int switch_min = INT_MAX;
1993 const ir_edge_t *edge;
1995 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1997 /* determine the smallest switch case value */
1998 foreach_out_edge(node, edge) {
1999 ir_node *proj = get_edge_src_irn(edge);
2000 int pn = get_Proj_proj(proj);
2005 if (switch_min != 0) {
2006 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2008 /* if smallest switch case is not 0 we need an additional sub */
2009 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2010 add_ia32_am_offs_int(new_sel, -switch_min);
2011 set_ia32_op_type(new_sel, ia32_AddrModeS);
2013 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2016 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2017 set_ia32_pncode(res, get_Cond_defaultProj(node));
2019 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2025 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2027 * @return The transformed node.
2029 static ir_node *gen_Cond(ir_node *node) {
2030 ir_node *src_block = get_nodes_block(node);
2031 ir_node *block = be_transform_node(src_block);
2032 ir_graph *irg = current_ir_graph;
2033 dbg_info *dbgi = get_irn_dbg_info(node);
2034 ir_node *sel = get_Cond_selector(node);
2035 ir_mode *sel_mode = get_irn_mode(sel);
2036 ir_node *res = NULL;
2037 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2038 ir_node *nomem = new_NoMem();
2048 if (sel_mode != mode_b) {
2049 return create_Switch(node);
2052 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2053 /* it's some mode_b value but not a direct comparison -> create a
2055 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2056 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2060 /* address mode makes only sense when we're the only user of the cmp */
2061 use_am = get_irn_n_edges(node) <= 1;
2063 cmp = get_Proj_pred(sel);
2064 cmp_a = get_Cmp_left(cmp);
2065 cmp_b = get_Cmp_right(cmp);
2066 cmp_mode = get_irn_mode(cmp_a);
2067 pnc = get_Proj_proj(sel);
2068 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2069 pnc |= ia32_pn_Cmp_Unsigned;
2072 if(mode_needs_gp_reg(cmp_mode)) {
2073 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2075 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2080 if (mode_is_float(cmp_mode)) {
2081 new_cmp_a = be_transform_node(cmp_a);
2082 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2083 if (USE_SSE2(env_cg)) {
2084 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
2086 set_ia32_commutative(res);
2087 set_ia32_ls_mode(res, cmp_mode);
2089 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2090 set_ia32_commutative(res);
2093 ia32_address_mode_t am;
2094 ia32_address_t *addr = &am.addr;
2095 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am);
2097 pnc = get_inversed_pnc(pnc);
2099 if(get_mode_size_bits(cmp_mode) == 8) {
2100 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
2101 addr->index, am.new_op1, am.new_op2,
2104 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2105 am.new_op1, am.new_op2, addr->mem, pnc);
2107 set_am_attributes(res, &am);
2108 assert(cmp_mode != NULL);
2109 set_ia32_ls_mode(res, cmp_mode);
2111 res = fix_mem_proj(res, &am);
2114 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2122 * Transforms a CopyB node.
2124 * @return The transformed node.
2126 static ir_node *gen_CopyB(ir_node *node) {
2127 ir_node *block = be_transform_node(get_nodes_block(node));
2128 ir_node *src = get_CopyB_src(node);
2129 ir_node *new_src = be_transform_node(src);
2130 ir_node *dst = get_CopyB_dst(node);
2131 ir_node *new_dst = be_transform_node(dst);
2132 ir_node *mem = get_CopyB_mem(node);
2133 ir_node *new_mem = be_transform_node(mem);
2134 ir_node *res = NULL;
2135 ir_graph *irg = current_ir_graph;
2136 dbg_info *dbgi = get_irn_dbg_info(node);
2137 int size = get_type_size_bytes(get_CopyB_type(node));
2140 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2141 /* then we need the size explicitly in ECX. */
2142 if (size >= 32 * 4) {
2143 rem = size & 0x3; /* size % 4 */
2146 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2147 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2149 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2150 /* we misuse the pncode field for the copyb size */
2151 set_ia32_pncode(res, rem);
2153 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2154 set_ia32_pncode(res, size);
2157 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2163 ir_node *gen_be_Copy(ir_node *node)
2165 ir_node *result = be_duplicate_node(node);
2166 ir_mode *mode = get_irn_mode(result);
2168 if (mode_needs_gp_reg(mode)) {
2169 set_irn_mode(result, mode_Iu);
2176 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2177 dbg_info *dbgi, ir_node *block, int use_am)
2179 ir_graph *irg = current_ir_graph;
2180 ir_node *new_block = be_transform_node(block);
2181 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2182 ir_node *nomem = new_rd_NoMem(irg);
2187 ia32_address_mode_t am;
2188 ia32_address_t *addr = &am.addr;
2190 /* can we use a test instruction? */
2191 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2192 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2193 if(is_And(cmp_left) &&
2194 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2195 ir_node *and_left = get_And_left(cmp_left);
2196 ir_node *and_right = get_And_right(cmp_left);
2198 mode = get_irn_mode(and_left);
2199 arg_left = and_left;
2200 arg_right = and_right;
2202 mode = get_irn_mode(cmp_left);
2203 arg_left = cmp_left;
2204 arg_right = cmp_left;
2207 assert(get_mode_size_bits(mode) <= 32);
2209 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
2211 pnc = get_inversed_pnc(pnc);
2213 if(get_mode_size_bits(mode) == 8) {
2214 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2215 addr->index, am.new_op1, am.new_op2,
2218 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
2219 addr->index, am.new_op1, am.new_op2,
2222 set_am_attributes(res, &am);
2223 set_ia32_ls_mode(res, mode);
2225 res = fix_mem_proj(res, &am);
2227 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2233 mode = get_irn_mode(cmp_left);
2234 assert(get_mode_size_bits(mode) <= 32);
2236 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am);
2238 pnc = get_inversed_pnc(pnc);
2240 if(get_mode_size_bits(mode) == 8) {
2241 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
2242 addr->index, am.new_op1, am.new_op2,
2245 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2246 am.new_op1, am.new_op2, addr->mem, pnc);
2248 set_am_attributes(res, &am);
2249 set_ia32_ls_mode(res, mode);
2251 res = fix_mem_proj(res, &am);
2253 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2259 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2260 ir_node *val_true, ir_node *val_false,
2261 dbg_info *dbgi, ir_node *block)
2263 ir_graph *irg = current_ir_graph;
2264 ir_node *new_block = be_transform_node(block);
2265 ir_node *new_val_true = be_transform_node(val_true);
2266 ir_node *new_val_false = be_transform_node(val_false);
2267 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2268 ir_node *nomem = new_NoMem();
2269 ir_node *new_cmp_left;
2270 ir_node *new_cmp_right;
2274 /* cmovs with unknowns are pointless... */
2275 if(is_Unknown(val_true)) {
2276 #ifdef DEBUG_libfirm
2277 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2279 return new_val_false;
2281 if(is_Unknown(val_false)) {
2282 #ifdef DEBUG_libfirm
2283 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2285 return new_val_true;
2288 /* can we use a test instruction? */
2289 if(is_Const_0(cmp_right)) {
2290 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2291 if(is_And(cmp_left) &&
2292 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2293 ir_node *and_left = get_And_left(cmp_left);
2294 ir_node *and_right = get_And_right(cmp_left);
2296 mode = get_irn_mode(and_left);
2297 new_cmp_left = be_transform_node(and_left);
2298 new_cmp_right = create_immediate_or_transform(and_right, 0);
2300 mode = get_irn_mode(cmp_left);
2301 new_cmp_left = be_transform_node(cmp_left);
2302 new_cmp_right = be_transform_node(cmp_left);
2305 assert(get_mode_size_bits(mode) <= 32);
2307 if(get_mode_size_bits(mode) == 8) {
2308 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
2309 noreg, noreg, new_cmp_left,
2310 new_cmp_right, nomem, new_val_true,
2311 new_val_false, pnc);
2313 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2314 noreg, new_cmp_left, new_cmp_right,
2315 nomem, new_val_true, new_val_false, pnc);
2317 set_ia32_ls_mode(res, mode);
2322 mode = get_irn_mode(cmp_left);
2323 new_cmp_left = be_transform_node(cmp_left);
2324 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2326 /* no support for 8,16 bit modes yet */
2327 assert(get_mode_size_bits(mode) <= 32);
2329 if(get_mode_size_bits(mode) == 8) {
2330 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
2331 new_cmp_left, new_cmp_right, nomem,
2332 new_val_true, new_val_false, pnc);
2334 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
2335 new_cmp_left, new_cmp_right, nomem,
2336 new_val_true, new_val_false, pnc);
2338 set_ia32_ls_mode(res, mode);
2345 * Transforms a Psi node into CMov.
2347 * @return The transformed node.
2349 static ir_node *gen_Psi(ir_node *node) {
2350 ir_node *psi_true = get_Psi_val(node, 0);
2351 ir_node *psi_default = get_Psi_default(node);
2352 ia32_code_gen_t *cg = env_cg;
2353 ir_node *cond = get_Psi_cond(node, 0);
2354 ir_node *block = get_nodes_block(node);
2355 dbg_info *dbgi = get_irn_dbg_info(node);
2362 assert(get_Psi_n_conds(node) == 1);
2363 assert(get_irn_mode(cond) == mode_b);
2364 assert(mode_needs_gp_reg(get_irn_mode(node)));
2366 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2367 /* a mode_b value, we have to compare it against 0 */
2369 cmp_right = new_Const_long(mode_Iu, 0);
2373 ir_node *cmp = get_Proj_pred(cond);
2375 cmp_left = get_Cmp_left(cmp);
2376 cmp_right = get_Cmp_right(cmp);
2377 cmp_mode = get_irn_mode(cmp_left);
2378 pnc = get_Proj_proj(cond);
2380 assert(!mode_is_float(cmp_mode));
2382 if (!mode_is_signed(cmp_mode)) {
2383 pnc |= ia32_pn_Cmp_Unsigned;
2387 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2388 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2389 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2390 pnc = get_negated_pnc(pnc, cmp_mode);
2391 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2393 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2396 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2402 * Create a conversion from x87 state register to general purpose.
2404 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2405 ir_node *block = be_transform_node(get_nodes_block(node));
2406 ir_node *op = get_Conv_op(node);
2407 ir_node *new_op = be_transform_node(op);
2408 ia32_code_gen_t *cg = env_cg;
2409 ir_graph *irg = current_ir_graph;
2410 dbg_info *dbgi = get_irn_dbg_info(node);
2411 ir_node *noreg = ia32_new_NoReg_gp(cg);
2412 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2413 ir_mode *mode = get_irn_mode(node);
2414 ir_node *fist, *load;
2417 fist = new_rd_ia32_vfist(dbgi, irg, block,
2418 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2420 set_irn_pinned(fist, op_pin_state_floats);
2421 set_ia32_use_frame(fist);
2422 set_ia32_op_type(fist, ia32_AddrModeD);
2424 assert(get_mode_size_bits(mode) <= 32);
2425 /* exception we can only store signed 32 bit integers, so for unsigned
2426 we store a 64bit (signed) integer and load the lower bits */
2427 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2428 set_ia32_ls_mode(fist, mode_Ls);
2430 set_ia32_ls_mode(fist, mode_Is);
2432 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2435 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2437 set_irn_pinned(load, op_pin_state_floats);
2438 set_ia32_use_frame(load);
2439 set_ia32_op_type(load, ia32_AddrModeS);
2440 set_ia32_ls_mode(load, mode_Is);
2441 if(get_ia32_ls_mode(fist) == mode_Ls) {
2442 ia32_attr_t *attr = get_ia32_attr(load);
2443 attr->data.need_64bit_stackent = 1;
2445 ia32_attr_t *attr = get_ia32_attr(load);
2446 attr->data.need_32bit_stackent = 1;
2448 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2450 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2454 * Creates a x87 strict Conv by placing a Sore and a Load
2456 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2458 ir_node *block = get_nodes_block(node);
2459 ir_graph *irg = current_ir_graph;
2460 dbg_info *dbgi = get_irn_dbg_info(node);
2461 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2462 ir_node *nomem = new_NoMem();
2463 ir_node *frame = get_irg_frame(irg);
2464 ir_node *store, *load;
2467 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2469 set_ia32_use_frame(store);
2470 set_ia32_op_type(store, ia32_AddrModeD);
2471 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2473 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2475 set_ia32_use_frame(load);
2476 set_ia32_op_type(load, ia32_AddrModeS);
2477 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2479 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2484 * Create a conversion from general purpose to x87 register
2486 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2487 ir_node *block = be_transform_node(get_nodes_block(node));
2488 ir_node *op = get_Conv_op(node);
2489 ir_node *new_op = be_transform_node(op);
2490 ir_graph *irg = current_ir_graph;
2491 dbg_info *dbgi = get_irn_dbg_info(node);
2492 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2493 ir_node *nomem = new_NoMem();
2494 ir_mode *mode = get_irn_mode(op);
2495 ir_mode *store_mode;
2496 ir_node *fild, *store;
2500 /* first convert to 32 bit signed if necessary */
2501 src_bits = get_mode_size_bits(src_mode);
2502 if (src_bits == 8) {
2503 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2505 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2507 } else if (src_bits < 32) {
2508 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2509 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2513 assert(get_mode_size_bits(mode) == 32);
2516 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2518 set_ia32_use_frame(store);
2519 set_ia32_op_type(store, ia32_AddrModeD);
2520 set_ia32_ls_mode(store, mode_Iu);
2522 /* exception for 32bit unsigned, do a 64bit spill+load */
2523 if(!mode_is_signed(mode)) {
2526 ir_node *zero_const = create_Immediate_from_int(0);
2528 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2531 set_ia32_use_frame(zero_store);
2532 set_ia32_op_type(zero_store, ia32_AddrModeD);
2533 add_ia32_am_offs_int(zero_store, 4);
2534 set_ia32_ls_mode(zero_store, mode_Iu);
2539 store = new_rd_Sync(dbgi, irg, block, 2, in);
2540 store_mode = mode_Ls;
2542 store_mode = mode_Is;
2546 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2548 set_ia32_use_frame(fild);
2549 set_ia32_op_type(fild, ia32_AddrModeS);
2550 set_ia32_ls_mode(fild, store_mode);
2552 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2558 * Crete a conversion from one integer mode into another one
2560 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2561 dbg_info *dbgi, ir_node *new_block,
2564 ir_graph *irg = current_ir_graph;
2565 int src_bits = get_mode_size_bits(src_mode);
2566 int tgt_bits = get_mode_size_bits(tgt_mode);
2567 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2568 ir_node *nomem = new_rd_NoMem(irg);
2570 ir_mode *smaller_mode;
2573 if (src_bits < tgt_bits) {
2574 smaller_mode = src_mode;
2575 smaller_bits = src_bits;
2577 smaller_mode = tgt_mode;
2578 smaller_bits = tgt_bits;
2581 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2582 if (smaller_bits == 8) {
2583 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2584 new_op, nomem, smaller_mode);
2586 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2587 nomem, smaller_mode);
2594 * Transforms a Conv node.
2596 * @return The created ia32 Conv node
2598 static ir_node *gen_Conv(ir_node *node) {
2599 ir_node *block = be_transform_node(get_nodes_block(node));
2600 ir_node *op = get_Conv_op(node);
2601 ir_node *new_op = be_transform_node(op);
2602 ir_graph *irg = current_ir_graph;
2603 dbg_info *dbgi = get_irn_dbg_info(node);
2604 ir_mode *src_mode = get_irn_mode(op);
2605 ir_mode *tgt_mode = get_irn_mode(node);
2606 int src_bits = get_mode_size_bits(src_mode);
2607 int tgt_bits = get_mode_size_bits(tgt_mode);
2608 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2609 ir_node *nomem = new_rd_NoMem(irg);
2612 if (src_mode == mode_b) {
2613 assert(mode_is_int(tgt_mode));
2614 /* nothing to do, we already model bools as 0/1 ints */
2618 if (src_mode == tgt_mode) {
2619 if (get_Conv_strict(node)) {
2620 if (USE_SSE2(env_cg)) {
2621 /* when we are in SSE mode, we can kill all strict no-op conversion */
2625 /* this should be optimized already, but who knows... */
2626 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2627 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2632 if (mode_is_float(src_mode)) {
2633 /* we convert from float ... */
2634 if (mode_is_float(tgt_mode)) {
2635 if(src_mode == mode_E && tgt_mode == mode_D
2636 && !get_Conv_strict(node)) {
2637 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2642 if (USE_SSE2(env_cg)) {
2643 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2644 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2645 set_ia32_ls_mode(res, tgt_mode);
2647 if(get_Conv_strict(node)) {
2648 res = gen_x87_strict_conv(tgt_mode, new_op);
2649 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2652 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2657 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2658 if (USE_SSE2(env_cg)) {
2659 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2660 set_ia32_ls_mode(res, src_mode);
2662 return gen_x87_fp_to_gp(node);
2666 /* we convert from int ... */
2667 if (mode_is_float(tgt_mode)) {
2669 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2670 if (USE_SSE2(env_cg)) {
2671 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2672 set_ia32_ls_mode(res, tgt_mode);
2674 res = gen_x87_gp_to_fp(node, src_mode);
2675 if(get_Conv_strict(node)) {
2676 res = gen_x87_strict_conv(tgt_mode, res);
2677 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2678 ia32_get_old_node_name(env_cg, node));
2682 } else if(tgt_mode == mode_b) {
2683 /* mode_b lowering already took care that we only have 0/1 values */
2684 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2685 src_mode, tgt_mode));
2689 if (src_bits == tgt_bits) {
2690 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2691 src_mode, tgt_mode));
2695 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2699 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2705 int check_immediate_constraint(long val, char immediate_constraint_type)
2707 switch (immediate_constraint_type) {
2711 return val >= 0 && val <= 32;
2713 return val >= 0 && val <= 63;
2715 return val >= -128 && val <= 127;
2717 return val == 0xff || val == 0xffff;
2719 return val >= 0 && val <= 3;
2721 return val >= 0 && val <= 255;
2723 return val >= 0 && val <= 127;
2727 panic("Invalid immediate constraint found");
2732 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2735 tarval *offset = NULL;
2736 int offset_sign = 0;
2738 ir_entity *symconst_ent = NULL;
2739 int symconst_sign = 0;
2741 ir_node *cnst = NULL;
2742 ir_node *symconst = NULL;
2748 mode = get_irn_mode(node);
2749 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2753 if(is_Minus(node)) {
2755 node = get_Minus_op(node);
2758 if(is_Const(node)) {
2761 offset_sign = minus;
2762 } else if(is_SymConst(node)) {
2765 symconst_sign = minus;
2766 } else if(is_Add(node)) {
2767 ir_node *left = get_Add_left(node);
2768 ir_node *right = get_Add_right(node);
2769 if(is_Const(left) && is_SymConst(right)) {
2772 symconst_sign = minus;
2773 offset_sign = minus;
2774 } else if(is_SymConst(left) && is_Const(right)) {
2777 symconst_sign = minus;
2778 offset_sign = minus;
2780 } else if(is_Sub(node)) {
2781 ir_node *left = get_Sub_left(node);
2782 ir_node *right = get_Sub_right(node);
2783 if(is_Const(left) && is_SymConst(right)) {
2786 symconst_sign = !minus;
2787 offset_sign = minus;
2788 } else if(is_SymConst(left) && is_Const(right)) {
2791 symconst_sign = minus;
2792 offset_sign = !minus;
2799 offset = get_Const_tarval(cnst);
2800 if(tarval_is_long(offset)) {
2801 val = get_tarval_long(offset);
2802 } else if(tarval_is_null(offset)) {
2805 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2810 if(!check_immediate_constraint(val, immediate_constraint_type))
2813 if(symconst != NULL) {
2814 if(immediate_constraint_type != 0) {
2815 /* we need full 32bits for symconsts */
2819 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2821 symconst_ent = get_SymConst_entity(symconst);
2823 if(cnst == NULL && symconst == NULL)
2826 if(offset_sign && offset != NULL) {
2827 offset = tarval_neg(offset);
2830 irg = current_ir_graph;
2831 dbgi = get_irn_dbg_info(node);
2832 block = get_irg_start_block(irg);
2833 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2834 symconst_sign, val);
2835 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2841 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2843 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2844 if (new_node == NULL) {
2845 new_node = be_transform_node(node);
2850 typedef struct constraint_t constraint_t;
2851 struct constraint_t {
2854 const arch_register_req_t **out_reqs;
2856 const arch_register_req_t *req;
2857 unsigned immediate_possible;
2858 char immediate_type;
2861 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2863 int immediate_possible = 0;
2864 char immediate_type = 0;
2865 unsigned limited = 0;
2866 const arch_register_class_t *cls = NULL;
2867 ir_graph *irg = current_ir_graph;
2868 struct obstack *obst = get_irg_obstack(irg);
2869 arch_register_req_t *req;
2870 unsigned *limited_ptr;
2874 /* TODO: replace all the asserts with nice error messages */
2876 printf("Constraint: %s\n", c);
2886 assert(cls == NULL ||
2887 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2888 cls = &ia32_reg_classes[CLASS_ia32_gp];
2889 limited |= 1 << REG_EAX;
2892 assert(cls == NULL ||
2893 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2894 cls = &ia32_reg_classes[CLASS_ia32_gp];
2895 limited |= 1 << REG_EBX;
2898 assert(cls == NULL ||
2899 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2900 cls = &ia32_reg_classes[CLASS_ia32_gp];
2901 limited |= 1 << REG_ECX;
2904 assert(cls == NULL ||
2905 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2906 cls = &ia32_reg_classes[CLASS_ia32_gp];
2907 limited |= 1 << REG_EDX;
2910 assert(cls == NULL ||
2911 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2912 cls = &ia32_reg_classes[CLASS_ia32_gp];
2913 limited |= 1 << REG_EDI;
2916 assert(cls == NULL ||
2917 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2918 cls = &ia32_reg_classes[CLASS_ia32_gp];
2919 limited |= 1 << REG_ESI;
2922 case 'q': /* q means lower part of the regs only, this makes no
2923 * difference to Q for us (we only assigne whole registers) */
2924 assert(cls == NULL ||
2925 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2926 cls = &ia32_reg_classes[CLASS_ia32_gp];
2927 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2931 assert(cls == NULL ||
2932 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2933 cls = &ia32_reg_classes[CLASS_ia32_gp];
2934 limited |= 1 << REG_EAX | 1 << REG_EDX;
2937 assert(cls == NULL ||
2938 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2939 cls = &ia32_reg_classes[CLASS_ia32_gp];
2940 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2941 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2948 assert(cls == NULL);
2949 cls = &ia32_reg_classes[CLASS_ia32_gp];
2955 /* TODO: mark values so the x87 simulator knows about t and u */
2956 assert(cls == NULL);
2957 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2962 assert(cls == NULL);
2963 /* TODO: check that sse2 is supported */
2964 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2974 assert(!immediate_possible);
2975 immediate_possible = 1;
2976 immediate_type = *c;
2980 assert(!immediate_possible);
2981 immediate_possible = 1;
2985 assert(!immediate_possible && cls == NULL);
2986 immediate_possible = 1;
2987 cls = &ia32_reg_classes[CLASS_ia32_gp];
3000 assert(constraint->is_in && "can only specify same constraint "
3003 sscanf(c, "%d%n", &same_as, &p);
3010 case 'E': /* no float consts yet */
3011 case 'F': /* no float consts yet */
3012 case 's': /* makes no sense on x86 */
3013 case 'X': /* we can't support that in firm */
3017 case '<': /* no autodecrement on x86 */
3018 case '>': /* no autoincrement on x86 */
3019 case 'C': /* sse constant not supported yet */
3020 case 'G': /* 80387 constant not supported yet */
3021 case 'y': /* we don't support mmx registers yet */
3022 case 'Z': /* not available in 32 bit mode */
3023 case 'e': /* not available in 32 bit mode */
3024 assert(0 && "asm constraint not supported");
3027 assert(0 && "unknown asm constraint found");
3034 const arch_register_req_t *other_constr;
3036 assert(cls == NULL && "same as and register constraint not supported");
3037 assert(!immediate_possible && "same as and immediate constraint not "
3039 assert(same_as < constraint->n_outs && "wrong constraint number in "
3040 "same_as constraint");
3042 other_constr = constraint->out_reqs[same_as];
3044 req = obstack_alloc(obst, sizeof(req[0]));
3045 req->cls = other_constr->cls;
3046 req->type = arch_register_req_type_should_be_same;
3047 req->limited = NULL;
3048 req->other_same = pos;
3049 req->other_different = -1;
3051 /* switch constraints. This is because in firm we have same_as
3052 * constraints on the output constraints while in the gcc asm syntax
3053 * they are specified on the input constraints */
3054 constraint->req = other_constr;
3055 constraint->out_reqs[same_as] = req;
3056 constraint->immediate_possible = 0;
3060 if(immediate_possible && cls == NULL) {
3061 cls = &ia32_reg_classes[CLASS_ia32_gp];
3063 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3064 assert(cls != NULL);
3066 if(immediate_possible) {
3067 assert(constraint->is_in
3068 && "imeediates make no sense for output constraints");
3070 /* todo: check types (no float input on 'r' constrained in and such... */
3073 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3074 limited_ptr = (unsigned*) (req+1);
3076 req = obstack_alloc(obst, sizeof(req[0]));
3078 memset(req, 0, sizeof(req[0]));
3081 req->type = arch_register_req_type_limited;
3082 *limited_ptr = limited;
3083 req->limited = limited_ptr;
3085 req->type = arch_register_req_type_normal;
3089 constraint->req = req;
3090 constraint->immediate_possible = immediate_possible;
3091 constraint->immediate_type = immediate_type;
3095 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3102 panic("Clobbers not supported yet");
3106 * generates code for a ASM node
3108 static ir_node *gen_ASM(ir_node *node)
3111 ir_graph *irg = current_ir_graph;
3112 ir_node *block = be_transform_node(get_nodes_block(node));
3113 dbg_info *dbgi = get_irn_dbg_info(node);
3120 ia32_asm_attr_t *attr;
3121 const arch_register_req_t **out_reqs;
3122 const arch_register_req_t **in_reqs;
3123 struct obstack *obst;
3124 constraint_t parsed_constraint;
3126 /* transform inputs */
3127 arity = get_irn_arity(node);
3128 in = alloca(arity * sizeof(in[0]));
3129 memset(in, 0, arity * sizeof(in[0]));
3131 n_outs = get_ASM_n_output_constraints(node);
3132 n_clobbers = get_ASM_n_clobbers(node);
3133 out_arity = n_outs + n_clobbers;
3135 /* construct register constraints */
3136 obst = get_irg_obstack(irg);
3137 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3138 parsed_constraint.out_reqs = out_reqs;
3139 parsed_constraint.n_outs = n_outs;
3140 parsed_constraint.is_in = 0;
3141 for(i = 0; i < out_arity; ++i) {
3145 const ir_asm_constraint *constraint;
3146 constraint = & get_ASM_output_constraints(node) [i];
3147 c = get_id_str(constraint->constraint);
3148 parse_asm_constraint(i, &parsed_constraint, c);
3150 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3151 c = get_id_str(glob_id);
3152 parse_clobber(node, i, &parsed_constraint, c);
3154 out_reqs[i] = parsed_constraint.req;
3157 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3158 parsed_constraint.is_in = 1;
3159 for(i = 0; i < arity; ++i) {
3160 const ir_asm_constraint *constraint;
3164 constraint = & get_ASM_input_constraints(node) [i];
3165 constr_id = constraint->constraint;
3166 c = get_id_str(constr_id);
3167 parse_asm_constraint(i, &parsed_constraint, c);
3168 in_reqs[i] = parsed_constraint.req;
3170 if(parsed_constraint.immediate_possible) {
3171 ir_node *pred = get_irn_n(node, i);
3172 char imm_type = parsed_constraint.immediate_type;
3173 ir_node *immediate = try_create_Immediate(pred, imm_type);
3175 if(immediate != NULL) {
3181 /* transform inputs */
3182 for(i = 0; i < arity; ++i) {
3184 ir_node *transformed;
3189 pred = get_irn_n(node, i);
3190 transformed = be_transform_node(pred);
3191 in[i] = transformed;
3194 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3196 generic_attr = get_irn_generic_attr(res);
3197 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3198 attr->asm_text = get_ASM_text(node);
3199 set_ia32_out_req_all(res, out_reqs);
3200 set_ia32_in_req_all(res, in_reqs);
3202 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3207 /********************************************
3210 * | |__ ___ _ __ ___ __| | ___ ___
3211 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3212 * | |_) | __/ | | | (_) | (_| | __/\__ \
3213 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3215 ********************************************/
3218 * Transforms a FrameAddr into an ia32 Add.
3220 static ir_node *gen_be_FrameAddr(ir_node *node) {
3221 ir_node *block = be_transform_node(get_nodes_block(node));
3222 ir_node *op = be_get_FrameAddr_frame(node);
3223 ir_node *new_op = be_transform_node(op);
3224 ir_graph *irg = current_ir_graph;
3225 dbg_info *dbgi = get_irn_dbg_info(node);
3226 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3229 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3230 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3231 set_ia32_use_frame(res);
3233 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3239 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3241 static ir_node *gen_be_Return(ir_node *node) {
3242 ir_graph *irg = current_ir_graph;
3243 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3244 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3245 ir_entity *ent = get_irg_entity(irg);
3246 ir_type *tp = get_entity_type(ent);
3251 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3252 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3255 int pn_ret_val, pn_ret_mem, arity, i;
3257 assert(ret_val != NULL);
3258 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3259 return be_duplicate_node(node);
3262 res_type = get_method_res_type(tp, 0);
3264 if (! is_Primitive_type(res_type)) {
3265 return be_duplicate_node(node);
3268 mode = get_type_mode(res_type);
3269 if (! mode_is_float(mode)) {
3270 return be_duplicate_node(node);
3273 assert(get_method_n_ress(tp) == 1);
3275 pn_ret_val = get_Proj_proj(ret_val);
3276 pn_ret_mem = get_Proj_proj(ret_mem);
3278 /* get the Barrier */
3279 barrier = get_Proj_pred(ret_val);
3281 /* get result input of the Barrier */
3282 ret_val = get_irn_n(barrier, pn_ret_val);
3283 new_ret_val = be_transform_node(ret_val);
3285 /* get memory input of the Barrier */
3286 ret_mem = get_irn_n(barrier, pn_ret_mem);
3287 new_ret_mem = be_transform_node(ret_mem);
3289 frame = get_irg_frame(irg);
3291 dbgi = get_irn_dbg_info(barrier);
3292 block = be_transform_node(get_nodes_block(barrier));
3294 noreg = ia32_new_NoReg_gp(env_cg);
3296 /* store xmm0 onto stack */
3297 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3298 new_ret_val, new_ret_mem);
3299 set_ia32_ls_mode(sse_store, mode);
3300 set_ia32_op_type(sse_store, ia32_AddrModeD);
3301 set_ia32_use_frame(sse_store);
3303 /* load into x87 register */
3304 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3305 set_ia32_op_type(fld, ia32_AddrModeS);
3306 set_ia32_use_frame(fld);
3308 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3309 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3311 /* create a new barrier */
3312 arity = get_irn_arity(barrier);
3313 in = alloca(arity * sizeof(in[0]));
3314 for (i = 0; i < arity; ++i) {
3317 if (i == pn_ret_val) {
3319 } else if (i == pn_ret_mem) {
3322 ir_node *in = get_irn_n(barrier, i);
3323 new_in = be_transform_node(in);
3328 new_barrier = new_ir_node(dbgi, irg, block,
3329 get_irn_op(barrier), get_irn_mode(barrier),
3331 copy_node_attr(barrier, new_barrier);
3332 be_duplicate_deps(barrier, new_barrier);
3333 be_set_transformed_node(barrier, new_barrier);
3334 mark_irn_visited(barrier);
3336 /* transform normally */
3337 return be_duplicate_node(node);
3341 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3343 static ir_node *gen_be_AddSP(ir_node *node) {
3344 ir_node *block = be_transform_node(get_nodes_block(node));
3345 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3347 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3348 ir_node *new_sp = be_transform_node(sp);
3349 ir_graph *irg = current_ir_graph;
3350 dbg_info *dbgi = get_irn_dbg_info(node);
3351 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3352 ir_node *nomem = new_NoMem();
3355 new_sz = create_immediate_or_transform(sz, 0);
3357 /* ia32 stack grows in reverse direction, make a SubSP */
3358 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3360 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3366 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3368 static ir_node *gen_be_SubSP(ir_node *node) {
3369 ir_node *block = be_transform_node(get_nodes_block(node));
3370 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3372 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3373 ir_node *new_sp = be_transform_node(sp);
3374 ir_graph *irg = current_ir_graph;
3375 dbg_info *dbgi = get_irn_dbg_info(node);
3376 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3377 ir_node *nomem = new_NoMem();
3380 new_sz = create_immediate_or_transform(sz, 0);
3382 /* ia32 stack grows in reverse direction, make an AddSP */
3383 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3384 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3390 * This function just sets the register for the Unknown node
3391 * as this is not done during register allocation because Unknown
3392 * is an "ignore" node.
3394 static ir_node *gen_Unknown(ir_node *node) {
3395 ir_mode *mode = get_irn_mode(node);
3397 if (mode_is_float(mode)) {
3398 if (USE_SSE2(env_cg)) {
3399 return ia32_new_Unknown_xmm(env_cg);
3401 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3402 ir_graph *irg = current_ir_graph;
3403 dbg_info *dbgi = get_irn_dbg_info(node);
3404 ir_node *block = get_irg_start_block(irg);
3405 return new_rd_ia32_vfldz(dbgi, irg, block);
3407 } else if (mode_needs_gp_reg(mode)) {
3408 return ia32_new_Unknown_gp(env_cg);
3410 assert(0 && "unsupported Unknown-Mode");
3417 * Change some phi modes
3419 static ir_node *gen_Phi(ir_node *node) {
3420 ir_node *block = be_transform_node(get_nodes_block(node));
3421 ir_graph *irg = current_ir_graph;
3422 dbg_info *dbgi = get_irn_dbg_info(node);
3423 ir_mode *mode = get_irn_mode(node);
3426 if(mode_needs_gp_reg(mode)) {
3427 /* we shouldn't have any 64bit stuff around anymore */
3428 assert(get_mode_size_bits(mode) <= 32);
3429 /* all integer operations are on 32bit registers now */
3431 } else if(mode_is_float(mode)) {
3432 if (USE_SSE2(env_cg)) {
3439 /* phi nodes allow loops, so we use the old arguments for now
3440 * and fix this later */
3441 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3442 get_irn_in(node) + 1);
3443 copy_node_attr(node, phi);
3444 be_duplicate_deps(node, phi);
3446 be_set_transformed_node(node, phi);
3447 be_enqueue_preds(node);
3455 static ir_node *gen_IJmp(ir_node *node) {
3456 /* TODO: support AM */
3457 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3461 /**********************************************************************
3464 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3465 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3466 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3467 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3469 **********************************************************************/
3471 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3473 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3476 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3477 ir_node *val, ir_node *mem);
3480 * Transforms a lowered Load into a "real" one.
3482 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3484 ir_node *block = be_transform_node(get_nodes_block(node));
3485 ir_node *ptr = get_irn_n(node, 0);
3486 ir_node *new_ptr = be_transform_node(ptr);
3487 ir_node *mem = get_irn_n(node, 1);
3488 ir_node *new_mem = be_transform_node(mem);
3489 ir_graph *irg = current_ir_graph;
3490 dbg_info *dbgi = get_irn_dbg_info(node);
3491 ir_mode *mode = get_ia32_ls_mode(node);
3492 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3495 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3497 set_ia32_op_type(new_op, ia32_AddrModeS);
3498 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3499 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3500 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3501 if (is_ia32_am_sc_sign(node))
3502 set_ia32_am_sc_sign(new_op);
3503 set_ia32_ls_mode(new_op, mode);
3504 if (is_ia32_use_frame(node)) {
3505 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3506 set_ia32_use_frame(new_op);
3509 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3515 * Transforms a lowered Store into a "real" one.
3517 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3519 ir_node *block = be_transform_node(get_nodes_block(node));
3520 ir_node *ptr = get_irn_n(node, 0);
3521 ir_node *new_ptr = be_transform_node(ptr);
3522 ir_node *val = get_irn_n(node, 1);
3523 ir_node *new_val = be_transform_node(val);
3524 ir_node *mem = get_irn_n(node, 2);
3525 ir_node *new_mem = be_transform_node(mem);
3526 ir_graph *irg = current_ir_graph;
3527 dbg_info *dbgi = get_irn_dbg_info(node);
3528 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3529 ir_mode *mode = get_ia32_ls_mode(node);
3533 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3535 am_offs = get_ia32_am_offs_int(node);
3536 add_ia32_am_offs_int(new_op, am_offs);
3538 set_ia32_op_type(new_op, ia32_AddrModeD);
3539 set_ia32_ls_mode(new_op, mode);
3540 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3541 set_ia32_use_frame(new_op);
3543 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3550 * Transforms an ia32_l_XXX into a "real" XXX node
3552 * @param node The node to transform
3553 * @return the created ia32 XXX node
3555 #define GEN_LOWERED_OP(op) \
3556 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3557 return gen_binop(node, get_binop_left(node), \
3558 get_binop_right(node), new_rd_ia32_##op,0); \
3561 #define GEN_LOWERED_x87_OP(op) \
3562 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3564 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3565 get_binop_right(node), new_rd_ia32_##op); \
3569 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3570 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3571 return gen_shift_binop(node, get_irn_n(node, 0), \
3572 get_irn_n(node, 1), new_rd_ia32_##op); \
3580 GEN_LOWERED_x87_OP(vfprem)
3581 GEN_LOWERED_x87_OP(vfmul)
3582 GEN_LOWERED_x87_OP(vfsub)
3583 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3584 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3585 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3586 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3590 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3592 * @param node The node to transform
3593 * @return the created ia32 Neg node
3595 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3596 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3600 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3602 * @param node The node to transform
3603 * @return the created ia32 vfild node
3605 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3606 return gen_lowered_Load(node, new_rd_ia32_vfild);
3610 * Transforms an ia32_l_Load into a "real" ia32_Load node
3612 * @param node The node to transform
3613 * @return the created ia32 Load node
3615 static ir_node *gen_ia32_l_Load(ir_node *node) {
3616 return gen_lowered_Load(node, new_rd_ia32_Load);
3620 * Transforms an ia32_l_Store into a "real" ia32_Store node
3622 * @param node The node to transform
3623 * @return the created ia32 Store node
3625 static ir_node *gen_ia32_l_Store(ir_node *node) {
3626 return gen_lowered_Store(node, new_rd_ia32_Store);
3630 * Transforms a l_vfist into a "real" vfist node.
3632 * @param node The node to transform
3633 * @return the created ia32 vfist node
3635 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3636 ir_node *block = be_transform_node(get_nodes_block(node));
3637 ir_node *ptr = get_irn_n(node, 0);
3638 ir_node *new_ptr = be_transform_node(ptr);
3639 ir_node *val = get_irn_n(node, 1);
3640 ir_node *new_val = be_transform_node(val);
3641 ir_node *mem = get_irn_n(node, 2);
3642 ir_node *new_mem = be_transform_node(mem);
3643 ir_graph *irg = current_ir_graph;
3644 dbg_info *dbgi = get_irn_dbg_info(node);
3645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3646 ir_mode *mode = get_ia32_ls_mode(node);
3647 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3651 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
3652 trunc_mode, new_mem);
3654 am_offs = get_ia32_am_offs_int(node);
3655 add_ia32_am_offs_int(new_op, am_offs);
3657 set_ia32_op_type(new_op, ia32_AddrModeD);
3658 set_ia32_ls_mode(new_op, mode);
3659 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3660 set_ia32_use_frame(new_op);
3662 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3668 * Transforms a l_vfdiv into a "real" vfdiv node.
3670 * @param env The transformation environment
3671 * @return the created ia32 vfdiv node
3673 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3674 ir_node *block = be_transform_node(get_nodes_block(node));
3675 ir_node *left = get_binop_left(node);
3676 ir_node *new_left = be_transform_node(left);
3677 ir_node *right = get_binop_right(node);
3678 ir_node *new_right = be_transform_node(right);
3679 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3680 ir_graph *irg = current_ir_graph;
3681 dbg_info *dbgi = get_irn_dbg_info(node);
3682 ir_node *fpcw = get_fpcw();
3685 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3686 new_right, new_NoMem(), fpcw);
3687 clear_ia32_commutative(vfdiv);
3689 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3695 * Transforms a l_MulS into a "real" MulS node.
3697 * @param env The transformation environment
3698 * @return the created ia32 Mul node
3700 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3701 ir_node *block = be_transform_node(get_nodes_block(node));
3702 ir_node *left = get_binop_left(node);
3703 ir_node *new_left = be_transform_node(left);
3704 ir_node *right = get_binop_right(node);
3705 ir_node *new_right = be_transform_node(right);
3706 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3707 ir_graph *irg = current_ir_graph;
3708 dbg_info *dbgi = get_irn_dbg_info(node);
3710 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3711 /* and then skip the result Proj, because all needed Projs are already there. */
3712 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3713 new_right, new_NoMem());
3714 clear_ia32_commutative(muls);
3716 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3722 * Transforms a l_IMulS into a "real" IMul1OPS node.
3724 * @param env The transformation environment
3725 * @return the created ia32 IMul1OP node
3727 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3728 ir_node *block = be_transform_node(get_nodes_block(node));
3729 ir_node *left = get_binop_left(node);
3730 ir_node *new_left = be_transform_node(left);
3731 ir_node *right = get_binop_right(node);
3732 ir_node *new_right = be_transform_node(right);
3733 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3734 ir_graph *irg = current_ir_graph;
3735 dbg_info *dbgi = get_irn_dbg_info(node);
3737 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3738 /* and then skip the result Proj, because all needed Projs are already there. */
3739 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
3740 new_right, new_NoMem());
3741 clear_ia32_commutative(muls);
3743 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3748 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3750 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3751 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3752 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3753 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3754 ir_node *block = be_transform_node(get_nodes_block(node));
3755 dbg_info *dbgi = get_irn_dbg_info(node);
3756 ir_graph *irg = current_ir_graph;
3757 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3758 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3763 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3764 * op1 - target to be shifted
3765 * op2 - contains bits to be shifted into target
3767 * Only op3 can be an immediate.
3769 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3770 ir_node *op2, ir_node *count)
3772 ir_node *block = be_transform_node(get_nodes_block(node));
3773 ir_node *new_op = NULL;
3774 ir_graph *irg = current_ir_graph;
3775 dbg_info *dbgi = get_irn_dbg_info(node);
3776 ir_node *new_op1 = be_transform_node(op1);
3777 ir_node *new_op2 = be_transform_node(op2);
3778 ir_node *new_count = create_immediate_or_transform(count, 'I');
3780 /* TODO proper AM support */
3782 if (is_ia32_l_ShlD(node))
3783 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3785 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3787 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3792 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3793 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3794 get_irn_n(node, 1), get_irn_n(node, 2));
3797 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3798 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3799 get_irn_n(node, 1), get_irn_n(node, 2));
3803 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3805 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3806 ir_node *block = be_transform_node(get_nodes_block(node));
3807 ir_node *val = get_irn_n(node, 1);
3808 ir_node *new_val = be_transform_node(val);
3809 ia32_code_gen_t *cg = env_cg;
3810 ir_node *res = NULL;
3811 ir_graph *irg = current_ir_graph;
3813 ir_node *noreg, *new_ptr, *new_mem;
3820 mem = get_irn_n(node, 2);
3821 new_mem = be_transform_node(mem);
3822 ptr = get_irn_n(node, 0);
3823 new_ptr = be_transform_node(ptr);
3824 noreg = ia32_new_NoReg_gp(cg);
3825 dbgi = get_irn_dbg_info(node);
3827 /* Store x87 -> MEM */
3828 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3829 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3830 set_ia32_use_frame(res);
3831 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3832 set_ia32_op_type(res, ia32_AddrModeD);
3834 /* Load MEM -> SSE */
3835 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3836 get_ia32_ls_mode(node));
3837 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3838 set_ia32_use_frame(res);
3839 set_ia32_op_type(res, ia32_AddrModeS);
3840 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3846 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3848 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3849 ir_node *block = be_transform_node(get_nodes_block(node));
3850 ir_node *val = get_irn_n(node, 1);
3851 ir_node *new_val = be_transform_node(val);
3852 ia32_code_gen_t *cg = env_cg;
3853 ir_graph *irg = current_ir_graph;
3854 ir_node *res = NULL;
3855 ir_entity *fent = get_ia32_frame_ent(node);
3856 ir_mode *lsmode = get_ia32_ls_mode(node);
3858 ir_node *noreg, *new_ptr, *new_mem;
3862 if (! USE_SSE2(cg)) {
3863 /* SSE unit is not used -> skip this node. */
3867 ptr = get_irn_n(node, 0);
3868 new_ptr = be_transform_node(ptr);
3869 mem = get_irn_n(node, 2);
3870 new_mem = be_transform_node(mem);
3871 noreg = ia32_new_NoReg_gp(cg);
3872 dbgi = get_irn_dbg_info(node);
3874 /* Store SSE -> MEM */
3875 if (is_ia32_xLoad(skip_Proj(new_val))) {
3876 ir_node *ld = skip_Proj(new_val);
3878 /* we can vfld the value directly into the fpu */
3879 fent = get_ia32_frame_ent(ld);
3880 ptr = get_irn_n(ld, 0);
3881 offs = get_ia32_am_offs_int(ld);
3883 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3884 set_ia32_frame_ent(res, fent);
3885 set_ia32_use_frame(res);
3886 set_ia32_ls_mode(res, lsmode);
3887 set_ia32_op_type(res, ia32_AddrModeD);
3891 /* Load MEM -> x87 */
3892 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3893 set_ia32_frame_ent(res, fent);
3894 set_ia32_use_frame(res);
3895 add_ia32_am_offs_int(res, offs);
3896 set_ia32_op_type(res, ia32_AddrModeS);
3897 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3902 /*********************************************************
3905 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3906 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3907 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3908 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3910 *********************************************************/
3913 * the BAD transformer.
3915 static ir_node *bad_transform(ir_node *node) {
3916 panic("No transform function for %+F available.\n", node);
3921 * Transform the Projs of an AddSP.
3923 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3924 ir_node *block = be_transform_node(get_nodes_block(node));
3925 ir_node *pred = get_Proj_pred(node);
3926 ir_node *new_pred = be_transform_node(pred);
3927 ir_graph *irg = current_ir_graph;
3928 dbg_info *dbgi = get_irn_dbg_info(node);
3929 long proj = get_Proj_proj(node);
3931 if (proj == pn_be_AddSP_sp) {
3932 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3933 pn_ia32_SubSP_stack);
3934 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3936 } else if(proj == pn_be_AddSP_res) {
3937 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3938 pn_ia32_SubSP_addr);
3939 } else if (proj == pn_be_AddSP_M) {
3940 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3944 return new_rd_Unknown(irg, get_irn_mode(node));
3948 * Transform the Projs of a SubSP.
3950 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3951 ir_node *block = be_transform_node(get_nodes_block(node));
3952 ir_node *pred = get_Proj_pred(node);
3953 ir_node *new_pred = be_transform_node(pred);
3954 ir_graph *irg = current_ir_graph;
3955 dbg_info *dbgi = get_irn_dbg_info(node);
3956 long proj = get_Proj_proj(node);
3958 if (proj == pn_be_SubSP_sp) {
3959 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3960 pn_ia32_AddSP_stack);
3961 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3963 } else if (proj == pn_be_SubSP_M) {
3964 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3968 return new_rd_Unknown(irg, get_irn_mode(node));
3972 * Transform and renumber the Projs from a Load.
3974 static ir_node *gen_Proj_Load(ir_node *node) {
3976 ir_node *block = be_transform_node(get_nodes_block(node));
3977 ir_node *pred = get_Proj_pred(node);
3978 ir_graph *irg = current_ir_graph;
3979 dbg_info *dbgi = get_irn_dbg_info(node);
3980 long proj = get_Proj_proj(node);
3983 /* loads might be part of source address mode matches, so we don't
3984 transform the ProjMs yet (with the exception of loads whose result is
3987 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
3990 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
3992 /* this is needed, because sometimes we have loops that are only
3993 reachable through the ProjM */
3994 be_enqueue_preds(node);
3995 /* do it in 2 steps, to silence firm verifier */
3996 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
3997 set_Proj_proj(res, pn_ia32_Load_M);
4001 /* renumber the proj */
4002 new_pred = be_transform_node(pred);
4003 if (is_ia32_Load(new_pred)) {
4004 if (proj == pn_Load_res) {
4005 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4007 } else if (proj == pn_Load_M) {
4008 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4011 } else if(is_ia32_Conv_I2I(new_pred)) {
4012 set_irn_mode(new_pred, mode_T);
4013 if (proj == pn_Load_res) {
4014 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
4015 } else if (proj == pn_Load_M) {
4016 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4018 } else if (is_ia32_xLoad(new_pred)) {
4019 if (proj == pn_Load_res) {
4020 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4022 } else if (proj == pn_Load_M) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4026 } else if (is_ia32_vfld(new_pred)) {
4027 if (proj == pn_Load_res) {
4028 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4030 } else if (proj == pn_Load_M) {
4031 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4035 /* can happen for ProJMs when source address mode happened for the
4038 /* however it should not be the result proj, as that would mean the
4039 load had multiple users and should not have been used for
4041 if(proj != pn_Load_M) {
4042 panic("internal error: transformed node not a Load");
4044 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4048 return new_rd_Unknown(irg, get_irn_mode(node));
4052 * Transform and renumber the Projs from a DivMod like instruction.
4054 static ir_node *gen_Proj_DivMod(ir_node *node) {
4055 ir_node *block = be_transform_node(get_nodes_block(node));
4056 ir_node *pred = get_Proj_pred(node);
4057 ir_node *new_pred = be_transform_node(pred);
4058 ir_graph *irg = current_ir_graph;
4059 dbg_info *dbgi = get_irn_dbg_info(node);
4060 ir_mode *mode = get_irn_mode(node);
4061 long proj = get_Proj_proj(node);
4063 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4065 switch (get_irn_opcode(pred)) {
4069 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4071 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4079 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4081 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4089 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4090 case pn_DivMod_res_div:
4091 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4092 case pn_DivMod_res_mod:
4093 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4103 return new_rd_Unknown(irg, mode);
4107 * Transform and renumber the Projs from a CopyB.
4109 static ir_node *gen_Proj_CopyB(ir_node *node) {
4110 ir_node *block = be_transform_node(get_nodes_block(node));
4111 ir_node *pred = get_Proj_pred(node);
4112 ir_node *new_pred = be_transform_node(pred);
4113 ir_graph *irg = current_ir_graph;
4114 dbg_info *dbgi = get_irn_dbg_info(node);
4115 ir_mode *mode = get_irn_mode(node);
4116 long proj = get_Proj_proj(node);
4119 case pn_CopyB_M_regular:
4120 if (is_ia32_CopyB_i(new_pred)) {
4121 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4122 } else if (is_ia32_CopyB(new_pred)) {
4123 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4131 return new_rd_Unknown(irg, mode);
4135 * Transform and renumber the Projs from a vfdiv.
4137 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4138 ir_node *block = be_transform_node(get_nodes_block(node));
4139 ir_node *pred = get_Proj_pred(node);
4140 ir_node *new_pred = be_transform_node(pred);
4141 ir_graph *irg = current_ir_graph;
4142 dbg_info *dbgi = get_irn_dbg_info(node);
4143 ir_mode *mode = get_irn_mode(node);
4144 long proj = get_Proj_proj(node);
4147 case pn_ia32_l_vfdiv_M:
4148 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4149 case pn_ia32_l_vfdiv_res:
4150 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4155 return new_rd_Unknown(irg, mode);
4159 * Transform and renumber the Projs from a Quot.
4161 static ir_node *gen_Proj_Quot(ir_node *node) {
4162 ir_node *block = be_transform_node(get_nodes_block(node));
4163 ir_node *pred = get_Proj_pred(node);
4164 ir_node *new_pred = be_transform_node(pred);
4165 ir_graph *irg = current_ir_graph;
4166 dbg_info *dbgi = get_irn_dbg_info(node);
4167 ir_mode *mode = get_irn_mode(node);
4168 long proj = get_Proj_proj(node);
4172 if (is_ia32_xDiv(new_pred)) {
4173 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4174 } else if (is_ia32_vfdiv(new_pred)) {
4175 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4179 if (is_ia32_xDiv(new_pred)) {
4180 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4181 } else if (is_ia32_vfdiv(new_pred)) {
4182 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4190 return new_rd_Unknown(irg, mode);
4194 * Transform the Thread Local Storage Proj.
4196 static ir_node *gen_Proj_tls(ir_node *node) {
4197 ir_node *block = be_transform_node(get_nodes_block(node));
4198 ir_graph *irg = current_ir_graph;
4199 dbg_info *dbgi = NULL;
4200 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4206 * Transform the Projs from a be_Call.
4208 static ir_node *gen_Proj_be_Call(ir_node *node) {
4209 ir_node *block = be_transform_node(get_nodes_block(node));
4210 ir_node *call = get_Proj_pred(node);
4211 ir_node *new_call = be_transform_node(call);
4212 ir_graph *irg = current_ir_graph;
4213 dbg_info *dbgi = get_irn_dbg_info(node);
4214 ir_type *method_type = be_Call_get_type(call);
4215 int n_res = get_method_n_ress(method_type);
4216 long proj = get_Proj_proj(node);
4217 ir_mode *mode = get_irn_mode(node);
4219 const arch_register_class_t *cls;
4221 /* The following is kinda tricky: If we're using SSE, then we have to
4222 * move the result value of the call in floating point registers to an
4223 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4224 * after the call, we have to make sure to correctly make the
4225 * MemProj and the result Proj use these 2 nodes
4227 if (proj == pn_be_Call_M_regular) {
4228 // get new node for result, are we doing the sse load/store hack?
4229 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4230 ir_node *call_res_new;
4231 ir_node *call_res_pred = NULL;
4233 if (call_res != NULL) {
4234 call_res_new = be_transform_node(call_res);
4235 call_res_pred = get_Proj_pred(call_res_new);
4238 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4239 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4240 pn_be_Call_M_regular);
4242 assert(is_ia32_xLoad(call_res_pred));
4243 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4247 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4248 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4249 && USE_SSE2(env_cg)) {
4251 ir_node *frame = get_irg_frame(irg);
4252 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4254 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4257 /* in case there is no memory output: create one to serialize the copy
4259 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4260 pn_be_Call_M_regular);
4261 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4262 pn_be_Call_first_res);
4264 /* store st(0) onto stack */
4265 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
4267 set_ia32_op_type(fstp, ia32_AddrModeD);
4268 set_ia32_use_frame(fstp);
4270 /* load into SSE register */
4271 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4273 set_ia32_op_type(sse_load, ia32_AddrModeS);
4274 set_ia32_use_frame(sse_load);
4276 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4282 /* transform call modes */
4283 if (mode_is_data(mode)) {
4284 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4288 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4292 * Transform the Projs from a Cmp.
4294 static ir_node *gen_Proj_Cmp(ir_node *node)
4296 /* normally Cmps are processed when looking at Cond nodes, but this case
4297 * can happen in complicated Psi conditions */
4299 ir_node *cmp = get_Proj_pred(node);
4300 long pnc = get_Proj_proj(node);
4301 ir_node *cmp_left = get_Cmp_left(cmp);
4302 ir_node *cmp_right = get_Cmp_right(cmp);
4303 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4304 dbg_info *dbgi = get_irn_dbg_info(cmp);
4305 ir_node *block = get_nodes_block(node);
4309 assert(!mode_is_float(cmp_mode));
4311 if(!mode_is_signed(cmp_mode)) {
4312 pnc |= ia32_pn_Cmp_Unsigned;
4316 * address mode makes only sense when we'll be the only node using the cmp
4318 use_am = get_irn_n_edges(cmp) <= 1;
4320 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4321 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4327 * Transform and potentially renumber Proj nodes.
4329 static ir_node *gen_Proj(ir_node *node) {
4330 ir_graph *irg = current_ir_graph;
4331 dbg_info *dbgi = get_irn_dbg_info(node);
4332 ir_node *pred = get_Proj_pred(node);
4333 long proj = get_Proj_proj(node);
4335 if (is_Store(pred)) {
4336 if (proj == pn_Store_M) {
4337 return be_transform_node(pred);
4340 return new_r_Bad(irg);
4342 } else if (is_Load(pred)) {
4343 return gen_Proj_Load(node);
4344 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4345 return gen_Proj_DivMod(node);
4346 } else if (is_CopyB(pred)) {
4347 return gen_Proj_CopyB(node);
4348 } else if (is_Quot(pred)) {
4349 return gen_Proj_Quot(node);
4350 } else if (is_ia32_l_vfdiv(pred)) {
4351 return gen_Proj_l_vfdiv(node);
4352 } else if (be_is_SubSP(pred)) {
4353 return gen_Proj_be_SubSP(node);
4354 } else if (be_is_AddSP(pred)) {
4355 return gen_Proj_be_AddSP(node);
4356 } else if (be_is_Call(pred)) {
4357 return gen_Proj_be_Call(node);
4358 } else if (is_Cmp(pred)) {
4359 return gen_Proj_Cmp(node);
4360 } else if (get_irn_op(pred) == op_Start) {
4361 if (proj == pn_Start_X_initial_exec) {
4362 ir_node *block = get_nodes_block(pred);
4365 /* we exchange the ProjX with a jump */
4366 block = be_transform_node(block);
4367 jump = new_rd_Jmp(dbgi, irg, block);
4370 if (node == be_get_old_anchor(anchor_tls)) {
4371 return gen_Proj_tls(node);
4374 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4378 ir_node *new_pred = be_transform_node(pred);
4379 ir_node *block = be_transform_node(get_nodes_block(node));
4380 ir_mode *mode = get_irn_mode(node);
4381 if (mode_needs_gp_reg(mode)) {
4382 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4383 get_Proj_proj(node));
4384 #ifdef DEBUG_libfirm
4385 new_proj->node_nr = node->node_nr;
4391 return be_duplicate_node(node);
4395 * Enters all transform functions into the generic pointer
4397 static void register_transformers(void)
4401 /* first clear the generic function pointer for all ops */
4402 clear_irp_opcodes_generic_func();
4404 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4405 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4442 /* transform ops from intrinsic lowering */
4466 GEN(ia32_l_X87toSSE);
4467 GEN(ia32_l_SSEtoX87);
4473 /* we should never see these nodes */
4488 /* handle generic backend nodes */
4496 op_Mulh = get_op_Mulh();
4505 * Pre-transform all unknown and noreg nodes.
4507 static void ia32_pretransform_node(void *arch_cg) {
4508 ia32_code_gen_t *cg = arch_cg;
4510 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4511 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4512 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4513 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4514 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4515 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4520 * Walker, checks if all ia32 nodes producing more than one result have
4521 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4524 void add_missing_keep_walker(ir_node *node, void *data)
4527 unsigned found_projs = 0;
4528 const ir_edge_t *edge;
4529 ir_mode *mode = get_irn_mode(node);
4534 if(!is_ia32_irn(node))
4537 n_outs = get_ia32_n_res(node);
4540 if(is_ia32_SwitchJmp(node))
4543 assert(n_outs < (int) sizeof(unsigned) * 8);
4544 foreach_out_edge(node, edge) {
4545 ir_node *proj = get_edge_src_irn(edge);
4546 int pn = get_Proj_proj(proj);
4548 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4549 found_projs |= 1 << pn;
4553 /* are keeps missing? */
4555 for(i = 0; i < n_outs; ++i) {
4558 const arch_register_req_t *req;
4559 const arch_register_class_t *class;
4561 if(found_projs & (1 << i)) {
4565 req = get_ia32_out_req(node, i);
4571 block = get_nodes_block(node);
4572 in[0] = new_r_Proj(current_ir_graph, block, node,
4573 arch_register_class_mode(class), i);
4574 if(last_keep != NULL) {
4575 be_Keep_add_node(last_keep, class, in[0]);
4577 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4583 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4587 void add_missing_keeps(ia32_code_gen_t *cg)
4589 ir_graph *irg = be_get_birg_irg(cg->birg);
4590 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4593 /* do the transformation */
4594 void ia32_transform_graph(ia32_code_gen_t *cg) {
4595 register_transformers();
4597 initial_fpcw = NULL;
4599 heights = heights_new(cg->irg);
4601 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4603 heights_free(heights);
4605 add_missing_keeps(cg);
4608 void ia32_init_transform(void)
4610 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");