2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
83 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
84 static const char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
89 } names [ia32_known_const_max] = {
90 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
91 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
92 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
93 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
95 static struct entity *ent_cache[ia32_known_const_max];
97 const char *tp_name, *ent_name, *cnst_str;
104 ent_name = names[kct].ent_name;
105 if (! ent_cache[kct]) {
106 tp_name = names[kct].tp_name;
107 cnst_str = names[kct].cnst_str;
109 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
110 tp = new_type_primitive(new_id_from_str(tp_name), mode);
111 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
113 set_entity_ld_ident(ent, get_entity_ident(ent));
114 set_entity_visibility(ent, visibility_local);
115 set_entity_variability(ent, variability_constant);
116 set_entity_allocation(ent, allocation_static);
118 /* we create a new entity here: It's initialization must resist on the
120 rem = current_ir_graph;
121 current_ir_graph = get_const_code_irg();
122 cnst = new_Const(mode, tv);
123 current_ir_graph = rem;
125 set_atomic_ent_value(ent, cnst);
127 /* cache the entry */
128 ent_cache[kct] = ent;
135 * Prints the old node name on cg obst and returns a pointer to it.
137 const char *get_old_node_name(ia32_transform_env_t *env) {
138 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
140 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
141 obstack_1grow(isa->name_obst, 0);
142 isa->name_obst_size += obstack_object_size(isa->name_obst);
143 return obstack_finish(isa->name_obst);
147 /* determine if one operator is an Imm */
148 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
150 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
151 else return is_ia32_Cnst(op2) ? op2 : NULL;
154 /* determine if one operator is not an Imm */
155 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
156 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
161 * Construct a standard binary operation, set AM and immediate if required.
163 * @param env The transformation environment
164 * @param op1 The first operand
165 * @param op2 The second operand
166 * @param func The node constructor function
167 * @return The constructed ia32 node.
169 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
170 ir_node *new_op = NULL;
171 ir_mode *mode = env->mode;
172 dbg_info *dbg = env->dbg;
173 ir_graph *irg = env->irg;
174 ir_node *block = env->block;
175 firm_dbg_module_t *mod = env->mod;
176 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
177 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
178 ir_node *nomem = new_NoMem();
179 ir_node *expr_op, *imm_op;
181 /* Check if immediate optimization is on and */
182 /* if it's an operation with immediate. */
183 if (! env->cg->opt.immops) {
187 else if (is_op_commutative(get_irn_op(env->irn))) {
188 imm_op = get_immediate_op(op1, op2);
189 expr_op = get_expr_op(op1, op2);
192 imm_op = get_immediate_op(NULL, op2);
193 expr_op = get_expr_op(op1, op2);
196 assert((expr_op || imm_op) && "invalid operands");
199 /* We have two consts here: not yet supported */
203 if (mode_is_float(mode)) {
204 /* floating point operations */
206 DB((mod, LEVEL_1, "FP with immediate ..."));
207 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
208 set_ia32_Immop_attr(new_op, imm_op);
209 set_ia32_am_support(new_op, ia32_am_None);
212 DB((mod, LEVEL_1, "FP binop ..."));
213 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
214 set_ia32_am_support(new_op, ia32_am_Source);
218 /* integer operations */
220 /* This is expr + const */
221 DB((mod, LEVEL_1, "INT with immediate ..."));
222 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
223 set_ia32_Immop_attr(new_op, imm_op);
226 set_ia32_am_support(new_op, ia32_am_Dest);
229 DB((mod, LEVEL_1, "INT binop ..."));
230 /* This is a normal operation */
231 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
234 set_ia32_am_support(new_op, ia32_am_Full);
238 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
240 set_ia32_res_mode(new_op, mode);
242 if (is_op_commutative(get_irn_op(env->irn))) {
243 set_ia32_commutative(new_op);
246 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
252 * Construct a shift/rotate binary operation, sets AM and immediate if required.
254 * @param env The transformation environment
255 * @param op1 The first operand
256 * @param op2 The second operand
257 * @param func The node constructor function
258 * @return The constructed ia32 node.
260 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
261 ir_node *new_op = NULL;
262 ir_mode *mode = env->mode;
263 dbg_info *dbg = env->dbg;
264 ir_graph *irg = env->irg;
265 ir_node *block = env->block;
266 firm_dbg_module_t *mod = env->mod;
267 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
268 ir_node *nomem = new_NoMem();
269 ir_node *expr_op, *imm_op;
272 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
274 /* Check if immediate optimization is on and */
275 /* if it's an operation with immediate. */
276 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
277 expr_op = get_expr_op(op1, op2);
279 assert((expr_op || imm_op) && "invalid operands");
282 /* We have two consts here: not yet supported */
286 /* Limit imm_op within range imm8 */
288 tv = get_ia32_Immop_tarval(imm_op);
291 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
298 /* integer operations */
300 /* This is shift/rot with const */
301 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
303 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
304 set_ia32_Immop_attr(new_op, imm_op);
307 /* This is a normal shift/rot */
308 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
309 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
313 set_ia32_am_support(new_op, ia32_am_Dest);
315 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
317 set_ia32_res_mode(new_op, mode);
319 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
324 * Construct a standard unary operation, set AM and immediate if required.
326 * @param env The transformation environment
327 * @param op The operand
328 * @param func The node constructor function
329 * @return The constructed ia32 node.
331 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
332 ir_node *new_op = NULL;
333 ir_mode *mode = env->mode;
334 dbg_info *dbg = env->dbg;
335 firm_dbg_module_t *mod = env->mod;
336 ir_graph *irg = env->irg;
337 ir_node *block = env->block;
338 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
339 ir_node *nomem = new_NoMem();
341 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
343 if (mode_is_float(mode)) {
344 DB((mod, LEVEL_1, "FP unop ..."));
345 /* floating point operations don't support implicit store */
346 set_ia32_am_support(new_op, ia32_am_None);
349 DB((mod, LEVEL_1, "INT unop ..."));
350 set_ia32_am_support(new_op, ia32_am_Dest);
353 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
355 set_ia32_res_mode(new_op, mode);
357 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
363 * Creates an ia32 Add with immediate.
365 * @param env The transformation environment
366 * @param expr_op The expression operator
367 * @param const_op The constant
368 * @return the created ia32 Add node
370 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
371 ir_node *new_op = NULL;
372 tarval *tv = get_ia32_Immop_tarval(const_op);
373 firm_dbg_module_t *mod = env->mod;
374 dbg_info *dbg = env->dbg;
375 ir_graph *irg = env->irg;
376 ir_node *block = env->block;
377 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
378 ir_node *nomem = new_NoMem();
380 tarval_classification_t class_tv, class_negtv;
382 /* try to optimize to inc/dec */
383 if (env->cg->opt.incdec && tv) {
384 /* optimize tarvals */
385 class_tv = classify_tarval(tv);
386 class_negtv = classify_tarval(tarval_neg(tv));
388 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
389 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
390 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
393 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
394 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
395 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
401 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
402 set_ia32_Immop_attr(new_op, const_op);
409 * Creates an ia32 Add.
411 * @param dbg firm node dbg
412 * @param block the block the new node should belong to
413 * @param op1 first operator
414 * @param op2 second operator
415 * @param mode node mode
416 * @return the created ia32 Add node
418 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
419 ir_node *new_op = NULL;
420 dbg_info *dbg = env->dbg;
421 ir_mode *mode = env->mode;
422 ir_graph *irg = env->irg;
423 ir_node *block = env->block;
424 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
425 ir_node *nomem = new_NoMem();
426 ir_node *expr_op, *imm_op;
428 /* Check if immediate optimization is on and */
429 /* if it's an operation with immediate. */
430 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
431 expr_op = get_expr_op(op1, op2);
433 assert((expr_op || imm_op) && "invalid operands");
435 if (mode_is_float(mode)) {
436 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
441 /* No expr_op means, that we have two const - one symconst and */
442 /* one tarval or another symconst - because this case is not */
443 /* covered by constant folding */
445 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
446 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
447 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
450 set_ia32_am_support(new_op, ia32_am_Source);
451 set_ia32_op_type(new_op, ia32_AddrModeS);
452 set_ia32_am_flavour(new_op, ia32_am_O);
454 /* Lea doesn't need a Proj */
458 /* This is expr + const */
459 new_op = gen_imm_Add(env, expr_op, imm_op);
462 set_ia32_am_support(new_op, ia32_am_Dest);
465 /* This is a normal add */
466 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
469 set_ia32_am_support(new_op, ia32_am_Full);
473 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
475 set_ia32_res_mode(new_op, mode);
477 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
483 * Creates an ia32 Mul.
485 * @param dbg firm node dbg
486 * @param block the block the new node should belong to
487 * @param op1 first operator
488 * @param op2 second operator
489 * @param mode node mode
490 * @return the created ia32 Mul node
492 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
495 if (mode_is_float(env->mode)) {
496 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
499 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
508 * Creates an ia32 Mulh.
509 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
510 * this result while Mul returns the lower 32 bit.
512 * @param env The transformation environment
513 * @param op1 The first operator
514 * @param op2 The second operator
515 * @return the created ia32 Mulh node
517 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
518 ir_node *proj_EAX, *proj_EDX, *mulh;
521 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
522 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
523 mulh = get_Proj_pred(proj_EAX);
524 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
526 /* to be on the save side */
527 set_Proj_proj(proj_EAX, pn_EAX);
529 if (get_ia32_cnst(mulh)) {
530 /* Mulh with const cannot have AM */
531 set_ia32_am_support(mulh, ia32_am_None);
534 /* Mulh cannot have AM for destination */
535 set_ia32_am_support(mulh, ia32_am_Source);
541 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
549 * Creates an ia32 And.
551 * @param env The transformation environment
552 * @param op1 The first operator
553 * @param op2 The second operator
554 * @return The created ia32 And node
556 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
557 if (mode_is_float(env->mode)) {
558 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
561 return gen_binop(env, op1, op2, new_rd_ia32_And);
568 * Creates an ia32 Or.
570 * @param env The transformation environment
571 * @param op1 The first operator
572 * @param op2 The second operator
573 * @return The created ia32 Or node
575 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
576 if (mode_is_float(env->mode)) {
577 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
580 return gen_binop(env, op1, op2, new_rd_ia32_Or);
587 * Creates an ia32 Eor.
589 * @param env The transformation environment
590 * @param op1 The first operator
591 * @param op2 The second operator
592 * @return The created ia32 Eor node
594 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
595 if (mode_is_float(env->mode)) {
596 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
599 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
606 * Creates an ia32 Max.
608 * @param env The transformation environment
609 * @param op1 The first operator
610 * @param op2 The second operator
611 * @return the created ia32 Max node
613 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
616 if (mode_is_float(env->mode)) {
617 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
620 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
621 set_ia32_am_support(new_op, ia32_am_None);
622 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
631 * Creates an ia32 Min.
633 * @param env The transformation environment
634 * @param op1 The first operator
635 * @param op2 The second operator
636 * @return the created ia32 Min node
638 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
641 if (mode_is_float(env->mode)) {
642 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
645 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
646 set_ia32_am_support(new_op, ia32_am_None);
647 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
656 * Creates an ia32 Sub with immediate.
658 * @param env The transformation environment
659 * @param op1 The first operator
660 * @param op2 The second operator
661 * @return The created ia32 Sub node
663 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
664 ir_node *new_op = NULL;
665 tarval *tv = get_ia32_Immop_tarval(const_op);
666 firm_dbg_module_t *mod = env->mod;
667 dbg_info *dbg = env->dbg;
668 ir_graph *irg = env->irg;
669 ir_node *block = env->block;
670 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
671 ir_node *nomem = new_NoMem();
673 tarval_classification_t class_tv, class_negtv;
675 /* try to optimize to inc/dec */
676 if (env->cg->opt.incdec && tv) {
677 /* optimize tarvals */
678 class_tv = classify_tarval(tv);
679 class_negtv = classify_tarval(tarval_neg(tv));
681 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
682 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
683 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
686 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
687 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
688 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
694 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
695 set_ia32_Immop_attr(new_op, const_op);
702 * Creates an ia32 Sub.
704 * @param env The transformation environment
705 * @param op1 The first operator
706 * @param op2 The second operator
707 * @return The created ia32 Sub node
709 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
710 ir_node *new_op = NULL;
711 dbg_info *dbg = env->dbg;
712 ir_mode *mode = env->mode;
713 ir_graph *irg = env->irg;
714 ir_node *block = env->block;
715 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
716 ir_node *nomem = new_NoMem();
717 ir_node *expr_op, *imm_op;
719 /* Check if immediate optimization is on and */
720 /* if it's an operation with immediate. */
721 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
722 expr_op = get_expr_op(op1, op2);
724 assert((expr_op || imm_op) && "invalid operands");
726 if (mode_is_float(mode)) {
727 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
732 /* No expr_op means, that we have two const - one symconst and */
733 /* one tarval or another symconst - because this case is not */
734 /* covered by constant folding */
736 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
737 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
738 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
741 set_ia32_am_support(new_op, ia32_am_Source);
742 set_ia32_op_type(new_op, ia32_AddrModeS);
743 set_ia32_am_flavour(new_op, ia32_am_O);
745 /* Lea doesn't need a Proj */
749 /* This is expr - const */
750 new_op = gen_imm_Sub(env, expr_op, imm_op);
753 set_ia32_am_support(new_op, ia32_am_Dest);
756 /* This is a normal sub */
757 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
760 set_ia32_am_support(new_op, ia32_am_Full);
764 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
766 set_ia32_res_mode(new_op, mode);
768 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
771 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
772 const ir_edge_t *edge;
774 assert(get_irn_mode(irn) == mode_T && "need mode_T");
776 foreach_out_edge(irn, edge) {
777 proj = get_edge_src_irn(edge);
779 if (get_Proj_proj(proj) == pn)
787 * Generates an ia32 DivMod with additional infrastructure for the
788 * register allocator if needed.
790 * @param env The transformation environment
791 * @param dividend -no comment- :)
792 * @param divisor -no comment- :)
793 * @param dm_flav flavour_Div/Mod/DivMod
794 * @return The created ia32 DivMod node
796 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
798 ir_node *edx_node, *cltd;
800 dbg_info *dbg = env->dbg;
801 ir_graph *irg = env->irg;
802 ir_node *block = env->block;
803 ir_mode *mode = env->mode;
804 ir_node *irn = env->irn;
809 mem = get_Div_mem(irn);
810 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
813 mem = get_Mod_mem(irn);
814 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
817 mem = get_DivMod_mem(irn);
818 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
824 if (mode_is_signed(mode)) {
825 /* in signed mode, we need to sign extend the dividend */
826 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
827 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
828 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
831 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
832 set_ia32_Const_type(edx_node, ia32_Const);
833 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
836 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
838 set_ia32_flavour(res, dm_flav);
839 set_ia32_n_res(res, 2);
841 /* Only one proj is used -> We must add a second proj and */
842 /* connect this one to a Keep node to eat up the second */
843 /* destroyed register. */
844 if (get_irn_n_edges(irn) == 1) {
845 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
846 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
848 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
849 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
852 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
855 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
858 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
860 set_ia32_res_mode(res, mode_Is);
867 * Wrapper for generate_DivMod. Sets flavour_Mod.
869 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
870 return generate_DivMod(env, op1, op2, flavour_Mod);
876 * Wrapper for generate_DivMod. Sets flavour_Div.
878 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
879 return generate_DivMod(env, op1, op2, flavour_Div);
885 * Wrapper for generate_DivMod. Sets flavour_DivMod.
887 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
888 return generate_DivMod(env, op1, op2, flavour_DivMod);
894 * Creates an ia32 floating Div.
896 * @param env The transformation environment
897 * @param op1 The first operator
898 * @param op2 The second operator
899 * @return The created ia32 fDiv node
901 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
902 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
903 ir_node *nomem = new_rd_NoMem(env->irg);
906 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
907 set_ia32_am_support(new_op, ia32_am_Source);
909 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
917 * Creates an ia32 Shl.
919 * @param env The transformation environment
920 * @param op1 The first operator
921 * @param op2 The second operator
922 * @return The created ia32 Shl node
924 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
925 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
931 * Creates an ia32 Shr.
933 * @param env The transformation environment
934 * @param op1 The first operator
935 * @param op2 The second operator
936 * @return The created ia32 Shr node
938 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
939 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
945 * Creates an ia32 Shrs.
947 * @param env The transformation environment
948 * @param op1 The first operator
949 * @param op2 The second operator
950 * @return The created ia32 Shrs node
952 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
953 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
959 * Creates an ia32 RotL.
961 * @param env The transformation environment
962 * @param op1 The first operator
963 * @param op2 The second operator
964 * @return The created ia32 RotL node
966 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
967 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
973 * Creates an ia32 RotR.
974 * NOTE: There is no RotR with immediate because this would always be a RotL
975 * "imm-mode_size_bits" which can be pre-calculated.
977 * @param env The transformation environment
978 * @param op1 The first operator
979 * @param op2 The second operator
980 * @return The created ia32 RotR node
982 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
983 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
989 * Creates an ia32 RotR or RotL (depending on the found pattern).
991 * @param env The transformation environment
992 * @param op1 The first operator
993 * @param op2 The second operator
994 * @return The created ia32 RotL or RotR node
996 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
997 ir_node *rotate = NULL;
999 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1000 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1001 that means we can create a RotR instead of an Add and a RotL */
1004 ir_node *pred = get_Proj_pred(op2);
1006 if (is_ia32_Add(pred)) {
1007 ir_node *pred_pred = get_irn_n(pred, 2);
1008 tarval *tv = get_ia32_Immop_tarval(pred);
1009 long bits = get_mode_size_bits(env->mode);
1011 if (is_Proj(pred_pred)) {
1012 pred_pred = get_Proj_pred(pred_pred);
1015 if (is_ia32_Minus(pred_pred) &&
1016 tarval_is_long(tv) &&
1017 get_tarval_long(tv) == bits)
1019 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1020 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1027 rotate = gen_RotL(env, op1, op2);
1036 * Transforms a Minus node.
1038 * @param env The transformation environment
1039 * @param op The operator
1040 * @return The created ia32 Minus node
1042 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1045 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1046 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1047 ir_node *nomem = new_rd_NoMem(env->irg);
1050 if (mode_is_float(env->mode)) {
1051 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1053 size = get_mode_size_bits(env->mode);
1054 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1056 set_ia32_sc(new_op, name);
1058 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1060 set_ia32_res_mode(new_op, env->mode);
1062 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1065 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1074 * Transforms a Not node.
1076 * @param env The transformation environment
1077 * @param op The operator
1078 * @return The created ia32 Not node
1080 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1083 if (mode_is_float(env->mode)) {
1087 new_op = gen_unop(env, op, new_rd_ia32_Not);
1096 * Transforms an Abs node.
1098 * @param env The transformation environment
1099 * @param op The operator
1100 * @return The created ia32 Abs node
1102 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1103 ir_node *res, *p_eax, *p_edx;
1104 dbg_info *dbg = env->dbg;
1105 ir_mode *mode = env->mode;
1106 ir_graph *irg = env->irg;
1107 ir_node *block = env->block;
1108 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1109 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1110 ir_node *nomem = new_NoMem();
1114 if (mode_is_float(mode)) {
1115 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1117 size = get_mode_size_bits(mode);
1118 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1120 set_ia32_sc(res, name);
1122 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1124 set_ia32_res_mode(res, mode);
1126 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1129 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1130 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1131 set_ia32_res_mode(res, mode);
1133 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1134 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1136 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1137 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1138 set_ia32_res_mode(res, mode);
1140 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1142 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1143 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1144 set_ia32_res_mode(res, mode);
1146 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1155 * Transforms a Load.
1157 * @param mod the debug module
1158 * @param block the block the new node should belong to
1159 * @param node the ir Load node
1160 * @param mode node mode
1161 * @return the created ia32 Load node
1163 static ir_node *gen_Load(ia32_transform_env_t *env) {
1164 ir_node *node = env->irn;
1165 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1168 if (mode_is_float(env->mode)) {
1169 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1172 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1175 set_ia32_am_support(new_op, ia32_am_Source);
1176 set_ia32_op_type(new_op, ia32_AddrModeS);
1177 set_ia32_am_flavour(new_op, ia32_B);
1178 set_ia32_ls_mode(new_op, get_Load_mode(node));
1180 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1188 * Transforms a Store.
1190 * @param mod the debug module
1191 * @param block the block the new node should belong to
1192 * @param node the ir Store node
1193 * @param mode node mode
1194 * @return the created ia32 Store node
1196 static ir_node *gen_Store(ia32_transform_env_t *env) {
1197 ir_node *node = env->irn;
1198 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1199 ir_node *val = get_Store_value(node);
1200 ir_node *ptr = get_Store_ptr(node);
1201 ir_node *mem = get_Store_mem(node);
1202 ir_mode *mode = get_irn_mode(val);
1203 ir_node *sval = val;
1206 /* in case of storing a const (but not a symconst) -> make it an attribute */
1207 if (is_ia32_Const(val)) {
1211 if (mode_is_float(mode)) {
1212 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1214 else if (get_mode_size_bits(mode) == 8) {
1215 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1218 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1221 /* stored const is an attribute (saves a register) */
1222 if (is_ia32_Const(val)) {
1223 set_ia32_Immop_attr(new_op, val);
1226 set_ia32_am_support(new_op, ia32_am_Dest);
1227 set_ia32_op_type(new_op, ia32_AddrModeD);
1228 set_ia32_am_flavour(new_op, ia32_B);
1229 set_ia32_ls_mode(new_op, get_irn_mode(val));
1231 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1239 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1241 * @param env The transformation environment
1242 * @return The transformed node.
1244 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1245 dbg_info *dbg = env->dbg;
1246 ir_graph *irg = env->irg;
1247 ir_node *block = env->block;
1248 ir_node *node = env->irn;
1249 ir_node *sel = get_Cond_selector(node);
1250 ir_mode *sel_mode = get_irn_mode(sel);
1251 ir_node *res = NULL;
1252 ir_node *pred = NULL;
1253 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1254 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1256 if (is_Proj(sel) && sel_mode == mode_b) {
1257 ir_node *nomem = new_NoMem();
1259 pred = get_Proj_pred(sel);
1261 /* get both compare operators */
1262 cmp_a = get_Cmp_left(pred);
1263 cmp_b = get_Cmp_right(pred);
1265 /* check if we can use a CondJmp with immediate */
1266 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1267 expr = get_expr_op(cmp_a, cmp_b);
1270 if (mode_is_int(get_irn_mode(expr))) {
1271 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1273 ir_node *op1 = expr;
1274 ir_node *op2 = expr;
1275 ir_node *and = skip_Proj(expr);
1278 /* check, if expr is an only once used And operation */
1279 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1280 op1 = get_irn_n(and, 2);
1281 op2 = get_irn_n(and, 3);
1283 cnst = get_ia32_cnst(and);
1285 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1286 set_ia32_pncode(res, get_Proj_proj(sel));
1289 copy_ia32_Immop_attr(res, and);
1292 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1296 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1297 set_ia32_Immop_attr(res, cnst);
1300 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1303 set_ia32_pncode(res, get_Proj_proj(sel));
1304 set_ia32_am_support(res, ia32_am_Source);
1307 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1308 set_ia32_pncode(res, get_Cond_defaultProj(node));
1311 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1318 * Transforms a CopyB node.
1320 * @param env The transformation environment
1321 * @return The transformed node.
1323 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1324 ir_node *res = NULL;
1325 dbg_info *dbg = env->dbg;
1326 ir_graph *irg = env->irg;
1327 ir_mode *mode = env->mode;
1328 ir_node *block = env->block;
1329 ir_node *node = env->irn;
1330 ir_node *src = get_CopyB_src(node);
1331 ir_node *dst = get_CopyB_dst(node);
1332 ir_node *mem = get_CopyB_mem(node);
1333 int size = get_type_size_bytes(get_CopyB_type(node));
1336 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1337 /* then we need the size explicitly in ECX. */
1338 if (size >= 16 * 4) {
1339 rem = size & 0x3; /* size % 4 */
1342 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1343 set_ia32_op_type(res, ia32_Const);
1344 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1346 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1347 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1350 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1351 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1354 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1362 * Transforms a Mux node into CMov.
1364 * @param env The transformation environment
1365 * @return The transformed node.
1367 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1368 ir_node *node = env->irn;
1369 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1370 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1372 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1379 * Following conversion rules apply:
1383 * 1) n bit -> m bit n > m (downscale)
1384 * a) target is signed: movsx
1385 * b) target is unsigned: and with lower bits sets
1386 * 2) n bit -> m bit n == m (sign change)
1388 * 3) n bit -> m bit n < m (upscale)
1389 * a) source is signed: movsx
1390 * b) source is unsigned: and with lower bits sets
1394 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1398 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1399 * if target mode < 32bit: additional INT -> INT conversion (see above)
1403 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1406 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1407 // ir_mode *src_mode, ir_mode *tgt_mode)
1409 // int n = get_mode_size_bits(src_mode);
1410 // int m = get_mode_size_bits(tgt_mode);
1411 // dbg_info *dbg = env->dbg;
1412 // ir_graph *irg = env->irg;
1413 // ir_node *block = env->block;
1414 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1415 // ir_node *nomem = new_rd_NoMem(irg);
1416 // ir_node *new_op, *proj;
1417 // assert(n > m && "downscale expected");
1418 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1419 // /* ASHL Sn, n - m */
1420 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1421 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1422 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1423 // set_ia32_am_support(new_op, ia32_am_Source);
1424 // SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1425 // /* ASHR Sn, n - m */
1426 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1427 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1430 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1431 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1437 * Transforms a Conv node.
1439 * @param env The transformation environment
1440 * @param op The operator
1441 * @return The created ia32 Conv node
1443 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1444 dbg_info *dbg = env->dbg;
1445 ir_graph *irg = env->irg;
1446 ir_mode *src_mode = get_irn_mode(op);
1447 ir_mode *tgt_mode = env->mode;
1448 ir_node *block = env->block;
1449 ir_node *new_op = NULL;
1450 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1451 ir_node *nomem = new_rd_NoMem(irg);
1452 firm_dbg_module_t *mod = env->mod;
1455 if (src_mode == tgt_mode) {
1456 /* this can happen when changing mode_P to mode_Is */
1457 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1458 edges_reroute(env->irn, op, irg);
1460 else if (mode_is_float(src_mode)) {
1461 /* we convert from float ... */
1462 if (mode_is_float(tgt_mode)) {
1464 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1465 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1469 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1470 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1471 /* if target mode is not int: add an additional downscale convert */
1472 if (get_mode_size_bits(tgt_mode) < 32) {
1473 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1474 set_ia32_res_mode(new_op, tgt_mode);
1475 set_ia32_am_support(new_op, ia32_am_Source);
1477 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1478 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1483 /* we convert from int ... */
1484 if (mode_is_float(tgt_mode)) {
1486 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1487 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1491 if (get_mode_size_bits(src_mode) == get_mode_size_bits(tgt_mode)) {
1492 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1493 edges_reroute(env->irn, op, irg);
1496 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1497 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1503 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1504 set_ia32_res_mode(new_op, tgt_mode);
1506 set_ia32_am_support(new_op, ia32_am_Source);
1508 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1516 /********************************************
1519 * | |__ ___ _ __ ___ __| | ___ ___
1520 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1521 * | |_) | __/ | | | (_) | (_| | __/\__ \
1522 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1524 ********************************************/
1526 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1527 ir_node *new_op = NULL;
1528 ir_node *node = env->irn;
1529 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1530 ir_node *mem = new_rd_NoMem(env->irg);
1531 ir_node *ptr = get_irn_n(node, 0);
1532 entity *ent = be_get_frame_entity(node);
1533 ir_mode *mode = env->mode;
1535 if (mode_is_float(mode)) {
1536 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1539 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1542 set_ia32_frame_ent(new_op, ent);
1543 set_ia32_use_frame(new_op);
1545 set_ia32_am_support(new_op, ia32_am_Source);
1546 set_ia32_op_type(new_op, ia32_AddrModeS);
1547 set_ia32_am_flavour(new_op, ia32_B);
1548 set_ia32_ls_mode(new_op, mode);
1550 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1552 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1556 * Transforms a FrameAddr into an ia32 Add.
1558 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1559 ir_node *new_op = NULL;
1560 ir_node *node = env->irn;
1561 ir_node *op = get_irn_n(node, 0);
1562 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1563 ir_node *nomem = new_rd_NoMem(env->irg);
1565 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1566 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1567 set_ia32_am_support(new_op, ia32_am_Full);
1568 set_ia32_use_frame(new_op);
1570 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1572 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1576 * Transforms a FrameLoad into an ia32 Load.
1578 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1579 ir_node *new_op = NULL;
1580 ir_node *node = env->irn;
1581 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1582 ir_node *mem = get_irn_n(node, 0);
1583 ir_node *ptr = get_irn_n(node, 1);
1584 entity *ent = be_get_frame_entity(node);
1585 ir_mode *mode = get_type_mode(get_entity_type(ent));
1587 if (mode_is_float(mode)) {
1588 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1591 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1594 set_ia32_frame_ent(new_op, ent);
1595 set_ia32_use_frame(new_op);
1597 set_ia32_am_support(new_op, ia32_am_Source);
1598 set_ia32_op_type(new_op, ia32_AddrModeS);
1599 set_ia32_am_flavour(new_op, ia32_B);
1600 set_ia32_ls_mode(new_op, mode);
1602 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1609 * Transforms a FrameStore into an ia32 Store.
1611 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1612 ir_node *new_op = NULL;
1613 ir_node *node = env->irn;
1614 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1615 ir_node *mem = get_irn_n(node, 0);
1616 ir_node *ptr = get_irn_n(node, 1);
1617 ir_node *val = get_irn_n(node, 2);
1618 entity *ent = be_get_frame_entity(node);
1619 ir_mode *mode = get_irn_mode(val);
1621 if (mode_is_float(mode)) {
1622 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1624 else if (get_mode_size_bits(mode) == 8) {
1625 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1628 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1631 set_ia32_frame_ent(new_op, ent);
1632 set_ia32_use_frame(new_op);
1634 set_ia32_am_support(new_op, ia32_am_Dest);
1635 set_ia32_op_type(new_op, ia32_AddrModeD);
1636 set_ia32_am_flavour(new_op, ia32_B);
1637 set_ia32_ls_mode(new_op, mode);
1639 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1646 /*********************************************************
1649 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1650 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1651 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1652 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1654 *********************************************************/
1657 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1658 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1660 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1661 ia32_transform_env_t tenv;
1662 ir_node *in1, *in2, *noreg, *nomem, *res;
1663 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1665 /* Return if AM node or not a Sub or fSub */
1666 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1669 noreg = ia32_new_NoReg_gp(cg);
1670 nomem = new_rd_NoMem(cg->irg);
1671 in1 = get_irn_n(irn, 2);
1672 in2 = get_irn_n(irn, 3);
1673 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1674 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1675 out_reg = get_ia32_out_reg(irn, 0);
1677 tenv.block = get_nodes_block(irn);
1678 tenv.dbg = get_irn_dbg_info(irn);
1682 tenv.mode = get_ia32_res_mode(irn);
1685 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1686 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1687 /* generate the neg src2 */
1688 res = gen_Minus(&tenv, in2);
1689 arch_set_irn_register(cg->arch_env, res, in2_reg);
1691 /* add to schedule */
1692 sched_add_before(irn, res);
1694 /* generate the add */
1695 if (mode_is_float(tenv.mode)) {
1696 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1697 set_ia32_am_support(res, ia32_am_Source);
1700 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1701 set_ia32_am_support(res, ia32_am_Full);
1704 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1706 slots = get_ia32_slots(res);
1709 /* add to schedule */
1710 sched_add_before(irn, res);
1712 /* remove the old sub */
1715 /* exchange the add and the sub */
1721 * Transforms a LEA into an Add if possible
1722 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1724 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1725 ia32_am_flavour_t am_flav;
1727 ir_node *res = NULL;
1728 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1730 ia32_transform_env_t tenv;
1731 const arch_register_t *out_reg, *base_reg, *index_reg;
1734 if (! is_ia32_Lea(irn))
1737 am_flav = get_ia32_am_flavour(irn);
1739 /* only some LEAs can be transformed to an Add */
1740 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1743 noreg = ia32_new_NoReg_gp(cg);
1744 nomem = new_rd_NoMem(cg->irg);
1747 base = get_irn_n(irn, 0);
1748 index = get_irn_n(irn,1);
1750 offs = get_ia32_am_offs(irn);
1752 /* offset has a explicit sign -> we need to skip + */
1753 if (offs && offs[0] == '+')
1756 out_reg = arch_get_irn_register(cg->arch_env, irn);
1757 base_reg = arch_get_irn_register(cg->arch_env, base);
1758 index_reg = arch_get_irn_register(cg->arch_env, index);
1760 tenv.block = get_nodes_block(irn);
1761 tenv.dbg = get_irn_dbg_info(irn);
1765 tenv.mode = get_irn_mode(irn);
1768 switch(get_ia32_am_flavour(irn)) {
1770 /* out register must be same as base register */
1771 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1777 /* out register must be same as base register */
1778 if (! REGS_ARE_EQUAL(out_reg, base_reg))
1785 /* out register must be same as index register */
1786 if (! REGS_ARE_EQUAL(out_reg, index_reg))
1793 /* out register must be same as one in register */
1794 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
1798 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
1803 /* in registers a different from out -> no Add possible */
1810 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
1811 arch_set_irn_register(cg->arch_env, res, out_reg);
1812 set_ia32_op_type(res, ia32_Normal);
1815 set_ia32_cnst(res, offs);
1817 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1819 /* add Add to schedule */
1820 sched_add_before(irn, res);
1822 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
1824 /* add result Proj to schedule */
1825 sched_add_before(irn, res);
1827 /* remove the old LEA */
1830 /* exchange the Add and the LEA */
1835 * Transforms the given firm node (and maybe some other related nodes)
1836 * into one or more assembler nodes.
1838 * @param node the firm node
1839 * @param env the debug module
1841 void ia32_transform_node(ir_node *node, void *env) {
1842 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1844 ir_node *asm_node = NULL;
1845 ia32_transform_env_t tenv;
1850 tenv.block = get_nodes_block(node);
1851 tenv.dbg = get_irn_dbg_info(node);
1852 tenv.irg = current_ir_graph;
1854 tenv.mod = cgenv->mod;
1855 tenv.mode = get_irn_mode(node);
1858 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1859 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1860 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1861 #define IGN(a) case iro_##a: break
1862 #define BAD(a) case iro_##a: goto bad
1863 #define OTHER_BIN(a) \
1864 if (get_irn_op(node) == get_op_##a()) { \
1865 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1869 if (be_is_##a(node)) { \
1870 asm_node = gen_##a(&tenv); \
1874 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1876 code = get_irn_opcode(node);
1922 /* constant transformation happens earlier */
1952 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1956 /* exchange nodes if a new one was generated */
1958 exchange(node, asm_node);
1959 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1962 DB((tenv.mod, LEVEL_1, "ignored\n"));