2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_common_transform.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 #define SFP_SIGN "0x80000000"
74 #define DFP_SIGN "0x8000000000000000"
75 #define SFP_ABS "0x7FFFFFFF"
76 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define DFP_INTMAX "9223372036854775807"
78 #define ULL_BIAS "18446744073709551616"
80 #define TP_SFP_SIGN "ia32_sfp_sign"
81 #define TP_DFP_SIGN "ia32_dfp_sign"
82 #define TP_SFP_ABS "ia32_sfp_abs"
83 #define TP_DFP_ABS "ia32_dfp_abs"
84 #define TP_ULL_BIAS "ia32_ull_bias"
86 #define ENT_SFP_SIGN ".LC_ia32_sfp_sign"
87 #define ENT_DFP_SIGN ".LC_ia32_dfp_sign"
88 #define ENT_SFP_ABS ".LC_ia32_sfp_abs"
89 #define ENT_DFP_ABS ".LC_ia32_dfp_abs"
90 #define ENT_ULL_BIAS ".LC_ia32_ull_bias"
92 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
93 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
95 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
97 static ir_node *initial_fpcw = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
102 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
105 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
106 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
109 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
110 ir_node *op1, ir_node *op2);
112 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
113 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
115 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
116 ir_node *base, ir_node *index, ir_node *mem);
118 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
119 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
122 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
124 static ir_node *create_immediate_or_transform(ir_node *node,
125 char immediate_constraint_type);
127 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
128 dbg_info *dbgi, ir_node *block,
129 ir_node *op, ir_node *orig_node);
131 /** Return non-zero is a node represents the 0 constant. */
132 static bool is_Const_0(ir_node *node)
134 return is_Const(node) && is_Const_null(node);
137 /** Return non-zero is a node represents the 1 constant. */
138 static bool is_Const_1(ir_node *node)
140 return is_Const(node) && is_Const_one(node);
143 /** Return non-zero is a node represents the -1 constant. */
144 static bool is_Const_Minus_1(ir_node *node)
146 return is_Const(node) && is_Const_all_one(node);
150 * returns true if constant can be created with a simple float command
152 static bool is_simple_x87_Const(ir_node *node)
154 tarval *tv = get_Const_tarval(node);
155 if (tarval_is_null(tv) || tarval_is_one(tv))
158 /* TODO: match all the other float constants */
163 * returns true if constant can be created with a simple float command
165 static bool is_simple_sse_Const(ir_node *node)
167 tarval *tv = get_Const_tarval(node);
168 ir_mode *mode = get_tarval_mode(tv);
173 if (tarval_is_null(tv) || tarval_is_one(tv))
176 if (mode == mode_D) {
177 unsigned val = get_tarval_sub_bits(tv, 0) |
178 (get_tarval_sub_bits(tv, 1) << 8) |
179 (get_tarval_sub_bits(tv, 2) << 16) |
180 (get_tarval_sub_bits(tv, 3) << 24);
182 /* lower 32bit are zero, really a 32bit constant */
186 /* TODO: match all the other float constants */
191 * Transforms a Const.
193 static ir_node *gen_Const(ir_node *node)
195 ir_node *old_block = get_nodes_block(node);
196 ir_node *block = be_transform_node(old_block);
197 dbg_info *dbgi = get_irn_dbg_info(node);
198 ir_mode *mode = get_irn_mode(node);
200 assert(is_Const(node));
202 if (mode_is_float(mode)) {
204 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
205 ir_node *nomem = new_NoMem();
209 if (ia32_cg_config.use_sse2) {
210 tarval *tv = get_Const_tarval(node);
211 if (tarval_is_null(tv)) {
212 load = new_bd_ia32_xZero(dbgi, block);
213 set_ia32_ls_mode(load, mode);
215 } else if (tarval_is_one(tv)) {
216 int cnst = mode == mode_F ? 26 : 55;
217 ir_node *imm1 = create_Immediate(NULL, 0, cnst);
218 ir_node *imm2 = create_Immediate(NULL, 0, 2);
219 ir_node *pslld, *psrld;
221 load = new_bd_ia32_xAllOnes(dbgi, block);
222 set_ia32_ls_mode(load, mode);
223 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
224 set_ia32_ls_mode(pslld, mode);
225 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
226 set_ia32_ls_mode(psrld, mode);
228 } else if (mode == mode_F) {
229 /* we can place any 32bit constant by using a movd gp, sse */
230 unsigned val = get_tarval_sub_bits(tv, 0) |
231 (get_tarval_sub_bits(tv, 1) << 8) |
232 (get_tarval_sub_bits(tv, 2) << 16) |
233 (get_tarval_sub_bits(tv, 3) << 24);
234 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
235 load = new_bd_ia32_xMovd(dbgi, block, cnst);
236 set_ia32_ls_mode(load, mode);
239 if (mode == mode_D) {
240 unsigned val = get_tarval_sub_bits(tv, 0) |
241 (get_tarval_sub_bits(tv, 1) << 8) |
242 (get_tarval_sub_bits(tv, 2) << 16) |
243 (get_tarval_sub_bits(tv, 3) << 24);
245 ir_node *imm32 = create_Immediate(NULL, 0, 32);
246 ir_node *cnst, *psllq;
248 /* fine, lower 32bit are zero, produce 32bit value */
249 val = get_tarval_sub_bits(tv, 4) |
250 (get_tarval_sub_bits(tv, 5) << 8) |
251 (get_tarval_sub_bits(tv, 6) << 16) |
252 (get_tarval_sub_bits(tv, 7) << 24);
253 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
254 load = new_bd_ia32_xMovd(dbgi, block, cnst);
255 set_ia32_ls_mode(load, mode);
256 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
257 set_ia32_ls_mode(psllq, mode);
262 floatent = create_float_const_entity(node);
264 load = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem,
266 set_ia32_op_type(load, ia32_AddrModeS);
267 set_ia32_am_sc(load, floatent);
268 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
269 res = new_r_Proj(current_ir_graph, block, load, mode_xmm, pn_ia32_xLoad_res);
272 if (is_Const_null(node)) {
273 load = new_bd_ia32_vfldz(dbgi, block);
275 set_ia32_ls_mode(load, mode);
276 } else if (is_Const_one(node)) {
277 load = new_bd_ia32_vfld1(dbgi, block);
279 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode);
284 set_ia32_op_type(load, ia32_AddrModeS);
285 set_ia32_am_sc(load, floatent);
286 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
287 res = new_r_Proj(current_ir_graph, block, load, mode_vfp, pn_ia32_vfld_res);
288 /* take the mode from the entity */
289 set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent)));
293 SET_IA32_ORIG_NODE(load, node);
295 be_dep_on_frame(load);
297 } else { /* non-float mode */
299 tarval *tv = get_Const_tarval(node);
302 tv = tarval_convert_to(tv, mode_Iu);
304 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
306 panic("couldn't convert constant tarval (%+F)", node);
308 val = get_tarval_long(tv);
310 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
311 SET_IA32_ORIG_NODE(cnst, node);
313 be_dep_on_frame(cnst);
319 * Transforms a SymConst.
321 static ir_node *gen_SymConst(ir_node *node)
323 ir_node *old_block = get_nodes_block(node);
324 ir_node *block = be_transform_node(old_block);
325 dbg_info *dbgi = get_irn_dbg_info(node);
326 ir_mode *mode = get_irn_mode(node);
329 if (mode_is_float(mode)) {
330 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
331 ir_node *nomem = new_NoMem();
333 if (ia32_cg_config.use_sse2)
334 cnst = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem, mode_E);
336 cnst = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode_E);
337 set_ia32_am_sc(cnst, get_SymConst_entity(node));
338 set_ia32_use_frame(cnst);
342 if (get_SymConst_kind(node) != symconst_addr_ent) {
343 panic("backend only support symconst_addr_ent (at %+F)", node);
345 entity = get_SymConst_entity(node);
346 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0);
349 SET_IA32_ORIG_NODE(cnst, node);
351 be_dep_on_frame(cnst);
355 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
356 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
358 static const struct {
360 const char *ent_name;
361 const char *cnst_str;
364 } names [ia32_known_const_max] = {
365 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
366 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
367 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
368 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
369 { TP_ULL_BIAS, ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
371 static ir_entity *ent_cache[ia32_known_const_max];
373 const char *tp_name, *ent_name, *cnst_str;
379 ent_name = names[kct].ent_name;
380 if (! ent_cache[kct]) {
381 tp_name = names[kct].tp_name;
382 cnst_str = names[kct].cnst_str;
384 switch (names[kct].mode) {
385 case 0: mode = mode_Iu; break;
386 case 1: mode = mode_Lu; break;
387 default: mode = mode_F; break;
389 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
390 tp = new_type_primitive(new_id_from_str(tp_name), mode);
391 /* set the specified alignment */
392 set_type_alignment_bytes(tp, names[kct].align);
394 if (kct == ia32_ULLBIAS) {
395 /* we are in the backend, construct a fixed type here */
396 unsigned size = get_type_size_bytes(tp);
397 tp = new_type_array(new_id_from_str(tp_name), 1, tp);
398 set_type_alignment_bytes(tp, names[kct].align);
399 set_type_size_bytes(tp, 2 * size);
400 set_type_state(tp, layout_fixed);
402 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
404 set_entity_ld_ident(ent, get_entity_ident(ent));
405 set_entity_visibility(ent, visibility_local);
406 set_entity_variability(ent, variability_constant);
407 set_entity_allocation(ent, allocation_static);
409 if (kct == ia32_ULLBIAS) {
410 ir_initializer_t *initializer = create_initializer_compound(2);
412 set_initializer_compound_value(initializer, 0,
413 create_initializer_tarval(get_tarval_null(mode)));
414 set_initializer_compound_value(initializer, 1,
415 create_initializer_tarval(tv));
417 set_entity_initializer(ent, initializer);
419 set_entity_initializer(ent, create_initializer_tarval(tv));
422 /* cache the entry */
423 ent_cache[kct] = ent;
426 return ent_cache[kct];
430 * return true if the node is a Proj(Load) and could be used in source address
431 * mode for another node. Will return only true if the @p other node is not
432 * dependent on the memory of the Load (for binary operations use the other
433 * input here, for unary operations use NULL).
435 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
436 ir_node *other, ir_node *other2, match_flags_t flags)
441 /* float constants are always available */
442 if (is_Const(node)) {
443 ir_mode *mode = get_irn_mode(node);
444 if (mode_is_float(mode)) {
445 if (ia32_cg_config.use_sse2) {
446 if (is_simple_sse_Const(node))
449 if (is_simple_x87_Const(node))
452 if (get_irn_n_edges(node) > 1)
460 load = get_Proj_pred(node);
461 pn = get_Proj_proj(node);
462 if (!is_Load(load) || pn != pn_Load_res)
464 if (get_nodes_block(load) != block)
466 /* we only use address mode if we're the only user of the load */
467 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
469 /* in some edge cases with address mode we might reach the load normally
470 * and through some AM sequence, if it is already materialized then we
471 * can't create an AM node from it */
472 if (be_is_transformed(node))
475 /* don't do AM if other node inputs depend on the load (via mem-proj) */
476 if (other != NULL && prevents_AM(block, load, other))
479 if (other2 != NULL && prevents_AM(block, load, other2))
485 typedef struct ia32_address_mode_t ia32_address_mode_t;
486 struct ia32_address_mode_t {
491 ia32_op_type_t op_type;
495 unsigned commutative : 1;
496 unsigned ins_permuted : 1;
499 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
503 /* construct load address */
504 memset(addr, 0, sizeof(addr[0]));
505 ia32_create_address_mode(addr, ptr, 0);
507 noreg_gp = ia32_new_NoReg_gp(env_cg);
508 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
509 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
510 addr->mem = be_transform_node(mem);
513 static void build_address(ia32_address_mode_t *am, ir_node *node,
514 ia32_create_am_flags_t flags)
516 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
517 ia32_address_t *addr = &am->addr;
523 if (is_Const(node)) {
524 ir_entity *entity = create_float_const_entity(node);
525 addr->base = noreg_gp;
526 addr->index = noreg_gp;
527 addr->mem = new_NoMem();
528 addr->symconst_ent = entity;
530 am->ls_mode = get_type_mode(get_entity_type(entity));
531 am->pinned = op_pin_state_floats;
535 load = get_Proj_pred(node);
536 ptr = get_Load_ptr(load);
537 mem = get_Load_mem(load);
538 new_mem = be_transform_node(mem);
539 am->pinned = get_irn_pinned(load);
540 am->ls_mode = get_Load_mode(load);
541 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
544 /* construct load address */
545 ia32_create_address_mode(addr, ptr, flags);
547 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
548 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
552 static void set_address(ir_node *node, const ia32_address_t *addr)
554 set_ia32_am_scale(node, addr->scale);
555 set_ia32_am_sc(node, addr->symconst_ent);
556 set_ia32_am_offs_int(node, addr->offset);
557 if (addr->symconst_sign)
558 set_ia32_am_sc_sign(node);
560 set_ia32_use_frame(node);
561 set_ia32_frame_ent(node, addr->frame_entity);
565 * Apply attributes of a given address mode to a node.
567 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
569 set_address(node, &am->addr);
571 set_ia32_op_type(node, am->op_type);
572 set_ia32_ls_mode(node, am->ls_mode);
573 if (am->pinned == op_pin_state_pinned) {
574 /* beware: some nodes are already pinned and did not allow to change the state */
575 if (get_irn_pinned(node) != op_pin_state_pinned)
576 set_irn_pinned(node, op_pin_state_pinned);
579 set_ia32_commutative(node);
583 * Check, if a given node is a Down-Conv, ie. a integer Conv
584 * from a mode with a mode with more bits to a mode with lesser bits.
585 * Moreover, we return only true if the node has not more than 1 user.
587 * @param node the node
588 * @return non-zero if node is a Down-Conv
590 static int is_downconv(const ir_node *node)
598 /* we only want to skip the conv when we're the only user
599 * (not optimal but for now...)
601 if (get_irn_n_edges(node) > 1)
604 src_mode = get_irn_mode(get_Conv_op(node));
605 dest_mode = get_irn_mode(node);
607 ia32_mode_needs_gp_reg(src_mode) &&
608 ia32_mode_needs_gp_reg(dest_mode) &&
609 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
612 /* Skip all Down-Conv's on a given node and return the resulting node. */
613 ir_node *ia32_skip_downconv(ir_node *node)
615 while (is_downconv(node))
616 node = get_Conv_op(node);
621 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
623 ir_mode *mode = get_irn_mode(node);
628 if (mode_is_signed(mode)) {
633 block = get_nodes_block(node);
634 dbgi = get_irn_dbg_info(node);
636 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
640 * matches operands of a node into ia32 addressing/operand modes. This covers
641 * usage of source address mode, immediates, operations with non 32-bit modes,
643 * The resulting data is filled into the @p am struct. block is the block
644 * of the node whose arguments are matched. op1, op2 are the first and second
645 * input that are matched (op1 may be NULL). other_op is another unrelated
646 * input that is not matched! but which is needed sometimes to check if AM
647 * for op1/op2 is legal.
648 * @p flags describes the supported modes of the operation in detail.
650 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
651 ir_node *op1, ir_node *op2, ir_node *other_op,
654 ia32_address_t *addr = &am->addr;
655 ir_mode *mode = get_irn_mode(op2);
656 int mode_bits = get_mode_size_bits(mode);
657 ir_node *noreg_gp, *new_op1, *new_op2;
659 unsigned commutative;
660 int use_am_and_immediates;
663 memset(am, 0, sizeof(am[0]));
665 commutative = (flags & match_commutative) != 0;
666 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
667 use_am = (flags & match_am) != 0;
668 use_immediate = (flags & match_immediate) != 0;
669 assert(!use_am_and_immediates || use_immediate);
672 assert(!commutative || op1 != NULL);
673 assert(use_am || !(flags & match_8bit_am));
674 assert(use_am || !(flags & match_16bit_am));
676 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
677 (mode_bits == 16 && !(flags & match_16bit_am))) {
681 /* we can simply skip downconvs for mode neutral nodes: the upper bits
682 * can be random for these operations */
683 if (flags & match_mode_neutral) {
684 op2 = ia32_skip_downconv(op2);
686 op1 = ia32_skip_downconv(op1);
690 /* match immediates. firm nodes are normalized: constants are always on the
693 if (!(flags & match_try_am) && use_immediate) {
694 new_op2 = try_create_Immediate(op2, 0);
697 noreg_gp = ia32_new_NoReg_gp(env_cg);
698 if (new_op2 == NULL &&
699 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
700 build_address(am, op2, 0);
701 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
702 if (mode_is_float(mode)) {
703 new_op2 = ia32_new_NoReg_vfp(env_cg);
707 am->op_type = ia32_AddrModeS;
708 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
710 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
712 build_address(am, op1, 0);
714 if (mode_is_float(mode)) {
715 noreg = ia32_new_NoReg_vfp(env_cg);
720 if (new_op2 != NULL) {
723 new_op1 = be_transform_node(op2);
725 am->ins_permuted = 1;
727 am->op_type = ia32_AddrModeS;
729 am->op_type = ia32_Normal;
731 if (flags & match_try_am) {
737 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
739 new_op2 = be_transform_node(op2);
741 (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2));
743 if (addr->base == NULL)
744 addr->base = noreg_gp;
745 if (addr->index == NULL)
746 addr->index = noreg_gp;
747 if (addr->mem == NULL)
748 addr->mem = new_NoMem();
750 am->new_op1 = new_op1;
751 am->new_op2 = new_op2;
752 am->commutative = commutative;
755 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
760 if (am->mem_proj == NULL)
763 /* we have to create a mode_T so the old MemProj can attach to us */
764 mode = get_irn_mode(node);
765 load = get_Proj_pred(am->mem_proj);
767 be_set_transformed_node(load, node);
769 if (mode != mode_T) {
770 set_irn_mode(node, mode_T);
771 return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res);
778 * Construct a standard binary operation, set AM and immediate if required.
780 * @param node The original node for which the binop is created
781 * @param op1 The first operand
782 * @param op2 The second operand
783 * @param func The node constructor function
784 * @return The constructed ia32 node.
786 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
787 construct_binop_func *func, match_flags_t flags)
790 ir_node *block, *new_block, *new_node;
791 ia32_address_mode_t am;
792 ia32_address_t *addr = &am.addr;
794 block = get_nodes_block(node);
795 match_arguments(&am, block, op1, op2, NULL, flags);
797 dbgi = get_irn_dbg_info(node);
798 new_block = be_transform_node(block);
799 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
800 am.new_op1, am.new_op2);
801 set_am_attributes(new_node, &am);
802 /* we can't use source address mode anymore when using immediates */
803 if (!(flags & match_am_and_immediates) &&
804 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
805 set_ia32_am_support(new_node, ia32_am_none);
806 SET_IA32_ORIG_NODE(new_node, node);
808 new_node = fix_mem_proj(new_node, &am);
815 n_ia32_l_binop_right,
816 n_ia32_l_binop_eflags
818 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
819 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
820 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
821 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
822 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
823 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
826 * Construct a binary operation which also consumes the eflags.
828 * @param node The node to transform
829 * @param func The node constructor function
830 * @param flags The match flags
831 * @return The constructor ia32 node
833 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
836 ir_node *src_block = get_nodes_block(node);
837 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
838 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
839 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
841 ir_node *block, *new_node, *new_eflags;
842 ia32_address_mode_t am;
843 ia32_address_t *addr = &am.addr;
845 match_arguments(&am, src_block, op1, op2, eflags, flags);
847 dbgi = get_irn_dbg_info(node);
848 block = be_transform_node(src_block);
849 new_eflags = be_transform_node(eflags);
850 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
851 am.new_op1, am.new_op2, new_eflags);
852 set_am_attributes(new_node, &am);
853 /* we can't use source address mode anymore when using immediates */
854 if (!(flags & match_am_and_immediates) &&
855 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
856 set_ia32_am_support(new_node, ia32_am_none);
857 SET_IA32_ORIG_NODE(new_node, node);
859 new_node = fix_mem_proj(new_node, &am);
864 static ir_node *get_fpcw(void)
867 if (initial_fpcw != NULL)
870 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
871 &ia32_fp_cw_regs[REG_FPCW]);
872 initial_fpcw = be_transform_node(fpcw);
878 * Construct a standard binary operation, set AM and immediate if required.
880 * @param op1 The first operand
881 * @param op2 The second operand
882 * @param func The node constructor function
883 * @return The constructed ia32 node.
885 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
886 construct_binop_float_func *func)
888 ir_mode *mode = get_irn_mode(node);
890 ir_node *block, *new_block, *new_node;
891 ia32_address_mode_t am;
892 ia32_address_t *addr = &am.addr;
893 ia32_x87_attr_t *attr;
894 /* All operations are considered commutative, because there are reverse
896 match_flags_t flags = match_commutative;
898 /* cannot use address mode with long double on x87 */
899 if (get_mode_size_bits(mode) <= 64)
902 block = get_nodes_block(node);
903 match_arguments(&am, block, op1, op2, NULL, flags);
905 dbgi = get_irn_dbg_info(node);
906 new_block = be_transform_node(block);
907 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
908 am.new_op1, am.new_op2, get_fpcw());
909 set_am_attributes(new_node, &am);
911 attr = get_ia32_x87_attr(new_node);
912 attr->attr.data.ins_permuted = am.ins_permuted;
914 SET_IA32_ORIG_NODE(new_node, node);
916 new_node = fix_mem_proj(new_node, &am);
922 * Construct a shift/rotate binary operation, sets AM and immediate if required.
924 * @param op1 The first operand
925 * @param op2 The second operand
926 * @param func The node constructor function
927 * @return The constructed ia32 node.
929 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
930 construct_shift_func *func,
934 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
936 assert(! mode_is_float(get_irn_mode(node)));
937 assert(flags & match_immediate);
938 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
940 if (flags & match_mode_neutral) {
941 op1 = ia32_skip_downconv(op1);
942 new_op1 = be_transform_node(op1);
943 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
944 new_op1 = create_upconv(op1, node);
946 new_op1 = be_transform_node(op1);
949 /* the shift amount can be any mode that is bigger than 5 bits, since all
950 * other bits are ignored anyway */
951 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
952 ir_node *const op = get_Conv_op(op2);
953 if (mode_is_float(get_irn_mode(op)))
956 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
958 new_op2 = create_immediate_or_transform(op2, 0);
960 dbgi = get_irn_dbg_info(node);
961 block = get_nodes_block(node);
962 new_block = be_transform_node(block);
963 new_node = func(dbgi, new_block, new_op1, new_op2);
964 SET_IA32_ORIG_NODE(new_node, node);
966 /* lowered shift instruction may have a dependency operand, handle it here */
967 if (get_irn_arity(node) == 3) {
968 /* we have a dependency */
969 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
970 add_irn_dep(new_node, new_dep);
978 * Construct a standard unary operation, set AM and immediate if required.
980 * @param op The operand
981 * @param func The node constructor function
982 * @return The constructed ia32 node.
984 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
988 ir_node *block, *new_block, *new_op, *new_node;
990 assert(flags == 0 || flags == match_mode_neutral);
991 if (flags & match_mode_neutral) {
992 op = ia32_skip_downconv(op);
995 new_op = be_transform_node(op);
996 dbgi = get_irn_dbg_info(node);
997 block = get_nodes_block(node);
998 new_block = be_transform_node(block);
999 new_node = func(dbgi, new_block, new_op);
1001 SET_IA32_ORIG_NODE(new_node, node);
1006 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1007 ia32_address_t *addr)
1009 ir_node *base, *index, *res;
1013 base = ia32_new_NoReg_gp(env_cg);
1015 base = be_transform_node(base);
1018 index = addr->index;
1019 if (index == NULL) {
1020 index = ia32_new_NoReg_gp(env_cg);
1022 index = be_transform_node(index);
1025 res = new_bd_ia32_Lea(dbgi, block, base, index);
1026 set_address(res, addr);
1032 * Returns non-zero if a given address mode has a symbolic or
1033 * numerical offset != 0.
1035 static int am_has_immediates(const ia32_address_t *addr)
1037 return addr->offset != 0 || addr->symconst_ent != NULL
1038 || addr->frame_entity || addr->use_frame;
1042 * Creates an ia32 Add.
1044 * @return the created ia32 Add node
1046 static ir_node *gen_Add(ir_node *node)
1048 ir_mode *mode = get_irn_mode(node);
1049 ir_node *op1 = get_Add_left(node);
1050 ir_node *op2 = get_Add_right(node);
1052 ir_node *block, *new_block, *new_node, *add_immediate_op;
1053 ia32_address_t addr;
1054 ia32_address_mode_t am;
1056 if (mode_is_float(mode)) {
1057 if (ia32_cg_config.use_sse2)
1058 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1059 match_commutative | match_am);
1061 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1064 ia32_mark_non_am(node);
1066 op2 = ia32_skip_downconv(op2);
1067 op1 = ia32_skip_downconv(op1);
1071 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1072 * 1. Add with immediate -> Lea
1073 * 2. Add with possible source address mode -> Add
1074 * 3. Otherwise -> Lea
1076 memset(&addr, 0, sizeof(addr));
1077 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1078 add_immediate_op = NULL;
1080 dbgi = get_irn_dbg_info(node);
1081 block = get_nodes_block(node);
1082 new_block = be_transform_node(block);
1085 if (addr.base == NULL && addr.index == NULL) {
1086 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1087 addr.symconst_sign, addr.offset);
1088 be_dep_on_frame(new_node);
1089 SET_IA32_ORIG_NODE(new_node, node);
1092 /* add with immediate? */
1093 if (addr.index == NULL) {
1094 add_immediate_op = addr.base;
1095 } else if (addr.base == NULL && addr.scale == 0) {
1096 add_immediate_op = addr.index;
1099 if (add_immediate_op != NULL) {
1100 if (!am_has_immediates(&addr)) {
1101 #ifdef DEBUG_libfirm
1102 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1105 return be_transform_node(add_immediate_op);
1108 new_node = create_lea_from_address(dbgi, new_block, &addr);
1109 SET_IA32_ORIG_NODE(new_node, node);
1113 /* test if we can use source address mode */
1114 match_arguments(&am, block, op1, op2, NULL, match_commutative
1115 | match_mode_neutral | match_am | match_immediate | match_try_am);
1117 /* construct an Add with source address mode */
1118 if (am.op_type == ia32_AddrModeS) {
1119 ia32_address_t *am_addr = &am.addr;
1120 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1121 am_addr->index, am_addr->mem, am.new_op1,
1123 set_am_attributes(new_node, &am);
1124 SET_IA32_ORIG_NODE(new_node, node);
1126 new_node = fix_mem_proj(new_node, &am);
1131 /* otherwise construct a lea */
1132 new_node = create_lea_from_address(dbgi, new_block, &addr);
1133 SET_IA32_ORIG_NODE(new_node, node);
1138 * Creates an ia32 Mul.
1140 * @return the created ia32 Mul node
1142 static ir_node *gen_Mul(ir_node *node)
1144 ir_node *op1 = get_Mul_left(node);
1145 ir_node *op2 = get_Mul_right(node);
1146 ir_mode *mode = get_irn_mode(node);
1148 if (mode_is_float(mode)) {
1149 if (ia32_cg_config.use_sse2)
1150 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1151 match_commutative | match_am);
1153 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1155 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1156 match_commutative | match_am | match_mode_neutral |
1157 match_immediate | match_am_and_immediates);
1161 * Creates an ia32 Mulh.
1162 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1163 * this result while Mul returns the lower 32 bit.
1165 * @return the created ia32 Mulh node
1167 static ir_node *gen_Mulh(ir_node *node)
1169 ir_node *block = get_nodes_block(node);
1170 ir_node *new_block = be_transform_node(block);
1171 dbg_info *dbgi = get_irn_dbg_info(node);
1172 ir_node *op1 = get_Mulh_left(node);
1173 ir_node *op2 = get_Mulh_right(node);
1174 ir_mode *mode = get_irn_mode(node);
1176 ir_node *proj_res_high;
1178 if (mode_is_signed(mode)) {
1179 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1180 proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node,
1181 mode_Iu, pn_ia32_IMul1OP_res_high);
1183 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1184 proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node,
1185 mode_Iu, pn_ia32_Mul_res_high);
1187 return proj_res_high;
1191 * Creates an ia32 And.
1193 * @return The created ia32 And node
1195 static ir_node *gen_And(ir_node *node)
1197 ir_node *op1 = get_And_left(node);
1198 ir_node *op2 = get_And_right(node);
1199 assert(! mode_is_float(get_irn_mode(node)));
1201 /* is it a zero extension? */
1202 if (is_Const(op2)) {
1203 tarval *tv = get_Const_tarval(op2);
1204 long v = get_tarval_long(tv);
1206 if (v == 0xFF || v == 0xFFFF) {
1207 dbg_info *dbgi = get_irn_dbg_info(node);
1208 ir_node *block = get_nodes_block(node);
1215 assert(v == 0xFFFF);
1218 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1223 return gen_binop(node, op1, op2, new_bd_ia32_And,
1224 match_commutative | match_mode_neutral | match_am | match_immediate);
1230 * Creates an ia32 Or.
1232 * @return The created ia32 Or node
1234 static ir_node *gen_Or(ir_node *node)
1236 ir_node *op1 = get_Or_left(node);
1237 ir_node *op2 = get_Or_right(node);
1239 assert (! mode_is_float(get_irn_mode(node)));
1240 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1241 | match_mode_neutral | match_am | match_immediate);
1247 * Creates an ia32 Eor.
1249 * @return The created ia32 Eor node
1251 static ir_node *gen_Eor(ir_node *node)
1253 ir_node *op1 = get_Eor_left(node);
1254 ir_node *op2 = get_Eor_right(node);
1256 assert(! mode_is_float(get_irn_mode(node)));
1257 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1258 | match_mode_neutral | match_am | match_immediate);
1263 * Creates an ia32 Sub.
1265 * @return The created ia32 Sub node
1267 static ir_node *gen_Sub(ir_node *node)
1269 ir_node *op1 = get_Sub_left(node);
1270 ir_node *op2 = get_Sub_right(node);
1271 ir_mode *mode = get_irn_mode(node);
1273 if (mode_is_float(mode)) {
1274 if (ia32_cg_config.use_sse2)
1275 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1277 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1280 if (is_Const(op2)) {
1281 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1285 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1286 | match_am | match_immediate);
1289 static ir_node *transform_AM_mem(ir_graph *const irg, ir_node *const block,
1290 ir_node *const src_val,
1291 ir_node *const src_mem,
1292 ir_node *const am_mem)
1294 if (is_NoMem(am_mem)) {
1295 return be_transform_node(src_mem);
1296 } else if (is_Proj(src_val) &&
1298 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1299 /* avoid memory loop */
1301 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1302 ir_node *const ptr_pred = get_Proj_pred(src_val);
1303 int const arity = get_Sync_n_preds(src_mem);
1308 NEW_ARR_A(ir_node*, ins, arity + 1);
1310 /* NOTE: This sometimes produces dead-code because the old sync in
1311 * src_mem might not be used anymore, we should detect this case
1312 * and kill the sync... */
1313 for (i = arity - 1; i >= 0; --i) {
1314 ir_node *const pred = get_Sync_pred(src_mem, i);
1316 /* avoid memory loop */
1317 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1320 ins[n++] = be_transform_node(pred);
1325 return new_r_Sync(irg, block, n, ins);
1329 ins[0] = be_transform_node(src_mem);
1331 return new_r_Sync(irg, block, 2, ins);
1335 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1336 ir_node *val, const ir_node *orig)
1341 if (ia32_cg_config.use_short_sex_eax) {
1342 const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_gp];
1345 res = new_bd_ia32_Cltd(dbgi, block, val);
1348 be_new_Keep(reg_class, current_ir_graph, block, 2, in);
1350 ir_node *imm31 = create_Immediate(NULL, 0, 31);
1351 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1353 SET_IA32_ORIG_NODE(res, orig);
1358 * Generates an ia32 DivMod with additional infrastructure for the
1359 * register allocator if needed.
1361 static ir_node *create_Div(ir_node *node)
1363 dbg_info *dbgi = get_irn_dbg_info(node);
1364 ir_node *block = get_nodes_block(node);
1365 ir_node *new_block = be_transform_node(block);
1372 ir_node *sign_extension;
1373 ia32_address_mode_t am;
1374 ia32_address_t *addr = &am.addr;
1376 /* the upper bits have random contents for smaller modes */
1377 switch (get_irn_opcode(node)) {
1379 op1 = get_Div_left(node);
1380 op2 = get_Div_right(node);
1381 mem = get_Div_mem(node);
1382 mode = get_Div_resmode(node);
1385 op1 = get_Mod_left(node);
1386 op2 = get_Mod_right(node);
1387 mem = get_Mod_mem(node);
1388 mode = get_Mod_resmode(node);
1391 op1 = get_DivMod_left(node);
1392 op2 = get_DivMod_right(node);
1393 mem = get_DivMod_mem(node);
1394 mode = get_DivMod_resmode(node);
1397 panic("invalid divmod node %+F", node);
1400 match_arguments(&am, block, op1, op2, NULL, match_am);
1402 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1403 is the memory of the consumed address. We can have only the second op as address
1404 in Div nodes, so check only op2. */
1405 new_mem = transform_AM_mem(current_ir_graph, block, op2, mem, addr->mem);
1407 if (mode_is_signed(mode)) {
1408 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1409 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1410 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1412 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0);
1413 be_dep_on_frame(sign_extension);
1415 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1416 addr->index, new_mem, am.new_op2,
1417 am.new_op1, sign_extension);
1420 set_irn_pinned(new_node, get_irn_pinned(node));
1422 set_am_attributes(new_node, &am);
1423 SET_IA32_ORIG_NODE(new_node, node);
1425 new_node = fix_mem_proj(new_node, &am);
1431 static ir_node *gen_Mod(ir_node *node)
1433 return create_Div(node);
1436 static ir_node *gen_Div(ir_node *node)
1438 return create_Div(node);
1441 static ir_node *gen_DivMod(ir_node *node)
1443 return create_Div(node);
1449 * Creates an ia32 floating Div.
1451 * @return The created ia32 xDiv node
1453 static ir_node *gen_Quot(ir_node *node)
1455 ir_node *op1 = get_Quot_left(node);
1456 ir_node *op2 = get_Quot_right(node);
1458 if (ia32_cg_config.use_sse2) {
1459 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1461 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1467 * Creates an ia32 Shl.
1469 * @return The created ia32 Shl node
1471 static ir_node *gen_Shl(ir_node *node)
1473 ir_node *left = get_Shl_left(node);
1474 ir_node *right = get_Shl_right(node);
1476 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1477 match_mode_neutral | match_immediate);
1481 * Creates an ia32 Shr.
1483 * @return The created ia32 Shr node
1485 static ir_node *gen_Shr(ir_node *node)
1487 ir_node *left = get_Shr_left(node);
1488 ir_node *right = get_Shr_right(node);
1490 return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
1496 * Creates an ia32 Sar.
1498 * @return The created ia32 Shrs node
1500 static ir_node *gen_Shrs(ir_node *node)
1502 ir_node *left = get_Shrs_left(node);
1503 ir_node *right = get_Shrs_right(node);
1505 if (is_Const(right)) {
1506 tarval *tv = get_Const_tarval(right);
1507 long val = get_tarval_long(tv);
1509 /* this is a sign extension */
1510 dbg_info *dbgi = get_irn_dbg_info(node);
1511 ir_node *block = be_transform_node(get_nodes_block(node));
1512 ir_node *new_op = be_transform_node(left);
1514 return create_sex_32_64(dbgi, block, new_op, node);
1518 /* 8 or 16 bit sign extension? */
1519 if (is_Const(right) && is_Shl(left)) {
1520 ir_node *shl_left = get_Shl_left(left);
1521 ir_node *shl_right = get_Shl_right(left);
1522 if (is_Const(shl_right)) {
1523 tarval *tv1 = get_Const_tarval(right);
1524 tarval *tv2 = get_Const_tarval(shl_right);
1525 if (tv1 == tv2 && tarval_is_long(tv1)) {
1526 long val = get_tarval_long(tv1);
1527 if (val == 16 || val == 24) {
1528 dbg_info *dbgi = get_irn_dbg_info(node);
1529 ir_node *block = get_nodes_block(node);
1539 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1548 return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
1554 * Creates an ia32 Rol.
1556 * @param op1 The first operator
1557 * @param op2 The second operator
1558 * @return The created ia32 RotL node
1560 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1562 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1568 * Creates an ia32 Ror.
1569 * NOTE: There is no RotR with immediate because this would always be a RotL
1570 * "imm-mode_size_bits" which can be pre-calculated.
1572 * @param op1 The first operator
1573 * @param op2 The second operator
1574 * @return The created ia32 RotR node
1576 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1578 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1584 * Creates an ia32 RotR or RotL (depending on the found pattern).
1586 * @return The created ia32 RotL or RotR node
1588 static ir_node *gen_Rotl(ir_node *node)
1590 ir_node *rotate = NULL;
1591 ir_node *op1 = get_Rotl_left(node);
1592 ir_node *op2 = get_Rotl_right(node);
1594 /* Firm has only RotL, so we are looking for a right (op2)
1595 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1596 that means we can create a RotR instead of an Add and a RotL */
1600 ir_node *left = get_Add_left(add);
1601 ir_node *right = get_Add_right(add);
1602 if (is_Const(right)) {
1603 tarval *tv = get_Const_tarval(right);
1604 ir_mode *mode = get_irn_mode(node);
1605 long bits = get_mode_size_bits(mode);
1607 if (is_Minus(left) &&
1608 tarval_is_long(tv) &&
1609 get_tarval_long(tv) == bits &&
1612 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1613 rotate = gen_Ror(node, op1, get_Minus_op(left));
1618 if (rotate == NULL) {
1619 rotate = gen_Rol(node, op1, op2);
1628 * Transforms a Minus node.
1630 * @return The created ia32 Minus node
1632 static ir_node *gen_Minus(ir_node *node)
1634 ir_node *op = get_Minus_op(node);
1635 ir_node *block = be_transform_node(get_nodes_block(node));
1636 dbg_info *dbgi = get_irn_dbg_info(node);
1637 ir_mode *mode = get_irn_mode(node);
1642 if (mode_is_float(mode)) {
1643 ir_node *new_op = be_transform_node(op);
1644 if (ia32_cg_config.use_sse2) {
1645 /* TODO: non-optimal... if we have many xXors, then we should
1646 * rather create a load for the const and use that instead of
1647 * several AM nodes... */
1648 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1649 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1650 ir_node *nomem = new_NoMem();
1652 new_node = new_bd_ia32_xXor(dbgi, block, noreg_gp, noreg_gp,
1653 nomem, new_op, noreg_xmm);
1655 size = get_mode_size_bits(mode);
1656 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1658 set_ia32_am_sc(new_node, ent);
1659 set_ia32_op_type(new_node, ia32_AddrModeS);
1660 set_ia32_ls_mode(new_node, mode);
1662 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1665 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1668 SET_IA32_ORIG_NODE(new_node, node);
1674 * Transforms a Not node.
1676 * @return The created ia32 Not node
1678 static ir_node *gen_Not(ir_node *node)
1680 ir_node *op = get_Not_op(node);
1682 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1683 assert (! mode_is_float(get_irn_mode(node)));
1685 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1691 * Transforms an Abs node.
1693 * @return The created ia32 Abs node
1695 static ir_node *gen_Abs(ir_node *node)
1697 ir_node *block = get_nodes_block(node);
1698 ir_node *new_block = be_transform_node(block);
1699 ir_node *op = get_Abs_op(node);
1700 dbg_info *dbgi = get_irn_dbg_info(node);
1701 ir_mode *mode = get_irn_mode(node);
1702 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1703 ir_node *nomem = new_NoMem();
1709 if (mode_is_float(mode)) {
1710 new_op = be_transform_node(op);
1712 if (ia32_cg_config.use_sse2) {
1713 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1714 new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_gp, noreg_gp,
1715 nomem, new_op, noreg_fp);
1717 size = get_mode_size_bits(mode);
1718 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1720 set_ia32_am_sc(new_node, ent);
1722 SET_IA32_ORIG_NODE(new_node, node);
1724 set_ia32_op_type(new_node, ia32_AddrModeS);
1725 set_ia32_ls_mode(new_node, mode);
1727 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
1728 SET_IA32_ORIG_NODE(new_node, node);
1731 ir_node *xor, *sign_extension;
1733 if (get_mode_size_bits(mode) == 32) {
1734 new_op = be_transform_node(op);
1736 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1739 sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
1741 xor = new_bd_ia32_Xor(dbgi, new_block, noreg_gp, noreg_gp,
1742 nomem, new_op, sign_extension);
1743 SET_IA32_ORIG_NODE(xor, node);
1745 new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_gp, noreg_gp,
1746 nomem, xor, sign_extension);
1747 SET_IA32_ORIG_NODE(new_node, node);
1754 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1756 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
1758 dbg_info *dbgi = get_irn_dbg_info(cmp);
1759 ir_node *block = get_nodes_block(cmp);
1760 ir_node *new_block = be_transform_node(block);
1761 ir_node *op1 = be_transform_node(x);
1762 ir_node *op2 = be_transform_node(n);
1764 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
1768 * Transform a node returning a "flag" result.
1770 * @param node the node to transform
1771 * @param pnc_out the compare mode to use
1773 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1782 /* we have a Cmp as input */
1783 if (is_Proj(node)) {
1784 ir_node *pred = get_Proj_pred(node);
1786 pn_Cmp pnc = get_Proj_proj(node);
1787 if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
1788 ir_node *l = get_Cmp_left(pred);
1789 ir_node *r = get_Cmp_right(pred);
1791 ir_node *la = get_And_left(l);
1792 ir_node *ra = get_And_right(l);
1794 ir_node *c = get_Shl_left(la);
1795 if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
1796 /* (1 << n) & ra) */
1797 ir_node *n = get_Shl_right(la);
1798 flags = gen_bt(pred, ra, n);
1799 /* we must generate a Jc/Jnc jump */
1800 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1803 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1808 ir_node *c = get_Shl_left(ra);
1809 if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
1810 /* la & (1 << n)) */
1811 ir_node *n = get_Shl_right(ra);
1812 flags = gen_bt(pred, la, n);
1813 /* we must generate a Jc/Jnc jump */
1814 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1817 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1823 flags = be_transform_node(pred);
1829 /* a mode_b value, we have to compare it against 0 */
1830 dbgi = get_irn_dbg_info(node);
1831 new_block = be_transform_node(get_nodes_block(node));
1832 new_op = be_transform_node(node);
1833 noreg = ia32_new_NoReg_gp(env_cg);
1834 nomem = new_NoMem();
1835 flags = new_bd_ia32_Test(dbgi, new_block, noreg, noreg, nomem, new_op,
1836 new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
1837 *pnc_out = pn_Cmp_Lg;
1842 * Transforms a Load.
1844 * @return the created ia32 Load node
1846 static ir_node *gen_Load(ir_node *node)
1848 ir_node *old_block = get_nodes_block(node);
1849 ir_node *block = be_transform_node(old_block);
1850 ir_node *ptr = get_Load_ptr(node);
1851 ir_node *mem = get_Load_mem(node);
1852 ir_node *new_mem = be_transform_node(mem);
1855 dbg_info *dbgi = get_irn_dbg_info(node);
1856 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1857 ir_mode *mode = get_Load_mode(node);
1860 ia32_address_t addr;
1862 /* construct load address */
1863 memset(&addr, 0, sizeof(addr));
1864 ia32_create_address_mode(&addr, ptr, 0);
1871 base = be_transform_node(base);
1874 if (index == NULL) {
1877 index = be_transform_node(index);
1880 if (mode_is_float(mode)) {
1881 if (ia32_cg_config.use_sse2) {
1882 new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
1884 res_mode = mode_xmm;
1886 new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
1888 res_mode = mode_vfp;
1891 assert(mode != mode_b);
1893 /* create a conv node with address mode for smaller modes */
1894 if (get_mode_size_bits(mode) < 32) {
1895 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
1896 new_mem, noreg, mode);
1898 new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
1903 set_irn_pinned(new_node, get_irn_pinned(node));
1904 set_ia32_op_type(new_node, ia32_AddrModeS);
1905 set_ia32_ls_mode(new_node, mode);
1906 set_address(new_node, &addr);
1908 if (get_irn_pinned(node) == op_pin_state_floats) {
1909 assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
1910 && pn_ia32_vfld_res == pn_ia32_Load_res
1911 && pn_ia32_Load_res == pn_ia32_res);
1912 arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
1915 SET_IA32_ORIG_NODE(new_node, node);
1917 be_dep_on_frame(new_node);
1921 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1922 ir_node *ptr, ir_node *other)
1929 /* we only use address mode if we're the only user of the load */
1930 if (get_irn_n_edges(node) > 1)
1933 load = get_Proj_pred(node);
1936 if (get_nodes_block(load) != block)
1939 /* store should have the same pointer as the load */
1940 if (get_Load_ptr(load) != ptr)
1943 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1944 if (other != NULL &&
1945 get_nodes_block(other) == block &&
1946 heights_reachable_in_block(heights, other, load)) {
1950 if (prevents_AM(block, load, mem))
1952 /* Store should be attached to the load via mem */
1953 assert(heights_reachable_in_block(heights, mem, load));
1958 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1959 ir_node *mem, ir_node *ptr, ir_mode *mode,
1960 construct_binop_dest_func *func,
1961 construct_binop_dest_func *func8bit,
1962 match_flags_t flags)
1964 ir_node *src_block = get_nodes_block(node);
1966 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1973 ia32_address_mode_t am;
1974 ia32_address_t *addr = &am.addr;
1975 memset(&am, 0, sizeof(am));
1977 assert(flags & match_immediate); /* there is no destam node without... */
1978 commutative = (flags & match_commutative) != 0;
1980 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
1981 build_address(&am, op1, ia32_create_am_double_use);
1982 new_op = create_immediate_or_transform(op2, 0);
1983 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1984 build_address(&am, op2, ia32_create_am_double_use);
1985 new_op = create_immediate_or_transform(op1, 0);
1990 if (addr->base == NULL)
1991 addr->base = noreg_gp;
1992 if (addr->index == NULL)
1993 addr->index = noreg_gp;
1994 if (addr->mem == NULL)
1995 addr->mem = new_NoMem();
1997 dbgi = get_irn_dbg_info(node);
1998 block = be_transform_node(src_block);
1999 new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem);
2001 if (get_mode_size_bits(mode) == 8) {
2002 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2004 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2006 set_address(new_node, addr);
2007 set_ia32_op_type(new_node, ia32_AddrModeD);
2008 set_ia32_ls_mode(new_node, mode);
2009 SET_IA32_ORIG_NODE(new_node, node);
2011 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2012 mem_proj = be_transform_node(am.mem_proj);
2013 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2018 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2019 ir_node *ptr, ir_mode *mode,
2020 construct_unop_dest_func *func)
2022 ir_node *src_block = get_nodes_block(node);
2028 ia32_address_mode_t am;
2029 ia32_address_t *addr = &am.addr;
2031 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2034 memset(&am, 0, sizeof(am));
2035 build_address(&am, op, ia32_create_am_double_use);
2037 dbgi = get_irn_dbg_info(node);
2038 block = be_transform_node(src_block);
2039 new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem);
2040 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2041 set_address(new_node, addr);
2042 set_ia32_op_type(new_node, ia32_AddrModeD);
2043 set_ia32_ls_mode(new_node, mode);
2044 SET_IA32_ORIG_NODE(new_node, node);
2046 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2047 mem_proj = be_transform_node(am.mem_proj);
2048 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2053 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2055 ir_mode *mode = get_irn_mode(node);
2056 ir_node *mux_true = get_Mux_true(node);
2057 ir_node *mux_false = get_Mux_false(node);
2067 ia32_address_t addr;
2069 if (get_mode_size_bits(mode) != 8)
2072 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2074 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2080 build_address_ptr(&addr, ptr, mem);
2082 dbgi = get_irn_dbg_info(node);
2083 block = get_nodes_block(node);
2084 new_block = be_transform_node(block);
2085 cond = get_Mux_sel(node);
2086 flags = get_flags_node(cond, &pnc);
2087 new_mem = be_transform_node(mem);
2088 new_node = new_bd_ia32_SetMem(dbgi, new_block, addr.base,
2089 addr.index, addr.mem, flags, pnc, negated);
2090 set_address(new_node, &addr);
2091 set_ia32_op_type(new_node, ia32_AddrModeD);
2092 set_ia32_ls_mode(new_node, mode);
2093 SET_IA32_ORIG_NODE(new_node, node);
2098 static ir_node *try_create_dest_am(ir_node *node)
2100 ir_node *val = get_Store_value(node);
2101 ir_node *mem = get_Store_mem(node);
2102 ir_node *ptr = get_Store_ptr(node);
2103 ir_mode *mode = get_irn_mode(val);
2104 unsigned bits = get_mode_size_bits(mode);
2109 /* handle only GP modes for now... */
2110 if (!ia32_mode_needs_gp_reg(mode))
2114 /* store must be the only user of the val node */
2115 if (get_irn_n_edges(val) > 1)
2117 /* skip pointless convs */
2119 ir_node *conv_op = get_Conv_op(val);
2120 ir_mode *pred_mode = get_irn_mode(conv_op);
2121 if (!ia32_mode_needs_gp_reg(pred_mode))
2123 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2131 /* value must be in the same block */
2132 if (get_nodes_block(node) != get_nodes_block(val))
2135 switch (get_irn_opcode(val)) {
2137 op1 = get_Add_left(val);
2138 op2 = get_Add_right(val);
2139 if (ia32_cg_config.use_incdec) {
2140 if (is_Const_1(op2)) {
2141 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2143 } else if (is_Const_Minus_1(op2)) {
2144 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2148 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2149 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2150 match_commutative | match_immediate);
2153 op1 = get_Sub_left(val);
2154 op2 = get_Sub_right(val);
2155 if (is_Const(op2)) {
2156 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2158 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2159 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2163 op1 = get_And_left(val);
2164 op2 = get_And_right(val);
2165 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2166 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2167 match_commutative | match_immediate);
2170 op1 = get_Or_left(val);
2171 op2 = get_Or_right(val);
2172 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2173 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2174 match_commutative | match_immediate);
2177 op1 = get_Eor_left(val);
2178 op2 = get_Eor_right(val);
2179 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2180 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2181 match_commutative | match_immediate);
2184 op1 = get_Shl_left(val);
2185 op2 = get_Shl_right(val);
2186 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2187 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2191 op1 = get_Shr_left(val);
2192 op2 = get_Shr_right(val);
2193 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2194 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2198 op1 = get_Shrs_left(val);
2199 op2 = get_Shrs_right(val);
2200 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2201 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2205 op1 = get_Rotl_left(val);
2206 op2 = get_Rotl_right(val);
2207 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2208 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2211 /* TODO: match ROR patterns... */
2213 new_node = try_create_SetMem(val, ptr, mem);
2216 op1 = get_Minus_op(val);
2217 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2220 /* should be lowered already */
2221 assert(mode != mode_b);
2222 op1 = get_Not_op(val);
2223 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2229 if (new_node != NULL) {
2230 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2231 get_irn_pinned(node) == op_pin_state_pinned) {
2232 set_irn_pinned(new_node, op_pin_state_pinned);
2239 static bool possible_int_mode_for_fp(ir_mode *mode)
2243 if (!mode_is_signed(mode))
2245 size = get_mode_size_bits(mode);
2246 if (size != 16 && size != 32)
2251 static int is_float_to_int_conv(const ir_node *node)
2253 ir_mode *mode = get_irn_mode(node);
2257 if (!possible_int_mode_for_fp(mode))
2262 conv_op = get_Conv_op(node);
2263 conv_mode = get_irn_mode(conv_op);
2265 if (!mode_is_float(conv_mode))
2272 * Transform a Store(floatConst) into a sequence of
2275 * @return the created ia32 Store node
2277 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2279 ir_mode *mode = get_irn_mode(cns);
2280 unsigned size = get_mode_size_bytes(mode);
2281 tarval *tv = get_Const_tarval(cns);
2282 ir_node *block = get_nodes_block(node);
2283 ir_node *new_block = be_transform_node(block);
2284 ir_node *ptr = get_Store_ptr(node);
2285 ir_node *mem = get_Store_mem(node);
2286 dbg_info *dbgi = get_irn_dbg_info(node);
2290 ia32_address_t addr;
2292 assert(size % 4 == 0);
2295 build_address_ptr(&addr, ptr, mem);
2299 get_tarval_sub_bits(tv, ofs) |
2300 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2301 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2302 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2303 ir_node *imm = create_Immediate(NULL, 0, val);
2305 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2306 addr.index, addr.mem, imm);
2308 set_irn_pinned(new_node, get_irn_pinned(node));
2309 set_ia32_op_type(new_node, ia32_AddrModeD);
2310 set_ia32_ls_mode(new_node, mode_Iu);
2311 set_address(new_node, &addr);
2312 SET_IA32_ORIG_NODE(new_node, node);
2315 ins[i++] = new_node;
2320 } while (size != 0);
2323 return new_rd_Sync(dbgi, current_ir_graph, new_block, i, ins);
2330 * Generate a vfist or vfisttp instruction.
2332 static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index,
2333 ir_node *mem, ir_node *val, ir_node **fist)
2337 if (ia32_cg_config.use_fisttp) {
2338 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2339 if other users exists */
2340 const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
2341 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2342 ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res);
2343 be_new_Keep(reg_class, irg, block, 1, &value);
2345 new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M);
2348 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2351 new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2357 * Transforms a general (no special case) Store.
2359 * @return the created ia32 Store node
2361 static ir_node *gen_general_Store(ir_node *node)
2363 ir_node *val = get_Store_value(node);
2364 ir_mode *mode = get_irn_mode(val);
2365 ir_node *block = get_nodes_block(node);
2366 ir_node *new_block = be_transform_node(block);
2367 ir_node *ptr = get_Store_ptr(node);
2368 ir_node *mem = get_Store_mem(node);
2369 dbg_info *dbgi = get_irn_dbg_info(node);
2370 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2371 ir_node *new_val, *new_node, *store;
2372 ia32_address_t addr;
2374 /* check for destination address mode */
2375 new_node = try_create_dest_am(node);
2376 if (new_node != NULL)
2379 /* construct store address */
2380 memset(&addr, 0, sizeof(addr));
2381 ia32_create_address_mode(&addr, ptr, 0);
2383 if (addr.base == NULL) {
2386 addr.base = be_transform_node(addr.base);
2389 if (addr.index == NULL) {
2392 addr.index = be_transform_node(addr.index);
2394 addr.mem = be_transform_node(mem);
2396 if (mode_is_float(mode)) {
2397 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2399 while (is_Conv(val) && mode == get_irn_mode(val)) {
2400 ir_node *op = get_Conv_op(val);
2401 if (!mode_is_float(get_irn_mode(op)))
2405 new_val = be_transform_node(val);
2406 if (ia32_cg_config.use_sse2) {
2407 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2408 addr.index, addr.mem, new_val);
2410 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2411 addr.index, addr.mem, new_val, mode);
2414 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2415 val = get_Conv_op(val);
2417 /* TODO: is this optimisation still necessary at all (middleend)? */
2418 /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
2419 while (is_Conv(val)) {
2420 ir_node *op = get_Conv_op(val);
2421 if (!mode_is_float(get_irn_mode(op)))
2423 if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
2427 new_val = be_transform_node(val);
2428 new_node = gen_vfist(dbgi, current_ir_graph, new_block, addr.base, addr.index, addr.mem, new_val, &store);
2430 new_val = create_immediate_or_transform(val, 0);
2431 assert(mode != mode_b);
2433 if (get_mode_size_bits(mode) == 8) {
2434 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2435 addr.index, addr.mem, new_val);
2437 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2438 addr.index, addr.mem, new_val);
2443 set_irn_pinned(store, get_irn_pinned(node));
2444 set_ia32_op_type(store, ia32_AddrModeD);
2445 set_ia32_ls_mode(store, mode);
2447 set_address(store, &addr);
2448 SET_IA32_ORIG_NODE(store, node);
2454 * Transforms a Store.
2456 * @return the created ia32 Store node
2458 static ir_node *gen_Store(ir_node *node)
2460 ir_node *val = get_Store_value(node);
2461 ir_mode *mode = get_irn_mode(val);
2463 if (mode_is_float(mode) && is_Const(val)) {
2464 /* We can transform every floating const store
2465 into a sequence of integer stores.
2466 If the constant is already in a register,
2467 it would be better to use it, but we don't
2468 have this information here. */
2469 return gen_float_const_Store(node, val);
2471 return gen_general_Store(node);
2475 * Transforms a Switch.
2477 * @return the created ia32 SwitchJmp node
2479 static ir_node *create_Switch(ir_node *node)
2481 dbg_info *dbgi = get_irn_dbg_info(node);
2482 ir_node *block = be_transform_node(get_nodes_block(node));
2483 ir_node *sel = get_Cond_selector(node);
2484 ir_node *new_sel = be_transform_node(sel);
2485 int switch_min = INT_MAX;
2486 int switch_max = INT_MIN;
2487 long default_pn = get_Cond_defaultProj(node);
2489 const ir_edge_t *edge;
2491 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2493 /* determine the smallest switch case value */
2494 foreach_out_edge(node, edge) {
2495 ir_node *proj = get_edge_src_irn(edge);
2496 long pn = get_Proj_proj(proj);
2497 if (pn == default_pn)
2500 if (pn < switch_min)
2502 if (pn > switch_max)
2506 if ((unsigned) (switch_max - switch_min) > 256000) {
2507 panic("Size of switch %+F bigger than 256000", node);
2510 if (switch_min != 0) {
2511 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2513 /* if smallest switch case is not 0 we need an additional sub */
2514 new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg);
2515 add_ia32_am_offs_int(new_sel, -switch_min);
2516 set_ia32_op_type(new_sel, ia32_AddrModeS);
2518 SET_IA32_ORIG_NODE(new_sel, node);
2521 new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
2522 SET_IA32_ORIG_NODE(new_node, node);
2528 * Transform a Cond node.
2530 static ir_node *gen_Cond(ir_node *node)
2532 ir_node *block = get_nodes_block(node);
2533 ir_node *new_block = be_transform_node(block);
2534 dbg_info *dbgi = get_irn_dbg_info(node);
2535 ir_node *sel = get_Cond_selector(node);
2536 ir_mode *sel_mode = get_irn_mode(sel);
2537 ir_node *flags = NULL;
2541 if (sel_mode != mode_b) {
2542 return create_Switch(node);
2545 /* we get flags from a Cmp */
2546 flags = get_flags_node(sel, &pnc);
2548 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc);
2549 SET_IA32_ORIG_NODE(new_node, node);
2554 static ir_node *gen_be_Copy(ir_node *node)
2556 ir_node *new_node = be_duplicate_node(node);
2557 ir_mode *mode = get_irn_mode(new_node);
2559 if (ia32_mode_needs_gp_reg(mode)) {
2560 set_irn_mode(new_node, mode_Iu);
2566 static ir_node *create_Fucom(ir_node *node)
2568 dbg_info *dbgi = get_irn_dbg_info(node);
2569 ir_node *block = get_nodes_block(node);
2570 ir_node *new_block = be_transform_node(block);
2571 ir_node *left = get_Cmp_left(node);
2572 ir_node *new_left = be_transform_node(left);
2573 ir_node *right = get_Cmp_right(node);
2577 if (ia32_cg_config.use_fucomi) {
2578 new_right = be_transform_node(right);
2579 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2581 set_ia32_commutative(new_node);
2582 SET_IA32_ORIG_NODE(new_node, node);
2584 if (ia32_cg_config.use_ftst && is_Const_0(right)) {
2585 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2587 new_right = be_transform_node(right);
2588 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2591 set_ia32_commutative(new_node);
2593 SET_IA32_ORIG_NODE(new_node, node);
2595 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2596 SET_IA32_ORIG_NODE(new_node, node);
2602 static ir_node *create_Ucomi(ir_node *node)
2604 dbg_info *dbgi = get_irn_dbg_info(node);
2605 ir_node *src_block = get_nodes_block(node);
2606 ir_node *new_block = be_transform_node(src_block);
2607 ir_node *left = get_Cmp_left(node);
2608 ir_node *right = get_Cmp_right(node);
2610 ia32_address_mode_t am;
2611 ia32_address_t *addr = &am.addr;
2613 match_arguments(&am, src_block, left, right, NULL,
2614 match_commutative | match_am);
2616 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2617 addr->mem, am.new_op1, am.new_op2,
2619 set_am_attributes(new_node, &am);
2621 SET_IA32_ORIG_NODE(new_node, node);
2623 new_node = fix_mem_proj(new_node, &am);
2629 * helper function: checks whether all Cmp projs are Lg or Eq which is needed
2630 * to fold an and into a test node
2632 static bool can_fold_test_and(ir_node *node)
2634 const ir_edge_t *edge;
2636 /** we can only have eq and lg projs */
2637 foreach_out_edge(node, edge) {
2638 ir_node *proj = get_edge_src_irn(edge);
2639 pn_Cmp pnc = get_Proj_proj(proj);
2640 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2648 * returns true if it is assured, that the upper bits of a node are "clean"
2649 * which means for a 16 or 8 bit value, that the upper bits in the register
2650 * are 0 for unsigned and a copy of the last significant bit for signed
2653 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
2655 assert(ia32_mode_needs_gp_reg(mode));
2656 if (get_mode_size_bits(mode) >= 32)
2659 if (is_Proj(transformed_node))
2660 return upper_bits_clean(get_Proj_pred(transformed_node), mode);
2662 switch (get_ia32_irn_opcode(transformed_node)) {
2663 case iro_ia32_Conv_I2I:
2664 case iro_ia32_Conv_I2I8Bit: {
2665 ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
2666 if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
2668 if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
2675 if (mode_is_signed(mode)) {
2676 return false; /* TODO handle signed modes */
2678 ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
2679 if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
2680 const ia32_immediate_attr_t *attr
2681 = get_ia32_immediate_attr_const(right);
2682 if (attr->symconst == 0 &&
2683 (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
2687 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
2691 /* TODO too conservative if shift amount is constant */
2692 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
2695 if (!mode_is_signed(mode)) {
2697 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
2698 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
2700 /* TODO if one is known to be zero extended, then || is sufficient */
2705 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
2706 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
2708 case iro_ia32_Const:
2709 case iro_ia32_Immediate: {
2710 const ia32_immediate_attr_t *attr =
2711 get_ia32_immediate_attr_const(transformed_node);
2712 if (mode_is_signed(mode)) {
2713 long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
2714 return shifted == 0 || shifted == -1;
2716 unsigned long shifted = (unsigned long)attr->offset;
2717 shifted >>= get_mode_size_bits(mode);
2718 return shifted == 0;
2728 * Generate code for a Cmp.
2730 static ir_node *gen_Cmp(ir_node *node)
2732 dbg_info *dbgi = get_irn_dbg_info(node);
2733 ir_node *block = get_nodes_block(node);
2734 ir_node *new_block = be_transform_node(block);
2735 ir_node *left = get_Cmp_left(node);
2736 ir_node *right = get_Cmp_right(node);
2737 ir_mode *cmp_mode = get_irn_mode(left);
2739 ia32_address_mode_t am;
2740 ia32_address_t *addr = &am.addr;
2743 if (mode_is_float(cmp_mode)) {
2744 if (ia32_cg_config.use_sse2) {
2745 return create_Ucomi(node);
2747 return create_Fucom(node);
2751 assert(ia32_mode_needs_gp_reg(cmp_mode));
2753 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
2754 cmp_unsigned = !mode_is_signed(cmp_mode);
2755 if (is_Const_0(right) &&
2757 get_irn_n_edges(left) == 1 &&
2758 can_fold_test_and(node)) {
2759 /* Test(and_left, and_right) */
2760 ir_node *and_left = get_And_left(left);
2761 ir_node *and_right = get_And_right(left);
2763 /* matze: code here used mode instead of cmd_mode, I think it is always
2764 * the same as cmp_mode, but I leave this here to see if this is really
2767 assert(get_irn_mode(and_left) == cmp_mode);
2769 match_arguments(&am, block, and_left, and_right, NULL,
2771 match_am | match_8bit_am | match_16bit_am |
2772 match_am_and_immediates | match_immediate);
2774 /* use 32bit compare mode if possible since the opcode is smaller */
2775 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2776 upper_bits_clean(am.new_op2, cmp_mode)) {
2777 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2780 if (get_mode_size_bits(cmp_mode) == 8) {
2781 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
2782 addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted,
2785 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
2786 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2789 /* Cmp(left, right) */
2790 match_arguments(&am, block, left, right, NULL,
2791 match_commutative | match_am | match_8bit_am |
2792 match_16bit_am | match_am_and_immediates |
2794 /* use 32bit compare mode if possible since the opcode is smaller */
2795 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2796 upper_bits_clean(am.new_op2, cmp_mode)) {
2797 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2800 if (get_mode_size_bits(cmp_mode) == 8) {
2801 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
2802 addr->index, addr->mem, am.new_op1,
2803 am.new_op2, am.ins_permuted,
2806 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
2807 addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
2810 set_am_attributes(new_node, &am);
2811 set_ia32_ls_mode(new_node, cmp_mode);
2813 SET_IA32_ORIG_NODE(new_node, node);
2815 new_node = fix_mem_proj(new_node, &am);
2820 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2823 dbg_info *dbgi = get_irn_dbg_info(node);
2824 ir_node *block = get_nodes_block(node);
2825 ir_node *new_block = be_transform_node(block);
2826 ir_node *val_true = get_Mux_true(node);
2827 ir_node *val_false = get_Mux_false(node);
2829 ia32_address_mode_t am;
2830 ia32_address_t *addr;
2832 assert(ia32_cg_config.use_cmov);
2833 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
2837 match_arguments(&am, block, val_false, val_true, flags,
2838 match_commutative | match_am | match_16bit_am | match_mode_neutral);
2840 new_node = new_bd_ia32_CMov(dbgi, new_block, addr->base, addr->index,
2841 addr->mem, am.new_op1, am.new_op2, new_flags,
2842 am.ins_permuted, pnc);
2843 set_am_attributes(new_node, &am);
2845 SET_IA32_ORIG_NODE(new_node, node);
2847 new_node = fix_mem_proj(new_node, &am);
2853 * Creates a ia32 Setcc instruction.
2855 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2856 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2859 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2860 ir_node *nomem = new_NoMem();
2861 ir_mode *mode = get_irn_mode(orig_node);
2864 new_node = new_bd_ia32_Set(dbgi, new_block, flags, pnc, ins_permuted);
2865 SET_IA32_ORIG_NODE(new_node, orig_node);
2867 /* we might need to conv the result up */
2868 if (get_mode_size_bits(mode) > 8) {
2869 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg, noreg,
2870 nomem, new_node, mode_Bu);
2871 SET_IA32_ORIG_NODE(new_node, orig_node);
2878 * Create instruction for an unsigned Difference or Zero.
2880 static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b)
2882 ir_graph *irg = current_ir_graph;
2883 ir_mode *mode = get_irn_mode(psi);
2884 ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *nomem;
2887 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
2888 match_mode_neutral | match_am | match_immediate | match_two_users);
2890 block = get_nodes_block(new_node);
2892 if (is_Proj(new_node)) {
2893 sub = get_Proj_pred(new_node);
2894 assert(is_ia32_Sub(sub));
2897 set_irn_mode(sub, mode_T);
2898 new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res);
2900 eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
2902 dbgi = get_irn_dbg_info(psi);
2903 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
2905 noreg = ia32_new_NoReg_gp(env_cg);
2906 new_node = new_bd_ia32_And(dbgi, block, noreg, noreg, nomem, new_node, sbb);
2907 set_ia32_commutative(new_node);
2912 * Transforms a Mux node into CMov.
2914 * @return The transformed node.
2916 static ir_node *gen_Mux(ir_node *node)
2918 dbg_info *dbgi = get_irn_dbg_info(node);
2919 ir_node *block = get_nodes_block(node);
2920 ir_node *new_block = be_transform_node(block);
2921 ir_node *mux_true = get_Mux_true(node);
2922 ir_node *mux_false = get_Mux_false(node);
2923 ir_node *cond = get_Mux_sel(node);
2924 ir_mode *mode = get_irn_mode(node);
2927 assert(get_irn_mode(cond) == mode_b);
2929 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
2930 if (mode_is_float(mode)) {
2931 ir_node *cmp = get_Proj_pred(cond);
2932 ir_node *cmp_left = get_Cmp_left(cmp);
2933 ir_node *cmp_right = get_Cmp_right(cmp);
2934 pn_Cmp pnc = get_Proj_proj(cond);
2936 if (ia32_cg_config.use_sse2) {
2937 if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
2938 if (cmp_left == mux_true && cmp_right == mux_false) {
2939 /* Mux(a <= b, a, b) => MIN */
2940 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
2941 match_commutative | match_am | match_two_users);
2942 } else if (cmp_left == mux_false && cmp_right == mux_true) {
2943 /* Mux(a <= b, b, a) => MAX */
2944 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
2945 match_commutative | match_am | match_two_users);
2947 } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
2948 if (cmp_left == mux_true && cmp_right == mux_false) {
2949 /* Mux(a >= b, a, b) => MAX */
2950 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
2951 match_commutative | match_am | match_two_users);
2952 } else if (cmp_left == mux_false && cmp_right == mux_true) {
2953 /* Mux(a >= b, b, a) => MIN */
2954 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
2955 match_commutative | match_am | match_two_users);
2959 panic("cannot transform floating point Mux");
2965 assert(ia32_mode_needs_gp_reg(mode));
2967 if (is_Proj(cond)) {
2968 ir_node *cmp = get_Proj_pred(cond);
2970 ir_node *cmp_left = get_Cmp_left(cmp);
2971 ir_node *cmp_right = get_Cmp_right(cmp);
2972 pn_Cmp pnc = get_Proj_proj(cond);
2974 /* check for unsigned Doz first */
2975 if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
2976 is_Const_0(mux_false) && is_Sub(mux_true) &&
2977 get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) {
2978 /* Mux(a >=u b, a - b, 0) unsigned Doz */
2979 return create_Doz(node, cmp_left, cmp_right);
2980 } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
2981 is_Const_0(mux_true) && is_Sub(mux_false) &&
2982 get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) {
2983 /* Mux(a <=u b, 0, a - b) unsigned Doz */
2984 return create_Doz(node, cmp_left, cmp_right);
2989 flags = get_flags_node(cond, &pnc);
2991 if (is_Const(mux_true) && is_Const(mux_false)) {
2992 /* both are const, good */
2993 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2994 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
2995 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2996 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1);
2998 /* Not that simple. */
3003 new_node = create_CMov(node, cond, flags, pnc);
3011 * Create a conversion from x87 state register to general purpose.
3013 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3015 ir_node *block = be_transform_node(get_nodes_block(node));
3016 ir_node *op = get_Conv_op(node);
3017 ir_node *new_op = be_transform_node(op);
3018 ia32_code_gen_t *cg = env_cg;
3019 ir_graph *irg = current_ir_graph;
3020 dbg_info *dbgi = get_irn_dbg_info(node);
3021 ir_node *noreg = ia32_new_NoReg_gp(cg);
3022 ir_mode *mode = get_irn_mode(node);
3023 ir_node *fist, *load, *mem;
3025 mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist);
3026 set_irn_pinned(fist, op_pin_state_floats);
3027 set_ia32_use_frame(fist);
3028 set_ia32_op_type(fist, ia32_AddrModeD);
3030 assert(get_mode_size_bits(mode) <= 32);
3031 /* exception we can only store signed 32 bit integers, so for unsigned
3032 we store a 64bit (signed) integer and load the lower bits */
3033 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3034 set_ia32_ls_mode(fist, mode_Ls);
3036 set_ia32_ls_mode(fist, mode_Is);
3038 SET_IA32_ORIG_NODE(fist, node);
3041 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg, mem);
3043 set_irn_pinned(load, op_pin_state_floats);
3044 set_ia32_use_frame(load);
3045 set_ia32_op_type(load, ia32_AddrModeS);
3046 set_ia32_ls_mode(load, mode_Is);
3047 if (get_ia32_ls_mode(fist) == mode_Ls) {
3048 ia32_attr_t *attr = get_ia32_attr(load);
3049 attr->data.need_64bit_stackent = 1;
3051 ia32_attr_t *attr = get_ia32_attr(load);
3052 attr->data.need_32bit_stackent = 1;
3054 SET_IA32_ORIG_NODE(load, node);
3056 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
3060 * Creates a x87 strict Conv by placing a Store and a Load
3062 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3064 ir_node *block = get_nodes_block(node);
3065 ir_graph *irg = current_ir_graph;
3066 dbg_info *dbgi = get_irn_dbg_info(node);
3067 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3068 ir_node *nomem = new_NoMem();
3069 ir_node *frame = get_irg_frame(irg);
3070 ir_node *store, *load;
3073 store = new_bd_ia32_vfst(dbgi, block, frame, noreg, nomem, node, tgt_mode);
3074 set_ia32_use_frame(store);
3075 set_ia32_op_type(store, ia32_AddrModeD);
3076 SET_IA32_ORIG_NODE(store, node);
3078 load = new_bd_ia32_vfld(dbgi, block, frame, noreg, store, tgt_mode);
3079 set_ia32_use_frame(load);
3080 set_ia32_op_type(load, ia32_AddrModeS);
3081 SET_IA32_ORIG_NODE(load, node);
3083 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
3087 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3088 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3090 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3092 func = get_mode_size_bits(mode) == 8 ?
3093 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3094 return func(dbgi, block, base, index, mem, val, mode);
3098 * Create a conversion from general purpose to x87 register
3100 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3102 ir_node *src_block = get_nodes_block(node);
3103 ir_node *block = be_transform_node(src_block);
3104 ir_graph *irg = current_ir_graph;
3105 dbg_info *dbgi = get_irn_dbg_info(node);
3106 ir_node *op = get_Conv_op(node);
3107 ir_node *new_op = NULL;
3111 ir_mode *store_mode;
3116 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3117 if (possible_int_mode_for_fp(src_mode)) {
3118 ia32_address_mode_t am;
3120 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
3121 if (am.op_type == ia32_AddrModeS) {
3122 ia32_address_t *addr = &am.addr;
3124 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index,
3126 new_node = new_r_Proj(irg, block, fild, mode_vfp,
3129 set_am_attributes(fild, &am);
3130 SET_IA32_ORIG_NODE(fild, node);
3132 fix_mem_proj(fild, &am);
3137 if (new_op == NULL) {
3138 new_op = be_transform_node(op);
3141 noreg = ia32_new_NoReg_gp(env_cg);
3142 nomem = new_NoMem();
3143 mode = get_irn_mode(op);
3145 /* first convert to 32 bit signed if necessary */
3146 if (get_mode_size_bits(src_mode) < 32) {
3147 if (!upper_bits_clean(new_op, src_mode)) {
3148 new_op = create_Conv_I2I(dbgi, block, noreg, noreg, nomem, new_op, src_mode);
3149 SET_IA32_ORIG_NODE(new_op, node);
3154 assert(get_mode_size_bits(mode) == 32);
3157 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg, nomem,
3160 set_ia32_use_frame(store);
3161 set_ia32_op_type(store, ia32_AddrModeD);
3162 set_ia32_ls_mode(store, mode_Iu);
3164 /* exception for 32bit unsigned, do a 64bit spill+load */
3165 if (!mode_is_signed(mode)) {
3168 ir_node *zero_const = create_Immediate(NULL, 0, 0);
3170 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3171 noreg, nomem, zero_const);
3173 set_ia32_use_frame(zero_store);
3174 set_ia32_op_type(zero_store, ia32_AddrModeD);
3175 add_ia32_am_offs_int(zero_store, 4);
3176 set_ia32_ls_mode(zero_store, mode_Iu);
3181 store = new_rd_Sync(dbgi, irg, block, 2, in);
3182 store_mode = mode_Ls;
3184 store_mode = mode_Is;
3188 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg, store);
3190 set_ia32_use_frame(fild);
3191 set_ia32_op_type(fild, ia32_AddrModeS);
3192 set_ia32_ls_mode(fild, store_mode);
3194 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
3200 * Create a conversion from one integer mode into another one
3202 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3203 dbg_info *dbgi, ir_node *block, ir_node *op,
3206 ir_node *new_block = be_transform_node(block);
3208 ir_mode *smaller_mode;
3209 ia32_address_mode_t am;
3210 ia32_address_t *addr = &am.addr;
3213 if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
3214 smaller_mode = src_mode;
3216 smaller_mode = tgt_mode;
3219 #ifdef DEBUG_libfirm
3221 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3226 match_arguments(&am, block, NULL, op, NULL,
3227 match_am | match_8bit_am | match_16bit_am);
3229 if (upper_bits_clean(am.new_op2, smaller_mode)) {
3230 /* unnecessary conv. in theory it shouldn't have been AM */
3231 assert(is_ia32_NoReg_GP(addr->base));
3232 assert(is_ia32_NoReg_GP(addr->index));
3233 assert(is_NoMem(addr->mem));
3234 assert(am.addr.offset == 0);
3235 assert(am.addr.symconst_ent == NULL);
3239 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3240 addr->mem, am.new_op2, smaller_mode);
3241 set_am_attributes(new_node, &am);
3242 /* match_arguments assume that out-mode = in-mode, this isn't true here
3244 set_ia32_ls_mode(new_node, smaller_mode);
3245 SET_IA32_ORIG_NODE(new_node, node);
3246 new_node = fix_mem_proj(new_node, &am);
3251 * Transforms a Conv node.
3253 * @return The created ia32 Conv node
3255 static ir_node *gen_Conv(ir_node *node)
3257 ir_node *block = get_nodes_block(node);
3258 ir_node *new_block = be_transform_node(block);
3259 ir_node *op = get_Conv_op(node);
3260 ir_node *new_op = NULL;
3261 dbg_info *dbgi = get_irn_dbg_info(node);
3262 ir_mode *src_mode = get_irn_mode(op);
3263 ir_mode *tgt_mode = get_irn_mode(node);
3264 int src_bits = get_mode_size_bits(src_mode);
3265 int tgt_bits = get_mode_size_bits(tgt_mode);
3266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3267 ir_node *nomem = new_NoMem();
3268 ir_node *res = NULL;
3270 assert(!mode_is_int(src_mode) || src_bits <= 32);
3271 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3273 if (src_mode == mode_b) {
3274 assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode));
3275 /* nothing to do, we already model bools as 0/1 ints */
3276 return be_transform_node(op);
3279 if (src_mode == tgt_mode) {
3280 if (get_Conv_strict(node)) {
3281 if (ia32_cg_config.use_sse2) {
3282 /* when we are in SSE mode, we can kill all strict no-op conversion */
3283 return be_transform_node(op);
3286 /* this should be optimized already, but who knows... */
3287 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3288 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3289 return be_transform_node(op);
3293 if (mode_is_float(src_mode)) {
3294 new_op = be_transform_node(op);
3295 /* we convert from float ... */
3296 if (mode_is_float(tgt_mode)) {
3297 if (src_mode == mode_E && tgt_mode == mode_D
3298 && !get_Conv_strict(node)) {
3299 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3304 if (ia32_cg_config.use_sse2) {
3305 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3306 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg, noreg,
3308 set_ia32_ls_mode(res, tgt_mode);
3310 if (get_Conv_strict(node)) {
3311 res = gen_x87_strict_conv(tgt_mode, new_op);
3312 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3315 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3320 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3321 if (ia32_cg_config.use_sse2) {
3322 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg, noreg,
3324 set_ia32_ls_mode(res, src_mode);
3326 return gen_x87_fp_to_gp(node);
3330 /* we convert from int ... */
3331 if (mode_is_float(tgt_mode)) {
3333 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3334 if (ia32_cg_config.use_sse2) {
3335 new_op = be_transform_node(op);
3336 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg, noreg,
3338 set_ia32_ls_mode(res, tgt_mode);
3340 res = gen_x87_gp_to_fp(node, src_mode);
3341 if (get_Conv_strict(node)) {
3342 /* The strict-Conv is only necessary, if the int mode has more bits
3343 * than the float mantissa */
3344 size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3345 size_t float_mantissa;
3346 /* FIXME There is no way to get the mantissa size of a mode */
3347 switch (get_mode_size_bits(tgt_mode)) {
3348 case 32: float_mantissa = 23 + 1; break; // + 1 for implicit 1
3349 case 64: float_mantissa = 52 + 1; break;
3351 case 96: float_mantissa = 64; break;
3352 default: float_mantissa = 0; break;
3354 if (float_mantissa < int_mantissa) {
3355 res = gen_x87_strict_conv(tgt_mode, res);
3356 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3361 } else if (tgt_mode == mode_b) {
3362 /* mode_b lowering already took care that we only have 0/1 values */
3363 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3364 src_mode, tgt_mode));
3365 return be_transform_node(op);
3368 if (src_bits == tgt_bits) {
3369 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3370 src_mode, tgt_mode));
3371 return be_transform_node(op);
3374 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3382 static ir_node *create_immediate_or_transform(ir_node *node,
3383 char immediate_constraint_type)
3385 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3386 if (new_node == NULL) {
3387 new_node = be_transform_node(node);
3393 * Transforms a FrameAddr into an ia32 Add.
3395 static ir_node *gen_be_FrameAddr(ir_node *node)
3397 ir_node *block = be_transform_node(get_nodes_block(node));
3398 ir_node *op = be_get_FrameAddr_frame(node);
3399 ir_node *new_op = be_transform_node(op);
3400 dbg_info *dbgi = get_irn_dbg_info(node);
3401 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3404 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg);
3405 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3406 set_ia32_use_frame(new_node);
3408 SET_IA32_ORIG_NODE(new_node, node);
3414 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3416 static ir_node *gen_be_Return(ir_node *node)
3418 ir_graph *irg = current_ir_graph;
3419 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3420 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3421 ir_entity *ent = get_irg_entity(irg);
3422 ir_type *tp = get_entity_type(ent);
3427 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3428 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3431 int pn_ret_val, pn_ret_mem, arity, i;
3433 assert(ret_val != NULL);
3434 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3435 return be_duplicate_node(node);
3438 res_type = get_method_res_type(tp, 0);
3440 if (! is_Primitive_type(res_type)) {
3441 return be_duplicate_node(node);
3444 mode = get_type_mode(res_type);
3445 if (! mode_is_float(mode)) {
3446 return be_duplicate_node(node);
3449 assert(get_method_n_ress(tp) == 1);
3451 pn_ret_val = get_Proj_proj(ret_val);
3452 pn_ret_mem = get_Proj_proj(ret_mem);
3454 /* get the Barrier */
3455 barrier = get_Proj_pred(ret_val);
3457 /* get result input of the Barrier */
3458 ret_val = get_irn_n(barrier, pn_ret_val);
3459 new_ret_val = be_transform_node(ret_val);
3461 /* get memory input of the Barrier */
3462 ret_mem = get_irn_n(barrier, pn_ret_mem);
3463 new_ret_mem = be_transform_node(ret_mem);
3465 frame = get_irg_frame(irg);
3467 dbgi = get_irn_dbg_info(barrier);
3468 block = be_transform_node(get_nodes_block(barrier));
3470 noreg = ia32_new_NoReg_gp(env_cg);
3472 /* store xmm0 onto stack */
3473 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg,
3474 new_ret_mem, new_ret_val);
3475 set_ia32_ls_mode(sse_store, mode);
3476 set_ia32_op_type(sse_store, ia32_AddrModeD);
3477 set_ia32_use_frame(sse_store);
3479 /* load into x87 register */
3480 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg, sse_store, mode);
3481 set_ia32_op_type(fld, ia32_AddrModeS);
3482 set_ia32_use_frame(fld);
3484 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3485 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3487 /* create a new barrier */
3488 arity = get_irn_arity(barrier);
3489 in = ALLOCAN(ir_node*, arity);
3490 for (i = 0; i < arity; ++i) {
3493 if (i == pn_ret_val) {
3495 } else if (i == pn_ret_mem) {
3498 ir_node *in = get_irn_n(barrier, i);
3499 new_in = be_transform_node(in);
3504 new_barrier = new_ir_node(dbgi, irg, block,
3505 get_irn_op(barrier), get_irn_mode(barrier),
3507 copy_node_attr(barrier, new_barrier);
3508 be_duplicate_deps(barrier, new_barrier);
3509 be_set_transformed_node(barrier, new_barrier);
3511 /* transform normally */
3512 return be_duplicate_node(node);
3516 * Transform a be_AddSP into an ia32_SubSP.
3518 static ir_node *gen_be_AddSP(ir_node *node)
3520 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3521 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3523 return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
3524 match_am | match_immediate);
3528 * Transform a be_SubSP into an ia32_AddSP
3530 static ir_node *gen_be_SubSP(ir_node *node)
3532 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3533 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3535 return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
3536 match_am | match_immediate);
3540 * Change some phi modes
3542 static ir_node *gen_Phi(ir_node *node)
3544 ir_node *block = be_transform_node(get_nodes_block(node));
3545 ir_graph *irg = current_ir_graph;
3546 dbg_info *dbgi = get_irn_dbg_info(node);
3547 ir_mode *mode = get_irn_mode(node);
3550 if (ia32_mode_needs_gp_reg(mode)) {
3551 /* we shouldn't have any 64bit stuff around anymore */
3552 assert(get_mode_size_bits(mode) <= 32);
3553 /* all integer operations are on 32bit registers now */
3555 } else if (mode_is_float(mode)) {
3556 if (ia32_cg_config.use_sse2) {
3563 /* phi nodes allow loops, so we use the old arguments for now
3564 * and fix this later */
3565 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3566 get_irn_in(node) + 1);
3567 copy_node_attr(node, phi);
3568 be_duplicate_deps(node, phi);
3570 be_enqueue_preds(node);
3578 static ir_node *gen_IJmp(ir_node *node)
3580 ir_node *block = get_nodes_block(node);
3581 ir_node *new_block = be_transform_node(block);
3582 dbg_info *dbgi = get_irn_dbg_info(node);
3583 ir_node *op = get_IJmp_target(node);
3585 ia32_address_mode_t am;
3586 ia32_address_t *addr = &am.addr;
3588 assert(get_irn_mode(op) == mode_P);
3590 match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
3592 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
3593 addr->mem, am.new_op2);
3594 set_am_attributes(new_node, &am);
3595 SET_IA32_ORIG_NODE(new_node, node);
3597 new_node = fix_mem_proj(new_node, &am);
3603 * Transform a Bound node.
3605 static ir_node *gen_Bound(ir_node *node)
3608 ir_node *lower = get_Bound_lower(node);
3609 dbg_info *dbgi = get_irn_dbg_info(node);
3611 if (is_Const_0(lower)) {
3612 /* typical case for Java */
3613 ir_node *sub, *res, *flags, *block;
3614 ir_graph *irg = current_ir_graph;
3616 res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
3617 new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
3619 block = get_nodes_block(res);
3620 if (! is_Proj(res)) {
3622 set_irn_mode(sub, mode_T);
3623 res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res);
3625 sub = get_Proj_pred(res);
3627 flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
3628 new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
3629 SET_IA32_ORIG_NODE(new_node, node);
3631 panic("generic Bound not supported in ia32 Backend");
3637 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3639 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3640 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3642 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
3643 match_immediate | match_mode_neutral);
3646 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3648 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
3649 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
3650 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
3654 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3656 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
3657 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
3658 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
3662 static ir_node *gen_ia32_l_Add(ir_node *node)
3664 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3665 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3666 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
3667 match_commutative | match_am | match_immediate |
3668 match_mode_neutral);
3670 if (is_Proj(lowered)) {
3671 lowered = get_Proj_pred(lowered);
3673 assert(is_ia32_Add(lowered));
3674 set_irn_mode(lowered, mode_T);
3680 static ir_node *gen_ia32_l_Adc(ir_node *node)
3682 return gen_binop_flags(node, new_bd_ia32_Adc,
3683 match_commutative | match_am | match_immediate |
3684 match_mode_neutral);
3688 * Transforms a l_MulS into a "real" MulS node.
3690 * @return the created ia32 Mul node
3692 static ir_node *gen_ia32_l_Mul(ir_node *node)
3694 ir_node *left = get_binop_left(node);
3695 ir_node *right = get_binop_right(node);
3697 return gen_binop(node, left, right, new_bd_ia32_Mul,
3698 match_commutative | match_am | match_mode_neutral);
3702 * Transforms a l_IMulS into a "real" IMul1OPS node.
3704 * @return the created ia32 IMul1OP node
3706 static ir_node *gen_ia32_l_IMul(ir_node *node)
3708 ir_node *left = get_binop_left(node);
3709 ir_node *right = get_binop_right(node);
3711 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
3712 match_commutative | match_am | match_mode_neutral);
3715 static ir_node *gen_ia32_l_Sub(ir_node *node)
3717 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
3718 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
3719 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
3720 match_am | match_immediate | match_mode_neutral);
3722 if (is_Proj(lowered)) {
3723 lowered = get_Proj_pred(lowered);
3725 assert(is_ia32_Sub(lowered));
3726 set_irn_mode(lowered, mode_T);
3732 static ir_node *gen_ia32_l_Sbb(ir_node *node)
3734 return gen_binop_flags(node, new_bd_ia32_Sbb,
3735 match_am | match_immediate | match_mode_neutral);
3739 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3740 * op1 - target to be shifted
3741 * op2 - contains bits to be shifted into target
3743 * Only op3 can be an immediate.
3745 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
3746 ir_node *low, ir_node *count)
3748 ir_node *block = get_nodes_block(node);
3749 ir_node *new_block = be_transform_node(block);
3750 dbg_info *dbgi = get_irn_dbg_info(node);
3751 ir_node *new_high = be_transform_node(high);
3752 ir_node *new_low = be_transform_node(low);
3756 /* the shift amount can be any mode that is bigger than 5 bits, since all
3757 * other bits are ignored anyway */
3758 while (is_Conv(count) &&
3759 get_irn_n_edges(count) == 1 &&
3760 mode_is_int(get_irn_mode(count))) {
3761 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
3762 count = get_Conv_op(count);
3764 new_count = create_immediate_or_transform(count, 0);
3766 if (is_ia32_l_ShlD(node)) {
3767 new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
3770 new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
3773 SET_IA32_ORIG_NODE(new_node, node);
3778 static ir_node *gen_ia32_l_ShlD(ir_node *node)
3780 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
3781 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
3782 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
3783 return gen_lowered_64bit_shifts(node, high, low, count);
3786 static ir_node *gen_ia32_l_ShrD(ir_node *node)
3788 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
3789 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
3790 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
3791 return gen_lowered_64bit_shifts(node, high, low, count);
3794 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
3796 ir_node *src_block = get_nodes_block(node);
3797 ir_node *block = be_transform_node(src_block);
3798 ir_graph *irg = current_ir_graph;
3799 dbg_info *dbgi = get_irn_dbg_info(node);
3800 ir_node *frame = get_irg_frame(irg);
3801 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3802 ir_node *nomem = new_NoMem();
3803 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
3804 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
3805 ir_node *new_val_low = be_transform_node(val_low);
3806 ir_node *new_val_high = be_transform_node(val_high);
3808 ir_node *sync, *fild, *res;
3809 ir_node *store_low, *store_high;
3811 if (ia32_cg_config.use_sse2) {
3812 panic("ia32_l_LLtoFloat not implemented for SSE2");
3816 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem,
3818 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem,
3820 SET_IA32_ORIG_NODE(store_low, node);
3821 SET_IA32_ORIG_NODE(store_high, node);
3823 set_ia32_use_frame(store_low);
3824 set_ia32_use_frame(store_high);
3825 set_ia32_op_type(store_low, ia32_AddrModeD);
3826 set_ia32_op_type(store_high, ia32_AddrModeD);
3827 set_ia32_ls_mode(store_low, mode_Iu);
3828 set_ia32_ls_mode(store_high, mode_Is);
3829 add_ia32_am_offs_int(store_high, 4);
3833 sync = new_rd_Sync(dbgi, irg, block, 2, in);
3836 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg, sync);
3838 set_ia32_use_frame(fild);
3839 set_ia32_op_type(fild, ia32_AddrModeS);
3840 set_ia32_ls_mode(fild, mode_Ls);
3842 SET_IA32_ORIG_NODE(fild, node);
3844 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
3846 if (! mode_is_signed(get_irn_mode(val_high))) {
3847 ia32_address_mode_t am;
3849 ir_node *count = create_Immediate(NULL, 0, 31);
3852 am.addr.base = ia32_new_NoReg_gp(env_cg);
3853 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
3854 am.addr.mem = nomem;
3857 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
3858 am.addr.use_frame = 0;
3859 am.addr.frame_entity = NULL;
3860 am.addr.symconst_sign = 0;
3861 am.ls_mode = mode_F;
3862 am.mem_proj = nomem;
3863 am.op_type = ia32_AddrModeS;
3865 am.new_op2 = ia32_new_NoReg_vfp(env_cg);
3866 am.pinned = op_pin_state_floats;
3868 am.ins_permuted = 0;
3870 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
3871 am.new_op1, am.new_op2, get_fpcw());
3872 set_am_attributes(fadd, &am);
3874 set_irn_mode(fadd, mode_T);
3875 res = new_rd_Proj(NULL, irg, block, fadd, mode_vfp, pn_ia32_res);
3880 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
3882 ir_node *src_block = get_nodes_block(node);
3883 ir_node *block = be_transform_node(src_block);
3884 ir_graph *irg = current_ir_graph;
3885 dbg_info *dbgi = get_irn_dbg_info(node);
3886 ir_node *frame = get_irg_frame(irg);
3887 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3888 ir_node *nomem = new_NoMem();
3889 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
3890 ir_node *new_val = be_transform_node(val);
3891 ir_node *fist, *mem;
3893 mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist);
3894 SET_IA32_ORIG_NODE(fist, node);
3895 set_ia32_use_frame(fist);
3896 set_ia32_op_type(fist, ia32_AddrModeD);
3897 set_ia32_ls_mode(fist, mode_Ls);
3903 * the BAD transformer.
3905 static ir_node *bad_transform(ir_node *node)
3907 panic("No transform function for %+F available.", node);
3911 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
3913 ir_graph *irg = current_ir_graph;
3914 ir_node *block = be_transform_node(get_nodes_block(node));
3915 ir_node *pred = get_Proj_pred(node);
3916 ir_node *new_pred = be_transform_node(pred);
3917 ir_node *frame = get_irg_frame(irg);
3918 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3919 dbg_info *dbgi = get_irn_dbg_info(node);
3920 long pn = get_Proj_proj(node);
3925 load = new_bd_ia32_Load(dbgi, block, frame, noreg, new_pred);
3926 SET_IA32_ORIG_NODE(load, node);
3927 set_ia32_use_frame(load);
3928 set_ia32_op_type(load, ia32_AddrModeS);
3929 set_ia32_ls_mode(load, mode_Iu);
3930 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
3931 * 32 bit from it with this particular load */
3932 attr = get_ia32_attr(load);
3933 attr->data.need_64bit_stackent = 1;
3935 if (pn == pn_ia32_l_FloattoLL_res_high) {
3936 add_ia32_am_offs_int(load, 4);
3938 assert(pn == pn_ia32_l_FloattoLL_res_low);
3941 proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
3947 * Transform the Projs of an AddSP.
3949 static ir_node *gen_Proj_be_AddSP(ir_node *node)
3951 ir_node *block = be_transform_node(get_nodes_block(node));
3952 ir_node *pred = get_Proj_pred(node);
3953 ir_node *new_pred = be_transform_node(pred);
3954 ir_graph *irg = current_ir_graph;
3955 dbg_info *dbgi = get_irn_dbg_info(node);
3956 long proj = get_Proj_proj(node);
3958 if (proj == pn_be_AddSP_sp) {
3959 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3960 pn_ia32_SubSP_stack);
3961 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
3963 } else if (proj == pn_be_AddSP_res) {
3964 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3965 pn_ia32_SubSP_addr);
3966 } else if (proj == pn_be_AddSP_M) {
3967 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3970 panic("No idea how to transform proj->AddSP");
3974 * Transform the Projs of a SubSP.
3976 static ir_node *gen_Proj_be_SubSP(ir_node *node)
3978 ir_node *block = be_transform_node(get_nodes_block(node));
3979 ir_node *pred = get_Proj_pred(node);
3980 ir_node *new_pred = be_transform_node(pred);
3981 ir_graph *irg = current_ir_graph;
3982 dbg_info *dbgi = get_irn_dbg_info(node);
3983 long proj = get_Proj_proj(node);
3985 if (proj == pn_be_SubSP_sp) {
3986 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3987 pn_ia32_AddSP_stack);
3988 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
3990 } else if (proj == pn_be_SubSP_M) {
3991 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3994 panic("No idea how to transform proj->SubSP");
3998 * Transform and renumber the Projs from a Load.
4000 static ir_node *gen_Proj_Load(ir_node *node)
4003 ir_node *block = be_transform_node(get_nodes_block(node));
4004 ir_node *pred = get_Proj_pred(node);
4005 ir_graph *irg = current_ir_graph;
4006 dbg_info *dbgi = get_irn_dbg_info(node);
4007 long proj = get_Proj_proj(node);
4009 /* loads might be part of source address mode matches, so we don't
4010 * transform the ProjMs yet (with the exception of loads whose result is
4013 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4016 /* this is needed, because sometimes we have loops that are only
4017 reachable through the ProjM */
4018 be_enqueue_preds(node);
4019 /* do it in 2 steps, to silence firm verifier */
4020 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4021 set_Proj_proj(res, pn_ia32_mem);
4025 /* renumber the proj */
4026 new_pred = be_transform_node(pred);
4027 if (is_ia32_Load(new_pred)) {
4030 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
4032 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
4033 case pn_Load_X_regular:
4034 return new_rd_Jmp(dbgi, irg, block);
4035 case pn_Load_X_except:
4036 /* This Load might raise an exception. Mark it. */
4037 set_ia32_exc_label(new_pred, 1);
4038 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4042 } else if (is_ia32_Conv_I2I(new_pred) ||
4043 is_ia32_Conv_I2I8Bit(new_pred)) {
4044 set_irn_mode(new_pred, mode_T);
4045 if (proj == pn_Load_res) {
4046 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4047 } else if (proj == pn_Load_M) {
4048 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4050 } else if (is_ia32_xLoad(new_pred)) {
4053 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4055 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
4056 case pn_Load_X_regular:
4057 return new_rd_Jmp(dbgi, irg, block);
4058 case pn_Load_X_except:
4059 /* This Load might raise an exception. Mark it. */
4060 set_ia32_exc_label(new_pred, 1);
4061 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4065 } else if (is_ia32_vfld(new_pred)) {
4068 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4070 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
4071 case pn_Load_X_regular:
4072 return new_rd_Jmp(dbgi, irg, block);
4073 case pn_Load_X_except:
4074 /* This Load might raise an exception. Mark it. */
4075 set_ia32_exc_label(new_pred, 1);
4076 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4081 /* can happen for ProJMs when source address mode happened for the
4084 /* however it should not be the result proj, as that would mean the
4085 load had multiple users and should not have been used for
4087 if (proj != pn_Load_M) {
4088 panic("internal error: transformed node not a Load");
4090 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4093 panic("No idea how to transform proj");
4097 * Transform and renumber the Projs from a DivMod like instruction.
4099 static ir_node *gen_Proj_DivMod(ir_node *node)
4101 ir_node *block = be_transform_node(get_nodes_block(node));
4102 ir_node *pred = get_Proj_pred(node);
4103 ir_node *new_pred = be_transform_node(pred);
4104 ir_graph *irg = current_ir_graph;
4105 dbg_info *dbgi = get_irn_dbg_info(node);
4106 long proj = get_Proj_proj(node);
4108 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4110 switch (get_irn_opcode(pred)) {
4114 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4116 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4117 case pn_Div_X_regular:
4118 return new_rd_Jmp(dbgi, irg, block);
4119 case pn_Div_X_except:
4120 set_ia32_exc_label(new_pred, 1);
4121 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4129 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4131 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4132 case pn_Mod_X_except:
4133 set_ia32_exc_label(new_pred, 1);
4134 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4142 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4143 case pn_DivMod_res_div:
4144 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4145 case pn_DivMod_res_mod:
4146 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4147 case pn_DivMod_X_regular:
4148 return new_rd_Jmp(dbgi, irg, block);
4149 case pn_DivMod_X_except:
4150 set_ia32_exc_label(new_pred, 1);
4151 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4160 panic("No idea how to transform proj->DivMod");
4164 * Transform and renumber the Projs from a CopyB.
4166 static ir_node *gen_Proj_CopyB(ir_node *node)
4168 ir_node *block = be_transform_node(get_nodes_block(node));
4169 ir_node *pred = get_Proj_pred(node);
4170 ir_node *new_pred = be_transform_node(pred);
4171 ir_graph *irg = current_ir_graph;
4172 dbg_info *dbgi = get_irn_dbg_info(node);
4173 long proj = get_Proj_proj(node);
4176 case pn_CopyB_M_regular:
4177 if (is_ia32_CopyB_i(new_pred)) {
4178 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4179 } else if (is_ia32_CopyB(new_pred)) {
4180 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4187 panic("No idea how to transform proj->CopyB");
4191 * Transform and renumber the Projs from a Quot.
4193 static ir_node *gen_Proj_Quot(ir_node *node)
4195 ir_node *block = be_transform_node(get_nodes_block(node));
4196 ir_node *pred = get_Proj_pred(node);
4197 ir_node *new_pred = be_transform_node(pred);
4198 ir_graph *irg = current_ir_graph;
4199 dbg_info *dbgi = get_irn_dbg_info(node);
4200 long proj = get_Proj_proj(node);
4204 if (is_ia32_xDiv(new_pred)) {
4205 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4206 } else if (is_ia32_vfdiv(new_pred)) {
4207 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4211 if (is_ia32_xDiv(new_pred)) {
4212 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4213 } else if (is_ia32_vfdiv(new_pred)) {
4214 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4217 case pn_Quot_X_regular:
4218 case pn_Quot_X_except:
4223 panic("No idea how to transform proj->Quot");
4226 static ir_node *gen_be_Call(ir_node *node)
4228 dbg_info *const dbgi = get_irn_dbg_info(node);
4229 ir_graph *const irg = current_ir_graph;
4230 ir_node *const src_block = get_nodes_block(node);
4231 ir_node *const block = be_transform_node(src_block);
4232 ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
4233 ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
4234 ir_node *const sp = be_transform_node(src_sp);
4235 ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
4236 ir_node *const noreg = ia32_new_NoReg_gp(env_cg);
4237 ia32_address_mode_t am;
4238 ia32_address_t *const addr = &am.addr;
4243 ir_node * eax = noreg;
4244 ir_node * ecx = noreg;
4245 ir_node * edx = noreg;
4246 unsigned const pop = be_Call_get_pop(node);
4247 ir_type *const call_tp = be_Call_get_type(node);
4249 /* Run the x87 simulator if the call returns a float value */
4250 if (get_method_n_ress(call_tp) > 0) {
4251 ir_type *const res_type = get_method_res_type(call_tp, 0);
4252 ir_mode *const res_mode = get_type_mode(res_type);
4254 if (res_mode != NULL && mode_is_float(res_mode)) {
4255 env_cg->do_x87_sim = 1;
4259 /* We do not want be_Call direct calls */
4260 assert(be_Call_get_entity(node) == NULL);
4262 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4263 match_am | match_immediate);
4265 i = get_irn_arity(node) - 1;
4266 fpcw = be_transform_node(get_irn_n(node, i--));
4267 for (; i >= be_pos_Call_first_arg; --i) {
4268 arch_register_req_t const *const req = arch_get_register_req(node, i);
4269 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4271 assert(req->type == arch_register_req_type_limited);
4272 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4274 switch (*req->limited) {
4275 case 1 << REG_EAX: assert(eax == noreg); eax = reg_parm; break;
4276 case 1 << REG_ECX: assert(ecx == noreg); ecx = reg_parm; break;
4277 case 1 << REG_EDX: assert(edx == noreg); edx = reg_parm; break;
4278 default: panic("Invalid GP register for register parameter");
4282 mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem);
4283 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4284 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4285 set_am_attributes(call, &am);
4286 call = fix_mem_proj(call, &am);
4288 if (get_irn_pinned(node) == op_pin_state_pinned)
4289 set_irn_pinned(call, op_pin_state_pinned);
4291 SET_IA32_ORIG_NODE(call, node);
4295 static ir_node *gen_be_IncSP(ir_node *node)
4297 ir_node *res = be_duplicate_node(node);
4298 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
4304 * Transform the Projs from a be_Call.
4306 static ir_node *gen_Proj_be_Call(ir_node *node)
4308 ir_node *block = be_transform_node(get_nodes_block(node));
4309 ir_node *call = get_Proj_pred(node);
4310 ir_node *new_call = be_transform_node(call);
4311 ir_graph *irg = current_ir_graph;
4312 dbg_info *dbgi = get_irn_dbg_info(node);
4313 ir_type *method_type = be_Call_get_type(call);
4314 int n_res = get_method_n_ress(method_type);
4315 long proj = get_Proj_proj(node);
4316 ir_mode *mode = get_irn_mode(node);
4320 /* The following is kinda tricky: If we're using SSE, then we have to
4321 * move the result value of the call in floating point registers to an
4322 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4323 * after the call, we have to make sure to correctly make the
4324 * MemProj and the result Proj use these 2 nodes
4326 if (proj == pn_be_Call_M_regular) {
4327 // get new node for result, are we doing the sse load/store hack?
4328 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4329 ir_node *call_res_new;
4330 ir_node *call_res_pred = NULL;
4332 if (call_res != NULL) {
4333 call_res_new = be_transform_node(call_res);
4334 call_res_pred = get_Proj_pred(call_res_new);
4337 if (call_res_pred == NULL || is_ia32_Call(call_res_pred)) {
4338 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4341 assert(is_ia32_xLoad(call_res_pred));
4342 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4346 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4347 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4349 ir_node *frame = get_irg_frame(irg);
4350 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4352 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4355 /* in case there is no memory output: create one to serialize the copy
4357 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4358 pn_be_Call_M_regular);
4359 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4360 pn_be_Call_first_res);
4362 /* store st(0) onto stack */
4363 fstp = new_bd_ia32_vfst(dbgi, block, frame, noreg, call_mem,
4365 set_ia32_op_type(fstp, ia32_AddrModeD);
4366 set_ia32_use_frame(fstp);
4368 /* load into SSE register */
4369 sse_load = new_bd_ia32_xLoad(dbgi, block, frame, noreg, fstp, mode);
4370 set_ia32_op_type(sse_load, ia32_AddrModeS);
4371 set_ia32_use_frame(sse_load);
4373 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4379 /* transform call modes */
4380 if (mode_is_data(mode)) {
4381 const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
4385 /* Map from be_Call to ia32_Call proj number */
4386 if (proj == pn_be_Call_sp) {
4387 proj = pn_ia32_Call_stack;
4388 } else if (proj == pn_be_Call_M_regular) {
4389 proj = pn_ia32_Call_M;
4391 arch_register_req_t const *const req = arch_get_register_req_out(node);
4392 int const n_outs = arch_irn_get_n_outs(new_call);
4395 assert(proj >= pn_be_Call_first_res);
4396 assert(req->type & arch_register_req_type_limited);
4398 for (i = 0; i < n_outs; ++i) {
4399 arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i);
4401 if (!(new_req->type & arch_register_req_type_limited) ||
4402 new_req->cls != req->cls ||
4403 *new_req->limited != *req->limited)
4412 res = new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4414 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
4416 case pn_ia32_Call_stack:
4417 arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
4420 case pn_ia32_Call_fpcw:
4421 arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]);
4429 * Transform the Projs from a Cmp.
4431 static ir_node *gen_Proj_Cmp(ir_node *node)
4433 /* this probably means not all mode_b nodes were lowered... */
4434 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
4439 * Transform the Projs from a Bound.
4441 static ir_node *gen_Proj_Bound(ir_node *node)
4443 ir_node *new_node, *block;
4444 ir_node *pred = get_Proj_pred(node);
4446 switch (get_Proj_proj(node)) {
4448 return be_transform_node(get_Bound_mem(pred));
4449 case pn_Bound_X_regular:
4450 new_node = be_transform_node(pred);
4451 block = get_nodes_block(new_node);
4452 return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true);
4453 case pn_Bound_X_except:
4454 new_node = be_transform_node(pred);
4455 block = get_nodes_block(new_node);
4456 return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false);
4458 return be_transform_node(get_Bound_index(pred));
4460 panic("unsupported Proj from Bound");
4464 static ir_node *gen_Proj_ASM(ir_node *node)
4470 if (get_irn_mode(node) != mode_M)
4471 return be_duplicate_node(node);
4473 pred = get_Proj_pred(node);
4474 new_pred = be_transform_node(pred);
4475 block = get_nodes_block(new_pred);
4476 return new_r_Proj(current_ir_graph, block, new_pred, mode_M,
4477 arch_irn_get_n_outs(new_pred) + 1);
4481 * Transform and potentially renumber Proj nodes.
4483 static ir_node *gen_Proj(ir_node *node)
4485 ir_node *pred = get_Proj_pred(node);
4488 switch (get_irn_opcode(pred)) {
4490 proj = get_Proj_proj(node);
4491 if (proj == pn_Store_M) {
4492 return be_transform_node(pred);
4494 panic("No idea how to transform proj->Store");
4497 return gen_Proj_Load(node);
4499 return gen_Proj_ASM(node);
4503 return gen_Proj_DivMod(node);
4505 return gen_Proj_CopyB(node);
4507 return gen_Proj_Quot(node);
4509 return gen_Proj_be_SubSP(node);
4511 return gen_Proj_be_AddSP(node);
4513 return gen_Proj_be_Call(node);
4515 return gen_Proj_Cmp(node);
4517 return gen_Proj_Bound(node);
4519 proj = get_Proj_proj(node);
4521 case pn_Start_X_initial_exec: {
4522 ir_node *block = get_nodes_block(pred);
4523 ir_node *new_block = be_transform_node(block);
4524 dbg_info *dbgi = get_irn_dbg_info(node);
4525 /* we exchange the ProjX with a jump */
4526 ir_node *jump = new_rd_Jmp(dbgi, current_ir_graph, new_block);
4531 case pn_Start_P_tls:
4532 return gen_Proj_tls(node);
4537 if (is_ia32_l_FloattoLL(pred)) {
4538 return gen_Proj_l_FloattoLL(node);
4540 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4544 ir_mode *mode = get_irn_mode(node);
4545 if (ia32_mode_needs_gp_reg(mode)) {
4546 ir_node *new_pred = be_transform_node(pred);
4547 ir_node *block = be_transform_node(get_nodes_block(node));
4548 ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred,
4549 mode_Iu, get_Proj_proj(node));
4550 #ifdef DEBUG_libfirm
4551 new_proj->node_nr = node->node_nr;
4557 return be_duplicate_node(node);
4561 * Enters all transform functions into the generic pointer
4563 static void register_transformers(void)
4567 /* first clear the generic function pointer for all ops */
4568 clear_irp_opcodes_generic_func();
4570 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4571 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4609 /* transform ops from intrinsic lowering */
4621 GEN(ia32_l_LLtoFloat);
4622 GEN(ia32_l_FloattoLL);
4628 /* we should never see these nodes */
4643 /* handle generic backend nodes */
4652 op_Mulh = get_op_Mulh();
4661 * Pre-transform all unknown and noreg nodes.
4663 static void ia32_pretransform_node(void)
4665 ia32_code_gen_t *cg = env_cg;
4667 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4668 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4669 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4670 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4671 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4672 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4677 * Walker, checks if all ia32 nodes producing more than one result have their
4678 * Projs, otherwise creates new Projs and keeps them using a be_Keep node.
4680 static void add_missing_keep_walker(ir_node *node, void *data)
4683 unsigned found_projs = 0;
4684 const ir_edge_t *edge;
4685 ir_mode *mode = get_irn_mode(node);
4690 if (!is_ia32_irn(node))
4693 n_outs = arch_irn_get_n_outs(node);
4696 if (is_ia32_SwitchJmp(node))
4699 assert(n_outs < (int) sizeof(unsigned) * 8);
4700 foreach_out_edge(node, edge) {
4701 ir_node *proj = get_edge_src_irn(edge);
4704 /* The node could be kept */
4708 if (get_irn_mode(proj) == mode_M)
4711 pn = get_Proj_proj(proj);
4712 assert(pn < n_outs);
4713 found_projs |= 1 << pn;
4717 /* are keeps missing? */
4719 for (i = 0; i < n_outs; ++i) {
4722 const arch_register_req_t *req;
4723 const arch_register_class_t *cls;
4725 if (found_projs & (1 << i)) {
4729 req = get_ia32_out_req(node, i);
4734 if (cls == &ia32_reg_classes[CLASS_ia32_flags]) {
4738 block = get_nodes_block(node);
4739 in[0] = new_r_Proj(current_ir_graph, block, node,
4740 arch_register_class_mode(cls), i);
4741 if (last_keep != NULL) {
4742 be_Keep_add_node(last_keep, cls, in[0]);
4744 last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in);
4745 if (sched_is_scheduled(node)) {
4746 sched_add_after(node, last_keep);
4753 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4756 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4758 ir_graph *irg = be_get_birg_irg(cg->birg);
4759 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4762 /* do the transformation */
4763 void ia32_transform_graph(ia32_code_gen_t *cg)
4767 register_transformers();
4769 initial_fpcw = NULL;
4771 BE_TIMER_PUSH(t_heights);
4772 heights = heights_new(cg->irg);
4773 BE_TIMER_POP(t_heights);
4774 ia32_calculate_non_address_mode_nodes(cg->birg);
4776 /* the transform phase is not safe for CSE (yet) because several nodes get
4777 * attributes set after their creation */
4778 cse_last = get_opt_cse();
4781 be_transform_graph(cg->birg, ia32_pretransform_node);
4783 set_opt_cse(cse_last);
4785 ia32_free_non_address_mode_nodes();
4786 heights_free(heights);
4790 void ia32_init_transform(void)
4792 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");