2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
493 /* don't do AM if other node inputs depend on the load (via mem-proj) */
494 if(other != NULL && get_nodes_block(other) == block
495 && heights_reachable_in_block(heights, other, load))
501 typedef struct ia32_address_mode_t ia32_address_mode_t;
502 struct ia32_address_mode_t {
506 ia32_op_type_t op_type;
514 static void build_address(ia32_address_mode_t *am, ir_node *node)
516 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
517 ia32_address_t *addr = &am->addr;
526 ir_entity *entity = create_float_const_entity(node);
527 addr->base = noreg_gp;
528 addr->index = noreg_gp;
529 addr->mem = new_NoMem();
530 addr->symconst_ent = entity;
532 am->ls_mode = get_irn_mode(node);
533 am->pinned = op_pin_state_floats;
537 load = get_Proj_pred(node);
538 ptr = get_Load_ptr(load);
539 mem = get_Load_mem(load);
540 new_mem = be_transform_node(mem);
541 am->pinned = get_irn_pinned(load);
542 am->ls_mode = get_Load_mode(load);
543 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
545 /* construct load address */
546 ia32_create_address_mode(addr, ptr, 0);
553 base = be_transform_node(base);
559 index = be_transform_node(index);
567 static void set_address(ir_node *node, ia32_address_t *addr)
569 set_ia32_am_scale(node, addr->scale);
570 set_ia32_am_sc(node, addr->symconst_ent);
571 set_ia32_am_offs_int(node, addr->offset);
572 if(addr->symconst_sign)
573 set_ia32_am_sc_sign(node);
575 set_ia32_use_frame(node);
576 set_ia32_frame_ent(node, addr->frame_entity);
579 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
581 set_address(node, &am->addr);
583 set_ia32_op_type(node, am->op_type);
584 set_ia32_ls_mode(node, am->ls_mode);
585 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
586 set_irn_pinned(node, am->pinned);
589 set_ia32_commutative(node);
592 static int is_downconv(const ir_node *node)
600 /* we only want to skip the conv when we're the only user
601 * (not optimal but for now...)
603 if(get_irn_n_edges(node) > 1)
606 src_mode = get_irn_mode(get_Conv_op(node));
607 dest_mode = get_irn_mode(node);
608 return mode_needs_gp_reg(src_mode)
609 && mode_needs_gp_reg(dest_mode)
610 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
614 match_commutative = 1 << 0,
615 match_am_and_immediates = 1 << 1,
616 match_no_am = 1 << 2,
617 match_8_bit_am = 1 << 3,
618 match_16_bit_am = 1 << 4,
619 match_no_immediate = 1 << 5,
620 match_force_32bit_op = 1 << 6,
621 match_skip_input_conv = 1 << 7
624 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
625 ir_node *op1, ir_node *op2, match_flags_t flags)
627 ia32_address_t *addr = &am->addr;
628 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
631 ir_mode *mode = get_irn_mode(op2);
634 int use_am_and_immediates;
637 int mode_bits = get_mode_size_bits(mode);
639 memset(am, 0, sizeof(am[0]));
641 commutative = (flags & match_commutative) != 0;
642 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
643 use_am = ! (flags & match_no_am);
644 use_immediate = !(flags & match_no_immediate);
645 skip_input_conv = (flags & match_skip_input_conv) != 0;
648 assert(!commutative || op1 != NULL);
650 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
652 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
656 while(is_downconv(op2)) {
657 op2 = get_Conv_op(op2);
660 while(is_downconv(op1)) {
661 op1 = get_Conv_op(op1);
665 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
666 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
667 build_address(am, op2);
668 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
669 if(mode_is_float(mode)) {
670 new_op2 = ia32_new_NoReg_vfp(env_cg);
674 am->op_type = ia32_AddrModeS;
675 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
676 use_am && use_source_address_mode(block, op1, op2)) {
678 build_address(am, op1);
680 if(mode_is_float(mode)) {
681 noreg = ia32_new_NoReg_vfp(env_cg);
686 if(new_op2 != NULL) {
689 new_op1 = be_transform_node(op2);
691 am->ins_permuted = 1;
693 am->op_type = ia32_AddrModeS;
695 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
697 new_op2 = be_transform_node(op2);
698 am->op_type = ia32_Normal;
699 if(flags & match_force_32bit_op) {
700 am->ls_mode = mode_Iu;
702 am->ls_mode = get_irn_mode(op2);
705 if(addr->base == NULL)
706 addr->base = noreg_gp;
707 if(addr->index == NULL)
708 addr->index = noreg_gp;
709 if(addr->mem == NULL)
710 addr->mem = new_NoMem();
712 am->new_op1 = new_op1;
713 am->new_op2 = new_op2;
714 am->commutative = commutative;
717 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
719 ir_graph *irg = current_ir_graph;
723 if(am->mem_proj == NULL)
726 /* we have to create a mode_T so the old MemProj can attach to us */
727 mode = get_irn_mode(node);
728 load = get_Proj_pred(am->mem_proj);
730 mark_irn_visited(load);
731 be_set_transformed_node(load, node);
734 set_irn_mode(node, mode_T);
735 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
742 * Construct a standard binary operation, set AM and immediate if required.
744 * @param op1 The first operand
745 * @param op2 The second operand
746 * @param func The node constructor function
747 * @return The constructed ia32 node.
749 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
750 construct_binop_func *func, match_flags_t flags)
752 ir_node *block = get_nodes_block(node);
753 ir_node *new_block = be_transform_node(block);
754 ir_graph *irg = current_ir_graph;
755 dbg_info *dbgi = get_irn_dbg_info(node);
757 ia32_address_mode_t am;
758 ia32_address_t *addr = &am.addr;
760 flags |= match_force_32bit_op;
762 match_arguments(&am, block, op1, op2, flags);
764 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
765 am.new_op1, am.new_op2);
766 set_am_attributes(new_node, &am);
767 /* we can't use source address mode anymore when using immediates */
768 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
769 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
770 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
772 new_node = fix_mem_proj(new_node, &am);
779 n_ia32_l_binop_right,
780 n_ia32_l_binop_eflags
782 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
783 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
784 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
785 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
786 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
787 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
790 * Construct a binary operation which also consumes the eflags.
792 * @param node The node to transform
793 * @param func The node constructor function
794 * @param flags The match flags
795 * @return The constructor ia32 node
797 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
800 ir_node *src_block = get_nodes_block(node);
801 ir_node *block = be_transform_node(src_block);
802 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
803 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
804 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
805 ir_node *new_eflags = be_transform_node(eflags);
806 ir_graph *irg = current_ir_graph;
807 dbg_info *dbgi = get_irn_dbg_info(node);
809 ia32_address_mode_t am;
810 ia32_address_t *addr = &am.addr;
812 match_arguments(&am, src_block, op1, op2, flags);
814 new_node = func(dbgi, irg, block, addr->base, addr->index,
815 addr->mem, am.new_op1, am.new_op2, new_eflags);
816 set_am_attributes(new_node, &am);
817 /* we can't use source address mode anymore when using immediates */
818 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
819 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
820 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
822 new_node = fix_mem_proj(new_node, &am);
828 * Construct a standard binary operation, set AM and immediate if required.
830 * @param op1 The first operand
831 * @param op2 The second operand
832 * @param func The node constructor function
833 * @return The constructed ia32 node.
835 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
836 construct_binop_func *func,
839 ir_node *block = get_nodes_block(node);
840 ir_node *new_block = be_transform_node(block);
841 dbg_info *dbgi = get_irn_dbg_info(node);
842 ir_graph *irg = current_ir_graph;
844 ia32_address_mode_t am;
845 ia32_address_t *addr = &am.addr;
847 match_arguments(&am, block, op1, op2, flags);
849 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
850 am.new_op1, am.new_op2);
851 set_am_attributes(new_node, &am);
853 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
855 new_node = fix_mem_proj(new_node, &am);
860 static ir_node *get_fpcw(void)
863 if(initial_fpcw != NULL)
866 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
867 &ia32_fp_cw_regs[REG_FPCW]);
868 initial_fpcw = be_transform_node(fpcw);
874 * Construct a standard binary operation, set AM and immediate if required.
876 * @param op1 The first operand
877 * @param op2 The second operand
878 * @param func The node constructor function
879 * @return The constructed ia32 node.
881 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
882 construct_binop_float_func *func,
885 ir_graph *irg = current_ir_graph;
886 dbg_info *dbgi = get_irn_dbg_info(node);
887 ir_node *block = get_nodes_block(node);
888 ir_node *new_block = be_transform_node(block);
890 ia32_address_mode_t am;
891 ia32_address_t *addr = &am.addr;
893 match_arguments(&am, block, op1, op2, flags);
895 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
896 am.new_op1, am.new_op2, get_fpcw());
897 set_am_attributes(new_node, &am);
899 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
901 new_node = fix_mem_proj(new_node, &am);
907 * Construct a shift/rotate binary operation, sets AM and immediate if required.
909 * @param op1 The first operand
910 * @param op2 The second operand
911 * @param func The node constructor function
912 * @return The constructed ia32 node.
914 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
915 construct_shift_func *func)
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_graph *irg = current_ir_graph;
919 ir_node *block = get_nodes_block(node);
920 ir_node *new_block = be_transform_node(block);
921 ir_node *new_op1 = be_transform_node(op1);
922 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
925 assert(! mode_is_float(get_irn_mode(node))
926 && "Shift/Rotate with float not supported");
928 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
929 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
931 /* lowered shift instruction may have a dependency operand, handle it here */
932 if (get_irn_arity(node) == 3) {
933 /* we have a dependency */
934 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
935 add_irn_dep(new_node, new_dep);
943 * Construct a standard unary operation, set AM and immediate if required.
945 * @param op The operand
946 * @param func The node constructor function
947 * @return The constructed ia32 node.
949 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
951 ir_node *block = be_transform_node(get_nodes_block(node));
952 ir_node *new_op = be_transform_node(op);
953 ir_node *new_node = NULL;
954 ir_graph *irg = current_ir_graph;
955 dbg_info *dbgi = get_irn_dbg_info(node);
957 new_node = func(dbgi, irg, block, new_op);
959 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
964 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
965 ia32_address_t *addr)
967 ir_graph *irg = current_ir_graph;
968 ir_node *base = addr->base;
969 ir_node *index = addr->index;
973 base = ia32_new_NoReg_gp(env_cg);
975 base = be_transform_node(base);
979 index = ia32_new_NoReg_gp(env_cg);
981 index = be_transform_node(index);
984 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
985 set_address(res, addr);
990 static int am_has_immediates(const ia32_address_t *addr)
992 return addr->offset != 0 || addr->symconst_ent != NULL
993 || addr->frame_entity || addr->use_frame;
997 * Creates an ia32 Add.
999 * @return the created ia32 Add node
1001 static ir_node *gen_Add(ir_node *node) {
1002 ir_graph *irg = current_ir_graph;
1003 dbg_info *dbgi = get_irn_dbg_info(node);
1004 ir_node *block = get_nodes_block(node);
1005 ir_node *new_block = be_transform_node(block);
1006 ir_node *op1 = get_Add_left(node);
1007 ir_node *op2 = get_Add_right(node);
1008 ir_mode *mode = get_irn_mode(node);
1010 ir_node *add_immediate_op;
1011 ia32_address_t addr;
1012 ia32_address_mode_t am;
1014 if (mode_is_float(mode)) {
1015 if (USE_SSE2(env_cg))
1016 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
1018 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
1021 while(is_downconv(op2)) {
1022 op2 = get_Conv_op(op2);
1024 while(is_downconv(op1)) {
1025 op1 = get_Conv_op(op1);
1030 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1031 * 1. Add with immediate -> Lea
1032 * 2. Add with possible source address mode -> Add
1033 * 3. Otherwise -> Lea
1035 memset(&addr, 0, sizeof(addr));
1036 ia32_create_address_mode(&addr, node, 1);
1037 add_immediate_op = NULL;
1039 if(addr.base == NULL && addr.index == NULL) {
1040 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1041 addr.symconst_sign, addr.offset);
1042 add_irn_dep(new_node, get_irg_frame(irg));
1043 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1046 /* add with immediate? */
1047 if(addr.index == NULL) {
1048 add_immediate_op = addr.base;
1049 } else if(addr.base == NULL && addr.scale == 0) {
1050 add_immediate_op = addr.index;
1053 if(add_immediate_op != NULL) {
1054 if(!am_has_immediates(&addr)) {
1055 #ifdef DEBUG_libfirm
1056 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1059 return be_transform_node(add_immediate_op);
1062 new_node = create_lea_from_address(dbgi, new_block, &addr);
1063 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1067 /* test if we can use source address mode */
1068 match_arguments(&am, block, op1, op2,
1069 match_commutative | match_force_32bit_op | match_skip_input_conv);
1071 /* construct an Add with source address mode */
1072 if (am.op_type == ia32_AddrModeS) {
1073 ia32_address_t *am_addr = &am.addr;
1074 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1075 am_addr->index, am_addr->mem, am.new_op1,
1077 set_am_attributes(new_node, &am);
1078 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1080 new_node = fix_mem_proj(new_node, &am);
1085 /* otherwise construct a lea */
1086 new_node = create_lea_from_address(dbgi, new_block, &addr);
1087 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1092 * Creates an ia32 Mul.
1094 * @return the created ia32 Mul node
1096 static ir_node *gen_Mul(ir_node *node) {
1097 ir_node *op1 = get_Mul_left(node);
1098 ir_node *op2 = get_Mul_right(node);
1099 ir_mode *mode = get_irn_mode(node);
1101 if (mode_is_float(mode)) {
1102 if (USE_SSE2(env_cg))
1103 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1105 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1109 for the lower 32bit of the result it doesn't matter whether we use
1110 signed or unsigned multiplication so we use IMul as it has fewer
1113 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1114 match_commutative | match_skip_input_conv | match_force_32bit_op);
1118 * Creates an ia32 Mulh.
1119 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1120 * this result while Mul returns the lower 32 bit.
1122 * @return the created ia32 Mulh node
1124 static ir_node *gen_Mulh(ir_node *node)
1126 ir_node *block = get_nodes_block(node);
1127 ir_node *new_block = be_transform_node(block);
1128 ir_graph *irg = current_ir_graph;
1129 dbg_info *dbgi = get_irn_dbg_info(node);
1130 ir_mode *mode = get_irn_mode(node);
1131 ir_node *op1 = get_Mulh_left(node);
1132 ir_node *op2 = get_Mulh_right(node);
1135 match_flags_t flags;
1136 ia32_address_mode_t am;
1137 ia32_address_t *addr = &am.addr;
1139 flags = match_force_32bit_op | match_commutative | match_no_immediate;
1141 assert(!mode_is_float(mode) && "Mulh with float not supported");
1143 match_arguments(&am, block, op1, op2, flags);
1145 if (mode_is_signed(mode)) {
1146 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1147 addr->index, addr->mem, am.new_op1,
1150 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1151 addr->index, addr->mem, am.new_op1,
1155 set_am_attributes(new_node, &am);
1156 /* we can't use source address mode anymore when using immediates */
1157 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1158 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1159 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1161 assert(get_irn_mode(new_node) == mode_T);
1163 fix_mem_proj(new_node, &am);
1165 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1166 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1167 mode_Iu, pn_ia32_IMul1OP_EDX);
1175 * Creates an ia32 And.
1177 * @return The created ia32 And node
1179 static ir_node *gen_And(ir_node *node) {
1180 ir_node *op1 = get_And_left(node);
1181 ir_node *op2 = get_And_right(node);
1182 assert(! mode_is_float(get_irn_mode(node)));
1184 /* is it a zero extension? */
1185 if (is_Const(op2)) {
1186 tarval *tv = get_Const_tarval(op2);
1187 long v = get_tarval_long(tv);
1189 if (v == 0xFF || v == 0xFFFF) {
1190 dbg_info *dbgi = get_irn_dbg_info(node);
1191 ir_node *block = get_nodes_block(node);
1198 assert(v == 0xFFFF);
1201 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1207 return gen_binop(node, op1, op2, new_rd_ia32_And,
1208 match_commutative | match_force_32bit_op | match_skip_input_conv);
1214 * Creates an ia32 Or.
1216 * @return The created ia32 Or node
1218 static ir_node *gen_Or(ir_node *node) {
1219 ir_node *op1 = get_Or_left(node);
1220 ir_node *op2 = get_Or_right(node);
1222 assert (! mode_is_float(get_irn_mode(node)));
1223 return gen_binop(node, op1, op2, new_rd_ia32_Or,
1224 match_commutative | match_skip_input_conv | match_force_32bit_op);
1230 * Creates an ia32 Eor.
1232 * @return The created ia32 Eor node
1234 static ir_node *gen_Eor(ir_node *node) {
1235 ir_node *op1 = get_Eor_left(node);
1236 ir_node *op2 = get_Eor_right(node);
1238 assert(! mode_is_float(get_irn_mode(node)));
1239 return gen_binop(node, op1, op2, new_rd_ia32_Xor,
1240 match_commutative | match_skip_input_conv | match_force_32bit_op);
1245 * Creates an ia32 Sub.
1247 * @return The created ia32 Sub node
1249 static ir_node *gen_Sub(ir_node *node) {
1250 ir_node *op1 = get_Sub_left(node);
1251 ir_node *op2 = get_Sub_right(node);
1252 ir_mode *mode = get_irn_mode(node);
1254 if (mode_is_float(mode)) {
1255 if (USE_SSE2(env_cg))
1256 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1258 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1262 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1266 return gen_binop(node, op1, op2, new_rd_ia32_Sub,
1267 match_force_32bit_op | match_skip_input_conv);
1270 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1273 * Generates an ia32 DivMod with additional infrastructure for the
1274 * register allocator if needed.
1276 * @param dividend -no comment- :)
1277 * @param divisor -no comment- :)
1278 * @param dm_flav flavour_Div/Mod/DivMod
1279 * @return The created ia32 DivMod node
1281 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1282 ir_node *divisor, ia32_op_flavour_t dm_flav)
1284 ir_node *block = be_transform_node(get_nodes_block(node));
1285 ir_node *new_dividend = be_transform_node(dividend);
1286 ir_node *new_divisor = be_transform_node(divisor);
1287 ir_graph *irg = current_ir_graph;
1288 dbg_info *dbgi = get_irn_dbg_info(node);
1289 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1290 ir_node *res, *proj_div, *proj_mod;
1292 ir_node *sign_extension;
1293 ir_node *mem, *new_mem;
1296 /* the upper bits have random contents for smaller modes */
1298 proj_div = proj_mod = NULL;
1302 mem = get_Div_mem(node);
1303 mode = get_Div_resmode(node);
1304 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1305 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1308 mem = get_Mod_mem(node);
1309 mode = get_Mod_resmode(node);
1310 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1311 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1313 case flavour_DivMod:
1314 mem = get_DivMod_mem(node);
1315 mode = get_DivMod_resmode(node);
1316 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1317 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1318 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1321 panic("invalid divmod flavour!");
1323 new_mem = be_transform_node(mem);
1325 assert(get_mode_size_bits(mode) == 32);
1327 if (mode_is_signed(mode)) {
1328 /* in signed mode, we need to sign extend the dividend */
1329 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1330 add_irn_dep(produceval, get_irg_frame(irg));
1331 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1334 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1335 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1336 add_irn_dep(sign_extension, get_irg_frame(irg));
1339 if (mode_is_signed(mode)) {
1340 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1341 new_dividend, sign_extension, new_divisor);
1343 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1344 new_dividend, sign_extension, new_divisor);
1347 set_ia32_exc_label(res, has_exc);
1348 set_irn_pinned(res, get_irn_pinned(node));
1350 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1357 * Wrapper for generate_DivMod. Sets flavour_Mod.
1360 static ir_node *gen_Mod(ir_node *node) {
1361 return generate_DivMod(node, get_Mod_left(node),
1362 get_Mod_right(node), flavour_Mod);
1366 * Wrapper for generate_DivMod. Sets flavour_Div.
1369 static ir_node *gen_Div(ir_node *node) {
1370 return generate_DivMod(node, get_Div_left(node),
1371 get_Div_right(node), flavour_Div);
1375 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1377 static ir_node *gen_DivMod(ir_node *node) {
1378 return generate_DivMod(node, get_DivMod_left(node),
1379 get_DivMod_right(node), flavour_DivMod);
1385 * Creates an ia32 floating Div.
1387 * @return The created ia32 xDiv node
1389 static ir_node *gen_Quot(ir_node *node)
1391 ir_node *op1 = get_Quot_left(node);
1392 ir_node *op2 = get_Quot_right(node);
1394 if (USE_SSE2(env_cg)) {
1395 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1397 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1403 * Creates an ia32 Shl.
1405 * @return The created ia32 Shl node
1407 static ir_node *gen_Shl(ir_node *node) {
1408 ir_node *left = get_Shl_left(node);
1409 ir_node *right = get_Shl_right(node);
1411 while(is_downconv(left)) {
1412 left = get_Conv_op(left);
1415 return gen_shift_binop(node, left, right, new_rd_ia32_Shl);
1421 * Creates an ia32 Shr.
1423 * @return The created ia32 Shr node
1425 static ir_node *gen_Shr(ir_node *node) {
1426 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1427 return gen_shift_binop(node, get_Shr_left(node),
1428 get_Shr_right(node), new_rd_ia32_Shr);
1434 * Creates an ia32 Sar.
1436 * @return The created ia32 Shrs node
1438 static ir_node *gen_Shrs(ir_node *node) {
1439 ir_node *left = get_Shrs_left(node);
1440 ir_node *right = get_Shrs_right(node);
1441 ir_mode *mode = get_irn_mode(node);
1443 assert(get_mode_size_bits(mode) == 32);
1445 if(is_Const(right) && mode == mode_Is) {
1446 tarval *tv = get_Const_tarval(right);
1447 long val = get_tarval_long(tv);
1449 /* this is a sign extension */
1450 ir_graph *irg = current_ir_graph;
1451 dbg_info *dbgi = get_irn_dbg_info(node);
1452 ir_node *block = be_transform_node(get_nodes_block(node));
1454 ir_node *new_op = be_transform_node(op);
1455 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1456 add_irn_dep(pval, get_irg_frame(irg));
1458 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1462 /* 8 or 16 bit sign extension? */
1463 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1464 ir_node *shl_left = get_Shl_left(left);
1465 ir_node *shl_right = get_Shl_right(left);
1466 if(is_Const(shl_right)) {
1467 tarval *tv1 = get_Const_tarval(right);
1468 tarval *tv2 = get_Const_tarval(shl_right);
1469 if(tv1 == tv2 && tarval_is_long(tv1)) {
1470 long val = get_tarval_long(tv1);
1471 if(val == 16 || val == 24) {
1472 dbg_info *dbgi = get_irn_dbg_info(node);
1473 ir_node *block = get_nodes_block(node);
1483 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1492 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1498 * Creates an ia32 RotL.
1500 * @param op1 The first operator
1501 * @param op2 The second operator
1502 * @return The created ia32 RotL node
1504 static ir_node *gen_RotL(ir_node *node,
1505 ir_node *op1, ir_node *op2) {
1506 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1507 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1513 * Creates an ia32 RotR.
1514 * NOTE: There is no RotR with immediate because this would always be a RotL
1515 * "imm-mode_size_bits" which can be pre-calculated.
1517 * @param op1 The first operator
1518 * @param op2 The second operator
1519 * @return The created ia32 RotR node
1521 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1523 assert(get_mode_size_bits(get_irn_mode(node)) == 32);
1524 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1530 * Creates an ia32 RotR or RotL (depending on the found pattern).
1532 * @return The created ia32 RotL or RotR node
1534 static ir_node *gen_Rot(ir_node *node) {
1535 ir_node *rotate = NULL;
1536 ir_node *op1 = get_Rot_left(node);
1537 ir_node *op2 = get_Rot_right(node);
1539 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1540 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1541 that means we can create a RotR instead of an Add and a RotL */
1543 if (get_irn_op(op2) == op_Add) {
1545 ir_node *left = get_Add_left(add);
1546 ir_node *right = get_Add_right(add);
1547 if (is_Const(right)) {
1548 tarval *tv = get_Const_tarval(right);
1549 ir_mode *mode = get_irn_mode(node);
1550 long bits = get_mode_size_bits(mode);
1552 if (get_irn_op(left) == op_Minus &&
1553 tarval_is_long(tv) &&
1554 get_tarval_long(tv) == bits &&
1557 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1558 rotate = gen_RotR(node, op1, get_Minus_op(left));
1563 if (rotate == NULL) {
1564 rotate = gen_RotL(node, op1, op2);
1573 * Transforms a Minus node.
1575 * @return The created ia32 Minus node
1577 static ir_node *gen_Minus(ir_node *node)
1579 ir_node *op = get_Minus_op(node);
1580 ir_node *block = be_transform_node(get_nodes_block(node));
1581 ir_graph *irg = current_ir_graph;
1582 dbg_info *dbgi = get_irn_dbg_info(node);
1583 ir_mode *mode = get_irn_mode(node);
1588 if (mode_is_float(mode)) {
1589 ir_node *new_op = be_transform_node(op);
1590 if (USE_SSE2(env_cg)) {
1591 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1592 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1593 ir_node *nomem = new_rd_NoMem(irg);
1595 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1598 size = get_mode_size_bits(mode);
1599 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1601 set_ia32_am_sc(res, ent);
1602 set_ia32_op_type(res, ia32_AddrModeS);
1603 set_ia32_ls_mode(res, mode);
1605 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1608 while(is_downconv(op)) {
1609 op = get_Conv_op(op);
1611 res = gen_unop(node, op, new_rd_ia32_Neg);
1614 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1620 * Transforms a Not node.
1622 * @return The created ia32 Not node
1624 static ir_node *gen_Not(ir_node *node) {
1625 ir_node *op = get_Not_op(node);
1626 ir_mode *mode = get_irn_mode(node);
1628 assert(mode != mode_b); /* should be lowered already */
1629 assert (! mode_is_float(mode));
1631 while(is_downconv(node)) {
1632 node = get_Conv_op(node);
1635 return gen_unop(node, op, new_rd_ia32_Not);
1641 * Transforms an Abs node.
1643 * @return The created ia32 Abs node
1645 static ir_node *gen_Abs(ir_node *node)
1647 ir_node *block = be_transform_node(get_nodes_block(node));
1648 ir_node *op = get_Abs_op(node);
1649 ir_node *new_op = be_transform_node(op);
1650 ir_graph *irg = current_ir_graph;
1651 dbg_info *dbgi = get_irn_dbg_info(node);
1652 ir_mode *mode = get_irn_mode(node);
1653 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1654 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1655 ir_node *nomem = new_NoMem();
1660 if (mode_is_float(mode)) {
1661 if (USE_SSE2(env_cg)) {
1662 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1664 size = get_mode_size_bits(mode);
1665 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1667 set_ia32_am_sc(res, ent);
1669 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1671 set_ia32_op_type(res, ia32_AddrModeS);
1672 set_ia32_ls_mode(res, mode);
1674 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1675 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1679 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1680 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1683 add_irn_dep(pval, get_irg_frame(irg));
1684 SET_IA32_ORIG_NODE(sign_extension,
1685 ia32_get_old_node_name(env_cg, node));
1687 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1689 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1691 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1693 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1700 * Transforms a Load.
1702 * @return the created ia32 Load node
1704 static ir_node *gen_Load(ir_node *node) {
1705 ir_node *old_block = get_nodes_block(node);
1706 ir_node *block = be_transform_node(old_block);
1707 ir_node *ptr = get_Load_ptr(node);
1708 ir_node *mem = get_Load_mem(node);
1709 ir_node *new_mem = be_transform_node(mem);
1712 ir_graph *irg = current_ir_graph;
1713 dbg_info *dbgi = get_irn_dbg_info(node);
1714 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1715 ir_mode *mode = get_Load_mode(node);
1718 ia32_address_t addr;
1720 /* construct load address */
1721 memset(&addr, 0, sizeof(addr));
1722 ia32_create_address_mode(&addr, ptr, 0);
1729 base = be_transform_node(base);
1735 index = be_transform_node(index);
1738 if (mode_is_float(mode)) {
1739 if (USE_SSE2(env_cg)) {
1740 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1742 res_mode = mode_xmm;
1744 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1746 res_mode = mode_vfp;
1752 /* create a conv node with address mode for smaller modes */
1753 if(get_mode_size_bits(mode) < 32) {
1754 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1755 new_mem, noreg, mode);
1757 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1762 set_irn_pinned(new_op, get_irn_pinned(node));
1763 set_ia32_op_type(new_op, ia32_AddrModeS);
1764 set_ia32_ls_mode(new_op, mode);
1765 set_address(new_op, &addr);
1767 /* make sure we are scheduled behind the initial IncSP/Barrier
1768 * to avoid spills being placed before it
1770 if (block == get_irg_start_block(irg)) {
1771 add_irn_dep(new_op, get_irg_frame(irg));
1774 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1775 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1780 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1781 ir_node *ptr, ir_mode *mode, ir_node *other)
1788 /* we only use address mode if we're the only user of the load */
1789 if(get_irn_n_edges(node) > 1)
1792 load = get_Proj_pred(node);
1795 if(get_nodes_block(load) != block)
1798 /* Store should be attached to the load */
1799 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1801 /* store should have the same pointer as the load */
1802 if(get_Load_ptr(load) != ptr)
1805 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1806 if(other != NULL && get_nodes_block(other) == block
1807 && heights_reachable_in_block(heights, other, load))
1810 assert(get_Load_mode(load) == mode);
1815 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1816 ir_node *mem, ir_node *ptr, ir_mode *mode,
1817 construct_binop_dest_func *func,
1818 construct_binop_dest_func *func8bit,
1821 ir_node *src_block = get_nodes_block(node);
1823 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1824 ir_graph *irg = current_ir_graph;
1828 ia32_address_mode_t am;
1829 ia32_address_t *addr = &am.addr;
1830 memset(&am, 0, sizeof(am));
1832 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1833 build_address(&am, op1);
1834 new_op = create_immediate_or_transform(op2, 0);
1835 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1836 build_address(&am, op2);
1837 new_op = create_immediate_or_transform(op1, 0);
1842 if(addr->base == NULL)
1843 addr->base = noreg_gp;
1844 if(addr->index == NULL)
1845 addr->index = noreg_gp;
1846 if(addr->mem == NULL)
1847 addr->mem = new_NoMem();
1849 dbgi = get_irn_dbg_info(node);
1850 block = be_transform_node(src_block);
1851 if(get_mode_size_bits(mode) == 8) {
1852 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1855 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1858 set_address(new_node, addr);
1859 set_ia32_op_type(new_node, ia32_AddrModeD);
1860 set_ia32_ls_mode(new_node, mode);
1861 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1866 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1867 ir_node *ptr, ir_mode *mode,
1868 construct_unop_dest_func *func)
1870 ir_node *src_block = get_nodes_block(node);
1872 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1873 ir_graph *irg = current_ir_graph;
1876 ia32_address_mode_t am;
1877 ia32_address_t *addr = &am.addr;
1878 memset(&am, 0, sizeof(am));
1880 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1883 build_address(&am, op);
1885 if(addr->base == NULL)
1886 addr->base = noreg_gp;
1887 if(addr->index == NULL)
1888 addr->index = noreg_gp;
1889 if(addr->mem == NULL)
1890 addr->mem = new_NoMem();
1892 dbgi = get_irn_dbg_info(node);
1893 block = be_transform_node(src_block);
1894 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1895 set_address(new_node, addr);
1896 set_ia32_op_type(new_node, ia32_AddrModeD);
1897 set_ia32_ls_mode(new_node, mode);
1898 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1903 static ir_node *try_create_dest_am(ir_node *node) {
1904 ir_node *val = get_Store_value(node);
1905 ir_node *mem = get_Store_mem(node);
1906 ir_node *ptr = get_Store_ptr(node);
1907 ir_mode *mode = get_irn_mode(val);
1912 /* handle only GP modes for now... */
1913 if(!mode_needs_gp_reg(mode))
1916 /* store must be the only user of the val node */
1917 if(get_irn_n_edges(val) > 1)
1920 switch(get_irn_opcode(val)) {
1922 op1 = get_Add_left(val);
1923 op2 = get_Add_right(val);
1924 if(is_Const_1(op2)) {
1925 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1926 new_rd_ia32_IncMem);
1928 } else if(is_Const_Minus_1(op2)) {
1929 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1930 new_rd_ia32_DecMem);
1933 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1934 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1937 op1 = get_Sub_left(val);
1938 op2 = get_Sub_right(val);
1940 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1943 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1944 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1947 op1 = get_And_left(val);
1948 op2 = get_And_right(val);
1949 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1950 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1953 op1 = get_Or_left(val);
1954 op2 = get_Or_right(val);
1955 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1956 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1959 op1 = get_Eor_left(val);
1960 op2 = get_Eor_right(val);
1961 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1962 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1965 op1 = get_Shl_left(val);
1966 op2 = get_Shl_right(val);
1967 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1968 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1971 op1 = get_Shr_left(val);
1972 op2 = get_Shr_right(val);
1973 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1974 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1977 op1 = get_Shrs_left(val);
1978 op2 = get_Shrs_right(val);
1979 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1980 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1983 op1 = get_Rot_left(val);
1984 op2 = get_Rot_right(val);
1985 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1986 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1988 /* TODO: match ROR patterns... */
1990 op1 = get_Minus_op(val);
1991 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1994 /* should be lowered already */
1995 assert(mode != mode_b);
1996 op1 = get_Not_op(val);
1997 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2007 * Transforms a Store.
2009 * @return the created ia32 Store node
2011 static ir_node *gen_Store(ir_node *node) {
2012 ir_node *block = be_transform_node(get_nodes_block(node));
2013 ir_node *ptr = get_Store_ptr(node);
2016 ir_node *val = get_Store_value(node);
2018 ir_node *mem = get_Store_mem(node);
2019 ir_node *new_mem = be_transform_node(mem);
2020 ir_graph *irg = current_ir_graph;
2021 dbg_info *dbgi = get_irn_dbg_info(node);
2022 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2023 ir_mode *mode = get_irn_mode(val);
2025 ia32_address_t addr;
2027 /* check for destination address mode */
2028 new_op = try_create_dest_am(node);
2032 /* construct store address */
2033 memset(&addr, 0, sizeof(addr));
2034 ia32_create_address_mode(&addr, ptr, 0);
2041 base = be_transform_node(base);
2047 index = be_transform_node(index);
2050 if (mode_is_float(mode)) {
2051 /* convs (and strict-convs) before stores are unnecessary if the mode
2053 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2054 val = get_Conv_op(val);
2056 new_val = be_transform_node(val);
2057 if (USE_SSE2(env_cg)) {
2058 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
2061 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
2065 new_val = create_immediate_or_transform(val, 0);
2069 if (get_mode_size_bits(mode) == 8) {
2070 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
2073 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
2078 set_irn_pinned(new_op, get_irn_pinned(node));
2079 set_ia32_op_type(new_op, ia32_AddrModeD);
2080 set_ia32_ls_mode(new_op, mode);
2082 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2083 set_address(new_op, &addr);
2084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2089 static ir_node *create_Switch(ir_node *node)
2091 ir_graph *irg = current_ir_graph;
2092 dbg_info *dbgi = get_irn_dbg_info(node);
2093 ir_node *block = be_transform_node(get_nodes_block(node));
2094 ir_node *sel = get_Cond_selector(node);
2095 ir_node *new_sel = be_transform_node(sel);
2097 int switch_min = INT_MAX;
2098 const ir_edge_t *edge;
2100 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2102 /* determine the smallest switch case value */
2103 foreach_out_edge(node, edge) {
2104 ir_node *proj = get_edge_src_irn(edge);
2105 int pn = get_Proj_proj(proj);
2110 if (switch_min != 0) {
2111 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2113 /* if smallest switch case is not 0 we need an additional sub */
2114 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2115 add_ia32_am_offs_int(new_sel, -switch_min);
2116 set_ia32_op_type(new_sel, ia32_AddrModeS);
2118 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2121 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2122 set_ia32_pncode(res, get_Cond_defaultProj(node));
2124 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2129 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2131 ir_graph *irg = current_ir_graph;
2139 /* we have a Cmp as input */
2141 ir_node *pred = get_Proj_pred(node);
2143 flags = be_transform_node(pred);
2144 *pnc_out = get_Proj_proj(node);
2149 /* a mode_b value, we have to compare it against 0 */
2150 dbgi = get_irn_dbg_info(node);
2151 new_block = be_transform_node(get_nodes_block(node));
2152 new_op = be_transform_node(node);
2153 noreg = ia32_new_NoReg_gp(env_cg);
2154 nomem = new_NoMem();
2155 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2156 new_op, new_op, 0, 0);
2157 *pnc_out = pn_Cmp_Lg;
2161 static ir_node *gen_Cond(ir_node *node) {
2162 ir_node *block = get_nodes_block(node);
2163 ir_node *new_block = be_transform_node(block);
2164 ir_graph *irg = current_ir_graph;
2165 dbg_info *dbgi = get_irn_dbg_info(node);
2166 ir_node *sel = get_Cond_selector(node);
2167 ir_mode *sel_mode = get_irn_mode(sel);
2169 ir_node *flags = NULL;
2172 if (sel_mode != mode_b) {
2173 return create_Switch(node);
2176 /* we get flags from a cmp */
2177 flags = get_flags_node(sel, &pnc);
2179 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2180 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2188 * Transforms a CopyB node.
2190 * @return The transformed node.
2192 static ir_node *gen_CopyB(ir_node *node) {
2193 ir_node *block = be_transform_node(get_nodes_block(node));
2194 ir_node *src = get_CopyB_src(node);
2195 ir_node *new_src = be_transform_node(src);
2196 ir_node *dst = get_CopyB_dst(node);
2197 ir_node *new_dst = be_transform_node(dst);
2198 ir_node *mem = get_CopyB_mem(node);
2199 ir_node *new_mem = be_transform_node(mem);
2200 ir_node *res = NULL;
2201 ir_graph *irg = current_ir_graph;
2202 dbg_info *dbgi = get_irn_dbg_info(node);
2203 int size = get_type_size_bytes(get_CopyB_type(node));
2206 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2207 /* then we need the size explicitly in ECX. */
2208 if (size >= 32 * 4) {
2209 rem = size & 0x3; /* size % 4 */
2212 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2214 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2216 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2218 add_irn_dep(res, get_irg_frame(irg));
2220 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2221 /* we misuse the pncode field for the copyb size */
2222 set_ia32_pncode(res, rem);
2224 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2225 set_ia32_pncode(res, size);
2228 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2233 static ir_node *gen_be_Copy(ir_node *node)
2235 ir_node *result = be_duplicate_node(node);
2236 ir_mode *mode = get_irn_mode(result);
2238 if (mode_needs_gp_reg(mode)) {
2239 set_irn_mode(result, mode_Iu);
2246 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2247 * to fold an and into a test node
2249 static int can_fold_test_and(ir_node *node)
2251 const ir_edge_t *edge;
2253 /** we can only have eq and lg projs */
2254 foreach_out_edge(node, edge) {
2255 ir_node *proj = get_edge_src_irn(edge);
2256 pn_Cmp pnc = get_Proj_proj(proj);
2257 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2264 static ir_node *try_create_Test(ir_node *node)
2266 ir_graph *irg = current_ir_graph;
2267 dbg_info *dbgi = get_irn_dbg_info(node);
2268 ir_node *block = get_nodes_block(node);
2269 ir_node *new_block = be_transform_node(block);
2270 ir_node *cmp_left = get_Cmp_left(node);
2271 ir_node *cmp_right = get_Cmp_right(node);
2276 ia32_address_mode_t am;
2277 ia32_address_t *addr = &am.addr;
2280 /* can we use a test instruction? */
2281 if(!is_Const_0(cmp_right))
2284 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2285 can_fold_test_and(node)) {
2286 ir_node *and_left = get_And_left(cmp_left);
2287 ir_node *and_right = get_And_right(cmp_left);
2289 mode = get_irn_mode(and_left);
2293 mode = get_irn_mode(cmp_left);
2298 assert(get_mode_size_bits(mode) <= 32);
2300 match_arguments(&am, block, left, right, match_commutative |
2301 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2303 cmp_unsigned = !mode_is_signed(mode);
2304 if(get_mode_size_bits(mode) == 8) {
2305 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2306 addr->index, addr->mem, am.new_op1,
2307 am.new_op2, am.ins_permuted, cmp_unsigned);
2309 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2310 addr->mem, am.new_op1, am.new_op2,
2311 am.ins_permuted, cmp_unsigned);
2313 set_am_attributes(res, &am);
2314 assert(mode != NULL);
2315 set_ia32_ls_mode(res, mode);
2317 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2319 res = fix_mem_proj(res, &am);
2323 static ir_node *create_Fucom(ir_node *node)
2325 ir_graph *irg = current_ir_graph;
2326 dbg_info *dbgi = get_irn_dbg_info(node);
2327 ir_node *block = get_nodes_block(node);
2328 ir_node *new_block = be_transform_node(block);
2329 ir_node *left = get_Cmp_left(node);
2330 ir_node *new_left = be_transform_node(left);
2331 ir_node *right = get_Cmp_right(node);
2335 if(transform_config.use_fucomi) {
2336 new_right = be_transform_node(right);
2337 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2338 set_ia32_commutative(res);
2339 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2341 if(transform_config.use_ftst && is_Const_null(right)) {
2342 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2344 new_right = be_transform_node(right);
2345 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2349 set_ia32_commutative(res);
2351 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2353 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2354 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2360 static ir_node *create_Ucomi(ir_node *node)
2362 ir_graph *irg = current_ir_graph;
2363 dbg_info *dbgi = get_irn_dbg_info(node);
2364 ir_node *src_block = get_nodes_block(node);
2365 ir_node *new_block = be_transform_node(src_block);
2366 ir_node *left = get_Cmp_left(node);
2367 ir_node *right = get_Cmp_right(node);
2369 ia32_address_mode_t am;
2370 ia32_address_t *addr = &am.addr;
2372 match_arguments(&am, src_block, left, right, match_commutative);
2374 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2375 addr->mem, am.new_op1, am.new_op2,
2377 set_am_attributes(new_node, &am);
2379 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2381 new_node = fix_mem_proj(new_node, &am);
2386 static ir_node *gen_Cmp(ir_node *node)
2388 ir_graph *irg = current_ir_graph;
2389 dbg_info *dbgi = get_irn_dbg_info(node);
2390 ir_node *block = get_nodes_block(node);
2391 ir_node *new_block = be_transform_node(block);
2392 ir_node *left = get_Cmp_left(node);
2393 ir_node *right = get_Cmp_right(node);
2394 ir_mode *cmp_mode = get_irn_mode(left);
2396 ia32_address_mode_t am;
2397 ia32_address_t *addr = &am.addr;
2400 if(mode_is_float(cmp_mode)) {
2401 if (USE_SSE2(env_cg)) {
2402 return create_Ucomi(node);
2404 return create_Fucom(node);
2408 assert(mode_needs_gp_reg(cmp_mode));
2410 /* we prefer the Test instruction where possible except cases where
2411 * we can use SourceAM */
2412 if(!use_source_address_mode(block, left, right) &&
2413 !use_source_address_mode(block, right, left)) {
2414 res = try_create_Test(node);
2419 match_arguments(&am, block, left, right,
2420 match_commutative | match_8_bit_am | match_16_bit_am |
2421 match_am_and_immediates);
2423 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2424 if(get_mode_size_bits(cmp_mode) == 8) {
2425 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2426 addr->mem, am.new_op1, am.new_op2,
2427 am.ins_permuted, cmp_unsigned);
2429 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2430 addr->mem, am.new_op1, am.new_op2,
2431 am.ins_permuted, cmp_unsigned);
2433 set_am_attributes(res, &am);
2434 assert(cmp_mode != NULL);
2435 set_ia32_ls_mode(res, cmp_mode);
2437 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2439 res = fix_mem_proj(res, &am);
2444 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2446 ir_graph *irg = current_ir_graph;
2447 dbg_info *dbgi = get_irn_dbg_info(node);
2448 ir_node *block = get_nodes_block(node);
2449 ir_node *new_block = be_transform_node(block);
2450 ir_node *val_true = get_Psi_val(node, 0);
2451 ir_node *val_false = get_Psi_default(node);
2453 match_flags_t match_flags;
2454 ia32_address_mode_t am;
2455 ia32_address_t *addr;
2457 assert(transform_config.use_cmov);
2458 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2462 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2463 | match_force_32bit_op;
2465 match_arguments(&am, block, val_false, val_true, match_flags);
2467 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2468 addr->mem, am.new_op1, am.new_op2, new_flags,
2469 am.ins_permuted, pnc);
2470 set_am_attributes(new_node, &am);
2472 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2474 new_node = fix_mem_proj(new_node, &am);
2481 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2482 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2485 ir_graph *irg = current_ir_graph;
2486 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2487 ir_node *nomem = new_NoMem();
2490 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2491 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2492 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2493 nomem, res, mode_Bu);
2494 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2500 * Transforms a Psi node into CMov.
2502 * @return The transformed node.
2504 static ir_node *gen_Psi(ir_node *node)
2506 dbg_info *dbgi = get_irn_dbg_info(node);
2507 ir_node *block = get_nodes_block(node);
2508 ir_node *new_block = be_transform_node(block);
2509 ir_node *psi_true = get_Psi_val(node, 0);
2510 ir_node *psi_default = get_Psi_default(node);
2511 ir_node *cond = get_Psi_cond(node, 0);
2512 ir_node *flags = NULL;
2516 assert(get_Psi_n_conds(node) == 1);
2517 assert(get_irn_mode(cond) == mode_b);
2518 assert(mode_needs_gp_reg(get_irn_mode(node)));
2520 flags = get_flags_node(cond, &pnc);
2522 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2523 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2524 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2525 res = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2527 res = create_CMov(node, flags, pnc);
2534 * Create a conversion from x87 state register to general purpose.
2536 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2537 ir_node *block = be_transform_node(get_nodes_block(node));
2538 ir_node *op = get_Conv_op(node);
2539 ir_node *new_op = be_transform_node(op);
2540 ia32_code_gen_t *cg = env_cg;
2541 ir_graph *irg = current_ir_graph;
2542 dbg_info *dbgi = get_irn_dbg_info(node);
2543 ir_node *noreg = ia32_new_NoReg_gp(cg);
2544 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2545 ir_mode *mode = get_irn_mode(node);
2546 ir_node *fist, *load;
2549 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2550 new_NoMem(), new_op, trunc_mode);
2552 set_irn_pinned(fist, op_pin_state_floats);
2553 set_ia32_use_frame(fist);
2554 set_ia32_op_type(fist, ia32_AddrModeD);
2556 assert(get_mode_size_bits(mode) <= 32);
2557 /* exception we can only store signed 32 bit integers, so for unsigned
2558 we store a 64bit (signed) integer and load the lower bits */
2559 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2560 set_ia32_ls_mode(fist, mode_Ls);
2562 set_ia32_ls_mode(fist, mode_Is);
2564 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2567 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2569 set_irn_pinned(load, op_pin_state_floats);
2570 set_ia32_use_frame(load);
2571 set_ia32_op_type(load, ia32_AddrModeS);
2572 set_ia32_ls_mode(load, mode_Is);
2573 if(get_ia32_ls_mode(fist) == mode_Ls) {
2574 ia32_attr_t *attr = get_ia32_attr(load);
2575 attr->data.need_64bit_stackent = 1;
2577 ia32_attr_t *attr = get_ia32_attr(load);
2578 attr->data.need_32bit_stackent = 1;
2580 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2582 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2586 * Creates a x87 strict Conv by placing a Sore and a Load
2588 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2590 ir_node *block = get_nodes_block(node);
2591 ir_graph *irg = current_ir_graph;
2592 dbg_info *dbgi = get_irn_dbg_info(node);
2593 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2594 ir_node *nomem = new_NoMem();
2595 ir_node *frame = get_irg_frame(irg);
2596 ir_node *store, *load;
2599 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2601 set_ia32_use_frame(store);
2602 set_ia32_op_type(store, ia32_AddrModeD);
2603 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2605 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2607 set_ia32_use_frame(load);
2608 set_ia32_op_type(load, ia32_AddrModeS);
2609 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2611 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2615 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2617 ir_graph *irg = current_ir_graph;
2618 ir_node *start_block = get_irg_start_block(irg);
2619 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2620 symconst, symconst_sign, val);
2621 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2627 * Create a conversion from general purpose to x87 register
2629 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2630 ir_node *src_block = get_nodes_block(node);
2631 ir_node *block = be_transform_node(src_block);
2632 ir_graph *irg = current_ir_graph;
2633 dbg_info *dbgi = get_irn_dbg_info(node);
2634 ir_node *op = get_Conv_op(node);
2639 ir_mode *store_mode;
2645 /* fild can use source AM if the operand is a signed 32bit integer */
2646 if (src_mode == mode_Is) {
2647 ia32_address_mode_t am;
2649 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2650 if (am.op_type == ia32_AddrModeS) {
2651 ia32_address_t *addr = &am.addr;
2653 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2654 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2656 set_am_attributes(fild, &am);
2657 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2659 fix_mem_proj(fild, &am);
2663 new_op = am.new_op2;
2665 new_op = be_transform_node(op);
2668 noreg = ia32_new_NoReg_gp(env_cg);
2669 nomem = new_NoMem();
2670 mode = get_irn_mode(op);
2672 /* first convert to 32 bit signed if necessary */
2673 src_bits = get_mode_size_bits(src_mode);
2674 if (src_bits == 8) {
2675 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2677 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2679 } else if (src_bits < 32) {
2680 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2682 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2686 assert(get_mode_size_bits(mode) == 32);
2689 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2692 set_ia32_use_frame(store);
2693 set_ia32_op_type(store, ia32_AddrModeD);
2694 set_ia32_ls_mode(store, mode_Iu);
2696 /* exception for 32bit unsigned, do a 64bit spill+load */
2697 if(!mode_is_signed(mode)) {
2700 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2702 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2703 get_irg_frame(irg), noreg, nomem,
2706 set_ia32_use_frame(zero_store);
2707 set_ia32_op_type(zero_store, ia32_AddrModeD);
2708 add_ia32_am_offs_int(zero_store, 4);
2709 set_ia32_ls_mode(zero_store, mode_Iu);
2714 store = new_rd_Sync(dbgi, irg, block, 2, in);
2715 store_mode = mode_Ls;
2717 store_mode = mode_Is;
2721 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2723 set_ia32_use_frame(fild);
2724 set_ia32_op_type(fild, ia32_AddrModeS);
2725 set_ia32_ls_mode(fild, store_mode);
2727 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2733 * Create a conversion from one integer mode into another one
2735 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2736 dbg_info *dbgi, ir_node *block, ir_node *op,
2739 ir_graph *irg = current_ir_graph;
2740 int src_bits = get_mode_size_bits(src_mode);
2741 int tgt_bits = get_mode_size_bits(tgt_mode);
2742 ir_node *new_block = be_transform_node(block);
2743 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2746 ir_mode *smaller_mode;
2748 ia32_address_mode_t am;
2749 ia32_address_t *addr = &am.addr;
2751 if (src_bits < tgt_bits) {
2752 smaller_mode = src_mode;
2753 smaller_bits = src_bits;
2755 smaller_mode = tgt_mode;
2756 smaller_bits = tgt_bits;
2759 memset(&am, 0, sizeof(am));
2760 if(use_source_address_mode(block, op, NULL)) {
2761 build_address(&am, op);
2763 am.op_type = ia32_AddrModeS;
2765 new_op = be_transform_node(op);
2766 am.op_type = ia32_Normal;
2768 if(addr->base == NULL)
2770 if(addr->index == NULL)
2771 addr->index = noreg;
2772 if(addr->mem == NULL)
2773 addr->mem = new_NoMem();
2775 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2776 if (smaller_bits == 8) {
2777 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2778 addr->index, addr->mem, new_op,
2781 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2782 addr->index, addr->mem, new_op,
2786 set_am_attributes(res, &am);
2787 set_ia32_ls_mode(res, smaller_mode);
2788 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2789 res = fix_mem_proj(res, &am);
2795 * Transforms a Conv node.
2797 * @return The created ia32 Conv node
2799 static ir_node *gen_Conv(ir_node *node) {
2800 ir_node *block = get_nodes_block(node);
2801 ir_node *new_block = be_transform_node(block);
2802 ir_node *op = get_Conv_op(node);
2803 ir_node *new_op = NULL;
2804 ir_graph *irg = current_ir_graph;
2805 dbg_info *dbgi = get_irn_dbg_info(node);
2806 ir_mode *src_mode = get_irn_mode(op);
2807 ir_mode *tgt_mode = get_irn_mode(node);
2808 int src_bits = get_mode_size_bits(src_mode);
2809 int tgt_bits = get_mode_size_bits(tgt_mode);
2810 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2811 ir_node *nomem = new_rd_NoMem(irg);
2812 ir_node *res = NULL;
2814 if (src_mode == mode_b) {
2815 assert(mode_is_int(tgt_mode));
2816 /* nothing to do, we already model bools as 0/1 ints */
2817 return be_transform_node(op);
2820 if (src_mode == tgt_mode) {
2821 if (get_Conv_strict(node)) {
2822 if (USE_SSE2(env_cg)) {
2823 /* when we are in SSE mode, we can kill all strict no-op conversion */
2824 return be_transform_node(op);
2827 /* this should be optimized already, but who knows... */
2828 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2829 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2830 return be_transform_node(op);
2834 if (mode_is_float(src_mode)) {
2835 new_op = be_transform_node(op);
2836 /* we convert from float ... */
2837 if (mode_is_float(tgt_mode)) {
2838 if(src_mode == mode_E && tgt_mode == mode_D
2839 && !get_Conv_strict(node)) {
2840 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2845 if (USE_SSE2(env_cg)) {
2846 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2847 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2849 set_ia32_ls_mode(res, tgt_mode);
2851 if(get_Conv_strict(node)) {
2852 res = gen_x87_strict_conv(tgt_mode, new_op);
2853 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2856 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2861 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2862 if (USE_SSE2(env_cg)) {
2863 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2865 set_ia32_ls_mode(res, src_mode);
2867 return gen_x87_fp_to_gp(node);
2871 /* we convert from int ... */
2872 if (mode_is_float(tgt_mode)) {
2874 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2875 if (USE_SSE2(env_cg)) {
2876 new_op = be_transform_node(op);
2877 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2879 set_ia32_ls_mode(res, tgt_mode);
2881 res = gen_x87_gp_to_fp(node, src_mode);
2882 if(get_Conv_strict(node)) {
2883 res = gen_x87_strict_conv(tgt_mode, res);
2884 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2885 ia32_get_old_node_name(env_cg, node));
2889 } else if(tgt_mode == mode_b) {
2890 /* mode_b lowering already took care that we only have 0/1 values */
2891 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2892 src_mode, tgt_mode));
2893 return be_transform_node(op);
2896 if (src_bits == tgt_bits) {
2897 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2898 src_mode, tgt_mode));
2899 return be_transform_node(op);
2902 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2910 static int check_immediate_constraint(long val, char immediate_constraint_type)
2912 switch (immediate_constraint_type) {
2916 return val >= 0 && val <= 32;
2918 return val >= 0 && val <= 63;
2920 return val >= -128 && val <= 127;
2922 return val == 0xff || val == 0xffff;
2924 return val >= 0 && val <= 3;
2926 return val >= 0 && val <= 255;
2928 return val >= 0 && val <= 127;
2932 panic("Invalid immediate constraint found");
2936 static ir_node *try_create_Immediate(ir_node *node,
2937 char immediate_constraint_type)
2940 tarval *offset = NULL;
2941 int offset_sign = 0;
2943 ir_entity *symconst_ent = NULL;
2944 int symconst_sign = 0;
2946 ir_node *cnst = NULL;
2947 ir_node *symconst = NULL;
2950 mode = get_irn_mode(node);
2951 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2955 if(is_Minus(node)) {
2957 node = get_Minus_op(node);
2960 if(is_Const(node)) {
2963 offset_sign = minus;
2964 } else if(is_SymConst(node)) {
2967 symconst_sign = minus;
2968 } else if(is_Add(node)) {
2969 ir_node *left = get_Add_left(node);
2970 ir_node *right = get_Add_right(node);
2971 if(is_Const(left) && is_SymConst(right)) {
2974 symconst_sign = minus;
2975 offset_sign = minus;
2976 } else if(is_SymConst(left) && is_Const(right)) {
2979 symconst_sign = minus;
2980 offset_sign = minus;
2982 } else if(is_Sub(node)) {
2983 ir_node *left = get_Sub_left(node);
2984 ir_node *right = get_Sub_right(node);
2985 if(is_Const(left) && is_SymConst(right)) {
2988 symconst_sign = !minus;
2989 offset_sign = minus;
2990 } else if(is_SymConst(left) && is_Const(right)) {
2993 symconst_sign = minus;
2994 offset_sign = !minus;
3001 offset = get_Const_tarval(cnst);
3002 if(tarval_is_long(offset)) {
3003 val = get_tarval_long(offset);
3005 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3010 if(!check_immediate_constraint(val, immediate_constraint_type))
3013 if(symconst != NULL) {
3014 if(immediate_constraint_type != 0) {
3015 /* we need full 32bits for symconsts */
3019 /* unfortunately the assembler/linker doesn't support -symconst */
3023 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3025 symconst_ent = get_SymConst_entity(symconst);
3027 if(cnst == NULL && symconst == NULL)
3030 if(offset_sign && offset != NULL) {
3031 offset = tarval_neg(offset);
3034 res = create_Immediate(symconst_ent, symconst_sign, val);
3039 static ir_node *create_immediate_or_transform(ir_node *node,
3040 char immediate_constraint_type)
3042 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3043 if (new_node == NULL) {
3044 new_node = be_transform_node(node);
3049 static const arch_register_req_t no_register_req = {
3050 arch_register_req_type_none,
3051 NULL, /* regclass */
3052 NULL, /* limit bitset */
3053 { -1, -1 }, /* same pos */
3054 -1 /* different pos */
3058 * An assembler constraint.
3060 typedef struct constraint_t constraint_t;
3061 struct constraint_t {
3064 const arch_register_req_t **out_reqs;
3066 const arch_register_req_t *req;
3067 unsigned immediate_possible;
3068 char immediate_type;
3071 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3073 int immediate_possible = 0;
3074 char immediate_type = 0;
3075 unsigned limited = 0;
3076 const arch_register_class_t *cls = NULL;
3077 ir_graph *irg = current_ir_graph;
3078 struct obstack *obst = get_irg_obstack(irg);
3079 arch_register_req_t *req;
3080 unsigned *limited_ptr;
3084 /* TODO: replace all the asserts with nice error messages */
3087 /* a memory constraint: no need to do anything in backend about it
3088 * (the dependencies are already respected by the memory edge of
3090 constraint->req = &no_register_req;
3102 assert(cls == NULL ||
3103 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3104 cls = &ia32_reg_classes[CLASS_ia32_gp];
3105 limited |= 1 << REG_EAX;
3108 assert(cls == NULL ||
3109 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3110 cls = &ia32_reg_classes[CLASS_ia32_gp];
3111 limited |= 1 << REG_EBX;
3114 assert(cls == NULL ||
3115 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3116 cls = &ia32_reg_classes[CLASS_ia32_gp];
3117 limited |= 1 << REG_ECX;
3120 assert(cls == NULL ||
3121 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3122 cls = &ia32_reg_classes[CLASS_ia32_gp];
3123 limited |= 1 << REG_EDX;
3126 assert(cls == NULL ||
3127 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3128 cls = &ia32_reg_classes[CLASS_ia32_gp];
3129 limited |= 1 << REG_EDI;
3132 assert(cls == NULL ||
3133 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3134 cls = &ia32_reg_classes[CLASS_ia32_gp];
3135 limited |= 1 << REG_ESI;
3138 case 'q': /* q means lower part of the regs only, this makes no
3139 * difference to Q for us (we only assigne whole registers) */
3140 assert(cls == NULL ||
3141 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3142 cls = &ia32_reg_classes[CLASS_ia32_gp];
3143 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3147 assert(cls == NULL ||
3148 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3149 cls = &ia32_reg_classes[CLASS_ia32_gp];
3150 limited |= 1 << REG_EAX | 1 << REG_EDX;
3153 assert(cls == NULL ||
3154 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3155 cls = &ia32_reg_classes[CLASS_ia32_gp];
3156 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3157 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3164 assert(cls == NULL);
3165 cls = &ia32_reg_classes[CLASS_ia32_gp];
3171 /* TODO: mark values so the x87 simulator knows about t and u */
3172 assert(cls == NULL);
3173 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3178 assert(cls == NULL);
3179 /* TODO: check that sse2 is supported */
3180 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3190 assert(!immediate_possible);
3191 immediate_possible = 1;
3192 immediate_type = *c;
3196 assert(!immediate_possible);
3197 immediate_possible = 1;
3201 assert(!immediate_possible && cls == NULL);
3202 immediate_possible = 1;
3203 cls = &ia32_reg_classes[CLASS_ia32_gp];
3216 assert(constraint->is_in && "can only specify same constraint "
3219 sscanf(c, "%d%n", &same_as, &p);
3227 /* memory constraint no need to do anything in backend about it
3228 * (the dependencies are already respected by the memory edge of
3230 constraint->req = &no_register_req;
3233 case 'E': /* no float consts yet */
3234 case 'F': /* no float consts yet */
3235 case 's': /* makes no sense on x86 */
3236 case 'X': /* we can't support that in firm */
3239 case '<': /* no autodecrement on x86 */
3240 case '>': /* no autoincrement on x86 */
3241 case 'C': /* sse constant not supported yet */
3242 case 'G': /* 80387 constant not supported yet */
3243 case 'y': /* we don't support mmx registers yet */
3244 case 'Z': /* not available in 32 bit mode */
3245 case 'e': /* not available in 32 bit mode */
3246 panic("unsupported asm constraint '%c' found in (%+F)",
3247 *c, current_ir_graph);
3250 panic("unknown asm constraint '%c' found in (%+F)", *c,
3258 const arch_register_req_t *other_constr;
3260 assert(cls == NULL && "same as and register constraint not supported");
3261 assert(!immediate_possible && "same as and immediate constraint not "
3263 assert(same_as < constraint->n_outs && "wrong constraint number in "
3264 "same_as constraint");
3266 other_constr = constraint->out_reqs[same_as];
3268 req = obstack_alloc(obst, sizeof(req[0]));
3269 req->cls = other_constr->cls;
3270 req->type = arch_register_req_type_should_be_same;
3271 req->limited = NULL;
3272 req->other_same[0] = pos;
3273 req->other_same[1] = -1;
3274 req->other_different = -1;
3276 /* switch constraints. This is because in firm we have same_as
3277 * constraints on the output constraints while in the gcc asm syntax
3278 * they are specified on the input constraints */
3279 constraint->req = other_constr;
3280 constraint->out_reqs[same_as] = req;
3281 constraint->immediate_possible = 0;
3285 if(immediate_possible && cls == NULL) {
3286 cls = &ia32_reg_classes[CLASS_ia32_gp];
3288 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3289 assert(cls != NULL);
3291 if(immediate_possible) {
3292 assert(constraint->is_in
3293 && "immediate make no sense for output constraints");
3295 /* todo: check types (no float input on 'r' constrained in and such... */
3298 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3299 limited_ptr = (unsigned*) (req+1);
3301 req = obstack_alloc(obst, sizeof(req[0]));
3303 memset(req, 0, sizeof(req[0]));
3306 req->type = arch_register_req_type_limited;
3307 *limited_ptr = limited;
3308 req->limited = limited_ptr;
3310 req->type = arch_register_req_type_normal;
3314 constraint->req = req;
3315 constraint->immediate_possible = immediate_possible;
3316 constraint->immediate_type = immediate_type;
3319 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3326 panic("Clobbers not supported yet");
3329 static int is_memory_op(const ir_asm_constraint *constraint)
3331 ident *id = constraint->constraint;
3332 const char *str = get_id_str(id);
3335 for(c = str; *c != '\0'; ++c) {
3344 * generates code for a ASM node
3346 static ir_node *gen_ASM(ir_node *node)
3349 ir_graph *irg = current_ir_graph;
3350 ir_node *block = get_nodes_block(node);
3351 ir_node *new_block = be_transform_node(block);
3352 dbg_info *dbgi = get_irn_dbg_info(node);
3356 int n_out_constraints;
3358 const arch_register_req_t **out_reg_reqs;
3359 const arch_register_req_t **in_reg_reqs;
3360 ia32_asm_reg_t *register_map;
3361 unsigned reg_map_size = 0;
3362 struct obstack *obst;
3363 const ir_asm_constraint *in_constraints;
3364 const ir_asm_constraint *out_constraints;
3366 constraint_t parsed_constraint;
3368 arity = get_irn_arity(node);
3369 in = alloca(arity * sizeof(in[0]));
3370 memset(in, 0, arity * sizeof(in[0]));
3372 n_out_constraints = get_ASM_n_output_constraints(node);
3373 n_clobbers = get_ASM_n_clobbers(node);
3374 out_arity = n_out_constraints + n_clobbers;
3376 in_constraints = get_ASM_input_constraints(node);
3377 out_constraints = get_ASM_output_constraints(node);
3378 clobbers = get_ASM_clobbers(node);
3380 /* construct output constraints */
3381 obst = get_irg_obstack(irg);
3382 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3383 parsed_constraint.out_reqs = out_reg_reqs;
3384 parsed_constraint.n_outs = n_out_constraints;
3385 parsed_constraint.is_in = 0;
3387 for(i = 0; i < out_arity; ++i) {
3390 if(i < n_out_constraints) {
3391 const ir_asm_constraint *constraint = &out_constraints[i];
3392 c = get_id_str(constraint->constraint);
3393 parse_asm_constraint(i, &parsed_constraint, c);
3395 if(constraint->pos > reg_map_size)
3396 reg_map_size = constraint->pos;
3398 ident *glob_id = clobbers [i - n_out_constraints];
3399 c = get_id_str(glob_id);
3400 parse_clobber(node, i, &parsed_constraint, c);
3403 out_reg_reqs[i] = parsed_constraint.req;
3406 /* construct input constraints */
3407 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3408 parsed_constraint.is_in = 1;
3409 for(i = 0; i < arity; ++i) {
3410 const ir_asm_constraint *constraint = &in_constraints[i];
3411 ident *constr_id = constraint->constraint;
3412 const char *c = get_id_str(constr_id);
3414 parse_asm_constraint(i, &parsed_constraint, c);
3415 in_reg_reqs[i] = parsed_constraint.req;
3417 if(constraint->pos > reg_map_size)
3418 reg_map_size = constraint->pos;
3420 if(parsed_constraint.immediate_possible) {
3421 ir_node *pred = get_irn_n(node, i);
3422 char imm_type = parsed_constraint.immediate_type;
3423 ir_node *immediate = try_create_Immediate(pred, imm_type);
3425 if(immediate != NULL) {
3432 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3433 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3435 for(i = 0; i < n_out_constraints; ++i) {
3436 const ir_asm_constraint *constraint = &out_constraints[i];
3437 unsigned pos = constraint->pos;
3439 assert(pos < reg_map_size);
3440 register_map[pos].use_input = 0;
3441 register_map[pos].valid = 1;
3442 register_map[pos].memory = is_memory_op(constraint);
3443 register_map[pos].inout_pos = i;
3444 register_map[pos].mode = constraint->mode;
3447 /* transform inputs */
3448 for(i = 0; i < arity; ++i) {
3449 const ir_asm_constraint *constraint = &in_constraints[i];
3450 unsigned pos = constraint->pos;
3451 ir_node *pred = get_irn_n(node, i);
3452 ir_node *transformed;
3454 assert(pos < reg_map_size);
3455 register_map[pos].use_input = 1;
3456 register_map[pos].valid = 1;
3457 register_map[pos].memory = is_memory_op(constraint);
3458 register_map[pos].inout_pos = i;
3459 register_map[pos].mode = constraint->mode;
3464 transformed = be_transform_node(pred);
3465 in[i] = transformed;
3468 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3469 get_ASM_text(node), register_map);
3471 set_ia32_out_req_all(res, out_reg_reqs);
3472 set_ia32_in_req_all(res, in_reg_reqs);
3474 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3479 /********************************************
3482 * | |__ ___ _ __ ___ __| | ___ ___
3483 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3484 * | |_) | __/ | | | (_) | (_| | __/\__ \
3485 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3487 ********************************************/
3490 * Transforms a FrameAddr into an ia32 Add.
3492 static ir_node *gen_be_FrameAddr(ir_node *node) {
3493 ir_node *block = be_transform_node(get_nodes_block(node));
3494 ir_node *op = be_get_FrameAddr_frame(node);
3495 ir_node *new_op = be_transform_node(op);
3496 ir_graph *irg = current_ir_graph;
3497 dbg_info *dbgi = get_irn_dbg_info(node);
3498 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3501 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3502 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3503 set_ia32_use_frame(res);
3505 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3511 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3513 static ir_node *gen_be_Return(ir_node *node) {
3514 ir_graph *irg = current_ir_graph;
3515 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3516 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3517 ir_entity *ent = get_irg_entity(irg);
3518 ir_type *tp = get_entity_type(ent);
3523 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3524 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3527 int pn_ret_val, pn_ret_mem, arity, i;
3529 assert(ret_val != NULL);
3530 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3531 return be_duplicate_node(node);
3534 res_type = get_method_res_type(tp, 0);
3536 if (! is_Primitive_type(res_type)) {
3537 return be_duplicate_node(node);
3540 mode = get_type_mode(res_type);
3541 if (! mode_is_float(mode)) {
3542 return be_duplicate_node(node);
3545 assert(get_method_n_ress(tp) == 1);
3547 pn_ret_val = get_Proj_proj(ret_val);
3548 pn_ret_mem = get_Proj_proj(ret_mem);
3550 /* get the Barrier */
3551 barrier = get_Proj_pred(ret_val);
3553 /* get result input of the Barrier */
3554 ret_val = get_irn_n(barrier, pn_ret_val);
3555 new_ret_val = be_transform_node(ret_val);
3557 /* get memory input of the Barrier */
3558 ret_mem = get_irn_n(barrier, pn_ret_mem);
3559 new_ret_mem = be_transform_node(ret_mem);
3561 frame = get_irg_frame(irg);
3563 dbgi = get_irn_dbg_info(barrier);
3564 block = be_transform_node(get_nodes_block(barrier));
3566 noreg = ia32_new_NoReg_gp(env_cg);
3568 /* store xmm0 onto stack */
3569 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3570 new_ret_mem, new_ret_val);
3571 set_ia32_ls_mode(sse_store, mode);
3572 set_ia32_op_type(sse_store, ia32_AddrModeD);
3573 set_ia32_use_frame(sse_store);
3575 /* load into x87 register */
3576 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3577 set_ia32_op_type(fld, ia32_AddrModeS);
3578 set_ia32_use_frame(fld);
3580 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3581 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3583 /* create a new barrier */
3584 arity = get_irn_arity(barrier);
3585 in = alloca(arity * sizeof(in[0]));
3586 for (i = 0; i < arity; ++i) {
3589 if (i == pn_ret_val) {
3591 } else if (i == pn_ret_mem) {
3594 ir_node *in = get_irn_n(barrier, i);
3595 new_in = be_transform_node(in);
3600 new_barrier = new_ir_node(dbgi, irg, block,
3601 get_irn_op(barrier), get_irn_mode(barrier),
3603 copy_node_attr(barrier, new_barrier);
3604 be_duplicate_deps(barrier, new_barrier);
3605 be_set_transformed_node(barrier, new_barrier);
3606 mark_irn_visited(barrier);
3608 /* transform normally */
3609 return be_duplicate_node(node);
3613 * Transform a be_AddSP into an ia32_SubSP.
3615 static ir_node *gen_be_AddSP(ir_node *node)
3617 ir_node *src_block = get_nodes_block(node);
3618 ir_node *new_block = be_transform_node(src_block);
3619 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3620 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3621 ir_graph *irg = current_ir_graph;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3624 ia32_address_mode_t am;
3625 ia32_address_t *addr = &am.addr;
3626 match_flags_t flags = 0;
3628 match_arguments(&am, src_block, sp, sz, flags);
3630 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3631 addr->mem, am.new_op1, am.new_op2);
3632 set_am_attributes(new_node, &am);
3633 /* we can't use source address mode anymore when using immediates */
3634 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3635 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3636 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3638 new_node = fix_mem_proj(new_node, &am);
3644 * Transform a be_SubSP into an ia32_AddSP
3646 static ir_node *gen_be_SubSP(ir_node *node)
3648 ir_node *src_block = get_nodes_block(node);
3649 ir_node *new_block = be_transform_node(src_block);
3650 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3651 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3652 ir_graph *irg = current_ir_graph;
3653 dbg_info *dbgi = get_irn_dbg_info(node);
3655 ia32_address_mode_t am;
3656 ia32_address_t *addr = &am.addr;
3657 match_flags_t flags = 0;
3659 match_arguments(&am, src_block, sp, sz, flags);
3661 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3662 addr->mem, am.new_op1, am.new_op2);
3663 set_am_attributes(new_node, &am);
3664 /* we can't use source address mode anymore when using immediates */
3665 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3666 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3667 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3669 new_node = fix_mem_proj(new_node, &am);
3675 * This function just sets the register for the Unknown node
3676 * as this is not done during register allocation because Unknown
3677 * is an "ignore" node.
3679 static ir_node *gen_Unknown(ir_node *node) {
3680 ir_mode *mode = get_irn_mode(node);
3682 if (mode_is_float(mode)) {
3683 if (USE_SSE2(env_cg)) {
3684 return ia32_new_Unknown_xmm(env_cg);
3686 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3687 ir_graph *irg = current_ir_graph;
3688 dbg_info *dbgi = get_irn_dbg_info(node);
3689 ir_node *block = get_irg_start_block(irg);
3690 return new_rd_ia32_vfldz(dbgi, irg, block);
3692 } else if (mode_needs_gp_reg(mode)) {
3693 return ia32_new_Unknown_gp(env_cg);
3695 assert(0 && "unsupported Unknown-Mode");
3702 * Change some phi modes
3704 static ir_node *gen_Phi(ir_node *node) {
3705 ir_node *block = be_transform_node(get_nodes_block(node));
3706 ir_graph *irg = current_ir_graph;
3707 dbg_info *dbgi = get_irn_dbg_info(node);
3708 ir_mode *mode = get_irn_mode(node);
3711 if(mode_needs_gp_reg(mode)) {
3712 /* we shouldn't have any 64bit stuff around anymore */
3713 assert(get_mode_size_bits(mode) <= 32);
3714 /* all integer operations are on 32bit registers now */
3716 } else if(mode_is_float(mode)) {
3717 if (USE_SSE2(env_cg)) {
3724 /* phi nodes allow loops, so we use the old arguments for now
3725 * and fix this later */
3726 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3727 get_irn_in(node) + 1);
3728 copy_node_attr(node, phi);
3729 be_duplicate_deps(node, phi);
3731 be_set_transformed_node(node, phi);
3732 be_enqueue_preds(node);
3740 static ir_node *gen_IJmp(ir_node *node)
3742 ir_node *block = get_nodes_block(node);
3743 ir_node *new_block = be_transform_node(block);
3744 ir_graph *irg = current_ir_graph;
3745 dbg_info *dbgi = get_irn_dbg_info(node);
3746 ir_node *op = get_IJmp_target(node);
3748 ia32_address_mode_t am;
3749 ia32_address_t *addr = &am.addr;
3750 match_flags_t flags;
3752 flags = match_force_32bit_op | match_no_immediate;
3754 match_arguments(&am, block, NULL, op, flags);
3756 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3757 addr->mem, am.new_op2);
3758 set_am_attributes(new_node, &am);
3759 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3761 new_node = fix_mem_proj(new_node, &am);
3767 /**********************************************************************
3770 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3771 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3772 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3773 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3775 **********************************************************************/
3777 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3779 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3782 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3783 ir_node *val, ir_node *mem);
3786 * Transforms a lowered Load into a "real" one.
3788 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3790 ir_node *block = be_transform_node(get_nodes_block(node));
3791 ir_node *ptr = get_irn_n(node, 0);
3792 ir_node *new_ptr = be_transform_node(ptr);
3793 ir_node *mem = get_irn_n(node, 1);
3794 ir_node *new_mem = be_transform_node(mem);
3795 ir_graph *irg = current_ir_graph;
3796 dbg_info *dbgi = get_irn_dbg_info(node);
3797 ir_mode *mode = get_ia32_ls_mode(node);
3798 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3801 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3803 set_ia32_op_type(new_op, ia32_AddrModeS);
3804 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3805 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3806 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3807 if (is_ia32_am_sc_sign(node))
3808 set_ia32_am_sc_sign(new_op);
3809 set_ia32_ls_mode(new_op, mode);
3810 if (is_ia32_use_frame(node)) {
3811 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3812 set_ia32_use_frame(new_op);
3815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3821 * Transforms a lowered Store into a "real" one.
3823 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3825 ir_node *block = be_transform_node(get_nodes_block(node));
3826 ir_node *ptr = get_irn_n(node, 0);
3827 ir_node *new_ptr = be_transform_node(ptr);
3828 ir_node *val = get_irn_n(node, 1);
3829 ir_node *new_val = be_transform_node(val);
3830 ir_node *mem = get_irn_n(node, 2);
3831 ir_node *new_mem = be_transform_node(mem);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3835 ir_mode *mode = get_ia32_ls_mode(node);
3839 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3841 am_offs = get_ia32_am_offs_int(node);
3842 add_ia32_am_offs_int(new_op, am_offs);
3844 set_ia32_op_type(new_op, ia32_AddrModeD);
3845 set_ia32_ls_mode(new_op, mode);
3846 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3847 set_ia32_use_frame(new_op);
3849 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3856 * Transforms an ia32_l_XXX into a "real" XXX node
3858 * @param node The node to transform
3859 * @return the created ia32 XXX node
3861 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3862 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3863 return gen_shift_binop(node, get_irn_n(node, 0), \
3864 get_irn_n(node, 1), new_rd_ia32_##op); \
3867 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3868 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3869 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3871 static ir_node *gen_ia32_l_Add(ir_node *node) {
3872 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3873 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3874 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3876 if(is_Proj(lowered)) {
3877 lowered = get_Proj_pred(lowered);
3879 assert(is_ia32_Add(lowered));
3880 set_irn_mode(lowered, mode_T);
3886 static ir_node *gen_ia32_l_Adc(ir_node *node)
3888 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3892 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3894 * @param node The node to transform
3895 * @return the created ia32 Neg node
3897 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3898 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3902 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3904 * @param node The node to transform
3905 * @return the created ia32 vfild node
3907 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3908 return gen_lowered_Load(node, new_rd_ia32_vfild);
3912 * Transforms an ia32_l_Load into a "real" ia32_Load node
3914 * @param node The node to transform
3915 * @return the created ia32 Load node
3917 static ir_node *gen_ia32_l_Load(ir_node *node) {
3918 return gen_lowered_Load(node, new_rd_ia32_Load);
3922 * Transforms an ia32_l_Store into a "real" ia32_Store node
3924 * @param node The node to transform
3925 * @return the created ia32 Store node
3927 static ir_node *gen_ia32_l_Store(ir_node *node) {
3928 return gen_lowered_Store(node, new_rd_ia32_Store);
3932 * Transforms a l_vfist into a "real" vfist node.
3934 * @param node The node to transform
3935 * @return the created ia32 vfist node
3937 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3938 ir_node *block = be_transform_node(get_nodes_block(node));
3939 ir_node *ptr = get_irn_n(node, 0);
3940 ir_node *new_ptr = be_transform_node(ptr);
3941 ir_node *val = get_irn_n(node, 1);
3942 ir_node *new_val = be_transform_node(val);
3943 ir_node *mem = get_irn_n(node, 2);
3944 ir_node *new_mem = be_transform_node(mem);
3945 ir_graph *irg = current_ir_graph;
3946 dbg_info *dbgi = get_irn_dbg_info(node);
3947 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3948 ir_mode *mode = get_ia32_ls_mode(node);
3949 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3953 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3954 new_val, trunc_mode);
3956 am_offs = get_ia32_am_offs_int(node);
3957 add_ia32_am_offs_int(new_op, am_offs);
3959 set_ia32_op_type(new_op, ia32_AddrModeD);
3960 set_ia32_ls_mode(new_op, mode);
3961 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3962 set_ia32_use_frame(new_op);
3964 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3970 * Transforms a l_MulS into a "real" MulS node.
3972 * @return the created ia32 Mul node
3974 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3975 ir_node *left = get_binop_left(node);
3976 ir_node *right = get_binop_right(node);
3978 return gen_binop(node, left, right, new_rd_ia32_Mul,
3979 match_commutative | match_no_immediate);
3983 * Transforms a l_IMulS into a "real" IMul1OPS node.
3985 * @return the created ia32 IMul1OP node
3987 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3988 ir_node *left = get_binop_left(node);
3989 ir_node *right = get_binop_right(node);
3991 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3992 match_commutative | match_no_immediate);
3995 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3996 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3997 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3998 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
4000 if(is_Proj(lowered)) {
4001 lowered = get_Proj_pred(lowered);
4003 assert(is_ia32_Sub(lowered));
4004 set_irn_mode(lowered, mode_T);
4010 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4011 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
4015 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4016 * op1 - target to be shifted
4017 * op2 - contains bits to be shifted into target
4019 * Only op3 can be an immediate.
4021 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
4022 ir_node *op2, ir_node *count)
4024 ir_node *block = be_transform_node(get_nodes_block(node));
4025 ir_node *new_op = NULL;
4026 ir_graph *irg = current_ir_graph;
4027 dbg_info *dbgi = get_irn_dbg_info(node);
4028 ir_node *new_op1 = be_transform_node(op1);
4029 ir_node *new_op2 = be_transform_node(op2);
4030 ir_node *new_count = create_immediate_or_transform(count, 'I');
4032 /* TODO proper AM support */
4034 if (is_ia32_l_ShlD(node))
4035 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
4037 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
4039 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4044 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
4045 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4046 get_irn_n(node, 1), get_irn_n(node, 2));
4049 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
4050 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
4051 get_irn_n(node, 1), get_irn_n(node, 2));
4055 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4057 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4058 ir_node *block = be_transform_node(get_nodes_block(node));
4059 ir_node *val = get_irn_n(node, 1);
4060 ir_node *new_val = be_transform_node(val);
4061 ia32_code_gen_t *cg = env_cg;
4062 ir_node *res = NULL;
4063 ir_graph *irg = current_ir_graph;
4065 ir_node *noreg, *new_ptr, *new_mem;
4072 mem = get_irn_n(node, 2);
4073 new_mem = be_transform_node(mem);
4074 ptr = get_irn_n(node, 0);
4075 new_ptr = be_transform_node(ptr);
4076 noreg = ia32_new_NoReg_gp(cg);
4077 dbgi = get_irn_dbg_info(node);
4079 /* Store x87 -> MEM */
4080 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4081 get_ia32_ls_mode(node));
4082 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4083 set_ia32_use_frame(res);
4084 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4085 set_ia32_op_type(res, ia32_AddrModeD);
4087 /* Load MEM -> SSE */
4088 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4089 get_ia32_ls_mode(node));
4090 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4091 set_ia32_use_frame(res);
4092 set_ia32_op_type(res, ia32_AddrModeS);
4093 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4099 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4101 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4102 ir_node *block = be_transform_node(get_nodes_block(node));
4103 ir_node *val = get_irn_n(node, 1);
4104 ir_node *new_val = be_transform_node(val);
4105 ia32_code_gen_t *cg = env_cg;
4106 ir_graph *irg = current_ir_graph;
4107 ir_node *res = NULL;
4108 ir_entity *fent = get_ia32_frame_ent(node);
4109 ir_mode *lsmode = get_ia32_ls_mode(node);
4111 ir_node *noreg, *new_ptr, *new_mem;
4115 if (! USE_SSE2(cg)) {
4116 /* SSE unit is not used -> skip this node. */
4120 ptr = get_irn_n(node, 0);
4121 new_ptr = be_transform_node(ptr);
4122 mem = get_irn_n(node, 2);
4123 new_mem = be_transform_node(mem);
4124 noreg = ia32_new_NoReg_gp(cg);
4125 dbgi = get_irn_dbg_info(node);
4127 /* Store SSE -> MEM */
4128 if (is_ia32_xLoad(skip_Proj(new_val))) {
4129 ir_node *ld = skip_Proj(new_val);
4131 /* we can vfld the value directly into the fpu */
4132 fent = get_ia32_frame_ent(ld);
4133 ptr = get_irn_n(ld, 0);
4134 offs = get_ia32_am_offs_int(ld);
4136 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4138 set_ia32_frame_ent(res, fent);
4139 set_ia32_use_frame(res);
4140 set_ia32_ls_mode(res, lsmode);
4141 set_ia32_op_type(res, ia32_AddrModeD);
4145 /* Load MEM -> x87 */
4146 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4147 set_ia32_frame_ent(res, fent);
4148 set_ia32_use_frame(res);
4149 add_ia32_am_offs_int(res, offs);
4150 set_ia32_op_type(res, ia32_AddrModeS);
4151 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4156 /*********************************************************
4159 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4160 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4161 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4162 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4164 *********************************************************/
4167 * the BAD transformer.
4169 static ir_node *bad_transform(ir_node *node) {
4170 panic("No transform function for %+F available.\n", node);
4175 * Transform the Projs of an AddSP.
4177 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4178 ir_node *block = be_transform_node(get_nodes_block(node));
4179 ir_node *pred = get_Proj_pred(node);
4180 ir_node *new_pred = be_transform_node(pred);
4181 ir_graph *irg = current_ir_graph;
4182 dbg_info *dbgi = get_irn_dbg_info(node);
4183 long proj = get_Proj_proj(node);
4185 if (proj == pn_be_AddSP_sp) {
4186 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4187 pn_ia32_SubSP_stack);
4188 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4190 } else if(proj == pn_be_AddSP_res) {
4191 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4192 pn_ia32_SubSP_addr);
4193 } else if (proj == pn_be_AddSP_M) {
4194 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4198 return new_rd_Unknown(irg, get_irn_mode(node));
4202 * Transform the Projs of a SubSP.
4204 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4205 ir_node *block = be_transform_node(get_nodes_block(node));
4206 ir_node *pred = get_Proj_pred(node);
4207 ir_node *new_pred = be_transform_node(pred);
4208 ir_graph *irg = current_ir_graph;
4209 dbg_info *dbgi = get_irn_dbg_info(node);
4210 long proj = get_Proj_proj(node);
4212 if (proj == pn_be_SubSP_sp) {
4213 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4214 pn_ia32_AddSP_stack);
4215 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4217 } else if (proj == pn_be_SubSP_M) {
4218 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4222 return new_rd_Unknown(irg, get_irn_mode(node));
4226 * Transform and renumber the Projs from a Load.
4228 static ir_node *gen_Proj_Load(ir_node *node) {
4230 ir_node *block = be_transform_node(get_nodes_block(node));
4231 ir_node *pred = get_Proj_pred(node);
4232 ir_graph *irg = current_ir_graph;
4233 dbg_info *dbgi = get_irn_dbg_info(node);
4234 long proj = get_Proj_proj(node);
4237 /* loads might be part of source address mode matches, so we don't
4238 transform the ProjMs yet (with the exception of loads whose result is
4241 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4244 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4246 /* this is needed, because sometimes we have loops that are only
4247 reachable through the ProjM */
4248 be_enqueue_preds(node);
4249 /* do it in 2 steps, to silence firm verifier */
4250 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4251 set_Proj_proj(res, pn_ia32_Load_M);
4255 /* renumber the proj */
4256 new_pred = be_transform_node(pred);
4257 if (is_ia32_Load(new_pred)) {
4258 if (proj == pn_Load_res) {
4259 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4261 } else if (proj == pn_Load_M) {
4262 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4265 } else if(is_ia32_Conv_I2I(new_pred)) {
4266 set_irn_mode(new_pred, mode_T);
4267 if (proj == pn_Load_res) {
4268 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4269 } else if (proj == pn_Load_M) {
4270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4272 } else if (is_ia32_xLoad(new_pred)) {
4273 if (proj == pn_Load_res) {
4274 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4276 } else if (proj == pn_Load_M) {
4277 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4280 } else if (is_ia32_vfld(new_pred)) {
4281 if (proj == pn_Load_res) {
4282 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4284 } else if (proj == pn_Load_M) {
4285 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4289 /* can happen for ProJMs when source address mode happened for the
4292 /* however it should not be the result proj, as that would mean the
4293 load had multiple users and should not have been used for
4295 if(proj != pn_Load_M) {
4296 panic("internal error: transformed node not a Load");
4298 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4302 return new_rd_Unknown(irg, get_irn_mode(node));
4306 * Transform and renumber the Projs from a DivMod like instruction.
4308 static ir_node *gen_Proj_DivMod(ir_node *node) {
4309 ir_node *block = be_transform_node(get_nodes_block(node));
4310 ir_node *pred = get_Proj_pred(node);
4311 ir_node *new_pred = be_transform_node(pred);
4312 ir_graph *irg = current_ir_graph;
4313 dbg_info *dbgi = get_irn_dbg_info(node);
4314 ir_mode *mode = get_irn_mode(node);
4315 long proj = get_Proj_proj(node);
4317 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4319 switch (get_irn_opcode(pred)) {
4323 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4325 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4333 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4335 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4343 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4344 case pn_DivMod_res_div:
4345 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4346 case pn_DivMod_res_mod:
4347 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4357 return new_rd_Unknown(irg, mode);
4361 * Transform and renumber the Projs from a CopyB.
4363 static ir_node *gen_Proj_CopyB(ir_node *node) {
4364 ir_node *block = be_transform_node(get_nodes_block(node));
4365 ir_node *pred = get_Proj_pred(node);
4366 ir_node *new_pred = be_transform_node(pred);
4367 ir_graph *irg = current_ir_graph;
4368 dbg_info *dbgi = get_irn_dbg_info(node);
4369 ir_mode *mode = get_irn_mode(node);
4370 long proj = get_Proj_proj(node);
4373 case pn_CopyB_M_regular:
4374 if (is_ia32_CopyB_i(new_pred)) {
4375 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4376 } else if (is_ia32_CopyB(new_pred)) {
4377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4385 return new_rd_Unknown(irg, mode);
4389 * Transform and renumber the Projs from a Quot.
4391 static ir_node *gen_Proj_Quot(ir_node *node) {
4392 ir_node *block = be_transform_node(get_nodes_block(node));
4393 ir_node *pred = get_Proj_pred(node);
4394 ir_node *new_pred = be_transform_node(pred);
4395 ir_graph *irg = current_ir_graph;
4396 dbg_info *dbgi = get_irn_dbg_info(node);
4397 ir_mode *mode = get_irn_mode(node);
4398 long proj = get_Proj_proj(node);
4402 if (is_ia32_xDiv(new_pred)) {
4403 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4404 } else if (is_ia32_vfdiv(new_pred)) {
4405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4409 if (is_ia32_xDiv(new_pred)) {
4410 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4411 } else if (is_ia32_vfdiv(new_pred)) {
4412 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4420 return new_rd_Unknown(irg, mode);
4424 * Transform the Thread Local Storage Proj.
4426 static ir_node *gen_Proj_tls(ir_node *node) {
4427 ir_node *block = be_transform_node(get_nodes_block(node));
4428 ir_graph *irg = current_ir_graph;
4429 dbg_info *dbgi = NULL;
4430 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4435 static ir_node *gen_be_Call(ir_node *node) {
4436 ir_node *res = be_duplicate_node(node);
4437 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4442 static ir_node *gen_be_IncSP(ir_node *node) {
4443 ir_node *res = be_duplicate_node(node);
4444 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4450 * Transform the Projs from a be_Call.
4452 static ir_node *gen_Proj_be_Call(ir_node *node) {
4453 ir_node *block = be_transform_node(get_nodes_block(node));
4454 ir_node *call = get_Proj_pred(node);
4455 ir_node *new_call = be_transform_node(call);
4456 ir_graph *irg = current_ir_graph;
4457 dbg_info *dbgi = get_irn_dbg_info(node);
4458 ir_type *method_type = be_Call_get_type(call);
4459 int n_res = get_method_n_ress(method_type);
4460 long proj = get_Proj_proj(node);
4461 ir_mode *mode = get_irn_mode(node);
4463 const arch_register_class_t *cls;
4465 /* The following is kinda tricky: If we're using SSE, then we have to
4466 * move the result value of the call in floating point registers to an
4467 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4468 * after the call, we have to make sure to correctly make the
4469 * MemProj and the result Proj use these 2 nodes
4471 if (proj == pn_be_Call_M_regular) {
4472 // get new node for result, are we doing the sse load/store hack?
4473 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4474 ir_node *call_res_new;
4475 ir_node *call_res_pred = NULL;
4477 if (call_res != NULL) {
4478 call_res_new = be_transform_node(call_res);
4479 call_res_pred = get_Proj_pred(call_res_new);
4482 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4483 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4484 pn_be_Call_M_regular);
4486 assert(is_ia32_xLoad(call_res_pred));
4487 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4491 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4492 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4493 && USE_SSE2(env_cg)) {
4495 ir_node *frame = get_irg_frame(irg);
4496 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4498 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4501 /* in case there is no memory output: create one to serialize the copy
4503 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4504 pn_be_Call_M_regular);
4505 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4506 pn_be_Call_first_res);
4508 /* store st(0) onto stack */
4509 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4511 set_ia32_op_type(fstp, ia32_AddrModeD);
4512 set_ia32_use_frame(fstp);
4514 /* load into SSE register */
4515 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4517 set_ia32_op_type(sse_load, ia32_AddrModeS);
4518 set_ia32_use_frame(sse_load);
4520 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4526 /* transform call modes */
4527 if (mode_is_data(mode)) {
4528 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4532 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4536 * Transform the Projs from a Cmp.
4538 static ir_node *gen_Proj_Cmp(ir_node *node)
4540 /* normally Cmps are processed when looking at Cond nodes, but this case
4541 * can happen in complicated Psi conditions */
4542 dbg_info *dbgi = get_irn_dbg_info(node);
4543 ir_node *block = get_nodes_block(node);
4544 ir_node *new_block = be_transform_node(block);
4545 ir_node *cmp = get_Proj_pred(node);
4546 ir_node *new_cmp = be_transform_node(cmp);
4547 long pnc = get_Proj_proj(node);
4550 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4556 * Transform and potentially renumber Proj nodes.
4558 static ir_node *gen_Proj(ir_node *node) {
4559 ir_graph *irg = current_ir_graph;
4560 dbg_info *dbgi = get_irn_dbg_info(node);
4561 ir_node *pred = get_Proj_pred(node);
4562 long proj = get_Proj_proj(node);
4564 if (is_Store(pred)) {
4565 if (proj == pn_Store_M) {
4566 return be_transform_node(pred);
4569 return new_r_Bad(irg);
4571 } else if (is_Load(pred)) {
4572 return gen_Proj_Load(node);
4573 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4574 return gen_Proj_DivMod(node);
4575 } else if (is_CopyB(pred)) {
4576 return gen_Proj_CopyB(node);
4577 } else if (is_Quot(pred)) {
4578 return gen_Proj_Quot(node);
4579 } else if (be_is_SubSP(pred)) {
4580 return gen_Proj_be_SubSP(node);
4581 } else if (be_is_AddSP(pred)) {
4582 return gen_Proj_be_AddSP(node);
4583 } else if (be_is_Call(pred)) {
4584 return gen_Proj_be_Call(node);
4585 } else if (is_Cmp(pred)) {
4586 return gen_Proj_Cmp(node);
4587 } else if (get_irn_op(pred) == op_Start) {
4588 if (proj == pn_Start_X_initial_exec) {
4589 ir_node *block = get_nodes_block(pred);
4592 /* we exchange the ProjX with a jump */
4593 block = be_transform_node(block);
4594 jump = new_rd_Jmp(dbgi, irg, block);
4597 if (node == be_get_old_anchor(anchor_tls)) {
4598 return gen_Proj_tls(node);
4601 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4605 ir_node *new_pred = be_transform_node(pred);
4606 ir_node *block = be_transform_node(get_nodes_block(node));
4607 ir_mode *mode = get_irn_mode(node);
4608 if (mode_needs_gp_reg(mode)) {
4609 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4610 get_Proj_proj(node));
4611 #ifdef DEBUG_libfirm
4612 new_proj->node_nr = node->node_nr;
4618 return be_duplicate_node(node);
4622 * Enters all transform functions into the generic pointer
4624 static void register_transformers(void)
4628 /* first clear the generic function pointer for all ops */
4629 clear_irp_opcodes_generic_func();
4631 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4632 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4670 /* transform ops from intrinsic lowering */
4687 GEN(ia32_l_X87toSSE);
4688 GEN(ia32_l_SSEtoX87);
4694 /* we should never see these nodes */
4709 /* handle generic backend nodes */
4718 op_Mulh = get_op_Mulh();
4727 * Pre-transform all unknown and noreg nodes.
4729 static void ia32_pretransform_node(void *arch_cg) {
4730 ia32_code_gen_t *cg = arch_cg;
4732 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4733 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4734 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4735 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4736 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4737 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4742 * Walker, checks if all ia32 nodes producing more than one result have
4743 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4745 static void add_missing_keep_walker(ir_node *node, void *data)
4748 unsigned found_projs = 0;
4749 const ir_edge_t *edge;
4750 ir_mode *mode = get_irn_mode(node);
4755 if(!is_ia32_irn(node))
4758 n_outs = get_ia32_n_res(node);
4761 if(is_ia32_SwitchJmp(node))
4764 assert(n_outs < (int) sizeof(unsigned) * 8);
4765 foreach_out_edge(node, edge) {
4766 ir_node *proj = get_edge_src_irn(edge);
4767 int pn = get_Proj_proj(proj);
4769 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4770 found_projs |= 1 << pn;
4774 /* are keeps missing? */
4776 for(i = 0; i < n_outs; ++i) {
4779 const arch_register_req_t *req;
4780 const arch_register_class_t *class;
4782 if(found_projs & (1 << i)) {
4786 req = get_ia32_out_req(node, i);
4791 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4795 block = get_nodes_block(node);
4796 in[0] = new_r_Proj(current_ir_graph, block, node,
4797 arch_register_class_mode(class), i);
4798 if(last_keep != NULL) {
4799 be_Keep_add_node(last_keep, class, in[0]);
4801 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4802 if(sched_is_scheduled(node)) {
4803 sched_add_after(node, last_keep);
4810 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4813 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4815 ir_graph *irg = be_get_birg_irg(cg->birg);
4816 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4819 /* do the transformation */
4820 void ia32_transform_graph(ia32_code_gen_t *cg) {
4822 ir_graph *irg = cg->irg;
4824 /* TODO: look at cpu and fill transform config in with that... */
4825 transform_config.use_incdec = 1;
4826 transform_config.use_sse2 = 0;
4827 transform_config.use_ffreep = 0;
4828 transform_config.use_ftst = 0;
4829 transform_config.use_femms = 0;
4830 transform_config.use_fucomi = 1;
4831 transform_config.use_cmov = 1;
4833 register_transformers();
4835 initial_fpcw = NULL;
4837 heights = heights_new(irg);
4838 calculate_non_address_mode_nodes(irg);
4840 /* the transform phase is not safe for CSE (yet) because several nodes get
4841 * attributes set after their creation */
4842 cse_last = get_opt_cse();
4845 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4847 set_opt_cse(cse_last);
4849 free_non_address_mode_nodes();
4850 heights_free(heights);
4854 void ia32_init_transform(void)
4856 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");