2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *new_block,
127 * Return true if a mode can be stored in the GP register set
129 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
130 if(mode == mode_fpcw)
132 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
136 * Returns 1 if irn is a Const representing 0, 0 otherwise
138 static INLINE int is_ia32_Const_0(ir_node *irn) {
139 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
140 && tarval_is_null(get_ia32_Immop_tarval(irn));
144 * Returns 1 if irn is a Const representing 1, 0 otherwise
146 static INLINE int is_ia32_Const_1(ir_node *irn) {
147 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
148 && tarval_is_one(get_ia32_Immop_tarval(irn));
152 * Collects all Projs of a node into the node array. Index is the projnum.
153 * BEWARE: The caller has to assure the appropriate array size!
155 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
156 const ir_edge_t *edge;
157 assert(get_irn_mode(irn) == mode_T && "need mode_T");
159 memset(projs, 0, size * sizeof(projs[0]));
161 foreach_out_edge(irn, edge) {
162 ir_node *proj = get_edge_src_irn(edge);
163 int proj_proj = get_Proj_proj(proj);
164 assert(proj_proj < size);
165 projs[proj_proj] = proj;
170 * Renumbers the proj having pn_old in the array tp pn_new
171 * and removes the proj from the array.
173 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
174 fprintf(stderr, "Warning: renumber_Proj used!\n");
176 set_Proj_proj(projs[pn_old], pn_new);
177 projs[pn_old] = NULL;
182 * creates a unique ident by adding a number to a tag
184 * @param tag the tag string, must contain a %d if a number
187 static ident *unique_id(const char *tag)
189 static unsigned id = 0;
192 snprintf(str, sizeof(str), tag, ++id);
193 return new_id_from_str(str);
197 * Get a primitive type for a mode.
199 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
201 pmap_entry *e = pmap_find(types, mode);
206 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
207 res = new_type_primitive(new_id_from_str(buf), mode);
208 set_type_alignment_bytes(res, 16);
209 pmap_insert(types, mode, res);
217 * Get an entity that is initialized with a tarval
219 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
221 tarval *tv = get_Const_tarval(cnst);
222 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
227 ir_mode *mode = get_irn_mode(cnst);
228 ir_type *tp = get_Const_type(cnst);
229 if (tp == firm_unknown_type)
230 tp = get_prim_type(cg->isa->types, mode);
232 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
234 set_entity_ld_ident(res, get_entity_ident(res));
235 set_entity_visibility(res, visibility_local);
236 set_entity_variability(res, variability_constant);
237 set_entity_allocation(res, allocation_static);
239 /* we create a new entity here: It's initialization must resist on the
241 rem = current_ir_graph;
242 current_ir_graph = get_const_code_irg();
243 set_atomic_ent_value(res, new_Const_type(tv, tp));
244 current_ir_graph = rem;
246 pmap_insert(cg->isa->tv_ent, tv, res);
254 static int is_Const_0(ir_node *node) {
258 return classify_Const(node) == CNST_NULL;
261 static int is_Const_1(ir_node *node) {
265 return classify_Const(node) == CNST_ONE;
269 * Transforms a Const.
271 static ir_node *gen_Const(ir_node *node) {
272 ir_graph *irg = current_ir_graph;
273 ir_node *old_block = get_nodes_block(node);
274 ir_node *block = be_transform_node(old_block);
275 dbg_info *dbgi = get_irn_dbg_info(node);
276 ir_mode *mode = get_irn_mode(node);
278 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env_cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env_cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
313 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet.
322 * So add a dependency to the initial frame pointer calculation to
323 * avoid that situation.
325 if (get_irg_start_block(irg) == block) {
326 add_irn_dep(load, get_irg_frame(irg));
329 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
332 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
345 return new_r_Bad(irg);
349 * Transforms a SymConst.
351 static ir_node *gen_SymConst(ir_node *node) {
352 ir_graph *irg = current_ir_graph;
353 ir_node *old_block = get_nodes_block(node);
354 ir_node *block = be_transform_node(old_block);
355 dbg_info *dbgi = get_irn_dbg_info(node);
356 ir_mode *mode = get_irn_mode(node);
359 if (mode_is_float(mode)) {
360 if (USE_SSE2(env_cg))
361 cnst = new_rd_ia32_xConst(dbgi, irg, block);
363 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
364 //set_ia32_ls_mode(cnst, mode);
365 set_ia32_ls_mode(cnst, mode_E);
367 cnst = new_rd_ia32_Const(dbgi, irg, block);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 set_ia32_Const_attr(cnst, node);
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 /* determine if one operator is an Imm */
451 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
453 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
455 return is_ia32_Cnst(op2) ? op2 : NULL;
459 /* determine if one operator is not an Imm */
460 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
461 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
464 static void fold_immediate(ir_node *node, int in1, int in2) {
468 if (!(env_cg->opt & IA32_OPT_IMMOPS))
471 left = get_irn_n(node, in1);
472 right = get_irn_n(node, in2);
473 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
474 /* we can only set right operand to immediate */
475 if(!is_ia32_commutative(node))
477 /* exchange left/right */
478 set_irn_n(node, in1, right);
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, left);
481 } else if(is_ia32_Cnst(right)) {
482 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
483 copy_ia32_Immop_attr(node, right);
488 clear_ia32_commutative(node);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
490 get_ia32_am_arity(node));
494 * Construct a standard binary operation, set AM and immediate if required.
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
502 construct_binop_func *func, int commutative)
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_graph *irg = current_ir_graph;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
508 ir_node *nomem = new_NoMem();
511 ir_node *new_op1 = be_transform_node(op1);
512 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
513 if (is_ia32_Immediate(new_op2)) {
517 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
518 if (func == new_rd_ia32_IMul) {
519 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
521 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
524 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
526 set_ia32_commutative(new_node);
533 * Construct a standard binary operation, set AM and immediate if required.
535 * @param op1 The first operand
536 * @param op2 The second operand
537 * @param func The node constructor function
538 * @return The constructed ia32 node.
540 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
541 construct_binop_func *func)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *new_op1 = be_transform_node(op1);
545 ir_node *new_op2 = be_transform_node(op2);
546 ir_node *new_node = NULL;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_graph *irg = current_ir_graph;
549 ir_mode *mode = get_irn_mode(node);
550 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
551 ir_node *nomem = new_NoMem();
553 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
555 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
556 if (is_op_commutative(get_irn_op(node))) {
557 set_ia32_commutative(new_node);
559 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
566 static ir_node *get_fpcw(void)
569 if(initial_fpcw != NULL)
572 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
573 &ia32_fp_cw_regs[REG_FPCW]);
574 initial_fpcw = be_transform_node(fpcw);
580 * Construct a standard binary operation, set AM and immediate if required.
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
588 construct_binop_float_func *func)
590 ir_node *block = be_transform_node(get_nodes_block(node));
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *new_op2 = be_transform_node(op2);
593 ir_node *new_node = NULL;
594 dbg_info *dbgi = get_irn_dbg_info(node);
595 ir_graph *irg = current_ir_graph;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
606 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 * Construct a shift/rotate binary operation, sets AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
625 ir_node *new_op = NULL;
626 dbg_info *dbgi = get_irn_dbg_info(node);
627 ir_graph *irg = current_ir_graph;
628 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
629 ir_node *nomem = new_NoMem();
631 assert(! mode_is_float(get_irn_mode(node))
632 && "Shift/Rotate with float not supported");
634 new_op2 = create_immediate_or_transform(op2, 'N');
636 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
639 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
643 set_ia32_emit_cl(new_op);
650 * Construct a standard unary operation, set AM and immediate if required.
652 * @param op The operand
653 * @param func The node constructor function
654 * @return The constructed ia32 node.
656 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
658 ir_node *block = be_transform_node(get_nodes_block(node));
659 ir_node *new_op = be_transform_node(op);
660 ir_node *new_node = NULL;
661 ir_graph *irg = current_ir_graph;
662 dbg_info *dbgi = get_irn_dbg_info(node);
663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
667 DB((dbg, LEVEL_1, "INT unop ..."));
668 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
670 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
676 * Creates an ia32 Add.
678 * @return the created ia32 Add node
680 static ir_node *gen_Add(ir_node *node) {
681 ir_node *block = be_transform_node(get_nodes_block(node));
682 ir_node *op1 = get_Add_left(node);
683 ir_node *new_op1 = be_transform_node(op1);
684 ir_node *op2 = get_Add_right(node);
685 ir_node *new_op2 = be_transform_node(op2);
686 ir_node *new_op = NULL;
687 ir_graph *irg = current_ir_graph;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_mode *mode = get_irn_mode(node);
690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
691 ir_node *nomem = new_NoMem();
692 ir_node *expr_op, *imm_op;
694 /* Check if immediate optimization is on and */
695 /* if it's an operation with immediate. */
696 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
697 expr_op = get_expr_op(new_op1, new_op2);
699 assert((expr_op || imm_op) && "invalid operands");
701 if (mode_is_float(mode)) {
702 if (USE_SSE2(env_cg))
703 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
705 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
710 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
711 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
713 /* No expr_op means, that we have two const - one symconst and */
714 /* one tarval or another symconst - because this case is not */
715 /* covered by constant folding */
716 /* We need to check for: */
717 /* 1) symconst + const -> becomes a LEA */
718 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
719 /* linker doesn't support two symconsts */
721 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
722 /* this is the 2nd case */
723 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
725 set_ia32_am_flavour(new_op, ia32_am_B);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
728 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 } else if (tp1 == ia32_ImmSymConst) {
730 tarval *tv = get_ia32_Immop_tarval(new_op2);
731 long offs = get_tarval_long(tv);
733 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
734 add_irn_dep(new_op, get_irg_frame(irg));
735 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
738 add_ia32_am_offs_int(new_op, offs);
739 set_ia32_am_flavour(new_op, ia32_am_OB);
740 set_ia32_op_type(new_op, ia32_AddrModeS);
741 } else if (tp2 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op1);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
754 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
755 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
756 tarval *restv = tarval_add(tv1, tv2);
758 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
760 new_op = new_rd_ia32_Const(dbgi, irg, block);
761 set_ia32_Const_tarval(new_op, restv);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
769 tarval_classification_t class_tv, class_negtv;
770 tarval *tv = get_ia32_Immop_tarval(imm_op);
772 /* optimize tarvals */
773 class_tv = classify_tarval(tv);
774 class_negtv = classify_tarval(tarval_neg(tv));
776 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
777 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
778 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
781 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
782 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 /* This is a normal add */
791 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
794 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
795 set_ia32_commutative(new_op);
797 fold_immediate(new_op, 2, 3);
799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
805 * Creates an ia32 Mul.
807 * @return the created ia32 Mul node
809 static ir_node *gen_Mul(ir_node *node) {
810 ir_node *op1 = get_Mul_left(node);
811 ir_node *op2 = get_Mul_right(node);
812 ir_mode *mode = get_irn_mode(node);
814 if (mode_is_float(mode)) {
815 if (USE_SSE2(env_cg))
816 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
818 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
822 for the lower 32bit of the result it doesn't matter whether we use
823 signed or unsigned multiplication so we use IMul as it has fewer
826 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
830 * Creates an ia32 Mulh.
831 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
832 * this result while Mul returns the lower 32 bit.
834 * @return the created ia32 Mulh node
836 static ir_node *gen_Mulh(ir_node *node) {
837 ir_node *block = be_transform_node(get_nodes_block(node));
838 ir_node *op1 = get_irn_n(node, 0);
839 ir_node *new_op1 = be_transform_node(op1);
840 ir_node *op2 = get_irn_n(node, 1);
841 ir_node *new_op2 = be_transform_node(op2);
842 ir_graph *irg = current_ir_graph;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
845 ir_mode *mode = get_irn_mode(node);
846 ir_node *proj_EDX, *res;
848 assert(!mode_is_float(mode) && "Mulh with float not supported");
849 if (mode_is_signed(mode)) {
850 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
851 new_op2, new_NoMem());
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 * Creates an ia32 And.
870 * @return The created ia32 And node
872 static ir_node *gen_And(ir_node *node) {
873 ir_node *op1 = get_And_left(node);
874 ir_node *op2 = get_And_right(node);
875 assert(! mode_is_float(get_irn_mode(node)));
877 /* check for zero extension first */
879 tarval *tv = get_Const_tarval(op2);
880 long v = get_tarval_long(tv);
882 if (v == 0xFF || v == 0xFFFF) {
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *block = be_transform_node(get_nodes_block(node));
885 ir_node *new_op = be_transform_node(op1);
895 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
896 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
902 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
908 * Creates an ia32 Or.
910 * @return The created ia32 Or node
912 static ir_node *gen_Or(ir_node *node) {
913 ir_node *op1 = get_Or_left(node);
914 ir_node *op2 = get_Or_right(node);
916 assert (! mode_is_float(get_irn_mode(node)));
917 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
923 * Creates an ia32 Eor.
925 * @return The created ia32 Eor node
927 static ir_node *gen_Eor(ir_node *node) {
928 ir_node *op1 = get_Eor_left(node);
929 ir_node *op2 = get_Eor_right(node);
931 assert(! mode_is_float(get_irn_mode(node)));
932 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
937 * Creates an ia32 Sub.
939 * @return The created ia32 Sub node
941 static ir_node *gen_Sub(ir_node *node) {
942 ir_node *block = be_transform_node(get_nodes_block(node));
943 ir_node *op1 = get_Sub_left(node);
944 ir_node *new_op1 = be_transform_node(op1);
945 ir_node *op2 = get_Sub_right(node);
946 ir_node *new_op2 = be_transform_node(op2);
947 ir_node *new_op = NULL;
948 ir_graph *irg = current_ir_graph;
949 dbg_info *dbgi = get_irn_dbg_info(node);
950 ir_mode *mode = get_irn_mode(node);
951 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
952 ir_node *nomem = new_NoMem();
953 ir_node *expr_op, *imm_op;
955 /* Check if immediate optimization is on and */
956 /* if it's an operation with immediate. */
957 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
958 expr_op = get_expr_op(new_op1, new_op2);
960 assert((expr_op || imm_op) && "invalid operands");
962 if (mode_is_float(mode)) {
963 if (USE_SSE2(env_cg))
964 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
966 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
971 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
972 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
974 /* No expr_op means, that we have two const - one symconst and */
975 /* one tarval or another symconst - because this case is not */
976 /* covered by constant folding */
977 /* We need to check for: */
978 /* 1) symconst - const -> becomes a LEA */
979 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
980 /* linker doesn't support two symconsts */
981 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
982 /* this is the 2nd case */
983 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
984 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
985 set_ia32_am_sc_sign(new_op);
986 set_ia32_am_flavour(new_op, ia32_am_B);
988 DBG_OPT_LEA3(op1, op2, node, new_op);
989 } else if (tp1 == ia32_ImmSymConst) {
990 tarval *tv = get_ia32_Immop_tarval(new_op2);
991 long offs = get_tarval_long(tv);
993 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
994 add_irn_dep(new_op, get_irg_frame(irg));
995 DBG_OPT_LEA3(op1, op2, node, new_op);
997 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
998 add_ia32_am_offs_int(new_op, -offs);
999 set_ia32_am_flavour(new_op, ia32_am_OB);
1000 set_ia32_op_type(new_op, ia32_AddrModeS);
1001 } else if (tp2 == ia32_ImmSymConst) {
1002 tarval *tv = get_ia32_Immop_tarval(new_op1);
1003 long offs = get_tarval_long(tv);
1005 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1006 add_irn_dep(new_op, get_irg_frame(irg));
1007 DBG_OPT_LEA3(op1, op2, node, new_op);
1009 add_ia32_am_offs_int(new_op, offs);
1010 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1011 set_ia32_am_sc_sign(new_op);
1012 set_ia32_am_flavour(new_op, ia32_am_OB);
1013 set_ia32_op_type(new_op, ia32_AddrModeS);
1015 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1016 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1017 tarval *restv = tarval_sub(tv1, tv2);
1019 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1021 new_op = new_rd_ia32_Const(dbgi, irg, block);
1022 set_ia32_Const_tarval(new_op, restv);
1023 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1026 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1028 } else if (imm_op) {
1029 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1030 tarval_classification_t class_tv, class_negtv;
1031 tarval *tv = get_ia32_Immop_tarval(imm_op);
1033 /* optimize tarvals */
1034 class_tv = classify_tarval(tv);
1035 class_negtv = classify_tarval(tarval_neg(tv));
1037 if (class_tv == TV_CLASSIFY_ONE) {
1038 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1039 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1040 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1042 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1043 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1044 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1051 /* This is a normal sub */
1052 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1054 /* set AM support */
1055 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1057 fold_immediate(new_op, 2, 3);
1059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1067 * Generates an ia32 DivMod with additional infrastructure for the
1068 * register allocator if needed.
1070 * @param dividend -no comment- :)
1071 * @param divisor -no comment- :)
1072 * @param dm_flav flavour_Div/Mod/DivMod
1073 * @return The created ia32 DivMod node
1075 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1076 ir_node *divisor, ia32_op_flavour_t dm_flav)
1078 ir_node *block = be_transform_node(get_nodes_block(node));
1079 ir_node *new_dividend = be_transform_node(dividend);
1080 ir_node *new_divisor = be_transform_node(divisor);
1081 ir_graph *irg = current_ir_graph;
1082 dbg_info *dbgi = get_irn_dbg_info(node);
1083 ir_mode *mode = get_irn_mode(node);
1084 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1085 ir_node *res, *proj_div, *proj_mod;
1086 ir_node *sign_extension;
1087 ir_node *mem, *new_mem;
1088 ir_node *projs[pn_DivMod_max];
1091 ia32_collect_Projs(node, projs, pn_DivMod_max);
1093 proj_div = proj_mod = NULL;
1097 mem = get_Div_mem(node);
1098 mode = get_Div_resmode(node);
1099 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1100 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1103 mem = get_Mod_mem(node);
1104 mode = get_Mod_resmode(node);
1105 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1106 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1108 case flavour_DivMod:
1109 mem = get_DivMod_mem(node);
1110 mode = get_DivMod_resmode(node);
1111 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1112 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1113 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1116 panic("invalid divmod flavour!");
1118 new_mem = be_transform_node(mem);
1120 if (mode_is_signed(mode)) {
1121 /* in signed mode, we need to sign extend the dividend */
1122 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1123 add_irn_dep(produceval, get_irg_frame(irg));
1124 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1127 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1128 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1130 add_irn_dep(sign_extension, get_irg_frame(irg));
1133 if (mode_is_signed(mode)) {
1134 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1135 sign_extension, new_divisor, new_mem, dm_flav);
1137 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1138 sign_extension, new_divisor, new_mem, dm_flav);
1141 set_ia32_exc_label(res, has_exc);
1142 set_irn_pinned(res, get_irn_pinned(node));
1143 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1145 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1152 * Wrapper for generate_DivMod. Sets flavour_Mod.
1155 static ir_node *gen_Mod(ir_node *node) {
1156 return generate_DivMod(node, get_Mod_left(node),
1157 get_Mod_right(node), flavour_Mod);
1161 * Wrapper for generate_DivMod. Sets flavour_Div.
1164 static ir_node *gen_Div(ir_node *node) {
1165 return generate_DivMod(node, get_Div_left(node),
1166 get_Div_right(node), flavour_Div);
1170 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1172 static ir_node *gen_DivMod(ir_node *node) {
1173 return generate_DivMod(node, get_DivMod_left(node),
1174 get_DivMod_right(node), flavour_DivMod);
1180 * Creates an ia32 floating Div.
1182 * @return The created ia32 xDiv node
1184 static ir_node *gen_Quot(ir_node *node) {
1185 ir_node *block = be_transform_node(get_nodes_block(node));
1186 ir_node *op1 = get_Quot_left(node);
1187 ir_node *new_op1 = be_transform_node(op1);
1188 ir_node *op2 = get_Quot_right(node);
1189 ir_node *new_op2 = be_transform_node(op2);
1190 ir_graph *irg = current_ir_graph;
1191 dbg_info *dbgi = get_irn_dbg_info(node);
1192 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1193 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1196 if (USE_SSE2(env_cg)) {
1197 ir_mode *mode = get_irn_mode(op1);
1198 if (is_ia32_xConst(new_op2)) {
1199 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1200 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1201 copy_ia32_Immop_attr(new_op, new_op2);
1203 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1204 // Matze: disabled for now, spillslot coalescer fails
1205 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1207 set_ia32_ls_mode(new_op, mode);
1209 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1210 new_op2, nomem, get_fpcw());
1211 // Matze: disabled for now (spillslot coalescer fails)
1212 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1214 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1220 * Creates an ia32 Shl.
1222 * @return The created ia32 Shl node
1224 static ir_node *gen_Shl(ir_node *node) {
1225 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1232 * Creates an ia32 Shr.
1234 * @return The created ia32 Shr node
1236 static ir_node *gen_Shr(ir_node *node) {
1237 return gen_shift_binop(node, get_Shr_left(node),
1238 get_Shr_right(node), new_rd_ia32_Shr);
1244 * Creates an ia32 Sar.
1246 * @return The created ia32 Shrs node
1248 static ir_node *gen_Shrs(ir_node *node) {
1249 ir_node *left = get_Shrs_left(node);
1250 ir_node *right = get_Shrs_right(node);
1251 ir_mode *mode = get_irn_mode(node);
1252 if(is_Const(right) && mode == mode_Is) {
1253 tarval *tv = get_Const_tarval(right);
1254 long val = get_tarval_long(tv);
1256 /* this is a sign extension */
1257 ir_graph *irg = current_ir_graph;
1258 dbg_info *dbgi = get_irn_dbg_info(node);
1259 ir_node *block = be_transform_node(get_nodes_block(node));
1261 ir_node *new_op = be_transform_node(op);
1262 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1263 add_irn_dep(pval, get_irg_frame(irg));
1265 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1269 /* 8 or 16 bit sign extension? */
1270 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1271 ir_node *shl_left = get_Shl_left(left);
1272 ir_node *shl_right = get_Shl_right(left);
1273 if(is_Const(shl_right)) {
1274 tarval *tv1 = get_Const_tarval(right);
1275 tarval *tv2 = get_Const_tarval(shl_right);
1276 if(tv1 == tv2 && tarval_is_long(tv1)) {
1277 long val = get_tarval_long(tv1);
1278 if(val == 16 || val == 24) {
1279 dbg_info *dbgi = get_irn_dbg_info(node);
1280 ir_node *block = be_transform_node(get_nodes_block(node));
1281 ir_node *new_op = be_transform_node(shl_left);
1291 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1293 SET_IA32_ORIG_NODE(res,
1294 ia32_get_old_node_name(env_cg, node));
1303 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1309 * Creates an ia32 RotL.
1311 * @param op1 The first operator
1312 * @param op2 The second operator
1313 * @return The created ia32 RotL node
1315 static ir_node *gen_RotL(ir_node *node,
1316 ir_node *op1, ir_node *op2) {
1317 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1323 * Creates an ia32 RotR.
1324 * NOTE: There is no RotR with immediate because this would always be a RotL
1325 * "imm-mode_size_bits" which can be pre-calculated.
1327 * @param op1 The first operator
1328 * @param op2 The second operator
1329 * @return The created ia32 RotR node
1331 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1333 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1339 * Creates an ia32 RotR or RotL (depending on the found pattern).
1341 * @return The created ia32 RotL or RotR node
1343 static ir_node *gen_Rot(ir_node *node) {
1344 ir_node *rotate = NULL;
1345 ir_node *op1 = get_Rot_left(node);
1346 ir_node *op2 = get_Rot_right(node);
1348 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1349 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1350 that means we can create a RotR instead of an Add and a RotL */
1352 if (get_irn_op(op2) == op_Add) {
1354 ir_node *left = get_Add_left(add);
1355 ir_node *right = get_Add_right(add);
1356 if (is_Const(right)) {
1357 tarval *tv = get_Const_tarval(right);
1358 ir_mode *mode = get_irn_mode(node);
1359 long bits = get_mode_size_bits(mode);
1361 if (get_irn_op(left) == op_Minus &&
1362 tarval_is_long(tv) &&
1363 get_tarval_long(tv) == bits)
1365 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1366 rotate = gen_RotR(node, op1, get_Minus_op(left));
1371 if (rotate == NULL) {
1372 rotate = gen_RotL(node, op1, op2);
1381 * Transforms a Minus node.
1383 * @param op The Minus operand
1384 * @return The created ia32 Minus node
1386 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1387 ir_node *block = be_transform_node(get_nodes_block(node));
1388 ir_graph *irg = current_ir_graph;
1389 dbg_info *dbgi = get_irn_dbg_info(node);
1390 ir_mode *mode = get_irn_mode(node);
1395 if (mode_is_float(mode)) {
1396 ir_node *new_op = be_transform_node(op);
1397 if (USE_SSE2(env_cg)) {
1398 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1399 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1400 ir_node *nomem = new_rd_NoMem(irg);
1402 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1404 size = get_mode_size_bits(mode);
1405 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1407 set_ia32_am_sc(res, ent);
1408 set_ia32_op_type(res, ia32_AddrModeS);
1409 set_ia32_ls_mode(res, mode);
1411 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1414 res = gen_unop(node, op, new_rd_ia32_Neg);
1417 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1423 * Transforms a Minus node.
1425 * @return The created ia32 Minus node
1427 static ir_node *gen_Minus(ir_node *node) {
1428 return gen_Minus_ex(node, get_Minus_op(node));
1431 static ir_node *gen_bin_Not(ir_node *node)
1433 ir_graph *irg = current_ir_graph;
1434 dbg_info *dbgi = get_irn_dbg_info(node);
1435 ir_node *block = be_transform_node(get_nodes_block(node));
1436 ir_node *op = get_Not_op(node);
1437 ir_node *new_op = be_transform_node(op);
1438 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1439 ir_node *nomem = new_NoMem();
1440 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1441 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1443 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1447 * Transforms a Not node.
1449 * @return The created ia32 Not node
1451 static ir_node *gen_Not(ir_node *node) {
1452 ir_node *op = get_Not_op(node);
1453 ir_mode *mode = get_irn_mode(node);
1455 if(mode == mode_b) {
1456 return gen_bin_Not(node);
1459 assert (! mode_is_float(get_irn_mode(node)));
1460 return gen_unop(node, op, new_rd_ia32_Not);
1466 * Transforms an Abs node.
1468 * @return The created ia32 Abs node
1470 static ir_node *gen_Abs(ir_node *node) {
1471 ir_node *block = be_transform_node(get_nodes_block(node));
1472 ir_node *op = get_Abs_op(node);
1473 ir_node *new_op = be_transform_node(op);
1474 ir_graph *irg = current_ir_graph;
1475 dbg_info *dbgi = get_irn_dbg_info(node);
1476 ir_mode *mode = get_irn_mode(node);
1477 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1478 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1479 ir_node *nomem = new_NoMem();
1484 if (mode_is_float(mode)) {
1485 if (USE_SSE2(env_cg)) {
1486 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1488 size = get_mode_size_bits(mode);
1489 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1491 set_ia32_am_sc(res, ent);
1493 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1495 set_ia32_op_type(res, ia32_AddrModeS);
1496 set_ia32_ls_mode(res, mode);
1499 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1500 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1504 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1505 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1508 add_irn_dep(pval, get_irg_frame(irg));
1509 SET_IA32_ORIG_NODE(sign_extension,
1510 ia32_get_old_node_name(env_cg, node));
1512 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1513 sign_extension, nomem);
1514 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1516 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1517 sign_extension, nomem);
1518 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1527 * Transforms a Load.
1529 * @return the created ia32 Load node
1531 static ir_node *gen_Load(ir_node *node) {
1532 ir_node *old_block = get_nodes_block(node);
1533 ir_node *block = be_transform_node(old_block);
1534 ir_node *ptr = get_Load_ptr(node);
1535 ir_node *new_ptr = be_transform_node(ptr);
1536 ir_node *mem = get_Load_mem(node);
1537 ir_node *new_mem = be_transform_node(mem);
1538 ir_graph *irg = current_ir_graph;
1539 dbg_info *dbgi = get_irn_dbg_info(node);
1540 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1541 ir_mode *mode = get_Load_mode(node);
1543 ir_node *lptr = new_ptr;
1546 ia32_am_flavour_t am_flav = ia32_am_B;
1548 /* address might be a constant (symconst or absolute address) */
1549 if (is_ia32_Const(new_ptr)) {
1554 if (mode_is_float(mode)) {
1555 if (USE_SSE2(env_cg)) {
1556 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1557 res_mode = mode_xmm;
1559 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1560 res_mode = mode_vfp;
1566 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1570 /* base is a constant address */
1572 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1573 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1574 am_flav = ia32_am_N;
1576 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1577 long offs = get_tarval_long(tv);
1579 add_ia32_am_offs_int(new_op, offs);
1580 am_flav = ia32_am_O;
1584 set_irn_pinned(new_op, get_irn_pinned(node));
1585 set_ia32_op_type(new_op, ia32_AddrModeS);
1586 set_ia32_am_flavour(new_op, am_flav);
1587 set_ia32_ls_mode(new_op, mode);
1589 /* make sure we are scheduled behind the initial IncSP/Barrier
1590 * to avoid spills being placed before it
1592 if (block == get_irg_start_block(irg)) {
1593 add_irn_dep(new_op, get_irg_frame(irg));
1596 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1597 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1605 * Transforms a Store.
1607 * @return the created ia32 Store node
1609 static ir_node *gen_Store(ir_node *node) {
1610 ir_node *block = be_transform_node(get_nodes_block(node));
1611 ir_node *ptr = get_Store_ptr(node);
1612 ir_node *new_ptr = be_transform_node(ptr);
1613 ir_node *val = get_Store_value(node);
1615 ir_node *mem = get_Store_mem(node);
1616 ir_node *new_mem = be_transform_node(mem);
1617 ir_graph *irg = current_ir_graph;
1618 dbg_info *dbgi = get_irn_dbg_info(node);
1619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1620 ir_node *sptr = new_ptr;
1621 ir_mode *mode = get_irn_mode(val);
1624 ia32_am_flavour_t am_flav = ia32_am_B;
1626 /* address might be a constant (symconst or absolute address) */
1627 if (is_ia32_Const(new_ptr)) {
1632 if (mode_is_float(mode)) {
1633 new_val = be_transform_node(val);
1634 if (USE_SSE2(env_cg)) {
1635 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1638 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1642 new_val = create_immediate_or_transform(val, 0);
1646 if (get_mode_size_bits(mode) == 8) {
1647 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1650 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1655 /* base is an constant address */
1657 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1658 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1659 am_flav = ia32_am_N;
1661 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1662 long offs = get_tarval_long(tv);
1664 add_ia32_am_offs_int(new_op, offs);
1665 am_flav = ia32_am_O;
1669 set_irn_pinned(new_op, get_irn_pinned(node));
1670 set_ia32_op_type(new_op, ia32_AddrModeD);
1671 set_ia32_am_flavour(new_op, am_flav);
1672 set_ia32_ls_mode(new_op, mode);
1674 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1675 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1680 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1685 if(get_mode_size_bits(mode) == 32)
1689 if(is_ia32_Immediate(new_op))
1692 if(mode_is_signed(mode))
1697 block = get_nodes_block(new_op);
1698 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1701 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1702 ir_node *cmp_left, ir_node *cmp_right)
1704 ir_node *new_cmp_left;
1705 ir_node *new_cmp_right;
1712 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1714 if(cmp_right != NULL && !is_Const_0(cmp_right))
1717 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1718 and_left = get_And_left(cmp_left);
1719 and_right = get_And_right(cmp_left);
1721 mode = get_irn_mode(and_left);
1722 new_cmp_left = be_transform_node(and_left);
1723 new_cmp_right = create_immediate_or_transform(and_right, 0);
1725 mode = get_irn_mode(cmp_left);
1726 new_cmp_left = be_transform_node(cmp_left);
1727 new_cmp_right = be_transform_node(cmp_left);
1730 assert(get_mode_size_bits(mode) <= 32);
1731 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1732 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1733 noreg = ia32_new_NoReg_gp(env_cg);
1734 nomem = new_NoMem();
1736 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1737 new_cmp_left, new_cmp_right, nomem, pnc);
1738 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1743 static ir_node *create_Switch(ir_node *node)
1745 ir_graph *irg = current_ir_graph;
1746 dbg_info *dbgi = get_irn_dbg_info(node);
1747 ir_node *block = be_transform_node(get_nodes_block(node));
1748 ir_node *sel = get_Cond_selector(node);
1749 ir_node *new_sel = be_transform_node(sel);
1751 int switch_min = INT_MAX;
1752 const ir_edge_t *edge;
1754 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1756 /* determine the smallest switch case value */
1757 foreach_out_edge(node, edge) {
1758 ir_node *proj = get_edge_src_irn(edge);
1759 int pn = get_Proj_proj(proj);
1764 if (switch_min != 0) {
1765 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1767 /* if smallest switch case is not 0 we need an additional sub */
1768 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1769 add_ia32_am_offs_int(new_sel, -switch_min);
1770 set_ia32_am_flavour(new_sel, ia32_am_OB);
1771 set_ia32_op_type(new_sel, ia32_AddrModeS);
1773 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1776 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1777 set_ia32_pncode(res, get_Cond_defaultProj(node));
1779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1785 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1787 * @return The transformed node.
1789 static ir_node *gen_Cond(ir_node *node) {
1790 ir_node *block = be_transform_node(get_nodes_block(node));
1791 ir_graph *irg = current_ir_graph;
1792 dbg_info *dbgi = get_irn_dbg_info(node);
1793 ir_node *sel = get_Cond_selector(node);
1794 ir_mode *sel_mode = get_irn_mode(sel);
1795 ir_node *res = NULL;
1796 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1803 ir_node *nomem = new_NoMem();
1806 if (sel_mode != mode_b) {
1807 return create_Switch(node);
1810 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1811 /* it's some mode_b value but not a direct comparison -> create a
1813 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1814 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1818 cmp = get_Proj_pred(sel);
1819 cmp_a = get_Cmp_left(cmp);
1820 cmp_b = get_Cmp_right(cmp);
1821 cmp_mode = get_irn_mode(cmp_a);
1822 pnc = get_Proj_proj(sel);
1823 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1824 pnc |= ia32_pn_Cmp_Unsigned;
1827 if(mode_needs_gp_reg(cmp_mode)) {
1828 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1830 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1835 new_cmp_a = be_transform_node(cmp_a);
1836 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1838 if (mode_is_float(cmp_mode)) {
1839 if (USE_SSE2(env_cg)) {
1840 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1842 set_ia32_commutative(res);
1843 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1844 set_ia32_ls_mode(res, cmp_mode);
1846 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1847 set_ia32_commutative(res);
1850 /** workaround smaller compare modes with converts...
1851 * We could easily support 16bit compares, for 8 bit we have to set
1852 * additional register constraints, which we don't do yet
1854 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1855 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1857 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1858 new_cmp_a, new_cmp_b, nomem, pnc);
1859 set_ia32_commutative(res);
1860 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1863 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1871 * Transforms a CopyB node.
1873 * @return The transformed node.
1875 static ir_node *gen_CopyB(ir_node *node) {
1876 ir_node *block = be_transform_node(get_nodes_block(node));
1877 ir_node *src = get_CopyB_src(node);
1878 ir_node *new_src = be_transform_node(src);
1879 ir_node *dst = get_CopyB_dst(node);
1880 ir_node *new_dst = be_transform_node(dst);
1881 ir_node *mem = get_CopyB_mem(node);
1882 ir_node *new_mem = be_transform_node(mem);
1883 ir_node *res = NULL;
1884 ir_graph *irg = current_ir_graph;
1885 dbg_info *dbgi = get_irn_dbg_info(node);
1886 int size = get_type_size_bytes(get_CopyB_type(node));
1889 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1890 /* then we need the size explicitly in ECX. */
1891 if (size >= 32 * 4) {
1892 rem = size & 0x3; /* size % 4 */
1895 res = new_rd_ia32_Const(dbgi, irg, block);
1896 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1897 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1899 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1900 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1902 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1903 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1906 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1912 ir_node *gen_be_Copy(ir_node *node)
1914 ir_node *result = be_duplicate_node(node);
1915 ir_mode *mode = get_irn_mode(result);
1917 if (mode_needs_gp_reg(mode)) {
1918 set_irn_mode(result, mode_Iu);
1925 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1926 dbg_info *dbgi, ir_node *block)
1928 ir_graph *irg = current_ir_graph;
1929 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1930 ir_node *nomem = new_rd_NoMem(irg);
1932 ir_node *new_cmp_left;
1933 ir_node *new_cmp_right;
1936 /* can we use a test instruction? */
1937 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1938 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1939 if(is_And(cmp_left) &&
1940 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1941 ir_node *and_left = get_And_left(cmp_left);
1942 ir_node *and_right = get_And_right(cmp_left);
1944 mode = get_irn_mode(and_left);
1945 new_cmp_left = be_transform_node(and_left);
1946 new_cmp_right = create_immediate_or_transform(and_right, 0);
1948 mode = get_irn_mode(cmp_left);
1949 new_cmp_left = be_transform_node(cmp_left);
1950 new_cmp_right = be_transform_node(cmp_left);
1953 assert(get_mode_size_bits(mode) <= 32);
1954 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1955 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1957 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1958 new_cmp_left, new_cmp_right, nomem, pnc);
1959 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1964 mode = get_irn_mode(cmp_left);
1966 new_cmp_left = be_transform_node(cmp_left);
1967 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1969 assert(get_mode_size_bits(mode) <= 32);
1970 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1971 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1973 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1974 new_cmp_left, new_cmp_right, nomem, pnc);
1979 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1980 ir_node *val_true, ir_node *val_false,
1981 dbg_info *dbgi, ir_node *block)
1983 ir_graph *irg = current_ir_graph;
1984 ir_node *new_val_true = be_transform_node(val_true);
1985 ir_node *new_val_false = be_transform_node(val_false);
1986 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1987 ir_node *nomem = new_NoMem();
1988 ir_node *new_cmp_left;
1989 ir_node *new_cmp_right;
1992 /* cmovs with unknowns are pointless... */
1993 if(is_Unknown(val_true)) {
1994 #ifdef DEBUG_libfirm
1995 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1997 return new_val_false;
1999 if(is_Unknown(val_false)) {
2000 #ifdef DEBUG_libfirm
2001 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2003 return new_val_true;
2006 /* can we use a test instruction? */
2007 if(is_Const_0(cmp_right)) {
2008 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2009 if(is_And(cmp_left) &&
2010 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2011 ir_node *and_left = get_And_left(cmp_left);
2012 ir_node *and_right = get_And_right(cmp_left);
2014 new_cmp_left = be_transform_node(and_left);
2015 new_cmp_right = create_immediate_or_transform(and_right, 0);
2017 new_cmp_left = be_transform_node(cmp_left);
2018 new_cmp_right = be_transform_node(cmp_left);
2021 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
2022 new_cmp_left, new_cmp_right, nomem,
2023 new_val_true, new_val_false, pnc);
2024 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2029 new_cmp_left = be_transform_node(cmp_left);
2030 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2032 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
2033 new_cmp_right, nomem, new_val_true, new_val_false,
2035 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2042 * Transforms a Psi node into CMov.
2044 * @return The transformed node.
2046 static ir_node *gen_Psi(ir_node *node) {
2047 ir_node *psi_true = get_Psi_val(node, 0);
2048 ir_node *psi_default = get_Psi_default(node);
2049 ia32_code_gen_t *cg = env_cg;
2050 ir_node *cond = get_Psi_cond(node, 0);
2051 ir_node *block = be_transform_node(get_nodes_block(node));
2052 dbg_info *dbgi = get_irn_dbg_info(node);
2059 assert(get_Psi_n_conds(node) == 1);
2060 assert(get_irn_mode(cond) == mode_b);
2062 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2063 /* a mode_b value, we have to compare it against 0 */
2065 cmp_right = new_Const_long(mode_Iu, 0);
2069 ir_node *cmp = get_Proj_pred(cond);
2071 cmp_left = get_Cmp_left(cmp);
2072 cmp_right = get_Cmp_right(cmp);
2073 cmp_mode = get_irn_mode(cmp_left);
2074 pnc = get_Proj_proj(cond);
2076 assert(!mode_is_float(cmp_mode));
2078 if (!mode_is_signed(cmp_mode)) {
2079 pnc |= ia32_pn_Cmp_Unsigned;
2083 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2084 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2085 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2086 pnc = get_negated_pnc(pnc, cmp_mode);
2087 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2089 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2098 * Following conversion rules apply:
2102 * 1) n bit -> m bit n > m (downscale)
2104 * 2) n bit -> m bit n == m (sign change)
2106 * 3) n bit -> m bit n < m (upscale)
2107 * a) source is signed: movsx
2108 * b) source is unsigned: and with lower bits sets
2112 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2116 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2120 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2121 * x87 is mode_E internally, conversions happen only at load and store
2122 * in non-strict semantic
2126 * Create a conversion from x87 state register to general purpose.
2128 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2129 ir_node *block = be_transform_node(get_nodes_block(node));
2130 ir_node *op = get_Conv_op(node);
2131 ir_node *new_op = be_transform_node(op);
2132 ia32_code_gen_t *cg = env_cg;
2133 ir_graph *irg = current_ir_graph;
2134 dbg_info *dbgi = get_irn_dbg_info(node);
2135 ir_node *noreg = ia32_new_NoReg_gp(cg);
2136 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2137 ir_node *fist, *load;
2140 fist = new_rd_ia32_vfist(dbgi, irg, block,
2141 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2143 set_irn_pinned(fist, op_pin_state_floats);
2144 set_ia32_use_frame(fist);
2145 set_ia32_op_type(fist, ia32_AddrModeD);
2146 set_ia32_am_flavour(fist, ia32_am_B);
2147 set_ia32_ls_mode(fist, mode_Iu);
2148 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2151 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2153 set_irn_pinned(load, op_pin_state_floats);
2154 set_ia32_use_frame(load);
2155 set_ia32_op_type(load, ia32_AddrModeS);
2156 set_ia32_am_flavour(load, ia32_am_B);
2157 set_ia32_ls_mode(load, mode_Iu);
2158 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2160 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2163 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2165 ir_node *block = get_nodes_block(node);
2166 ir_graph *irg = current_ir_graph;
2167 dbg_info *dbgi = get_irn_dbg_info(node);
2168 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2169 ir_node *nomem = new_NoMem();
2170 ir_node *frame = get_irg_frame(irg);
2171 ir_node *store, *load;
2174 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2176 set_ia32_use_frame(store);
2177 set_ia32_op_type(store, ia32_AddrModeD);
2178 set_ia32_am_flavour(store, ia32_am_OB);
2179 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2181 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2183 set_ia32_use_frame(load);
2184 set_ia32_op_type(load, ia32_AddrModeS);
2185 set_ia32_am_flavour(load, ia32_am_OB);
2186 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2188 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2193 * Create a conversion from general purpose to x87 register
2195 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2196 ir_node *block = be_transform_node(get_nodes_block(node));
2197 ir_node *op = get_Conv_op(node);
2198 ir_node *new_op = be_transform_node(op);
2199 ir_graph *irg = current_ir_graph;
2200 dbg_info *dbgi = get_irn_dbg_info(node);
2201 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2202 ir_node *nomem = new_NoMem();
2203 ir_node *fild, *store;
2207 /* first convert to 32 bit if necessary */
2208 src_bits = get_mode_size_bits(src_mode);
2209 if (src_bits == 8) {
2210 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2211 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2212 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2213 } else if (src_bits < 32) {
2214 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2215 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2216 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2220 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2222 set_ia32_use_frame(store);
2223 set_ia32_op_type(store, ia32_AddrModeD);
2224 set_ia32_am_flavour(store, ia32_am_OB);
2225 set_ia32_ls_mode(store, mode_Iu);
2228 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2230 set_ia32_use_frame(fild);
2231 set_ia32_op_type(fild, ia32_AddrModeS);
2232 set_ia32_am_flavour(fild, ia32_am_OB);
2233 set_ia32_ls_mode(fild, mode_Iu);
2235 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2241 * Crete a conversion from one integer mode into another one
2243 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2244 dbg_info *dbgi, ir_node *new_block,
2247 ir_graph *irg = current_ir_graph;
2248 int src_bits = get_mode_size_bits(src_mode);
2249 int tgt_bits = get_mode_size_bits(tgt_mode);
2250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2251 ir_node *nomem = new_rd_NoMem(irg);
2253 ir_mode *smaller_mode;
2256 if (src_bits < tgt_bits) {
2257 smaller_mode = src_mode;
2258 smaller_bits = src_bits;
2260 smaller_mode = tgt_mode;
2261 smaller_bits = tgt_bits;
2264 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2265 if (smaller_bits == 8) {
2266 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2267 new_op, nomem, smaller_mode);
2269 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2270 nomem, smaller_mode);
2272 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2278 * Transforms a Conv node.
2280 * @return The created ia32 Conv node
2282 static ir_node *gen_Conv(ir_node *node) {
2283 ir_node *block = be_transform_node(get_nodes_block(node));
2284 ir_node *op = get_Conv_op(node);
2285 ir_node *new_op = be_transform_node(op);
2286 ir_graph *irg = current_ir_graph;
2287 dbg_info *dbgi = get_irn_dbg_info(node);
2288 ir_mode *src_mode = get_irn_mode(op);
2289 ir_mode *tgt_mode = get_irn_mode(node);
2290 int src_bits = get_mode_size_bits(src_mode);
2291 int tgt_bits = get_mode_size_bits(tgt_mode);
2292 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2293 ir_node *nomem = new_rd_NoMem(irg);
2296 if (src_mode == mode_b) {
2297 assert(mode_is_int(tgt_mode));
2298 /* nothing to do, we already model bools as 0/1 ints */
2302 if (src_mode == tgt_mode) {
2303 if (get_Conv_strict(node)) {
2304 if (USE_SSE2(env_cg)) {
2305 /* when we are in SSE mode, we can kill all strict no-op conversion */
2309 /* this should be optimized already, but who knows... */
2310 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2311 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2316 if (mode_is_float(src_mode)) {
2317 /* we convert from float ... */
2318 if (mode_is_float(tgt_mode)) {
2319 if(src_mode == mode_E && tgt_mode == mode_D
2320 && !get_Conv_strict(node)) {
2321 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2326 if (USE_SSE2(env_cg)) {
2327 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2328 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2329 set_ia32_ls_mode(res, tgt_mode);
2331 if(get_Conv_strict(node)) {
2332 res = create_strict_conv(tgt_mode, new_op);
2333 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2336 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2341 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2342 if (USE_SSE2(env_cg)) {
2343 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2344 set_ia32_ls_mode(res, src_mode);
2346 return gen_x87_fp_to_gp(node);
2350 /* we convert from int ... */
2351 if (mode_is_float(tgt_mode)) {
2353 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2354 if (USE_SSE2(env_cg)) {
2355 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2356 set_ia32_ls_mode(res, tgt_mode);
2357 if(src_bits == 32) {
2358 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2361 res = gen_x87_gp_to_fp(node, src_mode);
2362 if(get_Conv_strict(node)) {
2363 res = create_strict_conv(tgt_mode, res);
2364 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2365 ia32_get_old_node_name(env_cg, node));
2369 } else if(tgt_mode == mode_b) {
2370 /* mode_b lowering already took care that we only have 0/1 values */
2371 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2372 src_mode, tgt_mode));
2376 if (src_bits == tgt_bits) {
2377 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2378 src_mode, tgt_mode));
2382 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2386 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2392 int check_immediate_constraint(long val, char immediate_constraint_type)
2394 switch (immediate_constraint_type) {
2398 return val >= 0 && val <= 32;
2400 return val >= 0 && val <= 63;
2402 return val >= -128 && val <= 127;
2404 return val == 0xff || val == 0xffff;
2406 return val >= 0 && val <= 3;
2408 return val >= 0 && val <= 255;
2410 return val >= 0 && val <= 127;
2414 panic("Invalid immediate constraint found");
2419 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2422 tarval *offset = NULL;
2423 int offset_sign = 0;
2425 ir_entity *symconst_ent = NULL;
2426 int symconst_sign = 0;
2428 ir_node *cnst = NULL;
2429 ir_node *symconst = NULL;
2435 mode = get_irn_mode(node);
2436 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2440 if(is_Minus(node)) {
2442 node = get_Minus_op(node);
2445 if(is_Const(node)) {
2448 offset_sign = minus;
2449 } else if(is_SymConst(node)) {
2452 symconst_sign = minus;
2453 } else if(is_Add(node)) {
2454 ir_node *left = get_Add_left(node);
2455 ir_node *right = get_Add_right(node);
2456 if(is_Const(left) && is_SymConst(right)) {
2459 symconst_sign = minus;
2460 offset_sign = minus;
2461 } else if(is_SymConst(left) && is_Const(right)) {
2464 symconst_sign = minus;
2465 offset_sign = minus;
2467 } else if(is_Sub(node)) {
2468 ir_node *left = get_Sub_left(node);
2469 ir_node *right = get_Sub_right(node);
2470 if(is_Const(left) && is_SymConst(right)) {
2473 symconst_sign = !minus;
2474 offset_sign = minus;
2475 } else if(is_SymConst(left) && is_Const(right)) {
2478 symconst_sign = minus;
2479 offset_sign = !minus;
2486 offset = get_Const_tarval(cnst);
2487 if(tarval_is_long(offset)) {
2488 val = get_tarval_long(offset);
2489 } else if(tarval_is_null(offset)) {
2492 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2497 if(!check_immediate_constraint(val, immediate_constraint_type))
2500 if(symconst != NULL) {
2501 if(immediate_constraint_type != 0) {
2502 /* we need full 32bits for symconsts */
2506 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2508 symconst_ent = get_SymConst_entity(symconst);
2510 if(cnst == NULL && symconst == NULL)
2513 if(offset_sign && offset != NULL) {
2514 offset = tarval_neg(offset);
2517 irg = current_ir_graph;
2518 dbgi = get_irn_dbg_info(node);
2519 block = get_irg_start_block(irg);
2520 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2521 symconst_sign, val);
2522 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2528 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2530 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2531 if (new_node == NULL) {
2532 new_node = be_transform_node(node);
2537 typedef struct constraint_t constraint_t;
2538 struct constraint_t {
2541 const arch_register_req_t **out_reqs;
2543 const arch_register_req_t *req;
2544 unsigned immediate_possible;
2545 char immediate_type;
2548 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2550 int immediate_possible = 0;
2551 char immediate_type = 0;
2552 unsigned limited = 0;
2553 const arch_register_class_t *cls = NULL;
2555 struct obstack *obst;
2556 arch_register_req_t *req;
2557 unsigned *limited_ptr;
2561 /* TODO: replace all the asserts with nice error messages */
2563 printf("Constraint: %s\n", c);
2573 assert(cls == NULL ||
2574 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2575 cls = &ia32_reg_classes[CLASS_ia32_gp];
2576 limited |= 1 << REG_EAX;
2579 assert(cls == NULL ||
2580 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2581 cls = &ia32_reg_classes[CLASS_ia32_gp];
2582 limited |= 1 << REG_EBX;
2585 assert(cls == NULL ||
2586 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2587 cls = &ia32_reg_classes[CLASS_ia32_gp];
2588 limited |= 1 << REG_ECX;
2591 assert(cls == NULL ||
2592 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2593 cls = &ia32_reg_classes[CLASS_ia32_gp];
2594 limited |= 1 << REG_EDX;
2597 assert(cls == NULL ||
2598 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2599 cls = &ia32_reg_classes[CLASS_ia32_gp];
2600 limited |= 1 << REG_EDI;
2603 assert(cls == NULL ||
2604 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2605 cls = &ia32_reg_classes[CLASS_ia32_gp];
2606 limited |= 1 << REG_ESI;
2609 case 'q': /* q means lower part of the regs only, this makes no
2610 * difference to Q for us (we only assigne whole registers) */
2611 assert(cls == NULL ||
2612 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2613 cls = &ia32_reg_classes[CLASS_ia32_gp];
2614 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2618 assert(cls == NULL ||
2619 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2620 cls = &ia32_reg_classes[CLASS_ia32_gp];
2621 limited |= 1 << REG_EAX | 1 << REG_EDX;
2624 assert(cls == NULL ||
2625 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2626 cls = &ia32_reg_classes[CLASS_ia32_gp];
2627 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2628 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2635 assert(cls == NULL);
2636 cls = &ia32_reg_classes[CLASS_ia32_gp];
2642 /* TODO: mark values so the x87 simulator knows about t and u */
2643 assert(cls == NULL);
2644 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2649 assert(cls == NULL);
2650 /* TODO: check that sse2 is supported */
2651 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2661 assert(!immediate_possible);
2662 immediate_possible = 1;
2663 immediate_type = *c;
2667 assert(!immediate_possible);
2668 immediate_possible = 1;
2672 assert(!immediate_possible && cls == NULL);
2673 immediate_possible = 1;
2674 cls = &ia32_reg_classes[CLASS_ia32_gp];
2687 assert(constraint->is_in && "can only specify same constraint "
2690 sscanf(c, "%d%n", &same_as, &p);
2697 case 'E': /* no float consts yet */
2698 case 'F': /* no float consts yet */
2699 case 's': /* makes no sense on x86 */
2700 case 'X': /* we can't support that in firm */
2704 case '<': /* no autodecrement on x86 */
2705 case '>': /* no autoincrement on x86 */
2706 case 'C': /* sse constant not supported yet */
2707 case 'G': /* 80387 constant not supported yet */
2708 case 'y': /* we don't support mmx registers yet */
2709 case 'Z': /* not available in 32 bit mode */
2710 case 'e': /* not available in 32 bit mode */
2711 assert(0 && "asm constraint not supported");
2714 assert(0 && "unknown asm constraint found");
2721 const arch_register_req_t *other_constr;
2723 assert(cls == NULL && "same as and register constraint not supported");
2724 assert(!immediate_possible && "same as and immediate constraint not "
2726 assert(same_as < constraint->n_outs && "wrong constraint number in "
2727 "same_as constraint");
2729 other_constr = constraint->out_reqs[same_as];
2731 req = obstack_alloc(obst, sizeof(req[0]));
2732 req->cls = other_constr->cls;
2733 req->type = arch_register_req_type_should_be_same;
2734 req->limited = NULL;
2735 req->other_same = pos;
2736 req->other_different = -1;
2738 /* switch constraints. This is because in firm we have same_as
2739 * constraints on the output constraints while in the gcc asm syntax
2740 * they are specified on the input constraints */
2741 constraint->req = other_constr;
2742 constraint->out_reqs[same_as] = req;
2743 constraint->immediate_possible = 0;
2747 if(immediate_possible && cls == NULL) {
2748 cls = &ia32_reg_classes[CLASS_ia32_gp];
2750 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2751 assert(cls != NULL);
2753 if(immediate_possible) {
2754 assert(constraint->is_in
2755 && "imeediates make no sense for output constraints");
2757 /* todo: check types (no float input on 'r' constrainted in and such... */
2759 irg = current_ir_graph;
2760 obst = get_irg_obstack(irg);
2763 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2764 limited_ptr = (unsigned*) (req+1);
2766 req = obstack_alloc(obst, sizeof(req[0]));
2768 memset(req, 0, sizeof(req[0]));
2771 req->type = arch_register_req_type_limited;
2772 *limited_ptr = limited;
2773 req->limited = limited_ptr;
2775 req->type = arch_register_req_type_normal;
2779 constraint->req = req;
2780 constraint->immediate_possible = immediate_possible;
2781 constraint->immediate_type = immediate_type;
2785 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2792 panic("Clobbers not supported yet");
2795 ir_node *gen_ASM(ir_node *node)
2798 ir_graph *irg = current_ir_graph;
2799 ir_node *block = be_transform_node(get_nodes_block(node));
2800 dbg_info *dbgi = get_irn_dbg_info(node);
2807 ia32_asm_attr_t *attr;
2808 const arch_register_req_t **out_reqs;
2809 const arch_register_req_t **in_reqs;
2810 struct obstack *obst;
2811 constraint_t parsed_constraint;
2813 /* transform inputs */
2814 arity = get_irn_arity(node);
2815 in = alloca(arity * sizeof(in[0]));
2816 memset(in, 0, arity * sizeof(in[0]));
2818 n_outs = get_ASM_n_output_constraints(node);
2819 n_clobbers = get_ASM_n_clobbers(node);
2820 out_arity = n_outs + n_clobbers;
2822 /* construct register constraints */
2823 obst = get_irg_obstack(irg);
2824 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2825 parsed_constraint.out_reqs = out_reqs;
2826 parsed_constraint.n_outs = n_outs;
2827 parsed_constraint.is_in = 0;
2828 for(i = 0; i < out_arity; ++i) {
2832 const ir_asm_constraint *constraint;
2833 constraint = & get_ASM_output_constraints(node) [i];
2834 c = get_id_str(constraint->constraint);
2835 parse_asm_constraint(i, &parsed_constraint, c);
2837 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2838 c = get_id_str(glob_id);
2839 parse_clobber(node, i, &parsed_constraint, c);
2841 out_reqs[i] = parsed_constraint.req;
2844 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2845 parsed_constraint.is_in = 1;
2846 for(i = 0; i < arity; ++i) {
2847 const ir_asm_constraint *constraint;
2851 constraint = & get_ASM_input_constraints(node) [i];
2852 constr_id = constraint->constraint;
2853 c = get_id_str(constr_id);
2854 parse_asm_constraint(i, &parsed_constraint, c);
2855 in_reqs[i] = parsed_constraint.req;
2857 if(parsed_constraint.immediate_possible) {
2858 ir_node *pred = get_irn_n(node, i);
2859 char imm_type = parsed_constraint.immediate_type;
2860 ir_node *immediate = try_create_Immediate(pred, imm_type);
2862 if(immediate != NULL) {
2868 /* transform inputs */
2869 for(i = 0; i < arity; ++i) {
2871 ir_node *transformed;
2876 pred = get_irn_n(node, i);
2877 transformed = be_transform_node(pred);
2878 in[i] = transformed;
2881 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2883 generic_attr = get_irn_generic_attr(res);
2884 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2885 attr->asm_text = get_ASM_text(node);
2886 set_ia32_out_req_all(res, out_reqs);
2887 set_ia32_in_req_all(res, in_reqs);
2889 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2894 /********************************************
2897 * | |__ ___ _ __ ___ __| | ___ ___
2898 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2899 * | |_) | __/ | | | (_) | (_| | __/\__ \
2900 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2902 ********************************************/
2904 static ir_node *gen_be_StackParam(ir_node *node) {
2905 ir_node *block = be_transform_node(get_nodes_block(node));
2906 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2907 ir_node *new_ptr = be_transform_node(ptr);
2908 ir_node *new_op = NULL;
2909 ir_graph *irg = current_ir_graph;
2910 dbg_info *dbgi = get_irn_dbg_info(node);
2911 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2912 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2913 ir_mode *load_mode = get_irn_mode(node);
2914 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2918 if (mode_is_float(load_mode)) {
2919 if (USE_SSE2(env_cg)) {
2920 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2921 pn_res = pn_ia32_xLoad_res;
2922 proj_mode = mode_xmm;
2924 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2925 pn_res = pn_ia32_vfld_res;
2926 proj_mode = mode_vfp;
2929 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2930 proj_mode = mode_Iu;
2931 pn_res = pn_ia32_Load_res;
2934 set_irn_pinned(new_op, op_pin_state_floats);
2935 set_ia32_frame_ent(new_op, ent);
2936 set_ia32_use_frame(new_op);
2938 set_ia32_op_type(new_op, ia32_AddrModeS);
2939 set_ia32_am_flavour(new_op, ia32_am_B);
2940 set_ia32_ls_mode(new_op, load_mode);
2941 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2943 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2945 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2949 * Transforms a FrameAddr into an ia32 Add.
2951 static ir_node *gen_be_FrameAddr(ir_node *node) {
2952 ir_node *block = be_transform_node(get_nodes_block(node));
2953 ir_node *op = be_get_FrameAddr_frame(node);
2954 ir_node *new_op = be_transform_node(op);
2955 ir_graph *irg = current_ir_graph;
2956 dbg_info *dbgi = get_irn_dbg_info(node);
2957 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2960 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2961 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2962 set_ia32_use_frame(res);
2963 set_ia32_am_flavour(res, ia32_am_OB);
2965 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2971 * Transforms a FrameLoad into an ia32 Load.
2973 static ir_node *gen_be_FrameLoad(ir_node *node) {
2974 ir_node *block = be_transform_node(get_nodes_block(node));
2975 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2976 ir_node *new_mem = be_transform_node(mem);
2977 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2978 ir_node *new_ptr = be_transform_node(ptr);
2979 ir_node *new_op = NULL;
2980 ir_graph *irg = current_ir_graph;
2981 dbg_info *dbgi = get_irn_dbg_info(node);
2982 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2983 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2984 ir_mode *mode = get_type_mode(get_entity_type(ent));
2985 ir_node *projs[pn_Load_max];
2987 ia32_collect_Projs(node, projs, pn_Load_max);
2989 if (mode_is_float(mode)) {
2990 if (USE_SSE2(env_cg)) {
2991 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2994 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2998 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
3001 set_irn_pinned(new_op, op_pin_state_floats);
3002 set_ia32_frame_ent(new_op, ent);
3003 set_ia32_use_frame(new_op);
3005 set_ia32_op_type(new_op, ia32_AddrModeS);
3006 set_ia32_am_flavour(new_op, ia32_am_B);
3007 set_ia32_ls_mode(new_op, mode);
3008 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
3010 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3017 * Transforms a FrameStore into an ia32 Store.
3019 static ir_node *gen_be_FrameStore(ir_node *node) {
3020 ir_node *block = be_transform_node(get_nodes_block(node));
3021 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
3022 ir_node *new_mem = be_transform_node(mem);
3023 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
3024 ir_node *new_ptr = be_transform_node(ptr);
3025 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3026 ir_node *new_val = be_transform_node(val);
3027 ir_node *new_op = NULL;
3028 ir_graph *irg = current_ir_graph;
3029 dbg_info *dbgi = get_irn_dbg_info(node);
3030 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3031 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3032 ir_mode *mode = get_irn_mode(val);
3034 if (mode_is_float(mode)) {
3035 if (USE_SSE2(env_cg)) {
3036 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3038 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3040 } else if (get_mode_size_bits(mode) == 8) {
3041 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3043 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3046 set_ia32_frame_ent(new_op, ent);
3047 set_ia32_use_frame(new_op);
3049 set_ia32_op_type(new_op, ia32_AddrModeD);
3050 set_ia32_am_flavour(new_op, ia32_am_B);
3051 set_ia32_ls_mode(new_op, mode);
3053 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3059 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3061 static ir_node *gen_be_Return(ir_node *node) {
3062 ir_graph *irg = current_ir_graph;
3063 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3064 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3065 ir_entity *ent = get_irg_entity(irg);
3066 ir_type *tp = get_entity_type(ent);
3071 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3072 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3075 int pn_ret_val, pn_ret_mem, arity, i;
3077 assert(ret_val != NULL);
3078 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3079 return be_duplicate_node(node);
3082 res_type = get_method_res_type(tp, 0);
3084 if (! is_Primitive_type(res_type)) {
3085 return be_duplicate_node(node);
3088 mode = get_type_mode(res_type);
3089 if (! mode_is_float(mode)) {
3090 return be_duplicate_node(node);
3093 assert(get_method_n_ress(tp) == 1);
3095 pn_ret_val = get_Proj_proj(ret_val);
3096 pn_ret_mem = get_Proj_proj(ret_mem);
3098 /* get the Barrier */
3099 barrier = get_Proj_pred(ret_val);
3101 /* get result input of the Barrier */
3102 ret_val = get_irn_n(barrier, pn_ret_val);
3103 new_ret_val = be_transform_node(ret_val);
3105 /* get memory input of the Barrier */
3106 ret_mem = get_irn_n(barrier, pn_ret_mem);
3107 new_ret_mem = be_transform_node(ret_mem);
3109 frame = get_irg_frame(irg);
3111 dbgi = get_irn_dbg_info(barrier);
3112 block = be_transform_node(get_nodes_block(barrier));
3114 noreg = ia32_new_NoReg_gp(env_cg);
3116 /* store xmm0 onto stack */
3117 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3118 new_ret_val, new_ret_mem);
3119 set_ia32_ls_mode(sse_store, mode);
3120 set_ia32_op_type(sse_store, ia32_AddrModeD);
3121 set_ia32_use_frame(sse_store);
3122 set_ia32_am_flavour(sse_store, ia32_am_B);
3124 /* load into x87 register */
3125 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3126 set_ia32_op_type(fld, ia32_AddrModeS);
3127 set_ia32_use_frame(fld);
3128 set_ia32_am_flavour(fld, ia32_am_B);
3130 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3131 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3133 /* create a new barrier */
3134 arity = get_irn_arity(barrier);
3135 in = alloca(arity * sizeof(in[0]));
3136 for (i = 0; i < arity; ++i) {
3139 if (i == pn_ret_val) {
3141 } else if (i == pn_ret_mem) {
3144 ir_node *in = get_irn_n(barrier, i);
3145 new_in = be_transform_node(in);
3150 new_barrier = new_ir_node(dbgi, irg, block,
3151 get_irn_op(barrier), get_irn_mode(barrier),
3153 copy_node_attr(barrier, new_barrier);
3154 be_duplicate_deps(barrier, new_barrier);
3155 be_set_transformed_node(barrier, new_barrier);
3156 mark_irn_visited(barrier);
3158 /* transform normally */
3159 return be_duplicate_node(node);
3163 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3165 static ir_node *gen_be_AddSP(ir_node *node) {
3166 ir_node *block = be_transform_node(get_nodes_block(node));
3167 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3169 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3170 ir_node *new_sp = be_transform_node(sp);
3171 ir_graph *irg = current_ir_graph;
3172 dbg_info *dbgi = get_irn_dbg_info(node);
3173 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3174 ir_node *nomem = new_NoMem();
3177 new_sz = create_immediate_or_transform(sz, 0);
3179 /* ia32 stack grows in reverse direction, make a SubSP */
3180 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3182 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3183 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3189 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3191 static ir_node *gen_be_SubSP(ir_node *node) {
3192 ir_node *block = be_transform_node(get_nodes_block(node));
3193 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3195 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3196 ir_node *new_sp = be_transform_node(sp);
3197 ir_graph *irg = current_ir_graph;
3198 dbg_info *dbgi = get_irn_dbg_info(node);
3199 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3200 ir_node *nomem = new_NoMem();
3203 new_sz = create_immediate_or_transform(sz, 0);
3205 /* ia32 stack grows in reverse direction, make an AddSP */
3206 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3207 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3208 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3214 * This function just sets the register for the Unknown node
3215 * as this is not done during register allocation because Unknown
3216 * is an "ignore" node.
3218 static ir_node *gen_Unknown(ir_node *node) {
3219 ir_mode *mode = get_irn_mode(node);
3221 if (mode_is_float(mode)) {
3223 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3224 if (USE_SSE2(env_cg))
3225 return ia32_new_Unknown_xmm(env_cg);
3227 return ia32_new_Unknown_vfp(env_cg);
3229 ir_graph *irg = current_ir_graph;
3230 dbg_info *dbgi = get_irn_dbg_info(node);
3231 ir_node *block = get_irg_start_block(irg);
3232 return new_rd_ia32_vfldz(dbgi, irg, block);
3234 } else if (mode_needs_gp_reg(mode)) {
3235 return ia32_new_Unknown_gp(env_cg);
3237 assert(0 && "unsupported Unknown-Mode");
3244 * Change some phi modes
3246 static ir_node *gen_Phi(ir_node *node) {
3247 ir_node *block = be_transform_node(get_nodes_block(node));
3248 ir_graph *irg = current_ir_graph;
3249 dbg_info *dbgi = get_irn_dbg_info(node);
3250 ir_mode *mode = get_irn_mode(node);
3253 if(mode_needs_gp_reg(mode)) {
3254 /* we shouldn't have any 64bit stuff around anymore */
3255 assert(get_mode_size_bits(mode) <= 32);
3256 /* all integer operations are on 32bit registers now */
3258 } else if(mode_is_float(mode)) {
3259 if (USE_SSE2(env_cg)) {
3266 /* phi nodes allow loops, so we use the old arguments for now
3267 * and fix this later */
3268 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3269 copy_node_attr(node, phi);
3270 be_duplicate_deps(node, phi);
3272 be_set_transformed_node(node, phi);
3273 be_enqueue_preds(node);
3281 static ir_node *gen_IJmp(ir_node *node) {
3282 ir_node *block = be_transform_node(get_nodes_block(node));
3283 ir_graph *irg = current_ir_graph;
3284 dbg_info *dbgi = get_irn_dbg_info(node);
3285 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3286 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3287 ir_node *nomem = new_NoMem();
3290 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3291 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3293 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3299 /**********************************************************************
3302 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3303 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3304 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3305 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3307 **********************************************************************/
3309 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3311 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3314 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3315 ir_node *val, ir_node *mem);
3318 * Transforms a lowered Load into a "real" one.
3320 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3322 ir_node *block = be_transform_node(get_nodes_block(node));
3323 ir_node *ptr = get_irn_n(node, 0);
3324 ir_node *new_ptr = be_transform_node(ptr);
3325 ir_node *mem = get_irn_n(node, 1);
3326 ir_node *new_mem = be_transform_node(mem);
3327 ir_graph *irg = current_ir_graph;
3328 dbg_info *dbgi = get_irn_dbg_info(node);
3329 ir_mode *mode = get_ia32_ls_mode(node);
3330 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3333 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3335 set_ia32_op_type(new_op, ia32_AddrModeS);
3336 set_ia32_am_flavour(new_op, ia32_am_OB);
3337 set_ia32_am_offs_int(new_op, 0);
3338 set_ia32_am_scale(new_op, 1);
3339 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3340 if (is_ia32_am_sc_sign(node))
3341 set_ia32_am_sc_sign(new_op);
3342 set_ia32_ls_mode(new_op, mode);
3343 if (is_ia32_use_frame(node)) {
3344 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3345 set_ia32_use_frame(new_op);
3348 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3354 * Transforms a lowered Store into a "real" one.
3356 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3358 ir_node *block = be_transform_node(get_nodes_block(node));
3359 ir_node *ptr = get_irn_n(node, 0);
3360 ir_node *new_ptr = be_transform_node(ptr);
3361 ir_node *val = get_irn_n(node, 1);
3362 ir_node *new_val = be_transform_node(val);
3363 ir_node *mem = get_irn_n(node, 2);
3364 ir_node *new_mem = be_transform_node(mem);
3365 ir_graph *irg = current_ir_graph;
3366 dbg_info *dbgi = get_irn_dbg_info(node);
3367 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3368 ir_mode *mode = get_ia32_ls_mode(node);
3371 ia32_am_flavour_t am_flav = ia32_B;
3373 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3375 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3377 add_ia32_am_offs_int(new_op, am_offs);
3380 set_ia32_op_type(new_op, ia32_AddrModeD);
3381 set_ia32_am_flavour(new_op, am_flav);
3382 set_ia32_ls_mode(new_op, mode);
3383 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3384 set_ia32_use_frame(new_op);
3386 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3393 * Transforms an ia32_l_XXX into a "real" XXX node
3395 * @param env The transformation environment
3396 * @return the created ia32 XXX node
3398 #define GEN_LOWERED_OP(op) \
3399 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3400 return gen_binop(node, get_binop_left(node), \
3401 get_binop_right(node), new_rd_ia32_##op,0); \
3404 #define GEN_LOWERED_x87_OP(op) \
3405 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3407 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3408 get_binop_right(node), new_rd_ia32_##op); \
3412 #define GEN_LOWERED_UNOP(op) \
3413 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3414 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3417 #define GEN_LOWERED_SHIFT_OP(op) \
3418 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3419 return gen_shift_binop(node, get_binop_left(node), \
3420 get_binop_right(node), new_rd_ia32_##op); \
3423 #define GEN_LOWERED_LOAD(op) \
3424 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3425 return gen_lowered_Load(node, new_rd_ia32_##op); \
3428 #define GEN_LOWERED_STORE(op) \
3429 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3430 return gen_lowered_Store(node, new_rd_ia32_##op); \
3437 GEN_LOWERED_OP(IMul)
3439 GEN_LOWERED_x87_OP(vfprem)
3440 GEN_LOWERED_x87_OP(vfmul)
3441 GEN_LOWERED_x87_OP(vfsub)
3443 GEN_LOWERED_UNOP(Neg)
3445 GEN_LOWERED_LOAD(vfild)
3446 GEN_LOWERED_LOAD(Load)
3447 // GEN_LOWERED_STORE(vfist) TODO
3448 GEN_LOWERED_STORE(Store)
3450 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3451 ir_node *block = be_transform_node(get_nodes_block(node));
3452 ir_node *left = get_binop_left(node);
3453 ir_node *new_left = be_transform_node(left);
3454 ir_node *right = get_binop_right(node);
3455 ir_node *new_right = be_transform_node(right);
3456 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3457 ir_graph *irg = current_ir_graph;
3458 dbg_info *dbgi = get_irn_dbg_info(node);
3459 ir_node *fpcw = get_fpcw();
3462 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3463 new_right, new_NoMem(), fpcw);
3464 clear_ia32_commutative(vfdiv);
3465 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3467 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3473 * Transforms a l_MulS into a "real" MulS node.
3475 * @param env The transformation environment
3476 * @return the created ia32 Mul node
3478 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3479 ir_node *block = be_transform_node(get_nodes_block(node));
3480 ir_node *left = get_binop_left(node);
3481 ir_node *new_left = be_transform_node(left);
3482 ir_node *right = get_binop_right(node);
3483 ir_node *new_right = be_transform_node(right);
3484 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3485 ir_graph *irg = current_ir_graph;
3486 dbg_info *dbgi = get_irn_dbg_info(node);
3488 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3489 /* and then skip the result Proj, because all needed Projs are already there. */
3490 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3491 new_right, new_NoMem());
3492 clear_ia32_commutative(muls);
3493 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3495 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3500 GEN_LOWERED_SHIFT_OP(Shl)
3501 GEN_LOWERED_SHIFT_OP(Shr)
3502 GEN_LOWERED_SHIFT_OP(Sar)
3505 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3506 * op1 - target to be shifted
3507 * op2 - contains bits to be shifted into target
3509 * Only op3 can be an immediate.
3511 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3512 ir_node *op2, ir_node *count)
3514 ir_node *block = be_transform_node(get_nodes_block(node));
3515 ir_node *new_op1 = be_transform_node(op1);
3516 ir_node *new_op2 = be_transform_node(op2);
3517 ir_node *new_count = be_transform_node(count);
3518 ir_node *new_op = NULL;
3519 ir_graph *irg = current_ir_graph;
3520 dbg_info *dbgi = get_irn_dbg_info(node);
3521 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3522 ir_node *nomem = new_NoMem();
3526 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3528 /* Check if immediate optimization is on and */
3529 /* if it's an operation with immediate. */
3530 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3532 /* Limit imm_op within range imm8 */
3534 tv = get_ia32_Immop_tarval(imm_op);
3537 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3538 set_ia32_Immop_tarval(imm_op, tv);
3545 /* integer operations */
3547 /* This is ShiftD with const */
3548 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3550 if (is_ia32_l_ShlD(node))
3551 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3552 new_op1, new_op2, noreg, nomem);
3554 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3555 new_op1, new_op2, noreg, nomem);
3556 copy_ia32_Immop_attr(new_op, imm_op);
3559 /* This is a normal ShiftD */
3560 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3561 if (is_ia32_l_ShlD(node))
3562 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3563 new_op1, new_op2, new_count, nomem);
3565 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3566 new_op1, new_op2, new_count, nomem);
3569 /* set AM support */
3570 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3572 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3574 set_ia32_emit_cl(new_op);
3579 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3580 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3581 get_irn_n(node, 1), get_irn_n(node, 2));
3584 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3585 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3586 get_irn_n(node, 1), get_irn_n(node, 2));
3590 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3592 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3593 ir_node *block = be_transform_node(get_nodes_block(node));
3594 ir_node *val = get_irn_n(node, 1);
3595 ir_node *new_val = be_transform_node(val);
3596 ia32_code_gen_t *cg = env_cg;
3597 ir_node *res = NULL;
3598 ir_graph *irg = current_ir_graph;
3600 ir_node *noreg, *new_ptr, *new_mem;
3607 mem = get_irn_n(node, 2);
3608 new_mem = be_transform_node(mem);
3609 ptr = get_irn_n(node, 0);
3610 new_ptr = be_transform_node(ptr);
3611 noreg = ia32_new_NoReg_gp(cg);
3612 dbgi = get_irn_dbg_info(node);
3614 /* Store x87 -> MEM */
3615 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3616 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3617 set_ia32_use_frame(res);
3618 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3619 set_ia32_am_flavour(res, ia32_B);
3620 set_ia32_op_type(res, ia32_AddrModeD);
3622 /* Load MEM -> SSE */
3623 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3624 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3625 set_ia32_use_frame(res);
3626 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3627 set_ia32_am_flavour(res, ia32_B);
3628 set_ia32_op_type(res, ia32_AddrModeS);
3629 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3635 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3637 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3638 ir_node *block = be_transform_node(get_nodes_block(node));
3639 ir_node *val = get_irn_n(node, 1);
3640 ir_node *new_val = be_transform_node(val);
3641 ia32_code_gen_t *cg = env_cg;
3642 ir_graph *irg = current_ir_graph;
3643 ir_node *res = NULL;
3644 ir_entity *fent = get_ia32_frame_ent(node);
3645 ir_mode *lsmode = get_ia32_ls_mode(node);
3647 ir_node *noreg, *new_ptr, *new_mem;
3651 if (! USE_SSE2(cg)) {
3652 /* SSE unit is not used -> skip this node. */
3656 ptr = get_irn_n(node, 0);
3657 new_ptr = be_transform_node(ptr);
3658 mem = get_irn_n(node, 2);
3659 new_mem = be_transform_node(mem);
3660 noreg = ia32_new_NoReg_gp(cg);
3661 dbgi = get_irn_dbg_info(node);
3663 /* Store SSE -> MEM */
3664 if (is_ia32_xLoad(skip_Proj(new_val))) {
3665 ir_node *ld = skip_Proj(new_val);
3667 /* we can vfld the value directly into the fpu */
3668 fent = get_ia32_frame_ent(ld);
3669 ptr = get_irn_n(ld, 0);
3670 offs = get_ia32_am_offs_int(ld);
3672 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3673 set_ia32_frame_ent(res, fent);
3674 set_ia32_use_frame(res);
3675 set_ia32_ls_mode(res, lsmode);
3676 set_ia32_am_flavour(res, ia32_B);
3677 set_ia32_op_type(res, ia32_AddrModeD);
3681 /* Load MEM -> x87 */
3682 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3683 set_ia32_frame_ent(res, fent);
3684 set_ia32_use_frame(res);
3685 add_ia32_am_offs_int(res, offs);
3686 set_ia32_am_flavour(res, ia32_B);
3687 set_ia32_op_type(res, ia32_AddrModeS);
3688 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3693 /*********************************************************
3696 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3697 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3698 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3699 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3701 *********************************************************/
3704 * the BAD transformer.
3706 static ir_node *bad_transform(ir_node *node) {
3707 panic("No transform function for %+F available.\n", node);
3712 * Transform the Projs of an AddSP.
3714 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3715 ir_node *block = be_transform_node(get_nodes_block(node));
3716 ir_node *pred = get_Proj_pred(node);
3717 ir_node *new_pred = be_transform_node(pred);
3718 ir_graph *irg = current_ir_graph;
3719 dbg_info *dbgi = get_irn_dbg_info(node);
3720 long proj = get_Proj_proj(node);
3722 if (proj == pn_be_AddSP_sp) {
3723 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3724 pn_ia32_SubSP_stack);
3725 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3727 } else if(proj == pn_be_AddSP_res) {
3728 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3729 pn_ia32_SubSP_addr);
3730 } else if (proj == pn_be_AddSP_M) {
3731 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3735 return new_rd_Unknown(irg, get_irn_mode(node));
3739 * Transform the Projs of a SubSP.
3741 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3742 ir_node *block = be_transform_node(get_nodes_block(node));
3743 ir_node *pred = get_Proj_pred(node);
3744 ir_node *new_pred = be_transform_node(pred);
3745 ir_graph *irg = current_ir_graph;
3746 dbg_info *dbgi = get_irn_dbg_info(node);
3747 long proj = get_Proj_proj(node);
3749 if (proj == pn_be_SubSP_sp) {
3750 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3751 pn_ia32_AddSP_stack);
3752 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3754 } else if (proj == pn_be_SubSP_M) {
3755 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3759 return new_rd_Unknown(irg, get_irn_mode(node));
3763 * Transform and renumber the Projs from a Load.
3765 static ir_node *gen_Proj_Load(ir_node *node) {
3766 ir_node *block = be_transform_node(get_nodes_block(node));
3767 ir_node *pred = get_Proj_pred(node);
3768 ir_node *new_pred = be_transform_node(pred);
3769 ir_graph *irg = current_ir_graph;
3770 dbg_info *dbgi = get_irn_dbg_info(node);
3771 long proj = get_Proj_proj(node);
3773 /* renumber the proj */
3774 if (is_ia32_Load(new_pred)) {
3775 if (proj == pn_Load_res) {
3776 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3777 } else if (proj == pn_Load_M) {
3778 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3780 } else if (is_ia32_xLoad(new_pred)) {
3781 if (proj == pn_Load_res) {
3782 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3783 } else if (proj == pn_Load_M) {
3784 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3786 } else if (is_ia32_vfld(new_pred)) {
3787 if (proj == pn_Load_res) {
3788 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3789 } else if (proj == pn_Load_M) {
3790 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3795 return new_rd_Unknown(irg, get_irn_mode(node));
3799 * Transform and renumber the Projs from a DivMod like instruction.
3801 static ir_node *gen_Proj_DivMod(ir_node *node) {
3802 ir_node *block = be_transform_node(get_nodes_block(node));
3803 ir_node *pred = get_Proj_pred(node);
3804 ir_node *new_pred = be_transform_node(pred);
3805 ir_graph *irg = current_ir_graph;
3806 dbg_info *dbgi = get_irn_dbg_info(node);
3807 ir_mode *mode = get_irn_mode(node);
3808 long proj = get_Proj_proj(node);
3810 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3812 switch (get_irn_opcode(pred)) {
3816 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3818 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3826 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3828 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3836 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3837 case pn_DivMod_res_div:
3838 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3839 case pn_DivMod_res_mod:
3840 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3850 return new_rd_Unknown(irg, mode);
3854 * Transform and renumber the Projs from a CopyB.
3856 static ir_node *gen_Proj_CopyB(ir_node *node) {
3857 ir_node *block = be_transform_node(get_nodes_block(node));
3858 ir_node *pred = get_Proj_pred(node);
3859 ir_node *new_pred = be_transform_node(pred);
3860 ir_graph *irg = current_ir_graph;
3861 dbg_info *dbgi = get_irn_dbg_info(node);
3862 ir_mode *mode = get_irn_mode(node);
3863 long proj = get_Proj_proj(node);
3866 case pn_CopyB_M_regular:
3867 if (is_ia32_CopyB_i(new_pred)) {
3868 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3869 } else if (is_ia32_CopyB(new_pred)) {
3870 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3878 return new_rd_Unknown(irg, mode);
3882 * Transform and renumber the Projs from a vfdiv.
3884 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3885 ir_node *block = be_transform_node(get_nodes_block(node));
3886 ir_node *pred = get_Proj_pred(node);
3887 ir_node *new_pred = be_transform_node(pred);
3888 ir_graph *irg = current_ir_graph;
3889 dbg_info *dbgi = get_irn_dbg_info(node);
3890 ir_mode *mode = get_irn_mode(node);
3891 long proj = get_Proj_proj(node);
3894 case pn_ia32_l_vfdiv_M:
3895 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3896 case pn_ia32_l_vfdiv_res:
3897 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3902 return new_rd_Unknown(irg, mode);
3906 * Transform and renumber the Projs from a Quot.
3908 static ir_node *gen_Proj_Quot(ir_node *node) {
3909 ir_node *block = be_transform_node(get_nodes_block(node));
3910 ir_node *pred = get_Proj_pred(node);
3911 ir_node *new_pred = be_transform_node(pred);
3912 ir_graph *irg = current_ir_graph;
3913 dbg_info *dbgi = get_irn_dbg_info(node);
3914 ir_mode *mode = get_irn_mode(node);
3915 long proj = get_Proj_proj(node);
3919 if (is_ia32_xDiv(new_pred)) {
3920 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3921 } else if (is_ia32_vfdiv(new_pred)) {
3922 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3926 if (is_ia32_xDiv(new_pred)) {
3927 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3928 } else if (is_ia32_vfdiv(new_pred)) {
3929 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3937 return new_rd_Unknown(irg, mode);
3941 * Transform the Thread Local Storage Proj.
3943 static ir_node *gen_Proj_tls(ir_node *node) {
3944 ir_node *block = be_transform_node(get_nodes_block(node));
3945 ir_graph *irg = current_ir_graph;
3946 dbg_info *dbgi = NULL;
3947 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3953 * Transform the Projs from a be_Call.
3955 static ir_node *gen_Proj_be_Call(ir_node *node) {
3956 ir_node *block = be_transform_node(get_nodes_block(node));
3957 ir_node *call = get_Proj_pred(node);
3958 ir_node *new_call = be_transform_node(call);
3959 ir_graph *irg = current_ir_graph;
3960 dbg_info *dbgi = get_irn_dbg_info(node);
3961 long proj = get_Proj_proj(node);
3962 ir_mode *mode = get_irn_mode(node);
3964 const arch_register_class_t *cls;
3966 /* The following is kinda tricky: If we're using SSE, then we have to
3967 * move the result value of the call in floating point registers to an
3968 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3969 * after the call, we have to make sure to correctly make the
3970 * MemProj and the result Proj use these 2 nodes
3972 if (proj == pn_be_Call_M_regular) {
3973 // get new node for result, are we doing the sse load/store hack?
3974 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3975 ir_node *call_res_new;
3976 ir_node *call_res_pred = NULL;
3978 if (call_res != NULL) {
3979 call_res_new = be_transform_node(call_res);
3980 call_res_pred = get_Proj_pred(call_res_new);
3983 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3984 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3985 pn_be_Call_M_regular);
3987 assert(is_ia32_xLoad(call_res_pred));
3988 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3992 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3994 ir_node *frame = get_irg_frame(irg);
3995 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3997 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4000 /* in case there is no memory output: create one to serialize the copy
4002 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4003 pn_be_Call_M_regular);
4004 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4005 pn_be_Call_first_res);
4007 /* store st(0) onto stack */
4008 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4010 set_ia32_op_type(fstp, ia32_AddrModeD);
4011 set_ia32_use_frame(fstp);
4012 set_ia32_am_flavour(fstp, ia32_am_B);
4014 /* load into SSE register */
4015 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4016 set_ia32_ls_mode(sse_load, mode);
4017 set_ia32_op_type(sse_load, ia32_AddrModeS);
4018 set_ia32_use_frame(sse_load);
4019 set_ia32_am_flavour(sse_load, ia32_am_B);
4021 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4025 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4027 /* get a Proj representing a caller save register */
4028 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4029 assert(is_Proj(p) && "Proj expected.");
4031 /* user of the the proj is the Keep */
4032 p = get_edge_src_irn(get_irn_out_edge_first(p));
4033 assert(be_is_Keep(p) && "Keep expected.");
4039 /* transform call modes */
4040 if (mode_is_data(mode)) {
4041 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4045 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4049 * Transform the Projs from a Cmp.
4051 static ir_node *gen_Proj_Cmp(ir_node *node)
4053 /* normally Cmps are processed when looking at Cond nodes, but this case
4054 * can happen in complicated Psi conditions */
4056 ir_node *cmp = get_Proj_pred(node);
4057 long pnc = get_Proj_proj(node);
4058 ir_node *cmp_left = get_Cmp_left(cmp);
4059 ir_node *cmp_right = get_Cmp_right(cmp);
4060 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4061 dbg_info *dbgi = get_irn_dbg_info(cmp);
4062 ir_node *block = be_transform_node(get_nodes_block(node));
4065 assert(!mode_is_float(cmp_mode));
4067 if(!mode_is_signed(cmp_mode)) {
4068 pnc |= ia32_pn_Cmp_Unsigned;
4071 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4072 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4078 * Transform and potentially renumber Proj nodes.
4080 static ir_node *gen_Proj(ir_node *node) {
4081 ir_graph *irg = current_ir_graph;
4082 dbg_info *dbgi = get_irn_dbg_info(node);
4083 ir_node *pred = get_Proj_pred(node);
4084 long proj = get_Proj_proj(node);
4086 if (is_Store(pred) || be_is_FrameStore(pred)) {
4087 if (proj == pn_Store_M) {
4088 return be_transform_node(pred);
4091 return new_r_Bad(irg);
4093 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4094 return gen_Proj_Load(node);
4095 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4096 return gen_Proj_DivMod(node);
4097 } else if (is_CopyB(pred)) {
4098 return gen_Proj_CopyB(node);
4099 } else if (is_Quot(pred)) {
4100 return gen_Proj_Quot(node);
4101 } else if (is_ia32_l_vfdiv(pred)) {
4102 return gen_Proj_l_vfdiv(node);
4103 } else if (be_is_SubSP(pred)) {
4104 return gen_Proj_be_SubSP(node);
4105 } else if (be_is_AddSP(pred)) {
4106 return gen_Proj_be_AddSP(node);
4107 } else if (be_is_Call(pred)) {
4108 return gen_Proj_be_Call(node);
4109 } else if (is_Cmp(pred)) {
4110 return gen_Proj_Cmp(node);
4111 } else if (get_irn_op(pred) == op_Start) {
4112 if (proj == pn_Start_X_initial_exec) {
4113 ir_node *block = get_nodes_block(pred);
4116 /* we exchange the ProjX with a jump */
4117 block = be_transform_node(block);
4118 jump = new_rd_Jmp(dbgi, irg, block);
4121 if (node == be_get_old_anchor(anchor_tls)) {
4122 return gen_Proj_tls(node);
4125 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4129 ir_node *new_pred = be_transform_node(pred);
4130 ir_node *block = be_transform_node(get_nodes_block(node));
4131 ir_mode *mode = get_irn_mode(node);
4132 if (mode_needs_gp_reg(mode)) {
4133 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4134 get_Proj_proj(node));
4135 #ifdef DEBUG_libfirm
4136 new_proj->node_nr = node->node_nr;
4142 return be_duplicate_node(node);
4146 * Enters all transform functions into the generic pointer
4148 static void register_transformers(void)
4152 /* first clear the generic function pointer for all ops */
4153 clear_irp_opcodes_generic_func();
4155 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4156 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4193 /* transform ops from intrinsic lowering */
4213 /* GEN(ia32_l_vfist); TODO */
4215 GEN(ia32_l_X87toSSE);
4216 GEN(ia32_l_SSEtoX87);
4221 /* we should never see these nodes */
4236 /* handle generic backend nodes */
4247 /* set the register for all Unknown nodes */
4250 op_Mulh = get_op_Mulh();
4259 * Pre-transform all unknown and noreg nodes.
4261 static void ia32_pretransform_node(void *arch_cg) {
4262 ia32_code_gen_t *cg = arch_cg;
4264 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4265 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4266 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4267 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4268 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4269 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4274 void add_missing_keep_walker(ir_node *node, void *data)
4277 unsigned found_projs = 0;
4278 const ir_edge_t *edge;
4279 ir_mode *mode = get_irn_mode(node);
4284 if(!is_ia32_irn(node))
4287 n_outs = get_ia32_n_res(node);
4290 if(is_ia32_SwitchJmp(node))
4293 assert(n_outs < (int) sizeof(unsigned) * 8);
4294 foreach_out_edge(node, edge) {
4295 ir_node *proj = get_edge_src_irn(edge);
4296 int pn = get_Proj_proj(proj);
4298 assert(pn < n_outs);
4299 found_projs |= 1 << pn;
4303 /* are keeps missing? */
4305 for(i = 0; i < n_outs; ++i) {
4308 const arch_register_req_t *req;
4309 const arch_register_class_t *class;
4311 if(found_projs & (1 << i)) {
4315 req = get_ia32_out_req(node, i);
4321 block = get_nodes_block(node);
4322 in[0] = new_r_Proj(current_ir_graph, block, node,
4323 arch_register_class_mode(class), i);
4324 if(last_keep != NULL) {
4325 be_Keep_add_node(last_keep, class, in[0]);
4327 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4333 * Adds missing keeps to nodes
4336 void add_missing_keeps(ia32_code_gen_t *cg)
4338 ir_graph *irg = be_get_birg_irg(cg->birg);
4339 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4342 /* do the transformation */
4343 void ia32_transform_graph(ia32_code_gen_t *cg) {
4344 register_transformers();
4346 initial_fpcw = NULL;
4347 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4348 edges_verify(cg->irg);
4349 add_missing_keeps(cg);
4350 edges_verify(cg->irg);
4353 void ia32_init_transform(void)
4355 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");