2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
32 #include "../benode_t.h"
33 #include "../besched.h"
36 #include "bearch_ia32_t.h"
37 #include "ia32_nodes_attr.h"
38 #include "ia32_transform.h"
39 #include "ia32_new_nodes.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_dbg_stat.h"
42 #include "ia32_optimize.h"
43 #include "ia32_util.h"
45 #include "gen_ia32_regalloc_if.h"
47 #define SFP_SIGN "0x80000000"
48 #define DFP_SIGN "0x8000000000000000"
49 #define SFP_ABS "0x7FFFFFFF"
50 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
52 #define TP_SFP_SIGN "ia32_sfp_sign"
53 #define TP_DFP_SIGN "ia32_dfp_sign"
54 #define TP_SFP_ABS "ia32_sfp_abs"
55 #define TP_DFP_ABS "ia32_dfp_abs"
57 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
58 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
59 #define ENT_SFP_ABS "IA32_SFP_ABS"
60 #define ENT_DFP_ABS "IA32_DFP_ABS"
62 extern ir_op *get_op_Mulh(void);
64 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op1, ir_node *op2, ir_node *mem);
67 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
68 ir_node *op, ir_node *mem);
71 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
74 /****************************************************************************************************
76 * | | | | / _| | | (_)
77 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
78 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
79 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
80 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
82 ****************************************************************************************************/
85 * Returns 1 if irn is a Const representing 0, 0 otherwise
87 static INLINE int is_ia32_Const_0(ir_node *irn) {
88 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
89 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
93 * Returns 1 if irn is a Const representing 1, 0 otherwise
95 static INLINE int is_ia32_Const_1(ir_node *irn) {
96 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
97 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
101 * Returns the Proj representing the UNKNOWN register for given mode.
103 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
104 be_abi_irg_t *babi = cg->birg->abi;
105 const arch_register_t *unknwn_reg = NULL;
107 if (mode_is_float(mode)) {
108 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
111 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
114 return be_abi_get_callee_save_irn(babi, unknwn_reg);
118 * Gets the Proj with number pn from irn.
120 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
121 const ir_edge_t *edge;
123 assert(get_irn_mode(irn) == mode_T && "need mode_T");
125 foreach_out_edge(irn, edge) {
126 proj = get_edge_src_irn(edge);
128 if (get_Proj_proj(proj) == pn)
136 * SSE convert of an integer node into a floating point node.
138 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
139 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
141 ir_node *noreg = ia32_new_NoReg_gp(cg);
142 ir_node *nomem = new_rd_NoMem(irg);
144 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
145 set_ia32_src_mode(conv, get_irn_mode(in));
146 set_ia32_tgt_mode(conv, tgt_mode);
147 set_ia32_am_support(conv, ia32_am_Source);
148 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
150 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
154 * SSE convert of an float node into a double node.
156 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
157 ir_node *in, ir_node *old_node)
159 ir_node *noreg = ia32_new_NoReg_gp(cg);
160 ir_node *nomem = new_rd_NoMem(irg);
162 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
163 set_ia32_src_mode(conv, mode_F);
164 set_ia32_tgt_mode(conv, mode_D);
165 set_ia32_am_support(conv, ia32_am_Source);
166 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
168 return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res);
171 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
172 static ident *gen_fp_known_const(ia32_known_const_t kct) {
173 static const struct {
175 const char *ent_name;
176 const char *cnst_str;
177 } names [ia32_known_const_max] = {
178 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
179 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
180 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
181 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
183 static struct entity *ent_cache[ia32_known_const_max];
185 const char *tp_name, *ent_name, *cnst_str;
193 ent_name = names[kct].ent_name;
194 if (! ent_cache[kct]) {
195 tp_name = names[kct].tp_name;
196 cnst_str = names[kct].cnst_str;
198 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
199 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
200 tp = new_type_primitive(new_id_from_str(tp_name), mode);
201 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
203 set_entity_ld_ident(ent, get_entity_ident(ent));
204 set_entity_visibility(ent, visibility_local);
205 set_entity_variability(ent, variability_constant);
206 set_entity_allocation(ent, allocation_static);
208 /* we create a new entity here: It's initialization must resist on the
210 rem = current_ir_graph;
211 current_ir_graph = get_const_code_irg();
212 cnst = new_Const(mode, tv);
213 current_ir_graph = rem;
215 set_atomic_ent_value(ent, cnst);
217 /* cache the entry */
218 ent_cache[kct] = ent;
221 return get_entity_ident(ent_cache[kct]);
226 * Prints the old node name on cg obst and returns a pointer to it.
228 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
229 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
231 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
232 obstack_1grow(isa->name_obst, 0);
233 isa->name_obst_size += obstack_object_size(isa->name_obst);
234 return obstack_finish(isa->name_obst);
238 /* determine if one operator is an Imm */
239 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
241 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
242 else return is_ia32_Cnst(op2) ? op2 : NULL;
245 /* determine if one operator is not an Imm */
246 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
247 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
252 * Construct a standard binary operation, set AM and immediate if required.
254 * @param env The transformation environment
255 * @param op1 The first operand
256 * @param op2 The second operand
257 * @param func The node constructor function
258 * @return The constructed ia32 node.
260 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
261 ir_node *new_op = NULL;
262 ir_mode *mode = env->mode;
263 dbg_info *dbg = env->dbg;
264 ir_graph *irg = env->irg;
265 ir_node *block = env->block;
266 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
267 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
268 ir_node *nomem = new_NoMem();
270 ir_node *expr_op, *imm_op;
271 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
273 /* Check if immediate optimization is on and */
274 /* if it's an operation with immediate. */
275 /* Mul/MulS/Mulh don't support immediates */
276 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
277 func == new_rd_ia32_Mul ||
278 func == new_rd_ia32_Mulh ||
279 func == new_rd_ia32_MulS)
283 /* immediate operations are requested, but we are here: it a mul */
284 if (env->cg->opt & IA32_OPT_IMMOPS)
287 else if (is_op_commutative(get_irn_op(env->irn))) {
288 imm_op = get_immediate_op(op1, op2);
289 expr_op = get_expr_op(op1, op2);
292 imm_op = get_immediate_op(NULL, op2);
293 expr_op = get_expr_op(op1, op2);
296 assert((expr_op || imm_op) && "invalid operands");
299 /* We have two consts here: not yet supported */
303 if (mode_is_float(mode)) {
304 /* floating point operations */
306 DB((mod, LEVEL_1, "FP with immediate ..."));
307 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
308 set_ia32_Immop_attr(new_op, imm_op);
309 set_ia32_am_support(new_op, ia32_am_None);
312 DB((mod, LEVEL_1, "FP binop ..."));
313 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
314 set_ia32_am_support(new_op, ia32_am_Source);
316 set_ia32_ls_mode(new_op, mode);
319 /* integer operations */
321 /* This is expr + const */
322 DB((mod, LEVEL_1, "INT with immediate ..."));
323 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
324 set_ia32_Immop_attr(new_op, imm_op);
327 set_ia32_am_support(new_op, ia32_am_Dest);
330 DB((mod, LEVEL_1, "INT binop ..."));
331 /* This is a normal operation */
332 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
335 set_ia32_am_support(new_op, ia32_am_Full);
338 /* Muls can only have AM source */
340 set_ia32_am_support(new_op, ia32_am_Source);
343 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
345 set_ia32_res_mode(new_op, mode);
347 if (is_op_commutative(get_irn_op(env->irn))) {
348 set_ia32_commutative(new_op);
351 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
357 * Construct a shift/rotate binary operation, sets AM and immediate if required.
359 * @param env The transformation environment
360 * @param op1 The first operand
361 * @param op2 The second operand
362 * @param func The node constructor function
363 * @return The constructed ia32 node.
365 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
366 ir_node *new_op = NULL;
367 ir_mode *mode = env->mode;
368 dbg_info *dbg = env->dbg;
369 ir_graph *irg = env->irg;
370 ir_node *block = env->block;
371 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
372 ir_node *nomem = new_NoMem();
373 ir_node *expr_op, *imm_op;
375 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
377 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
379 /* Check if immediate optimization is on and */
380 /* if it's an operation with immediate. */
381 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
382 expr_op = get_expr_op(op1, op2);
384 assert((expr_op || imm_op) && "invalid operands");
387 /* We have two consts here: not yet supported */
391 /* Limit imm_op within range imm8 */
393 tv = get_ia32_Immop_tarval(imm_op);
396 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
397 set_ia32_Immop_tarval(imm_op, tv);
404 /* integer operations */
406 /* This is shift/rot with const */
407 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
409 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
410 set_ia32_Immop_attr(new_op, imm_op);
413 /* This is a normal shift/rot */
414 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
415 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
419 set_ia32_am_support(new_op, ia32_am_Dest);
421 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
423 set_ia32_res_mode(new_op, mode);
424 set_ia32_emit_cl(new_op);
426 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
431 * Construct a standard unary operation, set AM and immediate if required.
433 * @param env The transformation environment
434 * @param op The operand
435 * @param func The node constructor function
436 * @return The constructed ia32 node.
438 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
439 ir_node *new_op = NULL;
440 ir_mode *mode = env->mode;
441 dbg_info *dbg = env->dbg;
442 ir_graph *irg = env->irg;
443 ir_node *block = env->block;
444 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
445 ir_node *nomem = new_NoMem();
446 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
448 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
450 if (mode_is_float(mode)) {
451 DB((mod, LEVEL_1, "FP unop ..."));
452 /* floating point operations don't support implicit store */
453 set_ia32_am_support(new_op, ia32_am_None);
456 DB((mod, LEVEL_1, "INT unop ..."));
457 set_ia32_am_support(new_op, ia32_am_Dest);
460 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
462 set_ia32_res_mode(new_op, mode);
464 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
470 * Creates an ia32 Add with immediate.
472 * @param env The transformation environment
473 * @param expr_op The expression operator
474 * @param const_op The constant
475 * @return the created ia32 Add node
477 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
478 ir_node *new_op = NULL;
479 tarval *tv = get_ia32_Immop_tarval(const_op);
480 dbg_info *dbg = env->dbg;
481 ir_graph *irg = env->irg;
482 ir_node *block = env->block;
483 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
484 ir_node *nomem = new_NoMem();
486 tarval_classification_t class_tv, class_negtv;
487 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
489 /* try to optimize to inc/dec */
490 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
491 /* optimize tarvals */
492 class_tv = classify_tarval(tv);
493 class_negtv = classify_tarval(tarval_neg(tv));
495 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
496 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
497 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
500 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
501 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
502 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
508 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
509 set_ia32_Immop_attr(new_op, const_op);
510 set_ia32_commutative(new_op);
517 * Creates an ia32 Add.
519 * @param env The transformation environment
520 * @return the created ia32 Add node
522 static ir_node *gen_Add(ia32_transform_env_t *env) {
523 ir_node *new_op = NULL;
524 dbg_info *dbg = env->dbg;
525 ir_mode *mode = env->mode;
526 ir_graph *irg = env->irg;
527 ir_node *block = env->block;
528 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
529 ir_node *nomem = new_NoMem();
530 ir_node *expr_op, *imm_op;
531 ir_node *op1 = get_Add_left(env->irn);
532 ir_node *op2 = get_Add_right(env->irn);
534 /* Check if immediate optimization is on and */
535 /* if it's an operation with immediate. */
536 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
537 expr_op = get_expr_op(op1, op2);
539 assert((expr_op || imm_op) && "invalid operands");
541 if (mode_is_float(mode)) {
543 if (USE_SSE2(env->cg))
544 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
546 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
551 /* No expr_op means, that we have two const - one symconst and */
552 /* one tarval or another symconst - because this case is not */
553 /* covered by constant folding */
554 /* We need to check for: */
555 /* 1) symconst + const -> becomes a LEA */
556 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
557 /* linker doesn't support two symconsts */
559 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
560 /* this is the 2nd case */
561 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
562 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
563 set_ia32_am_flavour(new_op, ia32_am_OB);
565 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
568 /* this is the 1st case */
569 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
571 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
573 if (get_ia32_op_type(op1) == ia32_SymConst) {
574 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
575 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
578 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
579 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
581 set_ia32_am_flavour(new_op, ia32_am_O);
585 set_ia32_am_support(new_op, ia32_am_Source);
586 set_ia32_op_type(new_op, ia32_AddrModeS);
588 /* Lea doesn't need a Proj */
592 /* This is expr + const */
593 new_op = gen_imm_Add(env, expr_op, imm_op);
596 set_ia32_am_support(new_op, ia32_am_Dest);
599 /* This is a normal add */
600 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
603 set_ia32_am_support(new_op, ia32_am_Full);
604 set_ia32_commutative(new_op);
608 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
610 set_ia32_res_mode(new_op, mode);
612 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
618 * Creates an ia32 Mul.
620 * @param env The transformation environment
621 * @return the created ia32 Mul node
623 static ir_node *gen_Mul(ia32_transform_env_t *env) {
624 ir_node *op1 = get_Mul_left(env->irn);
625 ir_node *op2 = get_Mul_right(env->irn);
628 if (mode_is_float(env->mode)) {
630 if (USE_SSE2(env->cg))
631 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
633 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
636 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
645 * Creates an ia32 Mulh.
646 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
647 * this result while Mul returns the lower 32 bit.
649 * @param env The transformation environment
650 * @return the created ia32 Mulh node
652 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
653 ir_node *op1 = get_irn_n(env->irn, 0);
654 ir_node *op2 = get_irn_n(env->irn, 1);
655 ir_node *proj_EAX, *proj_EDX, *mulh;
658 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
659 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
660 mulh = get_Proj_pred(proj_EAX);
661 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
663 /* to be on the save side */
664 set_Proj_proj(proj_EAX, pn_EAX);
666 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
667 /* Mulh with const cannot have AM */
668 set_ia32_am_support(mulh, ia32_am_None);
671 /* Mulh cannot have AM for destination */
672 set_ia32_am_support(mulh, ia32_am_Source);
678 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
686 * Creates an ia32 And.
688 * @param env The transformation environment
689 * @return The created ia32 And node
691 static ir_node *gen_And(ia32_transform_env_t *env) {
692 ir_node *op1 = get_And_left(env->irn);
693 ir_node *op2 = get_And_right(env->irn);
695 assert (! mode_is_float(env->mode));
696 return gen_binop(env, op1, op2, new_rd_ia32_And);
702 * Creates an ia32 Or.
704 * @param env The transformation environment
705 * @return The created ia32 Or node
707 static ir_node *gen_Or(ia32_transform_env_t *env) {
708 ir_node *op1 = get_Or_left(env->irn);
709 ir_node *op2 = get_Or_right(env->irn);
711 assert (! mode_is_float(env->mode));
712 return gen_binop(env, op1, op2, new_rd_ia32_Or);
718 * Creates an ia32 Eor.
720 * @param env The transformation environment
721 * @return The created ia32 Eor node
723 static ir_node *gen_Eor(ia32_transform_env_t *env) {
724 ir_node *op1 = get_Eor_left(env->irn);
725 ir_node *op2 = get_Eor_right(env->irn);
727 assert(! mode_is_float(env->mode));
728 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
734 * Creates an ia32 Max.
736 * @param env The transformation environment
737 * @return the created ia32 Max node
739 static ir_node *gen_Max(ia32_transform_env_t *env) {
740 ir_node *op1 = get_irn_n(env->irn, 0);
741 ir_node *op2 = get_irn_n(env->irn, 1);
744 if (mode_is_float(env->mode)) {
746 if (USE_SSE2(env->cg))
747 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
753 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
754 set_ia32_am_support(new_op, ia32_am_None);
755 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
764 * Creates an ia32 Min.
766 * @param env The transformation environment
767 * @return the created ia32 Min node
769 static ir_node *gen_Min(ia32_transform_env_t *env) {
770 ir_node *op1 = get_irn_n(env->irn, 0);
771 ir_node *op2 = get_irn_n(env->irn, 1);
774 if (mode_is_float(env->mode)) {
776 if (USE_SSE2(env->cg))
777 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
783 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
784 set_ia32_am_support(new_op, ia32_am_None);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
794 * Creates an ia32 Sub with immediate.
796 * @param env The transformation environment
797 * @param expr_op The first operator
798 * @param const_op The constant operator
799 * @return The created ia32 Sub node
801 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
802 ir_node *new_op = NULL;
803 tarval *tv = get_ia32_Immop_tarval(const_op);
804 dbg_info *dbg = env->dbg;
805 ir_graph *irg = env->irg;
806 ir_node *block = env->block;
807 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
808 ir_node *nomem = new_NoMem();
810 tarval_classification_t class_tv, class_negtv;
811 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
813 /* try to optimize to inc/dec */
814 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
815 /* optimize tarvals */
816 class_tv = classify_tarval(tv);
817 class_negtv = classify_tarval(tarval_neg(tv));
819 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
820 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
821 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
824 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
825 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
826 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
832 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
833 set_ia32_Immop_attr(new_op, const_op);
840 * Creates an ia32 Sub.
842 * @param env The transformation environment
843 * @return The created ia32 Sub node
845 static ir_node *gen_Sub(ia32_transform_env_t *env) {
846 ir_node *new_op = NULL;
847 dbg_info *dbg = env->dbg;
848 ir_mode *mode = env->mode;
849 ir_graph *irg = env->irg;
850 ir_node *block = env->block;
851 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
852 ir_node *nomem = new_NoMem();
853 ir_node *op1 = get_Sub_left(env->irn);
854 ir_node *op2 = get_Sub_right(env->irn);
855 ir_node *expr_op, *imm_op;
857 /* Check if immediate optimization is on and */
858 /* if it's an operation with immediate. */
859 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
860 expr_op = get_expr_op(op1, op2);
862 assert((expr_op || imm_op) && "invalid operands");
864 if (mode_is_float(mode)) {
866 if (USE_SSE2(env->cg))
867 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
869 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
874 /* No expr_op means, that we have two const - one symconst and */
875 /* one tarval or another symconst - because this case is not */
876 /* covered by constant folding */
877 /* We need to check for: */
878 /* 1) symconst - const -> becomes a LEA */
879 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
880 /* linker doesn't support two symconsts */
882 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
883 /* this is the 2nd case */
884 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
885 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
886 set_ia32_am_sc_sign(new_op);
887 set_ia32_am_flavour(new_op, ia32_am_OB);
889 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
892 /* this is the 1st case */
893 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
895 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
897 if (get_ia32_op_type(op1) == ia32_SymConst) {
898 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
899 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
902 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
903 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
904 set_ia32_am_sc_sign(new_op);
906 set_ia32_am_flavour(new_op, ia32_am_O);
910 set_ia32_am_support(new_op, ia32_am_Source);
911 set_ia32_op_type(new_op, ia32_AddrModeS);
913 /* Lea doesn't need a Proj */
917 /* This is expr - const */
918 new_op = gen_imm_Sub(env, expr_op, imm_op);
921 set_ia32_am_support(new_op, ia32_am_Dest);
924 /* This is a normal sub */
925 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
928 set_ia32_am_support(new_op, ia32_am_Full);
932 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
934 set_ia32_res_mode(new_op, mode);
936 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
942 * Generates an ia32 DivMod with additional infrastructure for the
943 * register allocator if needed.
945 * @param env The transformation environment
946 * @param dividend -no comment- :)
947 * @param divisor -no comment- :)
948 * @param dm_flav flavour_Div/Mod/DivMod
949 * @return The created ia32 DivMod node
951 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
953 ir_node *edx_node, *cltd;
955 dbg_info *dbg = env->dbg;
956 ir_graph *irg = env->irg;
957 ir_node *block = env->block;
958 ir_mode *mode = env->mode;
959 ir_node *irn = env->irn;
965 mem = get_Div_mem(irn);
966 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
969 mem = get_Mod_mem(irn);
970 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
973 mem = get_DivMod_mem(irn);
974 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
980 if (mode_is_signed(mode)) {
981 /* in signed mode, we need to sign extend the dividend */
982 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
983 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
984 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
987 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
988 set_ia32_Const_type(edx_node, ia32_Const);
989 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
992 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
994 set_ia32_n_res(res, 2);
996 /* Only one proj is used -> We must add a second proj and */
997 /* connect this one to a Keep node to eat up the second */
998 /* destroyed register. */
999 n = get_irn_n_edges(irn);
1002 proj = ia32_get_proj_for_mode(irn, mode_M);
1004 /* in case of two projs, one must be the memory proj */
1005 if (n == 1 || (n == 2 && proj)) {
1006 proj = ia32_get_res_proj(irn);
1007 assert(proj && "Result proj expected");
1009 if (get_irn_op(irn) == op_Div) {
1010 set_Proj_proj(proj, pn_DivMod_res_div);
1011 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
1014 set_Proj_proj(proj, pn_DivMod_res_mod);
1015 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
1018 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1021 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1023 set_ia32_res_mode(res, mode);
1030 * Wrapper for generate_DivMod. Sets flavour_Mod.
1032 * @param env The transformation environment
1034 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1035 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1039 * Wrapper for generate_DivMod. Sets flavour_Div.
1041 * @param env The transformation environment
1043 static ir_node *gen_Div(ia32_transform_env_t *env) {
1044 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1048 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1050 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1051 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1057 * Creates an ia32 floating Div.
1059 * @param env The transformation environment
1060 * @return The created ia32 xDiv node
1062 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1063 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1065 ir_node *nomem = new_rd_NoMem(env->irg);
1066 ir_node *op1 = get_Quot_left(env->irn);
1067 ir_node *op2 = get_Quot_right(env->irn);
1070 if (USE_SSE2(env->cg)) {
1071 if (is_ia32_xConst(op2)) {
1072 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1073 set_ia32_am_support(new_op, ia32_am_None);
1074 set_ia32_Immop_attr(new_op, op2);
1077 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1078 set_ia32_am_support(new_op, ia32_am_Source);
1082 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1083 set_ia32_am_support(new_op, ia32_am_Source);
1085 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1086 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1094 * Creates an ia32 Shl.
1096 * @param env The transformation environment
1097 * @return The created ia32 Shl node
1099 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1100 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1106 * Creates an ia32 Shr.
1108 * @param env The transformation environment
1109 * @return The created ia32 Shr node
1111 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1112 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1118 * Creates an ia32 Shrs.
1120 * @param env The transformation environment
1121 * @return The created ia32 Shrs node
1123 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1124 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1130 * Creates an ia32 RotL.
1132 * @param env The transformation environment
1133 * @param op1 The first operator
1134 * @param op2 The second operator
1135 * @return The created ia32 RotL node
1137 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1138 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1144 * Creates an ia32 RotR.
1145 * NOTE: There is no RotR with immediate because this would always be a RotL
1146 * "imm-mode_size_bits" which can be pre-calculated.
1148 * @param env The transformation environment
1149 * @param op1 The first operator
1150 * @param op2 The second operator
1151 * @return The created ia32 RotR node
1153 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1154 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1160 * Creates an ia32 RotR or RotL (depending on the found pattern).
1162 * @param env The transformation environment
1163 * @return The created ia32 RotL or RotR node
1165 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1166 ir_node *rotate = NULL;
1167 ir_node *op1 = get_Rot_left(env->irn);
1168 ir_node *op2 = get_Rot_right(env->irn);
1170 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1171 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1172 that means we can create a RotR instead of an Add and a RotL */
1175 ir_node *pred = get_Proj_pred(op2);
1177 if (is_ia32_Add(pred)) {
1178 ir_node *pred_pred = get_irn_n(pred, 2);
1179 tarval *tv = get_ia32_Immop_tarval(pred);
1180 long bits = get_mode_size_bits(env->mode);
1182 if (is_Proj(pred_pred)) {
1183 pred_pred = get_Proj_pred(pred_pred);
1186 if (is_ia32_Minus(pred_pred) &&
1187 tarval_is_long(tv) &&
1188 get_tarval_long(tv) == bits)
1190 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1191 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1198 rotate = gen_RotL(env, op1, op2);
1207 * Transforms a Minus node.
1209 * @param env The transformation environment
1210 * @param op The Minus operand
1211 * @return The created ia32 Minus node
1213 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1218 if (mode_is_float(env->mode)) {
1220 if (USE_SSE2(env->cg)) {
1221 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1222 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1223 ir_node *nomem = new_rd_NoMem(env->irg);
1225 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1227 size = get_mode_size_bits(env->mode);
1228 name = gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1230 set_ia32_am_sc(new_op, name);
1232 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1234 set_ia32_res_mode(new_op, env->mode);
1235 set_ia32_op_type(new_op, ia32_AddrModeS);
1236 set_ia32_ls_mode(new_op, env->mode);
1238 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1241 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1242 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1246 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1253 * Transforms a Minus node.
1255 * @param env The transformation environment
1256 * @return The created ia32 Minus node
1258 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1259 return gen_Minus_ex(env, get_Minus_op(env->irn));
1264 * Transforms a Not node.
1266 * @param env The transformation environment
1267 * @return The created ia32 Not node
1269 static ir_node *gen_Not(ia32_transform_env_t *env) {
1270 assert (! mode_is_float(env->mode));
1271 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1277 * Transforms an Abs node.
1279 * @param env The transformation environment
1280 * @return The created ia32 Abs node
1282 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1283 ir_node *res, *p_eax, *p_edx;
1284 dbg_info *dbg = env->dbg;
1285 ir_mode *mode = env->mode;
1286 ir_graph *irg = env->irg;
1287 ir_node *block = env->block;
1288 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1289 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1290 ir_node *nomem = new_NoMem();
1291 ir_node *op = get_Abs_op(env->irn);
1295 if (mode_is_float(mode)) {
1297 if (USE_SSE2(env->cg)) {
1298 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1300 size = get_mode_size_bits(mode);
1301 name = gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1303 set_ia32_am_sc(res, name);
1305 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1307 set_ia32_res_mode(res, mode);
1308 set_ia32_op_type(res, ia32_AddrModeS);
1309 set_ia32_ls_mode(res, env->mode);
1311 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1314 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1315 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1319 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1321 set_ia32_res_mode(res, mode);
1323 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1324 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1326 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1327 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1328 set_ia32_res_mode(res, mode);
1330 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1332 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1333 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1334 set_ia32_res_mode(res, mode);
1336 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1345 * Transforms a Load.
1347 * @param env The transformation environment
1348 * @return the created ia32 Load node
1350 static ir_node *gen_Load(ia32_transform_env_t *env) {
1351 ir_node *node = env->irn;
1352 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1353 ir_node *ptr = get_Load_ptr(node);
1354 ir_node *lptr = ptr;
1355 ir_mode *mode = get_Load_mode(node);
1358 ia32_am_flavour_t am_flav = ia32_am_B;
1360 /* address might be a constant (symconst or absolute address) */
1361 if (is_ia32_Const(ptr)) {
1366 if (mode_is_float(mode)) {
1368 if (USE_SSE2(env->cg))
1369 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1371 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1374 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1377 /* base is an constant address */
1379 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1380 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1381 am_flav = ia32_am_N;
1384 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1385 am_flav = ia32_am_O;
1389 set_ia32_am_support(new_op, ia32_am_Source);
1390 set_ia32_op_type(new_op, ia32_AddrModeS);
1391 set_ia32_am_flavour(new_op, am_flav);
1392 set_ia32_ls_mode(new_op, mode);
1395 check for special case: the loaded value might not be used (optimized, volatile, ...)
1396 we add a Proj + Keep for volatile loads and ignore all other cases
1398 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1399 /* add a result proj and a Keep to produce a pseudo use */
1400 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1401 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1404 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1412 * Transforms a Store.
1414 * @param env The transformation environment
1415 * @return the created ia32 Store node
1417 static ir_node *gen_Store(ia32_transform_env_t *env) {
1418 ir_node *node = env->irn;
1419 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1420 ir_node *val = get_Store_value(node);
1421 ir_node *ptr = get_Store_ptr(node);
1422 ir_node *sptr = ptr;
1423 ir_node *mem = get_Store_mem(node);
1424 ir_mode *mode = get_irn_mode(val);
1425 ir_node *sval = val;
1428 ia32_am_flavour_t am_flav = ia32_am_B;
1429 ia32_immop_type_t immop = ia32_ImmNone;
1431 if (! mode_is_float(mode)) {
1432 /* in case of storing a const (but not a symconst) -> make it an attribute */
1433 if (is_ia32_Cnst(val)) {
1434 switch (get_ia32_op_type(val)) {
1436 immop = ia32_ImmConst;
1439 immop = ia32_ImmSymConst;
1442 assert(0 && "unsupported Const type");
1448 /* address might be a constant (symconst or absolute address) */
1449 if (is_ia32_Const(ptr)) {
1454 if (mode_is_float(mode)) {
1456 if (USE_SSE2(env->cg))
1457 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1459 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1461 else if (get_mode_size_bits(mode) == 8) {
1462 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1465 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1468 /* stored const is an attribute (saves a register) */
1469 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1470 set_ia32_Immop_attr(new_op, val);
1473 /* base is an constant address */
1475 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1476 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1477 am_flav = ia32_am_N;
1480 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1481 am_flav = ia32_am_O;
1485 set_ia32_am_support(new_op, ia32_am_Dest);
1486 set_ia32_op_type(new_op, ia32_AddrModeD);
1487 set_ia32_am_flavour(new_op, am_flav);
1488 set_ia32_ls_mode(new_op, mode);
1489 set_ia32_immop_type(new_op, immop);
1491 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1499 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1501 * @param env The transformation environment
1502 * @return The transformed node.
1504 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1505 dbg_info *dbg = env->dbg;
1506 ir_graph *irg = env->irg;
1507 ir_node *block = env->block;
1508 ir_node *node = env->irn;
1509 ir_node *sel = get_Cond_selector(node);
1510 ir_mode *sel_mode = get_irn_mode(sel);
1511 ir_node *res = NULL;
1512 ir_node *pred = NULL;
1513 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1514 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1516 if (is_Proj(sel) && sel_mode == mode_b) {
1517 ir_node *nomem = new_NoMem();
1519 pred = get_Proj_pred(sel);
1521 /* get both compare operators */
1522 cmp_a = get_Cmp_left(pred);
1523 cmp_b = get_Cmp_right(pred);
1525 /* check if we can use a CondJmp with immediate */
1526 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1527 expr = get_expr_op(cmp_a, cmp_b);
1530 pn_Cmp pnc = get_Proj_proj(sel);
1532 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1533 if (get_ia32_op_type(cnst) == ia32_Const &&
1534 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1536 /* a Cmp A =/!= 0 */
1537 ir_node *op1 = expr;
1538 ir_node *op2 = expr;
1539 ir_node *and = skip_Proj(expr);
1540 const char *cnst = NULL;
1542 /* check, if expr is an only once used And operation */
1543 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1544 op1 = get_irn_n(and, 2);
1545 op2 = get_irn_n(and, 3);
1547 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1549 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1550 set_ia32_pncode(res, get_Proj_proj(sel));
1551 set_ia32_res_mode(res, get_irn_mode(op1));
1554 copy_ia32_Immop_attr(res, and);
1557 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1562 if (mode_is_float(get_irn_mode(expr))) {
1564 if (USE_SSE2(env->cg))
1565 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1571 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1573 set_ia32_Immop_attr(res, cnst);
1574 set_ia32_res_mode(res, get_irn_mode(expr));
1577 if (mode_is_float(get_irn_mode(cmp_a))) {
1579 if (USE_SSE2(env->cg))
1580 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1583 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1584 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1585 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1589 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1590 set_ia32_commutative(res);
1592 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1595 set_ia32_pncode(res, get_Proj_proj(sel));
1596 //set_ia32_am_support(res, ia32_am_Source);
1599 /* determine the smallest switch case value */
1600 int switch_min = INT_MAX;
1601 const ir_edge_t *edge;
1604 foreach_out_edge(node, edge) {
1605 int pn = get_Proj_proj(get_edge_src_irn(edge));
1606 switch_min = pn < switch_min ? pn : switch_min;
1610 /* if smallest switch case is not 0 we need an additional sub */
1611 snprintf(buf, sizeof(buf), "%d", switch_min);
1612 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1613 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1614 sub_ia32_am_offs(res, buf);
1615 set_ia32_am_flavour(res, ia32_am_OB);
1616 set_ia32_am_support(res, ia32_am_Source);
1617 set_ia32_op_type(res, ia32_AddrModeS);
1620 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1621 set_ia32_pncode(res, get_Cond_defaultProj(node));
1622 set_ia32_res_mode(res, get_irn_mode(sel));
1625 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1632 * Transforms a CopyB node.
1634 * @param env The transformation environment
1635 * @return The transformed node.
1637 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1638 ir_node *res = NULL;
1639 dbg_info *dbg = env->dbg;
1640 ir_graph *irg = env->irg;
1641 ir_node *block = env->block;
1642 ir_node *node = env->irn;
1643 ir_node *src = get_CopyB_src(node);
1644 ir_node *dst = get_CopyB_dst(node);
1645 ir_node *mem = get_CopyB_mem(node);
1646 int size = get_type_size_bytes(get_CopyB_type(node));
1647 ir_mode *dst_mode = get_irn_mode(dst);
1648 ir_mode *src_mode = get_irn_mode(src);
1650 ir_node *in[3], *tmp;
1652 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1653 /* then we need the size explicitly in ECX. */
1654 if (size >= 32 * 4) {
1655 rem = size & 0x3; /* size % 4 */
1658 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1659 set_ia32_op_type(res, ia32_Const);
1660 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1662 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
1663 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1665 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1666 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1667 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1668 in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
1669 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1671 tmp = ia32_get_proj_for_mode(node, mode_M);
1672 set_Proj_proj(tmp, pn_ia32_CopyB_M);
1675 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
1676 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1677 set_ia32_immop_type(res, ia32_ImmConst);
1679 /* ok: now attach Proj's because movsd will destroy esi and edi */
1680 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1681 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1682 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1684 tmp = ia32_get_proj_for_mode(node, mode_M);
1685 set_Proj_proj(tmp, pn_ia32_CopyB_i_M);
1688 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1696 * Transforms a Mux node into CMov.
1698 * @param env The transformation environment
1699 * @return The transformed node.
1701 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1703 ir_node *node = env->irn;
1704 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1705 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1707 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1714 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1715 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1718 * Transforms a Psi node into CMov.
1720 * @param env The transformation environment
1721 * @return The transformed node.
1723 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1724 ia32_code_gen_t *cg = env->cg;
1725 dbg_info *dbg = env->dbg;
1726 ir_graph *irg = env->irg;
1727 ir_mode *mode = env->mode;
1728 ir_node *block = env->block;
1729 ir_node *node = env->irn;
1730 ir_node *cmp_proj = get_Mux_sel(node);
1731 ir_node *psi_true = get_Psi_val(node, 0);
1732 ir_node *psi_default = get_Psi_default(node);
1733 ir_node *noreg = ia32_new_NoReg_gp(cg);
1734 ir_node *nomem = new_rd_NoMem(irg);
1735 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1738 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1740 cmp = get_Proj_pred(cmp_proj);
1741 cmp_a = get_Cmp_left(cmp);
1742 cmp_b = get_Cmp_right(cmp);
1743 pnc = get_Proj_proj(cmp_proj);
1745 if (mode_is_float(mode)) {
1746 /* floating point psi */
1749 /* 1st case: compare operands are float too */
1751 /* psi(cmp(a, b), t, f) can be done as: */
1752 /* tmp = cmp a, b */
1753 /* tmp2 = t and tmp */
1754 /* tmp3 = f and not tmp */
1755 /* res = tmp2 or tmp3 */
1757 /* in case the compare operands are int, we move them into xmm register */
1758 if (! mode_is_float(get_irn_mode(cmp_a))) {
1759 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1760 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1762 pnc |= 8; /* transform integer compare to fp compare */
1765 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1766 set_ia32_pncode(new_op, pnc);
1767 set_ia32_am_support(new_op, ia32_am_Source);
1768 set_ia32_res_mode(new_op, mode);
1769 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1770 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1772 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1773 set_ia32_am_support(and1, ia32_am_None);
1774 set_ia32_res_mode(and1, mode);
1775 set_ia32_commutative(and1);
1776 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1777 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1779 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1780 set_ia32_am_support(and2, ia32_am_None);
1781 set_ia32_res_mode(and2, mode);
1782 set_ia32_commutative(and2);
1783 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1784 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1786 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1787 set_ia32_am_support(new_op, ia32_am_None);
1788 set_ia32_res_mode(new_op, mode);
1789 set_ia32_commutative(new_op);
1790 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1791 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1795 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1796 set_ia32_pncode(new_op, pnc);
1797 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1802 construct_binop_func *set_func = NULL;
1803 cmov_func_t *cmov_func = NULL;
1805 if (mode_is_float(get_irn_mode(cmp_a))) {
1806 /* 1st case: compare operands are floats */
1811 set_func = new_rd_ia32_xCmpSet;
1812 cmov_func = new_rd_ia32_xCmpCMov;
1816 set_func = new_rd_ia32_vfCmpSet;
1817 cmov_func = new_rd_ia32_vfCmpCMov;
1820 pnc &= 7; /* fp compare -> int compare */
1823 /* 2nd case: compare operand are integer too */
1824 set_func = new_rd_ia32_CmpSet;
1825 cmov_func = new_rd_ia32_CmpCMov;
1828 /* create the nodes */
1830 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1831 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1832 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1833 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1834 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1835 set_ia32_pncode(new_op, pnc);
1837 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1838 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1839 /* we invert condition and set default to 0 */
1840 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1841 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1844 /* otherwise: use CMOVcc */
1845 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1846 set_ia32_pncode(new_op, pnc);
1849 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1853 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1854 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1855 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1856 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1857 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1859 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1860 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1861 /* we invert condition and set default to 0 */
1862 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1863 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1864 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1867 /* otherwise: use CMOVcc */
1868 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1869 set_ia32_pncode(new_op, pnc);
1870 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1880 * Following conversion rules apply:
1884 * 1) n bit -> m bit n > m (downscale)
1885 * a) target is signed: movsx
1886 * b) target is unsigned: and with lower bits sets
1887 * 2) n bit -> m bit n == m (sign change)
1889 * 3) n bit -> m bit n < m (upscale)
1890 * a) source is signed: movsx
1891 * b) source is unsigned: and with lower bits sets
1895 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1899 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1900 * if target mode < 32bit: additional INT -> INT conversion (see above)
1904 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1905 * x87 is mode_E internally, conversions happen only at load and store
1906 * in non-strict semantic
1910 * Create a conversion from x87 state register to general purpose.
1912 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1913 ia32_code_gen_t *cg = env->cg;
1914 entity *ent = cg->fp_to_gp;
1915 ir_graph *irg = env->irg;
1916 ir_node *block = env->block;
1917 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1918 ir_node *op = get_Conv_op(env->irn);
1919 ir_node *fist, *mem, *load;
1922 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1923 ent = cg->fp_to_gp =
1924 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1928 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1930 set_ia32_frame_ent(fist, ent);
1931 set_ia32_use_frame(fist);
1932 set_ia32_am_support(fist, ia32_am_Dest);
1933 set_ia32_op_type(fist, ia32_AddrModeD);
1934 set_ia32_am_flavour(fist, ia32_B);
1935 set_ia32_ls_mode(fist, mode_F);
1937 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1940 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1942 set_ia32_frame_ent(load, ent);
1943 set_ia32_use_frame(load);
1944 set_ia32_am_support(load, ia32_am_Source);
1945 set_ia32_op_type(load, ia32_AddrModeS);
1946 set_ia32_am_flavour(load, ia32_B);
1947 set_ia32_ls_mode(load, tgt_mode);
1949 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1953 * Create a conversion from x87 state register to general purpose.
1955 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1956 ia32_code_gen_t *cg = env->cg;
1957 entity *ent = cg->gp_to_fp;
1958 ir_graph *irg = env->irg;
1959 ir_node *block = env->block;
1960 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1961 ir_node *nomem = get_irg_no_mem(irg);
1962 ir_node *op = get_Conv_op(env->irn);
1963 ir_node *fild, *store, *mem;
1967 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1968 ent = cg->gp_to_fp =
1969 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1972 /* first convert to 32 bit */
1973 src_bits = get_mode_size_bits(src_mode);
1974 if (src_bits == 8) {
1975 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1976 op = new_r_Proj(irg, block, op, mode_Is, 0);
1978 else if (src_bits < 32) {
1979 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1980 op = new_r_Proj(irg, block, op, mode_Is, 0);
1984 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1986 set_ia32_frame_ent(store, ent);
1987 set_ia32_use_frame(store);
1989 set_ia32_am_support(store, ia32_am_Dest);
1990 set_ia32_op_type(store, ia32_AddrModeD);
1991 set_ia32_am_flavour(store, ia32_B);
1992 set_ia32_ls_mode(store, mode_Is);
1994 mem = new_r_Proj(irg, block, store, mode_M, 0);
1997 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1999 set_ia32_frame_ent(fild, ent);
2000 set_ia32_use_frame(fild);
2001 set_ia32_am_support(fild, ia32_am_Source);
2002 set_ia32_op_type(fild, ia32_AddrModeS);
2003 set_ia32_am_flavour(fild, ia32_B);
2004 set_ia32_ls_mode(fild, mode_F);
2006 return new_r_Proj(irg, block, fild, mode_F, 0);
2010 * Transforms a Conv node.
2012 * @param env The transformation environment
2013 * @return The created ia32 Conv node
2015 static ir_node *gen_Conv(ia32_transform_env_t *env) {
2016 dbg_info *dbg = env->dbg;
2017 ir_graph *irg = env->irg;
2018 ir_node *op = get_Conv_op(env->irn);
2019 ir_mode *src_mode = get_irn_mode(op);
2020 ir_mode *tgt_mode = env->mode;
2021 int src_bits = get_mode_size_bits(src_mode);
2022 int tgt_bits = get_mode_size_bits(tgt_mode);
2025 ir_node *block = env->block;
2026 ir_node *new_op = NULL;
2027 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2028 ir_node *nomem = new_rd_NoMem(irg);
2030 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2032 if (src_mode == tgt_mode) {
2033 /* this can happen when changing mode_P to mode_Is */
2034 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2035 edges_reroute(env->irn, op, irg);
2037 else if (mode_is_float(src_mode)) {
2038 /* we convert from float ... */
2039 if (mode_is_float(tgt_mode)) {
2041 if (USE_SSE2(env->cg)) {
2042 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2043 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2044 pn = pn_ia32_Conv_FP2FP_res;
2047 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2049 remark: we create a intermediate conv here, so modes will be spread correctly
2050 these convs will be killed later
2052 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2053 pn = pn_ia32_Conv_FP2FP_res;
2059 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2060 if (USE_SSE2(env->cg)) {
2061 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2062 pn = pn_ia32_Conv_FP2I_res;
2065 return gen_x87_fp_to_gp(env, tgt_mode);
2067 /* if target mode is not int: add an additional downscale convert */
2068 if (tgt_bits < 32) {
2069 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2070 set_ia32_am_support(new_op, ia32_am_Source);
2071 set_ia32_tgt_mode(new_op, tgt_mode);
2072 set_ia32_src_mode(new_op, src_mode);
2074 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2076 if (tgt_bits == 8 || src_bits == 8) {
2077 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2078 pn = pn_ia32_Conv_I2I8Bit_res;
2081 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2082 pn = pn_ia32_Conv_I2I_res;
2088 /* we convert from int ... */
2089 if (mode_is_float(tgt_mode)) {
2092 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2093 if (USE_SSE2(env->cg)) {
2094 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2095 pn = pn_ia32_Conv_I2FP_res;
2098 return gen_x87_gp_to_fp(env, src_mode);
2102 if (get_mode_size_bits(src_mode) == tgt_bits) {
2103 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2105 remark: we create a intermediate conv here, so modes will be spread correctly
2106 these convs will be killed later
2108 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2109 pn = pn_ia32_Conv_I2I_res;
2113 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2114 if (tgt_bits == 8 || src_bits == 8) {
2115 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2116 pn = pn_ia32_Conv_I2I8Bit_res;
2119 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2120 pn = pn_ia32_Conv_I2I_res;
2127 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2128 set_ia32_tgt_mode(new_op, tgt_mode);
2129 set_ia32_src_mode(new_op, src_mode);
2131 set_ia32_am_support(new_op, ia32_am_Source);
2133 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2136 nodeset_insert(env->cg->kill_conv, new_op);
2144 /********************************************
2147 * | |__ ___ _ __ ___ __| | ___ ___
2148 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2149 * | |_) | __/ | | | (_) | (_| | __/\__ \
2150 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2152 ********************************************/
2156 * Decides in which block the transformed StackParam should be placed.
2157 * If the StackParam has more than one user, the dominator block of
2158 * the users will be returned. In case of only one user, this is either
2159 * the user block or, in case of a Phi, the predecessor block of the Phi.
2161 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2162 ir_node *dom_bl = NULL;
2164 if (get_irn_n_edges(irn) == 1) {
2165 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2167 if (! is_Phi(src)) {
2168 dom_bl = get_nodes_block(src);
2171 /* Determine on which in position of the Phi the irn is */
2172 /* and get the corresponding cfg predecessor block. */
2174 int i = get_irn_pred_pos(src, irn);
2175 assert(i >= 0 && "kaputt");
2176 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2180 dom_bl = node_users_smallest_common_dominator(irn, 1);
2183 assert(dom_bl && "dominator block not found");
2189 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2190 ir_node *new_op = NULL;
2191 ir_node *node = env->irn;
2192 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2193 ir_node *mem = new_rd_NoMem(env->irg);
2194 ir_node *ptr = get_irn_n(node, 0);
2195 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2196 ir_mode *mode = env->mode;
2198 /* choose the block where to place the load */
2199 //env->block = get_block_transformed_stack_param(node);
2201 if (mode_is_float(mode)) {
2203 if (USE_SSE2(env->cg))
2204 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2206 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2209 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2212 set_ia32_frame_ent(new_op, ent);
2213 set_ia32_use_frame(new_op);
2215 set_ia32_am_support(new_op, ia32_am_Source);
2216 set_ia32_op_type(new_op, ia32_AddrModeS);
2217 set_ia32_am_flavour(new_op, ia32_B);
2218 set_ia32_ls_mode(new_op, mode);
2219 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2221 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2223 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2227 * Transforms a FrameAddr into an ia32 Add.
2229 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2230 ir_node *new_op = NULL;
2231 ir_node *node = env->irn;
2232 ir_node *op = get_irn_n(node, 0);
2233 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2234 ir_node *nomem = new_rd_NoMem(env->irg);
2236 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2237 set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node));
2238 set_ia32_am_support(new_op, ia32_am_Full);
2239 set_ia32_use_frame(new_op);
2240 set_ia32_immop_type(new_op, ia32_ImmConst);
2241 set_ia32_commutative(new_op);
2243 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2245 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2249 * Transforms a FrameLoad into an ia32 Load.
2251 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2252 ir_node *new_op = NULL;
2253 ir_node *node = env->irn;
2254 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2255 ir_node *mem = get_irn_n(node, 0);
2256 ir_node *ptr = get_irn_n(node, 1);
2257 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2258 ir_mode *mode = get_type_mode(get_entity_type(ent));
2260 if (mode_is_float(mode)) {
2262 if (USE_SSE2(env->cg))
2263 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2265 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2268 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2270 set_ia32_frame_ent(new_op, ent);
2271 set_ia32_use_frame(new_op);
2273 set_ia32_am_support(new_op, ia32_am_Source);
2274 set_ia32_op_type(new_op, ia32_AddrModeS);
2275 set_ia32_am_flavour(new_op, ia32_B);
2276 set_ia32_ls_mode(new_op, mode);
2278 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2285 * Transforms a FrameStore into an ia32 Store.
2287 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2288 ir_node *new_op = NULL;
2289 ir_node *node = env->irn;
2290 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2291 ir_node *mem = get_irn_n(node, 0);
2292 ir_node *ptr = get_irn_n(node, 1);
2293 ir_node *val = get_irn_n(node, 2);
2294 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2295 ir_mode *mode = get_irn_mode(val);
2297 if (mode_is_float(mode)) {
2299 if (USE_SSE2(env->cg))
2300 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2302 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2304 else if (get_mode_size_bits(mode) == 8) {
2305 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2308 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2311 set_ia32_frame_ent(new_op, ent);
2312 set_ia32_use_frame(new_op);
2314 set_ia32_am_support(new_op, ia32_am_Dest);
2315 set_ia32_op_type(new_op, ia32_AddrModeD);
2316 set_ia32_am_flavour(new_op, ia32_B);
2317 set_ia32_ls_mode(new_op, mode);
2319 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2325 * In case SSE is used we need to copy the result from FPU TOS.
2327 static ir_node *gen_be_Call(ia32_transform_env_t *env) {
2328 ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
2329 ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
2332 if (! call_res || ! USE_SSE2(env->cg))
2335 mode = get_irn_mode(call_res);
2337 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2339 call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular);
2341 if (mode_is_float(mode)) {
2342 /* store st(0) onto stack */
2343 ir_node *frame = get_irg_frame(env->irg);
2344 ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
2345 ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
2346 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2347 ir_node *sse_load, *p, *bad, *keep;
2351 set_ia32_ls_mode(fstp, mode);
2352 set_ia32_op_type(fstp, ia32_AddrModeD);
2353 set_ia32_use_frame(fstp);
2354 set_ia32_frame_ent(fstp, ent);
2355 set_ia32_am_flavour(fstp, ia32_B);
2356 set_ia32_am_support(fstp, ia32_am_Dest);
2358 /* load into SSE register */
2359 sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
2360 set_ia32_ls_mode(sse_load, mode);
2361 set_ia32_op_type(sse_load, ia32_AddrModeS);
2362 set_ia32_use_frame(sse_load);
2363 set_ia32_frame_ent(sse_load, ent);
2364 set_ia32_am_flavour(sse_load, ia32_B);
2365 set_ia32_am_support(sse_load, ia32_am_Source);
2366 sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
2368 /* reroute all users of the result proj to the sse load */
2369 edges_reroute(call_res, sse_load, env->irg);
2371 /* now: create new Keep whith all former ins and one additional in - the result Proj */
2373 /* get a Proj representing a caller save register */
2374 p = get_proj_for_pn(env->irn, pn_be_Call_first_res + 1);
2375 assert(is_Proj(p) && "Proj expected.");
2377 /* user of the the proj is the Keep */
2378 p = get_edge_src_irn(get_irn_out_edge_first(p));
2379 assert(be_is_Keep(p) && "Keep expected.");
2381 /* copy in array of the old keep and set the result proj as additional in */
2382 keep_arity = get_irn_arity(p) + 1;
2383 NEW_ARR_A(ir_node *, in_keep, keep_arity);
2384 in_keep[keep_arity - 1] = call_res;
2385 for (i = 0; i < keep_arity - 1; ++i)
2386 in_keep[i] = get_irn_n(p, i);
2388 /* create new keep and set the in class requirements properly */
2389 keep = be_new_Keep(NULL, env->irg, env->block, keep_arity, in_keep);
2390 for(i = 0; i < keep_arity; ++i) {
2391 const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
2392 be_node_set_reg_class(keep, i, cls);
2395 /* kill the old keep */
2396 bad = get_irg_bad(env->irg);
2397 for (i = 0; i < keep_arity - 1; i++)
2398 set_irn_n(p, i, bad);
2405 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2407 static ir_node *gen_be_Return(ia32_transform_env_t *env) {
2408 ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
2409 ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
2410 entity *ent = get_irg_entity(get_irn_irg(ret_val));
2411 ir_type *tp = get_entity_type(ent);
2413 if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
2417 if (get_method_n_ress(tp) == 1) {
2418 ir_type *res_type = get_method_res_type(tp, 0);
2421 if(is_Primitive_type(res_type)) {
2422 mode = get_type_mode(res_type);
2423 if(mode_is_float(mode)) {
2424 ir_node *frame = get_irg_frame(env->irg);
2425 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2426 ir_node *sse_store, *fld, *mproj;
2428 /* store xmm0 onto stack */
2429 sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
2430 set_ia32_ls_mode(sse_store, mode);
2431 set_ia32_op_type(sse_store, ia32_AddrModeD);
2432 set_ia32_use_frame(sse_store);
2433 set_ia32_frame_ent(sse_store, ent);
2434 set_ia32_am_flavour(sse_store, ia32_B);
2435 set_ia32_am_support(sse_store, ia32_am_Dest);
2436 sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
2439 fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
2440 set_ia32_ls_mode(fld, mode);
2441 set_ia32_op_type(fld, ia32_AddrModeS);
2442 set_ia32_use_frame(fld);
2443 set_ia32_frame_ent(fld, ent);
2444 set_ia32_am_flavour(fld, ia32_B);
2445 set_ia32_am_support(fld, ia32_am_Source);
2446 mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
2447 fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
2449 /* set new return value */
2450 set_irn_n(env->irn, be_pos_Return_val, fld);
2451 set_irn_n(env->irn, be_pos_Return_mem, mproj);
2460 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2462 static ir_node *gen_be_AddSP(ia32_transform_env_t *env) {
2464 const ir_edge_t *edge;
2465 ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size);
2466 ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp);
2468 new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz);
2470 if (is_ia32_Const(sz)) {
2471 set_ia32_Immop_attr(new_op, sz);
2472 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2474 else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
2475 set_ia32_immop_type(new_op, ia32_ImmSymConst);
2476 set_ia32_op_type(new_op, ia32_AddrModeS);
2477 set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
2478 add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
2479 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2483 foreach_out_edge(env->irn, edge) {
2484 ir_node *proj = get_edge_src_irn(edge);
2486 assert(is_Proj(proj));
2488 if (get_Proj_proj(proj) == pn_be_AddSP_res) {
2489 /* the node is not yet exchanged: we need to set the register manually */
2490 ia32_attr_t *attr = get_ia32_attr(new_op);
2491 attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP];
2492 set_Proj_proj(proj, pn_ia32_AddSP_stack);
2494 else if (get_Proj_proj(proj) == pn_be_AddSP_M) {
2495 set_Proj_proj(proj, pn_ia32_AddSP_M);
2502 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2508 * This function just sets the register for the Unknown node
2509 * as this is not done during register allocation because Unknown
2510 * is an "ignore" node.
2512 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2513 ir_mode *mode = env->mode;
2514 ir_node *irn = env->irn;
2516 if (mode_is_float(mode)) {
2517 if (USE_SSE2(env->cg))
2518 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2520 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2522 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2523 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2526 assert(0 && "unsupported Unknown-Mode");
2532 /**********************************************************************
2535 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2536 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2537 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2538 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2540 **********************************************************************/
2542 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2544 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2547 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2548 ir_node *val, ir_node *mem);
2551 * Transforms a lowered Load into a "real" one.
2553 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2554 ir_node *node = env->irn;
2555 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2556 ir_mode *mode = get_ia32_ls_mode(node);
2559 ia32_am_flavour_t am_flav = ia32_B;
2562 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2563 lowering we have x87 nodes, so we need to enforce simulation.
2565 if (mode_is_float(mode)) {
2567 if (fp_unit == fp_x87)
2571 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2572 am_offs = get_ia32_am_offs(node);
2576 add_ia32_am_offs(new_op, am_offs);
2579 set_ia32_am_support(new_op, ia32_am_Source);
2580 set_ia32_op_type(new_op, ia32_AddrModeS);
2581 set_ia32_am_flavour(new_op, am_flav);
2582 set_ia32_ls_mode(new_op, mode);
2583 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2584 set_ia32_use_frame(new_op);
2586 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2592 * Transforms a lowered Store into a "real" one.
2594 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2595 ir_node *node = env->irn;
2596 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2597 ir_mode *mode = get_ia32_ls_mode(node);
2600 ia32_am_flavour_t am_flav = ia32_B;
2603 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2604 lowering we have x87 nodes, so we need to enforce simulation.
2606 if (mode_is_float(mode)) {
2608 if (fp_unit == fp_x87)
2612 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2614 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2616 add_ia32_am_offs(new_op, am_offs);
2619 set_ia32_am_support(new_op, ia32_am_Dest);
2620 set_ia32_op_type(new_op, ia32_AddrModeD);
2621 set_ia32_am_flavour(new_op, am_flav);
2622 set_ia32_ls_mode(new_op, mode);
2623 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2624 set_ia32_use_frame(new_op);
2626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2633 * Transforms an ia32_l_XXX into a "real" XXX node
2635 * @param env The transformation environment
2636 * @return the created ia32 XXX node
2638 #define GEN_LOWERED_OP(op) \
2639 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2640 if (mode_is_float(env->mode)) \
2642 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2645 #define GEN_LOWERED_x87_OP(op) \
2646 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2648 FORCE_x87(env->cg); \
2649 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2650 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2654 #define GEN_LOWERED_UNOP(op) \
2655 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2656 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2659 #define GEN_LOWERED_SHIFT_OP(op) \
2660 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2661 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2664 #define GEN_LOWERED_LOAD(op, fp_unit) \
2665 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2666 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2669 #define GEN_LOWERED_STORE(op, fp_unit) \
2670 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2671 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2674 GEN_LOWERED_OP(AddC)
2676 GEN_LOWERED_OP(SubC)
2680 GEN_LOWERED_x87_OP(vfdiv)
2681 GEN_LOWERED_x87_OP(vfmul)
2682 GEN_LOWERED_x87_OP(vfsub)
2684 GEN_LOWERED_UNOP(Minus)
2686 GEN_LOWERED_LOAD(vfild, fp_x87)
2687 GEN_LOWERED_LOAD(Load, fp_none)
2688 GEN_LOWERED_STORE(vfist, fp_x87)
2689 GEN_LOWERED_STORE(Store, fp_none)
2692 * Transforms a l_MulS into a "real" MulS node.
2694 * @param env The transformation environment
2695 * @return the created ia32 MulS node
2697 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2699 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2700 /* and then skip the result Proj, because all needed Projs are already there. */
2702 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2703 ir_node *muls = get_Proj_pred(new_op);
2705 /* MulS cannot have AM for destination */
2706 if (get_ia32_am_support(muls) != ia32_am_None)
2707 set_ia32_am_support(muls, ia32_am_Source);
2712 GEN_LOWERED_SHIFT_OP(Shl)
2713 GEN_LOWERED_SHIFT_OP(Shr)
2714 GEN_LOWERED_SHIFT_OP(Shrs)
2717 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2718 * op1 - target to be shifted
2719 * op2 - contains bits to be shifted into target
2721 * Only op3 can be an immediate.
2723 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2724 ir_node *new_op = NULL;
2725 ir_mode *mode = env->mode;
2726 dbg_info *dbg = env->dbg;
2727 ir_graph *irg = env->irg;
2728 ir_node *block = env->block;
2729 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2730 ir_node *nomem = new_NoMem();
2733 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2735 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2737 /* Check if immediate optimization is on and */
2738 /* if it's an operation with immediate. */
2739 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2741 /* Limit imm_op within range imm8 */
2743 tv = get_ia32_Immop_tarval(imm_op);
2746 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2747 set_ia32_Immop_tarval(imm_op, tv);
2754 /* integer operations */
2756 /* This is ShiftD with const */
2757 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2759 if (is_ia32_l_ShlD(env->irn))
2760 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2762 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2763 set_ia32_Immop_attr(new_op, imm_op);
2766 /* This is a normal ShiftD */
2767 DB((mod, LEVEL_1, "ShiftD binop ..."));
2768 if (is_ia32_l_ShlD(env->irn))
2769 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2771 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2774 /* set AM support */
2775 set_ia32_am_support(new_op, ia32_am_Dest);
2777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2779 set_ia32_res_mode(new_op, mode);
2780 set_ia32_emit_cl(new_op);
2782 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2785 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2786 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2789 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2790 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2794 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2796 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2797 ia32_code_gen_t *cg = env->cg;
2798 ir_node *res = NULL;
2799 ir_node *ptr = get_irn_n(env->irn, 0);
2800 ir_node *val = get_irn_n(env->irn, 1);
2801 ir_node *mem = get_irn_n(env->irn, 2);
2804 ir_node *noreg = ia32_new_NoReg_gp(cg);
2806 /* Store x87 -> MEM */
2807 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2808 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2809 set_ia32_use_frame(res);
2810 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2811 set_ia32_am_support(res, ia32_am_Dest);
2812 set_ia32_am_flavour(res, ia32_B);
2813 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2815 /* Load MEM -> SSE */
2816 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2817 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2818 set_ia32_use_frame(res);
2819 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2820 set_ia32_am_support(res, ia32_am_Source);
2821 set_ia32_am_flavour(res, ia32_B);
2822 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2825 /* SSE unit is not used -> skip this node. */
2828 edges_reroute(env->irn, val, env->irg);
2829 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2830 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2837 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2839 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2840 ia32_code_gen_t *cg = env->cg;
2841 ir_node *res = NULL;
2842 ir_node *ptr = get_irn_n(env->irn, 0);
2843 ir_node *val = get_irn_n(env->irn, 1);
2844 ir_node *mem = get_irn_n(env->irn, 2);
2847 ir_node *noreg = ia32_new_NoReg_gp(cg);
2849 /* Store SSE -> MEM */
2850 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2851 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2852 set_ia32_use_frame(res);
2853 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2854 set_ia32_am_support(res, ia32_am_Dest);
2855 set_ia32_am_flavour(res, ia32_B);
2856 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2858 /* Load MEM -> x87 */
2859 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2860 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2861 set_ia32_use_frame(res);
2862 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2863 set_ia32_am_support(res, ia32_am_Source);
2864 set_ia32_am_flavour(res, ia32_B);
2865 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2868 /* SSE unit is not used -> skip this node. */
2871 edges_reroute(env->irn, val, env->irg);
2872 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2873 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2879 /*********************************************************
2882 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2883 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2884 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2885 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2887 *********************************************************/
2890 * the BAD transformer.
2892 static ir_node *bad_transform(ia32_transform_env_t *env) {
2893 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2899 * Enters all transform functions into the generic pointer
2901 void ia32_register_transformers(void) {
2902 ir_op *op_Max, *op_Min, *op_Mulh;
2904 /* first clear the generic function pointer for all ops */
2905 clear_irp_opcodes_generic_func();
2907 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2908 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2942 /* transform ops from intrinsic lowering */
2963 GEN(ia32_l_X87toSSE);
2964 GEN(ia32_l_SSEtoX87);
2979 /* constant transformation happens earlier */
2984 /* we should never see these nodes */
2999 /* handle generic backend nodes */
3008 /* set the register for all Unknown nodes */
3011 op_Max = get_op_Max();
3014 op_Min = get_op_Min();
3017 op_Mulh = get_op_Mulh();
3026 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
3029 * Transforms the given firm node (and maybe some other related nodes)
3030 * into one or more assembler nodes.
3032 * @param node the firm node
3033 * @param env the debug module
3035 void ia32_transform_node(ir_node *node, void *env) {
3036 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
3037 ir_op *op = get_irn_op(node);
3038 ir_node *asm_node = NULL;
3044 /* link arguments pointing to Unknown to the UNKNOWN Proj */
3045 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
3046 if (is_Unknown(get_irn_n(node, i)))
3047 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
3050 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
3051 if (op->ops.generic) {
3052 ia32_transform_env_t tenv;
3053 transform_func *transform = (transform_func *)op->ops.generic;
3055 tenv.block = get_nodes_block(node);
3056 tenv.dbg = get_irn_dbg_info(node);
3057 tenv.irg = current_ir_graph;
3059 tenv.mode = get_irn_mode(node);
3061 DEBUG_ONLY(tenv.mod = cg->mod;)
3063 asm_node = (*transform)(&tenv);
3066 /* exchange nodes if a new one was generated */
3068 exchange(node, asm_node);
3069 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
3072 DB((cg->mod, LEVEL_1, "ignored\n"));
3077 * Transforms a psi condition.
3079 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
3082 /* if the mode is target mode, we have already seen this part of the tree */
3083 if (get_irn_mode(cond) == mode)
3086 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
3088 set_irn_mode(cond, mode);
3090 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
3091 ir_node *in = get_irn_n(cond, i);
3093 /* if in is a compare: transform into Set/xCmp */
3095 ir_node *new_op = NULL;
3096 ir_node *cmp = get_Proj_pred(in);
3097 ir_node *cmp_a = get_Cmp_left(cmp);
3098 ir_node *cmp_b = get_Cmp_right(cmp);
3099 dbg_info *dbg = get_irn_dbg_info(cmp);
3100 ir_graph *irg = get_irn_irg(cmp);
3101 ir_node *block = get_nodes_block(cmp);
3102 ir_node *noreg = ia32_new_NoReg_gp(cg);
3103 ir_node *nomem = new_rd_NoMem(irg);
3104 int pnc = get_Proj_proj(in);
3106 /* this is a compare */
3107 if (mode_is_float(mode)) {
3108 /* Psi is float, we need a floating point compare */
3111 ir_mode *m = get_irn_mode(cmp_a);
3113 if (! mode_is_float(m)) {
3114 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
3115 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
3117 else if (m == mode_F) {
3118 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
3119 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
3120 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
3123 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
3124 set_ia32_pncode(new_op, pnc);
3125 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
3134 ia32_transform_env_t tenv;
3135 construct_binop_func *set_func = NULL;
3137 if (mode_is_float(get_irn_mode(cmp_a))) {
3138 /* 1st case: compare operands are floats */
3143 set_func = new_rd_ia32_xCmpSet;
3147 set_func = new_rd_ia32_vfCmpSet;
3150 pnc &= 7; /* fp compare -> int compare */
3153 /* 2nd case: compare operand are integer too */
3154 set_func = new_rd_ia32_CmpSet;
3165 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
3166 set_ia32_pncode(get_Proj_pred(new_op), pnc);
3167 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
3170 /* the the new compare as in */
3171 set_irn_n(cond, i, new_op);
3174 /* another complex condition */
3175 transform_psi_cond(in, mode, cg);
3181 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
3182 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
3183 * compare, which causes the compare result to be stores in a register. The
3184 * "And"s and "Or"s are transformed later, we just have to set their mode right.
3186 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
3187 ia32_code_gen_t *cg = env;
3188 ir_node *psi_sel, *new_cmp, *block;
3193 if (get_irn_opcode(node) != iro_Psi)
3196 psi_sel = get_Psi_cond(node, 0);
3198 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
3199 if (is_Proj(psi_sel))
3202 mode = get_irn_mode(node);
3204 transform_psi_cond(psi_sel, mode, cg);
3206 irg = get_irn_irg(node);
3207 block = get_nodes_block(node);
3209 /* we need to compare the evaluated condition tree with 0 */
3211 /* BEWARE: new_r_Const_long works for floating point as well */
3212 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
3213 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
3215 set_Psi_cond(node, 0, new_cmp);