2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
152 * creates a unique ident by adding a number to a tag
154 * @param tag the tag string, must contain a %d if a number
157 static ident *unique_id(const char *tag)
159 static unsigned id = 0;
162 snprintf(str, sizeof(str), tag, ++id);
163 return new_id_from_str(str);
167 * Get a primitive type for a mode.
169 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
171 pmap_entry *e = pmap_find(types, mode);
176 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
177 res = new_type_primitive(new_id_from_str(buf), mode);
178 set_type_alignment_bytes(res, 16);
179 pmap_insert(types, mode, res);
187 * Get an atomic entity that is initialized with a tarval
189 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
191 tarval *tv = get_Const_tarval(cnst);
192 pmap_entry *e = pmap_find(isa->tv_ent, tv);
197 ir_mode *mode = get_irn_mode(cnst);
198 ir_type *tp = get_Const_type(cnst);
199 if (tp == firm_unknown_type)
200 tp = get_prim_type(isa->types, mode);
202 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
204 set_entity_ld_ident(res, get_entity_ident(res));
205 set_entity_visibility(res, visibility_local);
206 set_entity_variability(res, variability_constant);
207 set_entity_allocation(res, allocation_static);
209 /* we create a new entity here: It's initialization must resist on the
211 rem = current_ir_graph;
212 current_ir_graph = get_const_code_irg();
213 set_atomic_ent_value(res, new_Const_type(tv, tp));
214 current_ir_graph = rem;
216 pmap_insert(isa->tv_ent, tv, res);
224 static int is_Const_0(ir_node *node) {
225 return is_Const(node) && is_Const_null(node);
228 static int is_Const_1(ir_node *node) {
229 return is_Const(node) && is_Const_one(node);
232 static int is_Const_Minus_1(ir_node *node) {
238 mode = get_irn_mode(node);
239 if(!mode_is_signed(mode))
242 tv = get_Const_tarval(node);
245 return tarval_is_one(tv);
249 * Transforms a Const.
251 static ir_node *gen_Const(ir_node *node) {
252 ir_graph *irg = current_ir_graph;
253 ir_node *old_block = get_nodes_block(node);
254 ir_node *block = be_transform_node(old_block);
255 dbg_info *dbgi = get_irn_dbg_info(node);
256 ir_mode *mode = get_irn_mode(node);
258 if (mode_is_float(mode)) {
260 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
261 ir_node *nomem = new_NoMem();
265 if (USE_SSE2(env_cg)) {
266 if (is_Const_null(node)) {
267 load = new_rd_ia32_xZero(dbgi, irg, block);
268 set_ia32_ls_mode(load, mode);
271 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
273 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
275 set_ia32_op_type(load, ia32_AddrModeS);
276 set_ia32_am_sc(load, floatent);
277 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
278 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
281 if (is_Const_null(node)) {
282 load = new_rd_ia32_vfldz(dbgi, irg, block);
284 } else if (is_Const_one(node)) {
285 load = new_rd_ia32_vfld1(dbgi, irg, block);
288 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
290 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
291 set_ia32_op_type(load, ia32_AddrModeS);
292 set_ia32_am_sc(load, floatent);
293 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
294 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
296 set_ia32_ls_mode(load, mode);
299 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
301 /* Const Nodes before the initial IncSP are a bad idea, because
302 * they could be spilled and we have no SP ready at that point yet.
303 * So add a dependency to the initial frame pointer calculation to
304 * avoid that situation.
306 if (get_irg_start_block(irg) == block) {
307 add_irn_dep(load, get_irg_frame(irg));
310 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
314 tarval *tv = get_Const_tarval(node);
317 tv = tarval_convert_to(tv, mode_Iu);
319 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
321 panic("couldn't convert constant tarval (%+F)", node);
323 val = get_tarval_long(tv);
325 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
326 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
329 if (get_irg_start_block(irg) == block) {
330 add_irn_dep(cnst, get_irg_frame(irg));
338 * Transforms a SymConst.
340 static ir_node *gen_SymConst(ir_node *node) {
341 ir_graph *irg = current_ir_graph;
342 ir_node *old_block = get_nodes_block(node);
343 ir_node *block = be_transform_node(old_block);
344 dbg_info *dbgi = get_irn_dbg_info(node);
345 ir_mode *mode = get_irn_mode(node);
348 if (mode_is_float(mode)) {
349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
350 ir_node *nomem = new_NoMem();
352 if (USE_SSE2(env_cg))
353 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
355 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
356 set_ia32_am_sc(cnst, get_SymConst_entity(node));
357 set_ia32_use_frame(cnst);
361 if(get_SymConst_kind(node) != symconst_addr_ent) {
362 panic("backend only support symconst_addr_ent (at %+F)", node);
364 entity = get_SymConst_entity(node);
365 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
368 /* Const Nodes before the initial IncSP are a bad idea, because
369 * they could be spilled and we have no SP ready at that point yet
371 if (get_irg_start_block(irg) == block) {
372 add_irn_dep(cnst, get_irg_frame(irg));
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
380 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
381 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
382 static const struct {
384 const char *ent_name;
385 const char *cnst_str;
388 } names [ia32_known_const_max] = {
389 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
390 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
391 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
392 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
393 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 switch (names[kct].mode) {
411 case 0: mode = mode_Iu; break;
412 case 1: mode = mode_Lu; break;
413 default: mode = mode_F; break;
415 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
416 tp = new_type_primitive(new_id_from_str(tp_name), mode);
417 /* set the specified alignment */
418 set_type_alignment_bytes(tp, names[kct].align);
420 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
422 set_entity_ld_ident(ent, get_entity_ident(ent));
423 set_entity_visibility(ent, visibility_local);
424 set_entity_variability(ent, variability_constant);
425 set_entity_allocation(ent, allocation_static);
427 /* we create a new entity here: It's initialization must resist on the
429 rem = current_ir_graph;
430 current_ir_graph = get_const_code_irg();
431 cnst = new_Const(mode, tv);
432 current_ir_graph = rem;
434 set_atomic_ent_value(ent, cnst);
436 /* cache the entry */
437 ent_cache[kct] = ent;
440 return ent_cache[kct];
445 * Prints the old node name on cg obst and returns a pointer to it.
447 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
448 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
450 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
451 obstack_1grow(isa->name_obst, 0);
452 return obstack_finish(isa->name_obst);
456 static int use_source_address_mode(ir_node *block, ir_node *node,
465 load = get_Proj_pred(node);
466 pn = get_Proj_proj(node);
467 if(!is_Load(load) || pn != pn_Load_res)
469 if(get_nodes_block(load) != block)
471 /* we only use address mode if we're the only user of the load */
472 if(get_irn_n_edges(node) > 1)
475 mode = get_irn_mode(node);
476 if(!mode_needs_gp_reg(mode))
478 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
481 /* don't do AM if other node inputs depend on the load (via mem-proj) */
482 if(other != NULL && get_nodes_block(other) == block
483 && heights_reachable_in_block(heights, other, load))
489 typedef struct ia32_address_mode_t ia32_address_mode_t;
490 struct ia32_address_mode_t {
494 ia32_op_type_t op_type;
501 static void build_address(ia32_address_mode_t *am, ir_node *node)
503 ia32_address_t *addr = &am->addr;
504 ir_node *load = get_Proj_pred(node);
505 ir_node *ptr = get_Load_ptr(load);
506 ir_node *mem = get_Load_mem(load);
507 ir_node *new_mem = be_transform_node(mem);
511 am->ls_mode = get_Load_mode(load);
512 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
514 /* construct load address */
515 ia32_create_address_mode(addr, ptr, 0);
520 base = ia32_new_NoReg_gp(env_cg);
522 base = be_transform_node(base);
526 index = ia32_new_NoReg_gp(env_cg);
528 index = be_transform_node(index);
536 static void set_address(ir_node *node, ia32_address_t *addr)
538 set_ia32_am_scale(node, addr->scale);
539 set_ia32_am_sc(node, addr->symconst_ent);
540 set_ia32_am_offs_int(node, addr->offset);
541 if(addr->symconst_sign)
542 set_ia32_am_sc_sign(node);
544 set_ia32_use_frame(node);
545 set_ia32_frame_ent(node, addr->frame_entity);
548 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
550 set_address(node, &am->addr);
552 set_ia32_op_type(node, am->op_type);
553 set_ia32_ls_mode(node, am->ls_mode);
555 set_ia32_commutative(node);
558 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
559 ir_node *op1, ir_node *op2, int commutative,
560 int use_am_and_immediates, int use_am,
563 ia32_address_t *addr = &am->addr;
564 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
568 memset(am, 0, sizeof(am[0]));
570 if(!use_8_16_bit_am && get_mode_size_bits(get_irn_mode(op1)) < 32)
573 new_op2 = try_create_Immediate(op2, 0);
574 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
575 build_address(am, op2);
576 new_op1 = be_transform_node(op1);
578 am->op_type = ia32_AddrModeS;
579 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
580 use_am && use_source_address_mode(block, op1, op2)) {
581 build_address(am, op1);
582 if(new_op2 != NULL) {
585 new_op1 = be_transform_node(op2);
589 am->op_type = ia32_AddrModeS;
591 new_op1 = be_transform_node(op1);
593 new_op2 = be_transform_node(op2);
594 am->op_type = ia32_Normal;
596 if(addr->base == NULL)
597 addr->base = noreg_gp;
598 if(addr->index == NULL)
599 addr->index = noreg_gp;
600 if(addr->mem == NULL)
601 addr->mem = new_NoMem();
603 am->new_op1 = new_op1;
604 am->new_op2 = new_op2;
605 am->commutative = commutative;
608 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
610 ir_graph *irg = current_ir_graph;
614 if(am->mem_proj == NULL)
617 /* we have to create a mode_T so the old MemProj can attach to us */
618 mode = get_irn_mode(node);
619 load = get_Proj_pred(am->mem_proj);
621 mark_irn_visited(load);
622 be_set_transformed_node(load, node);
625 set_irn_mode(node, mode_T);
626 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
633 * Construct a standard binary operation, set AM and immediate if required.
635 * @param op1 The first operand
636 * @param op2 The second operand
637 * @param func The node constructor function
638 * @return The constructed ia32 node.
640 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
641 construct_binop_func *func, int commutative)
643 ir_node *src_block = get_nodes_block(node);
644 ir_node *block = be_transform_node(src_block);
645 ir_graph *irg = current_ir_graph;
646 dbg_info *dbgi = get_irn_dbg_info(node);
648 ia32_address_mode_t am;
649 ia32_address_t *addr = &am.addr;
651 match_arguments(&am, src_block, op1, op2, commutative, 0, 1, 0);
653 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
654 am.new_op1, am.new_op2);
655 set_am_attributes(new_node, &am);
656 /* we can't use source address mode anymore when using immediates */
657 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
658 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
659 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 new_node = fix_mem_proj(new_node, &am);
667 * Construct a standard binary operation, set AM and immediate if required.
669 * @param op1 The first operand
670 * @param op2 The second operand
671 * @param func The node constructor function
672 * @return The constructed ia32 node.
674 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
675 construct_binop_func *func)
677 ir_node *block = be_transform_node(get_nodes_block(node));
678 ir_node *new_op1 = be_transform_node(op1);
679 ir_node *new_op2 = be_transform_node(op2);
680 ir_node *new_node = NULL;
681 dbg_info *dbgi = get_irn_dbg_info(node);
682 ir_graph *irg = current_ir_graph;
683 ir_mode *mode = get_irn_mode(node);
684 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
685 ir_node *nomem = new_NoMem();
687 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
689 if (is_op_commutative(get_irn_op(node))) {
690 set_ia32_commutative(new_node);
692 set_ia32_ls_mode(new_node, mode);
694 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
699 static ir_node *get_fpcw(void)
702 if(initial_fpcw != NULL)
705 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
706 &ia32_fp_cw_regs[REG_FPCW]);
707 initial_fpcw = be_transform_node(fpcw);
713 * Construct a standard binary operation, set AM and immediate if required.
715 * @param op1 The first operand
716 * @param op2 The second operand
717 * @param func The node constructor function
718 * @return The constructed ia32 node.
720 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
721 construct_binop_float_func *func)
723 ir_node *block = be_transform_node(get_nodes_block(node));
724 ir_node *new_op1 = be_transform_node(op1);
725 ir_node *new_op2 = be_transform_node(op2);
726 ir_node *new_node = NULL;
727 dbg_info *dbgi = get_irn_dbg_info(node);
728 ir_graph *irg = current_ir_graph;
729 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
730 ir_node *nomem = new_NoMem();
732 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
734 if (is_op_commutative(get_irn_op(node))) {
735 set_ia32_commutative(new_node);
738 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
744 * Construct a shift/rotate binary operation, sets AM and immediate if required.
746 * @param op1 The first operand
747 * @param op2 The second operand
748 * @param func The node constructor function
749 * @return The constructed ia32 node.
751 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
752 construct_shift_func *func)
754 dbg_info *dbgi = get_irn_dbg_info(node);
755 ir_graph *irg = current_ir_graph;
756 ir_node *block = get_nodes_block(node);
757 ir_node *new_block = be_transform_node(block);
758 ir_node *new_op1 = be_transform_node(op1);
759 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
762 assert(! mode_is_float(get_irn_mode(node))
763 && "Shift/Rotate with float not supported");
765 res = func(dbgi, irg, new_block, new_op1, new_op2);
766 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
768 /* lowered shift instruction may have a dependency operand, handle it here */
769 if (get_irn_arity(node) == 3) {
770 /* we have a dependency */
771 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
772 add_irn_dep(res, new_dep);
780 * Construct a standard unary operation, set AM and immediate if required.
782 * @param op The operand
783 * @param func The node constructor function
784 * @return The constructed ia32 node.
786 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
788 ir_node *block = be_transform_node(get_nodes_block(node));
789 ir_node *new_op = be_transform_node(op);
790 ir_node *new_node = NULL;
791 ir_graph *irg = current_ir_graph;
792 dbg_info *dbgi = get_irn_dbg_info(node);
794 new_node = func(dbgi, irg, block, new_op);
796 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
801 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
802 ia32_address_t *addr)
804 ir_graph *irg = current_ir_graph;
805 ir_node *base = addr->base;
806 ir_node *index = addr->index;
810 base = ia32_new_NoReg_gp(env_cg);
812 base = be_transform_node(base);
816 index = ia32_new_NoReg_gp(env_cg);
818 index = be_transform_node(index);
821 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
822 set_address(res, addr);
827 static int am_has_immediates(const ia32_address_t *addr)
829 return addr->offset != 0 || addr->symconst_ent != NULL
830 || addr->frame_entity || addr->use_frame;
834 * Creates an ia32 Add.
836 * @return the created ia32 Add node
838 static ir_node *gen_Add(ir_node *node) {
839 ir_node *block = be_transform_node(get_nodes_block(node));
840 ir_node *op1 = get_Add_left(node);
841 ir_node *op2 = get_Add_right(node);
844 ir_graph *irg = current_ir_graph;
845 dbg_info *dbgi = get_irn_dbg_info(node);
846 ir_mode *mode = get_irn_mode(node);
847 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
848 ir_node *src_block = get_nodes_block(node);
849 ir_node *add_immediate_op;
851 ia32_address_mode_t am;
853 if (mode_is_float(mode)) {
854 if (USE_SSE2(env_cg))
855 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
857 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
862 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
863 * 1. Add with immediate -> Lea
864 * 2. Add with possible source address mode -> Add
865 * 3. Otherwise -> Lea
867 memset(&addr, 0, sizeof(addr));
868 ia32_create_address_mode(&addr, node, 1);
869 add_immediate_op = NULL;
871 if(addr.base == NULL && addr.index == NULL) {
872 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
873 addr.symconst_sign, addr.offset);
874 add_irn_dep(new_op, get_irg_frame(irg));
875 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
878 /* add with immediate? */
879 if(addr.index == NULL) {
880 add_immediate_op = addr.base;
881 } else if(addr.base == NULL && addr.scale == 0) {
882 add_immediate_op = addr.index;
885 if(add_immediate_op != NULL) {
886 if(!am_has_immediates(&addr)) {
888 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
891 return be_transform_node(add_immediate_op);
894 new_op = create_lea_from_address(dbgi, block, &addr);
895 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
899 /* test if we can use source address mode */
900 memset(&am, 0, sizeof(am));
902 if(use_source_address_mode(src_block, op2, op1)) {
903 build_address(&am, op2);
904 new_op1 = be_transform_node(op1);
905 } else if(use_source_address_mode(src_block, op1, op2)) {
906 build_address(&am, op1);
907 new_op1 = be_transform_node(op2);
909 /* construct an Add with source address mode */
910 if(new_op1 != NULL) {
911 ia32_address_t *am_addr = &am.addr;
912 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
913 am_addr->mem, new_op1, noreg);
914 set_address(new_op, am_addr);
915 set_ia32_op_type(new_op, ia32_AddrModeS);
916 set_ia32_ls_mode(new_op, am.ls_mode);
917 set_ia32_commutative(new_op);
918 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
920 new_op = fix_mem_proj(new_op, &am);
925 /* otherwise construct a lea */
926 new_op = create_lea_from_address(dbgi, block, &addr);
927 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
932 * Creates an ia32 Mul.
934 * @return the created ia32 Mul node
936 static ir_node *gen_Mul(ir_node *node) {
937 ir_node *op1 = get_Mul_left(node);
938 ir_node *op2 = get_Mul_right(node);
939 ir_mode *mode = get_irn_mode(node);
941 if (mode_is_float(mode)) {
942 if (USE_SSE2(env_cg))
943 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
945 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
949 for the lower 32bit of the result it doesn't matter whether we use
950 signed or unsigned multiplication so we use IMul as it has fewer
953 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
957 * Creates an ia32 Mulh.
958 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
959 * this result while Mul returns the lower 32 bit.
961 * @return the created ia32 Mulh node
963 static ir_node *gen_Mulh(ir_node *node) {
964 ir_node *block = be_transform_node(get_nodes_block(node));
965 ir_node *op1 = get_irn_n(node, 0);
966 ir_node *new_op1 = be_transform_node(op1);
967 ir_node *op2 = get_irn_n(node, 1);
968 ir_node *new_op2 = be_transform_node(op2);
969 ir_graph *irg = current_ir_graph;
970 dbg_info *dbgi = get_irn_dbg_info(node);
971 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
972 ir_mode *mode = get_irn_mode(node);
973 ir_node *proj_EDX, *res;
975 assert(!mode_is_float(mode) && "Mulh with float not supported");
976 if (mode_is_signed(mode)) {
977 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
980 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
984 set_ia32_commutative(res);
986 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
994 * Creates an ia32 And.
996 * @return The created ia32 And node
998 static ir_node *gen_And(ir_node *node) {
999 ir_node *op1 = get_And_left(node);
1000 ir_node *op2 = get_And_right(node);
1001 assert(! mode_is_float(get_irn_mode(node)));
1003 /* is it a zero extension? */
1004 if (is_Const(op2)) {
1005 tarval *tv = get_Const_tarval(op2);
1006 long v = get_tarval_long(tv);
1008 if (v == 0xFF || v == 0xFFFF) {
1009 dbg_info *dbgi = get_irn_dbg_info(node);
1010 ir_node *block = get_nodes_block(node);
1017 assert(v == 0xFFFF);
1020 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1026 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1032 * Creates an ia32 Or.
1034 * @return The created ia32 Or node
1036 static ir_node *gen_Or(ir_node *node) {
1037 ir_node *op1 = get_Or_left(node);
1038 ir_node *op2 = get_Or_right(node);
1040 assert (! mode_is_float(get_irn_mode(node)));
1041 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1047 * Creates an ia32 Eor.
1049 * @return The created ia32 Eor node
1051 static ir_node *gen_Eor(ir_node *node) {
1052 ir_node *op1 = get_Eor_left(node);
1053 ir_node *op2 = get_Eor_right(node);
1055 assert(! mode_is_float(get_irn_mode(node)));
1056 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1061 * Creates an ia32 Sub.
1063 * @return The created ia32 Sub node
1065 static ir_node *gen_Sub(ir_node *node) {
1066 ir_node *op1 = get_Sub_left(node);
1067 ir_node *op2 = get_Sub_right(node);
1068 ir_mode *mode = get_irn_mode(node);
1070 if (mode_is_float(mode)) {
1071 if (USE_SSE2(env_cg))
1072 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1074 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1078 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1082 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1088 * Generates an ia32 DivMod with additional infrastructure for the
1089 * register allocator if needed.
1091 * @param dividend -no comment- :)
1092 * @param divisor -no comment- :)
1093 * @param dm_flav flavour_Div/Mod/DivMod
1094 * @return The created ia32 DivMod node
1096 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1097 ir_node *divisor, ia32_op_flavour_t dm_flav)
1099 ir_node *block = be_transform_node(get_nodes_block(node));
1100 ir_node *new_dividend = be_transform_node(dividend);
1101 ir_node *new_divisor = be_transform_node(divisor);
1102 ir_graph *irg = current_ir_graph;
1103 dbg_info *dbgi = get_irn_dbg_info(node);
1104 ir_mode *mode = get_irn_mode(node);
1105 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1106 ir_node *res, *proj_div, *proj_mod;
1107 ir_node *sign_extension;
1108 ir_node *mem, *new_mem;
1111 proj_div = proj_mod = NULL;
1115 mem = get_Div_mem(node);
1116 mode = get_Div_resmode(node);
1117 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1118 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1121 mem = get_Mod_mem(node);
1122 mode = get_Mod_resmode(node);
1123 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1124 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1126 case flavour_DivMod:
1127 mem = get_DivMod_mem(node);
1128 mode = get_DivMod_resmode(node);
1129 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1130 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1131 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1134 panic("invalid divmod flavour!");
1136 new_mem = be_transform_node(mem);
1138 if (mode_is_signed(mode)) {
1139 /* in signed mode, we need to sign extend the dividend */
1140 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1141 add_irn_dep(produceval, get_irg_frame(irg));
1142 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1145 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1146 add_irn_dep(sign_extension, get_irg_frame(irg));
1149 if (mode_is_signed(mode)) {
1150 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1151 new_dividend, sign_extension, new_divisor, dm_flav);
1153 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1154 sign_extension, new_divisor, dm_flav);
1157 set_ia32_exc_label(res, has_exc);
1158 set_irn_pinned(res, get_irn_pinned(node));
1160 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1167 * Wrapper for generate_DivMod. Sets flavour_Mod.
1170 static ir_node *gen_Mod(ir_node *node) {
1171 return generate_DivMod(node, get_Mod_left(node),
1172 get_Mod_right(node), flavour_Mod);
1176 * Wrapper for generate_DivMod. Sets flavour_Div.
1179 static ir_node *gen_Div(ir_node *node) {
1180 return generate_DivMod(node, get_Div_left(node),
1181 get_Div_right(node), flavour_Div);
1185 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1187 static ir_node *gen_DivMod(ir_node *node) {
1188 return generate_DivMod(node, get_DivMod_left(node),
1189 get_DivMod_right(node), flavour_DivMod);
1195 * Creates an ia32 floating Div.
1197 * @return The created ia32 xDiv node
1199 static ir_node *gen_Quot(ir_node *node) {
1200 ir_node *block = be_transform_node(get_nodes_block(node));
1201 ir_node *op1 = get_Quot_left(node);
1202 ir_node *new_op1 = be_transform_node(op1);
1203 ir_node *op2 = get_Quot_right(node);
1204 ir_node *new_op2 = be_transform_node(op2);
1205 ir_graph *irg = current_ir_graph;
1206 dbg_info *dbgi = get_irn_dbg_info(node);
1207 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1208 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1211 if (USE_SSE2(env_cg)) {
1212 ir_mode *mode = get_irn_mode(op1);
1213 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1215 set_ia32_ls_mode(new_op, mode);
1217 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1218 new_op2, get_fpcw());
1220 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1226 * Creates an ia32 Shl.
1228 * @return The created ia32 Shl node
1230 static ir_node *gen_Shl(ir_node *node) {
1231 ir_node *right = get_Shl_right(node);
1233 /* test whether we can build a lea */
1234 if(is_Const(right)) {
1235 tarval *tv = get_Const_tarval(right);
1236 if(tarval_is_long(tv)) {
1237 long val = get_tarval_long(tv);
1238 if(val >= 0 && val <= 3) {
1239 ir_graph *irg = current_ir_graph;
1240 dbg_info *dbgi = get_irn_dbg_info(node);
1241 ir_node *block = be_transform_node(get_nodes_block(node));
1242 ir_node *base = ia32_new_NoReg_gp(env_cg);
1243 ir_node *index = be_transform_node(get_Shl_left(node));
1244 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1245 set_ia32_am_scale(res, val);
1246 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1252 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1259 * Creates an ia32 Shr.
1261 * @return The created ia32 Shr node
1263 static ir_node *gen_Shr(ir_node *node) {
1264 return gen_shift_binop(node, get_Shr_left(node),
1265 get_Shr_right(node), new_rd_ia32_Shr);
1271 * Creates an ia32 Sar.
1273 * @return The created ia32 Shrs node
1275 static ir_node *gen_Shrs(ir_node *node) {
1276 ir_node *left = get_Shrs_left(node);
1277 ir_node *right = get_Shrs_right(node);
1278 ir_mode *mode = get_irn_mode(node);
1279 if(is_Const(right) && mode == mode_Is) {
1280 tarval *tv = get_Const_tarval(right);
1281 long val = get_tarval_long(tv);
1283 /* this is a sign extension */
1284 ir_graph *irg = current_ir_graph;
1285 dbg_info *dbgi = get_irn_dbg_info(node);
1286 ir_node *block = be_transform_node(get_nodes_block(node));
1288 ir_node *new_op = be_transform_node(op);
1289 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1290 add_irn_dep(pval, get_irg_frame(irg));
1292 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1296 /* 8 or 16 bit sign extension? */
1297 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1298 ir_node *shl_left = get_Shl_left(left);
1299 ir_node *shl_right = get_Shl_right(left);
1300 if(is_Const(shl_right)) {
1301 tarval *tv1 = get_Const_tarval(right);
1302 tarval *tv2 = get_Const_tarval(shl_right);
1303 if(tv1 == tv2 && tarval_is_long(tv1)) {
1304 long val = get_tarval_long(tv1);
1305 if(val == 16 || val == 24) {
1306 dbg_info *dbgi = get_irn_dbg_info(node);
1307 ir_node *block = get_nodes_block(node);
1317 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1326 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1332 * Creates an ia32 RotL.
1334 * @param op1 The first operator
1335 * @param op2 The second operator
1336 * @return The created ia32 RotL node
1338 static ir_node *gen_RotL(ir_node *node,
1339 ir_node *op1, ir_node *op2) {
1340 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1346 * Creates an ia32 RotR.
1347 * NOTE: There is no RotR with immediate because this would always be a RotL
1348 * "imm-mode_size_bits" which can be pre-calculated.
1350 * @param op1 The first operator
1351 * @param op2 The second operator
1352 * @return The created ia32 RotR node
1354 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1356 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1362 * Creates an ia32 RotR or RotL (depending on the found pattern).
1364 * @return The created ia32 RotL or RotR node
1366 static ir_node *gen_Rot(ir_node *node) {
1367 ir_node *rotate = NULL;
1368 ir_node *op1 = get_Rot_left(node);
1369 ir_node *op2 = get_Rot_right(node);
1371 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1372 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1373 that means we can create a RotR instead of an Add and a RotL */
1375 if (get_irn_op(op2) == op_Add) {
1377 ir_node *left = get_Add_left(add);
1378 ir_node *right = get_Add_right(add);
1379 if (is_Const(right)) {
1380 tarval *tv = get_Const_tarval(right);
1381 ir_mode *mode = get_irn_mode(node);
1382 long bits = get_mode_size_bits(mode);
1384 if (get_irn_op(left) == op_Minus &&
1385 tarval_is_long(tv) &&
1386 get_tarval_long(tv) == bits)
1388 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1389 rotate = gen_RotR(node, op1, get_Minus_op(left));
1394 if (rotate == NULL) {
1395 rotate = gen_RotL(node, op1, op2);
1404 * Transforms a Minus node.
1406 * @param op The Minus operand
1407 * @return The created ia32 Minus node
1409 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1410 ir_node *block = be_transform_node(get_nodes_block(node));
1411 ir_graph *irg = current_ir_graph;
1412 dbg_info *dbgi = get_irn_dbg_info(node);
1413 ir_mode *mode = get_irn_mode(node);
1418 if (mode_is_float(mode)) {
1419 ir_node *new_op = be_transform_node(op);
1420 if (USE_SSE2(env_cg)) {
1421 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1422 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1423 ir_node *nomem = new_rd_NoMem(irg);
1425 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1428 size = get_mode_size_bits(mode);
1429 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1431 set_ia32_am_sc(res, ent);
1432 set_ia32_op_type(res, ia32_AddrModeS);
1433 set_ia32_ls_mode(res, mode);
1435 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1438 res = gen_unop(node, op, new_rd_ia32_Neg);
1441 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1447 * Transforms a Minus node.
1449 * @return The created ia32 Minus node
1451 static ir_node *gen_Minus(ir_node *node) {
1452 return gen_Minus_ex(node, get_Minus_op(node));
1455 static ir_node *create_Immediate_from_int(int val)
1457 ir_graph *irg = current_ir_graph;
1458 ir_node *start_block = get_irg_start_block(irg);
1459 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1460 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1465 static ir_node *gen_bin_Not(ir_node *node)
1467 ir_graph *irg = current_ir_graph;
1468 dbg_info *dbgi = get_irn_dbg_info(node);
1469 ir_node *block = be_transform_node(get_nodes_block(node));
1470 ir_node *op = get_Not_op(node);
1471 ir_node *new_op = be_transform_node(op);
1472 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1473 ir_node *nomem = new_NoMem();
1474 ir_node *one = create_Immediate_from_int(1);
1476 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1480 * Transforms a Not node.
1482 * @return The created ia32 Not node
1484 static ir_node *gen_Not(ir_node *node) {
1485 ir_node *op = get_Not_op(node);
1486 ir_mode *mode = get_irn_mode(node);
1488 if(mode == mode_b) {
1489 return gen_bin_Not(node);
1492 assert (! mode_is_float(get_irn_mode(node)));
1493 return gen_unop(node, op, new_rd_ia32_Not);
1499 * Transforms an Abs node.
1501 * @return The created ia32 Abs node
1503 static ir_node *gen_Abs(ir_node *node) {
1504 ir_node *block = be_transform_node(get_nodes_block(node));
1505 ir_node *op = get_Abs_op(node);
1506 ir_node *new_op = be_transform_node(op);
1507 ir_graph *irg = current_ir_graph;
1508 dbg_info *dbgi = get_irn_dbg_info(node);
1509 ir_mode *mode = get_irn_mode(node);
1510 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1511 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1512 ir_node *nomem = new_NoMem();
1517 if (mode_is_float(mode)) {
1518 if (USE_SSE2(env_cg)) {
1519 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1521 size = get_mode_size_bits(mode);
1522 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1524 set_ia32_am_sc(res, ent);
1526 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1528 set_ia32_op_type(res, ia32_AddrModeS);
1529 set_ia32_ls_mode(res, mode);
1532 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1533 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1538 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1541 add_irn_dep(pval, get_irg_frame(irg));
1542 SET_IA32_ORIG_NODE(sign_extension,
1543 ia32_get_old_node_name(env_cg, node));
1545 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1547 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1549 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1551 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1558 * Transforms a Load.
1560 * @return the created ia32 Load node
1562 static ir_node *gen_Load(ir_node *node) {
1563 ir_node *old_block = get_nodes_block(node);
1564 ir_node *block = be_transform_node(old_block);
1565 ir_node *ptr = get_Load_ptr(node);
1566 ir_node *mem = get_Load_mem(node);
1567 ir_node *new_mem = be_transform_node(mem);
1570 ir_graph *irg = current_ir_graph;
1571 dbg_info *dbgi = get_irn_dbg_info(node);
1572 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1573 ir_mode *mode = get_Load_mode(node);
1576 ia32_address_t addr;
1578 /* construct load address */
1579 memset(&addr, 0, sizeof(addr));
1580 ia32_create_address_mode(&addr, ptr, 0);
1587 base = be_transform_node(base);
1593 index = be_transform_node(index);
1596 if (mode_is_float(mode)) {
1597 if (USE_SSE2(env_cg)) {
1598 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1600 res_mode = mode_xmm;
1602 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1604 res_mode = mode_vfp;
1610 /* create a conv node with address mode for smaller modes */
1611 if(get_mode_size_bits(mode) < 32) {
1612 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem,
1615 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1620 set_irn_pinned(new_op, get_irn_pinned(node));
1621 set_ia32_op_type(new_op, ia32_AddrModeS);
1622 set_ia32_ls_mode(new_op, mode);
1623 set_address(new_op, &addr);
1625 /* make sure we are scheduled behind the initial IncSP/Barrier
1626 * to avoid spills being placed before it
1628 if (block == get_irg_start_block(irg)) {
1629 add_irn_dep(new_op, get_irg_frame(irg));
1632 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1633 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1638 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1639 ir_node *ptr, ir_mode *mode, ir_node *other)
1646 /* we only use address mode if we're the only user of the load */
1647 if(get_irn_n_edges(node) > 1)
1650 load = get_Proj_pred(node);
1653 if(get_nodes_block(load) != block)
1656 /* Store should be attached to the load */
1657 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1659 /* store should have the same pointer as the load */
1660 if(get_Load_ptr(load) != ptr)
1663 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1664 if(other != NULL && get_nodes_block(other) == block
1665 && heights_reachable_in_block(heights, other, load))
1668 assert(get_Load_mode(load) == mode);
1673 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1674 ir_node *mem, ir_node *ptr, ir_mode *mode,
1675 construct_binop_dest_func *func, int commutative)
1677 ir_node *src_block = get_nodes_block(node);
1679 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1680 ir_graph *irg = current_ir_graph;
1684 ia32_address_mode_t am;
1685 ia32_address_t *addr = &am.addr;
1686 memset(&am, 0, sizeof(am));
1688 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1689 build_address(&am, op1);
1690 new_op = create_immediate_or_transform(op2, 0);
1691 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1692 build_address(&am, op2);
1693 new_op = create_immediate_or_transform(op1, 0);
1698 if(addr->base == NULL)
1699 addr->base = noreg_gp;
1700 if(addr->index == NULL)
1701 addr->index = noreg_gp;
1702 if(addr->mem == NULL)
1703 addr->mem = new_NoMem();
1705 dbgi = get_irn_dbg_info(node);
1706 block = be_transform_node(src_block);
1707 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, new_op);
1708 set_address(new_node, addr);
1709 set_ia32_op_type(new_node, ia32_AddrModeD);
1710 set_ia32_ls_mode(new_node, mode);
1711 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1716 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1717 ir_node *ptr, ir_mode *mode,
1718 construct_unop_dest_func *func)
1720 ir_node *src_block = get_nodes_block(node);
1722 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1723 ir_graph *irg = current_ir_graph;
1726 ia32_address_mode_t am;
1727 ia32_address_t *addr = &am.addr;
1728 memset(&am, 0, sizeof(am));
1730 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1733 build_address(&am, op);
1735 if(addr->base == NULL)
1736 addr->base = noreg_gp;
1737 if(addr->index == NULL)
1738 addr->index = noreg_gp;
1739 if(addr->mem == NULL)
1740 addr->mem = new_NoMem();
1742 dbgi = get_irn_dbg_info(node);
1743 block = be_transform_node(src_block);
1744 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1745 set_address(new_node, addr);
1746 set_ia32_op_type(new_node, ia32_AddrModeD);
1747 set_ia32_ls_mode(new_node, mode);
1748 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1753 static ir_node *try_create_dest_am(ir_node *node) {
1754 ir_node *val = get_Store_value(node);
1755 ir_node *mem = get_Store_mem(node);
1756 ir_node *ptr = get_Store_ptr(node);
1757 ir_mode *mode = get_irn_mode(val);
1762 /* handle only GP modes for now... */
1763 if(!mode_needs_gp_reg(mode))
1766 /* TODO0000 8bit operations have stricter constraints. This is not handled yet */
1767 if (get_mode_size_bits(mode) < 16)
1770 /* store must be the only user of the val node */
1771 if(get_irn_n_edges(val) > 1)
1774 switch(get_irn_opcode(val)) {
1776 op1 = get_Add_left(val);
1777 op2 = get_Add_right(val);
1778 if(is_Const_1(op2)) {
1779 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1780 new_rd_ia32_IncMem);
1782 } else if(is_Const_Minus_1(op2)) {
1783 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1784 new_rd_ia32_DecMem);
1787 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1788 new_rd_ia32_AddMem, 1);
1791 op1 = get_Sub_left(val);
1792 op2 = get_Sub_right(val);
1793 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1794 new_rd_ia32_SubMem, 0);
1797 op1 = get_And_left(val);
1798 op2 = get_And_right(val);
1799 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1800 new_rd_ia32_AndMem, 1);
1803 op1 = get_Or_left(val);
1804 op2 = get_Or_right(val);
1805 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1806 new_rd_ia32_OrMem, 1);
1809 op1 = get_Eor_left(val);
1810 op2 = get_Eor_right(val);
1811 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1812 new_rd_ia32_XorMem, 1);
1815 op1 = get_Shl_left(val);
1816 op2 = get_Shl_right(val);
1817 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1818 new_rd_ia32_ShlMem, 0);
1821 op1 = get_Shr_left(val);
1822 op2 = get_Shr_right(val);
1823 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1824 new_rd_ia32_ShrMem, 0);
1827 op1 = get_Shrs_left(val);
1828 op2 = get_Shrs_right(val);
1829 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1830 new_rd_ia32_SarMem, 0);
1833 op1 = get_Rot_left(val);
1834 op2 = get_Rot_right(val);
1835 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1836 new_rd_ia32_RolMem, 0);
1838 /* TODO: match ROR patterns... */
1840 op1 = get_Minus_op(val);
1841 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1844 /* TODO this would be ^ 1 with DestAM */
1847 op1 = get_Not_op(val);
1848 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1858 * Transforms a Store.
1860 * @return the created ia32 Store node
1862 static ir_node *gen_Store(ir_node *node) {
1863 ir_node *block = be_transform_node(get_nodes_block(node));
1864 ir_node *ptr = get_Store_ptr(node);
1867 ir_node *val = get_Store_value(node);
1869 ir_node *mem = get_Store_mem(node);
1870 ir_node *new_mem = be_transform_node(mem);
1871 ir_graph *irg = current_ir_graph;
1872 dbg_info *dbgi = get_irn_dbg_info(node);
1873 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1874 ir_mode *mode = get_irn_mode(val);
1876 ia32_address_t addr;
1878 /* check for destination address mode */
1879 new_op = try_create_dest_am(node);
1883 /* construct store address */
1884 memset(&addr, 0, sizeof(addr));
1885 ia32_create_address_mode(&addr, ptr, 0);
1892 base = be_transform_node(base);
1898 index = be_transform_node(index);
1901 if (mode_is_float(mode)) {
1902 new_val = be_transform_node(val);
1903 if (USE_SSE2(env_cg)) {
1904 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1907 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1911 new_val = create_immediate_or_transform(val, 0);
1915 if (get_mode_size_bits(mode) == 8) {
1916 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1919 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1924 set_irn_pinned(new_op, get_irn_pinned(node));
1925 set_ia32_op_type(new_op, ia32_AddrModeD);
1926 set_ia32_ls_mode(new_op, mode);
1928 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1929 set_address(new_op, &addr);
1930 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1935 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1936 ir_node *cmp_left, ir_node *cmp_right,
1943 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1944 ia32_address_mode_t am;
1945 ia32_address_t *addr = &am.addr;
1947 if(cmp_right != NULL && !is_Const_0(cmp_right))
1950 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1951 mode = get_irn_mode(cmp_left);
1952 arg_left = get_And_left(cmp_left);
1953 arg_right = get_And_right(cmp_left);
1955 mode = get_irn_mode(cmp_left);
1956 arg_left = cmp_left;
1957 arg_right = cmp_left;
1963 assert(get_mode_size_bits(mode) <= 32);
1964 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
1966 pnc = get_inversed_pnc(pnc);
1968 if(get_mode_size_bits(mode) == 8) {
1969 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1970 addr->index, addr->mem, am.new_op1,
1973 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1974 addr->index, addr->mem, am.new_op1, am.new_op2,
1977 set_am_attributes(res, &am);
1978 set_ia32_ls_mode(res, mode);
1980 res = fix_mem_proj(res, &am);
1985 static ir_node *create_Switch(ir_node *node)
1987 ir_graph *irg = current_ir_graph;
1988 dbg_info *dbgi = get_irn_dbg_info(node);
1989 ir_node *block = be_transform_node(get_nodes_block(node));
1990 ir_node *sel = get_Cond_selector(node);
1991 ir_node *new_sel = be_transform_node(sel);
1993 int switch_min = INT_MAX;
1994 const ir_edge_t *edge;
1996 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1998 /* determine the smallest switch case value */
1999 foreach_out_edge(node, edge) {
2000 ir_node *proj = get_edge_src_irn(edge);
2001 int pn = get_Proj_proj(proj);
2006 if (switch_min != 0) {
2007 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2009 /* if smallest switch case is not 0 we need an additional sub */
2010 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2011 add_ia32_am_offs_int(new_sel, -switch_min);
2012 set_ia32_op_type(new_sel, ia32_AddrModeS);
2014 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2017 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2018 set_ia32_pncode(res, get_Cond_defaultProj(node));
2020 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2026 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2028 * @return The transformed node.
2030 static ir_node *gen_Cond(ir_node *node) {
2031 ir_node *src_block = get_nodes_block(node);
2032 ir_node *block = be_transform_node(src_block);
2033 ir_graph *irg = current_ir_graph;
2034 dbg_info *dbgi = get_irn_dbg_info(node);
2035 ir_node *sel = get_Cond_selector(node);
2036 ir_mode *sel_mode = get_irn_mode(sel);
2037 ir_node *res = NULL;
2038 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2039 ir_node *nomem = new_NoMem();
2049 if (sel_mode != mode_b) {
2050 return create_Switch(node);
2053 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2054 /* it's some mode_b value but not a direct comparison -> create a
2056 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2057 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2061 /* address mode makes only sense when we're the only user of the cmp */
2062 use_am = get_irn_n_edges(node) <= 1;
2064 cmp = get_Proj_pred(sel);
2065 cmp_a = get_Cmp_left(cmp);
2066 cmp_b = get_Cmp_right(cmp);
2067 cmp_mode = get_irn_mode(cmp_a);
2068 pnc = get_Proj_proj(sel);
2069 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2070 pnc |= ia32_pn_Cmp_Unsigned;
2073 if(mode_needs_gp_reg(cmp_mode)) {
2074 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2076 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2081 if (mode_is_float(cmp_mode)) {
2082 new_cmp_a = be_transform_node(cmp_a);
2083 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2084 if (USE_SSE2(env_cg)) {
2085 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, nomem, cmp_a,
2087 set_ia32_commutative(res);
2088 set_ia32_ls_mode(res, cmp_mode);
2090 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2091 set_ia32_commutative(res);
2094 ia32_address_mode_t am;
2095 ia32_address_t *addr = &am.addr;
2096 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am, 1);
2098 pnc = get_inversed_pnc(pnc);
2100 if(get_mode_size_bits(cmp_mode) == 8) {
2101 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base, addr->index,
2102 addr->mem, am.new_op1, am.new_op2, pnc);
2104 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2105 addr->mem, am.new_op1, am.new_op2, pnc);
2107 set_am_attributes(res, &am);
2108 assert(cmp_mode != NULL);
2109 set_ia32_ls_mode(res, cmp_mode);
2111 res = fix_mem_proj(res, &am);
2114 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2122 * Transforms a CopyB node.
2124 * @return The transformed node.
2126 static ir_node *gen_CopyB(ir_node *node) {
2127 ir_node *block = be_transform_node(get_nodes_block(node));
2128 ir_node *src = get_CopyB_src(node);
2129 ir_node *new_src = be_transform_node(src);
2130 ir_node *dst = get_CopyB_dst(node);
2131 ir_node *new_dst = be_transform_node(dst);
2132 ir_node *mem = get_CopyB_mem(node);
2133 ir_node *new_mem = be_transform_node(mem);
2134 ir_node *res = NULL;
2135 ir_graph *irg = current_ir_graph;
2136 dbg_info *dbgi = get_irn_dbg_info(node);
2137 int size = get_type_size_bytes(get_CopyB_type(node));
2140 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2141 /* then we need the size explicitly in ECX. */
2142 if (size >= 32 * 4) {
2143 rem = size & 0x3; /* size % 4 */
2146 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2147 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2149 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2150 /* we misuse the pncode field for the copyb size */
2151 set_ia32_pncode(res, rem);
2153 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2154 set_ia32_pncode(res, size);
2157 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2163 ir_node *gen_be_Copy(ir_node *node)
2165 ir_node *result = be_duplicate_node(node);
2166 ir_mode *mode = get_irn_mode(result);
2168 if (mode_needs_gp_reg(mode)) {
2169 set_irn_mode(result, mode_Iu);
2176 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2177 dbg_info *dbgi, ir_node *block, int use_am)
2179 ir_graph *irg = current_ir_graph;
2180 ir_node *new_block = be_transform_node(block);
2181 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2182 ir_node *nomem = new_rd_NoMem(irg);
2187 ia32_address_mode_t am;
2188 ia32_address_t *addr = &am.addr;
2190 /* can we use a test instruction? */
2191 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2192 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2193 if(is_And(cmp_left) &&
2194 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2195 ir_node *and_left = get_And_left(cmp_left);
2196 ir_node *and_right = get_And_right(cmp_left);
2198 mode = get_irn_mode(and_left);
2199 arg_left = and_left;
2200 arg_right = and_right;
2202 mode = get_irn_mode(cmp_left);
2203 arg_left = cmp_left;
2204 arg_right = cmp_left;
2207 assert(get_mode_size_bits(mode) <= 32);
2209 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
2211 pnc = get_inversed_pnc(pnc);
2213 if(get_mode_size_bits(mode) == 8) {
2214 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2215 addr->index, addr->mem, am.new_op1,
2218 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base, addr->index,
2219 addr->mem, am.new_op1, am.new_op2, pnc);
2221 set_am_attributes(res, &am);
2222 set_ia32_ls_mode(res, mode);
2224 res = fix_mem_proj(res, &am);
2226 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2232 mode = get_irn_mode(cmp_left);
2233 assert(get_mode_size_bits(mode) <= 32);
2235 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am, 1);
2237 pnc = get_inversed_pnc(pnc);
2239 if(get_mode_size_bits(mode) == 8) {
2240 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base, addr->index,
2241 addr->mem, am.new_op1, am.new_op2, pnc);
2243 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2244 addr->mem, am.new_op1, am.new_op2, pnc);
2246 set_am_attributes(res, &am);
2247 set_ia32_ls_mode(res, mode);
2249 res = fix_mem_proj(res, &am);
2251 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, res,
2257 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2258 ir_node *val_true, ir_node *val_false,
2259 dbg_info *dbgi, ir_node *block)
2261 ir_graph *irg = current_ir_graph;
2262 ir_node *new_block = be_transform_node(block);
2263 ir_node *new_val_true = be_transform_node(val_true);
2264 ir_node *new_val_false = be_transform_node(val_false);
2265 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2266 ir_node *nomem = new_NoMem();
2267 ir_node *new_cmp_left;
2268 ir_node *new_cmp_right;
2272 /* cmovs with unknowns are pointless... */
2273 if(is_Unknown(val_true)) {
2274 #ifdef DEBUG_libfirm
2275 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2277 return new_val_false;
2279 if(is_Unknown(val_false)) {
2280 #ifdef DEBUG_libfirm
2281 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2283 return new_val_true;
2286 /* can we use a test instruction? */
2287 if(is_Const_0(cmp_right)) {
2288 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2289 if(is_And(cmp_left) &&
2290 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2291 ir_node *and_left = get_And_left(cmp_left);
2292 ir_node *and_right = get_And_right(cmp_left);
2294 mode = get_irn_mode(and_left);
2295 new_cmp_left = be_transform_node(and_left);
2296 new_cmp_right = create_immediate_or_transform(and_right, 0);
2298 mode = get_irn_mode(cmp_left);
2299 new_cmp_left = be_transform_node(cmp_left);
2300 new_cmp_right = be_transform_node(cmp_left);
2303 assert(get_mode_size_bits(mode) <= 32);
2305 if(get_mode_size_bits(mode) == 8) {
2306 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block, noreg,
2307 noreg, nomem, new_cmp_left, new_cmp_right,
2308 new_val_true, new_val_false, pnc);
2310 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2311 noreg, nomem, new_cmp_left, new_cmp_right,
2312 new_val_true, new_val_false, pnc);
2314 set_ia32_ls_mode(res, mode);
2319 mode = get_irn_mode(cmp_left);
2320 new_cmp_left = be_transform_node(cmp_left);
2321 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2323 /* no support for 8,16 bit modes yet */
2324 assert(get_mode_size_bits(mode) <= 32);
2326 if(get_mode_size_bits(mode) == 8) {
2327 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2328 new_cmp_left, new_cmp_right, new_val_true,
2329 new_val_false, pnc);
2331 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg, nomem,
2332 new_cmp_left, new_cmp_right, new_val_true,
2333 new_val_false, pnc);
2335 set_ia32_ls_mode(res, mode);
2342 * Transforms a Psi node into CMov.
2344 * @return The transformed node.
2346 static ir_node *gen_Psi(ir_node *node) {
2347 ir_node *psi_true = get_Psi_val(node, 0);
2348 ir_node *psi_default = get_Psi_default(node);
2349 ia32_code_gen_t *cg = env_cg;
2350 ir_node *cond = get_Psi_cond(node, 0);
2351 ir_node *block = get_nodes_block(node);
2352 dbg_info *dbgi = get_irn_dbg_info(node);
2359 assert(get_Psi_n_conds(node) == 1);
2360 assert(get_irn_mode(cond) == mode_b);
2361 assert(mode_needs_gp_reg(get_irn_mode(node)));
2363 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2364 /* a mode_b value, we have to compare it against 0 */
2366 cmp_right = new_Const_long(mode_Iu, 0);
2370 ir_node *cmp = get_Proj_pred(cond);
2372 cmp_left = get_Cmp_left(cmp);
2373 cmp_right = get_Cmp_right(cmp);
2374 cmp_mode = get_irn_mode(cmp_left);
2375 pnc = get_Proj_proj(cond);
2377 assert(!mode_is_float(cmp_mode));
2379 if (!mode_is_signed(cmp_mode)) {
2380 pnc |= ia32_pn_Cmp_Unsigned;
2384 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2385 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2386 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2387 pnc = get_negated_pnc(pnc, cmp_mode);
2388 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2390 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2393 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2399 * Create a conversion from x87 state register to general purpose.
2401 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2402 ir_node *block = be_transform_node(get_nodes_block(node));
2403 ir_node *op = get_Conv_op(node);
2404 ir_node *new_op = be_transform_node(op);
2405 ia32_code_gen_t *cg = env_cg;
2406 ir_graph *irg = current_ir_graph;
2407 dbg_info *dbgi = get_irn_dbg_info(node);
2408 ir_node *noreg = ia32_new_NoReg_gp(cg);
2409 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2410 ir_mode *mode = get_irn_mode(node);
2411 ir_node *fist, *load;
2414 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2415 new_NoMem(), new_op, trunc_mode);
2417 set_irn_pinned(fist, op_pin_state_floats);
2418 set_ia32_use_frame(fist);
2419 set_ia32_op_type(fist, ia32_AddrModeD);
2421 assert(get_mode_size_bits(mode) <= 32);
2422 /* exception we can only store signed 32 bit integers, so for unsigned
2423 we store a 64bit (signed) integer and load the lower bits */
2424 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2425 set_ia32_ls_mode(fist, mode_Ls);
2427 set_ia32_ls_mode(fist, mode_Is);
2429 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2432 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2434 set_irn_pinned(load, op_pin_state_floats);
2435 set_ia32_use_frame(load);
2436 set_ia32_op_type(load, ia32_AddrModeS);
2437 set_ia32_ls_mode(load, mode_Is);
2438 if(get_ia32_ls_mode(fist) == mode_Ls) {
2439 ia32_attr_t *attr = get_ia32_attr(load);
2440 attr->data.need_64bit_stackent = 1;
2442 ia32_attr_t *attr = get_ia32_attr(load);
2443 attr->data.need_32bit_stackent = 1;
2445 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2447 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2451 * Creates a x87 strict Conv by placing a Sore and a Load
2453 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2455 ir_node *block = get_nodes_block(node);
2456 ir_graph *irg = current_ir_graph;
2457 dbg_info *dbgi = get_irn_dbg_info(node);
2458 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2459 ir_node *nomem = new_NoMem();
2460 ir_node *frame = get_irg_frame(irg);
2461 ir_node *store, *load;
2464 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2466 set_ia32_use_frame(store);
2467 set_ia32_op_type(store, ia32_AddrModeD);
2468 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2470 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2472 set_ia32_use_frame(load);
2473 set_ia32_op_type(load, ia32_AddrModeS);
2474 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2476 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2481 * Create a conversion from general purpose to x87 register
2483 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2484 ir_node *block = be_transform_node(get_nodes_block(node));
2485 ir_node *op = get_Conv_op(node);
2486 ir_node *new_op = be_transform_node(op);
2487 ir_graph *irg = current_ir_graph;
2488 dbg_info *dbgi = get_irn_dbg_info(node);
2489 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2490 ir_node *nomem = new_NoMem();
2491 ir_mode *mode = get_irn_mode(op);
2492 ir_mode *store_mode;
2493 ir_node *fild, *store;
2497 /* first convert to 32 bit signed if necessary */
2498 src_bits = get_mode_size_bits(src_mode);
2499 if (src_bits == 8) {
2500 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2502 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2504 } else if (src_bits < 32) {
2505 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2507 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2511 assert(get_mode_size_bits(mode) == 32);
2514 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2517 set_ia32_use_frame(store);
2518 set_ia32_op_type(store, ia32_AddrModeD);
2519 set_ia32_ls_mode(store, mode_Iu);
2521 /* exception for 32bit unsigned, do a 64bit spill+load */
2522 if(!mode_is_signed(mode)) {
2525 ir_node *zero_const = create_Immediate_from_int(0);
2527 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2528 get_irg_frame(irg), noreg, nomem,
2531 set_ia32_use_frame(zero_store);
2532 set_ia32_op_type(zero_store, ia32_AddrModeD);
2533 add_ia32_am_offs_int(zero_store, 4);
2534 set_ia32_ls_mode(zero_store, mode_Iu);
2539 store = new_rd_Sync(dbgi, irg, block, 2, in);
2540 store_mode = mode_Ls;
2542 store_mode = mode_Is;
2546 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2548 set_ia32_use_frame(fild);
2549 set_ia32_op_type(fild, ia32_AddrModeS);
2550 set_ia32_ls_mode(fild, store_mode);
2552 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2558 * Crete a conversion from one integer mode into another one
2560 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2561 dbg_info *dbgi, ir_node *block, ir_node *op,
2564 ir_graph *irg = current_ir_graph;
2565 int src_bits = get_mode_size_bits(src_mode);
2566 int tgt_bits = get_mode_size_bits(tgt_mode);
2567 ir_node *new_block = be_transform_node(block);
2568 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2571 ir_mode *smaller_mode;
2573 ia32_address_mode_t am;
2574 ia32_address_t *addr = &am.addr;
2576 if (src_bits < tgt_bits) {
2577 smaller_mode = src_mode;
2578 smaller_bits = src_bits;
2580 smaller_mode = tgt_mode;
2581 smaller_bits = tgt_bits;
2584 memset(&am, 0, sizeof(am));
2585 if(use_source_address_mode(block, op, NULL)) {
2586 build_address(&am, op);
2588 am.op_type = ia32_AddrModeS;
2590 new_op = be_transform_node(op);
2591 am.op_type = ia32_Normal;
2593 if(addr->base == NULL)
2595 if(addr->index == NULL)
2596 addr->index = noreg;
2597 if(addr->mem == NULL)
2598 addr->mem = new_NoMem();
2600 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2601 if (smaller_bits == 8) {
2602 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2603 addr->index, addr->mem, new_op,
2606 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2607 addr->index, addr->mem, new_op,
2611 set_am_attributes(res, &am);
2612 set_ia32_ls_mode(res, smaller_mode);
2613 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2614 res = fix_mem_proj(res, &am);
2620 * Transforms a Conv node.
2622 * @return The created ia32 Conv node
2624 static ir_node *gen_Conv(ir_node *node) {
2625 ir_node *block = get_nodes_block(node);
2626 ir_node *new_block = be_transform_node(block);
2627 ir_node *op = get_Conv_op(node);
2628 ir_node *new_op = NULL;
2629 ir_graph *irg = current_ir_graph;
2630 dbg_info *dbgi = get_irn_dbg_info(node);
2631 ir_mode *src_mode = get_irn_mode(op);
2632 ir_mode *tgt_mode = get_irn_mode(node);
2633 int src_bits = get_mode_size_bits(src_mode);
2634 int tgt_bits = get_mode_size_bits(tgt_mode);
2635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2636 ir_node *nomem = new_rd_NoMem(irg);
2637 ir_node *res = NULL;
2639 if (src_mode == mode_b) {
2640 assert(mode_is_int(tgt_mode));
2641 /* nothing to do, we already model bools as 0/1 ints */
2642 return be_transform_node(op);
2645 if (src_mode == tgt_mode) {
2646 if (get_Conv_strict(node)) {
2647 if (USE_SSE2(env_cg)) {
2648 /* when we are in SSE mode, we can kill all strict no-op conversion */
2649 return be_transform_node(op);
2652 /* this should be optimized already, but who knows... */
2653 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2654 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2655 return be_transform_node(op);
2659 if (mode_is_float(src_mode)) {
2660 new_op = be_transform_node(op);
2661 /* we convert from float ... */
2662 if (mode_is_float(tgt_mode)) {
2663 if(src_mode == mode_E && tgt_mode == mode_D
2664 && !get_Conv_strict(node)) {
2665 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2670 if (USE_SSE2(env_cg)) {
2671 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2672 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2674 set_ia32_ls_mode(res, tgt_mode);
2676 if(get_Conv_strict(node)) {
2677 res = gen_x87_strict_conv(tgt_mode, new_op);
2678 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2681 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2686 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2687 if (USE_SSE2(env_cg)) {
2688 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2690 set_ia32_ls_mode(res, src_mode);
2692 return gen_x87_fp_to_gp(node);
2696 /* we convert from int ... */
2697 if (mode_is_float(tgt_mode)) {
2699 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2700 if (USE_SSE2(env_cg)) {
2701 new_op = be_transform_node(op);
2702 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2704 set_ia32_ls_mode(res, tgt_mode);
2706 res = gen_x87_gp_to_fp(node, src_mode);
2707 if(get_Conv_strict(node)) {
2708 res = gen_x87_strict_conv(tgt_mode, res);
2709 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2710 ia32_get_old_node_name(env_cg, node));
2714 } else if(tgt_mode == mode_b) {
2715 /* mode_b lowering already took care that we only have 0/1 values */
2716 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2717 src_mode, tgt_mode));
2718 return be_transform_node(op);
2721 if (src_bits == tgt_bits) {
2722 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2723 src_mode, tgt_mode));
2724 return be_transform_node(op);
2727 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2736 int check_immediate_constraint(long val, char immediate_constraint_type)
2738 switch (immediate_constraint_type) {
2742 return val >= 0 && val <= 32;
2744 return val >= 0 && val <= 63;
2746 return val >= -128 && val <= 127;
2748 return val == 0xff || val == 0xffff;
2750 return val >= 0 && val <= 3;
2752 return val >= 0 && val <= 255;
2754 return val >= 0 && val <= 127;
2758 panic("Invalid immediate constraint found");
2763 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2766 tarval *offset = NULL;
2767 int offset_sign = 0;
2769 ir_entity *symconst_ent = NULL;
2770 int symconst_sign = 0;
2772 ir_node *cnst = NULL;
2773 ir_node *symconst = NULL;
2779 mode = get_irn_mode(node);
2780 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2784 if(is_Minus(node)) {
2786 node = get_Minus_op(node);
2789 if(is_Const(node)) {
2792 offset_sign = minus;
2793 } else if(is_SymConst(node)) {
2796 symconst_sign = minus;
2797 } else if(is_Add(node)) {
2798 ir_node *left = get_Add_left(node);
2799 ir_node *right = get_Add_right(node);
2800 if(is_Const(left) && is_SymConst(right)) {
2803 symconst_sign = minus;
2804 offset_sign = minus;
2805 } else if(is_SymConst(left) && is_Const(right)) {
2808 symconst_sign = minus;
2809 offset_sign = minus;
2811 } else if(is_Sub(node)) {
2812 ir_node *left = get_Sub_left(node);
2813 ir_node *right = get_Sub_right(node);
2814 if(is_Const(left) && is_SymConst(right)) {
2817 symconst_sign = !minus;
2818 offset_sign = minus;
2819 } else if(is_SymConst(left) && is_Const(right)) {
2822 symconst_sign = minus;
2823 offset_sign = !minus;
2830 offset = get_Const_tarval(cnst);
2831 if(tarval_is_long(offset)) {
2832 val = get_tarval_long(offset);
2834 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2839 if(!check_immediate_constraint(val, immediate_constraint_type))
2842 if(symconst != NULL) {
2843 if(immediate_constraint_type != 0) {
2844 /* we need full 32bits for symconsts */
2848 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2850 symconst_ent = get_SymConst_entity(symconst);
2852 if(cnst == NULL && symconst == NULL)
2855 if(offset_sign && offset != NULL) {
2856 offset = tarval_neg(offset);
2859 irg = current_ir_graph;
2860 dbgi = get_irn_dbg_info(node);
2861 block = get_irg_start_block(irg);
2862 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2863 symconst_sign, val);
2864 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2870 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2872 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2873 if (new_node == NULL) {
2874 new_node = be_transform_node(node);
2879 typedef struct constraint_t constraint_t;
2880 struct constraint_t {
2883 const arch_register_req_t **out_reqs;
2885 const arch_register_req_t *req;
2886 unsigned immediate_possible;
2887 char immediate_type;
2890 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2892 int immediate_possible = 0;
2893 char immediate_type = 0;
2894 unsigned limited = 0;
2895 const arch_register_class_t *cls = NULL;
2896 ir_graph *irg = current_ir_graph;
2897 struct obstack *obst = get_irg_obstack(irg);
2898 arch_register_req_t *req;
2899 unsigned *limited_ptr;
2903 /* TODO: replace all the asserts with nice error messages */
2905 printf("Constraint: %s\n", c);
2915 assert(cls == NULL ||
2916 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2917 cls = &ia32_reg_classes[CLASS_ia32_gp];
2918 limited |= 1 << REG_EAX;
2921 assert(cls == NULL ||
2922 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2923 cls = &ia32_reg_classes[CLASS_ia32_gp];
2924 limited |= 1 << REG_EBX;
2927 assert(cls == NULL ||
2928 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2929 cls = &ia32_reg_classes[CLASS_ia32_gp];
2930 limited |= 1 << REG_ECX;
2933 assert(cls == NULL ||
2934 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2935 cls = &ia32_reg_classes[CLASS_ia32_gp];
2936 limited |= 1 << REG_EDX;
2939 assert(cls == NULL ||
2940 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2941 cls = &ia32_reg_classes[CLASS_ia32_gp];
2942 limited |= 1 << REG_EDI;
2945 assert(cls == NULL ||
2946 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2947 cls = &ia32_reg_classes[CLASS_ia32_gp];
2948 limited |= 1 << REG_ESI;
2951 case 'q': /* q means lower part of the regs only, this makes no
2952 * difference to Q for us (we only assigne whole registers) */
2953 assert(cls == NULL ||
2954 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2955 cls = &ia32_reg_classes[CLASS_ia32_gp];
2956 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2960 assert(cls == NULL ||
2961 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2962 cls = &ia32_reg_classes[CLASS_ia32_gp];
2963 limited |= 1 << REG_EAX | 1 << REG_EDX;
2966 assert(cls == NULL ||
2967 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2968 cls = &ia32_reg_classes[CLASS_ia32_gp];
2969 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2970 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2977 assert(cls == NULL);
2978 cls = &ia32_reg_classes[CLASS_ia32_gp];
2984 /* TODO: mark values so the x87 simulator knows about t and u */
2985 assert(cls == NULL);
2986 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2991 assert(cls == NULL);
2992 /* TODO: check that sse2 is supported */
2993 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3003 assert(!immediate_possible);
3004 immediate_possible = 1;
3005 immediate_type = *c;
3009 assert(!immediate_possible);
3010 immediate_possible = 1;
3014 assert(!immediate_possible && cls == NULL);
3015 immediate_possible = 1;
3016 cls = &ia32_reg_classes[CLASS_ia32_gp];
3029 assert(constraint->is_in && "can only specify same constraint "
3032 sscanf(c, "%d%n", &same_as, &p);
3039 case 'E': /* no float consts yet */
3040 case 'F': /* no float consts yet */
3041 case 's': /* makes no sense on x86 */
3042 case 'X': /* we can't support that in firm */
3046 case '<': /* no autodecrement on x86 */
3047 case '>': /* no autoincrement on x86 */
3048 case 'C': /* sse constant not supported yet */
3049 case 'G': /* 80387 constant not supported yet */
3050 case 'y': /* we don't support mmx registers yet */
3051 case 'Z': /* not available in 32 bit mode */
3052 case 'e': /* not available in 32 bit mode */
3053 assert(0 && "asm constraint not supported");
3056 assert(0 && "unknown asm constraint found");
3063 const arch_register_req_t *other_constr;
3065 assert(cls == NULL && "same as and register constraint not supported");
3066 assert(!immediate_possible && "same as and immediate constraint not "
3068 assert(same_as < constraint->n_outs && "wrong constraint number in "
3069 "same_as constraint");
3071 other_constr = constraint->out_reqs[same_as];
3073 req = obstack_alloc(obst, sizeof(req[0]));
3074 req->cls = other_constr->cls;
3075 req->type = arch_register_req_type_should_be_same;
3076 req->limited = NULL;
3077 req->other_same = pos;
3078 req->other_different = -1;
3080 /* switch constraints. This is because in firm we have same_as
3081 * constraints on the output constraints while in the gcc asm syntax
3082 * they are specified on the input constraints */
3083 constraint->req = other_constr;
3084 constraint->out_reqs[same_as] = req;
3085 constraint->immediate_possible = 0;
3089 if(immediate_possible && cls == NULL) {
3090 cls = &ia32_reg_classes[CLASS_ia32_gp];
3092 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3093 assert(cls != NULL);
3095 if(immediate_possible) {
3096 assert(constraint->is_in
3097 && "imeediates make no sense for output constraints");
3099 /* todo: check types (no float input on 'r' constrained in and such... */
3102 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3103 limited_ptr = (unsigned*) (req+1);
3105 req = obstack_alloc(obst, sizeof(req[0]));
3107 memset(req, 0, sizeof(req[0]));
3110 req->type = arch_register_req_type_limited;
3111 *limited_ptr = limited;
3112 req->limited = limited_ptr;
3114 req->type = arch_register_req_type_normal;
3118 constraint->req = req;
3119 constraint->immediate_possible = immediate_possible;
3120 constraint->immediate_type = immediate_type;
3124 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3131 panic("Clobbers not supported yet");
3135 * generates code for a ASM node
3137 static ir_node *gen_ASM(ir_node *node)
3140 ir_graph *irg = current_ir_graph;
3141 ir_node *block = be_transform_node(get_nodes_block(node));
3142 dbg_info *dbgi = get_irn_dbg_info(node);
3149 ia32_asm_attr_t *attr;
3150 const arch_register_req_t **out_reqs;
3151 const arch_register_req_t **in_reqs;
3152 struct obstack *obst;
3153 constraint_t parsed_constraint;
3155 /* transform inputs */
3156 arity = get_irn_arity(node);
3157 in = alloca(arity * sizeof(in[0]));
3158 memset(in, 0, arity * sizeof(in[0]));
3160 n_outs = get_ASM_n_output_constraints(node);
3161 n_clobbers = get_ASM_n_clobbers(node);
3162 out_arity = n_outs + n_clobbers;
3164 /* construct register constraints */
3165 obst = get_irg_obstack(irg);
3166 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3167 parsed_constraint.out_reqs = out_reqs;
3168 parsed_constraint.n_outs = n_outs;
3169 parsed_constraint.is_in = 0;
3170 for(i = 0; i < out_arity; ++i) {
3174 const ir_asm_constraint *constraint;
3175 constraint = & get_ASM_output_constraints(node) [i];
3176 c = get_id_str(constraint->constraint);
3177 parse_asm_constraint(i, &parsed_constraint, c);
3179 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3180 c = get_id_str(glob_id);
3181 parse_clobber(node, i, &parsed_constraint, c);
3183 out_reqs[i] = parsed_constraint.req;
3186 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3187 parsed_constraint.is_in = 1;
3188 for(i = 0; i < arity; ++i) {
3189 const ir_asm_constraint *constraint;
3193 constraint = & get_ASM_input_constraints(node) [i];
3194 constr_id = constraint->constraint;
3195 c = get_id_str(constr_id);
3196 parse_asm_constraint(i, &parsed_constraint, c);
3197 in_reqs[i] = parsed_constraint.req;
3199 if(parsed_constraint.immediate_possible) {
3200 ir_node *pred = get_irn_n(node, i);
3201 char imm_type = parsed_constraint.immediate_type;
3202 ir_node *immediate = try_create_Immediate(pred, imm_type);
3204 if(immediate != NULL) {
3210 /* transform inputs */
3211 for(i = 0; i < arity; ++i) {
3213 ir_node *transformed;
3218 pred = get_irn_n(node, i);
3219 transformed = be_transform_node(pred);
3220 in[i] = transformed;
3223 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3225 generic_attr = get_irn_generic_attr(res);
3226 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3227 attr->asm_text = get_ASM_text(node);
3228 set_ia32_out_req_all(res, out_reqs);
3229 set_ia32_in_req_all(res, in_reqs);
3231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3236 /********************************************
3239 * | |__ ___ _ __ ___ __| | ___ ___
3240 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3241 * | |_) | __/ | | | (_) | (_| | __/\__ \
3242 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3244 ********************************************/
3247 * Transforms a FrameAddr into an ia32 Add.
3249 static ir_node *gen_be_FrameAddr(ir_node *node) {
3250 ir_node *block = be_transform_node(get_nodes_block(node));
3251 ir_node *op = be_get_FrameAddr_frame(node);
3252 ir_node *new_op = be_transform_node(op);
3253 ir_graph *irg = current_ir_graph;
3254 dbg_info *dbgi = get_irn_dbg_info(node);
3255 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3258 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3259 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3260 set_ia32_use_frame(res);
3262 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3268 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3270 static ir_node *gen_be_Return(ir_node *node) {
3271 ir_graph *irg = current_ir_graph;
3272 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3273 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3274 ir_entity *ent = get_irg_entity(irg);
3275 ir_type *tp = get_entity_type(ent);
3280 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3281 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3284 int pn_ret_val, pn_ret_mem, arity, i;
3286 assert(ret_val != NULL);
3287 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3288 return be_duplicate_node(node);
3291 res_type = get_method_res_type(tp, 0);
3293 if (! is_Primitive_type(res_type)) {
3294 return be_duplicate_node(node);
3297 mode = get_type_mode(res_type);
3298 if (! mode_is_float(mode)) {
3299 return be_duplicate_node(node);
3302 assert(get_method_n_ress(tp) == 1);
3304 pn_ret_val = get_Proj_proj(ret_val);
3305 pn_ret_mem = get_Proj_proj(ret_mem);
3307 /* get the Barrier */
3308 barrier = get_Proj_pred(ret_val);
3310 /* get result input of the Barrier */
3311 ret_val = get_irn_n(barrier, pn_ret_val);
3312 new_ret_val = be_transform_node(ret_val);
3314 /* get memory input of the Barrier */
3315 ret_mem = get_irn_n(barrier, pn_ret_mem);
3316 new_ret_mem = be_transform_node(ret_mem);
3318 frame = get_irg_frame(irg);
3320 dbgi = get_irn_dbg_info(barrier);
3321 block = be_transform_node(get_nodes_block(barrier));
3323 noreg = ia32_new_NoReg_gp(env_cg);
3325 /* store xmm0 onto stack */
3326 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3327 new_ret_mem, new_ret_val);
3328 set_ia32_ls_mode(sse_store, mode);
3329 set_ia32_op_type(sse_store, ia32_AddrModeD);
3330 set_ia32_use_frame(sse_store);
3332 /* load into x87 register */
3333 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3334 set_ia32_op_type(fld, ia32_AddrModeS);
3335 set_ia32_use_frame(fld);
3337 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3338 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3340 /* create a new barrier */
3341 arity = get_irn_arity(barrier);
3342 in = alloca(arity * sizeof(in[0]));
3343 for (i = 0; i < arity; ++i) {
3346 if (i == pn_ret_val) {
3348 } else if (i == pn_ret_mem) {
3351 ir_node *in = get_irn_n(barrier, i);
3352 new_in = be_transform_node(in);
3357 new_barrier = new_ir_node(dbgi, irg, block,
3358 get_irn_op(barrier), get_irn_mode(barrier),
3360 copy_node_attr(barrier, new_barrier);
3361 be_duplicate_deps(barrier, new_barrier);
3362 be_set_transformed_node(barrier, new_barrier);
3363 mark_irn_visited(barrier);
3365 /* transform normally */
3366 return be_duplicate_node(node);
3370 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3372 static ir_node *gen_be_AddSP(ir_node *node) {
3373 ir_node *block = be_transform_node(get_nodes_block(node));
3374 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3376 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3377 ir_node *new_sp = be_transform_node(sp);
3378 ir_graph *irg = current_ir_graph;
3379 dbg_info *dbgi = get_irn_dbg_info(node);
3380 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3381 ir_node *nomem = new_NoMem();
3384 new_sz = create_immediate_or_transform(sz, 0);
3386 /* ia32 stack grows in reverse direction, make a SubSP */
3387 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3389 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3395 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3397 static ir_node *gen_be_SubSP(ir_node *node) {
3398 ir_node *block = be_transform_node(get_nodes_block(node));
3399 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3401 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3402 ir_node *new_sp = be_transform_node(sp);
3403 ir_graph *irg = current_ir_graph;
3404 dbg_info *dbgi = get_irn_dbg_info(node);
3405 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3406 ir_node *nomem = new_NoMem();
3409 new_sz = create_immediate_or_transform(sz, 0);
3411 /* ia32 stack grows in reverse direction, make an AddSP */
3412 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3414 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3420 * This function just sets the register for the Unknown node
3421 * as this is not done during register allocation because Unknown
3422 * is an "ignore" node.
3424 static ir_node *gen_Unknown(ir_node *node) {
3425 ir_mode *mode = get_irn_mode(node);
3427 if (mode_is_float(mode)) {
3428 if (USE_SSE2(env_cg)) {
3429 return ia32_new_Unknown_xmm(env_cg);
3431 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3432 ir_graph *irg = current_ir_graph;
3433 dbg_info *dbgi = get_irn_dbg_info(node);
3434 ir_node *block = get_irg_start_block(irg);
3435 return new_rd_ia32_vfldz(dbgi, irg, block);
3437 } else if (mode_needs_gp_reg(mode)) {
3438 return ia32_new_Unknown_gp(env_cg);
3440 assert(0 && "unsupported Unknown-Mode");
3447 * Change some phi modes
3449 static ir_node *gen_Phi(ir_node *node) {
3450 ir_node *block = be_transform_node(get_nodes_block(node));
3451 ir_graph *irg = current_ir_graph;
3452 dbg_info *dbgi = get_irn_dbg_info(node);
3453 ir_mode *mode = get_irn_mode(node);
3456 if(mode_needs_gp_reg(mode)) {
3457 /* we shouldn't have any 64bit stuff around anymore */
3458 assert(get_mode_size_bits(mode) <= 32);
3459 /* all integer operations are on 32bit registers now */
3461 } else if(mode_is_float(mode)) {
3462 if (USE_SSE2(env_cg)) {
3469 /* phi nodes allow loops, so we use the old arguments for now
3470 * and fix this later */
3471 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3472 get_irn_in(node) + 1);
3473 copy_node_attr(node, phi);
3474 be_duplicate_deps(node, phi);
3476 be_set_transformed_node(node, phi);
3477 be_enqueue_preds(node);
3485 static ir_node *gen_IJmp(ir_node *node) {
3486 /* TODO: support AM */
3487 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3491 /**********************************************************************
3494 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3495 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3496 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3497 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3499 **********************************************************************/
3501 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3503 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3506 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3507 ir_node *val, ir_node *mem);
3510 * Transforms a lowered Load into a "real" one.
3512 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3514 ir_node *block = be_transform_node(get_nodes_block(node));
3515 ir_node *ptr = get_irn_n(node, 0);
3516 ir_node *new_ptr = be_transform_node(ptr);
3517 ir_node *mem = get_irn_n(node, 1);
3518 ir_node *new_mem = be_transform_node(mem);
3519 ir_graph *irg = current_ir_graph;
3520 dbg_info *dbgi = get_irn_dbg_info(node);
3521 ir_mode *mode = get_ia32_ls_mode(node);
3522 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3525 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3527 set_ia32_op_type(new_op, ia32_AddrModeS);
3528 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3529 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3530 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3531 if (is_ia32_am_sc_sign(node))
3532 set_ia32_am_sc_sign(new_op);
3533 set_ia32_ls_mode(new_op, mode);
3534 if (is_ia32_use_frame(node)) {
3535 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3536 set_ia32_use_frame(new_op);
3539 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3545 * Transforms a lowered Store into a "real" one.
3547 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3549 ir_node *block = be_transform_node(get_nodes_block(node));
3550 ir_node *ptr = get_irn_n(node, 0);
3551 ir_node *new_ptr = be_transform_node(ptr);
3552 ir_node *val = get_irn_n(node, 1);
3553 ir_node *new_val = be_transform_node(val);
3554 ir_node *mem = get_irn_n(node, 2);
3555 ir_node *new_mem = be_transform_node(mem);
3556 ir_graph *irg = current_ir_graph;
3557 dbg_info *dbgi = get_irn_dbg_info(node);
3558 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3559 ir_mode *mode = get_ia32_ls_mode(node);
3563 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3565 am_offs = get_ia32_am_offs_int(node);
3566 add_ia32_am_offs_int(new_op, am_offs);
3568 set_ia32_op_type(new_op, ia32_AddrModeD);
3569 set_ia32_ls_mode(new_op, mode);
3570 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3571 set_ia32_use_frame(new_op);
3573 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3580 * Transforms an ia32_l_XXX into a "real" XXX node
3582 * @param node The node to transform
3583 * @return the created ia32 XXX node
3585 #define GEN_LOWERED_OP(op) \
3586 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3587 return gen_binop(node, get_binop_left(node), \
3588 get_binop_right(node), new_rd_ia32_##op,0); \
3591 #define GEN_LOWERED_x87_OP(op) \
3592 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3594 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3595 get_binop_right(node), new_rd_ia32_##op); \
3599 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3600 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3601 return gen_shift_binop(node, get_irn_n(node, 0), \
3602 get_irn_n(node, 1), new_rd_ia32_##op); \
3605 GEN_LOWERED_x87_OP(vfprem)
3606 GEN_LOWERED_x87_OP(vfmul)
3607 GEN_LOWERED_x87_OP(vfsub)
3608 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3609 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3610 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3611 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3613 static ir_node *gen_ia32_l_Add(ir_node *node) {
3614 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3615 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3616 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3618 if(is_Proj(lowered)) {
3619 lowered = get_Proj_pred(lowered);
3621 assert(is_ia32_Add(lowered));
3622 set_irn_mode(lowered, mode_T);
3628 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3629 ir_node *src_block = get_nodes_block(node);
3630 ir_node *block = be_transform_node(src_block);
3631 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3632 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3633 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3634 ir_node *new_flags = be_transform_node(flags);
3635 ir_graph *irg = current_ir_graph;
3636 dbg_info *dbgi = get_irn_dbg_info(node);
3638 ia32_address_mode_t am;
3639 ia32_address_t *addr = &am.addr;
3641 match_arguments(&am, src_block, op1, op2, 1, 0, 1, 0);
3643 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3644 addr->mem, am.new_op1, am.new_op2, new_flags);
3645 set_am_attributes(new_node, &am);
3646 /* we can't use source address mode anymore when using immediates */
3647 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3648 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3649 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3651 new_node = fix_mem_proj(new_node, &am);
3657 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3659 * @param node The node to transform
3660 * @return the created ia32 Neg node
3662 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3663 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3667 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3669 * @param node The node to transform
3670 * @return the created ia32 vfild node
3672 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3673 return gen_lowered_Load(node, new_rd_ia32_vfild);
3677 * Transforms an ia32_l_Load into a "real" ia32_Load node
3679 * @param node The node to transform
3680 * @return the created ia32 Load node
3682 static ir_node *gen_ia32_l_Load(ir_node *node) {
3683 return gen_lowered_Load(node, new_rd_ia32_Load);
3687 * Transforms an ia32_l_Store into a "real" ia32_Store node
3689 * @param node The node to transform
3690 * @return the created ia32 Store node
3692 static ir_node *gen_ia32_l_Store(ir_node *node) {
3693 return gen_lowered_Store(node, new_rd_ia32_Store);
3697 * Transforms a l_vfist into a "real" vfist node.
3699 * @param node The node to transform
3700 * @return the created ia32 vfist node
3702 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3703 ir_node *block = be_transform_node(get_nodes_block(node));
3704 ir_node *ptr = get_irn_n(node, 0);
3705 ir_node *new_ptr = be_transform_node(ptr);
3706 ir_node *val = get_irn_n(node, 1);
3707 ir_node *new_val = be_transform_node(val);
3708 ir_node *mem = get_irn_n(node, 2);
3709 ir_node *new_mem = be_transform_node(mem);
3710 ir_graph *irg = current_ir_graph;
3711 dbg_info *dbgi = get_irn_dbg_info(node);
3712 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3713 ir_mode *mode = get_ia32_ls_mode(node);
3714 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3718 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3719 new_val, trunc_mode);
3721 am_offs = get_ia32_am_offs_int(node);
3722 add_ia32_am_offs_int(new_op, am_offs);
3724 set_ia32_op_type(new_op, ia32_AddrModeD);
3725 set_ia32_ls_mode(new_op, mode);
3726 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3727 set_ia32_use_frame(new_op);
3729 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3735 * Transforms a l_vfdiv into a "real" vfdiv node.
3737 * @param env The transformation environment
3738 * @return the created ia32 vfdiv node
3740 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3741 ir_node *block = be_transform_node(get_nodes_block(node));
3742 ir_node *left = get_binop_left(node);
3743 ir_node *new_left = be_transform_node(left);
3744 ir_node *right = get_binop_right(node);
3745 ir_node *new_right = be_transform_node(right);
3746 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3747 ir_graph *irg = current_ir_graph;
3748 dbg_info *dbgi = get_irn_dbg_info(node);
3749 ir_node *fpcw = get_fpcw();
3752 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3753 new_left, new_right, fpcw);
3754 clear_ia32_commutative(vfdiv);
3756 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3762 * Transforms a l_MulS into a "real" MulS node.
3764 * @param env The transformation environment
3765 * @return the created ia32 Mul node
3767 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3768 ir_node *block = be_transform_node(get_nodes_block(node));
3769 ir_node *left = get_binop_left(node);
3770 ir_node *new_left = be_transform_node(left);
3771 ir_node *right = get_binop_right(node);
3772 ir_node *new_right = be_transform_node(right);
3773 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3774 ir_graph *irg = current_ir_graph;
3775 dbg_info *dbgi = get_irn_dbg_info(node);
3777 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3778 /* and then skip the result Proj, because all needed Projs are already there. */
3779 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3780 new_left, new_right);
3781 clear_ia32_commutative(muls);
3783 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3789 * Transforms a l_IMulS into a "real" IMul1OPS node.
3791 * @param env The transformation environment
3792 * @return the created ia32 IMul1OP node
3794 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3795 ir_node *block = be_transform_node(get_nodes_block(node));
3796 ir_node *left = get_binop_left(node);
3797 ir_node *new_left = be_transform_node(left);
3798 ir_node *right = get_binop_right(node);
3799 ir_node *new_right = be_transform_node(right);
3800 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3801 ir_graph *irg = current_ir_graph;
3802 dbg_info *dbgi = get_irn_dbg_info(node);
3804 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3805 /* and then skip the result Proj, because all needed Projs are already there. */
3806 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3807 new_NoMem(), new_left, new_right);
3808 clear_ia32_commutative(muls);
3810 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3815 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3817 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3818 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3819 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3820 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3821 ir_node *block = be_transform_node(get_nodes_block(node));
3822 dbg_info *dbgi = get_irn_dbg_info(node);
3823 ir_graph *irg = current_ir_graph;
3824 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3825 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3829 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3831 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3832 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3833 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3834 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3835 ir_node *block = be_transform_node(get_nodes_block(node));
3836 dbg_info *dbgi = get_irn_dbg_info(node);
3837 ir_graph *irg = current_ir_graph;
3838 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3839 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3844 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3845 * op1 - target to be shifted
3846 * op2 - contains bits to be shifted into target
3848 * Only op3 can be an immediate.
3850 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3851 ir_node *op2, ir_node *count)
3853 ir_node *block = be_transform_node(get_nodes_block(node));
3854 ir_node *new_op = NULL;
3855 ir_graph *irg = current_ir_graph;
3856 dbg_info *dbgi = get_irn_dbg_info(node);
3857 ir_node *new_op1 = be_transform_node(op1);
3858 ir_node *new_op2 = be_transform_node(op2);
3859 ir_node *new_count = create_immediate_or_transform(count, 'I');
3861 /* TODO proper AM support */
3863 if (is_ia32_l_ShlD(node))
3864 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3866 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3868 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3873 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3874 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3875 get_irn_n(node, 1), get_irn_n(node, 2));
3878 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3879 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3880 get_irn_n(node, 1), get_irn_n(node, 2));
3884 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3886 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3887 ir_node *block = be_transform_node(get_nodes_block(node));
3888 ir_node *val = get_irn_n(node, 1);
3889 ir_node *new_val = be_transform_node(val);
3890 ia32_code_gen_t *cg = env_cg;
3891 ir_node *res = NULL;
3892 ir_graph *irg = current_ir_graph;
3894 ir_node *noreg, *new_ptr, *new_mem;
3901 mem = get_irn_n(node, 2);
3902 new_mem = be_transform_node(mem);
3903 ptr = get_irn_n(node, 0);
3904 new_ptr = be_transform_node(ptr);
3905 noreg = ia32_new_NoReg_gp(cg);
3906 dbgi = get_irn_dbg_info(node);
3908 /* Store x87 -> MEM */
3909 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3910 get_ia32_ls_mode(node));
3911 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3912 set_ia32_use_frame(res);
3913 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3914 set_ia32_op_type(res, ia32_AddrModeD);
3916 /* Load MEM -> SSE */
3917 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3918 get_ia32_ls_mode(node));
3919 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3920 set_ia32_use_frame(res);
3921 set_ia32_op_type(res, ia32_AddrModeS);
3922 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3928 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3930 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3931 ir_node *block = be_transform_node(get_nodes_block(node));
3932 ir_node *val = get_irn_n(node, 1);
3933 ir_node *new_val = be_transform_node(val);
3934 ia32_code_gen_t *cg = env_cg;
3935 ir_graph *irg = current_ir_graph;
3936 ir_node *res = NULL;
3937 ir_entity *fent = get_ia32_frame_ent(node);
3938 ir_mode *lsmode = get_ia32_ls_mode(node);
3940 ir_node *noreg, *new_ptr, *new_mem;
3944 if (! USE_SSE2(cg)) {
3945 /* SSE unit is not used -> skip this node. */
3949 ptr = get_irn_n(node, 0);
3950 new_ptr = be_transform_node(ptr);
3951 mem = get_irn_n(node, 2);
3952 new_mem = be_transform_node(mem);
3953 noreg = ia32_new_NoReg_gp(cg);
3954 dbgi = get_irn_dbg_info(node);
3956 /* Store SSE -> MEM */
3957 if (is_ia32_xLoad(skip_Proj(new_val))) {
3958 ir_node *ld = skip_Proj(new_val);
3960 /* we can vfld the value directly into the fpu */
3961 fent = get_ia32_frame_ent(ld);
3962 ptr = get_irn_n(ld, 0);
3963 offs = get_ia32_am_offs_int(ld);
3965 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3967 set_ia32_frame_ent(res, fent);
3968 set_ia32_use_frame(res);
3969 set_ia32_ls_mode(res, lsmode);
3970 set_ia32_op_type(res, ia32_AddrModeD);
3974 /* Load MEM -> x87 */
3975 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3976 set_ia32_frame_ent(res, fent);
3977 set_ia32_use_frame(res);
3978 add_ia32_am_offs_int(res, offs);
3979 set_ia32_op_type(res, ia32_AddrModeS);
3980 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3985 /*********************************************************
3988 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3989 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3990 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3991 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3993 *********************************************************/
3996 * the BAD transformer.
3998 static ir_node *bad_transform(ir_node *node) {
3999 panic("No transform function for %+F available.\n", node);
4004 * Transform the Projs of an AddSP.
4006 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4007 ir_node *block = be_transform_node(get_nodes_block(node));
4008 ir_node *pred = get_Proj_pred(node);
4009 ir_node *new_pred = be_transform_node(pred);
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = get_irn_dbg_info(node);
4012 long proj = get_Proj_proj(node);
4014 if (proj == pn_be_AddSP_sp) {
4015 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4016 pn_ia32_SubSP_stack);
4017 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4019 } else if(proj == pn_be_AddSP_res) {
4020 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4021 pn_ia32_SubSP_addr);
4022 } else if (proj == pn_be_AddSP_M) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4027 return new_rd_Unknown(irg, get_irn_mode(node));
4031 * Transform the Projs of a SubSP.
4033 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4034 ir_node *block = be_transform_node(get_nodes_block(node));
4035 ir_node *pred = get_Proj_pred(node);
4036 ir_node *new_pred = be_transform_node(pred);
4037 ir_graph *irg = current_ir_graph;
4038 dbg_info *dbgi = get_irn_dbg_info(node);
4039 long proj = get_Proj_proj(node);
4041 if (proj == pn_be_SubSP_sp) {
4042 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4043 pn_ia32_AddSP_stack);
4044 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4046 } else if (proj == pn_be_SubSP_M) {
4047 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4051 return new_rd_Unknown(irg, get_irn_mode(node));
4055 * Transform and renumber the Projs from a Load.
4057 static ir_node *gen_Proj_Load(ir_node *node) {
4059 ir_node *block = be_transform_node(get_nodes_block(node));
4060 ir_node *pred = get_Proj_pred(node);
4061 ir_graph *irg = current_ir_graph;
4062 dbg_info *dbgi = get_irn_dbg_info(node);
4063 long proj = get_Proj_proj(node);
4066 /* loads might be part of source address mode matches, so we don't
4067 transform the ProjMs yet (with the exception of loads whose result is
4070 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4073 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4075 /* this is needed, because sometimes we have loops that are only
4076 reachable through the ProjM */
4077 be_enqueue_preds(node);
4078 /* do it in 2 steps, to silence firm verifier */
4079 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4080 set_Proj_proj(res, pn_ia32_Load_M);
4084 /* renumber the proj */
4085 new_pred = be_transform_node(pred);
4086 if (is_ia32_Load(new_pred)) {
4087 if (proj == pn_Load_res) {
4088 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4090 } else if (proj == pn_Load_M) {
4091 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4094 } else if(is_ia32_Conv_I2I(new_pred)) {
4095 set_irn_mode(new_pred, mode_T);
4096 if (proj == pn_Load_res) {
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4098 } else if (proj == pn_Load_M) {
4099 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4101 } else if (is_ia32_xLoad(new_pred)) {
4102 if (proj == pn_Load_res) {
4103 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4105 } else if (proj == pn_Load_M) {
4106 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4109 } else if (is_ia32_vfld(new_pred)) {
4110 if (proj == pn_Load_res) {
4111 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4113 } else if (proj == pn_Load_M) {
4114 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4118 /* can happen for ProJMs when source address mode happened for the
4121 /* however it should not be the result proj, as that would mean the
4122 load had multiple users and should not have been used for
4124 if(proj != pn_Load_M) {
4125 panic("internal error: transformed node not a Load");
4127 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4131 return new_rd_Unknown(irg, get_irn_mode(node));
4135 * Transform and renumber the Projs from a DivMod like instruction.
4137 static ir_node *gen_Proj_DivMod(ir_node *node) {
4138 ir_node *block = be_transform_node(get_nodes_block(node));
4139 ir_node *pred = get_Proj_pred(node);
4140 ir_node *new_pred = be_transform_node(pred);
4141 ir_graph *irg = current_ir_graph;
4142 dbg_info *dbgi = get_irn_dbg_info(node);
4143 ir_mode *mode = get_irn_mode(node);
4144 long proj = get_Proj_proj(node);
4146 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4148 switch (get_irn_opcode(pred)) {
4152 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4154 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4162 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4164 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4172 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4173 case pn_DivMod_res_div:
4174 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4175 case pn_DivMod_res_mod:
4176 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4186 return new_rd_Unknown(irg, mode);
4190 * Transform and renumber the Projs from a CopyB.
4192 static ir_node *gen_Proj_CopyB(ir_node *node) {
4193 ir_node *block = be_transform_node(get_nodes_block(node));
4194 ir_node *pred = get_Proj_pred(node);
4195 ir_node *new_pred = be_transform_node(pred);
4196 ir_graph *irg = current_ir_graph;
4197 dbg_info *dbgi = get_irn_dbg_info(node);
4198 ir_mode *mode = get_irn_mode(node);
4199 long proj = get_Proj_proj(node);
4202 case pn_CopyB_M_regular:
4203 if (is_ia32_CopyB_i(new_pred)) {
4204 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4205 } else if (is_ia32_CopyB(new_pred)) {
4206 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4214 return new_rd_Unknown(irg, mode);
4218 * Transform and renumber the Projs from a vfdiv.
4220 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4221 ir_node *block = be_transform_node(get_nodes_block(node));
4222 ir_node *pred = get_Proj_pred(node);
4223 ir_node *new_pred = be_transform_node(pred);
4224 ir_graph *irg = current_ir_graph;
4225 dbg_info *dbgi = get_irn_dbg_info(node);
4226 ir_mode *mode = get_irn_mode(node);
4227 long proj = get_Proj_proj(node);
4230 case pn_ia32_l_vfdiv_M:
4231 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4232 case pn_ia32_l_vfdiv_res:
4233 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4238 return new_rd_Unknown(irg, mode);
4242 * Transform and renumber the Projs from a Quot.
4244 static ir_node *gen_Proj_Quot(ir_node *node) {
4245 ir_node *block = be_transform_node(get_nodes_block(node));
4246 ir_node *pred = get_Proj_pred(node);
4247 ir_node *new_pred = be_transform_node(pred);
4248 ir_graph *irg = current_ir_graph;
4249 dbg_info *dbgi = get_irn_dbg_info(node);
4250 ir_mode *mode = get_irn_mode(node);
4251 long proj = get_Proj_proj(node);
4255 if (is_ia32_xDiv(new_pred)) {
4256 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4257 } else if (is_ia32_vfdiv(new_pred)) {
4258 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4262 if (is_ia32_xDiv(new_pred)) {
4263 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4264 } else if (is_ia32_vfdiv(new_pred)) {
4265 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4273 return new_rd_Unknown(irg, mode);
4277 * Transform the Thread Local Storage Proj.
4279 static ir_node *gen_Proj_tls(ir_node *node) {
4280 ir_node *block = be_transform_node(get_nodes_block(node));
4281 ir_graph *irg = current_ir_graph;
4282 dbg_info *dbgi = NULL;
4283 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4289 * Transform the Projs from a be_Call.
4291 static ir_node *gen_Proj_be_Call(ir_node *node) {
4292 ir_node *block = be_transform_node(get_nodes_block(node));
4293 ir_node *call = get_Proj_pred(node);
4294 ir_node *new_call = be_transform_node(call);
4295 ir_graph *irg = current_ir_graph;
4296 dbg_info *dbgi = get_irn_dbg_info(node);
4297 ir_type *method_type = be_Call_get_type(call);
4298 int n_res = get_method_n_ress(method_type);
4299 long proj = get_Proj_proj(node);
4300 ir_mode *mode = get_irn_mode(node);
4302 const arch_register_class_t *cls;
4304 /* The following is kinda tricky: If we're using SSE, then we have to
4305 * move the result value of the call in floating point registers to an
4306 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4307 * after the call, we have to make sure to correctly make the
4308 * MemProj and the result Proj use these 2 nodes
4310 if (proj == pn_be_Call_M_regular) {
4311 // get new node for result, are we doing the sse load/store hack?
4312 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4313 ir_node *call_res_new;
4314 ir_node *call_res_pred = NULL;
4316 if (call_res != NULL) {
4317 call_res_new = be_transform_node(call_res);
4318 call_res_pred = get_Proj_pred(call_res_new);
4321 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4322 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4323 pn_be_Call_M_regular);
4325 assert(is_ia32_xLoad(call_res_pred));
4326 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4330 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4331 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4332 && USE_SSE2(env_cg)) {
4334 ir_node *frame = get_irg_frame(irg);
4335 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4337 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4340 /* in case there is no memory output: create one to serialize the copy
4342 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4343 pn_be_Call_M_regular);
4344 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4345 pn_be_Call_first_res);
4347 /* store st(0) onto stack */
4348 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4350 set_ia32_op_type(fstp, ia32_AddrModeD);
4351 set_ia32_use_frame(fstp);
4353 /* load into SSE register */
4354 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4356 set_ia32_op_type(sse_load, ia32_AddrModeS);
4357 set_ia32_use_frame(sse_load);
4359 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4365 /* transform call modes */
4366 if (mode_is_data(mode)) {
4367 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4371 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4375 * Transform the Projs from a Cmp.
4377 static ir_node *gen_Proj_Cmp(ir_node *node)
4379 /* normally Cmps are processed when looking at Cond nodes, but this case
4380 * can happen in complicated Psi conditions */
4382 ir_node *cmp = get_Proj_pred(node);
4383 long pnc = get_Proj_proj(node);
4384 ir_node *cmp_left = get_Cmp_left(cmp);
4385 ir_node *cmp_right = get_Cmp_right(cmp);
4386 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4387 dbg_info *dbgi = get_irn_dbg_info(cmp);
4388 ir_node *block = get_nodes_block(node);
4392 assert(!mode_is_float(cmp_mode));
4394 if(!mode_is_signed(cmp_mode)) {
4395 pnc |= ia32_pn_Cmp_Unsigned;
4399 * address mode makes only sense when we'll be the only node using the cmp
4401 use_am = get_irn_n_edges(cmp) <= 1;
4403 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4404 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4410 * Transform and potentially renumber Proj nodes.
4412 static ir_node *gen_Proj(ir_node *node) {
4413 ir_graph *irg = current_ir_graph;
4414 dbg_info *dbgi = get_irn_dbg_info(node);
4415 ir_node *pred = get_Proj_pred(node);
4416 long proj = get_Proj_proj(node);
4418 if (is_Store(pred)) {
4419 if (proj == pn_Store_M) {
4420 return be_transform_node(pred);
4423 return new_r_Bad(irg);
4425 } else if (is_Load(pred)) {
4426 return gen_Proj_Load(node);
4427 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4428 return gen_Proj_DivMod(node);
4429 } else if (is_CopyB(pred)) {
4430 return gen_Proj_CopyB(node);
4431 } else if (is_Quot(pred)) {
4432 return gen_Proj_Quot(node);
4433 } else if (is_ia32_l_vfdiv(pred)) {
4434 return gen_Proj_l_vfdiv(node);
4435 } else if (be_is_SubSP(pred)) {
4436 return gen_Proj_be_SubSP(node);
4437 } else if (be_is_AddSP(pred)) {
4438 return gen_Proj_be_AddSP(node);
4439 } else if (be_is_Call(pred)) {
4440 return gen_Proj_be_Call(node);
4441 } else if (is_Cmp(pred)) {
4442 return gen_Proj_Cmp(node);
4443 } else if (get_irn_op(pred) == op_Start) {
4444 if (proj == pn_Start_X_initial_exec) {
4445 ir_node *block = get_nodes_block(pred);
4448 /* we exchange the ProjX with a jump */
4449 block = be_transform_node(block);
4450 jump = new_rd_Jmp(dbgi, irg, block);
4453 if (node == be_get_old_anchor(anchor_tls)) {
4454 return gen_Proj_tls(node);
4457 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4461 ir_node *new_pred = be_transform_node(pred);
4462 ir_node *block = be_transform_node(get_nodes_block(node));
4463 ir_mode *mode = get_irn_mode(node);
4464 if (mode_needs_gp_reg(mode)) {
4465 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4466 get_Proj_proj(node));
4467 #ifdef DEBUG_libfirm
4468 new_proj->node_nr = node->node_nr;
4474 return be_duplicate_node(node);
4478 * Enters all transform functions into the generic pointer
4480 static void register_transformers(void)
4484 /* first clear the generic function pointer for all ops */
4485 clear_irp_opcodes_generic_func();
4487 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4488 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4525 /* transform ops from intrinsic lowering */
4547 GEN(ia32_l_X87toSSE);
4548 GEN(ia32_l_SSEtoX87);
4554 /* we should never see these nodes */
4569 /* handle generic backend nodes */
4577 op_Mulh = get_op_Mulh();
4586 * Pre-transform all unknown and noreg nodes.
4588 static void ia32_pretransform_node(void *arch_cg) {
4589 ia32_code_gen_t *cg = arch_cg;
4591 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4592 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4593 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4594 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4595 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4596 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4601 * Walker, checks if all ia32 nodes producing more than one result have
4602 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4605 void add_missing_keep_walker(ir_node *node, void *data)
4608 unsigned found_projs = 0;
4609 const ir_edge_t *edge;
4610 ir_mode *mode = get_irn_mode(node);
4615 if(!is_ia32_irn(node))
4618 n_outs = get_ia32_n_res(node);
4621 if(is_ia32_SwitchJmp(node))
4624 assert(n_outs < (int) sizeof(unsigned) * 8);
4625 foreach_out_edge(node, edge) {
4626 ir_node *proj = get_edge_src_irn(edge);
4627 int pn = get_Proj_proj(proj);
4629 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4630 found_projs |= 1 << pn;
4634 /* are keeps missing? */
4636 for(i = 0; i < n_outs; ++i) {
4639 const arch_register_req_t *req;
4640 const arch_register_class_t *class;
4642 if(found_projs & (1 << i)) {
4646 req = get_ia32_out_req(node, i);
4651 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4655 block = get_nodes_block(node);
4656 in[0] = new_r_Proj(current_ir_graph, block, node,
4657 arch_register_class_mode(class), i);
4658 if(last_keep != NULL) {
4659 be_Keep_add_node(last_keep, class, in[0]);
4661 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4662 if(sched_is_scheduled(node)) {
4663 sched_add_after(node, last_keep);
4670 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4673 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4675 ir_graph *irg = be_get_birg_irg(cg->birg);
4676 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4679 /* do the transformation */
4680 void ia32_transform_graph(ia32_code_gen_t *cg) {
4681 register_transformers();
4683 initial_fpcw = NULL;
4685 heights = heights_new(cg->irg);
4687 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4689 heights_free(heights);
4693 void ia32_init_transform(void)
4695 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");