2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "archop.h" /* we need this for Min and Max nodes */
57 #include "../benode_t.h"
58 #include "../besched.h"
60 #include "../beutil.h"
61 #include "../beirg_t.h"
63 #include "bearch_ia32_t.h"
64 #include "ia32_nodes_attr.h"
65 #include "ia32_transform.h"
66 #include "ia32_new_nodes.h"
67 #include "ia32_map_regs.h"
68 #include "ia32_dbg_stat.h"
69 #include "ia32_optimize.h"
70 #include "ia32_util.h"
72 #include "gen_ia32_regalloc_if.h"
74 #define SFP_SIGN "0x80000000"
75 #define DFP_SIGN "0x8000000000000000"
76 #define SFP_ABS "0x7FFFFFFF"
77 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 typedef struct ia32_transform_env_t {
95 ir_graph *irg; /**< The irg, the node should be created in */
96 ia32_code_gen_t *cg; /**< The code generator */
97 int visited; /**< visited count that indicates whether a
98 node is already transformed */
99 pdeq *worklist; /**< worklist of nodes that still need to be
101 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
102 } ia32_transform_env_t;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
127 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
128 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
131 static INLINE int mode_needs_gp_reg(ir_mode *mode)
133 if(mode == mode_fpcw)
136 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
139 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
141 set_irn_link(old_node, new_node);
144 static INLINE ir_node *get_new_node(ir_node *old_node)
146 assert(irn_visited(old_node));
147 return (ir_node*) get_irn_link(old_node);
151 * Returns 1 if irn is a Const representing 0, 0 otherwise
153 static INLINE int is_ia32_Const_0(ir_node *irn) {
154 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
155 && tarval_is_null(get_ia32_Immop_tarval(irn));
159 * Returns 1 if irn is a Const representing 1, 0 otherwise
161 static INLINE int is_ia32_Const_1(ir_node *irn) {
162 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
163 && tarval_is_one(get_ia32_Immop_tarval(irn));
167 * Collects all Projs of a node into the node array. Index is the projnum.
168 * BEWARE: The caller has to assure the appropriate array size!
170 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
171 const ir_edge_t *edge;
172 assert(get_irn_mode(irn) == mode_T && "need mode_T");
174 memset(projs, 0, size * sizeof(projs[0]));
176 foreach_out_edge(irn, edge) {
177 ir_node *proj = get_edge_src_irn(edge);
178 int proj_proj = get_Proj_proj(proj);
179 assert(proj_proj < size);
180 projs[proj_proj] = proj;
185 * Renumbers the proj having pn_old in the array tp pn_new
186 * and removes the proj from the array.
188 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
189 fprintf(stderr, "Warning: renumber_Proj used!\n");
191 set_Proj_proj(projs[pn_old], pn_new);
192 projs[pn_old] = NULL;
197 * creates a unique ident by adding a number to a tag
199 * @param tag the tag string, must contain a %d if a number
202 static ident *unique_id(const char *tag)
204 static unsigned id = 0;
207 snprintf(str, sizeof(str), tag, ++id);
208 return new_id_from_str(str);
212 * Get a primitive type for a mode.
214 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
216 pmap_entry *e = pmap_find(types, mode);
221 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
222 res = new_type_primitive(new_id_from_str(buf), mode);
223 pmap_insert(types, mode, res);
231 * Get an entity that is initialized with a tarval
233 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
235 tarval *tv = get_Const_tarval(cnst);
236 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
241 ir_mode *mode = get_irn_mode(cnst);
242 ir_type *tp = get_Const_type(cnst);
243 if (tp == firm_unknown_type)
244 tp = get_prim_type(cg->isa->types, mode);
246 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
248 set_entity_ld_ident(res, get_entity_ident(res));
249 set_entity_visibility(res, visibility_local);
250 set_entity_variability(res, variability_constant);
251 set_entity_allocation(res, allocation_static);
253 /* we create a new entity here: It's initialization must resist on the
255 rem = current_ir_graph;
256 current_ir_graph = get_const_code_irg();
257 set_atomic_ent_value(res, new_Const_type(tv, tp));
258 current_ir_graph = rem;
260 pmap_insert(cg->isa->tv_ent, tv, res);
269 * Transforms a Const.
271 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
272 ir_graph *irg = env->irg;
273 dbg_info *dbgi = get_irn_dbg_info(node);
274 ir_mode *mode = get_irn_mode(node);
275 ir_node *block = transform_node(env, get_nodes_block(node));
277 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env->cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env->cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
298 set_ia32_am_support(load, ia32_am_Source);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env->cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_am_support(load, ia32_am_Source);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(load, get_irg_frame(irg));
327 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
330 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
337 set_ia32_Const_attr(cnst, node);
338 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
343 return new_r_Bad(irg);
347 * Transforms a SymConst.
349 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
350 ir_graph *irg = env->irg;
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
353 ir_node *block = transform_node(env, get_nodes_block(node));
356 if (mode_is_float(mode)) {
358 if (USE_SSE2(env->cg))
359 cnst = new_rd_ia32_xConst(dbgi, irg, block);
361 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
362 set_ia32_ls_mode(cnst, mode);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
381 * SSE convert of an integer node into a floating point node.
383 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
384 ir_graph *irg, ir_node *block,
385 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
387 ir_node *noreg = ia32_new_NoReg_gp(cg);
388 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *old_pred = get_Cmp_left(old_node);
390 ir_mode *in_mode = get_irn_mode(old_pred);
391 int in_bits = get_mode_size_bits(in_mode);
393 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_ls_mode(conv, tgt_mode);
396 set_ia32_am_support(conv, ia32_am_Source);
398 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
404 * SSE convert of an float node into a double node.
406 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
407 ir_graph *irg, ir_node *block,
408 ir_node *in, ir_node *old_node)
410 ir_node *noreg = ia32_new_NoReg_gp(cg);
411 ir_node *nomem = new_rd_NoMem(irg);
413 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
414 set_ia32_am_support(conv, ia32_am_Source);
415 set_ia32_ls_mode(conv, mode_xmm);
416 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
421 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
422 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
423 static const struct {
425 const char *ent_name;
426 const char *cnst_str;
427 } names [ia32_known_const_max] = {
428 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
429 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
430 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
431 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
433 static ir_entity *ent_cache[ia32_known_const_max];
435 const char *tp_name, *ent_name, *cnst_str;
443 ent_name = names[kct].ent_name;
444 if (! ent_cache[kct]) {
445 tp_name = names[kct].tp_name;
446 cnst_str = names[kct].cnst_str;
448 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
450 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
451 tp = new_type_primitive(new_id_from_str(tp_name), mode);
452 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
454 set_entity_ld_ident(ent, get_entity_ident(ent));
455 set_entity_visibility(ent, visibility_local);
456 set_entity_variability(ent, variability_constant);
457 set_entity_allocation(ent, allocation_static);
459 /* we create a new entity here: It's initialization must resist on the
461 rem = current_ir_graph;
462 current_ir_graph = get_const_code_irg();
463 cnst = new_Const(mode, tv);
464 current_ir_graph = rem;
466 set_atomic_ent_value(ent, cnst);
468 /* cache the entry */
469 ent_cache[kct] = ent;
472 return ent_cache[kct];
477 * Prints the old node name on cg obst and returns a pointer to it.
479 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
480 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
482 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
483 obstack_1grow(isa->name_obst, 0);
484 return obstack_finish(isa->name_obst);
488 /* determine if one operator is an Imm */
489 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
491 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
493 return is_ia32_Cnst(op2) ? op2 : NULL;
497 /* determine if one operator is not an Imm */
498 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
499 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
502 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
506 if(! (env->cg->opt & IA32_OPT_IMMOPS))
509 left = get_irn_n(node, in1);
510 right = get_irn_n(node, in2);
511 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
512 /* we can only set right operand to immediate */
513 if(!is_ia32_commutative(node))
515 /* exchange left/right */
516 set_irn_n(node, in1, right);
517 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
518 copy_ia32_Immop_attr(node, left);
519 } else if(is_ia32_Cnst(right)) {
520 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
521 copy_ia32_Immop_attr(node, right);
526 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param env The transformation environment
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
539 ir_node *op1, ir_node *op2,
540 construct_binop_func *func) {
541 ir_node *new_node = NULL;
542 ir_graph *irg = env->irg;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_node *block = transform_node(env, get_nodes_block(node));
545 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
546 ir_node *nomem = new_NoMem();
547 ir_node *new_op1 = transform_node(env, op1);
548 ir_node *new_op2 = transform_node(env, op2);
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
551 if(func == new_rd_ia32_IMul) {
552 set_ia32_am_support(new_node, ia32_am_Source);
554 set_ia32_am_support(new_node, ia32_am_Full);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
558 if (is_op_commutative(get_irn_op(node))) {
559 set_ia32_commutative(new_node);
561 fold_immediate(env, new_node, 2, 3);
567 * Construct a standard binary operation, set AM and immediate if required.
569 * @param env The transformation environment
570 * @param op1 The first operand
571 * @param op2 The second operand
572 * @param func The node constructor function
573 * @return The constructed ia32 node.
575 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
576 ir_node *op1, ir_node *op2,
577 construct_binop_func *func)
579 ir_node *new_node = NULL;
580 dbg_info *dbgi = get_irn_dbg_info(node);
581 ir_graph *irg = env->irg;
582 ir_mode *mode = get_irn_mode(node);
583 ir_node *block = transform_node(env, get_nodes_block(node));
584 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
585 ir_node *nomem = new_NoMem();
586 ir_node *new_op1 = transform_node(env, op1);
587 ir_node *new_op2 = transform_node(env, op2);
589 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
590 set_ia32_am_support(new_node, ia32_am_Source);
591 if (is_op_commutative(get_irn_op(node))) {
592 set_ia32_commutative(new_node);
594 if (USE_SSE2(env->cg)) {
595 set_ia32_ls_mode(new_node, mode);
598 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
605 * Construct a shift/rotate binary operation, sets AM and immediate if required.
607 * @param env The transformation environment
608 * @param op1 The first operand
609 * @param op2 The second operand
610 * @param func The node constructor function
611 * @return The constructed ia32 node.
613 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
614 ir_node *op1, ir_node *op2,
615 construct_binop_func *func) {
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = env->irg;
619 ir_node *block = transform_node(env, get_nodes_block(node));
620 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
621 ir_node *nomem = new_NoMem();
624 ir_node *new_op1 = transform_node(env, op1);
625 ir_node *new_op2 = transform_node(env, op2);
628 assert(! mode_is_float(get_irn_mode(node))
629 && "Shift/Rotate with float not supported");
631 /* Check if immediate optimization is on and */
632 /* if it's an operation with immediate. */
633 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
634 expr_op = get_expr_op(new_op1, new_op2);
636 assert((expr_op || imm_op) && "invalid operands");
639 /* We have two consts here: not yet supported */
643 /* Limit imm_op within range imm8 */
645 tv = get_ia32_Immop_tarval(imm_op);
648 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
649 set_ia32_Immop_tarval(imm_op, tv);
656 /* integer operations */
658 /* This is shift/rot with const */
659 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
661 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
662 copy_ia32_Immop_attr(new_op, imm_op);
664 /* This is a normal shift/rot */
665 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
666 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
670 set_ia32_am_support(new_op, ia32_am_Dest);
672 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
674 set_ia32_emit_cl(new_op);
681 * Construct a standard unary operation, set AM and immediate if required.
683 * @param env The transformation environment
684 * @param op The operand
685 * @param func The node constructor function
686 * @return The constructed ia32 node.
688 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
689 construct_unop_func *func) {
690 ir_node *new_node = NULL;
691 ir_graph *irg = env->irg;
692 dbg_info *dbgi = get_irn_dbg_info(node);
693 ir_node *block = transform_node(env, get_nodes_block(node));
694 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
695 ir_node *nomem = new_NoMem();
696 ir_node *new_op = transform_node(env, op);
698 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
699 DB((dbg, LEVEL_1, "INT unop ..."));
700 set_ia32_am_support(new_node, ia32_am_Dest);
702 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
709 * Creates an ia32 Add.
711 * @param env The transformation environment
712 * @return the created ia32 Add node
714 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
715 ir_node *new_op = NULL;
716 ir_graph *irg = env->irg;
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_mode *mode = get_irn_mode(node);
719 ir_node *block = transform_node(env, get_nodes_block(node));
720 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
721 ir_node *nomem = new_NoMem();
722 ir_node *expr_op, *imm_op;
723 ir_node *op1 = get_Add_left(node);
724 ir_node *op2 = get_Add_right(node);
725 ir_node *new_op1 = transform_node(env, op1);
726 ir_node *new_op2 = transform_node(env, op2);
728 /* Check if immediate optimization is on and */
729 /* if it's an operation with immediate. */
730 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
731 expr_op = get_expr_op(new_op1, new_op2);
733 assert((expr_op || imm_op) && "invalid operands");
735 if (mode_is_float(mode)) {
737 if (USE_SSE2(env->cg))
738 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
740 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
745 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
746 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
748 /* No expr_op means, that we have two const - one symconst and */
749 /* one tarval or another symconst - because this case is not */
750 /* covered by constant folding */
751 /* We need to check for: */
752 /* 1) symconst + const -> becomes a LEA */
753 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
754 /* linker doesn't support two symconsts */
756 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
757 /* this is the 2nd case */
758 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
759 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
760 set_ia32_am_flavour(new_op, ia32_am_OB);
761 set_ia32_am_support(new_op, ia32_am_Source);
762 set_ia32_op_type(new_op, ia32_AddrModeS);
764 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 } else if (tp1 == ia32_ImmSymConst) {
766 tarval *tv = get_ia32_Immop_tarval(new_op2);
767 long offs = get_tarval_long(tv);
769 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
770 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
772 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
773 add_ia32_am_offs_int(new_op, offs);
774 set_ia32_am_flavour(new_op, ia32_am_O);
775 set_ia32_am_support(new_op, ia32_am_Source);
776 set_ia32_op_type(new_op, ia32_AddrModeS);
777 } else if (tp2 == ia32_ImmSymConst) {
778 tarval *tv = get_ia32_Immop_tarval(new_op1);
779 long offs = get_tarval_long(tv);
781 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
782 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
784 add_ia32_am_offs_int(new_op, offs);
785 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
786 set_ia32_am_flavour(new_op, ia32_am_O);
787 set_ia32_am_support(new_op, ia32_am_Source);
788 set_ia32_op_type(new_op, ia32_AddrModeS);
790 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
791 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
792 tarval *restv = tarval_add(tv1, tv2);
794 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
796 new_op = new_rd_ia32_Const(dbgi, irg, block);
797 set_ia32_Const_tarval(new_op, restv);
798 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
801 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
804 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
805 tarval_classification_t class_tv, class_negtv;
806 tarval *tv = get_ia32_Immop_tarval(imm_op);
808 /* optimize tarvals */
809 class_tv = classify_tarval(tv);
810 class_negtv = classify_tarval(tarval_neg(tv));
812 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
813 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
814 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
817 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
818 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
819 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
820 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
826 /* This is a normal add */
827 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
830 set_ia32_am_support(new_op, ia32_am_Full);
831 set_ia32_commutative(new_op);
833 fold_immediate(env, new_op, 2, 3);
835 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
841 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
842 ir_graph *irg = env->irg;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *block = transform_node(env, get_nodes_block(node));
845 ir_node *op1 = get_Mul_left(node);
846 ir_node *op2 = get_Mul_right(node);
847 ir_node *new_op1 = transform_node(env, op1);
848 ir_node *new_op2 = transform_node(env, op2);
849 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
850 ir_node *proj_EAX, *proj_EDX, *res;
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
854 set_ia32_commutative(res);
855 set_ia32_am_support(res, ia32_am_Source);
857 /* imediates are not supported, so no fold_immediate */
858 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
859 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
863 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
871 * Creates an ia32 Mul.
873 * @param env The transformation environment
874 * @return the created ia32 Mul node
876 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
877 ir_node *op1 = get_Mul_left(node);
878 ir_node *op2 = get_Mul_right(node);
879 ir_mode *mode = get_irn_mode(node);
881 if (mode_is_float(mode)) {
883 if (USE_SSE2(env->cg))
884 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
886 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
889 // for the lower 32bit of the result it doesn't matter whether we use
890 // signed or unsigned multiplication so we use IMul as it has fewer
892 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
896 * Creates an ia32 Mulh.
897 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
898 * this result while Mul returns the lower 32 bit.
900 * @param env The transformation environment
901 * @return the created ia32 Mulh node
903 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
904 ir_graph *irg = env->irg;
905 dbg_info *dbgi = get_irn_dbg_info(node);
906 ir_node *block = transform_node(env, get_nodes_block(node));
907 ir_node *op1 = get_irn_n(node, 0);
908 ir_node *op2 = get_irn_n(node, 1);
909 ir_node *new_op1 = transform_node(env, op1);
910 ir_node *new_op2 = transform_node(env, op2);
911 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
912 ir_node *proj_EAX, *proj_EDX, *res;
913 ir_mode *mode = get_irn_mode(node);
916 assert(!mode_is_float(mode) && "Mulh with float not supported");
917 if(mode_is_signed(mode)) {
918 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
920 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
923 set_ia32_commutative(res);
924 set_ia32_am_support(res, ia32_am_Source);
926 set_ia32_am_support(res, ia32_am_Source);
928 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
929 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
933 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
941 * Creates an ia32 And.
943 * @param env The transformation environment
944 * @return The created ia32 And node
946 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
947 ir_node *op1 = get_And_left(node);
948 ir_node *op2 = get_And_right(node);
950 assert (! mode_is_float(get_irn_mode(node)));
951 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
957 * Creates an ia32 Or.
959 * @param env The transformation environment
960 * @return The created ia32 Or node
962 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
963 ir_node *op1 = get_Or_left(node);
964 ir_node *op2 = get_Or_right(node);
966 assert (! mode_is_float(get_irn_mode(node)));
967 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
973 * Creates an ia32 Eor.
975 * @param env The transformation environment
976 * @return The created ia32 Eor node
978 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
979 ir_node *op1 = get_Eor_left(node);
980 ir_node *op2 = get_Eor_right(node);
982 assert(! mode_is_float(get_irn_mode(node)));
983 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
989 * Creates an ia32 Max.
991 * @param env The transformation environment
992 * @return the created ia32 Max node
994 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
995 ir_graph *irg = env->irg;
997 ir_mode *mode = get_irn_mode(node);
998 dbg_info *dbgi = get_irn_dbg_info(node);
999 ir_node *block = transform_node(env, get_nodes_block(node));
1000 ir_node *op1 = get_irn_n(node, 0);
1001 ir_node *op2 = get_irn_n(node, 1);
1002 ir_node *new_op1 = transform_node(env, op1);
1003 ir_node *new_op2 = transform_node(env, op2);
1004 ir_mode *op_mode = get_irn_mode(op1);
1006 assert(get_mode_size_bits(mode) == 32);
1008 if (mode_is_float(mode)) {
1010 if (USE_SSE2(env->cg)) {
1011 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1013 panic("Can't create Max node");
1016 long pnc = pn_Cmp_Gt;
1017 if(!mode_is_signed(op_mode)) {
1018 pnc |= ia32_pn_Cmp_Unsigned;
1020 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1021 set_ia32_pncode(new_op, pnc);
1022 set_ia32_am_support(new_op, ia32_am_None);
1024 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1030 * Creates an ia32 Min.
1032 * @param env The transformation environment
1033 * @return the created ia32 Min node
1035 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1036 ir_graph *irg = env->irg;
1038 ir_mode *mode = get_irn_mode(node);
1039 dbg_info *dbgi = get_irn_dbg_info(node);
1040 ir_node *block = transform_node(env, get_nodes_block(node));
1041 ir_node *op1 = get_irn_n(node, 0);
1042 ir_node *op2 = get_irn_n(node, 1);
1043 ir_node *new_op1 = transform_node(env, op1);
1044 ir_node *new_op2 = transform_node(env, op2);
1045 ir_mode *op_mode = get_irn_mode(op1);
1047 assert(get_mode_size_bits(mode) == 32);
1049 if (mode_is_float(mode)) {
1051 if (USE_SSE2(env->cg)) {
1052 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1054 panic("can't create Min node");
1057 long pnc = pn_Cmp_Lt;
1058 if(!mode_is_signed(op_mode)) {
1059 pnc |= ia32_pn_Cmp_Unsigned;
1061 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1062 set_ia32_pncode(new_op, pnc);
1063 set_ia32_am_support(new_op, ia32_am_None);
1065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1072 * Creates an ia32 Sub.
1074 * @param env The transformation environment
1075 * @return The created ia32 Sub node
1077 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1078 ir_node *new_op = NULL;
1079 ir_graph *irg = env->irg;
1080 dbg_info *dbgi = get_irn_dbg_info(node);
1081 ir_mode *mode = get_irn_mode(node);
1082 ir_node *block = transform_node(env, get_nodes_block(node));
1083 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1084 ir_node *nomem = new_NoMem();
1085 ir_node *op1 = get_Sub_left(node);
1086 ir_node *op2 = get_Sub_right(node);
1087 ir_node *new_op1 = transform_node(env, op1);
1088 ir_node *new_op2 = transform_node(env, op2);
1089 ir_node *expr_op, *imm_op;
1091 /* Check if immediate optimization is on and */
1092 /* if it's an operation with immediate. */
1093 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1094 expr_op = get_expr_op(new_op1, new_op2);
1096 assert((expr_op || imm_op) && "invalid operands");
1098 if (mode_is_float(mode)) {
1100 if (USE_SSE2(env->cg))
1101 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1103 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1108 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1109 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1111 /* No expr_op means, that we have two const - one symconst and */
1112 /* one tarval or another symconst - because this case is not */
1113 /* covered by constant folding */
1114 /* We need to check for: */
1115 /* 1) symconst - const -> becomes a LEA */
1116 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1117 /* linker doesn't support two symconsts */
1118 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1119 /* this is the 2nd case */
1120 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1121 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1122 set_ia32_am_sc_sign(new_op);
1123 set_ia32_am_flavour(new_op, ia32_am_OB);
1125 DBG_OPT_LEA3(op1, op2, node, new_op);
1126 } else if (tp1 == ia32_ImmSymConst) {
1127 tarval *tv = get_ia32_Immop_tarval(new_op2);
1128 long offs = get_tarval_long(tv);
1130 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1131 DBG_OPT_LEA3(op1, op2, node, new_op);
1133 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1134 add_ia32_am_offs_int(new_op, -offs);
1135 set_ia32_am_flavour(new_op, ia32_am_O);
1136 set_ia32_am_support(new_op, ia32_am_Source);
1137 set_ia32_op_type(new_op, ia32_AddrModeS);
1138 } else if (tp2 == ia32_ImmSymConst) {
1139 tarval *tv = get_ia32_Immop_tarval(new_op1);
1140 long offs = get_tarval_long(tv);
1142 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1143 DBG_OPT_LEA3(op1, op2, node, new_op);
1145 add_ia32_am_offs_int(new_op, offs);
1146 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1147 set_ia32_am_sc_sign(new_op);
1148 set_ia32_am_flavour(new_op, ia32_am_O);
1149 set_ia32_am_support(new_op, ia32_am_Source);
1150 set_ia32_op_type(new_op, ia32_AddrModeS);
1152 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1153 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1154 tarval *restv = tarval_sub(tv1, tv2);
1156 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1158 new_op = new_rd_ia32_Const(dbgi, irg, block);
1159 set_ia32_Const_tarval(new_op, restv);
1160 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1163 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1165 } else if (imm_op) {
1166 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1167 tarval_classification_t class_tv, class_negtv;
1168 tarval *tv = get_ia32_Immop_tarval(imm_op);
1170 /* optimize tarvals */
1171 class_tv = classify_tarval(tv);
1172 class_negtv = classify_tarval(tarval_neg(tv));
1174 if (class_tv == TV_CLASSIFY_ONE) {
1175 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1176 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1179 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1180 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1181 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1188 /* This is a normal sub */
1189 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1191 /* set AM support */
1192 set_ia32_am_support(new_op, ia32_am_Full);
1194 fold_immediate(env, new_op, 2, 3);
1196 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1204 * Generates an ia32 DivMod with additional infrastructure for the
1205 * register allocator if needed.
1207 * @param env The transformation environment
1208 * @param dividend -no comment- :)
1209 * @param divisor -no comment- :)
1210 * @param dm_flav flavour_Div/Mod/DivMod
1211 * @return The created ia32 DivMod node
1213 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1214 ir_node *dividend, ir_node *divisor,
1215 ia32_op_flavour_t dm_flav) {
1216 ir_graph *irg = env->irg;
1217 dbg_info *dbgi = get_irn_dbg_info(node);
1218 ir_mode *mode = get_irn_mode(node);
1219 ir_node *block = transform_node(env, get_nodes_block(node));
1220 ir_node *res, *proj_div, *proj_mod;
1221 ir_node *edx_node, *cltd;
1222 ir_node *in_keep[1];
1223 ir_node *mem, *new_mem;
1224 ir_node *projs[pn_DivMod_max];
1225 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1226 ir_node *new_dividend = transform_node(env, dividend);
1227 ir_node *new_divisor = transform_node(env, divisor);
1229 ia32_collect_Projs(node, projs, pn_DivMod_max);
1233 mem = get_Div_mem(node);
1234 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1237 mem = get_Mod_mem(node);
1238 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1240 case flavour_DivMod:
1241 mem = get_DivMod_mem(node);
1242 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1243 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1244 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1247 panic("invalid divmod flavour!");
1249 new_mem = transform_node(env, mem);
1251 if (mode_is_signed(mode)) {
1252 /* in signed mode, we need to sign extend the dividend */
1253 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1254 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1255 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1257 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1258 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1259 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1262 if(mode_is_signed(mode)) {
1263 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1265 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1268 /* Matze: code can't handle this at the moment... */
1270 /* set AM support */
1271 set_ia32_am_support(res, ia32_am_Source);
1274 set_ia32_n_res(res, 2);
1276 /* Only one proj is used -> We must add a second proj and */
1277 /* connect this one to a Keep node to eat up the second */
1278 /* destroyed register. */
1279 /* We also renumber the Firm projs into ia32 projs. */
1281 switch (get_irn_opcode(node)) {
1283 /* add Proj-Keep for mod res */
1284 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1285 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1288 /* add Proj-Keep for div res */
1289 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1290 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1293 /* check, which Proj-Keep, we need to add */
1294 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1295 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1297 if (proj_div && proj_mod) {
1298 /* nothing to be done */
1300 else if (! proj_div && ! proj_mod) {
1301 assert(0 && "Missing DivMod result proj");
1303 else if (! proj_div) {
1304 /* We have only mod result: add div res Proj-Keep */
1305 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1306 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1309 /* We have only div result: add mod res Proj-Keep */
1310 in_keep[0] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1311 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1315 assert(0 && "Div, Mod, or DivMod expected.");
1319 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1326 * Wrapper for generate_DivMod. Sets flavour_Mod.
1328 * @param env The transformation environment
1330 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1331 return generate_DivMod(env, node, get_Mod_left(node),
1332 get_Mod_right(node), flavour_Mod);
1336 * Wrapper for generate_DivMod. Sets flavour_Div.
1338 * @param env The transformation environment
1340 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1341 return generate_DivMod(env, node, get_Div_left(node),
1342 get_Div_right(node), flavour_Div);
1346 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1348 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1349 return generate_DivMod(env, node, get_DivMod_left(node),
1350 get_DivMod_right(node), flavour_DivMod);
1356 * Creates an ia32 floating Div.
1358 * @param env The transformation environment
1359 * @return The created ia32 xDiv node
1361 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1362 ir_graph *irg = env->irg;
1363 dbg_info *dbgi = get_irn_dbg_info(node);
1364 ir_node *block = transform_node(env, get_nodes_block(node));
1365 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1367 ir_node *nomem = new_rd_NoMem(env->irg);
1368 ir_node *op1 = get_Quot_left(node);
1369 ir_node *op2 = get_Quot_right(node);
1370 ir_node *new_op1 = transform_node(env, op1);
1371 ir_node *new_op2 = transform_node(env, op2);
1374 if (USE_SSE2(env->cg)) {
1375 ir_mode *mode = get_irn_mode(op1);
1376 if (is_ia32_xConst(new_op2)) {
1377 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1378 set_ia32_am_support(new_op, ia32_am_None);
1379 copy_ia32_Immop_attr(new_op, new_op2);
1381 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1382 // Matze: disabled for now, spillslot coalescer fails
1383 //set_ia32_am_support(new_op, ia32_am_Source);
1385 set_ia32_ls_mode(new_op, mode);
1387 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1388 // Matze: disabled for now (spillslot coalescer fails)
1389 //set_ia32_am_support(new_op, ia32_am_Source);
1391 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1397 * Creates an ia32 Shl.
1399 * @param env The transformation environment
1400 * @return The created ia32 Shl node
1402 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1403 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1410 * Creates an ia32 Shr.
1412 * @param env The transformation environment
1413 * @return The created ia32 Shr node
1415 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1416 return gen_shift_binop(env, node, get_Shr_left(node),
1417 get_Shr_right(node), new_rd_ia32_Shr);
1423 * Creates an ia32 Sar.
1425 * @param env The transformation environment
1426 * @return The created ia32 Shrs node
1428 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1429 return gen_shift_binop(env, node, get_Shrs_left(node),
1430 get_Shrs_right(node), new_rd_ia32_Sar);
1436 * Creates an ia32 RotL.
1438 * @param env The transformation environment
1439 * @param op1 The first operator
1440 * @param op2 The second operator
1441 * @return The created ia32 RotL node
1443 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1444 ir_node *op1, ir_node *op2) {
1445 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1451 * Creates an ia32 RotR.
1452 * NOTE: There is no RotR with immediate because this would always be a RotL
1453 * "imm-mode_size_bits" which can be pre-calculated.
1455 * @param env The transformation environment
1456 * @param op1 The first operator
1457 * @param op2 The second operator
1458 * @return The created ia32 RotR node
1460 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1462 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1468 * Creates an ia32 RotR or RotL (depending on the found pattern).
1470 * @param env The transformation environment
1471 * @return The created ia32 RotL or RotR node
1473 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1474 ir_node *rotate = NULL;
1475 ir_node *op1 = get_Rot_left(node);
1476 ir_node *op2 = get_Rot_right(node);
1478 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1479 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1480 that means we can create a RotR instead of an Add and a RotL */
1482 if (get_irn_op(op2) == op_Add) {
1484 ir_node *left = get_Add_left(add);
1485 ir_node *right = get_Add_right(add);
1486 if (is_Const(right)) {
1487 tarval *tv = get_Const_tarval(right);
1488 ir_mode *mode = get_irn_mode(node);
1489 long bits = get_mode_size_bits(mode);
1491 if (get_irn_op(left) == op_Minus &&
1492 tarval_is_long(tv) &&
1493 get_tarval_long(tv) == bits)
1495 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1496 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1501 if (rotate == NULL) {
1502 rotate = gen_RotL(env, node, op1, op2);
1511 * Transforms a Minus node.
1513 * @param env The transformation environment
1514 * @param op The Minus operand
1515 * @return The created ia32 Minus node
1517 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1520 ir_graph *irg = env->irg;
1521 dbg_info *dbgi = get_irn_dbg_info(node);
1522 ir_node *block = transform_node(env, get_nodes_block(node));
1523 ir_mode *mode = get_irn_mode(node);
1526 if (mode_is_float(mode)) {
1527 ir_node *new_op = transform_node(env, op);
1529 if (USE_SSE2(env->cg)) {
1530 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1531 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1532 ir_node *nomem = new_rd_NoMem(irg);
1534 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1536 size = get_mode_size_bits(mode);
1537 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1539 set_ia32_am_sc(res, ent);
1540 set_ia32_op_type(res, ia32_AddrModeS);
1541 set_ia32_ls_mode(res, mode);
1543 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1546 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1549 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1555 * Transforms a Minus node.
1557 * @param env The transformation environment
1558 * @return The created ia32 Minus node
1560 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1561 return gen_Minus_ex(env, node, get_Minus_op(node));
1566 * Transforms a Not node.
1568 * @param env The transformation environment
1569 * @return The created ia32 Not node
1571 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1572 ir_node *op = get_Not_op(node);
1574 assert (! mode_is_float(get_irn_mode(node)));
1575 return gen_unop(env, node, op, new_rd_ia32_Not);
1581 * Transforms an Abs node.
1583 * @param env The transformation environment
1584 * @return The created ia32 Abs node
1586 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1587 ir_node *res, *p_eax, *p_edx;
1588 ir_graph *irg = env->irg;
1589 dbg_info *dbgi = get_irn_dbg_info(node);
1590 ir_node *block = transform_node(env, get_nodes_block(node));
1591 ir_mode *mode = get_irn_mode(node);
1592 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1593 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1594 ir_node *nomem = new_NoMem();
1595 ir_node *op = get_Abs_op(node);
1596 ir_node *new_op = transform_node(env, op);
1600 if (mode_is_float(mode)) {
1602 if (USE_SSE2(env->cg)) {
1603 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1605 size = get_mode_size_bits(mode);
1606 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1608 set_ia32_am_sc(res, ent);
1610 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1612 set_ia32_op_type(res, ia32_AddrModeS);
1613 set_ia32_ls_mode(res, mode);
1616 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1617 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1621 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1622 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1624 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1625 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1627 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1628 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1630 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1631 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1640 * Transforms a Load.
1642 * @param env The transformation environment
1643 * @return the created ia32 Load node
1645 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1646 ir_graph *irg = env->irg;
1647 dbg_info *dbgi = get_irn_dbg_info(node);
1648 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1649 ir_mode *mode = get_Load_mode(node);
1650 ir_node *block = transform_node(env, get_nodes_block(node));
1651 ir_node *ptr = get_Load_ptr(node);
1652 ir_node *new_ptr = transform_node(env, ptr);
1653 ir_node *lptr = new_ptr;
1654 ir_node *mem = get_Load_mem(node);
1655 ir_node *new_mem = transform_node(env, mem);
1658 ia32_am_flavour_t am_flav = ia32_am_B;
1659 ir_node *projs[pn_Load_max];
1661 ia32_collect_Projs(node, projs, pn_Load_max);
1664 check for special case: the loaded value might not be used (optimized, volatile, ...)
1665 we add a Proj + Keep for volatile loads and ignore all other cases
1667 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1668 /* add a result proj and a Keep to produce a pseudo use */
1669 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1670 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1673 /* address might be a constant (symconst or absolute address) */
1674 if (is_ia32_Const(new_ptr)) {
1679 if (mode_is_float(mode)) {
1681 if (USE_SSE2(env->cg)) {
1682 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1684 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1687 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1690 /* base is a constant address */
1692 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1693 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1694 am_flav = ia32_am_N;
1696 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1697 long offs = get_tarval_long(tv);
1699 add_ia32_am_offs_int(new_op, offs);
1700 am_flav = ia32_am_O;
1704 set_ia32_am_support(new_op, ia32_am_Source);
1705 set_ia32_op_type(new_op, ia32_AddrModeS);
1706 set_ia32_am_flavour(new_op, am_flav);
1707 set_ia32_ls_mode(new_op, mode);
1709 /* make sure we are scheduled behind the intial IncSP/Barrier
1710 * to avoid spills being placed before it
1712 if(block == get_irg_start_block(irg)) {
1713 add_irn_dep(new_op, get_irg_frame(irg));
1716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1724 * Transforms a Store.
1726 * @param env The transformation environment
1727 * @return the created ia32 Store node
1729 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1730 ir_graph *irg = env->irg;
1731 dbg_info *dbgi = get_irn_dbg_info(node);
1732 ir_node *block = transform_node(env, get_nodes_block(node));
1733 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1734 ir_node *ptr = get_Store_ptr(node);
1735 ir_node *new_ptr = transform_node(env, ptr);
1736 ir_node *sptr = new_ptr;
1737 ir_node *val = get_Store_value(node);
1738 ir_node *new_val = transform_node(env, val);
1739 ir_node *mem = get_Store_mem(node);
1740 ir_node *new_mem = transform_node(env, mem);
1741 ir_mode *mode = get_irn_mode(val);
1742 ir_node *sval = new_val;
1745 ia32_am_flavour_t am_flav = ia32_am_B;
1747 if (is_ia32_Const(new_val)) {
1748 assert(!mode_is_float(mode));
1752 /* address might be a constant (symconst or absolute address) */
1753 if (is_ia32_Const(new_ptr)) {
1758 if (mode_is_float(mode)) {
1760 if (USE_SSE2(env->cg)) {
1761 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1763 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1765 } else if (get_mode_size_bits(mode) == 8) {
1766 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1768 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1771 /* stored const is an immediate value */
1772 if (is_ia32_Const(new_val)) {
1773 assert(!mode_is_float(mode));
1774 copy_ia32_Immop_attr(new_op, new_val);
1777 /* base is an constant address */
1779 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1780 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1781 am_flav = ia32_am_N;
1783 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1784 long offs = get_tarval_long(tv);
1786 add_ia32_am_offs_int(new_op, offs);
1787 am_flav = ia32_am_O;
1791 set_ia32_am_support(new_op, ia32_am_Dest);
1792 set_ia32_op_type(new_op, ia32_AddrModeD);
1793 set_ia32_am_flavour(new_op, am_flav);
1794 set_ia32_ls_mode(new_op, mode);
1796 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1804 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1806 * @param env The transformation environment
1807 * @return The transformed node.
1809 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1810 ir_graph *irg = env->irg;
1811 dbg_info *dbgi = get_irn_dbg_info(node);
1812 ir_node *block = transform_node(env, get_nodes_block(node));
1813 ir_node *sel = get_Cond_selector(node);
1814 ir_mode *sel_mode = get_irn_mode(sel);
1815 ir_node *res = NULL;
1816 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1817 ir_node *cnst, *expr;
1819 if (is_Proj(sel) && sel_mode == mode_b) {
1820 ir_node *nomem = new_NoMem();
1821 ir_node *pred = get_Proj_pred(sel);
1822 ir_node *cmp_a = get_Cmp_left(pred);
1823 ir_node *new_cmp_a = transform_node(env, cmp_a);
1824 ir_node *cmp_b = get_Cmp_right(pred);
1825 ir_node *new_cmp_b = transform_node(env, cmp_b);
1826 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1828 int pnc = get_Proj_proj(sel);
1829 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1830 pnc |= ia32_pn_Cmp_Unsigned;
1833 /* check if we can use a CondJmp with immediate */
1834 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1835 expr = get_expr_op(new_cmp_a, new_cmp_b);
1837 if (cnst != NULL && expr != NULL) {
1838 /* immop has to be the right operand, we might need to flip pnc */
1839 if(cnst != new_cmp_b) {
1840 pnc = get_inversed_pnc(pnc);
1843 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1844 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1845 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1847 /* a Cmp A =/!= 0 */
1848 ir_node *op1 = expr;
1849 ir_node *op2 = expr;
1852 /* check, if expr is an only once used And operation */
1853 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1854 op1 = get_irn_n(expr, 2);
1855 op2 = get_irn_n(expr, 3);
1857 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1859 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1860 set_ia32_pncode(res, pnc);
1863 copy_ia32_Immop_attr(res, expr);
1866 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1871 if (mode_is_float(cmp_mode)) {
1873 if (USE_SSE2(env->cg)) {
1874 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1875 set_ia32_ls_mode(res, cmp_mode);
1881 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1883 copy_ia32_Immop_attr(res, cnst);
1886 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1888 if (mode_is_float(cmp_mode)) {
1890 if (USE_SSE2(env->cg)) {
1891 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1892 set_ia32_ls_mode(res, cmp_mode);
1895 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1896 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1897 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1901 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1902 set_ia32_commutative(res);
1906 set_ia32_pncode(res, pnc);
1907 // Matze: disabled for now, because the default collect_spills_walker
1908 // is not able to detect the mode of the spilled value
1909 // moreover, the lea optimize phase freely exchanges left/right
1910 // without updating the pnc
1911 //set_ia32_am_support(res, ia32_am_Source);
1914 /* determine the smallest switch case value */
1915 int switch_min = INT_MAX;
1916 const ir_edge_t *edge;
1917 ir_node *new_sel = transform_node(env, sel);
1919 foreach_out_edge(node, edge) {
1920 int pn = get_Proj_proj(get_edge_src_irn(edge));
1921 switch_min = pn < switch_min ? pn : switch_min;
1925 /* if smallest switch case is not 0 we need an additional sub */
1926 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1927 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1928 add_ia32_am_offs_int(res, -switch_min);
1929 set_ia32_am_flavour(res, ia32_am_OB);
1930 set_ia32_am_support(res, ia32_am_Source);
1931 set_ia32_op_type(res, ia32_AddrModeS);
1934 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1935 set_ia32_pncode(res, get_Cond_defaultProj(node));
1938 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1945 * Transforms a CopyB node.
1947 * @param env The transformation environment
1948 * @return The transformed node.
1950 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1951 ir_node *res = NULL;
1952 ir_graph *irg = env->irg;
1953 dbg_info *dbgi = get_irn_dbg_info(node);
1954 ir_node *block = transform_node(env, get_nodes_block(node));
1955 ir_node *src = get_CopyB_src(node);
1956 ir_node *new_src = transform_node(env, src);
1957 ir_node *dst = get_CopyB_dst(node);
1958 ir_node *new_dst = transform_node(env, dst);
1959 ir_node *mem = get_CopyB_mem(node);
1960 ir_node *new_mem = transform_node(env, mem);
1961 int size = get_type_size_bytes(get_CopyB_type(node));
1962 ir_mode *dst_mode = get_irn_mode(dst);
1963 ir_mode *src_mode = get_irn_mode(src);
1967 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1968 /* then we need the size explicitly in ECX. */
1969 if (size >= 32 * 4) {
1970 rem = size & 0x3; /* size % 4 */
1973 res = new_rd_ia32_Const(dbgi, irg, block);
1974 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1975 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1977 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1978 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1980 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1981 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1982 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1983 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1984 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1987 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1988 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1990 /* ok: now attach Proj's because movsd will destroy esi and edi */
1991 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1992 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1993 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1996 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2004 * Transforms a Mux node into CMov.
2006 * @param env The transformation environment
2007 * @return The transformed node.
2009 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
2010 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
2011 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2013 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2019 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2020 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2021 ir_node *psi_default);
2024 * Transforms a Psi node into CMov.
2026 * @param env The transformation environment
2027 * @return The transformed node.
2029 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2030 ia32_code_gen_t *cg = env->cg;
2031 ir_graph *irg = env->irg;
2032 dbg_info *dbgi = get_irn_dbg_info(node);
2033 ir_mode *mode = get_irn_mode(node);
2034 ir_node *block = transform_node(env, get_nodes_block(node));
2035 ir_node *cmp_proj = get_Mux_sel(node);
2036 ir_node *psi_true = get_Psi_val(node, 0);
2037 ir_node *psi_default = get_Psi_default(node);
2038 ir_node *new_psi_true = transform_node(env, psi_true);
2039 ir_node *new_psi_default = transform_node(env, psi_default);
2040 ir_node *noreg = ia32_new_NoReg_gp(cg);
2041 ir_node *nomem = new_rd_NoMem(irg);
2042 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2043 ir_node *new_cmp_a, *new_cmp_b;
2047 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2049 cmp = get_Proj_pred(cmp_proj);
2050 cmp_a = get_Cmp_left(cmp);
2051 cmp_b = get_Cmp_right(cmp);
2052 cmp_mode = get_irn_mode(cmp_a);
2053 new_cmp_a = transform_node(env, cmp_a);
2054 new_cmp_b = transform_node(env, cmp_b);
2056 pnc = get_Proj_proj(cmp_proj);
2057 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2058 pnc |= ia32_pn_Cmp_Unsigned;
2061 if (mode_is_float(mode)) {
2062 /* floating point psi */
2065 /* 1st case: compare operands are float too */
2067 /* psi(cmp(a, b), t, f) can be done as: */
2068 /* tmp = cmp a, b */
2069 /* tmp2 = t and tmp */
2070 /* tmp3 = f and not tmp */
2071 /* res = tmp2 or tmp3 */
2073 /* in case the compare operands are int, we move them into xmm register */
2074 if (! mode_is_float(get_irn_mode(cmp_a))) {
2075 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2076 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2078 pnc |= 8; /* transform integer compare to fp compare */
2081 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2082 set_ia32_pncode(new_op, pnc);
2083 set_ia32_am_support(new_op, ia32_am_Source);
2084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2086 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2087 set_ia32_am_support(and1, ia32_am_None);
2088 set_ia32_commutative(and1);
2089 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2091 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2092 set_ia32_am_support(and2, ia32_am_None);
2093 set_ia32_commutative(and2);
2094 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2096 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2097 set_ia32_am_support(new_op, ia32_am_None);
2098 set_ia32_commutative(new_op);
2099 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2103 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2104 set_ia32_pncode(new_op, pnc);
2105 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2110 construct_binop_func *set_func = NULL;
2111 cmov_func_t *cmov_func = NULL;
2113 if (mode_is_float(get_irn_mode(cmp_a))) {
2114 /* 1st case: compare operands are floats */
2119 set_func = new_rd_ia32_xCmpSet;
2120 cmov_func = new_rd_ia32_xCmpCMov;
2124 set_func = new_rd_ia32_vfCmpSet;
2125 cmov_func = new_rd_ia32_vfCmpCMov;
2128 pnc &= ~0x8; /* fp compare -> int compare */
2131 /* 2nd case: compare operand are integer too */
2132 set_func = new_rd_ia32_CmpSet;
2133 cmov_func = new_rd_ia32_CmpCMov;
2136 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2137 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2138 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2139 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2140 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2141 set_ia32_pncode(new_op, pnc);
2143 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2144 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2145 /* we invert condition and set default to 0 */
2146 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2147 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2150 /* otherwise: use CMOVcc */
2151 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2152 set_ia32_pncode(new_op, pnc);
2155 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2158 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2159 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2160 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2161 set_ia32_pncode(new_op, pnc);
2162 set_ia32_am_support(new_op, ia32_am_Source);
2164 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2165 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2166 /* we invert condition and set default to 0 */
2167 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2168 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2169 set_ia32_am_support(new_op, ia32_am_Source);
2172 /* otherwise: use CMOVcc */
2173 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2174 set_ia32_pncode(new_op, pnc);
2175 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2185 * Following conversion rules apply:
2189 * 1) n bit -> m bit n > m (downscale)
2191 * 2) n bit -> m bit n == m (sign change)
2193 * 3) n bit -> m bit n < m (upscale)
2194 * a) source is signed: movsx
2195 * b) source is unsigned: and with lower bits sets
2199 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2203 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2207 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2208 * x87 is mode_E internally, conversions happen only at load and store
2209 * in non-strict semantic
2213 * Create a conversion from x87 state register to general purpose.
2215 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2216 ia32_code_gen_t *cg = env->cg;
2217 ir_graph *irg = env->irg;
2218 dbg_info *dbgi = get_irn_dbg_info(node);
2219 ir_node *block = transform_node(env, get_nodes_block(node));
2220 ir_node *noreg = ia32_new_NoReg_gp(cg);
2221 ir_node *op = get_Conv_op(node);
2222 ir_node *new_op = transform_node(env, op);
2223 ir_node *fist, *load;
2224 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2227 fist = new_rd_ia32_vfist(dbgi, irg, block,
2228 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2230 set_ia32_use_frame(fist);
2231 set_ia32_am_support(fist, ia32_am_Dest);
2232 set_ia32_op_type(fist, ia32_AddrModeD);
2233 set_ia32_am_flavour(fist, ia32_am_B);
2234 set_ia32_ls_mode(fist, mode_Iu);
2235 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2238 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2240 set_ia32_use_frame(load);
2241 set_ia32_am_support(load, ia32_am_Source);
2242 set_ia32_op_type(load, ia32_AddrModeS);
2243 set_ia32_am_flavour(load, ia32_am_B);
2244 set_ia32_ls_mode(load, mode_Iu);
2245 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2247 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2251 * Create a conversion from general purpose to x87 register
2253 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2255 ia32_code_gen_t *cg = env->cg;
2257 ir_graph *irg = env->irg;
2258 dbg_info *dbgi = get_irn_dbg_info(node);
2259 ir_node *block = transform_node(env, get_nodes_block(node));
2260 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2261 ir_node *nomem = new_NoMem();
2262 ir_node *op = get_Conv_op(node);
2263 ir_node *new_op = transform_node(env, op);
2264 ir_node *fild, *store;
2267 /* first convert to 32 bit if necessary */
2268 src_bits = get_mode_size_bits(src_mode);
2269 if (src_bits == 8) {
2270 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2271 set_ia32_am_support(new_op, ia32_am_Source);
2272 set_ia32_ls_mode(new_op, src_mode);
2273 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2274 } else if (src_bits < 32) {
2275 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2276 set_ia32_am_support(new_op, ia32_am_Source);
2277 set_ia32_ls_mode(new_op, src_mode);
2278 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2282 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2284 set_ia32_use_frame(store);
2285 set_ia32_am_support(store, ia32_am_Dest);
2286 set_ia32_op_type(store, ia32_AddrModeD);
2287 set_ia32_am_flavour(store, ia32_am_OB);
2288 set_ia32_ls_mode(store, mode_Iu);
2291 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2293 set_ia32_use_frame(fild);
2294 set_ia32_am_support(fild, ia32_am_Source);
2295 set_ia32_op_type(fild, ia32_AddrModeS);
2296 set_ia32_am_flavour(fild, ia32_am_OB);
2297 set_ia32_ls_mode(fild, mode_Iu);
2299 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2303 * Transforms a Conv node.
2305 * @param env The transformation environment
2306 * @return The created ia32 Conv node
2308 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2309 ir_graph *irg = env->irg;
2310 dbg_info *dbgi = get_irn_dbg_info(node);
2311 ir_node *op = get_Conv_op(node);
2312 ir_mode *src_mode = get_irn_mode(op);
2313 ir_mode *tgt_mode = get_irn_mode(node);
2314 int src_bits = get_mode_size_bits(src_mode);
2315 int tgt_bits = get_mode_size_bits(tgt_mode);
2316 ir_node *block = transform_node(env, get_nodes_block(node));
2318 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2319 ir_node *nomem = new_rd_NoMem(irg);
2320 ir_node *new_op = transform_node(env, op);
2322 if (src_mode == tgt_mode) {
2323 if (get_Conv_strict(node)) {
2324 if (USE_SSE2(env->cg)) {
2325 /* when we are in SSE mode, we can kill all strict no-op conversion */
2329 /* this should be optimized already, but who knows... */
2330 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2331 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2336 if (mode_is_float(src_mode)) {
2337 /* we convert from float ... */
2338 if (mode_is_float(tgt_mode)) {
2340 if (USE_SSE2(env->cg)) {
2341 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2342 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2343 set_ia32_ls_mode(res, tgt_mode);
2345 // Matze: TODO what about strict convs?
2346 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2347 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2352 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2353 if (USE_SSE2(env->cg)) {
2354 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2355 set_ia32_ls_mode(res, src_mode);
2357 return gen_x87_fp_to_gp(env, node);
2361 /* we convert from int ... */
2362 if (mode_is_float(tgt_mode)) {
2365 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2366 if (USE_SSE2(env->cg)) {
2367 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2368 set_ia32_ls_mode(res, tgt_mode);
2369 if(src_bits == 32) {
2370 set_ia32_am_support(res, ia32_am_Source);
2373 return gen_x87_gp_to_fp(env, node, src_mode);
2377 ir_mode *smaller_mode;
2380 if (src_bits == tgt_bits) {
2381 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2385 if(src_bits < tgt_bits) {
2386 smaller_mode = src_mode;
2387 smaller_bits = src_bits;
2389 smaller_mode = tgt_mode;
2390 smaller_bits = tgt_bits;
2393 // The following is not correct, we can't change the mode,
2394 // maybe others are using the load too
2395 // better move this to a separate phase!
2398 if(is_Proj(new_op)) {
2399 /* load operations do already sign/zero extend, so we have
2400 * nothing left to do */
2401 ir_node *pred = get_Proj_pred(new_op);
2402 if(is_ia32_Load(pred)) {
2403 set_ia32_ls_mode(pred, smaller_mode);
2409 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2410 if (smaller_bits == 8) {
2411 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2412 set_ia32_ls_mode(res, smaller_mode);
2414 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2415 set_ia32_ls_mode(res, smaller_mode);
2417 set_ia32_am_support(res, ia32_am_Source);
2421 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2428 /********************************************
2431 * | |__ ___ _ __ ___ __| | ___ ___
2432 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2433 * | |_) | __/ | | | (_) | (_| | __/\__ \
2434 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2436 ********************************************/
2438 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2439 ir_node *new_op = NULL;
2440 ir_graph *irg = env->irg;
2441 dbg_info *dbgi = get_irn_dbg_info(node);
2442 ir_node *block = transform_node(env, get_nodes_block(node));
2443 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2444 ir_node *nomem = new_rd_NoMem(env->irg);
2445 ir_node *ptr = get_irn_n(node, 0);
2446 ir_node *new_ptr = transform_node(env, ptr);
2447 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2448 ir_mode *load_mode = get_irn_mode(node);
2452 if (mode_is_float(load_mode)) {
2454 if (USE_SSE2(env->cg)) {
2455 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2456 pn_res = pn_ia32_xLoad_res;
2457 proj_mode = mode_xmm;
2459 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2460 pn_res = pn_ia32_vfld_res;
2461 proj_mode = mode_vfp;
2464 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2465 proj_mode = mode_Iu;
2466 pn_res = pn_ia32_Load_res;
2469 set_ia32_frame_ent(new_op, ent);
2470 set_ia32_use_frame(new_op);
2472 set_ia32_am_support(new_op, ia32_am_Source);
2473 set_ia32_op_type(new_op, ia32_AddrModeS);
2474 set_ia32_am_flavour(new_op, ia32_am_B);
2475 set_ia32_ls_mode(new_op, load_mode);
2476 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2478 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2480 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2484 * Transforms a FrameAddr into an ia32 Add.
2486 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2487 ir_graph *irg = env->irg;
2488 dbg_info *dbgi = get_irn_dbg_info(node);
2489 ir_node *block = transform_node(env, get_nodes_block(node));
2490 ir_node *op = get_irn_n(node, 0);
2491 ir_node *new_op = transform_node(env, op);
2493 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2495 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2496 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2497 set_ia32_am_support(res, ia32_am_Full);
2498 set_ia32_use_frame(res);
2499 set_ia32_am_flavour(res, ia32_am_OB);
2501 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2507 * Transforms a FrameLoad into an ia32 Load.
2509 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2510 ir_node *new_op = NULL;
2511 ir_graph *irg = env->irg;
2512 dbg_info *dbgi = get_irn_dbg_info(node);
2513 ir_node *block = transform_node(env, get_nodes_block(node));
2514 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2515 ir_node *mem = get_irn_n(node, 0);
2516 ir_node *ptr = get_irn_n(node, 1);
2517 ir_node *new_mem = transform_node(env, mem);
2518 ir_node *new_ptr = transform_node(env, ptr);
2519 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2520 ir_mode *mode = get_type_mode(get_entity_type(ent));
2521 ir_node *projs[pn_Load_max];
2523 ia32_collect_Projs(node, projs, pn_Load_max);
2525 if (mode_is_float(mode)) {
2527 if (USE_SSE2(env->cg)) {
2528 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2531 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2535 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2538 set_ia32_frame_ent(new_op, ent);
2539 set_ia32_use_frame(new_op);
2541 set_ia32_am_support(new_op, ia32_am_Source);
2542 set_ia32_op_type(new_op, ia32_AddrModeS);
2543 set_ia32_am_flavour(new_op, ia32_am_B);
2544 set_ia32_ls_mode(new_op, mode);
2546 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2553 * Transforms a FrameStore into an ia32 Store.
2555 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2556 ir_node *new_op = NULL;
2557 ir_graph *irg = env->irg;
2558 dbg_info *dbgi = get_irn_dbg_info(node);
2559 ir_node *block = transform_node(env, get_nodes_block(node));
2560 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2561 ir_node *mem = get_irn_n(node, 0);
2562 ir_node *ptr = get_irn_n(node, 1);
2563 ir_node *val = get_irn_n(node, 2);
2564 ir_node *new_mem = transform_node(env, mem);
2565 ir_node *new_ptr = transform_node(env, ptr);
2566 ir_node *new_val = transform_node(env, val);
2567 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2568 ir_mode *mode = get_irn_mode(val);
2570 if (mode_is_float(mode)) {
2572 if (USE_SSE2(env->cg)) {
2573 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2575 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2577 } else if (get_mode_size_bits(mode) == 8) {
2578 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2580 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2583 set_ia32_frame_ent(new_op, ent);
2584 set_ia32_use_frame(new_op);
2586 set_ia32_am_support(new_op, ia32_am_Dest);
2587 set_ia32_op_type(new_op, ia32_AddrModeD);
2588 set_ia32_am_flavour(new_op, ia32_am_B);
2589 set_ia32_ls_mode(new_op, mode);
2591 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2597 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2599 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2600 ir_graph *irg = env->irg;
2603 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2604 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2605 ir_entity *ent = get_irg_entity(irg);
2606 ir_type *tp = get_entity_type(ent);
2609 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2610 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2612 int pn_ret_val, pn_ret_mem, arity, i;
2614 assert(ret_val != NULL);
2615 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2616 return duplicate_node(env, node);
2619 res_type = get_method_res_type(tp, 0);
2621 if (!is_Primitive_type(res_type)) {
2622 return duplicate_node(env, node);
2625 mode = get_type_mode(res_type);
2626 if (!mode_is_float(mode)) {
2627 return duplicate_node(env, node);
2630 assert(get_method_n_ress(tp) == 1);
2632 pn_ret_val = get_Proj_proj(ret_val);
2633 pn_ret_mem = get_Proj_proj(ret_mem);
2635 /* get the Barrier */
2636 barrier = get_Proj_pred(ret_val);
2638 /* get result input of the Barrier */
2639 ret_val = get_irn_n(barrier, pn_ret_val);
2640 new_ret_val = transform_node(env, ret_val);
2642 /* get memory input of the Barrier */
2643 ret_mem = get_irn_n(barrier, pn_ret_mem);
2644 new_ret_mem = transform_node(env, ret_mem);
2646 frame = get_irg_frame(irg);
2648 dbgi = get_irn_dbg_info(barrier);
2649 block = transform_node(env, get_nodes_block(barrier));
2651 /* store xmm0 onto stack */
2652 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2653 set_ia32_ls_mode(sse_store, mode);
2654 set_ia32_op_type(sse_store, ia32_AddrModeD);
2655 set_ia32_use_frame(sse_store);
2656 set_ia32_am_flavour(sse_store, ia32_am_B);
2657 set_ia32_am_support(sse_store, ia32_am_Dest);
2660 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2661 set_ia32_ls_mode(fld, mode);
2662 set_ia32_op_type(fld, ia32_AddrModeS);
2663 set_ia32_use_frame(fld);
2664 set_ia32_am_flavour(fld, ia32_am_B);
2665 set_ia32_am_support(fld, ia32_am_Source);
2667 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2668 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2669 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2671 /* create a new barrier */
2672 arity = get_irn_arity(barrier);
2673 in = alloca(arity * sizeof(in[0]));
2674 for(i = 0; i < arity; ++i) {
2676 if(i == pn_ret_val) {
2678 } else if(i == pn_ret_mem) {
2681 ir_node *in = get_irn_n(barrier, i);
2682 new_in = transform_node(env, in);
2687 new_barrier = new_ir_node(dbgi, irg, block,
2688 get_irn_op(barrier), get_irn_mode(barrier),
2690 copy_node_attr(barrier, new_barrier);
2691 duplicate_deps(env, barrier, new_barrier);
2692 set_new_node(barrier, new_barrier);
2693 mark_irn_visited(barrier);
2695 /* transform normally */
2696 return duplicate_node(env, node);
2700 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2702 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2704 ir_graph *irg = env->irg;
2705 dbg_info *dbgi = get_irn_dbg_info(node);
2706 ir_node *block = transform_node(env, get_nodes_block(node));
2707 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2708 ir_node *new_sz = transform_node(env, sz);
2709 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2710 ir_node *new_sp = transform_node(env, sp);
2711 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2712 ir_node *nomem = new_NoMem();
2714 /* ia32 stack grows in reverse direction, make a SubSP */
2715 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2716 set_ia32_am_support(new_op, ia32_am_Source);
2717 fold_immediate(env, new_op, 2, 3);
2719 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2725 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2727 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2729 ir_graph *irg = env->irg;
2730 dbg_info *dbgi = get_irn_dbg_info(node);
2731 ir_node *block = transform_node(env, get_nodes_block(node));
2732 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2733 ir_node *new_sz = transform_node(env, sz);
2734 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2735 ir_node *new_sp = transform_node(env, sp);
2736 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2737 ir_node *nomem = new_NoMem();
2739 /* ia32 stack grows in reverse direction, make an AddSP */
2740 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2741 set_ia32_am_support(new_op, ia32_am_Source);
2742 fold_immediate(env, new_op, 2, 3);
2744 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2750 * This function just sets the register for the Unknown node
2751 * as this is not done during register allocation because Unknown
2752 * is an "ignore" node.
2754 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2755 ir_mode *mode = get_irn_mode(node);
2757 if (mode_is_float(mode)) {
2758 if (USE_SSE2(env->cg))
2759 return ia32_new_Unknown_xmm(env->cg);
2761 return ia32_new_Unknown_vfp(env->cg);
2762 } else if (mode_needs_gp_reg(mode)) {
2763 return ia32_new_Unknown_gp(env->cg);
2765 assert(0 && "unsupported Unknown-Mode");
2772 * Change some phi modes
2774 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2775 ir_graph *irg = env->irg;
2776 dbg_info *dbgi = get_irn_dbg_info(node);
2777 ir_mode *mode = get_irn_mode(node);
2778 ir_node *block = transform_node(env, get_nodes_block(node));
2782 if(mode_needs_gp_reg(mode)) {
2783 // we shouldn't have any 64bit stuff around anymore
2784 assert(get_mode_size_bits(mode) <= 32);
2785 // all integer operations are on 32bit registers now
2787 } else if(mode_is_float(mode)) {
2788 assert(mode == mode_D || mode == mode_F);
2789 if (USE_SSE2(env->cg)) {
2796 /* phi nodes allow loops, so we use the old arguments for now
2797 * and fix this later */
2798 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2799 get_irn_in(node) + 1);
2800 copy_node_attr(node, phi);
2801 duplicate_deps(env, node, phi);
2803 set_new_node(node, phi);
2805 /* put the preds in the worklist */
2806 arity = get_irn_arity(node);
2807 for(i = 0; i < arity; ++i) {
2808 ir_node *pred = get_irn_n(node, i);
2809 pdeq_putr(env->worklist, pred);
2815 /**********************************************************************
2818 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2819 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2820 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2821 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2823 **********************************************************************/
2825 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2827 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2830 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2831 ir_node *val, ir_node *mem);
2834 * Transforms a lowered Load into a "real" one.
2836 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2837 ir_graph *irg = env->irg;
2838 dbg_info *dbgi = get_irn_dbg_info(node);
2839 ir_node *block = transform_node(env, get_nodes_block(node));
2840 ir_mode *mode = get_ia32_ls_mode(node);
2842 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2843 ir_node *ptr = get_irn_n(node, 0);
2844 ir_node *mem = get_irn_n(node, 1);
2845 ir_node *new_ptr = transform_node(env, ptr);
2846 ir_node *new_mem = transform_node(env, mem);
2849 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2850 lowering we have x87 nodes, so we need to enforce simulation.
2852 if (mode_is_float(mode)) {
2854 if (fp_unit == fp_x87)
2858 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2860 set_ia32_am_support(new_op, ia32_am_Source);
2861 set_ia32_op_type(new_op, ia32_AddrModeS);
2862 set_ia32_am_flavour(new_op, ia32_am_OB);
2863 set_ia32_am_offs_int(new_op, 0);
2864 set_ia32_am_scale(new_op, 1);
2865 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2866 if(is_ia32_am_sc_sign(node))
2867 set_ia32_am_sc_sign(new_op);
2868 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2869 if(is_ia32_use_frame(node)) {
2870 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2871 set_ia32_use_frame(new_op);
2874 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2880 * Transforms a lowered Store into a "real" one.
2882 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2883 ir_graph *irg = env->irg;
2884 dbg_info *dbgi = get_irn_dbg_info(node);
2885 ir_node *block = transform_node(env, get_nodes_block(node));
2886 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2887 ir_mode *mode = get_ia32_ls_mode(node);
2890 ia32_am_flavour_t am_flav = ia32_B;
2891 ir_node *ptr = get_irn_n(node, 0);
2892 ir_node *val = get_irn_n(node, 1);
2893 ir_node *mem = get_irn_n(node, 2);
2894 ir_node *new_ptr = transform_node(env, ptr);
2895 ir_node *new_val = transform_node(env, val);
2896 ir_node *new_mem = transform_node(env, mem);
2899 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2900 lowering we have x87 nodes, so we need to enforce simulation.
2902 if (mode_is_float(mode)) {
2904 if (fp_unit == fp_x87)
2908 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2910 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2912 add_ia32_am_offs_int(new_op, am_offs);
2915 set_ia32_am_support(new_op, ia32_am_Dest);
2916 set_ia32_op_type(new_op, ia32_AddrModeD);
2917 set_ia32_am_flavour(new_op, am_flav);
2918 set_ia32_ls_mode(new_op, mode);
2919 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2920 set_ia32_use_frame(new_op);
2922 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2929 * Transforms an ia32_l_XXX into a "real" XXX node
2931 * @param env The transformation environment
2932 * @return the created ia32 XXX node
2934 #define GEN_LOWERED_OP(op) \
2935 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2936 ir_mode *mode = get_irn_mode(node); \
2937 if (mode_is_float(mode)) \
2939 return gen_binop(env, node, get_binop_left(node), \
2940 get_binop_right(node), new_rd_ia32_##op); \
2943 #define GEN_LOWERED_x87_OP(op) \
2944 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2946 FORCE_x87(env->cg); \
2947 new_op = gen_binop_float(env, node, get_binop_left(node), \
2948 get_binop_right(node), new_rd_ia32_##op); \
2952 #define GEN_LOWERED_UNOP(op) \
2953 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2954 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2957 #define GEN_LOWERED_SHIFT_OP(op) \
2958 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2959 return gen_shift_binop(env, node, get_binop_left(node), \
2960 get_binop_right(node), new_rd_ia32_##op); \
2963 #define GEN_LOWERED_LOAD(op, fp_unit) \
2964 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2965 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2968 #define GEN_LOWERED_STORE(op, fp_unit) \
2969 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2970 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2977 GEN_LOWERED_OP(IMul)
2979 GEN_LOWERED_x87_OP(vfprem)
2980 GEN_LOWERED_x87_OP(vfmul)
2981 GEN_LOWERED_x87_OP(vfsub)
2983 GEN_LOWERED_UNOP(Neg)
2985 GEN_LOWERED_LOAD(vfild, fp_x87)
2986 GEN_LOWERED_LOAD(Load, fp_none)
2987 /*GEN_LOWERED_STORE(vfist, fp_x87)
2990 GEN_LOWERED_STORE(Store, fp_none)
2992 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2993 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2994 ir_graph *irg = env->irg;
2995 dbg_info *dbgi = get_irn_dbg_info(node);
2996 ir_node *block = transform_node(env, get_nodes_block(node));
2997 ir_node *left = get_binop_left(node);
2998 ir_node *right = get_binop_right(node);
2999 ir_node *new_left = transform_node(env, left);
3000 ir_node *new_right = transform_node(env, right);
3003 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3004 clear_ia32_commutative(vfdiv);
3005 set_ia32_am_support(vfdiv, ia32_am_Source);
3006 fold_immediate(env, vfdiv, 2, 3);
3008 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3016 * Transforms a l_MulS into a "real" MulS node.
3018 * @param env The transformation environment
3019 * @return the created ia32 Mul node
3021 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3022 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3023 ir_graph *irg = env->irg;
3024 dbg_info *dbgi = get_irn_dbg_info(node);
3025 ir_node *block = transform_node(env, get_nodes_block(node));
3026 ir_node *left = get_binop_left(node);
3027 ir_node *right = get_binop_right(node);
3028 ir_node *new_left = transform_node(env, left);
3029 ir_node *new_right = transform_node(env, right);
3032 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3033 /* and then skip the result Proj, because all needed Projs are already there. */
3034 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3035 clear_ia32_commutative(muls);
3036 set_ia32_am_support(muls, ia32_am_Source);
3037 fold_immediate(env, muls, 2, 3);
3039 /* check if EAX and EDX proj exist, add missing one */
3040 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3041 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3042 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3044 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3049 GEN_LOWERED_SHIFT_OP(Shl)
3050 GEN_LOWERED_SHIFT_OP(Shr)
3051 GEN_LOWERED_SHIFT_OP(Sar)
3054 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3055 * op1 - target to be shifted
3056 * op2 - contains bits to be shifted into target
3058 * Only op3 can be an immediate.
3060 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3061 ir_node *op1, ir_node *op2,
3063 ir_node *new_op = NULL;
3064 ir_graph *irg = env->irg;
3065 dbg_info *dbgi = get_irn_dbg_info(node);
3066 ir_node *block = transform_node(env, get_nodes_block(node));
3067 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3068 ir_node *nomem = new_NoMem();
3070 ir_node *new_op1 = transform_node(env, op1);
3071 ir_node *new_op2 = transform_node(env, op2);
3072 ir_node *new_count = transform_node(env, count);
3075 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3077 /* Check if immediate optimization is on and */
3078 /* if it's an operation with immediate. */
3079 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3081 /* Limit imm_op within range imm8 */
3083 tv = get_ia32_Immop_tarval(imm_op);
3086 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3087 set_ia32_Immop_tarval(imm_op, tv);
3094 /* integer operations */
3096 /* This is ShiftD with const */
3097 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3099 if (is_ia32_l_ShlD(node))
3100 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3101 new_op1, new_op2, noreg, nomem);
3103 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3104 new_op1, new_op2, noreg, nomem);
3105 copy_ia32_Immop_attr(new_op, imm_op);
3108 /* This is a normal ShiftD */
3109 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3110 if (is_ia32_l_ShlD(node))
3111 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3112 new_op1, new_op2, new_count, nomem);
3114 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3115 new_op1, new_op2, new_count, nomem);
3118 /* set AM support */
3119 // Matze: node has unsupported format (6inputs)
3120 //set_ia32_am_support(new_op, ia32_am_Dest);
3122 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3124 set_ia32_emit_cl(new_op);
3129 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3130 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3131 get_irn_n(node, 1), get_irn_n(node, 2));
3134 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3135 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3136 get_irn_n(node, 1), get_irn_n(node, 2));
3140 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3142 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3143 ia32_code_gen_t *cg = env->cg;
3144 ir_node *res = NULL;
3145 ir_graph *irg = env->irg;
3146 dbg_info *dbgi = get_irn_dbg_info(node);
3147 ir_node *block = transform_node(env, get_nodes_block(node));
3148 ir_node *ptr = get_irn_n(node, 0);
3149 ir_node *val = get_irn_n(node, 1);
3150 ir_node *new_val = transform_node(env, val);
3151 ir_node *mem = get_irn_n(node, 2);
3152 ir_node *noreg, *new_ptr, *new_mem;
3158 noreg = ia32_new_NoReg_gp(cg);
3159 new_mem = transform_node(env, mem);
3160 new_ptr = transform_node(env, ptr);
3162 /* Store x87 -> MEM */
3163 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3164 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3165 set_ia32_use_frame(res);
3166 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3167 set_ia32_am_support(res, ia32_am_Dest);
3168 set_ia32_am_flavour(res, ia32_B);
3169 set_ia32_op_type(res, ia32_AddrModeD);
3171 /* Load MEM -> SSE */
3172 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3173 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3174 set_ia32_use_frame(res);
3175 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3176 set_ia32_am_support(res, ia32_am_Source);
3177 set_ia32_am_flavour(res, ia32_B);
3178 set_ia32_op_type(res, ia32_AddrModeS);
3179 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3185 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3187 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3188 ia32_code_gen_t *cg = env->cg;
3189 ir_graph *irg = env->irg;
3190 dbg_info *dbgi = get_irn_dbg_info(node);
3191 ir_node *block = transform_node(env, get_nodes_block(node));
3192 ir_node *res = NULL;
3193 ir_node *ptr = get_irn_n(node, 0);
3194 ir_node *val = get_irn_n(node, 1);
3195 ir_node *mem = get_irn_n(node, 2);
3196 ir_entity *fent = get_ia32_frame_ent(node);
3197 ir_mode *lsmode = get_ia32_ls_mode(node);
3198 ir_node *new_val = transform_node(env, val);
3199 ir_node *noreg, *new_ptr, *new_mem;
3202 if (!USE_SSE2(cg)) {
3203 /* SSE unit is not used -> skip this node. */
3207 noreg = ia32_new_NoReg_gp(cg);
3208 new_val = transform_node(env, val);
3209 new_ptr = transform_node(env, ptr);
3210 new_mem = transform_node(env, mem);
3212 /* Store SSE -> MEM */
3213 if (is_ia32_xLoad(skip_Proj(new_val))) {
3214 ir_node *ld = skip_Proj(new_val);
3216 /* we can vfld the value directly into the fpu */
3217 fent = get_ia32_frame_ent(ld);
3218 ptr = get_irn_n(ld, 0);
3219 offs = get_ia32_am_offs_int(ld);
3221 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3222 set_ia32_frame_ent(res, fent);
3223 set_ia32_use_frame(res);
3224 set_ia32_ls_mode(res, lsmode);
3225 set_ia32_am_support(res, ia32_am_Dest);
3226 set_ia32_am_flavour(res, ia32_B);
3227 set_ia32_op_type(res, ia32_AddrModeD);
3231 /* Load MEM -> x87 */
3232 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3233 set_ia32_frame_ent(res, fent);
3234 set_ia32_use_frame(res);
3235 set_ia32_ls_mode(res, lsmode);
3236 add_ia32_am_offs_int(res, offs);
3237 set_ia32_am_support(res, ia32_am_Source);
3238 set_ia32_am_flavour(res, ia32_B);
3239 set_ia32_op_type(res, ia32_AddrModeS);
3240 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3245 /*********************************************************
3248 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3249 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3250 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3251 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3253 *********************************************************/
3256 * the BAD transformer.
3258 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3259 panic("No transform function for %+F available.\n", node);
3263 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3264 /* end has to be duplicated manually because we need a dynamic in array */
3265 ir_graph *irg = env->irg;
3266 dbg_info *dbgi = get_irn_dbg_info(node);
3267 ir_node *block = transform_node(env, get_nodes_block(node));
3271 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3272 copy_node_attr(node, new_end);
3273 duplicate_deps(env, node, new_end);
3275 set_irg_end(irg, new_end);
3276 set_new_node(new_end, new_end);
3278 /* transform preds */
3279 arity = get_irn_arity(node);
3280 for(i = 0; i < arity; ++i) {
3281 ir_node *in = get_irn_n(node, i);
3282 ir_node *new_in = transform_node(env, in);
3284 add_End_keepalive(new_end, new_in);
3290 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3291 ir_graph *irg = env->irg;
3292 dbg_info *dbgi = get_irn_dbg_info(node);
3293 ir_node *start_block = env->old_anchors[anchor_start_block];
3298 * We replace the ProjX from the start node with a jump,
3299 * so the startblock has no preds anymore now
3301 if(node == start_block) {
3302 return new_rd_Block(dbgi, irg, 0, NULL);
3305 /* we use the old blocks for now, because jumps allow cycles in the graph
3306 * we have to fix this later */
3307 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3308 get_irn_arity(node), get_irn_in(node) + 1);
3309 copy_node_attr(node, block);
3311 #ifdef DEBUG_libfirm
3312 block->node_nr = node->node_nr;
3314 set_new_node(node, block);
3316 /* put the preds in the worklist */
3317 arity = get_irn_arity(node);
3318 for(i = 0; i < arity; ++i) {
3319 ir_node *in = get_irn_n(node, i);
3320 pdeq_putr(env->worklist, in);
3326 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3327 ir_graph *irg = env->irg;
3328 ir_node *block = transform_node(env, get_nodes_block(node));
3329 dbg_info *dbgi = get_irn_dbg_info(node);
3330 ir_node *pred = get_Proj_pred(node);
3331 ir_node *new_pred = transform_node(env, pred);
3332 long proj = get_Proj_proj(node);
3334 if(proj == pn_be_AddSP_res) {
3335 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3336 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3338 } else if(proj == pn_be_AddSP_M) {
3339 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3343 return new_rd_Unknown(irg, get_irn_mode(node));
3346 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3347 ir_graph *irg = env->irg;
3348 ir_node *block = transform_node(env, get_nodes_block(node));
3349 dbg_info *dbgi = get_irn_dbg_info(node);
3350 ir_node *pred = get_Proj_pred(node);
3351 ir_node *new_pred = transform_node(env, pred);
3352 long proj = get_Proj_proj(node);
3354 if(proj == pn_be_SubSP_res) {
3355 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3356 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3358 } else if(proj == pn_be_SubSP_M) {
3359 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3363 return new_rd_Unknown(irg, get_irn_mode(node));
3366 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3367 ir_graph *irg = env->irg;
3368 ir_node *block = transform_node(env, get_nodes_block(node));
3369 dbg_info *dbgi = get_irn_dbg_info(node);
3370 ir_node *pred = get_Proj_pred(node);
3371 ir_node *new_pred = transform_node(env, pred);
3372 long proj = get_Proj_proj(node);
3374 /* renumber the proj */
3375 if(is_ia32_Load(new_pred)) {
3376 if(proj == pn_Load_res) {
3377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3378 } else if(proj == pn_Load_M) {
3379 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3381 } else if(is_ia32_xLoad(new_pred)) {
3382 if(proj == pn_Load_res) {
3383 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3384 } else if(proj == pn_Load_M) {
3385 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3387 } else if(is_ia32_vfld(new_pred)) {
3388 if(proj == pn_Load_res) {
3389 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3390 } else if(proj == pn_Load_M) {
3391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3396 return new_rd_Unknown(irg, get_irn_mode(node));
3399 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3400 ir_graph *irg = env->irg;
3401 dbg_info *dbgi = get_irn_dbg_info(node);
3402 ir_node *block = transform_node(env, get_nodes_block(node));
3403 ir_mode *mode = get_irn_mode(node);
3405 ir_node *pred = get_Proj_pred(node);
3406 ir_node *new_pred = transform_node(env, pred);
3407 long proj = get_Proj_proj(node);
3409 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3411 switch(get_irn_opcode(pred)) {
3415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3417 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3425 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3427 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3435 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3436 case pn_DivMod_res_div:
3437 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3438 case pn_DivMod_res_mod:
3439 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3449 return new_rd_Unknown(irg, mode);
3452 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3454 ir_graph *irg = env->irg;
3455 dbg_info *dbgi = get_irn_dbg_info(node);
3456 ir_node *block = transform_node(env, get_nodes_block(node));
3457 ir_mode *mode = get_irn_mode(node);
3459 ir_node *pred = get_Proj_pred(node);
3460 ir_node *new_pred = transform_node(env, pred);
3461 long proj = get_Proj_proj(node);
3464 case pn_CopyB_M_regular:
3465 if(is_ia32_CopyB_i(new_pred)) {
3466 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3468 } else if(is_ia32_CopyB(new_pred)) {
3469 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3478 return new_rd_Unknown(irg, mode);
3481 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3483 ir_graph *irg = env->irg;
3484 dbg_info *dbgi = get_irn_dbg_info(node);
3485 ir_node *block = transform_node(env, get_nodes_block(node));
3486 ir_mode *mode = get_irn_mode(node);
3488 ir_node *pred = get_Proj_pred(node);
3489 ir_node *new_pred = transform_node(env, pred);
3490 long proj = get_Proj_proj(node);
3493 case pn_ia32_l_vfdiv_M:
3494 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3495 case pn_ia32_l_vfdiv_res:
3496 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3501 return new_rd_Unknown(irg, mode);
3504 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3506 ir_graph *irg = env->irg;
3507 dbg_info *dbgi = get_irn_dbg_info(node);
3508 ir_node *block = transform_node(env, get_nodes_block(node));
3509 ir_mode *mode = get_irn_mode(node);
3511 ir_node *pred = get_Proj_pred(node);
3512 ir_node *new_pred = transform_node(env, pred);
3513 long proj = get_Proj_proj(node);
3517 if(is_ia32_xDiv(new_pred)) {
3518 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3520 } else if(is_ia32_vfdiv(new_pred)) {
3521 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3526 if(is_ia32_xDiv(new_pred)) {
3527 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3529 } else if(is_ia32_vfdiv(new_pred)) {
3530 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3539 return new_rd_Unknown(irg, mode);
3542 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3543 ir_graph *irg = env->irg;
3544 //dbg_info *dbgi = get_irn_dbg_info(node);
3545 dbg_info *dbgi = NULL;
3546 ir_node *block = transform_node(env, get_nodes_block(node));
3548 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3553 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3554 ir_graph *irg = env->irg;
3555 dbg_info *dbgi = get_irn_dbg_info(node);
3556 long proj = get_Proj_proj(node);
3557 ir_mode *mode = get_irn_mode(node);
3558 ir_node *block = transform_node(env, get_nodes_block(node));
3560 ir_node *call = get_Proj_pred(node);
3561 ir_node *new_call = transform_node(env, call);
3562 const arch_register_class_t *cls;
3564 /* The following is kinda tricky: If we're using SSE, then we have to
3565 * move the result value of the call in floating point registers to an
3566 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3567 * after the call, we have to make sure to correctly make the
3568 * MemProj and the result Proj use these 2 nodes
3570 if(proj == pn_be_Call_M_regular) {
3571 // get new node for result, are we doing the sse load/store hack?
3572 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3573 ir_node *call_res_new;
3574 ir_node *call_res_pred = NULL;
3576 if(call_res != NULL) {
3577 call_res_new = transform_node(env, call_res);
3578 call_res_pred = get_Proj_pred(call_res_new);
3581 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3582 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3584 assert(is_ia32_xLoad(call_res_pred));
3585 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3588 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3589 && USE_SSE2(env->cg)) {
3591 ir_node *frame = get_irg_frame(irg);
3592 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3594 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3596 const arch_register_class_t *cls;
3598 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3599 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3601 /* store st(0) onto stack */
3602 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3604 set_ia32_ls_mode(fstp, mode);
3605 set_ia32_op_type(fstp, ia32_AddrModeD);
3606 set_ia32_use_frame(fstp);
3607 set_ia32_am_flavour(fstp, ia32_am_B);
3608 set_ia32_am_support(fstp, ia32_am_Dest);
3610 /* load into SSE register */
3611 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3612 set_ia32_ls_mode(sse_load, mode);
3613 set_ia32_op_type(sse_load, ia32_AddrModeS);
3614 set_ia32_use_frame(sse_load);
3615 set_ia32_am_flavour(sse_load, ia32_am_B);
3616 set_ia32_am_support(sse_load, ia32_am_Source);
3618 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3620 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3622 /* get a Proj representing a caller save register */
3623 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3624 assert(is_Proj(p) && "Proj expected.");
3626 /* user of the the proj is the Keep */
3627 p = get_edge_src_irn(get_irn_out_edge_first(p));
3628 assert(be_is_Keep(p) && "Keep expected.");
3630 /* keep the result */
3631 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3632 keepin[0] = sse_load;
3633 be_new_Keep(cls, irg, block, 1, keepin);
3638 /* transform call modes */
3639 if (mode_is_data(mode)) {
3640 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3644 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3647 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3648 ir_graph *irg = env->irg;
3649 dbg_info *dbgi = get_irn_dbg_info(node);
3650 ir_node *pred = get_Proj_pred(node);
3651 long proj = get_Proj_proj(node);
3653 if(is_Store(pred) || be_is_FrameStore(pred)) {
3654 if(proj == pn_Store_M) {
3655 return transform_node(env, pred);
3658 return new_r_Bad(irg);
3660 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3661 return gen_Proj_Load(env, node);
3662 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3663 return gen_Proj_DivMod(env, node);
3664 } else if(is_CopyB(pred)) {
3665 return gen_Proj_CopyB(env, node);
3666 } else if(is_Quot(pred)) {
3667 return gen_Proj_Quot(env, node);
3668 } else if(is_ia32_l_vfdiv(pred)) {
3669 return gen_Proj_l_vfdiv(env, node);
3670 } else if(be_is_SubSP(pred)) {
3671 return gen_Proj_be_SubSP(env, node);
3672 } else if(be_is_AddSP(pred)) {
3673 return gen_Proj_be_AddSP(env, node);
3674 } else if(be_is_Call(pred)) {
3675 return gen_Proj_be_Call(env, node);
3676 } else if(get_irn_op(pred) == op_Start) {
3677 if(proj == pn_Start_X_initial_exec) {
3678 ir_node *block = get_nodes_block(pred);
3681 block = transform_node(env, block);
3682 // we exchange the ProjX with a jump
3683 jump = new_rd_Jmp(dbgi, irg, block);
3684 ir_fprintf(stderr, "created jump: %+F\n", jump);
3687 if(node == env->old_anchors[anchor_tls]) {
3688 return gen_Proj_tls(env, node);
3691 ir_node *new_pred = transform_node(env, pred);
3692 ir_node *block = transform_node(env, get_nodes_block(node));
3693 ir_mode *mode = get_irn_mode(node);
3694 if (mode_needs_gp_reg(mode)) {
3695 return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
3699 return duplicate_node(env, node);
3703 * Enters all transform functions into the generic pointer
3705 static void register_transformers(void) {
3706 ir_op *op_Max, *op_Min, *op_Mulh;
3708 /* first clear the generic function pointer for all ops */
3709 clear_irp_opcodes_generic_func();
3711 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3712 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3751 /* transform ops from intrinsic lowering */
3771 /* GEN(ia32_l_vfist); TODO */
3773 GEN(ia32_l_X87toSSE);
3774 GEN(ia32_l_SSEtoX87);
3779 /* we should never see these nodes */
3794 /* handle generic backend nodes */
3804 /* set the register for all Unknown nodes */
3807 op_Max = get_op_Max();
3810 op_Min = get_op_Min();
3813 op_Mulh = get_op_Mulh();
3821 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3825 int deps = get_irn_deps(old_node);
3827 for(i = 0; i < deps; ++i) {
3828 ir_node *dep = get_irn_dep(old_node, i);
3829 ir_node *new_dep = transform_node(env, dep);
3831 add_irn_dep(new_node, new_dep);
3835 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3837 ir_graph *irg = env->irg;
3838 dbg_info *dbgi = get_irn_dbg_info(node);
3839 ir_mode *mode = get_irn_mode(node);
3840 ir_op *op = get_irn_op(node);
3845 block = transform_node(env, get_nodes_block(node));
3847 arity = get_irn_arity(node);
3848 if(op->opar == oparity_dynamic) {
3849 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3850 for(i = 0; i < arity; ++i) {
3851 ir_node *in = get_irn_n(node, i);
3852 in = transform_node(env, in);
3853 add_irn_n(new_node, in);
3856 ir_node **ins = alloca(arity * sizeof(ins[0]));
3857 for(i = 0; i < arity; ++i) {
3858 ir_node *in = get_irn_n(node, i);
3859 ins[i] = transform_node(env, in);
3862 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3865 copy_node_attr(node, new_node);
3866 duplicate_deps(env, node, new_node);
3871 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3874 ir_op *op = get_irn_op(node);
3876 if(irn_visited(node)) {
3877 assert(get_new_node(node) != NULL);
3878 return get_new_node(node);
3881 mark_irn_visited(node);
3882 DEBUG_ONLY(set_new_node(node, NULL));
3884 if (op->ops.generic) {
3885 transform_func *transform = (transform_func *)op->ops.generic;
3887 new_node = (*transform)(env, node);
3888 assert(new_node != NULL);
3890 new_node = duplicate_node(env, node);
3892 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3894 set_new_node(node, new_node);
3895 mark_irn_visited(new_node);
3896 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3900 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3904 if(irn_visited(node))
3906 mark_irn_visited(node);
3908 assert(node_is_in_irgs_storage(env->irg, node));
3910 if(!is_Block(node)) {
3911 ir_node *block = get_nodes_block(node);
3912 ir_node *new_block = (ir_node*) get_irn_link(block);
3914 if(new_block != NULL) {
3915 set_nodes_block(node, new_block);
3919 fix_loops(env, block);
3922 arity = get_irn_arity(node);
3923 for(i = 0; i < arity; ++i) {
3924 ir_node *in = get_irn_n(node, i);
3925 ir_node *new = (ir_node*) get_irn_link(in);
3927 if(new != NULL && new != in) {
3928 set_irn_n(node, i, new);
3935 arity = get_irn_deps(node);
3936 for(i = 0; i < arity; ++i) {
3937 ir_node *in = get_irn_dep(node, i);
3938 ir_node *new = (ir_node*) get_irn_link(in);
3940 if(new != NULL && new != in) {
3941 set_irn_dep(node, i, new);
3949 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3954 *place = transform_node(env, *place);
3957 static void transform_nodes(ia32_code_gen_t *cg)
3960 ir_graph *irg = cg->irg;
3962 ia32_transform_env_t env;
3964 hook_dead_node_elim(irg, 1);
3966 inc_irg_visited(irg);
3970 env.visited = get_irg_visited(irg);
3971 env.worklist = new_pdeq();
3972 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3974 old_end = get_irg_end(irg);
3976 /* put all anchor nodes in the worklist */
3977 for(i = 0; i < anchor_max; ++i) {
3978 ir_node *anchor = irg->anchors[i];
3981 pdeq_putr(env.worklist, anchor);
3984 env.old_anchors[i] = anchor;
3985 // and set it to NULL to make sure we don't accidently use it
3986 irg->anchors[i] = NULL;
3989 // pre transform some anchors (so they are available in the other transform
3991 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3992 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3993 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3994 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3995 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3997 pre_transform_node(&cg->unknown_gp, &env);
3998 pre_transform_node(&cg->unknown_vfp, &env);
3999 pre_transform_node(&cg->unknown_xmm, &env);
4000 pre_transform_node(&cg->noreg_gp, &env);
4001 pre_transform_node(&cg->noreg_vfp, &env);
4002 pre_transform_node(&cg->noreg_xmm, &env);
4004 /* process worklist (this should transform all nodes in the graph) */
4005 while(!pdeq_empty(env.worklist)) {
4006 ir_node *node = pdeq_getl(env.worklist);
4007 transform_node(&env, node);
4010 /* fix loops and set new anchors*/
4011 inc_irg_visited(irg);
4012 for(i = 0; i < anchor_max; ++i) {
4013 ir_node *anchor = env.old_anchors[i];
4017 anchor = get_irn_link(anchor);
4018 fix_loops(&env, anchor);
4019 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4020 irg->anchors[i] = anchor;
4023 del_pdeq(env.worklist);
4025 hook_dead_node_elim(irg, 0);
4028 void ia32_transform_graph(ia32_code_gen_t *cg)
4030 ir_graph *irg = cg->irg;
4031 be_irg_t *birg = cg->birg;
4032 ir_graph *old_current_ir_graph = current_ir_graph;
4033 int old_interprocedural_view = get_interprocedural_view();
4034 struct obstack *old_obst = NULL;
4035 struct obstack *new_obst = NULL;
4037 current_ir_graph = irg;
4038 set_interprocedural_view(0);
4039 register_transformers();
4041 /* most analysis info is wrong after transformation */
4042 free_callee_info(irg);
4044 irg->outs_state = outs_none;
4046 free_loop_information(irg);
4047 set_irg_doms_inconsistent(irg);
4048 be_invalidate_liveness(birg);
4049 be_invalidate_dom_front(birg);
4051 /* create a new obstack */
4052 old_obst = irg->obst;
4053 new_obst = xmalloc(sizeof(*new_obst));
4054 obstack_init(new_obst);
4055 irg->obst = new_obst;
4056 irg->last_node_idx = 0;
4058 /* create new value table for CSE */
4059 del_identities(irg->value_table);
4060 irg->value_table = new_identities();
4062 /* do the main transformation */
4063 transform_nodes(cg);
4065 /* we don't want the globals anchor anymore */
4066 set_irg_globals(irg, new_r_Bad(irg));
4068 /* free the old obstack */
4069 obstack_free(old_obst, 0);
4073 current_ir_graph = old_current_ir_graph;
4074 set_interprocedural_view(old_interprocedural_view);
4076 /* recalculate edges */
4077 edges_deactivate(irg);
4078 edges_activate(irg);
4082 * Transforms a psi condition.
4084 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4087 /* if the mode is target mode, we have already seen this part of the tree */
4088 if (get_irn_mode(cond) == mode)
4091 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4093 set_irn_mode(cond, mode);
4095 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4096 ir_node *in = get_irn_n(cond, i);
4098 /* if in is a compare: transform into Set/xCmp */
4100 ir_node *new_op = NULL;
4101 ir_node *cmp = get_Proj_pred(in);
4102 ir_node *cmp_a = get_Cmp_left(cmp);
4103 ir_node *cmp_b = get_Cmp_right(cmp);
4104 dbg_info *dbgi = get_irn_dbg_info(cmp);
4105 ir_graph *irg = get_irn_irg(cmp);
4106 ir_node *block = get_nodes_block(cmp);
4107 ir_node *noreg = ia32_new_NoReg_gp(cg);
4108 ir_node *nomem = new_rd_NoMem(irg);
4109 int pnc = get_Proj_proj(in);
4111 /* this is a compare */
4112 if (mode_is_float(mode)) {
4113 /* Psi is float, we need a floating point compare */
4116 ir_mode *m = get_irn_mode(cmp_a);
4118 if (! mode_is_float(m)) {
4119 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4120 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4121 } else if (m == mode_F) {
4122 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4123 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4124 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4127 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4128 set_ia32_pncode(new_op, pnc);
4129 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4136 construct_binop_func *set_func = NULL;
4138 if (mode_is_float(get_irn_mode(cmp_a))) {
4139 /* 1st case: compare operands are floats */
4144 set_func = new_rd_ia32_xCmpSet;
4147 set_func = new_rd_ia32_vfCmpSet;
4150 pnc &= 7; /* fp compare -> int compare */
4152 /* 2nd case: compare operand are integer too */
4153 set_func = new_rd_ia32_CmpSet;
4156 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4157 if(!mode_is_signed(mode))
4158 pnc |= ia32_pn_Cmp_Unsigned;
4160 set_ia32_pncode(new_op, pnc);
4161 set_ia32_am_support(new_op, ia32_am_Source);
4164 /* the the new compare as in */
4165 set_irn_n(cond, i, new_op);
4167 /* another complex condition */
4168 transform_psi_cond(in, mode, cg);
4174 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4175 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4176 * each compare, which causes the compare result to be stored in a register. The
4177 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4179 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4180 ia32_code_gen_t *cg = env;
4181 ir_node *psi_sel, *new_cmp, *block;
4186 if (get_irn_opcode(node) != iro_Psi)
4189 psi_sel = get_Psi_cond(node, 0);
4191 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4192 if (is_Proj(psi_sel)) {
4193 assert(is_Cmp(get_Proj_pred(psi_sel)));
4197 //mode = get_irn_mode(node);
4198 // TODO probably wrong...
4201 transform_psi_cond(psi_sel, mode, cg);
4203 irg = get_irn_irg(node);
4204 block = get_nodes_block(node);
4206 /* we need to compare the evaluated condition tree with 0 */
4207 mode = get_irn_mode(node);
4208 if (mode_is_float(mode)) {
4209 /* BEWARE: new_r_Const_long works for floating point as well */
4210 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4212 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4213 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4214 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4216 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4217 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4218 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4221 set_Psi_cond(node, 0, new_cmp);
4224 void ia32_init_transform(void)
4226 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");