2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)
474 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
480 load = get_Proj_pred(node);
481 pn = get_Proj_proj(node);
482 if(!is_Load(load) || pn != pn_Load_res)
484 if(get_nodes_block(load) != block)
486 /* we only use address mode if we're the only user of the load */
487 if(get_irn_n_edges(node) > 1)
490 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
493 /* don't do AM if other node inputs depend on the load (via mem-proj) */
494 if(other != NULL && get_nodes_block(other) == block
495 && heights_reachable_in_block(heights, other, load))
501 typedef struct ia32_address_mode_t ia32_address_mode_t;
502 struct ia32_address_mode_t {
506 ia32_op_type_t op_type;
513 static void build_address(ia32_address_mode_t *am, ir_node *node)
515 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
516 ia32_address_t *addr = &am->addr;
525 ir_entity *entity = create_float_const_entity(node);
526 addr->base = noreg_gp;
527 addr->index = noreg_gp;
528 addr->mem = new_NoMem();
529 addr->symconst_ent = entity;
531 am->ls_mode = get_irn_mode(node);
535 load = get_Proj_pred(node);
536 ptr = get_Load_ptr(load);
537 mem = get_Load_mem(load);
538 new_mem = be_transform_node(mem);
539 am->ls_mode = get_Load_mode(load);
540 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
542 /* construct load address */
543 ia32_create_address_mode(addr, ptr, 0);
550 base = be_transform_node(base);
556 index = be_transform_node(index);
564 static void set_address(ir_node *node, ia32_address_t *addr)
566 set_ia32_am_scale(node, addr->scale);
567 set_ia32_am_sc(node, addr->symconst_ent);
568 set_ia32_am_offs_int(node, addr->offset);
569 if(addr->symconst_sign)
570 set_ia32_am_sc_sign(node);
572 set_ia32_use_frame(node);
573 set_ia32_frame_ent(node, addr->frame_entity);
576 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
578 set_address(node, &am->addr);
580 set_ia32_op_type(node, am->op_type);
581 set_ia32_ls_mode(node, am->ls_mode);
583 set_ia32_commutative(node);
587 match_commutative = 1 << 0,
588 match_am_and_immediates = 1 << 1,
589 match_no_am = 1 << 2,
590 match_8_bit_am = 1 << 3,
591 match_16_bit_am = 1 << 4,
592 match_no_immediate = 1 << 5,
593 match_force_32bit_op = 1 << 6
596 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
597 ir_node *op1, ir_node *op2, match_flags_t flags)
599 ia32_address_t *addr = &am->addr;
600 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
603 ir_mode *mode = get_irn_mode(op2);
606 int use_am_and_immediates;
608 int mode_bits = get_mode_size_bits(mode);
610 memset(am, 0, sizeof(am[0]));
612 commutative = (flags & match_commutative) != 0;
613 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
614 use_am = ! (flags & match_no_am);
615 use_immediate = !(flags & match_no_immediate);
618 assert(!commutative || op1 != NULL);
620 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
622 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
626 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
627 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
628 build_address(am, op2);
629 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
630 if(mode_is_float(mode)) {
631 new_op2 = ia32_new_NoReg_vfp(env_cg);
635 am->op_type = ia32_AddrModeS;
636 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
637 use_am && use_source_address_mode(block, op1, op2)) {
639 build_address(am, op1);
641 if(mode_is_float(mode)) {
642 noreg = ia32_new_NoReg_vfp(env_cg);
647 if(new_op2 != NULL) {
650 new_op1 = be_transform_node(op2);
652 am->ins_permuted = 1;
654 am->op_type = ia32_AddrModeS;
656 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
658 new_op2 = be_transform_node(op2);
659 am->op_type = ia32_Normal;
660 if(flags & match_force_32bit_op) {
661 am->ls_mode = mode_Iu;
663 am->ls_mode = get_irn_mode(op2);
666 if(addr->base == NULL)
667 addr->base = noreg_gp;
668 if(addr->index == NULL)
669 addr->index = noreg_gp;
670 if(addr->mem == NULL)
671 addr->mem = new_NoMem();
673 am->new_op1 = new_op1;
674 am->new_op2 = new_op2;
675 am->commutative = commutative;
678 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
680 ir_graph *irg = current_ir_graph;
684 if(am->mem_proj == NULL)
687 /* we have to create a mode_T so the old MemProj can attach to us */
688 mode = get_irn_mode(node);
689 load = get_Proj_pred(am->mem_proj);
691 mark_irn_visited(load);
692 be_set_transformed_node(load, node);
695 set_irn_mode(node, mode_T);
696 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
703 * Construct a standard binary operation, set AM and immediate if required.
705 * @param op1 The first operand
706 * @param op2 The second operand
707 * @param func The node constructor function
708 * @return The constructed ia32 node.
710 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
711 construct_binop_func *func, match_flags_t flags)
713 ir_node *block = get_nodes_block(node);
714 ir_node *new_block = be_transform_node(block);
715 ir_graph *irg = current_ir_graph;
716 dbg_info *dbgi = get_irn_dbg_info(node);
718 ia32_address_mode_t am;
719 ia32_address_t *addr = &am.addr;
721 flags |= match_force_32bit_op;
723 match_arguments(&am, block, op1, op2, flags);
725 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
726 am.new_op1, am.new_op2);
727 set_am_attributes(new_node, &am);
728 /* we can't use source address mode anymore when using immediates */
729 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
730 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
731 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
733 new_node = fix_mem_proj(new_node, &am);
740 n_ia32_l_binop_right,
741 n_ia32_l_binop_eflags
743 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
744 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
745 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
746 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
747 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
748 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
751 * Construct a binary operation which also consumes the eflags.
753 * @param node The node to transform
754 * @param func The node constructor function
755 * @param flags The match flags
756 * @return The constructor ia32 node
758 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
761 ir_node *src_block = get_nodes_block(node);
762 ir_node *block = be_transform_node(src_block);
763 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
764 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
765 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
766 ir_node *new_eflags = be_transform_node(eflags);
767 ir_graph *irg = current_ir_graph;
768 dbg_info *dbgi = get_irn_dbg_info(node);
770 ia32_address_mode_t am;
771 ia32_address_t *addr = &am.addr;
773 match_arguments(&am, src_block, op1, op2, flags);
775 new_node = func(dbgi, irg, block, addr->base, addr->index,
776 addr->mem, am.new_op1, am.new_op2, new_eflags);
777 set_am_attributes(new_node, &am);
778 /* we can't use source address mode anymore when using immediates */
779 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
780 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
781 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
783 new_node = fix_mem_proj(new_node, &am);
789 * Construct a standard binary operation, set AM and immediate if required.
791 * @param op1 The first operand
792 * @param op2 The second operand
793 * @param func The node constructor function
794 * @return The constructed ia32 node.
796 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
797 construct_binop_func *func,
800 ir_node *block = get_nodes_block(node);
801 ir_node *new_block = be_transform_node(block);
802 dbg_info *dbgi = get_irn_dbg_info(node);
803 ir_graph *irg = current_ir_graph;
805 ia32_address_mode_t am;
806 ia32_address_t *addr = &am.addr;
808 match_arguments(&am, block, op1, op2, flags);
810 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
811 am.new_op1, am.new_op2);
812 set_am_attributes(new_node, &am);
814 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
816 new_node = fix_mem_proj(new_node, &am);
821 static ir_node *get_fpcw(void)
824 if(initial_fpcw != NULL)
827 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
828 &ia32_fp_cw_regs[REG_FPCW]);
829 initial_fpcw = be_transform_node(fpcw);
835 * Construct a standard binary operation, set AM and immediate if required.
837 * @param op1 The first operand
838 * @param op2 The second operand
839 * @param func The node constructor function
840 * @return The constructed ia32 node.
842 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
843 construct_binop_float_func *func,
846 ir_graph *irg = current_ir_graph;
847 dbg_info *dbgi = get_irn_dbg_info(node);
848 ir_node *block = get_nodes_block(node);
849 ir_node *new_block = be_transform_node(block);
851 ia32_address_mode_t am;
852 ia32_address_t *addr = &am.addr;
854 match_arguments(&am, block, op1, op2, flags);
856 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
857 am.new_op1, am.new_op2, get_fpcw());
858 set_am_attributes(new_node, &am);
860 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
862 new_node = fix_mem_proj(new_node, &am);
868 * Construct a shift/rotate binary operation, sets AM and immediate if required.
870 * @param op1 The first operand
871 * @param op2 The second operand
872 * @param func The node constructor function
873 * @return The constructed ia32 node.
875 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
876 construct_shift_func *func)
878 dbg_info *dbgi = get_irn_dbg_info(node);
879 ir_graph *irg = current_ir_graph;
880 ir_node *block = get_nodes_block(node);
881 ir_node *new_block = be_transform_node(block);
882 ir_node *new_op1 = be_transform_node(op1);
883 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
886 assert(! mode_is_float(get_irn_mode(node))
887 && "Shift/Rotate with float not supported");
889 res = func(dbgi, irg, new_block, new_op1, new_op2);
890 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
892 /* lowered shift instruction may have a dependency operand, handle it here */
893 if (get_irn_arity(node) == 3) {
894 /* we have a dependency */
895 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
896 add_irn_dep(res, new_dep);
904 * Construct a standard unary operation, set AM and immediate if required.
906 * @param op The operand
907 * @param func The node constructor function
908 * @return The constructed ia32 node.
910 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
912 ir_node *block = be_transform_node(get_nodes_block(node));
913 ir_node *new_op = be_transform_node(op);
914 ir_node *new_node = NULL;
915 ir_graph *irg = current_ir_graph;
916 dbg_info *dbgi = get_irn_dbg_info(node);
918 new_node = func(dbgi, irg, block, new_op);
920 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
925 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
926 ia32_address_t *addr)
928 ir_graph *irg = current_ir_graph;
929 ir_node *base = addr->base;
930 ir_node *index = addr->index;
934 base = ia32_new_NoReg_gp(env_cg);
936 base = be_transform_node(base);
940 index = ia32_new_NoReg_gp(env_cg);
942 index = be_transform_node(index);
945 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
946 set_address(res, addr);
951 static int am_has_immediates(const ia32_address_t *addr)
953 return addr->offset != 0 || addr->symconst_ent != NULL
954 || addr->frame_entity || addr->use_frame;
958 * Creates an ia32 Add.
960 * @return the created ia32 Add node
962 static ir_node *gen_Add(ir_node *node) {
963 ir_graph *irg = current_ir_graph;
964 dbg_info *dbgi = get_irn_dbg_info(node);
965 ir_node *block = get_nodes_block(node);
966 ir_node *new_block = be_transform_node(block);
967 ir_node *op1 = get_Add_left(node);
968 ir_node *op2 = get_Add_right(node);
969 ir_mode *mode = get_irn_mode(node);
970 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
973 ir_node *add_immediate_op;
975 ia32_address_mode_t am;
977 if (mode_is_float(mode)) {
978 if (USE_SSE2(env_cg))
979 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
981 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
986 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
987 * 1. Add with immediate -> Lea
988 * 2. Add with possible source address mode -> Add
989 * 3. Otherwise -> Lea
991 memset(&addr, 0, sizeof(addr));
992 ia32_create_address_mode(&addr, node, 1);
993 add_immediate_op = NULL;
995 if(addr.base == NULL && addr.index == NULL) {
996 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
997 addr.symconst_sign, addr.offset);
998 add_irn_dep(new_node, get_irg_frame(irg));
999 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1002 /* add with immediate? */
1003 if(addr.index == NULL) {
1004 add_immediate_op = addr.base;
1005 } else if(addr.base == NULL && addr.scale == 0) {
1006 add_immediate_op = addr.index;
1009 if(add_immediate_op != NULL) {
1010 if(!am_has_immediates(&addr)) {
1011 #ifdef DEBUG_libfirm
1012 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1015 return be_transform_node(add_immediate_op);
1018 new_node = create_lea_from_address(dbgi, new_block, &addr);
1019 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1023 /* test if we can use source address mode */
1024 memset(&am, 0, sizeof(am));
1026 if(use_source_address_mode(block, op2, op1)) {
1027 build_address(&am, op2);
1028 new_op1 = be_transform_node(op1);
1029 } else if(use_source_address_mode(block, op1, op2)) {
1030 build_address(&am, op1);
1031 new_op1 = be_transform_node(op2);
1033 /* construct an Add with source address mode */
1034 if(new_op1 != NULL) {
1035 ia32_address_t *am_addr = &am.addr;
1036 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1037 am_addr->index, am_addr->mem, new_op1, noreg);
1038 set_address(new_node, am_addr);
1039 set_ia32_op_type(new_node, ia32_AddrModeS);
1040 set_ia32_ls_mode(new_node, am.ls_mode);
1041 set_ia32_commutative(new_node);
1042 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1044 new_node = fix_mem_proj(new_node, &am);
1049 /* otherwise construct a lea */
1050 new_node = create_lea_from_address(dbgi, new_block, &addr);
1051 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1056 * Creates an ia32 Mul.
1058 * @return the created ia32 Mul node
1060 static ir_node *gen_Mul(ir_node *node) {
1061 ir_node *op1 = get_Mul_left(node);
1062 ir_node *op2 = get_Mul_right(node);
1063 ir_mode *mode = get_irn_mode(node);
1065 if (mode_is_float(mode)) {
1066 if (USE_SSE2(env_cg))
1067 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1069 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1073 for the lower 32bit of the result it doesn't matter whether we use
1074 signed or unsigned multiplication so we use IMul as it has fewer
1077 return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative);
1081 * Creates an ia32 Mulh.
1082 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1083 * this result while Mul returns the lower 32 bit.
1085 * @return the created ia32 Mulh node
1087 static ir_node *gen_Mulh(ir_node *node) {
1088 ir_node *block = be_transform_node(get_nodes_block(node));
1089 ir_node *op1 = get_irn_n(node, 0);
1090 ir_node *new_op1 = be_transform_node(op1);
1091 ir_node *op2 = get_irn_n(node, 1);
1092 ir_node *new_op2 = be_transform_node(op2);
1093 ir_graph *irg = current_ir_graph;
1094 dbg_info *dbgi = get_irn_dbg_info(node);
1095 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1096 ir_mode *mode = get_irn_mode(node);
1097 ir_node *proj_EDX, *res;
1099 assert(!mode_is_float(mode) && "Mulh with float not supported");
1100 if (mode_is_signed(mode)) {
1101 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1104 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1108 set_ia32_commutative(res);
1110 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_IMul1OP_EDX);
1118 * Creates an ia32 And.
1120 * @return The created ia32 And node
1122 static ir_node *gen_And(ir_node *node) {
1123 ir_node *op1 = get_And_left(node);
1124 ir_node *op2 = get_And_right(node);
1125 assert(! mode_is_float(get_irn_mode(node)));
1127 /* is it a zero extension? */
1128 if (is_Const(op2)) {
1129 tarval *tv = get_Const_tarval(op2);
1130 long v = get_tarval_long(tv);
1132 if (v == 0xFF || v == 0xFFFF) {
1133 dbg_info *dbgi = get_irn_dbg_info(node);
1134 ir_node *block = get_nodes_block(node);
1141 assert(v == 0xFFFF);
1144 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1150 return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative);
1156 * Creates an ia32 Or.
1158 * @return The created ia32 Or node
1160 static ir_node *gen_Or(ir_node *node) {
1161 ir_node *op1 = get_Or_left(node);
1162 ir_node *op2 = get_Or_right(node);
1164 assert (! mode_is_float(get_irn_mode(node)));
1165 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative);
1171 * Creates an ia32 Eor.
1173 * @return The created ia32 Eor node
1175 static ir_node *gen_Eor(ir_node *node) {
1176 ir_node *op1 = get_Eor_left(node);
1177 ir_node *op2 = get_Eor_right(node);
1179 assert(! mode_is_float(get_irn_mode(node)));
1180 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative);
1185 * Creates an ia32 Sub.
1187 * @return The created ia32 Sub node
1189 static ir_node *gen_Sub(ir_node *node) {
1190 ir_node *op1 = get_Sub_left(node);
1191 ir_node *op2 = get_Sub_right(node);
1192 ir_mode *mode = get_irn_mode(node);
1194 if (mode_is_float(mode)) {
1195 if (USE_SSE2(env_cg))
1196 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1198 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1202 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1206 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1209 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1212 * Generates an ia32 DivMod with additional infrastructure for the
1213 * register allocator if needed.
1215 * @param dividend -no comment- :)
1216 * @param divisor -no comment- :)
1217 * @param dm_flav flavour_Div/Mod/DivMod
1218 * @return The created ia32 DivMod node
1220 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1221 ir_node *divisor, ia32_op_flavour_t dm_flav)
1223 ir_node *block = be_transform_node(get_nodes_block(node));
1224 ir_node *new_dividend = be_transform_node(dividend);
1225 ir_node *new_divisor = be_transform_node(divisor);
1226 ir_graph *irg = current_ir_graph;
1227 dbg_info *dbgi = get_irn_dbg_info(node);
1228 ir_mode *mode = get_irn_mode(node);
1229 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1230 ir_node *res, *proj_div, *proj_mod;
1231 ir_node *sign_extension;
1232 ir_node *mem, *new_mem;
1235 proj_div = proj_mod = NULL;
1239 mem = get_Div_mem(node);
1240 mode = get_Div_resmode(node);
1241 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1242 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1245 mem = get_Mod_mem(node);
1246 mode = get_Mod_resmode(node);
1247 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1248 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1250 case flavour_DivMod:
1251 mem = get_DivMod_mem(node);
1252 mode = get_DivMod_resmode(node);
1253 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1254 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1255 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1258 panic("invalid divmod flavour!");
1260 new_mem = be_transform_node(mem);
1262 if (mode_is_signed(mode)) {
1263 /* in signed mode, we need to sign extend the dividend */
1264 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1265 add_irn_dep(produceval, get_irg_frame(irg));
1266 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1269 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1270 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1271 add_irn_dep(sign_extension, get_irg_frame(irg));
1274 if (mode_is_signed(mode)) {
1275 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1276 new_dividend, sign_extension, new_divisor);
1278 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1279 new_dividend, sign_extension, new_divisor);
1282 set_ia32_exc_label(res, has_exc);
1283 set_irn_pinned(res, get_irn_pinned(node));
1285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1292 * Wrapper for generate_DivMod. Sets flavour_Mod.
1295 static ir_node *gen_Mod(ir_node *node) {
1296 return generate_DivMod(node, get_Mod_left(node),
1297 get_Mod_right(node), flavour_Mod);
1301 * Wrapper for generate_DivMod. Sets flavour_Div.
1304 static ir_node *gen_Div(ir_node *node) {
1305 return generate_DivMod(node, get_Div_left(node),
1306 get_Div_right(node), flavour_Div);
1310 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1312 static ir_node *gen_DivMod(ir_node *node) {
1313 return generate_DivMod(node, get_DivMod_left(node),
1314 get_DivMod_right(node), flavour_DivMod);
1320 * Creates an ia32 floating Div.
1322 * @return The created ia32 xDiv node
1324 static ir_node *gen_Quot(ir_node *node)
1326 ir_node *op1 = get_Quot_left(node);
1327 ir_node *op2 = get_Quot_right(node);
1329 if (USE_SSE2(env_cg)) {
1330 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1332 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1338 * Creates an ia32 Shl.
1340 * @return The created ia32 Shl node
1342 static ir_node *gen_Shl(ir_node *node) {
1343 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1350 * Creates an ia32 Shr.
1352 * @return The created ia32 Shr node
1354 static ir_node *gen_Shr(ir_node *node) {
1355 return gen_shift_binop(node, get_Shr_left(node),
1356 get_Shr_right(node), new_rd_ia32_Shr);
1362 * Creates an ia32 Sar.
1364 * @return The created ia32 Shrs node
1366 static ir_node *gen_Shrs(ir_node *node) {
1367 ir_node *left = get_Shrs_left(node);
1368 ir_node *right = get_Shrs_right(node);
1369 ir_mode *mode = get_irn_mode(node);
1370 if(is_Const(right) && mode == mode_Is) {
1371 tarval *tv = get_Const_tarval(right);
1372 long val = get_tarval_long(tv);
1374 /* this is a sign extension */
1375 ir_graph *irg = current_ir_graph;
1376 dbg_info *dbgi = get_irn_dbg_info(node);
1377 ir_node *block = be_transform_node(get_nodes_block(node));
1379 ir_node *new_op = be_transform_node(op);
1380 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1381 add_irn_dep(pval, get_irg_frame(irg));
1383 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1387 /* 8 or 16 bit sign extension? */
1388 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1389 ir_node *shl_left = get_Shl_left(left);
1390 ir_node *shl_right = get_Shl_right(left);
1391 if(is_Const(shl_right)) {
1392 tarval *tv1 = get_Const_tarval(right);
1393 tarval *tv2 = get_Const_tarval(shl_right);
1394 if(tv1 == tv2 && tarval_is_long(tv1)) {
1395 long val = get_tarval_long(tv1);
1396 if(val == 16 || val == 24) {
1397 dbg_info *dbgi = get_irn_dbg_info(node);
1398 ir_node *block = get_nodes_block(node);
1408 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1417 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1423 * Creates an ia32 RotL.
1425 * @param op1 The first operator
1426 * @param op2 The second operator
1427 * @return The created ia32 RotL node
1429 static ir_node *gen_RotL(ir_node *node,
1430 ir_node *op1, ir_node *op2) {
1431 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1437 * Creates an ia32 RotR.
1438 * NOTE: There is no RotR with immediate because this would always be a RotL
1439 * "imm-mode_size_bits" which can be pre-calculated.
1441 * @param op1 The first operator
1442 * @param op2 The second operator
1443 * @return The created ia32 RotR node
1445 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1447 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1453 * Creates an ia32 RotR or RotL (depending on the found pattern).
1455 * @return The created ia32 RotL or RotR node
1457 static ir_node *gen_Rot(ir_node *node) {
1458 ir_node *rotate = NULL;
1459 ir_node *op1 = get_Rot_left(node);
1460 ir_node *op2 = get_Rot_right(node);
1462 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1463 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1464 that means we can create a RotR instead of an Add and a RotL */
1466 if (get_irn_op(op2) == op_Add) {
1468 ir_node *left = get_Add_left(add);
1469 ir_node *right = get_Add_right(add);
1470 if (is_Const(right)) {
1471 tarval *tv = get_Const_tarval(right);
1472 ir_mode *mode = get_irn_mode(node);
1473 long bits = get_mode_size_bits(mode);
1475 if (get_irn_op(left) == op_Minus &&
1476 tarval_is_long(tv) &&
1477 get_tarval_long(tv) == bits)
1479 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1480 rotate = gen_RotR(node, op1, get_Minus_op(left));
1485 if (rotate == NULL) {
1486 rotate = gen_RotL(node, op1, op2);
1495 * Transforms a Minus node.
1497 * @return The created ia32 Minus node
1499 static ir_node *gen_Minus(ir_node *node)
1501 ir_node *op = get_Minus_op(node);
1502 ir_node *block = be_transform_node(get_nodes_block(node));
1503 ir_graph *irg = current_ir_graph;
1504 dbg_info *dbgi = get_irn_dbg_info(node);
1505 ir_mode *mode = get_irn_mode(node);
1510 if (mode_is_float(mode)) {
1511 ir_node *new_op = be_transform_node(op);
1512 if (USE_SSE2(env_cg)) {
1513 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1514 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1515 ir_node *nomem = new_rd_NoMem(irg);
1517 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1520 size = get_mode_size_bits(mode);
1521 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1523 set_ia32_am_sc(res, ent);
1524 set_ia32_op_type(res, ia32_AddrModeS);
1525 set_ia32_ls_mode(res, mode);
1527 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1530 res = gen_unop(node, op, new_rd_ia32_Neg);
1533 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1539 * Transforms a Not node.
1541 * @return The created ia32 Not node
1543 static ir_node *gen_Not(ir_node *node) {
1544 ir_node *op = get_Not_op(node);
1545 ir_mode *mode = get_irn_mode(node);
1547 assert(mode != mode_b); /* should be lowered already */
1549 assert (! mode_is_float(get_irn_mode(node)));
1550 return gen_unop(node, op, new_rd_ia32_Not);
1556 * Transforms an Abs node.
1558 * @return The created ia32 Abs node
1560 static ir_node *gen_Abs(ir_node *node)
1562 ir_node *block = be_transform_node(get_nodes_block(node));
1563 ir_node *op = get_Abs_op(node);
1564 ir_node *new_op = be_transform_node(op);
1565 ir_graph *irg = current_ir_graph;
1566 dbg_info *dbgi = get_irn_dbg_info(node);
1567 ir_mode *mode = get_irn_mode(node);
1568 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1569 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1570 ir_node *nomem = new_NoMem();
1575 if (mode_is_float(mode)) {
1576 if (USE_SSE2(env_cg)) {
1577 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1579 size = get_mode_size_bits(mode);
1580 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1582 set_ia32_am_sc(res, ent);
1584 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1586 set_ia32_op_type(res, ia32_AddrModeS);
1587 set_ia32_ls_mode(res, mode);
1589 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1594 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1595 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1598 add_irn_dep(pval, get_irg_frame(irg));
1599 SET_IA32_ORIG_NODE(sign_extension,
1600 ia32_get_old_node_name(env_cg, node));
1602 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1604 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1606 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1608 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1615 * Transforms a Load.
1617 * @return the created ia32 Load node
1619 static ir_node *gen_Load(ir_node *node) {
1620 ir_node *old_block = get_nodes_block(node);
1621 ir_node *block = be_transform_node(old_block);
1622 ir_node *ptr = get_Load_ptr(node);
1623 ir_node *mem = get_Load_mem(node);
1624 ir_node *new_mem = be_transform_node(mem);
1627 ir_graph *irg = current_ir_graph;
1628 dbg_info *dbgi = get_irn_dbg_info(node);
1629 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1630 ir_mode *mode = get_Load_mode(node);
1633 ia32_address_t addr;
1635 /* construct load address */
1636 memset(&addr, 0, sizeof(addr));
1637 ia32_create_address_mode(&addr, ptr, 0);
1644 base = be_transform_node(base);
1650 index = be_transform_node(index);
1653 if (mode_is_float(mode)) {
1654 if (USE_SSE2(env_cg)) {
1655 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1657 res_mode = mode_xmm;
1659 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1661 res_mode = mode_vfp;
1667 /* create a conv node with address mode for smaller modes */
1668 if(get_mode_size_bits(mode) < 32) {
1669 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1670 new_mem, noreg, mode);
1672 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1677 set_irn_pinned(new_op, get_irn_pinned(node));
1678 set_ia32_op_type(new_op, ia32_AddrModeS);
1679 set_ia32_ls_mode(new_op, mode);
1680 set_address(new_op, &addr);
1682 /* make sure we are scheduled behind the initial IncSP/Barrier
1683 * to avoid spills being placed before it
1685 if (block == get_irg_start_block(irg)) {
1686 add_irn_dep(new_op, get_irg_frame(irg));
1689 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1690 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1695 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1696 ir_node *ptr, ir_mode *mode, ir_node *other)
1703 /* we only use address mode if we're the only user of the load */
1704 if(get_irn_n_edges(node) > 1)
1707 load = get_Proj_pred(node);
1710 if(get_nodes_block(load) != block)
1713 /* Store should be attached to the load */
1714 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1716 /* store should have the same pointer as the load */
1717 if(get_Load_ptr(load) != ptr)
1720 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1721 if(other != NULL && get_nodes_block(other) == block
1722 && heights_reachable_in_block(heights, other, load))
1725 assert(get_Load_mode(load) == mode);
1730 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1731 ir_node *mem, ir_node *ptr, ir_mode *mode,
1732 construct_binop_dest_func *func,
1733 construct_binop_dest_func *func8bit,
1736 ir_node *src_block = get_nodes_block(node);
1738 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1739 ir_graph *irg = current_ir_graph;
1743 ia32_address_mode_t am;
1744 ia32_address_t *addr = &am.addr;
1745 memset(&am, 0, sizeof(am));
1747 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1748 build_address(&am, op1);
1749 new_op = create_immediate_or_transform(op2, 0);
1750 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1751 build_address(&am, op2);
1752 new_op = create_immediate_or_transform(op1, 0);
1757 if(addr->base == NULL)
1758 addr->base = noreg_gp;
1759 if(addr->index == NULL)
1760 addr->index = noreg_gp;
1761 if(addr->mem == NULL)
1762 addr->mem = new_NoMem();
1764 dbgi = get_irn_dbg_info(node);
1765 block = be_transform_node(src_block);
1766 if(get_mode_size_bits(mode) == 8) {
1767 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1770 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1773 set_address(new_node, addr);
1774 set_ia32_op_type(new_node, ia32_AddrModeD);
1775 set_ia32_ls_mode(new_node, mode);
1776 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1781 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1782 ir_node *ptr, ir_mode *mode,
1783 construct_unop_dest_func *func)
1785 ir_node *src_block = get_nodes_block(node);
1787 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1788 ir_graph *irg = current_ir_graph;
1791 ia32_address_mode_t am;
1792 ia32_address_t *addr = &am.addr;
1793 memset(&am, 0, sizeof(am));
1795 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1798 build_address(&am, op);
1800 if(addr->base == NULL)
1801 addr->base = noreg_gp;
1802 if(addr->index == NULL)
1803 addr->index = noreg_gp;
1804 if(addr->mem == NULL)
1805 addr->mem = new_NoMem();
1807 dbgi = get_irn_dbg_info(node);
1808 block = be_transform_node(src_block);
1809 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1810 set_address(new_node, addr);
1811 set_ia32_op_type(new_node, ia32_AddrModeD);
1812 set_ia32_ls_mode(new_node, mode);
1813 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1818 static ir_node *try_create_dest_am(ir_node *node) {
1819 ir_node *val = get_Store_value(node);
1820 ir_node *mem = get_Store_mem(node);
1821 ir_node *ptr = get_Store_ptr(node);
1822 ir_mode *mode = get_irn_mode(val);
1827 /* handle only GP modes for now... */
1828 if(!mode_needs_gp_reg(mode))
1831 /* store must be the only user of the val node */
1832 if(get_irn_n_edges(val) > 1)
1835 switch(get_irn_opcode(val)) {
1837 op1 = get_Add_left(val);
1838 op2 = get_Add_right(val);
1839 if(is_Const_1(op2)) {
1840 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1841 new_rd_ia32_IncMem);
1843 } else if(is_Const_Minus_1(op2)) {
1844 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1845 new_rd_ia32_DecMem);
1848 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1849 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1852 op1 = get_Sub_left(val);
1853 op2 = get_Sub_right(val);
1855 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1858 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1859 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1862 op1 = get_And_left(val);
1863 op2 = get_And_right(val);
1864 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1865 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1868 op1 = get_Or_left(val);
1869 op2 = get_Or_right(val);
1870 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1871 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1874 op1 = get_Eor_left(val);
1875 op2 = get_Eor_right(val);
1876 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1877 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1880 op1 = get_Shl_left(val);
1881 op2 = get_Shl_right(val);
1882 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1883 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1886 op1 = get_Shr_left(val);
1887 op2 = get_Shr_right(val);
1888 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1889 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1892 op1 = get_Shrs_left(val);
1893 op2 = get_Shrs_right(val);
1894 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1895 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1898 op1 = get_Rot_left(val);
1899 op2 = get_Rot_right(val);
1900 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1901 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1903 /* TODO: match ROR patterns... */
1905 op1 = get_Minus_op(val);
1906 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1909 /* should be lowered already */
1910 assert(mode != mode_b);
1911 op1 = get_Not_op(val);
1912 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1922 * Transforms a Store.
1924 * @return the created ia32 Store node
1926 static ir_node *gen_Store(ir_node *node) {
1927 ir_node *block = be_transform_node(get_nodes_block(node));
1928 ir_node *ptr = get_Store_ptr(node);
1931 ir_node *val = get_Store_value(node);
1933 ir_node *mem = get_Store_mem(node);
1934 ir_node *new_mem = be_transform_node(mem);
1935 ir_graph *irg = current_ir_graph;
1936 dbg_info *dbgi = get_irn_dbg_info(node);
1937 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1938 ir_mode *mode = get_irn_mode(val);
1940 ia32_address_t addr;
1942 /* check for destination address mode */
1943 new_op = try_create_dest_am(node);
1947 /* construct store address */
1948 memset(&addr, 0, sizeof(addr));
1949 ia32_create_address_mode(&addr, ptr, 0);
1956 base = be_transform_node(base);
1962 index = be_transform_node(index);
1965 if (mode_is_float(mode)) {
1966 new_val = be_transform_node(val);
1967 if (USE_SSE2(env_cg)) {
1968 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1971 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1975 new_val = create_immediate_or_transform(val, 0);
1979 if (get_mode_size_bits(mode) == 8) {
1980 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1983 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1988 set_irn_pinned(new_op, get_irn_pinned(node));
1989 set_ia32_op_type(new_op, ia32_AddrModeD);
1990 set_ia32_ls_mode(new_op, mode);
1992 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1993 set_address(new_op, &addr);
1994 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1999 static ir_node *create_Switch(ir_node *node)
2001 ir_graph *irg = current_ir_graph;
2002 dbg_info *dbgi = get_irn_dbg_info(node);
2003 ir_node *block = be_transform_node(get_nodes_block(node));
2004 ir_node *sel = get_Cond_selector(node);
2005 ir_node *new_sel = be_transform_node(sel);
2007 int switch_min = INT_MAX;
2008 const ir_edge_t *edge;
2010 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2012 /* determine the smallest switch case value */
2013 foreach_out_edge(node, edge) {
2014 ir_node *proj = get_edge_src_irn(edge);
2015 int pn = get_Proj_proj(proj);
2020 if (switch_min != 0) {
2021 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2023 /* if smallest switch case is not 0 we need an additional sub */
2024 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2025 add_ia32_am_offs_int(new_sel, -switch_min);
2026 set_ia32_op_type(new_sel, ia32_AddrModeS);
2028 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2031 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2032 set_ia32_pncode(res, get_Cond_defaultProj(node));
2034 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2039 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2041 ir_graph *irg = current_ir_graph;
2049 /* we have a Cmp as input */
2051 ir_node *pred = get_Proj_pred(node);
2053 flags = be_transform_node(pred);
2054 *pnc_out = get_Proj_proj(node);
2059 /* a mode_b value, we have to compare it against 0 */
2060 dbgi = get_irn_dbg_info(node);
2061 new_block = be_transform_node(get_nodes_block(node));
2062 new_op = be_transform_node(node);
2063 noreg = ia32_new_NoReg_gp(env_cg);
2064 nomem = new_NoMem();
2065 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2066 new_op, new_op, 0, 0);
2067 *pnc_out = pn_Cmp_Lg;
2071 static ir_node *gen_Cond(ir_node *node) {
2072 ir_node *block = get_nodes_block(node);
2073 ir_node *new_block = be_transform_node(block);
2074 ir_graph *irg = current_ir_graph;
2075 dbg_info *dbgi = get_irn_dbg_info(node);
2076 ir_node *sel = get_Cond_selector(node);
2077 ir_mode *sel_mode = get_irn_mode(sel);
2079 ir_node *flags = NULL;
2082 if (sel_mode != mode_b) {
2083 return create_Switch(node);
2086 /* we get flags from a cmp */
2087 flags = get_flags_node(sel, &pnc);
2089 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2090 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2098 * Transforms a CopyB node.
2100 * @return The transformed node.
2102 static ir_node *gen_CopyB(ir_node *node) {
2103 ir_node *block = be_transform_node(get_nodes_block(node));
2104 ir_node *src = get_CopyB_src(node);
2105 ir_node *new_src = be_transform_node(src);
2106 ir_node *dst = get_CopyB_dst(node);
2107 ir_node *new_dst = be_transform_node(dst);
2108 ir_node *mem = get_CopyB_mem(node);
2109 ir_node *new_mem = be_transform_node(mem);
2110 ir_node *res = NULL;
2111 ir_graph *irg = current_ir_graph;
2112 dbg_info *dbgi = get_irn_dbg_info(node);
2113 int size = get_type_size_bytes(get_CopyB_type(node));
2116 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2117 /* then we need the size explicitly in ECX. */
2118 if (size >= 32 * 4) {
2119 rem = size & 0x3; /* size % 4 */
2122 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2124 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2126 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2128 add_irn_dep(res, get_irg_frame(irg));
2130 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2131 /* we misuse the pncode field for the copyb size */
2132 set_ia32_pncode(res, rem);
2134 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2135 set_ia32_pncode(res, size);
2138 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2143 static ir_node *gen_be_Copy(ir_node *node)
2145 ir_node *result = be_duplicate_node(node);
2146 ir_mode *mode = get_irn_mode(result);
2148 if (mode_needs_gp_reg(mode)) {
2149 set_irn_mode(result, mode_Iu);
2156 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2157 * to fold an and into a test node
2159 static int can_fold_test_and(ir_node *node)
2161 const ir_edge_t *edge;
2163 /** we can only have eq and lg projs */
2164 foreach_out_edge(node, edge) {
2165 ir_node *proj = get_edge_src_irn(edge);
2166 pn_Cmp pnc = get_Proj_proj(proj);
2167 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2174 static ir_node *try_create_Test(ir_node *node)
2176 ir_graph *irg = current_ir_graph;
2177 dbg_info *dbgi = get_irn_dbg_info(node);
2178 ir_node *block = get_nodes_block(node);
2179 ir_node *new_block = be_transform_node(block);
2180 ir_node *cmp_left = get_Cmp_left(node);
2181 ir_node *cmp_right = get_Cmp_right(node);
2186 ia32_address_mode_t am;
2187 ia32_address_t *addr = &am.addr;
2190 /* can we use a test instruction? */
2191 if(!is_Const_0(cmp_right))
2194 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2195 can_fold_test_and(node)) {
2196 ir_node *and_left = get_And_left(cmp_left);
2197 ir_node *and_right = get_And_right(cmp_left);
2199 mode = get_irn_mode(and_left);
2203 mode = get_irn_mode(cmp_left);
2208 assert(get_mode_size_bits(mode) <= 32);
2210 match_arguments(&am, block, left, right, match_commutative |
2211 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2213 cmp_unsigned = !mode_is_signed(mode);
2214 if(get_mode_size_bits(mode) == 8) {
2215 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2216 addr->index, addr->mem, am.new_op1,
2217 am.new_op2, am.ins_permuted, cmp_unsigned);
2219 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2220 addr->mem, am.new_op1, am.new_op2,
2221 am.ins_permuted, cmp_unsigned);
2223 set_am_attributes(res, &am);
2224 assert(mode != NULL);
2225 set_ia32_ls_mode(res, mode);
2227 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2229 res = fix_mem_proj(res, &am);
2233 static ir_node *create_Fucom(ir_node *node)
2235 ir_graph *irg = current_ir_graph;
2236 dbg_info *dbgi = get_irn_dbg_info(node);
2237 ir_node *block = get_nodes_block(node);
2238 ir_node *new_block = be_transform_node(block);
2239 ir_node *left = get_Cmp_left(node);
2240 ir_node *new_left = be_transform_node(left);
2241 ir_node *right = get_Cmp_right(node);
2245 if(transform_config.use_fucomi) {
2246 new_right = be_transform_node(right);
2247 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2248 set_ia32_commutative(res);
2249 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2251 if(transform_config.use_ftst && is_Const_null(right)) {
2252 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2254 new_right = be_transform_node(right);
2255 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2259 set_ia32_commutative(res);
2261 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2263 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2264 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2270 static ir_node *create_Ucomi(ir_node *node)
2272 ir_graph *irg = current_ir_graph;
2273 dbg_info *dbgi = get_irn_dbg_info(node);
2274 ir_node *src_block = get_nodes_block(node);
2275 ir_node *new_block = be_transform_node(src_block);
2276 ir_node *left = get_Cmp_left(node);
2277 ir_node *right = get_Cmp_right(node);
2279 ia32_address_mode_t am;
2280 ia32_address_t *addr = &am.addr;
2282 match_arguments(&am, src_block, left, right, match_commutative);
2284 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2285 addr->mem, am.new_op1, am.new_op2,
2287 set_am_attributes(new_node, &am);
2289 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2291 new_node = fix_mem_proj(new_node, &am);
2296 static ir_node *gen_Cmp(ir_node *node)
2298 ir_graph *irg = current_ir_graph;
2299 dbg_info *dbgi = get_irn_dbg_info(node);
2300 ir_node *block = get_nodes_block(node);
2301 ir_node *new_block = be_transform_node(block);
2302 ir_node *left = get_Cmp_left(node);
2303 ir_node *right = get_Cmp_right(node);
2304 ir_mode *cmp_mode = get_irn_mode(left);
2306 ia32_address_mode_t am;
2307 ia32_address_t *addr = &am.addr;
2310 if(mode_is_float(cmp_mode)) {
2311 if (USE_SSE2(env_cg)) {
2312 return create_Ucomi(node);
2314 return create_Fucom(node);
2318 assert(mode_needs_gp_reg(cmp_mode));
2320 /* we prefer the Test instruction where possible except cases where
2321 * we can use SourceAM */
2322 if(!use_source_address_mode(block, left, right) &&
2323 !use_source_address_mode(block, right, left)) {
2324 res = try_create_Test(node);
2329 match_arguments(&am, block, left, right,
2330 match_commutative | match_8_bit_am | match_16_bit_am |
2331 match_am_and_immediates);
2333 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2334 if(get_mode_size_bits(cmp_mode) == 8) {
2335 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2336 addr->mem, am.new_op1, am.new_op2,
2337 am.ins_permuted, cmp_unsigned);
2339 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2340 addr->mem, am.new_op1, am.new_op2,
2341 am.ins_permuted, cmp_unsigned);
2343 set_am_attributes(res, &am);
2344 assert(cmp_mode != NULL);
2345 set_ia32_ls_mode(res, cmp_mode);
2347 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2349 res = fix_mem_proj(res, &am);
2354 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2356 ir_graph *irg = current_ir_graph;
2357 dbg_info *dbgi = get_irn_dbg_info(node);
2358 ir_node *block = get_nodes_block(node);
2359 ir_node *new_block = be_transform_node(block);
2360 ir_node *val_true = get_Psi_val(node, 0);
2361 ir_node *val_false = get_Psi_default(node);
2363 match_flags_t match_flags;
2364 ia32_address_mode_t am;
2365 ia32_address_t *addr;
2367 assert(transform_config.use_cmov);
2368 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2372 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2373 | match_force_32bit_op;
2375 match_arguments(&am, block, val_false, val_true, match_flags);
2377 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2378 addr->mem, am.new_op1, am.new_op2, new_flags,
2379 am.ins_permuted, pnc);
2380 set_am_attributes(new_node, &am);
2382 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2384 new_node = fix_mem_proj(new_node, &am);
2391 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2392 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2394 ir_graph *irg = current_ir_graph;
2395 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2396 ir_node *nomem = new_NoMem();
2399 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2400 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2401 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2402 nomem, res, mode_Bu);
2403 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2409 * Transforms a Psi node into CMov.
2411 * @return The transformed node.
2413 static ir_node *gen_Psi(ir_node *node)
2415 dbg_info *dbgi = get_irn_dbg_info(node);
2416 ir_node *block = get_nodes_block(node);
2417 ir_node *new_block = be_transform_node(block);
2418 ir_node *psi_true = get_Psi_val(node, 0);
2419 ir_node *psi_default = get_Psi_default(node);
2420 ir_node *cond = get_Psi_cond(node, 0);
2421 ir_node *flags = NULL;
2426 assert(get_Psi_n_conds(node) == 1);
2427 assert(get_irn_mode(cond) == mode_b);
2428 assert(mode_needs_gp_reg(get_irn_mode(node)));
2430 flags = get_flags_node(cond, &pnc);
2432 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2433 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2434 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2435 pnc = get_negated_pnc(pnc, cmp_mode);
2436 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2438 res = create_CMov(node, flags, pnc);
2445 * Create a conversion from x87 state register to general purpose.
2447 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2448 ir_node *block = be_transform_node(get_nodes_block(node));
2449 ir_node *op = get_Conv_op(node);
2450 ir_node *new_op = be_transform_node(op);
2451 ia32_code_gen_t *cg = env_cg;
2452 ir_graph *irg = current_ir_graph;
2453 dbg_info *dbgi = get_irn_dbg_info(node);
2454 ir_node *noreg = ia32_new_NoReg_gp(cg);
2455 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2456 ir_mode *mode = get_irn_mode(node);
2457 ir_node *fist, *load;
2460 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2461 new_NoMem(), new_op, trunc_mode);
2463 set_irn_pinned(fist, op_pin_state_floats);
2464 set_ia32_use_frame(fist);
2465 set_ia32_op_type(fist, ia32_AddrModeD);
2467 assert(get_mode_size_bits(mode) <= 32);
2468 /* exception we can only store signed 32 bit integers, so for unsigned
2469 we store a 64bit (signed) integer and load the lower bits */
2470 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2471 set_ia32_ls_mode(fist, mode_Ls);
2473 set_ia32_ls_mode(fist, mode_Is);
2475 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2478 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2480 set_irn_pinned(load, op_pin_state_floats);
2481 set_ia32_use_frame(load);
2482 set_ia32_op_type(load, ia32_AddrModeS);
2483 set_ia32_ls_mode(load, mode_Is);
2484 if(get_ia32_ls_mode(fist) == mode_Ls) {
2485 ia32_attr_t *attr = get_ia32_attr(load);
2486 attr->data.need_64bit_stackent = 1;
2488 ia32_attr_t *attr = get_ia32_attr(load);
2489 attr->data.need_32bit_stackent = 1;
2491 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2493 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2497 * Creates a x87 strict Conv by placing a Sore and a Load
2499 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2501 ir_node *block = get_nodes_block(node);
2502 ir_graph *irg = current_ir_graph;
2503 dbg_info *dbgi = get_irn_dbg_info(node);
2504 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2505 ir_node *nomem = new_NoMem();
2506 ir_node *frame = get_irg_frame(irg);
2507 ir_node *store, *load;
2510 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2512 set_ia32_use_frame(store);
2513 set_ia32_op_type(store, ia32_AddrModeD);
2514 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2516 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2518 set_ia32_use_frame(load);
2519 set_ia32_op_type(load, ia32_AddrModeS);
2520 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2522 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2526 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2528 ir_graph *irg = current_ir_graph;
2529 ir_node *start_block = get_irg_start_block(irg);
2530 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2531 symconst, symconst_sign, val);
2532 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2538 * Create a conversion from general purpose to x87 register
2540 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2541 ir_node *src_block = get_nodes_block(node);
2542 ir_node *block = be_transform_node(src_block);
2543 ir_graph *irg = current_ir_graph;
2544 dbg_info *dbgi = get_irn_dbg_info(node);
2545 ir_node *op = get_Conv_op(node);
2550 ir_mode *store_mode;
2556 /* fild can use source AM if the operand is a signed 32bit integer */
2557 if (src_mode == mode_Is) {
2558 ia32_address_mode_t am;
2560 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2561 if (am.op_type == ia32_AddrModeS) {
2562 ia32_address_t *addr = &am.addr;
2564 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2565 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2567 set_am_attributes(fild, &am);
2568 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2570 fix_mem_proj(fild, &am);
2574 new_op = am.new_op2;
2576 new_op = be_transform_node(op);
2579 noreg = ia32_new_NoReg_gp(env_cg);
2580 nomem = new_NoMem();
2581 mode = get_irn_mode(op);
2583 /* first convert to 32 bit signed if necessary */
2584 src_bits = get_mode_size_bits(src_mode);
2585 if (src_bits == 8) {
2586 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2588 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2590 } else if (src_bits < 32) {
2591 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2593 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2597 assert(get_mode_size_bits(mode) == 32);
2600 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2603 set_ia32_use_frame(store);
2604 set_ia32_op_type(store, ia32_AddrModeD);
2605 set_ia32_ls_mode(store, mode_Iu);
2607 /* exception for 32bit unsigned, do a 64bit spill+load */
2608 if(!mode_is_signed(mode)) {
2611 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2613 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2614 get_irg_frame(irg), noreg, nomem,
2617 set_ia32_use_frame(zero_store);
2618 set_ia32_op_type(zero_store, ia32_AddrModeD);
2619 add_ia32_am_offs_int(zero_store, 4);
2620 set_ia32_ls_mode(zero_store, mode_Iu);
2625 store = new_rd_Sync(dbgi, irg, block, 2, in);
2626 store_mode = mode_Ls;
2628 store_mode = mode_Is;
2632 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2634 set_ia32_use_frame(fild);
2635 set_ia32_op_type(fild, ia32_AddrModeS);
2636 set_ia32_ls_mode(fild, store_mode);
2638 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2644 * Crete a conversion from one integer mode into another one
2646 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2647 dbg_info *dbgi, ir_node *block, ir_node *op,
2650 ir_graph *irg = current_ir_graph;
2651 int src_bits = get_mode_size_bits(src_mode);
2652 int tgt_bits = get_mode_size_bits(tgt_mode);
2653 ir_node *new_block = be_transform_node(block);
2654 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2657 ir_mode *smaller_mode;
2659 ia32_address_mode_t am;
2660 ia32_address_t *addr = &am.addr;
2662 if (src_bits < tgt_bits) {
2663 smaller_mode = src_mode;
2664 smaller_bits = src_bits;
2666 smaller_mode = tgt_mode;
2667 smaller_bits = tgt_bits;
2670 memset(&am, 0, sizeof(am));
2671 if(use_source_address_mode(block, op, NULL)) {
2672 build_address(&am, op);
2674 am.op_type = ia32_AddrModeS;
2676 new_op = be_transform_node(op);
2677 am.op_type = ia32_Normal;
2679 if(addr->base == NULL)
2681 if(addr->index == NULL)
2682 addr->index = noreg;
2683 if(addr->mem == NULL)
2684 addr->mem = new_NoMem();
2686 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2687 if (smaller_bits == 8) {
2688 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2689 addr->index, addr->mem, new_op,
2692 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2693 addr->index, addr->mem, new_op,
2697 set_am_attributes(res, &am);
2698 set_ia32_ls_mode(res, smaller_mode);
2699 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2700 res = fix_mem_proj(res, &am);
2706 * Transforms a Conv node.
2708 * @return The created ia32 Conv node
2710 static ir_node *gen_Conv(ir_node *node) {
2711 ir_node *block = get_nodes_block(node);
2712 ir_node *new_block = be_transform_node(block);
2713 ir_node *op = get_Conv_op(node);
2714 ir_node *new_op = NULL;
2715 ir_graph *irg = current_ir_graph;
2716 dbg_info *dbgi = get_irn_dbg_info(node);
2717 ir_mode *src_mode = get_irn_mode(op);
2718 ir_mode *tgt_mode = get_irn_mode(node);
2719 int src_bits = get_mode_size_bits(src_mode);
2720 int tgt_bits = get_mode_size_bits(tgt_mode);
2721 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2722 ir_node *nomem = new_rd_NoMem(irg);
2723 ir_node *res = NULL;
2725 if (src_mode == mode_b) {
2726 assert(mode_is_int(tgt_mode));
2727 /* nothing to do, we already model bools as 0/1 ints */
2728 return be_transform_node(op);
2731 if (src_mode == tgt_mode) {
2732 if (get_Conv_strict(node)) {
2733 if (USE_SSE2(env_cg)) {
2734 /* when we are in SSE mode, we can kill all strict no-op conversion */
2735 return be_transform_node(op);
2738 /* this should be optimized already, but who knows... */
2739 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2740 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2741 return be_transform_node(op);
2745 if (mode_is_float(src_mode)) {
2746 new_op = be_transform_node(op);
2747 /* we convert from float ... */
2748 if (mode_is_float(tgt_mode)) {
2749 if(src_mode == mode_E && tgt_mode == mode_D
2750 && !get_Conv_strict(node)) {
2751 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2756 if (USE_SSE2(env_cg)) {
2757 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2758 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2760 set_ia32_ls_mode(res, tgt_mode);
2762 if(get_Conv_strict(node)) {
2763 res = gen_x87_strict_conv(tgt_mode, new_op);
2764 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2767 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2772 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2773 if (USE_SSE2(env_cg)) {
2774 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2776 set_ia32_ls_mode(res, src_mode);
2778 return gen_x87_fp_to_gp(node);
2782 /* we convert from int ... */
2783 if (mode_is_float(tgt_mode)) {
2785 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2786 if (USE_SSE2(env_cg)) {
2787 new_op = be_transform_node(op);
2788 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2790 set_ia32_ls_mode(res, tgt_mode);
2792 res = gen_x87_gp_to_fp(node, src_mode);
2793 if(get_Conv_strict(node)) {
2794 res = gen_x87_strict_conv(tgt_mode, res);
2795 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2796 ia32_get_old_node_name(env_cg, node));
2800 } else if(tgt_mode == mode_b) {
2801 /* mode_b lowering already took care that we only have 0/1 values */
2802 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2803 src_mode, tgt_mode));
2804 return be_transform_node(op);
2807 if (src_bits == tgt_bits) {
2808 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2809 src_mode, tgt_mode));
2810 return be_transform_node(op);
2813 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2821 static int check_immediate_constraint(long val, char immediate_constraint_type)
2823 switch (immediate_constraint_type) {
2827 return val >= 0 && val <= 32;
2829 return val >= 0 && val <= 63;
2831 return val >= -128 && val <= 127;
2833 return val == 0xff || val == 0xffff;
2835 return val >= 0 && val <= 3;
2837 return val >= 0 && val <= 255;
2839 return val >= 0 && val <= 127;
2843 panic("Invalid immediate constraint found");
2847 static ir_node *try_create_Immediate(ir_node *node,
2848 char immediate_constraint_type)
2851 tarval *offset = NULL;
2852 int offset_sign = 0;
2854 ir_entity *symconst_ent = NULL;
2855 int symconst_sign = 0;
2857 ir_node *cnst = NULL;
2858 ir_node *symconst = NULL;
2861 mode = get_irn_mode(node);
2862 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2866 if(is_Minus(node)) {
2868 node = get_Minus_op(node);
2871 if(is_Const(node)) {
2874 offset_sign = minus;
2875 } else if(is_SymConst(node)) {
2878 symconst_sign = minus;
2879 } else if(is_Add(node)) {
2880 ir_node *left = get_Add_left(node);
2881 ir_node *right = get_Add_right(node);
2882 if(is_Const(left) && is_SymConst(right)) {
2885 symconst_sign = minus;
2886 offset_sign = minus;
2887 } else if(is_SymConst(left) && is_Const(right)) {
2890 symconst_sign = minus;
2891 offset_sign = minus;
2893 } else if(is_Sub(node)) {
2894 ir_node *left = get_Sub_left(node);
2895 ir_node *right = get_Sub_right(node);
2896 if(is_Const(left) && is_SymConst(right)) {
2899 symconst_sign = !minus;
2900 offset_sign = minus;
2901 } else if(is_SymConst(left) && is_Const(right)) {
2904 symconst_sign = minus;
2905 offset_sign = !minus;
2912 offset = get_Const_tarval(cnst);
2913 if(tarval_is_long(offset)) {
2914 val = get_tarval_long(offset);
2916 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2921 if(!check_immediate_constraint(val, immediate_constraint_type))
2924 if(symconst != NULL) {
2925 if(immediate_constraint_type != 0) {
2926 /* we need full 32bits for symconsts */
2930 /* unfortunately the assembler/linker doesn't support -symconst */
2934 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2936 symconst_ent = get_SymConst_entity(symconst);
2938 if(cnst == NULL && symconst == NULL)
2941 if(offset_sign && offset != NULL) {
2942 offset = tarval_neg(offset);
2945 res = create_Immediate(symconst_ent, symconst_sign, val);
2950 static ir_node *create_immediate_or_transform(ir_node *node,
2951 char immediate_constraint_type)
2953 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2954 if (new_node == NULL) {
2955 new_node = be_transform_node(node);
2960 static const arch_register_req_t no_register_req = {
2961 arch_register_req_type_none,
2962 NULL, /* regclass */
2963 NULL, /* limit bitset */
2964 { -1, -1 }, /* same pos */
2965 -1 /* different pos */
2968 typedef struct constraint_t constraint_t;
2969 struct constraint_t {
2972 const arch_register_req_t **out_reqs;
2974 const arch_register_req_t *req;
2975 unsigned immediate_possible;
2976 char immediate_type;
2979 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2981 int immediate_possible = 0;
2982 char immediate_type = 0;
2983 unsigned limited = 0;
2984 const arch_register_class_t *cls = NULL;
2985 ir_graph *irg = current_ir_graph;
2986 struct obstack *obst = get_irg_obstack(irg);
2987 arch_register_req_t *req;
2988 unsigned *limited_ptr;
2992 /* TODO: replace all the asserts with nice error messages */
2995 /* a memory constraint: no need to do anything in backend about it
2996 * (the dependencies are already respected by the memory edge of
2998 constraint->req = &no_register_req;
3010 assert(cls == NULL ||
3011 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3012 cls = &ia32_reg_classes[CLASS_ia32_gp];
3013 limited |= 1 << REG_EAX;
3016 assert(cls == NULL ||
3017 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3018 cls = &ia32_reg_classes[CLASS_ia32_gp];
3019 limited |= 1 << REG_EBX;
3022 assert(cls == NULL ||
3023 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3024 cls = &ia32_reg_classes[CLASS_ia32_gp];
3025 limited |= 1 << REG_ECX;
3028 assert(cls == NULL ||
3029 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3030 cls = &ia32_reg_classes[CLASS_ia32_gp];
3031 limited |= 1 << REG_EDX;
3034 assert(cls == NULL ||
3035 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3036 cls = &ia32_reg_classes[CLASS_ia32_gp];
3037 limited |= 1 << REG_EDI;
3040 assert(cls == NULL ||
3041 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3042 cls = &ia32_reg_classes[CLASS_ia32_gp];
3043 limited |= 1 << REG_ESI;
3046 case 'q': /* q means lower part of the regs only, this makes no
3047 * difference to Q for us (we only assigne whole registers) */
3048 assert(cls == NULL ||
3049 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3050 cls = &ia32_reg_classes[CLASS_ia32_gp];
3051 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3055 assert(cls == NULL ||
3056 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3057 cls = &ia32_reg_classes[CLASS_ia32_gp];
3058 limited |= 1 << REG_EAX | 1 << REG_EDX;
3061 assert(cls == NULL ||
3062 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3063 cls = &ia32_reg_classes[CLASS_ia32_gp];
3064 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3065 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3072 assert(cls == NULL);
3073 cls = &ia32_reg_classes[CLASS_ia32_gp];
3079 /* TODO: mark values so the x87 simulator knows about t and u */
3080 assert(cls == NULL);
3081 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3086 assert(cls == NULL);
3087 /* TODO: check that sse2 is supported */
3088 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3098 assert(!immediate_possible);
3099 immediate_possible = 1;
3100 immediate_type = *c;
3104 assert(!immediate_possible);
3105 immediate_possible = 1;
3109 assert(!immediate_possible && cls == NULL);
3110 immediate_possible = 1;
3111 cls = &ia32_reg_classes[CLASS_ia32_gp];
3124 assert(constraint->is_in && "can only specify same constraint "
3127 sscanf(c, "%d%n", &same_as, &p);
3135 /* memory constraint no need to do anything in backend about it
3136 * (the dependencies are already respected by the memory edge of
3138 constraint->req = &no_register_req;
3141 case 'E': /* no float consts yet */
3142 case 'F': /* no float consts yet */
3143 case 's': /* makes no sense on x86 */
3144 case 'X': /* we can't support that in firm */
3147 case '<': /* no autodecrement on x86 */
3148 case '>': /* no autoincrement on x86 */
3149 case 'C': /* sse constant not supported yet */
3150 case 'G': /* 80387 constant not supported yet */
3151 case 'y': /* we don't support mmx registers yet */
3152 case 'Z': /* not available in 32 bit mode */
3153 case 'e': /* not available in 32 bit mode */
3154 panic("unsupported asm constraint '%c' found in (%+F)",
3155 *c, current_ir_graph);
3158 panic("unknown asm constraint '%c' found in (%+F)", *c,
3166 const arch_register_req_t *other_constr;
3168 assert(cls == NULL && "same as and register constraint not supported");
3169 assert(!immediate_possible && "same as and immediate constraint not "
3171 assert(same_as < constraint->n_outs && "wrong constraint number in "
3172 "same_as constraint");
3174 other_constr = constraint->out_reqs[same_as];
3176 req = obstack_alloc(obst, sizeof(req[0]));
3177 req->cls = other_constr->cls;
3178 req->type = arch_register_req_type_should_be_same;
3179 req->limited = NULL;
3180 req->other_same[0] = pos;
3181 req->other_same[1] = -1;
3182 req->other_different = -1;
3184 /* switch constraints. This is because in firm we have same_as
3185 * constraints on the output constraints while in the gcc asm syntax
3186 * they are specified on the input constraints */
3187 constraint->req = other_constr;
3188 constraint->out_reqs[same_as] = req;
3189 constraint->immediate_possible = 0;
3193 if(immediate_possible && cls == NULL) {
3194 cls = &ia32_reg_classes[CLASS_ia32_gp];
3196 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3197 assert(cls != NULL);
3199 if(immediate_possible) {
3200 assert(constraint->is_in
3201 && "imeediates make no sense for output constraints");
3203 /* todo: check types (no float input on 'r' constrained in and such... */
3206 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3207 limited_ptr = (unsigned*) (req+1);
3209 req = obstack_alloc(obst, sizeof(req[0]));
3211 memset(req, 0, sizeof(req[0]));
3214 req->type = arch_register_req_type_limited;
3215 *limited_ptr = limited;
3216 req->limited = limited_ptr;
3218 req->type = arch_register_req_type_normal;
3222 constraint->req = req;
3223 constraint->immediate_possible = immediate_possible;
3224 constraint->immediate_type = immediate_type;
3227 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3234 panic("Clobbers not supported yet");
3237 static int is_memory_op(const ir_asm_constraint *constraint)
3239 ident *id = constraint->constraint;
3240 const char *str = get_id_str(id);
3243 for(c = str; *c != '\0'; ++c) {
3252 * generates code for a ASM node
3254 static ir_node *gen_ASM(ir_node *node)
3257 ir_graph *irg = current_ir_graph;
3258 ir_node *block = get_nodes_block(node);
3259 ir_node *new_block = be_transform_node(block);
3260 dbg_info *dbgi = get_irn_dbg_info(node);
3264 int n_out_constraints;
3266 const arch_register_req_t **out_reg_reqs;
3267 const arch_register_req_t **in_reg_reqs;
3268 ia32_asm_reg_t *register_map;
3269 unsigned reg_map_size = 0;
3270 struct obstack *obst;
3271 const ir_asm_constraint *in_constraints;
3272 const ir_asm_constraint *out_constraints;
3274 constraint_t parsed_constraint;
3276 arity = get_irn_arity(node);
3277 in = alloca(arity * sizeof(in[0]));
3278 memset(in, 0, arity * sizeof(in[0]));
3280 n_out_constraints = get_ASM_n_output_constraints(node);
3281 n_clobbers = get_ASM_n_clobbers(node);
3282 out_arity = n_out_constraints + n_clobbers;
3284 in_constraints = get_ASM_input_constraints(node);
3285 out_constraints = get_ASM_output_constraints(node);
3286 clobbers = get_ASM_clobbers(node);
3288 /* construct output constraints */
3289 obst = get_irg_obstack(irg);
3290 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3291 parsed_constraint.out_reqs = out_reg_reqs;
3292 parsed_constraint.n_outs = n_out_constraints;
3293 parsed_constraint.is_in = 0;
3295 for(i = 0; i < out_arity; ++i) {
3298 if(i < n_out_constraints) {
3299 const ir_asm_constraint *constraint = &out_constraints[i];
3300 c = get_id_str(constraint->constraint);
3301 parse_asm_constraint(i, &parsed_constraint, c);
3303 if(constraint->pos > reg_map_size)
3304 reg_map_size = constraint->pos;
3306 ident *glob_id = clobbers [i - n_out_constraints];
3307 c = get_id_str(glob_id);
3308 parse_clobber(node, i, &parsed_constraint, c);
3311 out_reg_reqs[i] = parsed_constraint.req;
3314 /* construct input constraints */
3315 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3316 parsed_constraint.is_in = 1;
3317 for(i = 0; i < arity; ++i) {
3318 const ir_asm_constraint *constraint = &in_constraints[i];
3319 ident *constr_id = constraint->constraint;
3320 const char *c = get_id_str(constr_id);
3322 parse_asm_constraint(i, &parsed_constraint, c);
3323 in_reg_reqs[i] = parsed_constraint.req;
3325 if(constraint->pos > reg_map_size)
3326 reg_map_size = constraint->pos;
3328 if(parsed_constraint.immediate_possible) {
3329 ir_node *pred = get_irn_n(node, i);
3330 char imm_type = parsed_constraint.immediate_type;
3331 ir_node *immediate = try_create_Immediate(pred, imm_type);
3333 if(immediate != NULL) {
3340 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3341 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3343 for(i = 0; i < n_out_constraints; ++i) {
3344 const ir_asm_constraint *constraint = &out_constraints[i];
3345 unsigned pos = constraint->pos;
3347 assert(pos < reg_map_size);
3348 register_map[pos].use_input = 0;
3349 register_map[pos].valid = 1;
3350 register_map[pos].memory = is_memory_op(constraint);
3351 register_map[pos].inout_pos = i;
3352 register_map[pos].mode = constraint->mode;
3355 /* transform inputs */
3356 for(i = 0; i < arity; ++i) {
3357 const ir_asm_constraint *constraint = &in_constraints[i];
3358 unsigned pos = constraint->pos;
3359 ir_node *pred = get_irn_n(node, i);
3360 ir_node *transformed;
3362 assert(pos < reg_map_size);
3363 register_map[pos].use_input = 1;
3364 register_map[pos].valid = 1;
3365 register_map[pos].memory = is_memory_op(constraint);
3366 register_map[pos].inout_pos = i;
3367 register_map[pos].mode = constraint->mode;
3372 transformed = be_transform_node(pred);
3373 in[i] = transformed;
3376 res = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3377 get_ASM_text(node), register_map);
3379 set_ia32_out_req_all(res, out_reg_reqs);
3380 set_ia32_in_req_all(res, in_reg_reqs);
3382 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3387 /********************************************
3390 * | |__ ___ _ __ ___ __| | ___ ___
3391 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3392 * | |_) | __/ | | | (_) | (_| | __/\__ \
3393 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3395 ********************************************/
3398 * Transforms a FrameAddr into an ia32 Add.
3400 static ir_node *gen_be_FrameAddr(ir_node *node) {
3401 ir_node *block = be_transform_node(get_nodes_block(node));
3402 ir_node *op = be_get_FrameAddr_frame(node);
3403 ir_node *new_op = be_transform_node(op);
3404 ir_graph *irg = current_ir_graph;
3405 dbg_info *dbgi = get_irn_dbg_info(node);
3406 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3409 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3410 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3411 set_ia32_use_frame(res);
3413 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3419 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3421 static ir_node *gen_be_Return(ir_node *node) {
3422 ir_graph *irg = current_ir_graph;
3423 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3424 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3425 ir_entity *ent = get_irg_entity(irg);
3426 ir_type *tp = get_entity_type(ent);
3431 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3432 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3435 int pn_ret_val, pn_ret_mem, arity, i;
3437 assert(ret_val != NULL);
3438 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3439 return be_duplicate_node(node);
3442 res_type = get_method_res_type(tp, 0);
3444 if (! is_Primitive_type(res_type)) {
3445 return be_duplicate_node(node);
3448 mode = get_type_mode(res_type);
3449 if (! mode_is_float(mode)) {
3450 return be_duplicate_node(node);
3453 assert(get_method_n_ress(tp) == 1);
3455 pn_ret_val = get_Proj_proj(ret_val);
3456 pn_ret_mem = get_Proj_proj(ret_mem);
3458 /* get the Barrier */
3459 barrier = get_Proj_pred(ret_val);
3461 /* get result input of the Barrier */
3462 ret_val = get_irn_n(barrier, pn_ret_val);
3463 new_ret_val = be_transform_node(ret_val);
3465 /* get memory input of the Barrier */
3466 ret_mem = get_irn_n(barrier, pn_ret_mem);
3467 new_ret_mem = be_transform_node(ret_mem);
3469 frame = get_irg_frame(irg);
3471 dbgi = get_irn_dbg_info(barrier);
3472 block = be_transform_node(get_nodes_block(barrier));
3474 noreg = ia32_new_NoReg_gp(env_cg);
3476 /* store xmm0 onto stack */
3477 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3478 new_ret_mem, new_ret_val);
3479 set_ia32_ls_mode(sse_store, mode);
3480 set_ia32_op_type(sse_store, ia32_AddrModeD);
3481 set_ia32_use_frame(sse_store);
3483 /* load into x87 register */
3484 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3485 set_ia32_op_type(fld, ia32_AddrModeS);
3486 set_ia32_use_frame(fld);
3488 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3489 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3491 /* create a new barrier */
3492 arity = get_irn_arity(barrier);
3493 in = alloca(arity * sizeof(in[0]));
3494 for (i = 0; i < arity; ++i) {
3497 if (i == pn_ret_val) {
3499 } else if (i == pn_ret_mem) {
3502 ir_node *in = get_irn_n(barrier, i);
3503 new_in = be_transform_node(in);
3508 new_barrier = new_ir_node(dbgi, irg, block,
3509 get_irn_op(barrier), get_irn_mode(barrier),
3511 copy_node_attr(barrier, new_barrier);
3512 be_duplicate_deps(barrier, new_barrier);
3513 be_set_transformed_node(barrier, new_barrier);
3514 mark_irn_visited(barrier);
3516 /* transform normally */
3517 return be_duplicate_node(node);
3521 * Transform a be_AddSP into an ia32_SubSP.
3523 static ir_node *gen_be_AddSP(ir_node *node)
3525 ir_node *src_block = get_nodes_block(node);
3526 ir_node *new_block = be_transform_node(src_block);
3527 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3528 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3529 ir_graph *irg = current_ir_graph;
3530 dbg_info *dbgi = get_irn_dbg_info(node);
3532 ia32_address_mode_t am;
3533 ia32_address_t *addr = &am.addr;
3534 match_flags_t flags = 0;
3536 match_arguments(&am, src_block, sp, sz, flags);
3538 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3539 addr->mem, am.new_op1, am.new_op2);
3540 set_am_attributes(new_node, &am);
3541 /* we can't use source address mode anymore when using immediates */
3542 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3543 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3544 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3546 new_node = fix_mem_proj(new_node, &am);
3552 * Transform a be_SubSP into an ia32_AddSP
3554 static ir_node *gen_be_SubSP(ir_node *node)
3556 ir_node *src_block = get_nodes_block(node);
3557 ir_node *new_block = be_transform_node(src_block);
3558 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3559 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3560 ir_graph *irg = current_ir_graph;
3561 dbg_info *dbgi = get_irn_dbg_info(node);
3563 ia32_address_mode_t am;
3564 ia32_address_t *addr = &am.addr;
3565 match_flags_t flags = 0;
3567 match_arguments(&am, src_block, sp, sz, flags);
3569 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3570 addr->mem, am.new_op1, am.new_op2);
3571 set_am_attributes(new_node, &am);
3572 /* we can't use source address mode anymore when using immediates */
3573 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3574 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3575 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3577 new_node = fix_mem_proj(new_node, &am);
3583 * This function just sets the register for the Unknown node
3584 * as this is not done during register allocation because Unknown
3585 * is an "ignore" node.
3587 static ir_node *gen_Unknown(ir_node *node) {
3588 ir_mode *mode = get_irn_mode(node);
3590 if (mode_is_float(mode)) {
3591 if (USE_SSE2(env_cg)) {
3592 return ia32_new_Unknown_xmm(env_cg);
3594 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3595 ir_graph *irg = current_ir_graph;
3596 dbg_info *dbgi = get_irn_dbg_info(node);
3597 ir_node *block = get_irg_start_block(irg);
3598 return new_rd_ia32_vfldz(dbgi, irg, block);
3600 } else if (mode_needs_gp_reg(mode)) {
3601 return ia32_new_Unknown_gp(env_cg);
3603 assert(0 && "unsupported Unknown-Mode");
3610 * Change some phi modes
3612 static ir_node *gen_Phi(ir_node *node) {
3613 ir_node *block = be_transform_node(get_nodes_block(node));
3614 ir_graph *irg = current_ir_graph;
3615 dbg_info *dbgi = get_irn_dbg_info(node);
3616 ir_mode *mode = get_irn_mode(node);
3619 if(mode_needs_gp_reg(mode)) {
3620 /* we shouldn't have any 64bit stuff around anymore */
3621 assert(get_mode_size_bits(mode) <= 32);
3622 /* all integer operations are on 32bit registers now */
3624 } else if(mode_is_float(mode)) {
3625 if (USE_SSE2(env_cg)) {
3632 /* phi nodes allow loops, so we use the old arguments for now
3633 * and fix this later */
3634 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3635 get_irn_in(node) + 1);
3636 copy_node_attr(node, phi);
3637 be_duplicate_deps(node, phi);
3639 be_set_transformed_node(node, phi);
3640 be_enqueue_preds(node);
3648 static ir_node *gen_IJmp(ir_node *node) {
3649 /* TODO: support AM */
3650 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3654 /**********************************************************************
3657 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3658 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3659 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3660 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3662 **********************************************************************/
3664 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3666 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3669 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3670 ir_node *val, ir_node *mem);
3673 * Transforms a lowered Load into a "real" one.
3675 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3677 ir_node *block = be_transform_node(get_nodes_block(node));
3678 ir_node *ptr = get_irn_n(node, 0);
3679 ir_node *new_ptr = be_transform_node(ptr);
3680 ir_node *mem = get_irn_n(node, 1);
3681 ir_node *new_mem = be_transform_node(mem);
3682 ir_graph *irg = current_ir_graph;
3683 dbg_info *dbgi = get_irn_dbg_info(node);
3684 ir_mode *mode = get_ia32_ls_mode(node);
3685 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3688 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3690 set_ia32_op_type(new_op, ia32_AddrModeS);
3691 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3692 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3693 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3694 if (is_ia32_am_sc_sign(node))
3695 set_ia32_am_sc_sign(new_op);
3696 set_ia32_ls_mode(new_op, mode);
3697 if (is_ia32_use_frame(node)) {
3698 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3699 set_ia32_use_frame(new_op);
3702 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3708 * Transforms a lowered Store into a "real" one.
3710 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3712 ir_node *block = be_transform_node(get_nodes_block(node));
3713 ir_node *ptr = get_irn_n(node, 0);
3714 ir_node *new_ptr = be_transform_node(ptr);
3715 ir_node *val = get_irn_n(node, 1);
3716 ir_node *new_val = be_transform_node(val);
3717 ir_node *mem = get_irn_n(node, 2);
3718 ir_node *new_mem = be_transform_node(mem);
3719 ir_graph *irg = current_ir_graph;
3720 dbg_info *dbgi = get_irn_dbg_info(node);
3721 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3722 ir_mode *mode = get_ia32_ls_mode(node);
3726 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3728 am_offs = get_ia32_am_offs_int(node);
3729 add_ia32_am_offs_int(new_op, am_offs);
3731 set_ia32_op_type(new_op, ia32_AddrModeD);
3732 set_ia32_ls_mode(new_op, mode);
3733 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3734 set_ia32_use_frame(new_op);
3736 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3743 * Transforms an ia32_l_XXX into a "real" XXX node
3745 * @param node The node to transform
3746 * @return the created ia32 XXX node
3748 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3749 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3750 return gen_shift_binop(node, get_irn_n(node, 0), \
3751 get_irn_n(node, 1), new_rd_ia32_##op); \
3754 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3755 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3756 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3758 static ir_node *gen_ia32_l_Add(ir_node *node) {
3759 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3760 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3761 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3763 if(is_Proj(lowered)) {
3764 lowered = get_Proj_pred(lowered);
3766 assert(is_ia32_Add(lowered));
3767 set_irn_mode(lowered, mode_T);
3773 static ir_node *gen_ia32_l_Adc(ir_node *node)
3775 return gen_binop_flags(node, new_rd_ia32_Adc, match_commutative);
3779 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3781 * @param node The node to transform
3782 * @return the created ia32 Neg node
3784 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3785 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3789 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3791 * @param node The node to transform
3792 * @return the created ia32 vfild node
3794 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3795 return gen_lowered_Load(node, new_rd_ia32_vfild);
3799 * Transforms an ia32_l_Load into a "real" ia32_Load node
3801 * @param node The node to transform
3802 * @return the created ia32 Load node
3804 static ir_node *gen_ia32_l_Load(ir_node *node) {
3805 return gen_lowered_Load(node, new_rd_ia32_Load);
3809 * Transforms an ia32_l_Store into a "real" ia32_Store node
3811 * @param node The node to transform
3812 * @return the created ia32 Store node
3814 static ir_node *gen_ia32_l_Store(ir_node *node) {
3815 return gen_lowered_Store(node, new_rd_ia32_Store);
3819 * Transforms a l_vfist into a "real" vfist node.
3821 * @param node The node to transform
3822 * @return the created ia32 vfist node
3824 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3825 ir_node *block = be_transform_node(get_nodes_block(node));
3826 ir_node *ptr = get_irn_n(node, 0);
3827 ir_node *new_ptr = be_transform_node(ptr);
3828 ir_node *val = get_irn_n(node, 1);
3829 ir_node *new_val = be_transform_node(val);
3830 ir_node *mem = get_irn_n(node, 2);
3831 ir_node *new_mem = be_transform_node(mem);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3835 ir_mode *mode = get_ia32_ls_mode(node);
3836 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3840 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3841 new_val, trunc_mode);
3843 am_offs = get_ia32_am_offs_int(node);
3844 add_ia32_am_offs_int(new_op, am_offs);
3846 set_ia32_op_type(new_op, ia32_AddrModeD);
3847 set_ia32_ls_mode(new_op, mode);
3848 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3849 set_ia32_use_frame(new_op);
3851 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3857 * Transforms a l_MulS into a "real" MulS node.
3859 * @return the created ia32 Mul node
3861 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3862 ir_node *left = get_binop_left(node);
3863 ir_node *right = get_binop_right(node);
3865 return gen_binop(node, left, right, new_rd_ia32_Mul,
3866 match_commutative | match_no_immediate);
3870 * Transforms a l_IMulS into a "real" IMul1OPS node.
3872 * @return the created ia32 IMul1OP node
3874 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3875 ir_node *left = get_binop_left(node);
3876 ir_node *right = get_binop_right(node);
3878 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
3879 match_commutative | match_no_immediate);
3882 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3883 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3884 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3885 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3887 if(is_Proj(lowered)) {
3888 lowered = get_Proj_pred(lowered);
3890 assert(is_ia32_Sub(lowered));
3891 set_irn_mode(lowered, mode_T);
3897 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3898 return gen_binop_flags(node, new_rd_ia32_Sbb, 0);
3902 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3903 * op1 - target to be shifted
3904 * op2 - contains bits to be shifted into target
3906 * Only op3 can be an immediate.
3908 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3909 ir_node *op2, ir_node *count)
3911 ir_node *block = be_transform_node(get_nodes_block(node));
3912 ir_node *new_op = NULL;
3913 ir_graph *irg = current_ir_graph;
3914 dbg_info *dbgi = get_irn_dbg_info(node);
3915 ir_node *new_op1 = be_transform_node(op1);
3916 ir_node *new_op2 = be_transform_node(op2);
3917 ir_node *new_count = create_immediate_or_transform(count, 'I');
3919 /* TODO proper AM support */
3921 if (is_ia32_l_ShlD(node))
3922 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3924 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3926 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3931 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3932 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3933 get_irn_n(node, 1), get_irn_n(node, 2));
3936 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3937 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3938 get_irn_n(node, 1), get_irn_n(node, 2));
3942 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3944 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3945 ir_node *block = be_transform_node(get_nodes_block(node));
3946 ir_node *val = get_irn_n(node, 1);
3947 ir_node *new_val = be_transform_node(val);
3948 ia32_code_gen_t *cg = env_cg;
3949 ir_node *res = NULL;
3950 ir_graph *irg = current_ir_graph;
3952 ir_node *noreg, *new_ptr, *new_mem;
3959 mem = get_irn_n(node, 2);
3960 new_mem = be_transform_node(mem);
3961 ptr = get_irn_n(node, 0);
3962 new_ptr = be_transform_node(ptr);
3963 noreg = ia32_new_NoReg_gp(cg);
3964 dbgi = get_irn_dbg_info(node);
3966 /* Store x87 -> MEM */
3967 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3968 get_ia32_ls_mode(node));
3969 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3970 set_ia32_use_frame(res);
3971 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3972 set_ia32_op_type(res, ia32_AddrModeD);
3974 /* Load MEM -> SSE */
3975 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3976 get_ia32_ls_mode(node));
3977 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3978 set_ia32_use_frame(res);
3979 set_ia32_op_type(res, ia32_AddrModeS);
3980 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3986 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3988 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3989 ir_node *block = be_transform_node(get_nodes_block(node));
3990 ir_node *val = get_irn_n(node, 1);
3991 ir_node *new_val = be_transform_node(val);
3992 ia32_code_gen_t *cg = env_cg;
3993 ir_graph *irg = current_ir_graph;
3994 ir_node *res = NULL;
3995 ir_entity *fent = get_ia32_frame_ent(node);
3996 ir_mode *lsmode = get_ia32_ls_mode(node);
3998 ir_node *noreg, *new_ptr, *new_mem;
4002 if (! USE_SSE2(cg)) {
4003 /* SSE unit is not used -> skip this node. */
4007 ptr = get_irn_n(node, 0);
4008 new_ptr = be_transform_node(ptr);
4009 mem = get_irn_n(node, 2);
4010 new_mem = be_transform_node(mem);
4011 noreg = ia32_new_NoReg_gp(cg);
4012 dbgi = get_irn_dbg_info(node);
4014 /* Store SSE -> MEM */
4015 if (is_ia32_xLoad(skip_Proj(new_val))) {
4016 ir_node *ld = skip_Proj(new_val);
4018 /* we can vfld the value directly into the fpu */
4019 fent = get_ia32_frame_ent(ld);
4020 ptr = get_irn_n(ld, 0);
4021 offs = get_ia32_am_offs_int(ld);
4023 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4025 set_ia32_frame_ent(res, fent);
4026 set_ia32_use_frame(res);
4027 set_ia32_ls_mode(res, lsmode);
4028 set_ia32_op_type(res, ia32_AddrModeD);
4032 /* Load MEM -> x87 */
4033 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4034 set_ia32_frame_ent(res, fent);
4035 set_ia32_use_frame(res);
4036 add_ia32_am_offs_int(res, offs);
4037 set_ia32_op_type(res, ia32_AddrModeS);
4038 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4043 /*********************************************************
4046 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4047 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4048 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4049 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4051 *********************************************************/
4054 * the BAD transformer.
4056 static ir_node *bad_transform(ir_node *node) {
4057 panic("No transform function for %+F available.\n", node);
4062 * Transform the Projs of an AddSP.
4064 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4065 ir_node *block = be_transform_node(get_nodes_block(node));
4066 ir_node *pred = get_Proj_pred(node);
4067 ir_node *new_pred = be_transform_node(pred);
4068 ir_graph *irg = current_ir_graph;
4069 dbg_info *dbgi = get_irn_dbg_info(node);
4070 long proj = get_Proj_proj(node);
4072 if (proj == pn_be_AddSP_sp) {
4073 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4074 pn_ia32_SubSP_stack);
4075 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4077 } else if(proj == pn_be_AddSP_res) {
4078 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4079 pn_ia32_SubSP_addr);
4080 } else if (proj == pn_be_AddSP_M) {
4081 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4085 return new_rd_Unknown(irg, get_irn_mode(node));
4089 * Transform the Projs of a SubSP.
4091 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4092 ir_node *block = be_transform_node(get_nodes_block(node));
4093 ir_node *pred = get_Proj_pred(node);
4094 ir_node *new_pred = be_transform_node(pred);
4095 ir_graph *irg = current_ir_graph;
4096 dbg_info *dbgi = get_irn_dbg_info(node);
4097 long proj = get_Proj_proj(node);
4099 if (proj == pn_be_SubSP_sp) {
4100 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4101 pn_ia32_AddSP_stack);
4102 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4104 } else if (proj == pn_be_SubSP_M) {
4105 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4109 return new_rd_Unknown(irg, get_irn_mode(node));
4113 * Transform and renumber the Projs from a Load.
4115 static ir_node *gen_Proj_Load(ir_node *node) {
4117 ir_node *block = be_transform_node(get_nodes_block(node));
4118 ir_node *pred = get_Proj_pred(node);
4119 ir_graph *irg = current_ir_graph;
4120 dbg_info *dbgi = get_irn_dbg_info(node);
4121 long proj = get_Proj_proj(node);
4124 /* loads might be part of source address mode matches, so we don't
4125 transform the ProjMs yet (with the exception of loads whose result is
4128 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4131 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4133 /* this is needed, because sometimes we have loops that are only
4134 reachable through the ProjM */
4135 be_enqueue_preds(node);
4136 /* do it in 2 steps, to silence firm verifier */
4137 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4138 set_Proj_proj(res, pn_ia32_Load_M);
4142 /* renumber the proj */
4143 new_pred = be_transform_node(pred);
4144 if (is_ia32_Load(new_pred)) {
4145 if (proj == pn_Load_res) {
4146 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4148 } else if (proj == pn_Load_M) {
4149 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4152 } else if(is_ia32_Conv_I2I(new_pred)) {
4153 set_irn_mode(new_pred, mode_T);
4154 if (proj == pn_Load_res) {
4155 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4156 } else if (proj == pn_Load_M) {
4157 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4159 } else if (is_ia32_xLoad(new_pred)) {
4160 if (proj == pn_Load_res) {
4161 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4163 } else if (proj == pn_Load_M) {
4164 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4167 } else if (is_ia32_vfld(new_pred)) {
4168 if (proj == pn_Load_res) {
4169 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4171 } else if (proj == pn_Load_M) {
4172 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4176 /* can happen for ProJMs when source address mode happened for the
4179 /* however it should not be the result proj, as that would mean the
4180 load had multiple users and should not have been used for
4182 if(proj != pn_Load_M) {
4183 panic("internal error: transformed node not a Load");
4185 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4189 return new_rd_Unknown(irg, get_irn_mode(node));
4193 * Transform and renumber the Projs from a DivMod like instruction.
4195 static ir_node *gen_Proj_DivMod(ir_node *node) {
4196 ir_node *block = be_transform_node(get_nodes_block(node));
4197 ir_node *pred = get_Proj_pred(node);
4198 ir_node *new_pred = be_transform_node(pred);
4199 ir_graph *irg = current_ir_graph;
4200 dbg_info *dbgi = get_irn_dbg_info(node);
4201 ir_mode *mode = get_irn_mode(node);
4202 long proj = get_Proj_proj(node);
4204 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4206 switch (get_irn_opcode(pred)) {
4210 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4212 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4220 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4222 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4230 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4231 case pn_DivMod_res_div:
4232 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4233 case pn_DivMod_res_mod:
4234 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4244 return new_rd_Unknown(irg, mode);
4248 * Transform and renumber the Projs from a CopyB.
4250 static ir_node *gen_Proj_CopyB(ir_node *node) {
4251 ir_node *block = be_transform_node(get_nodes_block(node));
4252 ir_node *pred = get_Proj_pred(node);
4253 ir_node *new_pred = be_transform_node(pred);
4254 ir_graph *irg = current_ir_graph;
4255 dbg_info *dbgi = get_irn_dbg_info(node);
4256 ir_mode *mode = get_irn_mode(node);
4257 long proj = get_Proj_proj(node);
4260 case pn_CopyB_M_regular:
4261 if (is_ia32_CopyB_i(new_pred)) {
4262 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4263 } else if (is_ia32_CopyB(new_pred)) {
4264 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4272 return new_rd_Unknown(irg, mode);
4276 * Transform and renumber the Projs from a Quot.
4278 static ir_node *gen_Proj_Quot(ir_node *node) {
4279 ir_node *block = be_transform_node(get_nodes_block(node));
4280 ir_node *pred = get_Proj_pred(node);
4281 ir_node *new_pred = be_transform_node(pred);
4282 ir_graph *irg = current_ir_graph;
4283 dbg_info *dbgi = get_irn_dbg_info(node);
4284 ir_mode *mode = get_irn_mode(node);
4285 long proj = get_Proj_proj(node);
4289 if (is_ia32_xDiv(new_pred)) {
4290 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4291 } else if (is_ia32_vfdiv(new_pred)) {
4292 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4296 if (is_ia32_xDiv(new_pred)) {
4297 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4298 } else if (is_ia32_vfdiv(new_pred)) {
4299 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4307 return new_rd_Unknown(irg, mode);
4311 * Transform the Thread Local Storage Proj.
4313 static ir_node *gen_Proj_tls(ir_node *node) {
4314 ir_node *block = be_transform_node(get_nodes_block(node));
4315 ir_graph *irg = current_ir_graph;
4316 dbg_info *dbgi = NULL;
4317 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4322 static ir_node *gen_be_Call(ir_node *node) {
4323 ir_node *res = be_duplicate_node(node);
4324 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4329 static ir_node *gen_be_IncSP(ir_node *node) {
4330 ir_node *res = be_duplicate_node(node);
4331 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4337 * Transform the Projs from a be_Call.
4339 static ir_node *gen_Proj_be_Call(ir_node *node) {
4340 ir_node *block = be_transform_node(get_nodes_block(node));
4341 ir_node *call = get_Proj_pred(node);
4342 ir_node *new_call = be_transform_node(call);
4343 ir_graph *irg = current_ir_graph;
4344 dbg_info *dbgi = get_irn_dbg_info(node);
4345 ir_type *method_type = be_Call_get_type(call);
4346 int n_res = get_method_n_ress(method_type);
4347 long proj = get_Proj_proj(node);
4348 ir_mode *mode = get_irn_mode(node);
4350 const arch_register_class_t *cls;
4352 /* The following is kinda tricky: If we're using SSE, then we have to
4353 * move the result value of the call in floating point registers to an
4354 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4355 * after the call, we have to make sure to correctly make the
4356 * MemProj and the result Proj use these 2 nodes
4358 if (proj == pn_be_Call_M_regular) {
4359 // get new node for result, are we doing the sse load/store hack?
4360 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4361 ir_node *call_res_new;
4362 ir_node *call_res_pred = NULL;
4364 if (call_res != NULL) {
4365 call_res_new = be_transform_node(call_res);
4366 call_res_pred = get_Proj_pred(call_res_new);
4369 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4370 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4371 pn_be_Call_M_regular);
4373 assert(is_ia32_xLoad(call_res_pred));
4374 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4378 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4379 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4380 && USE_SSE2(env_cg)) {
4382 ir_node *frame = get_irg_frame(irg);
4383 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4385 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4388 /* in case there is no memory output: create one to serialize the copy
4390 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4391 pn_be_Call_M_regular);
4392 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4393 pn_be_Call_first_res);
4395 /* store st(0) onto stack */
4396 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4398 set_ia32_op_type(fstp, ia32_AddrModeD);
4399 set_ia32_use_frame(fstp);
4401 /* load into SSE register */
4402 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4404 set_ia32_op_type(sse_load, ia32_AddrModeS);
4405 set_ia32_use_frame(sse_load);
4407 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4413 /* transform call modes */
4414 if (mode_is_data(mode)) {
4415 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4419 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4423 * Transform the Projs from a Cmp.
4425 static ir_node *gen_Proj_Cmp(ir_node *node)
4427 /* normally Cmps are processed when looking at Cond nodes, but this case
4428 * can happen in complicated Psi conditions */
4429 dbg_info *dbgi = get_irn_dbg_info(node);
4430 ir_node *block = get_nodes_block(node);
4431 ir_node *new_block = be_transform_node(block);
4432 ir_node *cmp = get_Proj_pred(node);
4433 ir_node *new_cmp = be_transform_node(cmp);
4434 long pnc = get_Proj_proj(node);
4437 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4443 * Transform and potentially renumber Proj nodes.
4445 static ir_node *gen_Proj(ir_node *node) {
4446 ir_graph *irg = current_ir_graph;
4447 dbg_info *dbgi = get_irn_dbg_info(node);
4448 ir_node *pred = get_Proj_pred(node);
4449 long proj = get_Proj_proj(node);
4451 if (is_Store(pred)) {
4452 if (proj == pn_Store_M) {
4453 return be_transform_node(pred);
4456 return new_r_Bad(irg);
4458 } else if (is_Load(pred)) {
4459 return gen_Proj_Load(node);
4460 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4461 return gen_Proj_DivMod(node);
4462 } else if (is_CopyB(pred)) {
4463 return gen_Proj_CopyB(node);
4464 } else if (is_Quot(pred)) {
4465 return gen_Proj_Quot(node);
4466 } else if (be_is_SubSP(pred)) {
4467 return gen_Proj_be_SubSP(node);
4468 } else if (be_is_AddSP(pred)) {
4469 return gen_Proj_be_AddSP(node);
4470 } else if (be_is_Call(pred)) {
4471 return gen_Proj_be_Call(node);
4472 } else if (is_Cmp(pred)) {
4473 return gen_Proj_Cmp(node);
4474 } else if (get_irn_op(pred) == op_Start) {
4475 if (proj == pn_Start_X_initial_exec) {
4476 ir_node *block = get_nodes_block(pred);
4479 /* we exchange the ProjX with a jump */
4480 block = be_transform_node(block);
4481 jump = new_rd_Jmp(dbgi, irg, block);
4484 if (node == be_get_old_anchor(anchor_tls)) {
4485 return gen_Proj_tls(node);
4488 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4492 ir_node *new_pred = be_transform_node(pred);
4493 ir_node *block = be_transform_node(get_nodes_block(node));
4494 ir_mode *mode = get_irn_mode(node);
4495 if (mode_needs_gp_reg(mode)) {
4496 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4497 get_Proj_proj(node));
4498 #ifdef DEBUG_libfirm
4499 new_proj->node_nr = node->node_nr;
4505 return be_duplicate_node(node);
4509 * Enters all transform functions into the generic pointer
4511 static void register_transformers(void)
4515 /* first clear the generic function pointer for all ops */
4516 clear_irp_opcodes_generic_func();
4518 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4519 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4557 /* transform ops from intrinsic lowering */
4574 GEN(ia32_l_X87toSSE);
4575 GEN(ia32_l_SSEtoX87);
4581 /* we should never see these nodes */
4596 /* handle generic backend nodes */
4605 op_Mulh = get_op_Mulh();
4614 * Pre-transform all unknown and noreg nodes.
4616 static void ia32_pretransform_node(void *arch_cg) {
4617 ia32_code_gen_t *cg = arch_cg;
4619 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4620 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4621 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4622 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4623 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4624 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4629 * Walker, checks if all ia32 nodes producing more than one result have
4630 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4632 static void add_missing_keep_walker(ir_node *node, void *data)
4635 unsigned found_projs = 0;
4636 const ir_edge_t *edge;
4637 ir_mode *mode = get_irn_mode(node);
4642 if(!is_ia32_irn(node))
4645 n_outs = get_ia32_n_res(node);
4648 if(is_ia32_SwitchJmp(node))
4651 assert(n_outs < (int) sizeof(unsigned) * 8);
4652 foreach_out_edge(node, edge) {
4653 ir_node *proj = get_edge_src_irn(edge);
4654 int pn = get_Proj_proj(proj);
4656 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4657 found_projs |= 1 << pn;
4661 /* are keeps missing? */
4663 for(i = 0; i < n_outs; ++i) {
4666 const arch_register_req_t *req;
4667 const arch_register_class_t *class;
4669 if(found_projs & (1 << i)) {
4673 req = get_ia32_out_req(node, i);
4678 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4682 block = get_nodes_block(node);
4683 in[0] = new_r_Proj(current_ir_graph, block, node,
4684 arch_register_class_mode(class), i);
4685 if(last_keep != NULL) {
4686 be_Keep_add_node(last_keep, class, in[0]);
4688 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4689 if(sched_is_scheduled(node)) {
4690 sched_add_after(node, last_keep);
4697 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4700 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4702 ir_graph *irg = be_get_birg_irg(cg->birg);
4703 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4706 /* do the transformation */
4707 void ia32_transform_graph(ia32_code_gen_t *cg) {
4709 ir_graph *irg = cg->irg;
4711 /* TODO: look at cpu and fill transform config in with that... */
4712 transform_config.use_incdec = 1;
4713 transform_config.use_sse2 = 0;
4714 transform_config.use_ffreep = 0;
4715 transform_config.use_ftst = 0;
4716 transform_config.use_femms = 0;
4717 transform_config.use_fucomi = 1;
4718 transform_config.use_cmov = 1;
4720 register_transformers();
4722 initial_fpcw = NULL;
4724 heights = heights_new(irg);
4725 calculate_non_address_mode_nodes(irg);
4727 /* the transform phase is not safe for CSE (yet) because several nodes get
4728 * attributes set after their creation */
4729 cse_last = get_opt_cse();
4732 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4734 set_opt_cse(cse_last);
4736 free_non_address_mode_nodes();
4737 heights_free(heights);
4741 void ia32_init_transform(void)
4743 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");