2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
152 * creates a unique ident by adding a number to a tag
154 * @param tag the tag string, must contain a %d if a number
157 static ident *unique_id(const char *tag)
159 static unsigned id = 0;
162 snprintf(str, sizeof(str), tag, ++id);
163 return new_id_from_str(str);
167 * Get a primitive type for a mode.
169 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
171 pmap_entry *e = pmap_find(types, mode);
176 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
177 res = new_type_primitive(new_id_from_str(buf), mode);
178 set_type_alignment_bytes(res, 16);
179 pmap_insert(types, mode, res);
187 * Get an atomic entity that is initialized with a tarval
189 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
191 tarval *tv = get_Const_tarval(cnst);
192 pmap_entry *e = pmap_find(isa->tv_ent, tv);
197 ir_mode *mode = get_irn_mode(cnst);
198 ir_type *tp = get_Const_type(cnst);
199 if (tp == firm_unknown_type)
200 tp = get_prim_type(isa->types, mode);
202 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
204 set_entity_ld_ident(res, get_entity_ident(res));
205 set_entity_visibility(res, visibility_local);
206 set_entity_variability(res, variability_constant);
207 set_entity_allocation(res, allocation_static);
209 /* we create a new entity here: It's initialization must resist on the
211 rem = current_ir_graph;
212 current_ir_graph = get_const_code_irg();
213 set_atomic_ent_value(res, new_Const_type(tv, tp));
214 current_ir_graph = rem;
216 pmap_insert(isa->tv_ent, tv, res);
224 static int is_Const_0(ir_node *node) {
228 return classify_Const(node) == CNST_NULL;
231 static int is_Const_1(ir_node *node) {
235 return classify_Const(node) == CNST_ONE;
238 static int is_Const_Minus_1(ir_node *node) {
244 mode = get_irn_mode(node);
245 if(!mode_is_signed(mode))
248 tv = get_Const_tarval(node);
251 return classify_tarval(tv) == CNST_ONE;
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
270 cnst_classify_t clss = classify_Const(node);
272 if (USE_SSE2(env_cg)) {
273 if (clss == CNST_NULL) {
274 load = new_rd_ia32_xZero(dbgi, irg, block);
275 set_ia32_ls_mode(load, mode);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
282 set_ia32_op_type(load, ia32_AddrModeS);
283 set_ia32_am_sc(load, floatent);
284 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
285 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_sc(load, floatent);
300 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
306 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
308 /* Const Nodes before the initial IncSP are a bad idea, because
309 * they could be spilled and we have no SP ready at that point yet.
310 * So add a dependency to the initial frame pointer calculation to
311 * avoid that situation.
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(load, get_irg_frame(irg));
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 tarval *tv = get_Const_tarval(node);
324 tv = tarval_convert_to(tv, mode_Iu);
326 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
328 panic("couldn't convert constant tarval (%+F)", node);
330 val = get_tarval_long(tv);
332 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
333 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
336 if (get_irg_start_block(irg) == block) {
337 add_irn_dep(cnst, get_irg_frame(irg));
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *old_block = get_nodes_block(node);
350 ir_node *block = be_transform_node(old_block);
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
356 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
357 ir_node *nomem = new_NoMem();
359 if (USE_SSE2(env_cg))
360 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
363 set_ia32_am_sc(cnst, get_SymConst_entity(node));
364 set_ia32_use_frame(cnst);
368 if(get_SymConst_kind(node) != symconst_addr_ent) {
369 panic("backend only support symconst_addr_ent (at %+F)", node);
371 entity = get_SymConst_entity(node);
372 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
375 /* Const Nodes before the initial IncSP are a bad idea, because
376 * they could be spilled and we have no SP ready at that point yet
378 if (get_irg_start_block(irg) == block) {
379 add_irn_dep(cnst, get_irg_frame(irg));
382 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
387 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
388 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
389 static const struct {
391 const char *ent_name;
392 const char *cnst_str;
395 } names [ia32_known_const_max] = {
396 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
397 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
398 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
399 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
400 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
402 static ir_entity *ent_cache[ia32_known_const_max];
404 const char *tp_name, *ent_name, *cnst_str;
412 ent_name = names[kct].ent_name;
413 if (! ent_cache[kct]) {
414 tp_name = names[kct].tp_name;
415 cnst_str = names[kct].cnst_str;
417 switch (names[kct].mode) {
418 case 0: mode = mode_Iu; break;
419 case 1: mode = mode_Lu; break;
420 default: mode = mode_F; break;
422 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
423 tp = new_type_primitive(new_id_from_str(tp_name), mode);
424 /* set the specified alignment */
425 set_type_alignment_bytes(tp, names[kct].align);
427 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
429 set_entity_ld_ident(ent, get_entity_ident(ent));
430 set_entity_visibility(ent, visibility_local);
431 set_entity_variability(ent, variability_constant);
432 set_entity_allocation(ent, allocation_static);
434 /* we create a new entity here: It's initialization must resist on the
436 rem = current_ir_graph;
437 current_ir_graph = get_const_code_irg();
438 cnst = new_Const(mode, tv);
439 current_ir_graph = rem;
441 set_atomic_ent_value(ent, cnst);
443 /* cache the entry */
444 ent_cache[kct] = ent;
447 return ent_cache[kct];
452 * Prints the old node name on cg obst and returns a pointer to it.
454 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
455 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
457 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
458 obstack_1grow(isa->name_obst, 0);
459 return obstack_finish(isa->name_obst);
463 static int use_source_address_mode(ir_node *block, ir_node *node,
472 load = get_Proj_pred(node);
473 pn = get_Proj_proj(node);
474 if(!is_Load(load) || pn != pn_Load_res)
476 if(get_nodes_block(load) != block)
478 /* we only use address mode if we're the only user of the load */
479 if(get_irn_n_edges(node) > 1)
482 mode = get_irn_mode(node);
483 if(!mode_needs_gp_reg(mode))
486 * Matze: the unresolved question here is wether 8/16bit operations
487 * are a good idea if they define registers (as writing to an 8/16
488 * bit reg is bad on modern cpu as it confuses the dependency calculation
491 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
494 /* don't do AM if other node inputs depend on the load (via mem-proj) */
495 if(other != NULL && get_nodes_block(other) == block
496 && heights_reachable_in_block(heights, other, load))
502 typedef struct ia32_address_mode_t ia32_address_mode_t;
503 struct ia32_address_mode_t {
507 ia32_op_type_t op_type;
514 static void build_address(ia32_address_mode_t *am, ir_node *node)
516 ia32_address_t *addr = &am->addr;
517 ir_node *load = get_Proj_pred(node);
518 ir_node *ptr = get_Load_ptr(load);
519 ir_node *mem = get_Load_mem(load);
520 ir_node *new_mem = be_transform_node(mem);
524 am->ls_mode = get_Load_mode(load);
525 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
527 /* construct load address */
528 ia32_create_address_mode(addr, ptr, 0);
533 base = ia32_new_NoReg_gp(env_cg);
535 base = be_transform_node(base);
539 index = ia32_new_NoReg_gp(env_cg);
541 index = be_transform_node(index);
549 static void set_address(ir_node *node, ia32_address_t *addr)
551 set_ia32_am_scale(node, addr->scale);
552 set_ia32_am_sc(node, addr->symconst_ent);
553 set_ia32_am_offs_int(node, addr->offset);
554 if(addr->symconst_sign)
555 set_ia32_am_sc_sign(node);
557 set_ia32_use_frame(node);
558 set_ia32_frame_ent(node, addr->frame_entity);
561 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
563 set_address(node, &am->addr);
565 set_ia32_op_type(node, am->op_type);
566 set_ia32_ls_mode(node, am->ls_mode);
568 set_ia32_commutative(node);
571 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
572 ir_node *op1, ir_node *op2, int commutative,
573 int use_am_and_immediates, int use_am,
576 ia32_address_t *addr = &am->addr;
577 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
581 memset(am, 0, sizeof(am[0]));
583 if(!use_8_16_bit_am && get_mode_size_bits(get_irn_mode(op1)) < 32)
586 new_op2 = try_create_Immediate(op2, 0);
587 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
588 build_address(am, op2);
589 new_op1 = be_transform_node(op1);
591 am->op_type = ia32_AddrModeS;
592 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
593 use_am && use_source_address_mode(block, op1, op2)) {
594 build_address(am, op1);
595 if(new_op2 != NULL) {
598 new_op1 = be_transform_node(op2);
602 am->op_type = ia32_AddrModeS;
604 new_op1 = be_transform_node(op1);
606 new_op2 = be_transform_node(op2);
607 am->op_type = ia32_Normal;
609 if(addr->base == NULL)
610 addr->base = noreg_gp;
611 if(addr->index == NULL)
612 addr->index = noreg_gp;
613 if(addr->mem == NULL)
614 addr->mem = new_NoMem();
616 am->new_op1 = new_op1;
617 am->new_op2 = new_op2;
618 am->commutative = commutative;
621 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
623 ir_graph *irg = current_ir_graph;
627 if(am->mem_proj == NULL)
630 /* we have to create a mode_T so the old MemProj can attach to us */
631 mode = get_irn_mode(node);
632 load = get_Proj_pred(am->mem_proj);
634 mark_irn_visited(load);
635 be_set_transformed_node(load, node);
638 set_irn_mode(node, mode_T);
639 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
646 * Construct a standard binary operation, set AM and immediate if required.
648 * @param op1 The first operand
649 * @param op2 The second operand
650 * @param func The node constructor function
651 * @return The constructed ia32 node.
653 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
654 construct_binop_func *func, int commutative)
656 ir_node *src_block = get_nodes_block(node);
657 ir_node *block = be_transform_node(src_block);
658 ir_graph *irg = current_ir_graph;
659 dbg_info *dbgi = get_irn_dbg_info(node);
661 ia32_address_mode_t am;
662 ia32_address_t *addr = &am.addr;
664 match_arguments(&am, src_block, op1, op2, commutative, 0, 1, 0);
666 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
667 am.new_op1, am.new_op2);
668 set_am_attributes(new_node, &am);
669 /* we can't use source address mode anymore when using immediates */
670 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
671 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
672 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
674 new_node = fix_mem_proj(new_node, &am);
680 * Construct a standard binary operation, set AM and immediate if required.
682 * @param op1 The first operand
683 * @param op2 The second operand
684 * @param func The node constructor function
685 * @return The constructed ia32 node.
687 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
688 construct_binop_func *func)
690 ir_node *block = be_transform_node(get_nodes_block(node));
691 ir_node *new_op1 = be_transform_node(op1);
692 ir_node *new_op2 = be_transform_node(op2);
693 ir_node *new_node = NULL;
694 dbg_info *dbgi = get_irn_dbg_info(node);
695 ir_graph *irg = current_ir_graph;
696 ir_mode *mode = get_irn_mode(node);
697 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
698 ir_node *nomem = new_NoMem();
700 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
702 if (is_op_commutative(get_irn_op(node))) {
703 set_ia32_commutative(new_node);
705 set_ia32_ls_mode(new_node, mode);
707 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
712 static ir_node *get_fpcw(void)
715 if(initial_fpcw != NULL)
718 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
719 &ia32_fp_cw_regs[REG_FPCW]);
720 initial_fpcw = be_transform_node(fpcw);
726 * Construct a standard binary operation, set AM and immediate if required.
728 * @param op1 The first operand
729 * @param op2 The second operand
730 * @param func The node constructor function
731 * @return The constructed ia32 node.
733 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
734 construct_binop_float_func *func)
736 ir_node *block = be_transform_node(get_nodes_block(node));
737 ir_node *new_op1 = be_transform_node(op1);
738 ir_node *new_op2 = be_transform_node(op2);
739 ir_node *new_node = NULL;
740 dbg_info *dbgi = get_irn_dbg_info(node);
741 ir_graph *irg = current_ir_graph;
742 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
743 ir_node *nomem = new_NoMem();
745 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
747 if (is_op_commutative(get_irn_op(node))) {
748 set_ia32_commutative(new_node);
751 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
757 * Construct a shift/rotate binary operation, sets AM and immediate if required.
759 * @param op1 The first operand
760 * @param op2 The second operand
761 * @param func The node constructor function
762 * @return The constructed ia32 node.
764 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
765 construct_shift_func *func)
767 dbg_info *dbgi = get_irn_dbg_info(node);
768 ir_graph *irg = current_ir_graph;
769 ir_node *block = get_nodes_block(node);
770 ir_node *new_block = be_transform_node(block);
771 ir_node *new_op1 = be_transform_node(op1);
772 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
775 assert(! mode_is_float(get_irn_mode(node))
776 && "Shift/Rotate with float not supported");
778 res = func(dbgi, irg, new_block, new_op1, new_op2);
779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
781 /* lowered shift instruction may have a dependency operand, handle it here */
782 if (get_irn_arity(node) == 3) {
783 /* we have a dependency */
784 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
785 add_irn_dep(res, new_dep);
793 * Construct a standard unary operation, set AM and immediate if required.
795 * @param op The operand
796 * @param func The node constructor function
797 * @return The constructed ia32 node.
799 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
801 ir_node *block = be_transform_node(get_nodes_block(node));
802 ir_node *new_op = be_transform_node(op);
803 ir_node *new_node = NULL;
804 ir_graph *irg = current_ir_graph;
805 dbg_info *dbgi = get_irn_dbg_info(node);
807 new_node = func(dbgi, irg, block, new_op);
809 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
814 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
815 ia32_address_t *addr)
817 ir_graph *irg = current_ir_graph;
818 ir_node *base = addr->base;
819 ir_node *index = addr->index;
823 base = ia32_new_NoReg_gp(env_cg);
825 base = be_transform_node(base);
829 index = ia32_new_NoReg_gp(env_cg);
831 index = be_transform_node(index);
834 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
835 set_address(res, addr);
840 static int am_has_immediates(const ia32_address_t *addr)
842 return addr->offset != 0 || addr->symconst_ent != NULL
843 || addr->frame_entity || addr->use_frame;
847 * Creates an ia32 Add.
849 * @return the created ia32 Add node
851 static ir_node *gen_Add(ir_node *node) {
852 ir_node *block = be_transform_node(get_nodes_block(node));
853 ir_node *op1 = get_Add_left(node);
854 ir_node *op2 = get_Add_right(node);
857 ir_graph *irg = current_ir_graph;
858 dbg_info *dbgi = get_irn_dbg_info(node);
859 ir_mode *mode = get_irn_mode(node);
860 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
861 ir_node *src_block = get_nodes_block(node);
862 ir_node *add_immediate_op;
864 ia32_address_mode_t am;
866 if (mode_is_float(mode)) {
867 if (USE_SSE2(env_cg))
868 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
870 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
875 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
876 * 1. Add with immediate -> Lea
877 * 2. Add with possible source address mode -> Add
878 * 3. Otherwise -> Lea
880 memset(&addr, 0, sizeof(addr));
881 ia32_create_address_mode(&addr, node, 1);
882 add_immediate_op = NULL;
884 if(addr.base == NULL && addr.index == NULL) {
885 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
886 addr.symconst_sign, addr.offset);
887 add_irn_dep(new_op, get_irg_frame(irg));
888 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
891 /* add with immediate? */
892 if(addr.index == NULL) {
893 add_immediate_op = addr.base;
894 } else if(addr.base == NULL && addr.scale == 0) {
895 add_immediate_op = addr.index;
898 if(add_immediate_op != NULL) {
899 if(!am_has_immediates(&addr)) {
901 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
904 return be_transform_node(add_immediate_op);
907 new_op = create_lea_from_address(dbgi, block, &addr);
908 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
912 /* test if we can use source address mode */
913 memset(&am, 0, sizeof(am));
915 if(use_source_address_mode(src_block, op2, op1)) {
916 build_address(&am, op2);
917 new_op1 = be_transform_node(op1);
918 } else if(use_source_address_mode(src_block, op1, op2)) {
919 build_address(&am, op1);
920 new_op1 = be_transform_node(op2);
922 /* construct an Add with source address mode */
923 if(new_op1 != NULL) {
924 ia32_address_t *am_addr = &am.addr;
925 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
926 am_addr->mem, new_op1, noreg);
927 set_address(new_op, am_addr);
928 set_ia32_op_type(new_op, ia32_AddrModeS);
929 set_ia32_ls_mode(new_op, am.ls_mode);
930 set_ia32_commutative(new_op);
931 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
933 new_op = fix_mem_proj(new_op, &am);
938 /* otherwise construct a lea */
939 new_op = create_lea_from_address(dbgi, block, &addr);
940 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
945 * Creates an ia32 Mul.
947 * @return the created ia32 Mul node
949 static ir_node *gen_Mul(ir_node *node) {
950 ir_node *op1 = get_Mul_left(node);
951 ir_node *op2 = get_Mul_right(node);
952 ir_mode *mode = get_irn_mode(node);
954 if (mode_is_float(mode)) {
955 if (USE_SSE2(env_cg))
956 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
958 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
962 for the lower 32bit of the result it doesn't matter whether we use
963 signed or unsigned multiplication so we use IMul as it has fewer
966 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
970 * Creates an ia32 Mulh.
971 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
972 * this result while Mul returns the lower 32 bit.
974 * @return the created ia32 Mulh node
976 static ir_node *gen_Mulh(ir_node *node) {
977 ir_node *block = be_transform_node(get_nodes_block(node));
978 ir_node *op1 = get_irn_n(node, 0);
979 ir_node *new_op1 = be_transform_node(op1);
980 ir_node *op2 = get_irn_n(node, 1);
981 ir_node *new_op2 = be_transform_node(op2);
982 ir_graph *irg = current_ir_graph;
983 dbg_info *dbgi = get_irn_dbg_info(node);
984 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
985 ir_mode *mode = get_irn_mode(node);
986 ir_node *proj_EDX, *res;
988 assert(!mode_is_float(mode) && "Mulh with float not supported");
989 if (mode_is_signed(mode)) {
990 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
993 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
997 set_ia32_commutative(res);
999 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1007 * Creates an ia32 And.
1009 * @return The created ia32 And node
1011 static ir_node *gen_And(ir_node *node) {
1012 ir_node *op1 = get_And_left(node);
1013 ir_node *op2 = get_And_right(node);
1014 assert(! mode_is_float(get_irn_mode(node)));
1016 /* is it a zero extension? */
1017 if (is_Const(op2)) {
1018 tarval *tv = get_Const_tarval(op2);
1019 long v = get_tarval_long(tv);
1021 if (v == 0xFF || v == 0xFFFF) {
1022 dbg_info *dbgi = get_irn_dbg_info(node);
1023 ir_node *block = get_nodes_block(node);
1030 assert(v == 0xFFFF);
1033 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1039 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1045 * Creates an ia32 Or.
1047 * @return The created ia32 Or node
1049 static ir_node *gen_Or(ir_node *node) {
1050 ir_node *op1 = get_Or_left(node);
1051 ir_node *op2 = get_Or_right(node);
1053 assert (! mode_is_float(get_irn_mode(node)));
1054 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1060 * Creates an ia32 Eor.
1062 * @return The created ia32 Eor node
1064 static ir_node *gen_Eor(ir_node *node) {
1065 ir_node *op1 = get_Eor_left(node);
1066 ir_node *op2 = get_Eor_right(node);
1068 assert(! mode_is_float(get_irn_mode(node)));
1069 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1074 * Creates an ia32 Sub.
1076 * @return The created ia32 Sub node
1078 static ir_node *gen_Sub(ir_node *node) {
1079 ir_node *op1 = get_Sub_left(node);
1080 ir_node *op2 = get_Sub_right(node);
1081 ir_mode *mode = get_irn_mode(node);
1083 if (mode_is_float(mode)) {
1084 if (USE_SSE2(env_cg))
1085 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1087 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1091 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1095 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1101 * Generates an ia32 DivMod with additional infrastructure for the
1102 * register allocator if needed.
1104 * @param dividend -no comment- :)
1105 * @param divisor -no comment- :)
1106 * @param dm_flav flavour_Div/Mod/DivMod
1107 * @return The created ia32 DivMod node
1109 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1110 ir_node *divisor, ia32_op_flavour_t dm_flav)
1112 ir_node *block = be_transform_node(get_nodes_block(node));
1113 ir_node *new_dividend = be_transform_node(dividend);
1114 ir_node *new_divisor = be_transform_node(divisor);
1115 ir_graph *irg = current_ir_graph;
1116 dbg_info *dbgi = get_irn_dbg_info(node);
1117 ir_mode *mode = get_irn_mode(node);
1118 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1119 ir_node *res, *proj_div, *proj_mod;
1120 ir_node *sign_extension;
1121 ir_node *mem, *new_mem;
1124 proj_div = proj_mod = NULL;
1128 mem = get_Div_mem(node);
1129 mode = get_Div_resmode(node);
1130 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1131 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1134 mem = get_Mod_mem(node);
1135 mode = get_Mod_resmode(node);
1136 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1137 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1139 case flavour_DivMod:
1140 mem = get_DivMod_mem(node);
1141 mode = get_DivMod_resmode(node);
1142 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1143 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1144 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1147 panic("invalid divmod flavour!");
1149 new_mem = be_transform_node(mem);
1151 if (mode_is_signed(mode)) {
1152 /* in signed mode, we need to sign extend the dividend */
1153 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1154 add_irn_dep(produceval, get_irg_frame(irg));
1155 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1158 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1159 add_irn_dep(sign_extension, get_irg_frame(irg));
1162 if (mode_is_signed(mode)) {
1163 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1164 new_dividend, sign_extension, new_divisor, dm_flav);
1166 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1167 sign_extension, new_divisor, dm_flav);
1170 set_ia32_exc_label(res, has_exc);
1171 set_irn_pinned(res, get_irn_pinned(node));
1173 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1180 * Wrapper for generate_DivMod. Sets flavour_Mod.
1183 static ir_node *gen_Mod(ir_node *node) {
1184 return generate_DivMod(node, get_Mod_left(node),
1185 get_Mod_right(node), flavour_Mod);
1189 * Wrapper for generate_DivMod. Sets flavour_Div.
1192 static ir_node *gen_Div(ir_node *node) {
1193 return generate_DivMod(node, get_Div_left(node),
1194 get_Div_right(node), flavour_Div);
1198 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1200 static ir_node *gen_DivMod(ir_node *node) {
1201 return generate_DivMod(node, get_DivMod_left(node),
1202 get_DivMod_right(node), flavour_DivMod);
1208 * Creates an ia32 floating Div.
1210 * @return The created ia32 xDiv node
1212 static ir_node *gen_Quot(ir_node *node) {
1213 ir_node *block = be_transform_node(get_nodes_block(node));
1214 ir_node *op1 = get_Quot_left(node);
1215 ir_node *new_op1 = be_transform_node(op1);
1216 ir_node *op2 = get_Quot_right(node);
1217 ir_node *new_op2 = be_transform_node(op2);
1218 ir_graph *irg = current_ir_graph;
1219 dbg_info *dbgi = get_irn_dbg_info(node);
1220 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1221 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1224 if (USE_SSE2(env_cg)) {
1225 ir_mode *mode = get_irn_mode(op1);
1226 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1228 set_ia32_ls_mode(new_op, mode);
1230 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1231 new_op2, get_fpcw());
1233 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1239 * Creates an ia32 Shl.
1241 * @return The created ia32 Shl node
1243 static ir_node *gen_Shl(ir_node *node) {
1244 ir_node *right = get_Shl_right(node);
1246 /* test whether we can build a lea */
1247 if(is_Const(right)) {
1248 tarval *tv = get_Const_tarval(right);
1249 if(tarval_is_long(tv)) {
1250 long val = get_tarval_long(tv);
1251 if(val >= 0 && val <= 3) {
1252 ir_graph *irg = current_ir_graph;
1253 dbg_info *dbgi = get_irn_dbg_info(node);
1254 ir_node *block = be_transform_node(get_nodes_block(node));
1255 ir_node *base = ia32_new_NoReg_gp(env_cg);
1256 ir_node *index = be_transform_node(get_Shl_left(node));
1257 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1258 set_ia32_am_scale(res, val);
1259 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1265 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1272 * Creates an ia32 Shr.
1274 * @return The created ia32 Shr node
1276 static ir_node *gen_Shr(ir_node *node) {
1277 return gen_shift_binop(node, get_Shr_left(node),
1278 get_Shr_right(node), new_rd_ia32_Shr);
1284 * Creates an ia32 Sar.
1286 * @return The created ia32 Shrs node
1288 static ir_node *gen_Shrs(ir_node *node) {
1289 ir_node *left = get_Shrs_left(node);
1290 ir_node *right = get_Shrs_right(node);
1291 ir_mode *mode = get_irn_mode(node);
1292 if(is_Const(right) && mode == mode_Is) {
1293 tarval *tv = get_Const_tarval(right);
1294 long val = get_tarval_long(tv);
1296 /* this is a sign extension */
1297 ir_graph *irg = current_ir_graph;
1298 dbg_info *dbgi = get_irn_dbg_info(node);
1299 ir_node *block = be_transform_node(get_nodes_block(node));
1301 ir_node *new_op = be_transform_node(op);
1302 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1303 add_irn_dep(pval, get_irg_frame(irg));
1305 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1309 /* 8 or 16 bit sign extension? */
1310 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1311 ir_node *shl_left = get_Shl_left(left);
1312 ir_node *shl_right = get_Shl_right(left);
1313 if(is_Const(shl_right)) {
1314 tarval *tv1 = get_Const_tarval(right);
1315 tarval *tv2 = get_Const_tarval(shl_right);
1316 if(tv1 == tv2 && tarval_is_long(tv1)) {
1317 long val = get_tarval_long(tv1);
1318 if(val == 16 || val == 24) {
1319 dbg_info *dbgi = get_irn_dbg_info(node);
1320 ir_node *block = get_nodes_block(node);
1330 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1339 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1345 * Creates an ia32 RotL.
1347 * @param op1 The first operator
1348 * @param op2 The second operator
1349 * @return The created ia32 RotL node
1351 static ir_node *gen_RotL(ir_node *node,
1352 ir_node *op1, ir_node *op2) {
1353 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1359 * Creates an ia32 RotR.
1360 * NOTE: There is no RotR with immediate because this would always be a RotL
1361 * "imm-mode_size_bits" which can be pre-calculated.
1363 * @param op1 The first operator
1364 * @param op2 The second operator
1365 * @return The created ia32 RotR node
1367 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1369 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1375 * Creates an ia32 RotR or RotL (depending on the found pattern).
1377 * @return The created ia32 RotL or RotR node
1379 static ir_node *gen_Rot(ir_node *node) {
1380 ir_node *rotate = NULL;
1381 ir_node *op1 = get_Rot_left(node);
1382 ir_node *op2 = get_Rot_right(node);
1384 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1385 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1386 that means we can create a RotR instead of an Add and a RotL */
1388 if (get_irn_op(op2) == op_Add) {
1390 ir_node *left = get_Add_left(add);
1391 ir_node *right = get_Add_right(add);
1392 if (is_Const(right)) {
1393 tarval *tv = get_Const_tarval(right);
1394 ir_mode *mode = get_irn_mode(node);
1395 long bits = get_mode_size_bits(mode);
1397 if (get_irn_op(left) == op_Minus &&
1398 tarval_is_long(tv) &&
1399 get_tarval_long(tv) == bits)
1401 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1402 rotate = gen_RotR(node, op1, get_Minus_op(left));
1407 if (rotate == NULL) {
1408 rotate = gen_RotL(node, op1, op2);
1417 * Transforms a Minus node.
1419 * @param op The Minus operand
1420 * @return The created ia32 Minus node
1422 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1423 ir_node *block = be_transform_node(get_nodes_block(node));
1424 ir_graph *irg = current_ir_graph;
1425 dbg_info *dbgi = get_irn_dbg_info(node);
1426 ir_mode *mode = get_irn_mode(node);
1431 if (mode_is_float(mode)) {
1432 ir_node *new_op = be_transform_node(op);
1433 if (USE_SSE2(env_cg)) {
1434 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1435 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1436 ir_node *nomem = new_rd_NoMem(irg);
1438 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1441 size = get_mode_size_bits(mode);
1442 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1444 set_ia32_am_sc(res, ent);
1445 set_ia32_op_type(res, ia32_AddrModeS);
1446 set_ia32_ls_mode(res, mode);
1448 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1451 res = gen_unop(node, op, new_rd_ia32_Neg);
1454 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1460 * Transforms a Minus node.
1462 * @return The created ia32 Minus node
1464 static ir_node *gen_Minus(ir_node *node) {
1465 return gen_Minus_ex(node, get_Minus_op(node));
1468 static ir_node *create_Immediate_from_int(int val)
1470 ir_graph *irg = current_ir_graph;
1471 ir_node *start_block = get_irg_start_block(irg);
1472 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1473 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1478 static ir_node *gen_bin_Not(ir_node *node)
1480 ir_graph *irg = current_ir_graph;
1481 dbg_info *dbgi = get_irn_dbg_info(node);
1482 ir_node *block = be_transform_node(get_nodes_block(node));
1483 ir_node *op = get_Not_op(node);
1484 ir_node *new_op = be_transform_node(op);
1485 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1486 ir_node *nomem = new_NoMem();
1487 ir_node *one = create_Immediate_from_int(1);
1489 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1493 * Transforms a Not node.
1495 * @return The created ia32 Not node
1497 static ir_node *gen_Not(ir_node *node) {
1498 ir_node *op = get_Not_op(node);
1499 ir_mode *mode = get_irn_mode(node);
1501 if(mode == mode_b) {
1502 return gen_bin_Not(node);
1505 assert (! mode_is_float(get_irn_mode(node)));
1506 return gen_unop(node, op, new_rd_ia32_Not);
1512 * Transforms an Abs node.
1514 * @return The created ia32 Abs node
1516 static ir_node *gen_Abs(ir_node *node) {
1517 ir_node *block = be_transform_node(get_nodes_block(node));
1518 ir_node *op = get_Abs_op(node);
1519 ir_node *new_op = be_transform_node(op);
1520 ir_graph *irg = current_ir_graph;
1521 dbg_info *dbgi = get_irn_dbg_info(node);
1522 ir_mode *mode = get_irn_mode(node);
1523 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1524 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1525 ir_node *nomem = new_NoMem();
1530 if (mode_is_float(mode)) {
1531 if (USE_SSE2(env_cg)) {
1532 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1534 size = get_mode_size_bits(mode);
1535 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1537 set_ia32_am_sc(res, ent);
1539 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1541 set_ia32_op_type(res, ia32_AddrModeS);
1542 set_ia32_ls_mode(res, mode);
1545 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1546 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1550 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1551 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1554 add_irn_dep(pval, get_irg_frame(irg));
1555 SET_IA32_ORIG_NODE(sign_extension,
1556 ia32_get_old_node_name(env_cg, node));
1558 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1560 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1562 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1564 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1571 * Transforms a Load.
1573 * @return the created ia32 Load node
1575 static ir_node *gen_Load(ir_node *node) {
1576 ir_node *old_block = get_nodes_block(node);
1577 ir_node *block = be_transform_node(old_block);
1578 ir_node *ptr = get_Load_ptr(node);
1579 ir_node *mem = get_Load_mem(node);
1580 ir_node *new_mem = be_transform_node(mem);
1583 ir_graph *irg = current_ir_graph;
1584 dbg_info *dbgi = get_irn_dbg_info(node);
1585 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1586 ir_mode *mode = get_Load_mode(node);
1589 ia32_address_t addr;
1591 /* construct load address */
1592 memset(&addr, 0, sizeof(addr));
1593 ia32_create_address_mode(&addr, ptr, 0);
1600 base = be_transform_node(base);
1606 index = be_transform_node(index);
1609 if (mode_is_float(mode)) {
1610 if (USE_SSE2(env_cg)) {
1611 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1613 res_mode = mode_xmm;
1615 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1617 res_mode = mode_vfp;
1623 /* create a conv node with address mode for smaller modes */
1624 if(get_mode_size_bits(mode) < 32) {
1625 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem,
1628 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1633 set_irn_pinned(new_op, get_irn_pinned(node));
1634 set_ia32_op_type(new_op, ia32_AddrModeS);
1635 set_ia32_ls_mode(new_op, mode);
1636 set_address(new_op, &addr);
1638 /* make sure we are scheduled behind the initial IncSP/Barrier
1639 * to avoid spills being placed before it
1641 if (block == get_irg_start_block(irg)) {
1642 add_irn_dep(new_op, get_irg_frame(irg));
1645 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1646 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1651 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1652 ir_node *ptr, ir_mode *mode, ir_node *other)
1659 /* we only use address mode if we're the only user of the load */
1660 if(get_irn_n_edges(node) > 1)
1663 load = get_Proj_pred(node);
1666 if(get_nodes_block(load) != block)
1669 /* Store should be attached to the load */
1670 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1672 /* store should have the same pointer as the load */
1673 if(get_Load_ptr(load) != ptr)
1676 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1677 if(other != NULL && get_nodes_block(other) == block
1678 && heights_reachable_in_block(heights, other, load))
1681 assert(get_Load_mode(load) == mode);
1686 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1687 ir_node *mem, ir_node *ptr, ir_mode *mode,
1688 construct_binop_dest_func *func, int commutative)
1690 ir_node *src_block = get_nodes_block(node);
1692 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1693 ir_graph *irg = current_ir_graph;
1697 ia32_address_mode_t am;
1698 ia32_address_t *addr = &am.addr;
1699 memset(&am, 0, sizeof(am));
1701 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1702 build_address(&am, op1);
1703 new_op = create_immediate_or_transform(op2, 0);
1704 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1705 build_address(&am, op2);
1706 new_op = create_immediate_or_transform(op1, 0);
1711 if(addr->base == NULL)
1712 addr->base = noreg_gp;
1713 if(addr->index == NULL)
1714 addr->index = noreg_gp;
1715 if(addr->mem == NULL)
1716 addr->mem = new_NoMem();
1718 dbgi = get_irn_dbg_info(node);
1719 block = be_transform_node(src_block);
1720 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, new_op);
1721 set_address(new_node, addr);
1722 set_ia32_op_type(new_node, ia32_AddrModeD);
1723 set_ia32_ls_mode(new_node, mode);
1724 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1729 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1730 ir_node *ptr, ir_mode *mode,
1731 construct_unop_dest_func *func)
1733 ir_node *src_block = get_nodes_block(node);
1735 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1736 ir_graph *irg = current_ir_graph;
1739 ia32_address_mode_t am;
1740 ia32_address_t *addr = &am.addr;
1741 memset(&am, 0, sizeof(am));
1743 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1746 build_address(&am, op);
1748 if(addr->base == NULL)
1749 addr->base = noreg_gp;
1750 if(addr->index == NULL)
1751 addr->index = noreg_gp;
1752 if(addr->mem == NULL)
1753 addr->mem = new_NoMem();
1755 dbgi = get_irn_dbg_info(node);
1756 block = be_transform_node(src_block);
1757 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1758 set_address(new_node, addr);
1759 set_ia32_op_type(new_node, ia32_AddrModeD);
1760 set_ia32_ls_mode(new_node, mode);
1761 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1766 static ir_node *try_create_dest_am(ir_node *node) {
1767 ir_node *val = get_Store_value(node);
1768 ir_node *mem = get_Store_mem(node);
1769 ir_node *ptr = get_Store_ptr(node);
1770 ir_mode *mode = get_irn_mode(val);
1775 /* handle only GP modes for now... */
1776 if(!mode_needs_gp_reg(mode))
1779 /* store must be the only user of the val node */
1780 if(get_irn_n_edges(val) > 1)
1783 switch(get_irn_opcode(val)) {
1785 op1 = get_Add_left(val);
1786 op2 = get_Add_right(val);
1787 if(is_Const_1(op2)) {
1788 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1789 new_rd_ia32_IncMem);
1791 } else if(is_Const_Minus_1(op2)) {
1792 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1793 new_rd_ia32_DecMem);
1796 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1797 new_rd_ia32_AddMem, 1);
1800 op1 = get_Sub_left(val);
1801 op2 = get_Sub_right(val);
1802 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1803 new_rd_ia32_SubMem, 0);
1806 op1 = get_And_left(val);
1807 op2 = get_And_right(val);
1808 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1809 new_rd_ia32_AndMem, 1);
1812 op1 = get_Or_left(val);
1813 op2 = get_Or_right(val);
1814 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1815 new_rd_ia32_OrMem, 1);
1818 op1 = get_Eor_left(val);
1819 op2 = get_Eor_right(val);
1820 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1821 new_rd_ia32_XorMem, 1);
1824 op1 = get_Shl_left(val);
1825 op2 = get_Shl_right(val);
1826 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1827 new_rd_ia32_ShlMem, 0);
1830 op1 = get_Shr_left(val);
1831 op2 = get_Shr_right(val);
1832 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1833 new_rd_ia32_ShrMem, 0);
1836 op1 = get_Shrs_left(val);
1837 op2 = get_Shrs_right(val);
1838 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1839 new_rd_ia32_SarMem, 0);
1842 op1 = get_Rot_left(val);
1843 op2 = get_Rot_right(val);
1844 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1845 new_rd_ia32_RolMem, 0);
1847 /* TODO: match ROR patterns... */
1849 op1 = get_Minus_op(val);
1850 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1853 /* TODO this would be ^ 1 with DestAM */
1856 op1 = get_Not_op(val);
1857 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1867 * Transforms a Store.
1869 * @return the created ia32 Store node
1871 static ir_node *gen_Store(ir_node *node) {
1872 ir_node *block = be_transform_node(get_nodes_block(node));
1873 ir_node *ptr = get_Store_ptr(node);
1876 ir_node *val = get_Store_value(node);
1878 ir_node *mem = get_Store_mem(node);
1879 ir_node *new_mem = be_transform_node(mem);
1880 ir_graph *irg = current_ir_graph;
1881 dbg_info *dbgi = get_irn_dbg_info(node);
1882 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1883 ir_mode *mode = get_irn_mode(val);
1885 ia32_address_t addr;
1887 /* check for destination address mode */
1888 new_op = try_create_dest_am(node);
1892 /* construct store address */
1893 memset(&addr, 0, sizeof(addr));
1894 ia32_create_address_mode(&addr, ptr, 0);
1901 base = be_transform_node(base);
1907 index = be_transform_node(index);
1910 if (mode_is_float(mode)) {
1911 new_val = be_transform_node(val);
1912 if (USE_SSE2(env_cg)) {
1913 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1916 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1920 new_val = create_immediate_or_transform(val, 0);
1924 if (get_mode_size_bits(mode) == 8) {
1925 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1928 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1933 set_irn_pinned(new_op, get_irn_pinned(node));
1934 set_ia32_op_type(new_op, ia32_AddrModeD);
1935 set_ia32_ls_mode(new_op, mode);
1937 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1938 set_address(new_op, &addr);
1939 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1944 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1945 ir_node *cmp_left, ir_node *cmp_right,
1952 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1953 ia32_address_mode_t am;
1954 ia32_address_t *addr = &am.addr;
1956 if(cmp_right != NULL && !is_Const_0(cmp_right))
1959 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1960 mode = get_irn_mode(cmp_left);
1961 arg_left = get_And_left(cmp_left);
1962 arg_right = get_And_right(cmp_left);
1964 mode = get_irn_mode(cmp_left);
1965 arg_left = cmp_left;
1966 arg_right = cmp_left;
1972 assert(get_mode_size_bits(mode) <= 32);
1973 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
1975 pnc = get_inversed_pnc(pnc);
1977 if(get_mode_size_bits(mode) == 8) {
1978 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1979 addr->index, addr->mem, am.new_op1,
1982 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1983 addr->index, addr->mem, am.new_op1, am.new_op2,
1986 set_am_attributes(res, &am);
1987 set_ia32_ls_mode(res, mode);
1989 res = fix_mem_proj(res, &am);
1994 static ir_node *create_Switch(ir_node *node)
1996 ir_graph *irg = current_ir_graph;
1997 dbg_info *dbgi = get_irn_dbg_info(node);
1998 ir_node *block = be_transform_node(get_nodes_block(node));
1999 ir_node *sel = get_Cond_selector(node);
2000 ir_node *new_sel = be_transform_node(sel);
2002 int switch_min = INT_MAX;
2003 const ir_edge_t *edge;
2005 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2007 /* determine the smallest switch case value */
2008 foreach_out_edge(node, edge) {
2009 ir_node *proj = get_edge_src_irn(edge);
2010 int pn = get_Proj_proj(proj);
2015 if (switch_min != 0) {
2016 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2018 /* if smallest switch case is not 0 we need an additional sub */
2019 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2020 add_ia32_am_offs_int(new_sel, -switch_min);
2021 set_ia32_op_type(new_sel, ia32_AddrModeS);
2023 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2026 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2027 set_ia32_pncode(res, get_Cond_defaultProj(node));
2029 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2035 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2037 * @return The transformed node.
2039 static ir_node *gen_Cond(ir_node *node) {
2040 ir_node *src_block = get_nodes_block(node);
2041 ir_node *block = be_transform_node(src_block);
2042 ir_graph *irg = current_ir_graph;
2043 dbg_info *dbgi = get_irn_dbg_info(node);
2044 ir_node *sel = get_Cond_selector(node);
2045 ir_mode *sel_mode = get_irn_mode(sel);
2046 ir_node *res = NULL;
2047 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2048 ir_node *nomem = new_NoMem();
2058 if (sel_mode != mode_b) {
2059 return create_Switch(node);
2062 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2063 /* it's some mode_b value but not a direct comparison -> create a
2065 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2066 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2070 /* address mode makes only sense when we're the only user of the cmp */
2071 use_am = get_irn_n_edges(node) <= 1;
2073 cmp = get_Proj_pred(sel);
2074 cmp_a = get_Cmp_left(cmp);
2075 cmp_b = get_Cmp_right(cmp);
2076 cmp_mode = get_irn_mode(cmp_a);
2077 pnc = get_Proj_proj(sel);
2078 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2079 pnc |= ia32_pn_Cmp_Unsigned;
2082 if(mode_needs_gp_reg(cmp_mode)) {
2083 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2085 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2090 if (mode_is_float(cmp_mode)) {
2091 new_cmp_a = be_transform_node(cmp_a);
2092 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2093 if (USE_SSE2(env_cg)) {
2094 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, nomem, cmp_a,
2096 set_ia32_commutative(res);
2097 set_ia32_ls_mode(res, cmp_mode);
2099 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2100 set_ia32_commutative(res);
2103 ia32_address_mode_t am;
2104 ia32_address_t *addr = &am.addr;
2105 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am, 1);
2107 pnc = get_inversed_pnc(pnc);
2109 if(get_mode_size_bits(cmp_mode) == 8) {
2110 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base, addr->index,
2111 addr->mem, am.new_op1, am.new_op2, pnc);
2113 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2114 addr->mem, am.new_op1, am.new_op2, pnc);
2116 set_am_attributes(res, &am);
2117 assert(cmp_mode != NULL);
2118 set_ia32_ls_mode(res, cmp_mode);
2120 res = fix_mem_proj(res, &am);
2123 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2131 * Transforms a CopyB node.
2133 * @return The transformed node.
2135 static ir_node *gen_CopyB(ir_node *node) {
2136 ir_node *block = be_transform_node(get_nodes_block(node));
2137 ir_node *src = get_CopyB_src(node);
2138 ir_node *new_src = be_transform_node(src);
2139 ir_node *dst = get_CopyB_dst(node);
2140 ir_node *new_dst = be_transform_node(dst);
2141 ir_node *mem = get_CopyB_mem(node);
2142 ir_node *new_mem = be_transform_node(mem);
2143 ir_node *res = NULL;
2144 ir_graph *irg = current_ir_graph;
2145 dbg_info *dbgi = get_irn_dbg_info(node);
2146 int size = get_type_size_bytes(get_CopyB_type(node));
2149 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2150 /* then we need the size explicitly in ECX. */
2151 if (size >= 32 * 4) {
2152 rem = size & 0x3; /* size % 4 */
2155 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2156 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2158 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2159 /* we misuse the pncode field for the copyb size */
2160 set_ia32_pncode(res, rem);
2162 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2163 set_ia32_pncode(res, size);
2166 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2172 ir_node *gen_be_Copy(ir_node *node)
2174 ir_node *result = be_duplicate_node(node);
2175 ir_mode *mode = get_irn_mode(result);
2177 if (mode_needs_gp_reg(mode)) {
2178 set_irn_mode(result, mode_Iu);
2185 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2186 dbg_info *dbgi, ir_node *block, int use_am)
2188 ir_graph *irg = current_ir_graph;
2189 ir_node *new_block = be_transform_node(block);
2190 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2191 ir_node *nomem = new_rd_NoMem(irg);
2196 ia32_address_mode_t am;
2197 ia32_address_t *addr = &am.addr;
2199 /* can we use a test instruction? */
2200 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2201 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2202 if(is_And(cmp_left) &&
2203 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2204 ir_node *and_left = get_And_left(cmp_left);
2205 ir_node *and_right = get_And_right(cmp_left);
2207 mode = get_irn_mode(and_left);
2208 arg_left = and_left;
2209 arg_right = and_right;
2211 mode = get_irn_mode(cmp_left);
2212 arg_left = cmp_left;
2213 arg_right = cmp_left;
2216 assert(get_mode_size_bits(mode) <= 32);
2218 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
2220 pnc = get_inversed_pnc(pnc);
2222 if(get_mode_size_bits(mode) == 8) {
2223 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2224 addr->index, addr->mem, am.new_op1,
2227 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base, addr->index,
2228 addr->mem, am.new_op1, am.new_op2, pnc);
2230 set_am_attributes(res, &am);
2231 set_ia32_ls_mode(res, mode);
2233 res = fix_mem_proj(res, &am);
2235 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2241 mode = get_irn_mode(cmp_left);
2242 assert(get_mode_size_bits(mode) <= 32);
2244 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am, 1);
2246 pnc = get_inversed_pnc(pnc);
2248 if(get_mode_size_bits(mode) == 8) {
2249 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base, addr->index,
2250 addr->mem, am.new_op1, am.new_op2, pnc);
2252 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2253 addr->mem, am.new_op1, am.new_op2, pnc);
2255 set_am_attributes(res, &am);
2256 set_ia32_ls_mode(res, mode);
2258 res = fix_mem_proj(res, &am);
2260 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, res,
2266 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2267 ir_node *val_true, ir_node *val_false,
2268 dbg_info *dbgi, ir_node *block)
2270 ir_graph *irg = current_ir_graph;
2271 ir_node *new_block = be_transform_node(block);
2272 ir_node *new_val_true = be_transform_node(val_true);
2273 ir_node *new_val_false = be_transform_node(val_false);
2274 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2275 ir_node *nomem = new_NoMem();
2276 ir_node *new_cmp_left;
2277 ir_node *new_cmp_right;
2281 /* cmovs with unknowns are pointless... */
2282 if(is_Unknown(val_true)) {
2283 #ifdef DEBUG_libfirm
2284 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2286 return new_val_false;
2288 if(is_Unknown(val_false)) {
2289 #ifdef DEBUG_libfirm
2290 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2292 return new_val_true;
2295 /* can we use a test instruction? */
2296 if(is_Const_0(cmp_right)) {
2297 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2298 if(is_And(cmp_left) &&
2299 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2300 ir_node *and_left = get_And_left(cmp_left);
2301 ir_node *and_right = get_And_right(cmp_left);
2303 mode = get_irn_mode(and_left);
2304 new_cmp_left = be_transform_node(and_left);
2305 new_cmp_right = create_immediate_or_transform(and_right, 0);
2307 mode = get_irn_mode(cmp_left);
2308 new_cmp_left = be_transform_node(cmp_left);
2309 new_cmp_right = be_transform_node(cmp_left);
2312 assert(get_mode_size_bits(mode) <= 32);
2314 if(get_mode_size_bits(mode) == 8) {
2315 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block, noreg,
2316 noreg, nomem, new_cmp_left, new_cmp_right,
2317 new_val_true, new_val_false, pnc);
2319 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2320 noreg, nomem, new_cmp_left, new_cmp_right,
2321 new_val_true, new_val_false, pnc);
2323 set_ia32_ls_mode(res, mode);
2328 mode = get_irn_mode(cmp_left);
2329 new_cmp_left = be_transform_node(cmp_left);
2330 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2332 /* no support for 8,16 bit modes yet */
2333 assert(get_mode_size_bits(mode) <= 32);
2335 if(get_mode_size_bits(mode) == 8) {
2336 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2337 new_cmp_left, new_cmp_right, new_val_true,
2338 new_val_false, pnc);
2340 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg, nomem,
2341 new_cmp_left, new_cmp_right, new_val_true,
2342 new_val_false, pnc);
2344 set_ia32_ls_mode(res, mode);
2351 * Transforms a Psi node into CMov.
2353 * @return The transformed node.
2355 static ir_node *gen_Psi(ir_node *node) {
2356 ir_node *psi_true = get_Psi_val(node, 0);
2357 ir_node *psi_default = get_Psi_default(node);
2358 ia32_code_gen_t *cg = env_cg;
2359 ir_node *cond = get_Psi_cond(node, 0);
2360 ir_node *block = get_nodes_block(node);
2361 dbg_info *dbgi = get_irn_dbg_info(node);
2368 assert(get_Psi_n_conds(node) == 1);
2369 assert(get_irn_mode(cond) == mode_b);
2370 assert(mode_needs_gp_reg(get_irn_mode(node)));
2372 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2373 /* a mode_b value, we have to compare it against 0 */
2375 cmp_right = new_Const_long(mode_Iu, 0);
2379 ir_node *cmp = get_Proj_pred(cond);
2381 cmp_left = get_Cmp_left(cmp);
2382 cmp_right = get_Cmp_right(cmp);
2383 cmp_mode = get_irn_mode(cmp_left);
2384 pnc = get_Proj_proj(cond);
2386 assert(!mode_is_float(cmp_mode));
2388 if (!mode_is_signed(cmp_mode)) {
2389 pnc |= ia32_pn_Cmp_Unsigned;
2393 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2394 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2395 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2396 pnc = get_negated_pnc(pnc, cmp_mode);
2397 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2399 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2402 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2408 * Create a conversion from x87 state register to general purpose.
2410 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2411 ir_node *block = be_transform_node(get_nodes_block(node));
2412 ir_node *op = get_Conv_op(node);
2413 ir_node *new_op = be_transform_node(op);
2414 ia32_code_gen_t *cg = env_cg;
2415 ir_graph *irg = current_ir_graph;
2416 dbg_info *dbgi = get_irn_dbg_info(node);
2417 ir_node *noreg = ia32_new_NoReg_gp(cg);
2418 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2419 ir_mode *mode = get_irn_mode(node);
2420 ir_node *fist, *load;
2423 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2424 new_NoMem(), new_op, trunc_mode);
2426 set_irn_pinned(fist, op_pin_state_floats);
2427 set_ia32_use_frame(fist);
2428 set_ia32_op_type(fist, ia32_AddrModeD);
2430 assert(get_mode_size_bits(mode) <= 32);
2431 /* exception we can only store signed 32 bit integers, so for unsigned
2432 we store a 64bit (signed) integer and load the lower bits */
2433 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2434 set_ia32_ls_mode(fist, mode_Ls);
2436 set_ia32_ls_mode(fist, mode_Is);
2438 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2441 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2443 set_irn_pinned(load, op_pin_state_floats);
2444 set_ia32_use_frame(load);
2445 set_ia32_op_type(load, ia32_AddrModeS);
2446 set_ia32_ls_mode(load, mode_Is);
2447 if(get_ia32_ls_mode(fist) == mode_Ls) {
2448 ia32_attr_t *attr = get_ia32_attr(load);
2449 attr->data.need_64bit_stackent = 1;
2451 ia32_attr_t *attr = get_ia32_attr(load);
2452 attr->data.need_32bit_stackent = 1;
2454 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2456 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2460 * Creates a x87 strict Conv by placing a Sore and a Load
2462 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2464 ir_node *block = get_nodes_block(node);
2465 ir_graph *irg = current_ir_graph;
2466 dbg_info *dbgi = get_irn_dbg_info(node);
2467 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2468 ir_node *nomem = new_NoMem();
2469 ir_node *frame = get_irg_frame(irg);
2470 ir_node *store, *load;
2473 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2475 set_ia32_use_frame(store);
2476 set_ia32_op_type(store, ia32_AddrModeD);
2477 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2479 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2481 set_ia32_use_frame(load);
2482 set_ia32_op_type(load, ia32_AddrModeS);
2483 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2485 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2490 * Create a conversion from general purpose to x87 register
2492 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2493 ir_node *block = be_transform_node(get_nodes_block(node));
2494 ir_node *op = get_Conv_op(node);
2495 ir_node *new_op = be_transform_node(op);
2496 ir_graph *irg = current_ir_graph;
2497 dbg_info *dbgi = get_irn_dbg_info(node);
2498 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2499 ir_node *nomem = new_NoMem();
2500 ir_mode *mode = get_irn_mode(op);
2501 ir_mode *store_mode;
2502 ir_node *fild, *store;
2506 /* first convert to 32 bit signed if necessary */
2507 src_bits = get_mode_size_bits(src_mode);
2508 if (src_bits == 8) {
2509 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2511 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2513 } else if (src_bits < 32) {
2514 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2516 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2520 assert(get_mode_size_bits(mode) == 32);
2523 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2526 set_ia32_use_frame(store);
2527 set_ia32_op_type(store, ia32_AddrModeD);
2528 set_ia32_ls_mode(store, mode_Iu);
2530 /* exception for 32bit unsigned, do a 64bit spill+load */
2531 if(!mode_is_signed(mode)) {
2534 ir_node *zero_const = create_Immediate_from_int(0);
2536 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2537 get_irg_frame(irg), noreg, nomem,
2540 set_ia32_use_frame(zero_store);
2541 set_ia32_op_type(zero_store, ia32_AddrModeD);
2542 add_ia32_am_offs_int(zero_store, 4);
2543 set_ia32_ls_mode(zero_store, mode_Iu);
2548 store = new_rd_Sync(dbgi, irg, block, 2, in);
2549 store_mode = mode_Ls;
2551 store_mode = mode_Is;
2555 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2557 set_ia32_use_frame(fild);
2558 set_ia32_op_type(fild, ia32_AddrModeS);
2559 set_ia32_ls_mode(fild, store_mode);
2561 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2567 * Crete a conversion from one integer mode into another one
2569 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2570 dbg_info *dbgi, ir_node *block, ir_node *op,
2573 ir_graph *irg = current_ir_graph;
2574 int src_bits = get_mode_size_bits(src_mode);
2575 int tgt_bits = get_mode_size_bits(tgt_mode);
2576 ir_node *new_block = be_transform_node(block);
2577 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2580 ir_mode *smaller_mode;
2582 ia32_address_mode_t am;
2583 ia32_address_t *addr = &am.addr;
2585 if (src_bits < tgt_bits) {
2586 smaller_mode = src_mode;
2587 smaller_bits = src_bits;
2589 smaller_mode = tgt_mode;
2590 smaller_bits = tgt_bits;
2593 memset(&am, 0, sizeof(am));
2594 if(use_source_address_mode(block, op, NULL)) {
2595 build_address(&am, op);
2597 am.op_type = ia32_AddrModeS;
2599 new_op = be_transform_node(op);
2600 am.op_type = ia32_Normal;
2602 if(addr->base == NULL)
2604 if(addr->index == NULL)
2605 addr->index = noreg;
2606 if(addr->mem == NULL)
2607 addr->mem = new_NoMem();
2609 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2610 if (smaller_bits == 8) {
2611 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2612 addr->index, addr->mem, new_op,
2615 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2616 addr->index, addr->mem, new_op,
2620 set_am_attributes(res, &am);
2621 set_ia32_ls_mode(res, smaller_mode);
2622 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2623 res = fix_mem_proj(res, &am);
2629 * Transforms a Conv node.
2631 * @return The created ia32 Conv node
2633 static ir_node *gen_Conv(ir_node *node) {
2634 ir_node *block = get_nodes_block(node);
2635 ir_node *new_block = be_transform_node(block);
2636 ir_node *op = get_Conv_op(node);
2637 ir_node *new_op = NULL;
2638 ir_graph *irg = current_ir_graph;
2639 dbg_info *dbgi = get_irn_dbg_info(node);
2640 ir_mode *src_mode = get_irn_mode(op);
2641 ir_mode *tgt_mode = get_irn_mode(node);
2642 int src_bits = get_mode_size_bits(src_mode);
2643 int tgt_bits = get_mode_size_bits(tgt_mode);
2644 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2645 ir_node *nomem = new_rd_NoMem(irg);
2646 ir_node *res = NULL;
2648 if (src_mode == mode_b) {
2649 assert(mode_is_int(tgt_mode));
2650 /* nothing to do, we already model bools as 0/1 ints */
2651 return be_transform_node(op);
2654 if (src_mode == tgt_mode) {
2655 if (get_Conv_strict(node)) {
2656 if (USE_SSE2(env_cg)) {
2657 /* when we are in SSE mode, we can kill all strict no-op conversion */
2658 return be_transform_node(op);
2661 /* this should be optimized already, but who knows... */
2662 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2663 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2664 return be_transform_node(op);
2668 if (mode_is_float(src_mode)) {
2669 new_op = be_transform_node(op);
2670 /* we convert from float ... */
2671 if (mode_is_float(tgt_mode)) {
2672 if(src_mode == mode_E && tgt_mode == mode_D
2673 && !get_Conv_strict(node)) {
2674 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2679 if (USE_SSE2(env_cg)) {
2680 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2681 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2683 set_ia32_ls_mode(res, tgt_mode);
2685 if(get_Conv_strict(node)) {
2686 res = gen_x87_strict_conv(tgt_mode, new_op);
2687 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2690 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2695 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2696 if (USE_SSE2(env_cg)) {
2697 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2699 set_ia32_ls_mode(res, src_mode);
2701 return gen_x87_fp_to_gp(node);
2705 /* we convert from int ... */
2706 if (mode_is_float(tgt_mode)) {
2708 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2709 if (USE_SSE2(env_cg)) {
2710 new_op = be_transform_node(op);
2711 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2713 set_ia32_ls_mode(res, tgt_mode);
2715 res = gen_x87_gp_to_fp(node, src_mode);
2716 if(get_Conv_strict(node)) {
2717 res = gen_x87_strict_conv(tgt_mode, res);
2718 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2719 ia32_get_old_node_name(env_cg, node));
2723 } else if(tgt_mode == mode_b) {
2724 /* mode_b lowering already took care that we only have 0/1 values */
2725 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2726 src_mode, tgt_mode));
2727 return be_transform_node(op);
2730 if (src_bits == tgt_bits) {
2731 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2732 src_mode, tgt_mode));
2733 return be_transform_node(op);
2736 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2745 int check_immediate_constraint(long val, char immediate_constraint_type)
2747 switch (immediate_constraint_type) {
2751 return val >= 0 && val <= 32;
2753 return val >= 0 && val <= 63;
2755 return val >= -128 && val <= 127;
2757 return val == 0xff || val == 0xffff;
2759 return val >= 0 && val <= 3;
2761 return val >= 0 && val <= 255;
2763 return val >= 0 && val <= 127;
2767 panic("Invalid immediate constraint found");
2772 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2775 tarval *offset = NULL;
2776 int offset_sign = 0;
2778 ir_entity *symconst_ent = NULL;
2779 int symconst_sign = 0;
2781 ir_node *cnst = NULL;
2782 ir_node *symconst = NULL;
2788 mode = get_irn_mode(node);
2789 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2793 if(is_Minus(node)) {
2795 node = get_Minus_op(node);
2798 if(is_Const(node)) {
2801 offset_sign = minus;
2802 } else if(is_SymConst(node)) {
2805 symconst_sign = minus;
2806 } else if(is_Add(node)) {
2807 ir_node *left = get_Add_left(node);
2808 ir_node *right = get_Add_right(node);
2809 if(is_Const(left) && is_SymConst(right)) {
2812 symconst_sign = minus;
2813 offset_sign = minus;
2814 } else if(is_SymConst(left) && is_Const(right)) {
2817 symconst_sign = minus;
2818 offset_sign = minus;
2820 } else if(is_Sub(node)) {
2821 ir_node *left = get_Sub_left(node);
2822 ir_node *right = get_Sub_right(node);
2823 if(is_Const(left) && is_SymConst(right)) {
2826 symconst_sign = !minus;
2827 offset_sign = minus;
2828 } else if(is_SymConst(left) && is_Const(right)) {
2831 symconst_sign = minus;
2832 offset_sign = !minus;
2839 offset = get_Const_tarval(cnst);
2840 if(tarval_is_long(offset)) {
2841 val = get_tarval_long(offset);
2842 } else if(tarval_is_null(offset)) {
2845 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2850 if(!check_immediate_constraint(val, immediate_constraint_type))
2853 if(symconst != NULL) {
2854 if(immediate_constraint_type != 0) {
2855 /* we need full 32bits for symconsts */
2859 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2861 symconst_ent = get_SymConst_entity(symconst);
2863 if(cnst == NULL && symconst == NULL)
2866 if(offset_sign && offset != NULL) {
2867 offset = tarval_neg(offset);
2870 irg = current_ir_graph;
2871 dbgi = get_irn_dbg_info(node);
2872 block = get_irg_start_block(irg);
2873 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2874 symconst_sign, val);
2875 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2881 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2883 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2884 if (new_node == NULL) {
2885 new_node = be_transform_node(node);
2890 typedef struct constraint_t constraint_t;
2891 struct constraint_t {
2894 const arch_register_req_t **out_reqs;
2896 const arch_register_req_t *req;
2897 unsigned immediate_possible;
2898 char immediate_type;
2901 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2903 int immediate_possible = 0;
2904 char immediate_type = 0;
2905 unsigned limited = 0;
2906 const arch_register_class_t *cls = NULL;
2907 ir_graph *irg = current_ir_graph;
2908 struct obstack *obst = get_irg_obstack(irg);
2909 arch_register_req_t *req;
2910 unsigned *limited_ptr;
2914 /* TODO: replace all the asserts with nice error messages */
2916 printf("Constraint: %s\n", c);
2926 assert(cls == NULL ||
2927 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2928 cls = &ia32_reg_classes[CLASS_ia32_gp];
2929 limited |= 1 << REG_EAX;
2932 assert(cls == NULL ||
2933 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2934 cls = &ia32_reg_classes[CLASS_ia32_gp];
2935 limited |= 1 << REG_EBX;
2938 assert(cls == NULL ||
2939 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2940 cls = &ia32_reg_classes[CLASS_ia32_gp];
2941 limited |= 1 << REG_ECX;
2944 assert(cls == NULL ||
2945 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2946 cls = &ia32_reg_classes[CLASS_ia32_gp];
2947 limited |= 1 << REG_EDX;
2950 assert(cls == NULL ||
2951 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2952 cls = &ia32_reg_classes[CLASS_ia32_gp];
2953 limited |= 1 << REG_EDI;
2956 assert(cls == NULL ||
2957 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2958 cls = &ia32_reg_classes[CLASS_ia32_gp];
2959 limited |= 1 << REG_ESI;
2962 case 'q': /* q means lower part of the regs only, this makes no
2963 * difference to Q for us (we only assigne whole registers) */
2964 assert(cls == NULL ||
2965 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2966 cls = &ia32_reg_classes[CLASS_ia32_gp];
2967 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2971 assert(cls == NULL ||
2972 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2973 cls = &ia32_reg_classes[CLASS_ia32_gp];
2974 limited |= 1 << REG_EAX | 1 << REG_EDX;
2977 assert(cls == NULL ||
2978 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2979 cls = &ia32_reg_classes[CLASS_ia32_gp];
2980 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2981 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2988 assert(cls == NULL);
2989 cls = &ia32_reg_classes[CLASS_ia32_gp];
2995 /* TODO: mark values so the x87 simulator knows about t and u */
2996 assert(cls == NULL);
2997 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3002 assert(cls == NULL);
3003 /* TODO: check that sse2 is supported */
3004 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3014 assert(!immediate_possible);
3015 immediate_possible = 1;
3016 immediate_type = *c;
3020 assert(!immediate_possible);
3021 immediate_possible = 1;
3025 assert(!immediate_possible && cls == NULL);
3026 immediate_possible = 1;
3027 cls = &ia32_reg_classes[CLASS_ia32_gp];
3040 assert(constraint->is_in && "can only specify same constraint "
3043 sscanf(c, "%d%n", &same_as, &p);
3050 case 'E': /* no float consts yet */
3051 case 'F': /* no float consts yet */
3052 case 's': /* makes no sense on x86 */
3053 case 'X': /* we can't support that in firm */
3057 case '<': /* no autodecrement on x86 */
3058 case '>': /* no autoincrement on x86 */
3059 case 'C': /* sse constant not supported yet */
3060 case 'G': /* 80387 constant not supported yet */
3061 case 'y': /* we don't support mmx registers yet */
3062 case 'Z': /* not available in 32 bit mode */
3063 case 'e': /* not available in 32 bit mode */
3064 assert(0 && "asm constraint not supported");
3067 assert(0 && "unknown asm constraint found");
3074 const arch_register_req_t *other_constr;
3076 assert(cls == NULL && "same as and register constraint not supported");
3077 assert(!immediate_possible && "same as and immediate constraint not "
3079 assert(same_as < constraint->n_outs && "wrong constraint number in "
3080 "same_as constraint");
3082 other_constr = constraint->out_reqs[same_as];
3084 req = obstack_alloc(obst, sizeof(req[0]));
3085 req->cls = other_constr->cls;
3086 req->type = arch_register_req_type_should_be_same;
3087 req->limited = NULL;
3088 req->other_same = pos;
3089 req->other_different = -1;
3091 /* switch constraints. This is because in firm we have same_as
3092 * constraints on the output constraints while in the gcc asm syntax
3093 * they are specified on the input constraints */
3094 constraint->req = other_constr;
3095 constraint->out_reqs[same_as] = req;
3096 constraint->immediate_possible = 0;
3100 if(immediate_possible && cls == NULL) {
3101 cls = &ia32_reg_classes[CLASS_ia32_gp];
3103 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3104 assert(cls != NULL);
3106 if(immediate_possible) {
3107 assert(constraint->is_in
3108 && "imeediates make no sense for output constraints");
3110 /* todo: check types (no float input on 'r' constrained in and such... */
3113 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3114 limited_ptr = (unsigned*) (req+1);
3116 req = obstack_alloc(obst, sizeof(req[0]));
3118 memset(req, 0, sizeof(req[0]));
3121 req->type = arch_register_req_type_limited;
3122 *limited_ptr = limited;
3123 req->limited = limited_ptr;
3125 req->type = arch_register_req_type_normal;
3129 constraint->req = req;
3130 constraint->immediate_possible = immediate_possible;
3131 constraint->immediate_type = immediate_type;
3135 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3142 panic("Clobbers not supported yet");
3146 * generates code for a ASM node
3148 static ir_node *gen_ASM(ir_node *node)
3151 ir_graph *irg = current_ir_graph;
3152 ir_node *block = be_transform_node(get_nodes_block(node));
3153 dbg_info *dbgi = get_irn_dbg_info(node);
3160 ia32_asm_attr_t *attr;
3161 const arch_register_req_t **out_reqs;
3162 const arch_register_req_t **in_reqs;
3163 struct obstack *obst;
3164 constraint_t parsed_constraint;
3166 /* transform inputs */
3167 arity = get_irn_arity(node);
3168 in = alloca(arity * sizeof(in[0]));
3169 memset(in, 0, arity * sizeof(in[0]));
3171 n_outs = get_ASM_n_output_constraints(node);
3172 n_clobbers = get_ASM_n_clobbers(node);
3173 out_arity = n_outs + n_clobbers;
3175 /* construct register constraints */
3176 obst = get_irg_obstack(irg);
3177 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3178 parsed_constraint.out_reqs = out_reqs;
3179 parsed_constraint.n_outs = n_outs;
3180 parsed_constraint.is_in = 0;
3181 for(i = 0; i < out_arity; ++i) {
3185 const ir_asm_constraint *constraint;
3186 constraint = & get_ASM_output_constraints(node) [i];
3187 c = get_id_str(constraint->constraint);
3188 parse_asm_constraint(i, &parsed_constraint, c);
3190 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3191 c = get_id_str(glob_id);
3192 parse_clobber(node, i, &parsed_constraint, c);
3194 out_reqs[i] = parsed_constraint.req;
3197 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3198 parsed_constraint.is_in = 1;
3199 for(i = 0; i < arity; ++i) {
3200 const ir_asm_constraint *constraint;
3204 constraint = & get_ASM_input_constraints(node) [i];
3205 constr_id = constraint->constraint;
3206 c = get_id_str(constr_id);
3207 parse_asm_constraint(i, &parsed_constraint, c);
3208 in_reqs[i] = parsed_constraint.req;
3210 if(parsed_constraint.immediate_possible) {
3211 ir_node *pred = get_irn_n(node, i);
3212 char imm_type = parsed_constraint.immediate_type;
3213 ir_node *immediate = try_create_Immediate(pred, imm_type);
3215 if(immediate != NULL) {
3221 /* transform inputs */
3222 for(i = 0; i < arity; ++i) {
3224 ir_node *transformed;
3229 pred = get_irn_n(node, i);
3230 transformed = be_transform_node(pred);
3231 in[i] = transformed;
3234 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3236 generic_attr = get_irn_generic_attr(res);
3237 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3238 attr->asm_text = get_ASM_text(node);
3239 set_ia32_out_req_all(res, out_reqs);
3240 set_ia32_in_req_all(res, in_reqs);
3242 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3247 /********************************************
3250 * | |__ ___ _ __ ___ __| | ___ ___
3251 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3252 * | |_) | __/ | | | (_) | (_| | __/\__ \
3253 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3255 ********************************************/
3258 * Transforms a FrameAddr into an ia32 Add.
3260 static ir_node *gen_be_FrameAddr(ir_node *node) {
3261 ir_node *block = be_transform_node(get_nodes_block(node));
3262 ir_node *op = be_get_FrameAddr_frame(node);
3263 ir_node *new_op = be_transform_node(op);
3264 ir_graph *irg = current_ir_graph;
3265 dbg_info *dbgi = get_irn_dbg_info(node);
3266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3269 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3270 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3271 set_ia32_use_frame(res);
3273 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3279 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3281 static ir_node *gen_be_Return(ir_node *node) {
3282 ir_graph *irg = current_ir_graph;
3283 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3284 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3285 ir_entity *ent = get_irg_entity(irg);
3286 ir_type *tp = get_entity_type(ent);
3291 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3292 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3295 int pn_ret_val, pn_ret_mem, arity, i;
3297 assert(ret_val != NULL);
3298 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3299 return be_duplicate_node(node);
3302 res_type = get_method_res_type(tp, 0);
3304 if (! is_Primitive_type(res_type)) {
3305 return be_duplicate_node(node);
3308 mode = get_type_mode(res_type);
3309 if (! mode_is_float(mode)) {
3310 return be_duplicate_node(node);
3313 assert(get_method_n_ress(tp) == 1);
3315 pn_ret_val = get_Proj_proj(ret_val);
3316 pn_ret_mem = get_Proj_proj(ret_mem);
3318 /* get the Barrier */
3319 barrier = get_Proj_pred(ret_val);
3321 /* get result input of the Barrier */
3322 ret_val = get_irn_n(barrier, pn_ret_val);
3323 new_ret_val = be_transform_node(ret_val);
3325 /* get memory input of the Barrier */
3326 ret_mem = get_irn_n(barrier, pn_ret_mem);
3327 new_ret_mem = be_transform_node(ret_mem);
3329 frame = get_irg_frame(irg);
3331 dbgi = get_irn_dbg_info(barrier);
3332 block = be_transform_node(get_nodes_block(barrier));
3334 noreg = ia32_new_NoReg_gp(env_cg);
3336 /* store xmm0 onto stack */
3337 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3338 new_ret_mem, new_ret_val);
3339 set_ia32_ls_mode(sse_store, mode);
3340 set_ia32_op_type(sse_store, ia32_AddrModeD);
3341 set_ia32_use_frame(sse_store);
3343 /* load into x87 register */
3344 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3345 set_ia32_op_type(fld, ia32_AddrModeS);
3346 set_ia32_use_frame(fld);
3348 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3349 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3351 /* create a new barrier */
3352 arity = get_irn_arity(barrier);
3353 in = alloca(arity * sizeof(in[0]));
3354 for (i = 0; i < arity; ++i) {
3357 if (i == pn_ret_val) {
3359 } else if (i == pn_ret_mem) {
3362 ir_node *in = get_irn_n(barrier, i);
3363 new_in = be_transform_node(in);
3368 new_barrier = new_ir_node(dbgi, irg, block,
3369 get_irn_op(barrier), get_irn_mode(barrier),
3371 copy_node_attr(barrier, new_barrier);
3372 be_duplicate_deps(barrier, new_barrier);
3373 be_set_transformed_node(barrier, new_barrier);
3374 mark_irn_visited(barrier);
3376 /* transform normally */
3377 return be_duplicate_node(node);
3381 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3383 static ir_node *gen_be_AddSP(ir_node *node) {
3384 ir_node *block = be_transform_node(get_nodes_block(node));
3385 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3387 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3388 ir_node *new_sp = be_transform_node(sp);
3389 ir_graph *irg = current_ir_graph;
3390 dbg_info *dbgi = get_irn_dbg_info(node);
3391 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3392 ir_node *nomem = new_NoMem();
3395 new_sz = create_immediate_or_transform(sz, 0);
3397 /* ia32 stack grows in reverse direction, make a SubSP */
3398 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3400 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3406 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3408 static ir_node *gen_be_SubSP(ir_node *node) {
3409 ir_node *block = be_transform_node(get_nodes_block(node));
3410 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3412 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3413 ir_node *new_sp = be_transform_node(sp);
3414 ir_graph *irg = current_ir_graph;
3415 dbg_info *dbgi = get_irn_dbg_info(node);
3416 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3417 ir_node *nomem = new_NoMem();
3420 new_sz = create_immediate_or_transform(sz, 0);
3422 /* ia32 stack grows in reverse direction, make an AddSP */
3423 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3425 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3431 * This function just sets the register for the Unknown node
3432 * as this is not done during register allocation because Unknown
3433 * is an "ignore" node.
3435 static ir_node *gen_Unknown(ir_node *node) {
3436 ir_mode *mode = get_irn_mode(node);
3438 if (mode_is_float(mode)) {
3439 if (USE_SSE2(env_cg)) {
3440 return ia32_new_Unknown_xmm(env_cg);
3442 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3443 ir_graph *irg = current_ir_graph;
3444 dbg_info *dbgi = get_irn_dbg_info(node);
3445 ir_node *block = get_irg_start_block(irg);
3446 return new_rd_ia32_vfldz(dbgi, irg, block);
3448 } else if (mode_needs_gp_reg(mode)) {
3449 return ia32_new_Unknown_gp(env_cg);
3451 assert(0 && "unsupported Unknown-Mode");
3458 * Change some phi modes
3460 static ir_node *gen_Phi(ir_node *node) {
3461 ir_node *block = be_transform_node(get_nodes_block(node));
3462 ir_graph *irg = current_ir_graph;
3463 dbg_info *dbgi = get_irn_dbg_info(node);
3464 ir_mode *mode = get_irn_mode(node);
3467 if(mode_needs_gp_reg(mode)) {
3468 /* we shouldn't have any 64bit stuff around anymore */
3469 assert(get_mode_size_bits(mode) <= 32);
3470 /* all integer operations are on 32bit registers now */
3472 } else if(mode_is_float(mode)) {
3473 if (USE_SSE2(env_cg)) {
3480 /* phi nodes allow loops, so we use the old arguments for now
3481 * and fix this later */
3482 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3483 get_irn_in(node) + 1);
3484 copy_node_attr(node, phi);
3485 be_duplicate_deps(node, phi);
3487 be_set_transformed_node(node, phi);
3488 be_enqueue_preds(node);
3496 static ir_node *gen_IJmp(ir_node *node) {
3497 /* TODO: support AM */
3498 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3502 /**********************************************************************
3505 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3506 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3507 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3508 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3510 **********************************************************************/
3512 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3514 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3517 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3518 ir_node *val, ir_node *mem);
3521 * Transforms a lowered Load into a "real" one.
3523 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3525 ir_node *block = be_transform_node(get_nodes_block(node));
3526 ir_node *ptr = get_irn_n(node, 0);
3527 ir_node *new_ptr = be_transform_node(ptr);
3528 ir_node *mem = get_irn_n(node, 1);
3529 ir_node *new_mem = be_transform_node(mem);
3530 ir_graph *irg = current_ir_graph;
3531 dbg_info *dbgi = get_irn_dbg_info(node);
3532 ir_mode *mode = get_ia32_ls_mode(node);
3533 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3536 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3538 set_ia32_op_type(new_op, ia32_AddrModeS);
3539 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3540 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3541 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3542 if (is_ia32_am_sc_sign(node))
3543 set_ia32_am_sc_sign(new_op);
3544 set_ia32_ls_mode(new_op, mode);
3545 if (is_ia32_use_frame(node)) {
3546 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3547 set_ia32_use_frame(new_op);
3550 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3556 * Transforms a lowered Store into a "real" one.
3558 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3560 ir_node *block = be_transform_node(get_nodes_block(node));
3561 ir_node *ptr = get_irn_n(node, 0);
3562 ir_node *new_ptr = be_transform_node(ptr);
3563 ir_node *val = get_irn_n(node, 1);
3564 ir_node *new_val = be_transform_node(val);
3565 ir_node *mem = get_irn_n(node, 2);
3566 ir_node *new_mem = be_transform_node(mem);
3567 ir_graph *irg = current_ir_graph;
3568 dbg_info *dbgi = get_irn_dbg_info(node);
3569 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3570 ir_mode *mode = get_ia32_ls_mode(node);
3574 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3576 am_offs = get_ia32_am_offs_int(node);
3577 add_ia32_am_offs_int(new_op, am_offs);
3579 set_ia32_op_type(new_op, ia32_AddrModeD);
3580 set_ia32_ls_mode(new_op, mode);
3581 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3582 set_ia32_use_frame(new_op);
3584 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3591 * Transforms an ia32_l_XXX into a "real" XXX node
3593 * @param node The node to transform
3594 * @return the created ia32 XXX node
3596 #define GEN_LOWERED_OP(op) \
3597 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3598 return gen_binop(node, get_binop_left(node), \
3599 get_binop_right(node), new_rd_ia32_##op,0); \
3602 #define GEN_LOWERED_x87_OP(op) \
3603 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3605 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3606 get_binop_right(node), new_rd_ia32_##op); \
3610 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3611 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3612 return gen_shift_binop(node, get_irn_n(node, 0), \
3613 get_irn_n(node, 1), new_rd_ia32_##op); \
3616 GEN_LOWERED_x87_OP(vfprem)
3617 GEN_LOWERED_x87_OP(vfmul)
3618 GEN_LOWERED_x87_OP(vfsub)
3619 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3620 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3621 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3622 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3624 static ir_node *gen_ia32_l_Add(ir_node *node) {
3625 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3626 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3627 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3629 if(is_Proj(lowered)) {
3630 lowered = get_Proj_pred(lowered);
3632 assert(is_ia32_Add(lowered));
3633 set_irn_mode(lowered, mode_T);
3639 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3640 ir_node *src_block = get_nodes_block(node);
3641 ir_node *block = be_transform_node(src_block);
3642 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3643 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3644 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3645 ir_node *new_flags = be_transform_node(flags);
3646 ir_graph *irg = current_ir_graph;
3647 dbg_info *dbgi = get_irn_dbg_info(node);
3649 ia32_address_mode_t am;
3650 ia32_address_t *addr = &am.addr;
3652 match_arguments(&am, src_block, op1, op2, 1, 0, 1, 0);
3654 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index, am.new_op1,
3655 am.new_op2, addr->mem, new_flags);
3656 set_am_attributes(new_node, &am);
3657 /* we can't use source address mode anymore when using immediates */
3658 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3659 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3660 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3662 new_node = fix_mem_proj(new_node, &am);
3668 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3670 * @param node The node to transform
3671 * @return the created ia32 Neg node
3673 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3674 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3678 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3680 * @param node The node to transform
3681 * @return the created ia32 vfild node
3683 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3684 return gen_lowered_Load(node, new_rd_ia32_vfild);
3688 * Transforms an ia32_l_Load into a "real" ia32_Load node
3690 * @param node The node to transform
3691 * @return the created ia32 Load node
3693 static ir_node *gen_ia32_l_Load(ir_node *node) {
3694 return gen_lowered_Load(node, new_rd_ia32_Load);
3698 * Transforms an ia32_l_Store into a "real" ia32_Store node
3700 * @param node The node to transform
3701 * @return the created ia32 Store node
3703 static ir_node *gen_ia32_l_Store(ir_node *node) {
3704 return gen_lowered_Store(node, new_rd_ia32_Store);
3708 * Transforms a l_vfist into a "real" vfist node.
3710 * @param node The node to transform
3711 * @return the created ia32 vfist node
3713 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3714 ir_node *block = be_transform_node(get_nodes_block(node));
3715 ir_node *ptr = get_irn_n(node, 0);
3716 ir_node *new_ptr = be_transform_node(ptr);
3717 ir_node *val = get_irn_n(node, 1);
3718 ir_node *new_val = be_transform_node(val);
3719 ir_node *mem = get_irn_n(node, 2);
3720 ir_node *new_mem = be_transform_node(mem);
3721 ir_graph *irg = current_ir_graph;
3722 dbg_info *dbgi = get_irn_dbg_info(node);
3723 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3724 ir_mode *mode = get_ia32_ls_mode(node);
3725 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3729 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3730 new_val, trunc_mode);
3732 am_offs = get_ia32_am_offs_int(node);
3733 add_ia32_am_offs_int(new_op, am_offs);
3735 set_ia32_op_type(new_op, ia32_AddrModeD);
3736 set_ia32_ls_mode(new_op, mode);
3737 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3738 set_ia32_use_frame(new_op);
3740 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3746 * Transforms a l_vfdiv into a "real" vfdiv node.
3748 * @param env The transformation environment
3749 * @return the created ia32 vfdiv node
3751 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3752 ir_node *block = be_transform_node(get_nodes_block(node));
3753 ir_node *left = get_binop_left(node);
3754 ir_node *new_left = be_transform_node(left);
3755 ir_node *right = get_binop_right(node);
3756 ir_node *new_right = be_transform_node(right);
3757 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3758 ir_graph *irg = current_ir_graph;
3759 dbg_info *dbgi = get_irn_dbg_info(node);
3760 ir_node *fpcw = get_fpcw();
3763 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3764 new_left, new_right, fpcw);
3765 clear_ia32_commutative(vfdiv);
3767 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3773 * Transforms a l_MulS into a "real" MulS node.
3775 * @param env The transformation environment
3776 * @return the created ia32 Mul node
3778 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3779 ir_node *block = be_transform_node(get_nodes_block(node));
3780 ir_node *left = get_binop_left(node);
3781 ir_node *new_left = be_transform_node(left);
3782 ir_node *right = get_binop_right(node);
3783 ir_node *new_right = be_transform_node(right);
3784 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3785 ir_graph *irg = current_ir_graph;
3786 dbg_info *dbgi = get_irn_dbg_info(node);
3788 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3789 /* and then skip the result Proj, because all needed Projs are already there. */
3790 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3791 new_left, new_right);
3792 clear_ia32_commutative(muls);
3794 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3800 * Transforms a l_IMulS into a "real" IMul1OPS node.
3802 * @param env The transformation environment
3803 * @return the created ia32 IMul1OP node
3805 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3806 ir_node *block = be_transform_node(get_nodes_block(node));
3807 ir_node *left = get_binop_left(node);
3808 ir_node *new_left = be_transform_node(left);
3809 ir_node *right = get_binop_right(node);
3810 ir_node *new_right = be_transform_node(right);
3811 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3812 ir_graph *irg = current_ir_graph;
3813 dbg_info *dbgi = get_irn_dbg_info(node);
3815 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3816 /* and then skip the result Proj, because all needed Projs are already there. */
3817 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3818 new_NoMem(), new_left, new_right);
3819 clear_ia32_commutative(muls);
3821 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3826 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3828 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3829 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3830 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3831 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3832 ir_node *block = be_transform_node(get_nodes_block(node));
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_graph *irg = current_ir_graph;
3835 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3836 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3840 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3842 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3843 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3844 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3845 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3846 ir_node *block = be_transform_node(get_nodes_block(node));
3847 dbg_info *dbgi = get_irn_dbg_info(node);
3848 ir_graph *irg = current_ir_graph;
3849 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3850 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3855 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3856 * op1 - target to be shifted
3857 * op2 - contains bits to be shifted into target
3859 * Only op3 can be an immediate.
3861 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3862 ir_node *op2, ir_node *count)
3864 ir_node *block = be_transform_node(get_nodes_block(node));
3865 ir_node *new_op = NULL;
3866 ir_graph *irg = current_ir_graph;
3867 dbg_info *dbgi = get_irn_dbg_info(node);
3868 ir_node *new_op1 = be_transform_node(op1);
3869 ir_node *new_op2 = be_transform_node(op2);
3870 ir_node *new_count = create_immediate_or_transform(count, 'I');
3872 /* TODO proper AM support */
3874 if (is_ia32_l_ShlD(node))
3875 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3877 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3879 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3884 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3885 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3886 get_irn_n(node, 1), get_irn_n(node, 2));
3889 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3890 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3891 get_irn_n(node, 1), get_irn_n(node, 2));
3895 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3897 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3898 ir_node *block = be_transform_node(get_nodes_block(node));
3899 ir_node *val = get_irn_n(node, 1);
3900 ir_node *new_val = be_transform_node(val);
3901 ia32_code_gen_t *cg = env_cg;
3902 ir_node *res = NULL;
3903 ir_graph *irg = current_ir_graph;
3905 ir_node *noreg, *new_ptr, *new_mem;
3912 mem = get_irn_n(node, 2);
3913 new_mem = be_transform_node(mem);
3914 ptr = get_irn_n(node, 0);
3915 new_ptr = be_transform_node(ptr);
3916 noreg = ia32_new_NoReg_gp(cg);
3917 dbgi = get_irn_dbg_info(node);
3919 /* Store x87 -> MEM */
3920 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3921 get_ia32_ls_mode(node));
3922 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3923 set_ia32_use_frame(res);
3924 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3925 set_ia32_op_type(res, ia32_AddrModeD);
3927 /* Load MEM -> SSE */
3928 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3929 get_ia32_ls_mode(node));
3930 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3931 set_ia32_use_frame(res);
3932 set_ia32_op_type(res, ia32_AddrModeS);
3933 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3939 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3941 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3942 ir_node *block = be_transform_node(get_nodes_block(node));
3943 ir_node *val = get_irn_n(node, 1);
3944 ir_node *new_val = be_transform_node(val);
3945 ia32_code_gen_t *cg = env_cg;
3946 ir_graph *irg = current_ir_graph;
3947 ir_node *res = NULL;
3948 ir_entity *fent = get_ia32_frame_ent(node);
3949 ir_mode *lsmode = get_ia32_ls_mode(node);
3951 ir_node *noreg, *new_ptr, *new_mem;
3955 if (! USE_SSE2(cg)) {
3956 /* SSE unit is not used -> skip this node. */
3960 ptr = get_irn_n(node, 0);
3961 new_ptr = be_transform_node(ptr);
3962 mem = get_irn_n(node, 2);
3963 new_mem = be_transform_node(mem);
3964 noreg = ia32_new_NoReg_gp(cg);
3965 dbgi = get_irn_dbg_info(node);
3967 /* Store SSE -> MEM */
3968 if (is_ia32_xLoad(skip_Proj(new_val))) {
3969 ir_node *ld = skip_Proj(new_val);
3971 /* we can vfld the value directly into the fpu */
3972 fent = get_ia32_frame_ent(ld);
3973 ptr = get_irn_n(ld, 0);
3974 offs = get_ia32_am_offs_int(ld);
3976 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3978 set_ia32_frame_ent(res, fent);
3979 set_ia32_use_frame(res);
3980 set_ia32_ls_mode(res, lsmode);
3981 set_ia32_op_type(res, ia32_AddrModeD);
3985 /* Load MEM -> x87 */
3986 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3987 set_ia32_frame_ent(res, fent);
3988 set_ia32_use_frame(res);
3989 add_ia32_am_offs_int(res, offs);
3990 set_ia32_op_type(res, ia32_AddrModeS);
3991 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3996 /*********************************************************
3999 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4000 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4001 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4002 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4004 *********************************************************/
4007 * the BAD transformer.
4009 static ir_node *bad_transform(ir_node *node) {
4010 panic("No transform function for %+F available.\n", node);
4015 * Transform the Projs of an AddSP.
4017 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4018 ir_node *block = be_transform_node(get_nodes_block(node));
4019 ir_node *pred = get_Proj_pred(node);
4020 ir_node *new_pred = be_transform_node(pred);
4021 ir_graph *irg = current_ir_graph;
4022 dbg_info *dbgi = get_irn_dbg_info(node);
4023 long proj = get_Proj_proj(node);
4025 if (proj == pn_be_AddSP_sp) {
4026 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4027 pn_ia32_SubSP_stack);
4028 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4030 } else if(proj == pn_be_AddSP_res) {
4031 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4032 pn_ia32_SubSP_addr);
4033 } else if (proj == pn_be_AddSP_M) {
4034 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4038 return new_rd_Unknown(irg, get_irn_mode(node));
4042 * Transform the Projs of a SubSP.
4044 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4045 ir_node *block = be_transform_node(get_nodes_block(node));
4046 ir_node *pred = get_Proj_pred(node);
4047 ir_node *new_pred = be_transform_node(pred);
4048 ir_graph *irg = current_ir_graph;
4049 dbg_info *dbgi = get_irn_dbg_info(node);
4050 long proj = get_Proj_proj(node);
4052 if (proj == pn_be_SubSP_sp) {
4053 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4054 pn_ia32_AddSP_stack);
4055 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4057 } else if (proj == pn_be_SubSP_M) {
4058 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4062 return new_rd_Unknown(irg, get_irn_mode(node));
4066 * Transform and renumber the Projs from a Load.
4068 static ir_node *gen_Proj_Load(ir_node *node) {
4070 ir_node *block = be_transform_node(get_nodes_block(node));
4071 ir_node *pred = get_Proj_pred(node);
4072 ir_graph *irg = current_ir_graph;
4073 dbg_info *dbgi = get_irn_dbg_info(node);
4074 long proj = get_Proj_proj(node);
4077 /* loads might be part of source address mode matches, so we don't
4078 transform the ProjMs yet (with the exception of loads whose result is
4081 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4084 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4086 /* this is needed, because sometimes we have loops that are only
4087 reachable through the ProjM */
4088 be_enqueue_preds(node);
4089 /* do it in 2 steps, to silence firm verifier */
4090 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4091 set_Proj_proj(res, pn_ia32_Load_M);
4095 /* renumber the proj */
4096 new_pred = be_transform_node(pred);
4097 if (is_ia32_Load(new_pred)) {
4098 if (proj == pn_Load_res) {
4099 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4101 } else if (proj == pn_Load_M) {
4102 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4105 } else if(is_ia32_Conv_I2I(new_pred)) {
4106 set_irn_mode(new_pred, mode_T);
4107 if (proj == pn_Load_res) {
4108 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4109 } else if (proj == pn_Load_M) {
4110 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4112 } else if (is_ia32_xLoad(new_pred)) {
4113 if (proj == pn_Load_res) {
4114 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4116 } else if (proj == pn_Load_M) {
4117 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4120 } else if (is_ia32_vfld(new_pred)) {
4121 if (proj == pn_Load_res) {
4122 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4124 } else if (proj == pn_Load_M) {
4125 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4129 /* can happen for ProJMs when source address mode happened for the
4132 /* however it should not be the result proj, as that would mean the
4133 load had multiple users and should not have been used for
4135 if(proj != pn_Load_M) {
4136 panic("internal error: transformed node not a Load");
4138 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4142 return new_rd_Unknown(irg, get_irn_mode(node));
4146 * Transform and renumber the Projs from a DivMod like instruction.
4148 static ir_node *gen_Proj_DivMod(ir_node *node) {
4149 ir_node *block = be_transform_node(get_nodes_block(node));
4150 ir_node *pred = get_Proj_pred(node);
4151 ir_node *new_pred = be_transform_node(pred);
4152 ir_graph *irg = current_ir_graph;
4153 dbg_info *dbgi = get_irn_dbg_info(node);
4154 ir_mode *mode = get_irn_mode(node);
4155 long proj = get_Proj_proj(node);
4157 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4159 switch (get_irn_opcode(pred)) {
4163 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4165 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4173 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4175 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4183 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4184 case pn_DivMod_res_div:
4185 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4186 case pn_DivMod_res_mod:
4187 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4197 return new_rd_Unknown(irg, mode);
4201 * Transform and renumber the Projs from a CopyB.
4203 static ir_node *gen_Proj_CopyB(ir_node *node) {
4204 ir_node *block = be_transform_node(get_nodes_block(node));
4205 ir_node *pred = get_Proj_pred(node);
4206 ir_node *new_pred = be_transform_node(pred);
4207 ir_graph *irg = current_ir_graph;
4208 dbg_info *dbgi = get_irn_dbg_info(node);
4209 ir_mode *mode = get_irn_mode(node);
4210 long proj = get_Proj_proj(node);
4213 case pn_CopyB_M_regular:
4214 if (is_ia32_CopyB_i(new_pred)) {
4215 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4216 } else if (is_ia32_CopyB(new_pred)) {
4217 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4225 return new_rd_Unknown(irg, mode);
4229 * Transform and renumber the Projs from a vfdiv.
4231 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4232 ir_node *block = be_transform_node(get_nodes_block(node));
4233 ir_node *pred = get_Proj_pred(node);
4234 ir_node *new_pred = be_transform_node(pred);
4235 ir_graph *irg = current_ir_graph;
4236 dbg_info *dbgi = get_irn_dbg_info(node);
4237 ir_mode *mode = get_irn_mode(node);
4238 long proj = get_Proj_proj(node);
4241 case pn_ia32_l_vfdiv_M:
4242 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4243 case pn_ia32_l_vfdiv_res:
4244 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4249 return new_rd_Unknown(irg, mode);
4253 * Transform and renumber the Projs from a Quot.
4255 static ir_node *gen_Proj_Quot(ir_node *node) {
4256 ir_node *block = be_transform_node(get_nodes_block(node));
4257 ir_node *pred = get_Proj_pred(node);
4258 ir_node *new_pred = be_transform_node(pred);
4259 ir_graph *irg = current_ir_graph;
4260 dbg_info *dbgi = get_irn_dbg_info(node);
4261 ir_mode *mode = get_irn_mode(node);
4262 long proj = get_Proj_proj(node);
4266 if (is_ia32_xDiv(new_pred)) {
4267 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4268 } else if (is_ia32_vfdiv(new_pred)) {
4269 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4273 if (is_ia32_xDiv(new_pred)) {
4274 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4275 } else if (is_ia32_vfdiv(new_pred)) {
4276 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4284 return new_rd_Unknown(irg, mode);
4288 * Transform the Thread Local Storage Proj.
4290 static ir_node *gen_Proj_tls(ir_node *node) {
4291 ir_node *block = be_transform_node(get_nodes_block(node));
4292 ir_graph *irg = current_ir_graph;
4293 dbg_info *dbgi = NULL;
4294 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4300 * Transform the Projs from a be_Call.
4302 static ir_node *gen_Proj_be_Call(ir_node *node) {
4303 ir_node *block = be_transform_node(get_nodes_block(node));
4304 ir_node *call = get_Proj_pred(node);
4305 ir_node *new_call = be_transform_node(call);
4306 ir_graph *irg = current_ir_graph;
4307 dbg_info *dbgi = get_irn_dbg_info(node);
4308 ir_type *method_type = be_Call_get_type(call);
4309 int n_res = get_method_n_ress(method_type);
4310 long proj = get_Proj_proj(node);
4311 ir_mode *mode = get_irn_mode(node);
4313 const arch_register_class_t *cls;
4315 /* The following is kinda tricky: If we're using SSE, then we have to
4316 * move the result value of the call in floating point registers to an
4317 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4318 * after the call, we have to make sure to correctly make the
4319 * MemProj and the result Proj use these 2 nodes
4321 if (proj == pn_be_Call_M_regular) {
4322 // get new node for result, are we doing the sse load/store hack?
4323 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4324 ir_node *call_res_new;
4325 ir_node *call_res_pred = NULL;
4327 if (call_res != NULL) {
4328 call_res_new = be_transform_node(call_res);
4329 call_res_pred = get_Proj_pred(call_res_new);
4332 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4333 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4334 pn_be_Call_M_regular);
4336 assert(is_ia32_xLoad(call_res_pred));
4337 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4341 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4342 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4343 && USE_SSE2(env_cg)) {
4345 ir_node *frame = get_irg_frame(irg);
4346 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4348 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4351 /* in case there is no memory output: create one to serialize the copy
4353 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4354 pn_be_Call_M_regular);
4355 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4356 pn_be_Call_first_res);
4358 /* store st(0) onto stack */
4359 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4361 set_ia32_op_type(fstp, ia32_AddrModeD);
4362 set_ia32_use_frame(fstp);
4364 /* load into SSE register */
4365 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4367 set_ia32_op_type(sse_load, ia32_AddrModeS);
4368 set_ia32_use_frame(sse_load);
4370 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4376 /* transform call modes */
4377 if (mode_is_data(mode)) {
4378 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4382 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4386 * Transform the Projs from a Cmp.
4388 static ir_node *gen_Proj_Cmp(ir_node *node)
4390 /* normally Cmps are processed when looking at Cond nodes, but this case
4391 * can happen in complicated Psi conditions */
4393 ir_node *cmp = get_Proj_pred(node);
4394 long pnc = get_Proj_proj(node);
4395 ir_node *cmp_left = get_Cmp_left(cmp);
4396 ir_node *cmp_right = get_Cmp_right(cmp);
4397 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4398 dbg_info *dbgi = get_irn_dbg_info(cmp);
4399 ir_node *block = get_nodes_block(node);
4403 assert(!mode_is_float(cmp_mode));
4405 if(!mode_is_signed(cmp_mode)) {
4406 pnc |= ia32_pn_Cmp_Unsigned;
4410 * address mode makes only sense when we'll be the only node using the cmp
4412 use_am = get_irn_n_edges(cmp) <= 1;
4414 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4415 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4421 * Transform and potentially renumber Proj nodes.
4423 static ir_node *gen_Proj(ir_node *node) {
4424 ir_graph *irg = current_ir_graph;
4425 dbg_info *dbgi = get_irn_dbg_info(node);
4426 ir_node *pred = get_Proj_pred(node);
4427 long proj = get_Proj_proj(node);
4429 if (is_Store(pred)) {
4430 if (proj == pn_Store_M) {
4431 return be_transform_node(pred);
4434 return new_r_Bad(irg);
4436 } else if (is_Load(pred)) {
4437 return gen_Proj_Load(node);
4438 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4439 return gen_Proj_DivMod(node);
4440 } else if (is_CopyB(pred)) {
4441 return gen_Proj_CopyB(node);
4442 } else if (is_Quot(pred)) {
4443 return gen_Proj_Quot(node);
4444 } else if (is_ia32_l_vfdiv(pred)) {
4445 return gen_Proj_l_vfdiv(node);
4446 } else if (be_is_SubSP(pred)) {
4447 return gen_Proj_be_SubSP(node);
4448 } else if (be_is_AddSP(pred)) {
4449 return gen_Proj_be_AddSP(node);
4450 } else if (be_is_Call(pred)) {
4451 return gen_Proj_be_Call(node);
4452 } else if (is_Cmp(pred)) {
4453 return gen_Proj_Cmp(node);
4454 } else if (get_irn_op(pred) == op_Start) {
4455 if (proj == pn_Start_X_initial_exec) {
4456 ir_node *block = get_nodes_block(pred);
4459 /* we exchange the ProjX with a jump */
4460 block = be_transform_node(block);
4461 jump = new_rd_Jmp(dbgi, irg, block);
4464 if (node == be_get_old_anchor(anchor_tls)) {
4465 return gen_Proj_tls(node);
4468 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4472 ir_node *new_pred = be_transform_node(pred);
4473 ir_node *block = be_transform_node(get_nodes_block(node));
4474 ir_mode *mode = get_irn_mode(node);
4475 if (mode_needs_gp_reg(mode)) {
4476 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4477 get_Proj_proj(node));
4478 #ifdef DEBUG_libfirm
4479 new_proj->node_nr = node->node_nr;
4485 return be_duplicate_node(node);
4489 * Enters all transform functions into the generic pointer
4491 static void register_transformers(void)
4495 /* first clear the generic function pointer for all ops */
4496 clear_irp_opcodes_generic_func();
4498 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4499 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4536 /* transform ops from intrinsic lowering */
4558 GEN(ia32_l_X87toSSE);
4559 GEN(ia32_l_SSEtoX87);
4565 /* we should never see these nodes */
4580 /* handle generic backend nodes */
4588 op_Mulh = get_op_Mulh();
4597 * Pre-transform all unknown and noreg nodes.
4599 static void ia32_pretransform_node(void *arch_cg) {
4600 ia32_code_gen_t *cg = arch_cg;
4602 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4603 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4604 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4605 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4606 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4607 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4612 * Walker, checks if all ia32 nodes producing more than one result have
4613 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4616 void add_missing_keep_walker(ir_node *node, void *data)
4619 unsigned found_projs = 0;
4620 const ir_edge_t *edge;
4621 ir_mode *mode = get_irn_mode(node);
4626 if(!is_ia32_irn(node))
4629 n_outs = get_ia32_n_res(node);
4632 if(is_ia32_SwitchJmp(node))
4635 assert(n_outs < (int) sizeof(unsigned) * 8);
4636 foreach_out_edge(node, edge) {
4637 ir_node *proj = get_edge_src_irn(edge);
4638 int pn = get_Proj_proj(proj);
4640 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4641 found_projs |= 1 << pn;
4645 /* are keeps missing? */
4647 for(i = 0; i < n_outs; ++i) {
4650 const arch_register_req_t *req;
4651 const arch_register_class_t *class;
4653 if(found_projs & (1 << i)) {
4657 req = get_ia32_out_req(node, i);
4662 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4666 block = get_nodes_block(node);
4667 in[0] = new_r_Proj(current_ir_graph, block, node,
4668 arch_register_class_mode(class), i);
4669 if(last_keep != NULL) {
4670 be_Keep_add_node(last_keep, class, in[0]);
4672 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4673 if(sched_is_scheduled(node)) {
4674 sched_add_after(node, last_keep);
4681 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4684 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4686 ir_graph *irg = be_get_birg_irg(cg->birg);
4687 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4690 /* do the transformation */
4691 void ia32_transform_graph(ia32_code_gen_t *cg) {
4692 register_transformers();
4694 initial_fpcw = NULL;
4696 heights = heights_new(cg->irg);
4698 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4700 heights_free(heights);
4704 void ia32_init_transform(void)
4706 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");