2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
563 * Construct a standard binary operation, set AM and immediate if required.
565 * @param op1 The first operand
566 * @param op2 The second operand
567 * @param func The node constructor function
568 * @return The constructed ia32 node.
570 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
571 construct_binop_float_func *func)
573 ir_node *block = be_transform_node(get_nodes_block(node));
574 ir_node *new_op1 = be_transform_node(op1);
575 ir_node *new_op2 = be_transform_node(op2);
576 ir_node *new_node = NULL;
577 dbg_info *dbgi = get_irn_dbg_info(node);
578 ir_graph *irg = current_ir_graph;
579 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
580 ir_node *nomem = new_NoMem();
581 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
582 &ia32_fp_cw_regs[REG_FPCW]);
584 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
586 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
587 if (is_op_commutative(get_irn_op(node))) {
588 set_ia32_commutative(new_node);
591 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
597 * Construct a shift/rotate binary operation, sets AM and immediate if required.
599 * @param op1 The first operand
600 * @param op2 The second operand
601 * @param func The node constructor function
602 * @return The constructed ia32 node.
604 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
605 construct_binop_func *func)
607 ir_node *block = be_transform_node(get_nodes_block(node));
608 ir_node *new_op1 = be_transform_node(op1);
610 ir_node *new_op = NULL;
611 dbg_info *dbgi = get_irn_dbg_info(node);
612 ir_graph *irg = current_ir_graph;
613 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
614 ir_node *nomem = new_NoMem();
616 assert(! mode_is_float(get_irn_mode(node))
617 && "Shift/Rotate with float not supported");
619 new_op2 = create_immediate_or_transform(op2, 'N');
621 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
624 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
626 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
628 set_ia32_emit_cl(new_op);
635 * Construct a standard unary operation, set AM and immediate if required.
637 * @param op The operand
638 * @param func The node constructor function
639 * @return The constructed ia32 node.
641 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
643 ir_node *block = be_transform_node(get_nodes_block(node));
644 ir_node *new_op = be_transform_node(op);
645 ir_node *new_node = NULL;
646 ir_graph *irg = current_ir_graph;
647 dbg_info *dbgi = get_irn_dbg_info(node);
648 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
649 ir_node *nomem = new_NoMem();
651 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
652 DB((dbg, LEVEL_1, "INT unop ..."));
653 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
661 * Creates an ia32 Add.
663 * @return the created ia32 Add node
665 static ir_node *gen_Add(ir_node *node) {
666 ir_node *block = be_transform_node(get_nodes_block(node));
667 ir_node *op1 = get_Add_left(node);
668 ir_node *new_op1 = be_transform_node(op1);
669 ir_node *op2 = get_Add_right(node);
670 ir_node *new_op2 = be_transform_node(op2);
671 ir_node *new_op = NULL;
672 ir_graph *irg = current_ir_graph;
673 dbg_info *dbgi = get_irn_dbg_info(node);
674 ir_mode *mode = get_irn_mode(node);
675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
676 ir_node *nomem = new_NoMem();
677 ir_node *expr_op, *imm_op;
679 /* Check if immediate optimization is on and */
680 /* if it's an operation with immediate. */
681 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
682 expr_op = get_expr_op(new_op1, new_op2);
684 assert((expr_op || imm_op) && "invalid operands");
686 if (mode_is_float(mode)) {
688 if (USE_SSE2(env_cg))
689 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
691 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
696 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
697 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
699 /* No expr_op means, that we have two const - one symconst and */
700 /* one tarval or another symconst - because this case is not */
701 /* covered by constant folding */
702 /* We need to check for: */
703 /* 1) symconst + const -> becomes a LEA */
704 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
705 /* linker doesn't support two symconsts */
707 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
708 /* this is the 2nd case */
709 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
710 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
711 set_ia32_am_flavour(new_op, ia32_am_B);
712 set_ia32_op_type(new_op, ia32_AddrModeS);
714 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
715 } else if (tp1 == ia32_ImmSymConst) {
716 tarval *tv = get_ia32_Immop_tarval(new_op2);
717 long offs = get_tarval_long(tv);
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
720 add_irn_dep(new_op, get_irg_frame(irg));
721 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
723 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
724 add_ia32_am_offs_int(new_op, offs);
725 set_ia32_am_flavour(new_op, ia32_am_OB);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
727 } else if (tp2 == ia32_ImmSymConst) {
728 tarval *tv = get_ia32_Immop_tarval(new_op1);
729 long offs = get_tarval_long(tv);
731 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
732 add_irn_dep(new_op, get_irg_frame(irg));
733 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
735 add_ia32_am_offs_int(new_op, offs);
736 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
737 set_ia32_am_flavour(new_op, ia32_am_OB);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
741 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
742 tarval *restv = tarval_add(tv1, tv2);
744 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
746 new_op = new_rd_ia32_Const(dbgi, irg, block);
747 set_ia32_Const_tarval(new_op, restv);
748 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
751 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
754 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
755 tarval_classification_t class_tv, class_negtv;
756 tarval *tv = get_ia32_Immop_tarval(imm_op);
758 /* optimize tarvals */
759 class_tv = classify_tarval(tv);
760 class_negtv = classify_tarval(tarval_neg(tv));
762 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
763 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
764 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
767 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
768 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
769 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
776 /* This is a normal add */
777 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
780 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
781 set_ia32_commutative(new_op);
783 fold_immediate(new_op, 2, 3);
785 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
791 * Creates an ia32 Mul.
793 * @return the created ia32 Mul node
795 static ir_node *gen_Mul(ir_node *node) {
796 ir_node *op1 = get_Mul_left(node);
797 ir_node *op2 = get_Mul_right(node);
798 ir_mode *mode = get_irn_mode(node);
800 if (mode_is_float(mode)) {
802 if (USE_SSE2(env_cg))
803 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
805 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
809 for the lower 32bit of the result it doesn't matter whether we use
810 signed or unsigned multiplication so we use IMul as it has fewer
813 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
817 * Creates an ia32 Mulh.
818 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
819 * this result while Mul returns the lower 32 bit.
821 * @return the created ia32 Mulh node
823 static ir_node *gen_Mulh(ir_node *node) {
824 ir_node *block = be_transform_node(get_nodes_block(node));
825 ir_node *op1 = get_irn_n(node, 0);
826 ir_node *new_op1 = be_transform_node(op1);
827 ir_node *op2 = get_irn_n(node, 1);
828 ir_node *new_op2 = be_transform_node(op2);
829 ir_graph *irg = current_ir_graph;
830 dbg_info *dbgi = get_irn_dbg_info(node);
831 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
832 ir_mode *mode = get_irn_mode(node);
833 ir_node *proj_EAX, *proj_EDX, *res;
836 assert(!mode_is_float(mode) && "Mulh with float not supported");
837 if (mode_is_signed(mode)) {
838 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
840 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
843 set_ia32_commutative(res);
844 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
846 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
847 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
851 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
859 * Creates an ia32 And.
861 * @return The created ia32 And node
863 static ir_node *gen_And(ir_node *node) {
864 ir_node *op1 = get_And_left(node);
865 ir_node *op2 = get_And_right(node);
867 assert (! mode_is_float(get_irn_mode(node)));
868 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
874 * Creates an ia32 Or.
876 * @return The created ia32 Or node
878 static ir_node *gen_Or(ir_node *node) {
879 ir_node *op1 = get_Or_left(node);
880 ir_node *op2 = get_Or_right(node);
882 assert (! mode_is_float(get_irn_mode(node)));
883 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
889 * Creates an ia32 Eor.
891 * @return The created ia32 Eor node
893 static ir_node *gen_Eor(ir_node *node) {
894 ir_node *op1 = get_Eor_left(node);
895 ir_node *op2 = get_Eor_right(node);
897 assert(! mode_is_float(get_irn_mode(node)));
898 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
904 * Creates an ia32 Max.
906 * @return the created ia32 Max node
908 static ir_node *gen_Max(ir_node *node) {
909 ir_node *block = be_transform_node(get_nodes_block(node));
910 ir_node *op1 = get_irn_n(node, 0);
911 ir_node *new_op1 = be_transform_node(op1);
912 ir_node *op2 = get_irn_n(node, 1);
913 ir_node *new_op2 = be_transform_node(op2);
914 ir_graph *irg = current_ir_graph;
915 ir_mode *mode = get_irn_mode(node);
916 dbg_info *dbgi = get_irn_dbg_info(node);
917 ir_mode *op_mode = get_irn_mode(op1);
920 assert(get_mode_size_bits(mode) == 32);
922 if (mode_is_float(mode)) {
924 if (USE_SSE2(env_cg)) {
925 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
927 panic("Can't create Max node");
930 long pnc = pn_Cmp_Gt;
931 if (! mode_is_signed(op_mode)) {
932 pnc |= ia32_pn_Cmp_Unsigned;
934 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
935 new_op1, new_op2, pnc);
937 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
943 * Creates an ia32 Min.
945 * @return the created ia32 Min node
947 static ir_node *gen_Min(ir_node *node) {
948 ir_node *block = be_transform_node(get_nodes_block(node));
949 ir_node *op1 = get_irn_n(node, 0);
950 ir_node *new_op1 = be_transform_node(op1);
951 ir_node *op2 = get_irn_n(node, 1);
952 ir_node *new_op2 = be_transform_node(op2);
953 ir_graph *irg = current_ir_graph;
954 ir_mode *mode = get_irn_mode(node);
955 dbg_info *dbgi = get_irn_dbg_info(node);
956 ir_mode *op_mode = get_irn_mode(op1);
959 assert(get_mode_size_bits(mode) == 32);
961 if (mode_is_float(mode)) {
963 if (USE_SSE2(env_cg)) {
964 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
966 panic("can't create Min node");
969 long pnc = pn_Cmp_Lt;
970 if (! mode_is_signed(op_mode)) {
971 pnc |= ia32_pn_Cmp_Unsigned;
973 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
974 new_op1, new_op2, pnc);
976 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
983 * Creates an ia32 Sub.
985 * @return The created ia32 Sub node
987 static ir_node *gen_Sub(ir_node *node) {
988 ir_node *block = be_transform_node(get_nodes_block(node));
989 ir_node *op1 = get_Sub_left(node);
990 ir_node *new_op1 = be_transform_node(op1);
991 ir_node *op2 = get_Sub_right(node);
992 ir_node *new_op2 = be_transform_node(op2);
993 ir_node *new_op = NULL;
994 ir_graph *irg = current_ir_graph;
995 dbg_info *dbgi = get_irn_dbg_info(node);
996 ir_mode *mode = get_irn_mode(node);
997 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
998 ir_node *nomem = new_NoMem();
999 ir_node *expr_op, *imm_op;
1001 /* Check if immediate optimization is on and */
1002 /* if it's an operation with immediate. */
1003 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1004 expr_op = get_expr_op(new_op1, new_op2);
1006 assert((expr_op || imm_op) && "invalid operands");
1008 if (mode_is_float(mode)) {
1010 if (USE_SSE2(env_cg))
1011 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1013 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1018 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1019 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1021 /* No expr_op means, that we have two const - one symconst and */
1022 /* one tarval or another symconst - because this case is not */
1023 /* covered by constant folding */
1024 /* We need to check for: */
1025 /* 1) symconst - const -> becomes a LEA */
1026 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1027 /* linker doesn't support two symconsts */
1028 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1029 /* this is the 2nd case */
1030 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1031 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1032 set_ia32_am_sc_sign(new_op);
1033 set_ia32_am_flavour(new_op, ia32_am_B);
1035 DBG_OPT_LEA3(op1, op2, node, new_op);
1036 } else if (tp1 == ia32_ImmSymConst) {
1037 tarval *tv = get_ia32_Immop_tarval(new_op2);
1038 long offs = get_tarval_long(tv);
1040 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1041 add_irn_dep(new_op, get_irg_frame(irg));
1042 DBG_OPT_LEA3(op1, op2, node, new_op);
1044 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1045 add_ia32_am_offs_int(new_op, -offs);
1046 set_ia32_am_flavour(new_op, ia32_am_OB);
1047 set_ia32_op_type(new_op, ia32_AddrModeS);
1048 } else if (tp2 == ia32_ImmSymConst) {
1049 tarval *tv = get_ia32_Immop_tarval(new_op1);
1050 long offs = get_tarval_long(tv);
1052 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1053 add_irn_dep(new_op, get_irg_frame(irg));
1054 DBG_OPT_LEA3(op1, op2, node, new_op);
1056 add_ia32_am_offs_int(new_op, offs);
1057 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1058 set_ia32_am_sc_sign(new_op);
1059 set_ia32_am_flavour(new_op, ia32_am_OB);
1060 set_ia32_op_type(new_op, ia32_AddrModeS);
1062 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1063 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1064 tarval *restv = tarval_sub(tv1, tv2);
1066 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1068 new_op = new_rd_ia32_Const(dbgi, irg, block);
1069 set_ia32_Const_tarval(new_op, restv);
1070 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1075 } else if (imm_op) {
1076 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1077 tarval_classification_t class_tv, class_negtv;
1078 tarval *tv = get_ia32_Immop_tarval(imm_op);
1080 /* optimize tarvals */
1081 class_tv = classify_tarval(tv);
1082 class_negtv = classify_tarval(tarval_neg(tv));
1084 if (class_tv == TV_CLASSIFY_ONE) {
1085 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1086 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1089 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1090 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1091 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1098 /* This is a normal sub */
1099 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1101 /* set AM support */
1102 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1104 fold_immediate(new_op, 2, 3);
1106 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1114 * Generates an ia32 DivMod with additional infrastructure for the
1115 * register allocator if needed.
1117 * @param dividend -no comment- :)
1118 * @param divisor -no comment- :)
1119 * @param dm_flav flavour_Div/Mod/DivMod
1120 * @return The created ia32 DivMod node
1122 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1123 ir_node *divisor, ia32_op_flavour_t dm_flav)
1125 ir_node *block = be_transform_node(get_nodes_block(node));
1126 ir_node *new_dividend = be_transform_node(dividend);
1127 ir_node *new_divisor = be_transform_node(divisor);
1128 ir_graph *irg = current_ir_graph;
1129 dbg_info *dbgi = get_irn_dbg_info(node);
1130 ir_mode *mode = get_irn_mode(node);
1131 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1132 ir_node *res, *proj_div, *proj_mod;
1133 ir_node *sign_extension;
1134 ir_node *in_keep[2];
1135 ir_node *mem, *new_mem;
1136 ir_node *projs[pn_DivMod_max];
1139 ia32_collect_Projs(node, projs, pn_DivMod_max);
1141 proj_div = proj_mod = NULL;
1145 mem = get_Div_mem(node);
1146 mode = get_Div_resmode(node);
1147 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1148 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1151 mem = get_Mod_mem(node);
1152 mode = get_Mod_resmode(node);
1153 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1154 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1156 case flavour_DivMod:
1157 mem = get_DivMod_mem(node);
1158 mode = get_DivMod_resmode(node);
1159 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1160 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1161 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1164 panic("invalid divmod flavour!");
1166 new_mem = be_transform_node(mem);
1168 if (mode_is_signed(mode)) {
1169 /* in signed mode, we need to sign extend the dividend */
1170 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1172 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1173 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1175 add_irn_dep(sign_extension, get_irg_frame(irg));
1178 if (mode_is_signed(mode)) {
1179 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1180 sign_extension, new_divisor, new_mem, dm_flav);
1182 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1183 sign_extension, new_divisor, new_mem, dm_flav);
1186 set_ia32_exc_label(res, has_exc);
1187 set_irn_pinned(res, get_irn_pinned(node));
1189 /* Matze: code can't handle this at the moment... */
1191 /* set AM support */
1192 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1195 /* check, which Proj-Keep, we need to add */
1197 if (proj_div == NULL) {
1198 /* We have only mod result: add div res Proj-Keep */
1199 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1202 if (proj_mod == NULL) {
1203 /* We have only div result: add mod res Proj-Keep */
1204 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1208 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1210 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1217 * Wrapper for generate_DivMod. Sets flavour_Mod.
1220 static ir_node *gen_Mod(ir_node *node) {
1221 return generate_DivMod(node, get_Mod_left(node),
1222 get_Mod_right(node), flavour_Mod);
1226 * Wrapper for generate_DivMod. Sets flavour_Div.
1229 static ir_node *gen_Div(ir_node *node) {
1230 return generate_DivMod(node, get_Div_left(node),
1231 get_Div_right(node), flavour_Div);
1235 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1237 static ir_node *gen_DivMod(ir_node *node) {
1238 return generate_DivMod(node, get_DivMod_left(node),
1239 get_DivMod_right(node), flavour_DivMod);
1245 * Creates an ia32 floating Div.
1247 * @return The created ia32 xDiv node
1249 static ir_node *gen_Quot(ir_node *node) {
1250 ir_node *block = be_transform_node(get_nodes_block(node));
1251 ir_node *op1 = get_Quot_left(node);
1252 ir_node *new_op1 = be_transform_node(op1);
1253 ir_node *op2 = get_Quot_right(node);
1254 ir_node *new_op2 = be_transform_node(op2);
1255 ir_graph *irg = current_ir_graph;
1256 dbg_info *dbgi = get_irn_dbg_info(node);
1257 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1258 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1262 if (USE_SSE2(env_cg)) {
1263 ir_mode *mode = get_irn_mode(op1);
1264 if (is_ia32_xConst(new_op2)) {
1265 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1266 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1267 copy_ia32_Immop_attr(new_op, new_op2);
1269 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1270 // Matze: disabled for now, spillslot coalescer fails
1271 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1273 set_ia32_ls_mode(new_op, mode);
1275 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1276 &ia32_fp_cw_regs[REG_FPCW]);
1277 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1278 new_op2, nomem, fpcw);
1279 // Matze: disabled for now (spillslot coalescer fails)
1280 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1282 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1288 * Creates an ia32 Shl.
1290 * @return The created ia32 Shl node
1292 static ir_node *gen_Shl(ir_node *node) {
1293 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1300 * Creates an ia32 Shr.
1302 * @return The created ia32 Shr node
1304 static ir_node *gen_Shr(ir_node *node) {
1305 return gen_shift_binop(node, get_Shr_left(node),
1306 get_Shr_right(node), new_rd_ia32_Shr);
1312 * Creates an ia32 Sar.
1314 * @return The created ia32 Shrs node
1316 static ir_node *gen_Shrs(ir_node *node) {
1317 ir_node *left = get_Shrs_left(node);
1318 ir_node *right = get_Shrs_right(node);
1319 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1320 tarval *tv = get_Const_tarval(right);
1321 long val = get_tarval_long(tv);
1323 /* this is a sign extension */
1324 ir_graph *irg = current_ir_graph;
1325 dbg_info *dbgi = get_irn_dbg_info(node);
1326 ir_node *block = be_transform_node(get_nodes_block(node));
1328 ir_node *new_op = be_transform_node(op);
1330 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1334 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1340 * Creates an ia32 RotL.
1342 * @param op1 The first operator
1343 * @param op2 The second operator
1344 * @return The created ia32 RotL node
1346 static ir_node *gen_RotL(ir_node *node,
1347 ir_node *op1, ir_node *op2) {
1348 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1354 * Creates an ia32 RotR.
1355 * NOTE: There is no RotR with immediate because this would always be a RotL
1356 * "imm-mode_size_bits" which can be pre-calculated.
1358 * @param op1 The first operator
1359 * @param op2 The second operator
1360 * @return The created ia32 RotR node
1362 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1364 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1370 * Creates an ia32 RotR or RotL (depending on the found pattern).
1372 * @return The created ia32 RotL or RotR node
1374 static ir_node *gen_Rot(ir_node *node) {
1375 ir_node *rotate = NULL;
1376 ir_node *op1 = get_Rot_left(node);
1377 ir_node *op2 = get_Rot_right(node);
1379 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1380 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1381 that means we can create a RotR instead of an Add and a RotL */
1383 if (get_irn_op(op2) == op_Add) {
1385 ir_node *left = get_Add_left(add);
1386 ir_node *right = get_Add_right(add);
1387 if (is_Const(right)) {
1388 tarval *tv = get_Const_tarval(right);
1389 ir_mode *mode = get_irn_mode(node);
1390 long bits = get_mode_size_bits(mode);
1392 if (get_irn_op(left) == op_Minus &&
1393 tarval_is_long(tv) &&
1394 get_tarval_long(tv) == bits)
1396 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1397 rotate = gen_RotR(node, op1, get_Minus_op(left));
1402 if (rotate == NULL) {
1403 rotate = gen_RotL(node, op1, op2);
1412 * Transforms a Minus node.
1414 * @param op The Minus operand
1415 * @return The created ia32 Minus node
1417 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1418 ir_node *block = be_transform_node(get_nodes_block(node));
1419 ir_graph *irg = current_ir_graph;
1420 dbg_info *dbgi = get_irn_dbg_info(node);
1421 ir_mode *mode = get_irn_mode(node);
1426 if (mode_is_float(mode)) {
1427 ir_node *new_op = be_transform_node(op);
1429 if (USE_SSE2(env_cg)) {
1430 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1431 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1432 ir_node *nomem = new_rd_NoMem(irg);
1434 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1436 size = get_mode_size_bits(mode);
1437 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1439 set_ia32_am_sc(res, ent);
1440 set_ia32_op_type(res, ia32_AddrModeS);
1441 set_ia32_ls_mode(res, mode);
1443 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1446 res = gen_unop(node, op, new_rd_ia32_Neg);
1449 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1455 * Transforms a Minus node.
1457 * @return The created ia32 Minus node
1459 static ir_node *gen_Minus(ir_node *node) {
1460 return gen_Minus_ex(node, get_Minus_op(node));
1465 * Transforms a Not node.
1467 * @return The created ia32 Not node
1469 static ir_node *gen_Not(ir_node *node) {
1470 ir_node *op = get_Not_op(node);
1472 assert (! mode_is_float(get_irn_mode(node)));
1473 return gen_unop(node, op, new_rd_ia32_Not);
1479 * Transforms an Abs node.
1481 * @return The created ia32 Abs node
1483 static ir_node *gen_Abs(ir_node *node) {
1484 ir_node *block = be_transform_node(get_nodes_block(node));
1485 ir_node *op = get_Abs_op(node);
1486 ir_node *new_op = be_transform_node(op);
1487 ir_graph *irg = current_ir_graph;
1488 dbg_info *dbgi = get_irn_dbg_info(node);
1489 ir_mode *mode = get_irn_mode(node);
1490 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1491 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1492 ir_node *nomem = new_NoMem();
1497 if (mode_is_float(mode)) {
1499 if (USE_SSE2(env_cg)) {
1500 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1502 size = get_mode_size_bits(mode);
1503 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1505 set_ia32_am_sc(res, ent);
1507 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1509 set_ia32_op_type(res, ia32_AddrModeS);
1510 set_ia32_ls_mode(res, mode);
1513 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1514 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1518 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1519 SET_IA32_ORIG_NODE(sign_extension,
1520 ia32_get_old_node_name(env_cg, node));
1522 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1523 sign_extension, nomem);
1524 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1526 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1527 sign_extension, nomem);
1528 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 * Transforms a Load.
1539 * @return the created ia32 Load node
1541 static ir_node *gen_Load(ir_node *node) {
1542 ir_node *block = be_transform_node(get_nodes_block(node));
1543 ir_node *ptr = get_Load_ptr(node);
1544 ir_node *new_ptr = be_transform_node(ptr);
1545 ir_node *mem = get_Load_mem(node);
1546 ir_node *new_mem = be_transform_node(mem);
1547 ir_graph *irg = current_ir_graph;
1548 dbg_info *dbgi = get_irn_dbg_info(node);
1549 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1550 ir_mode *mode = get_Load_mode(node);
1552 ir_node *lptr = new_ptr;
1555 ir_node *projs[pn_Load_max];
1556 ia32_am_flavour_t am_flav = ia32_am_B;
1558 ia32_collect_Projs(node, projs, pn_Load_max);
1560 /* address might be a constant (symconst or absolute address) */
1561 if (is_ia32_Const(new_ptr)) {
1566 if (mode_is_float(mode)) {
1568 if (USE_SSE2(env_cg)) {
1569 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1570 res_mode = mode_xmm;
1572 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1573 res_mode = mode_vfp;
1576 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1581 check for special case: the loaded value might not be used
1583 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1584 /* add a result proj and a Keep to produce a pseudo use */
1585 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1587 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1590 /* base is a constant address */
1592 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1593 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1594 am_flav = ia32_am_N;
1596 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1597 long offs = get_tarval_long(tv);
1599 add_ia32_am_offs_int(new_op, offs);
1600 am_flav = ia32_am_O;
1604 set_irn_pinned(new_op, get_irn_pinned(node));
1605 set_ia32_op_type(new_op, ia32_AddrModeS);
1606 set_ia32_am_flavour(new_op, am_flav);
1607 set_ia32_ls_mode(new_op, mode);
1609 /* make sure we are scheduled behind the initial IncSP/Barrier
1610 * to avoid spills being placed before it
1612 if (block == get_irg_start_block(irg)) {
1613 add_irn_dep(new_op, get_irg_frame(irg));
1616 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1617 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1625 * Transforms a Store.
1627 * @return the created ia32 Store node
1629 static ir_node *gen_Store(ir_node *node) {
1630 ir_node *block = be_transform_node(get_nodes_block(node));
1631 ir_node *ptr = get_Store_ptr(node);
1632 ir_node *new_ptr = be_transform_node(ptr);
1633 ir_node *val = get_Store_value(node);
1635 ir_node *mem = get_Store_mem(node);
1636 ir_node *new_mem = be_transform_node(mem);
1637 ir_graph *irg = current_ir_graph;
1638 dbg_info *dbgi = get_irn_dbg_info(node);
1639 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1640 ir_node *sptr = new_ptr;
1641 ir_mode *mode = get_irn_mode(val);
1644 ia32_am_flavour_t am_flav = ia32_am_B;
1646 /* address might be a constant (symconst or absolute address) */
1647 if (is_ia32_Const(new_ptr)) {
1652 if (mode_is_float(mode)) {
1655 new_val = be_transform_node(val);
1656 if (USE_SSE2(env_cg)) {
1657 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1660 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1664 new_val = create_immediate_or_transform(val, 0);
1666 if (get_mode_size_bits(mode) == 8) {
1667 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1670 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1675 /* base is an constant address */
1677 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1678 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1679 am_flav = ia32_am_N;
1681 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1682 long offs = get_tarval_long(tv);
1684 add_ia32_am_offs_int(new_op, offs);
1685 am_flav = ia32_am_O;
1689 set_irn_pinned(new_op, get_irn_pinned(node));
1690 set_ia32_op_type(new_op, ia32_AddrModeD);
1691 set_ia32_am_flavour(new_op, am_flav);
1692 set_ia32_ls_mode(new_op, mode);
1694 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1695 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1700 static ir_node *try_create_TestJmp(ir_node *block, ir_node *node, long pnc)
1702 ir_node *cmp_a = get_Cmp_left(node);
1704 ir_node *cmp_b = get_Cmp_right(node);
1714 if(!is_Const(cmp_b))
1717 tv = get_Const_tarval(cmp_b);
1718 if(!tarval_is_null(tv))
1721 if(is_And(cmp_a) && (pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg)) {
1722 and_left = get_And_left(cmp_a);
1723 and_right = get_And_right(cmp_a);
1725 new_cmp_a = be_transform_node(and_left);
1726 new_cmp_b = create_immediate_or_transform(and_right, 0);
1728 new_cmp_a = be_transform_node(cmp_a);
1729 new_cmp_b = be_transform_node(cmp_a);
1732 dbgi = get_irn_dbg_info(node);
1733 noreg = ia32_new_NoReg_gp(env_cg);
1734 nomem = new_NoMem();
1736 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1737 new_cmp_a, new_cmp_b, nomem, pnc);
1738 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1739 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1744 static ir_node *create_Switch(ir_node *node)
1746 ir_graph *irg = current_ir_graph;
1747 dbg_info *dbgi = get_irn_dbg_info(node);
1748 ir_node *block = be_transform_node(get_nodes_block(node));
1749 ir_node *sel = get_Cond_selector(node);
1750 ir_node *new_sel = be_transform_node(sel);
1752 int switch_min = INT_MAX;
1753 const ir_edge_t *edge;
1755 /* determine the smallest switch case value */
1756 foreach_out_edge(node, edge) {
1757 ir_node *proj = get_edge_src_irn(edge);
1758 int pn = get_Proj_proj(proj);
1763 if (switch_min != 0) {
1764 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1766 /* if smallest switch case is not 0 we need an additional sub */
1767 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1768 add_ia32_am_offs_int(new_sel, -switch_min);
1769 set_ia32_am_flavour(new_sel, ia32_am_OB);
1770 set_ia32_op_type(new_sel, ia32_AddrModeS);
1772 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1775 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1776 set_ia32_pncode(res, get_Cond_defaultProj(node));
1778 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1784 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1786 * @return The transformed node.
1788 static ir_node *gen_Cond(ir_node *node) {
1789 ir_node *block = be_transform_node(get_nodes_block(node));
1790 ir_graph *irg = current_ir_graph;
1791 dbg_info *dbgi = get_irn_dbg_info(node);
1792 ir_node *sel = get_Cond_selector(node);
1793 ir_mode *sel_mode = get_irn_mode(sel);
1794 ir_node *res = NULL;
1795 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1802 ir_node *nomem = new_NoMem();
1805 if (sel_mode != mode_b) {
1806 return create_Switch(node);
1809 cmp = get_Proj_pred(sel);
1810 cmp_a = get_Cmp_left(cmp);
1811 cmp_b = get_Cmp_right(cmp);
1812 cmp_mode = get_irn_mode(cmp_a);
1813 pnc = get_Proj_proj(sel);
1814 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1815 pnc |= ia32_pn_Cmp_Unsigned;
1818 if(mode_needs_gp_reg(cmp_mode)) {
1819 res = try_create_TestJmp(block, cmp, pnc);
1824 new_cmp_a = be_transform_node(cmp_a);
1825 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1827 if (mode_is_float(cmp_mode)) {
1829 if (USE_SSE2(env_cg)) {
1830 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1832 set_ia32_commutative(res);
1833 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1834 set_ia32_ls_mode(res, cmp_mode);
1837 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1838 set_ia32_commutative(res);
1839 proj_eax = new_r_Proj(irg, block, res, mode_Iu,
1840 pn_ia32_vfCondJmp_temp_reg_eax);
1841 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1,
1845 assert(get_mode_size_bits(cmp_mode) == 32);
1846 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1847 new_cmp_a, new_cmp_b, nomem, pnc);
1848 set_ia32_commutative(res);
1849 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1852 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1860 * Transforms a CopyB node.
1862 * @return The transformed node.
1864 static ir_node *gen_CopyB(ir_node *node) {
1865 ir_node *block = be_transform_node(get_nodes_block(node));
1866 ir_node *src = get_CopyB_src(node);
1867 ir_node *new_src = be_transform_node(src);
1868 ir_node *dst = get_CopyB_dst(node);
1869 ir_node *new_dst = be_transform_node(dst);
1870 ir_node *mem = get_CopyB_mem(node);
1871 ir_node *new_mem = be_transform_node(mem);
1872 ir_node *res = NULL;
1873 ir_graph *irg = current_ir_graph;
1874 dbg_info *dbgi = get_irn_dbg_info(node);
1875 int size = get_type_size_bytes(get_CopyB_type(node));
1876 ir_mode *dst_mode = get_irn_mode(dst);
1877 ir_mode *src_mode = get_irn_mode(src);
1881 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1882 /* then we need the size explicitly in ECX. */
1883 if (size >= 32 * 4) {
1884 rem = size & 0x3; /* size % 4 */
1887 res = new_rd_ia32_Const(dbgi, irg, block);
1888 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1889 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1891 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1892 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1894 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1895 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1896 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1897 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1898 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1901 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1902 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1904 /* ok: now attach Proj's because movsd will destroy esi and edi */
1905 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1906 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1907 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1910 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1916 ir_node *gen_be_Copy(ir_node *node)
1918 ir_node *result = be_duplicate_node(node);
1919 ir_mode *mode = get_irn_mode(result);
1921 if (mode_needs_gp_reg(mode)) {
1922 set_irn_mode(result, mode_Iu);
1931 * Transforms a Mux node into CMov.
1933 * @return The transformed node.
1935 static ir_node *gen_Mux(ir_node *node) {
1936 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1937 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1939 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1945 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1946 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1947 ir_node *psi_default);
1950 * Transforms a Psi node into CMov.
1952 * @return The transformed node.
1954 static ir_node *gen_Psi(ir_node *node) {
1955 ir_node *block = be_transform_node(get_nodes_block(node));
1956 ir_node *psi_true = get_Psi_val(node, 0);
1957 ir_node *psi_default = get_Psi_default(node);
1958 ia32_code_gen_t *cg = env_cg;
1959 ir_graph *irg = current_ir_graph;
1960 dbg_info *dbgi = get_irn_dbg_info(node);
1961 ir_node *cond = get_Psi_cond(node, 0);
1962 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1963 ir_node *nomem = new_NoMem();
1965 ir_node *cmp, *cmp_a, *cmp_b;
1966 ir_node *new_cmp_a, *new_cmp_b;
1970 assert(get_Psi_n_conds(node) == 1);
1971 assert(get_irn_mode(cond) == mode_b);
1973 if(is_And(cond) || is_Or(cond)) {
1974 ir_node *new_cond = be_transform_node(cond);
1975 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
1976 arch_set_irn_register(env_cg->arch_env, zero,
1977 &ia32_gp_regs[REG_GP_NOREG]);
1979 /* we have to compare the result against zero */
1980 new_cmp_a = new_cond;
1985 cmp = get_Proj_pred(cond);
1986 cmp_a = get_Cmp_left(cmp);
1987 cmp_b = get_Cmp_right(cmp);
1988 cmp_mode = get_irn_mode(cmp_a);
1989 pnc = get_Proj_proj(cond);
1991 new_cmp_a = be_transform_node(cmp_a);
1992 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1994 if (!mode_is_signed(cmp_mode)) {
1995 pnc |= ia32_pn_Cmp_Unsigned;
1999 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2000 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2001 new_cmp_a, new_cmp_b, nomem, pnc);
2002 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2003 pnc = get_negated_pnc(pnc, cmp_mode);
2004 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2005 new_cmp_a, new_cmp_b, nomem, pnc);
2007 ir_node *new_psi_true = be_transform_node(psi_true);
2008 ir_node *new_psi_default = be_transform_node(psi_default);
2009 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2010 new_psi_true, new_psi_default, pnc);
2012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2018 * Following conversion rules apply:
2022 * 1) n bit -> m bit n > m (downscale)
2024 * 2) n bit -> m bit n == m (sign change)
2026 * 3) n bit -> m bit n < m (upscale)
2027 * a) source is signed: movsx
2028 * b) source is unsigned: and with lower bits sets
2032 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2036 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2040 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2041 * x87 is mode_E internally, conversions happen only at load and store
2042 * in non-strict semantic
2046 * Create a conversion from x87 state register to general purpose.
2048 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2049 ir_node *block = be_transform_node(get_nodes_block(node));
2050 ir_node *op = get_Conv_op(node);
2051 ir_node *new_op = be_transform_node(op);
2052 ia32_code_gen_t *cg = env_cg;
2053 ir_graph *irg = current_ir_graph;
2054 dbg_info *dbgi = get_irn_dbg_info(node);
2055 ir_node *noreg = ia32_new_NoReg_gp(cg);
2056 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2057 ir_node *fist, *load;
2060 fist = new_rd_ia32_vfist(dbgi, irg, block,
2061 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2063 set_irn_pinned(fist, op_pin_state_floats);
2064 set_ia32_use_frame(fist);
2065 set_ia32_op_type(fist, ia32_AddrModeD);
2066 set_ia32_am_flavour(fist, ia32_am_B);
2067 set_ia32_ls_mode(fist, mode_Iu);
2068 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2071 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2073 set_irn_pinned(load, op_pin_state_floats);
2074 set_ia32_use_frame(load);
2075 set_ia32_op_type(load, ia32_AddrModeS);
2076 set_ia32_am_flavour(load, ia32_am_B);
2077 set_ia32_ls_mode(load, mode_Iu);
2078 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2080 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2084 * Create a conversion from general purpose to x87 register
2086 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2087 ir_node *block = be_transform_node(get_nodes_block(node));
2088 ir_node *op = get_Conv_op(node);
2089 ir_node *new_op = be_transform_node(op);
2090 ir_graph *irg = current_ir_graph;
2091 dbg_info *dbgi = get_irn_dbg_info(node);
2092 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2093 ir_node *nomem = new_NoMem();
2094 ir_node *fild, *store;
2097 /* first convert to 32 bit if necessary */
2098 src_bits = get_mode_size_bits(src_mode);
2099 if (src_bits == 8) {
2100 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2101 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2102 set_ia32_ls_mode(new_op, src_mode);
2103 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2104 } else if (src_bits < 32) {
2105 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2106 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2107 set_ia32_ls_mode(new_op, src_mode);
2108 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2112 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2114 set_ia32_use_frame(store);
2115 set_ia32_op_type(store, ia32_AddrModeD);
2116 set_ia32_am_flavour(store, ia32_am_OB);
2117 set_ia32_ls_mode(store, mode_Iu);
2120 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2122 set_ia32_use_frame(fild);
2123 set_ia32_op_type(fild, ia32_AddrModeS);
2124 set_ia32_am_flavour(fild, ia32_am_OB);
2125 set_ia32_ls_mode(fild, mode_Iu);
2127 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2130 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2133 ir_node *block = get_nodes_block(node);
2134 ir_graph *irg = current_ir_graph;
2135 dbg_info *dbgi = get_irn_dbg_info(node);
2136 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2137 ir_node *nomem = new_NoMem();
2138 int src_bits = get_mode_size_bits(src_mode);
2139 int tgt_bits = get_mode_size_bits(tgt_mode);
2140 ir_node *frame = get_irg_frame(irg);
2141 ir_mode *smaller_mode;
2142 ir_node *store, *load;
2145 if(src_bits <= tgt_bits)
2146 smaller_mode = src_mode;
2148 smaller_mode = tgt_mode;
2150 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2152 set_ia32_use_frame(store);
2153 set_ia32_op_type(store, ia32_AddrModeD);
2154 set_ia32_am_flavour(store, ia32_am_OB);
2156 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2158 set_ia32_use_frame(load);
2159 set_ia32_op_type(load, ia32_AddrModeS);
2160 set_ia32_am_flavour(load, ia32_am_OB);
2162 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2167 * Transforms a Conv node.
2169 * @return The created ia32 Conv node
2171 static ir_node *gen_Conv(ir_node *node) {
2172 ir_node *block = be_transform_node(get_nodes_block(node));
2173 ir_node *op = get_Conv_op(node);
2174 ir_node *new_op = be_transform_node(op);
2175 ir_graph *irg = current_ir_graph;
2176 dbg_info *dbgi = get_irn_dbg_info(node);
2177 ir_mode *src_mode = get_irn_mode(op);
2178 ir_mode *tgt_mode = get_irn_mode(node);
2179 int src_bits = get_mode_size_bits(src_mode);
2180 int tgt_bits = get_mode_size_bits(tgt_mode);
2181 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2182 ir_node *nomem = new_rd_NoMem(irg);
2185 if (src_mode == tgt_mode) {
2186 if (get_Conv_strict(node)) {
2187 if (USE_SSE2(env_cg)) {
2188 /* when we are in SSE mode, we can kill all strict no-op conversion */
2192 /* this should be optimized already, but who knows... */
2193 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2194 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2199 if (mode_is_float(src_mode)) {
2200 /* we convert from float ... */
2201 if (mode_is_float(tgt_mode)) {
2202 if(src_mode == mode_E && tgt_mode == mode_D
2203 && !get_Conv_strict(node)) {
2204 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2209 if (USE_SSE2(env_cg)) {
2210 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2211 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2212 set_ia32_ls_mode(res, tgt_mode);
2214 // Matze: TODO what about strict convs?
2215 if(get_Conv_strict(node)) {
2216 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2217 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2220 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2225 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2226 if (USE_SSE2(env_cg)) {
2227 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2228 set_ia32_ls_mode(res, src_mode);
2230 return gen_x87_fp_to_gp(node);
2234 /* we convert from int ... */
2235 if (mode_is_float(tgt_mode)) {
2238 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2239 if (USE_SSE2(env_cg)) {
2240 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2241 set_ia32_ls_mode(res, tgt_mode);
2242 if(src_bits == 32) {
2243 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2246 return gen_x87_gp_to_fp(node, src_mode);
2250 ir_mode *smaller_mode;
2253 if (src_bits == tgt_bits) {
2254 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2258 if (src_bits < tgt_bits) {
2259 smaller_mode = src_mode;
2260 smaller_bits = src_bits;
2262 smaller_mode = tgt_mode;
2263 smaller_bits = tgt_bits;
2266 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2267 if (smaller_bits == 8) {
2268 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2269 set_ia32_ls_mode(res, smaller_mode);
2271 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2272 set_ia32_ls_mode(res, smaller_mode);
2274 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2278 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2284 int check_immediate_constraint(long val, char immediate_constraint_type)
2286 switch (immediate_constraint_type) {
2290 return val >= 0 && val <= 32;
2292 return val >= 0 && val <= 63;
2294 return val >= -128 && val <= 127;
2296 return val == 0xff || val == 0xffff;
2298 return val >= 0 && val <= 3;
2300 return val >= 0 && val <= 255;
2302 return val >= 0 && val <= 127;
2306 panic("Invalid immediate constraint found");
2311 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2314 tarval *offset = NULL;
2315 int offset_sign = 0;
2317 ir_entity *symconst_ent = NULL;
2318 int symconst_sign = 0;
2320 ir_node *cnst = NULL;
2321 ir_node *symconst = NULL;
2327 mode = get_irn_mode(node);
2328 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2329 !mode_is_reference(mode)) {
2333 if(is_Minus(node)) {
2335 node = get_Minus_op(node);
2338 if(is_Const(node)) {
2341 offset_sign = minus;
2342 } else if(is_SymConst(node)) {
2345 symconst_sign = minus;
2346 } else if(is_Add(node)) {
2347 ir_node *left = get_Add_left(node);
2348 ir_node *right = get_Add_right(node);
2349 if(is_Const(left) && is_SymConst(right)) {
2352 symconst_sign = minus;
2353 offset_sign = minus;
2354 } else if(is_SymConst(left) && is_Const(right)) {
2357 symconst_sign = minus;
2358 offset_sign = minus;
2360 } else if(is_Sub(node)) {
2361 ir_node *left = get_Sub_left(node);
2362 ir_node *right = get_Sub_right(node);
2363 if(is_Const(left) && is_SymConst(right)) {
2366 symconst_sign = !minus;
2367 offset_sign = minus;
2368 } else if(is_SymConst(left) && is_Const(right)) {
2371 symconst_sign = minus;
2372 offset_sign = !minus;
2379 offset = get_Const_tarval(cnst);
2380 if(tarval_is_long(offset)) {
2381 val = get_tarval_long(offset);
2382 } else if(tarval_is_null(offset)) {
2385 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2390 if(!check_immediate_constraint(val, immediate_constraint_type))
2393 if(symconst != NULL) {
2394 if(immediate_constraint_type != 0) {
2395 /* we need full 32bits for symconsts */
2399 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2401 symconst_ent = get_SymConst_entity(symconst);
2403 if(cnst == NULL && symconst == NULL)
2406 if(offset_sign && offset != NULL) {
2407 offset = tarval_neg(offset);
2410 irg = current_ir_graph;
2411 dbgi = get_irn_dbg_info(node);
2412 block = get_irg_start_block(irg);
2413 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2415 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2417 /* make sure we don't schedule stuff before the barrier */
2418 add_irn_dep(res, get_irg_frame(irg));
2424 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2426 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2427 if (new_node == NULL) {
2428 new_node = be_transform_node(node);
2433 typedef struct constraint_t constraint_t;
2434 struct constraint_t {
2437 const arch_register_req_t **out_reqs;
2439 const arch_register_req_t *req;
2440 unsigned immediate_possible;
2441 char immediate_type;
2444 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2446 int immediate_possible = 0;
2447 char immediate_type = 0;
2448 unsigned limited = 0;
2449 const arch_register_class_t *cls = NULL;
2451 struct obstack *obst;
2452 arch_register_req_t *req;
2453 unsigned *limited_ptr;
2457 /* TODO: replace all the asserts with nice error messages */
2459 printf("Constraint: %s\n", c);
2469 assert(cls == NULL ||
2470 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2471 cls = &ia32_reg_classes[CLASS_ia32_gp];
2472 limited |= 1 << REG_EAX;
2475 assert(cls == NULL ||
2476 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2477 cls = &ia32_reg_classes[CLASS_ia32_gp];
2478 limited |= 1 << REG_EBX;
2481 assert(cls == NULL ||
2482 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2483 cls = &ia32_reg_classes[CLASS_ia32_gp];
2484 limited |= 1 << REG_ECX;
2487 assert(cls == NULL ||
2488 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2489 cls = &ia32_reg_classes[CLASS_ia32_gp];
2490 limited |= 1 << REG_EDX;
2493 assert(cls == NULL ||
2494 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2495 cls = &ia32_reg_classes[CLASS_ia32_gp];
2496 limited |= 1 << REG_EDI;
2499 assert(cls == NULL ||
2500 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2501 cls = &ia32_reg_classes[CLASS_ia32_gp];
2502 limited |= 1 << REG_ESI;
2505 case 'q': /* q means lower part of the regs only, this makes no
2506 * difference to Q for us (we only assigne whole registers) */
2507 assert(cls == NULL ||
2508 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2509 cls = &ia32_reg_classes[CLASS_ia32_gp];
2510 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2514 assert(cls == NULL ||
2515 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2516 cls = &ia32_reg_classes[CLASS_ia32_gp];
2517 limited |= 1 << REG_EAX | 1 << REG_EDX;
2520 assert(cls == NULL ||
2521 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2522 cls = &ia32_reg_classes[CLASS_ia32_gp];
2523 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2524 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2531 assert(cls == NULL);
2532 cls = &ia32_reg_classes[CLASS_ia32_gp];
2538 /* TODO: mark values so the x87 simulator knows about t and u */
2539 assert(cls == NULL);
2540 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2545 assert(cls == NULL);
2546 /* TODO: check that sse2 is supported */
2547 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2557 assert(!immediate_possible);
2558 immediate_possible = 1;
2559 immediate_type = *c;
2563 assert(!immediate_possible);
2564 immediate_possible = 1;
2568 assert(!immediate_possible && cls == NULL);
2569 immediate_possible = 1;
2570 cls = &ia32_reg_classes[CLASS_ia32_gp];
2583 assert(constraint->is_in && "can only specify same constraint "
2586 sscanf(c, "%d%n", &same_as, &p);
2593 case 'E': /* no float consts yet */
2594 case 'F': /* no float consts yet */
2595 case 's': /* makes no sense on x86 */
2596 case 'X': /* we can't support that in firm */
2600 case '<': /* no autodecrement on x86 */
2601 case '>': /* no autoincrement on x86 */
2602 case 'C': /* sse constant not supported yet */
2603 case 'G': /* 80387 constant not supported yet */
2604 case 'y': /* we don't support mmx registers yet */
2605 case 'Z': /* not available in 32 bit mode */
2606 case 'e': /* not available in 32 bit mode */
2607 assert(0 && "asm constraint not supported");
2610 assert(0 && "unknown asm constraint found");
2617 const arch_register_req_t *other_constr;
2619 assert(cls == NULL && "same as and register constraint not supported");
2620 assert(!immediate_possible && "same as and immediate constraint not "
2622 assert(same_as < constraint->n_outs && "wrong constraint number in "
2623 "same_as constraint");
2625 other_constr = constraint->out_reqs[same_as];
2627 req = obstack_alloc(obst, sizeof(req[0]));
2628 req->cls = other_constr->cls;
2629 req->type = arch_register_req_type_should_be_same;
2630 req->limited = NULL;
2631 req->other_same = pos;
2632 req->other_different = -1;
2634 /* switch constraints. This is because in firm we have same_as
2635 * constraints on the output constraints while in the gcc asm syntax
2636 * they are specified on the input constraints */
2637 constraint->req = other_constr;
2638 constraint->out_reqs[same_as] = req;
2639 constraint->immediate_possible = 0;
2643 if(immediate_possible && cls == NULL) {
2644 cls = &ia32_reg_classes[CLASS_ia32_gp];
2646 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2647 assert(cls != NULL);
2649 if(immediate_possible) {
2650 assert(constraint->is_in
2651 && "imeediates make no sense for output constraints");
2653 /* todo: check types (no float input on 'r' constrainted in and such... */
2655 irg = current_ir_graph;
2656 obst = get_irg_obstack(irg);
2659 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2660 limited_ptr = (unsigned*) (req+1);
2662 req = obstack_alloc(obst, sizeof(req[0]));
2664 memset(req, 0, sizeof(req[0]));
2667 req->type = arch_register_req_type_limited;
2668 *limited_ptr = limited;
2669 req->limited = limited_ptr;
2671 req->type = arch_register_req_type_normal;
2675 constraint->req = req;
2676 constraint->immediate_possible = immediate_possible;
2677 constraint->immediate_type = immediate_type;
2681 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2688 panic("Clobbers not supported yet");
2691 ir_node *gen_ASM(ir_node *node)
2694 ir_graph *irg = current_ir_graph;
2695 ir_node *block = be_transform_node(get_nodes_block(node));
2696 dbg_info *dbgi = get_irn_dbg_info(node);
2703 ia32_asm_attr_t *attr;
2704 const arch_register_req_t **out_reqs;
2705 const arch_register_req_t **in_reqs;
2706 struct obstack *obst;
2707 constraint_t parsed_constraint;
2709 /* assembler could contain float statements */
2712 /* transform inputs */
2713 arity = get_irn_arity(node);
2714 in = alloca(arity * sizeof(in[0]));
2715 memset(in, 0, arity * sizeof(in[0]));
2717 n_outs = get_ASM_n_output_constraints(node);
2718 n_clobbers = get_ASM_n_clobbers(node);
2719 out_arity = n_outs + n_clobbers;
2721 /* construct register constraints */
2722 obst = get_irg_obstack(irg);
2723 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2724 parsed_constraint.out_reqs = out_reqs;
2725 parsed_constraint.n_outs = n_outs;
2726 parsed_constraint.is_in = 0;
2727 for(i = 0; i < out_arity; ++i) {
2731 const ir_asm_constraint *constraint;
2732 constraint = & get_ASM_output_constraints(node) [i];
2733 c = get_id_str(constraint->constraint);
2734 parse_asm_constraint(i, &parsed_constraint, c);
2736 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2737 c = get_id_str(glob_id);
2738 parse_clobber(node, i, &parsed_constraint, c);
2740 out_reqs[i] = parsed_constraint.req;
2743 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2744 parsed_constraint.is_in = 1;
2745 for(i = 0; i < arity; ++i) {
2746 const ir_asm_constraint *constraint;
2750 constraint = & get_ASM_input_constraints(node) [i];
2751 constr_id = constraint->constraint;
2752 c = get_id_str(constr_id);
2753 parse_asm_constraint(i, &parsed_constraint, c);
2754 in_reqs[i] = parsed_constraint.req;
2756 if(parsed_constraint.immediate_possible) {
2757 ir_node *pred = get_irn_n(node, i);
2758 char imm_type = parsed_constraint.immediate_type;
2759 ir_node *immediate = try_create_Immediate(pred, imm_type);
2761 if(immediate != NULL) {
2767 /* transform inputs */
2768 for(i = 0; i < arity; ++i) {
2770 ir_node *transformed;
2775 pred = get_irn_n(node, i);
2776 transformed = be_transform_node(pred);
2777 in[i] = transformed;
2780 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2782 generic_attr = get_irn_generic_attr(res);
2783 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2784 attr->asm_text = get_ASM_text(node);
2785 set_ia32_out_req_all(res, out_reqs);
2786 set_ia32_in_req_all(res, in_reqs);
2788 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2793 /********************************************
2796 * | |__ ___ _ __ ___ __| | ___ ___
2797 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2798 * | |_) | __/ | | | (_) | (_| | __/\__ \
2799 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2801 ********************************************/
2803 static ir_node *gen_be_StackParam(ir_node *node) {
2804 ir_node *block = be_transform_node(get_nodes_block(node));
2805 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2806 ir_node *new_ptr = be_transform_node(ptr);
2807 ir_node *new_op = NULL;
2808 ir_graph *irg = current_ir_graph;
2809 dbg_info *dbgi = get_irn_dbg_info(node);
2810 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2811 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2812 ir_mode *load_mode = get_irn_mode(node);
2813 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2817 if (mode_is_float(load_mode)) {
2819 if (USE_SSE2(env_cg)) {
2820 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2821 pn_res = pn_ia32_xLoad_res;
2822 proj_mode = mode_xmm;
2824 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2825 pn_res = pn_ia32_vfld_res;
2826 proj_mode = mode_vfp;
2829 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2830 proj_mode = mode_Iu;
2831 pn_res = pn_ia32_Load_res;
2834 set_irn_pinned(new_op, op_pin_state_floats);
2835 set_ia32_frame_ent(new_op, ent);
2836 set_ia32_use_frame(new_op);
2838 set_ia32_op_type(new_op, ia32_AddrModeS);
2839 set_ia32_am_flavour(new_op, ia32_am_B);
2840 set_ia32_ls_mode(new_op, load_mode);
2841 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2843 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2845 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2849 * Transforms a FrameAddr into an ia32 Add.
2851 static ir_node *gen_be_FrameAddr(ir_node *node) {
2852 ir_node *block = be_transform_node(get_nodes_block(node));
2853 ir_node *op = be_get_FrameAddr_frame(node);
2854 ir_node *new_op = be_transform_node(op);
2855 ir_graph *irg = current_ir_graph;
2856 dbg_info *dbgi = get_irn_dbg_info(node);
2857 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2860 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2861 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2862 set_ia32_use_frame(res);
2863 set_ia32_am_flavour(res, ia32_am_OB);
2865 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2871 * Transforms a FrameLoad into an ia32 Load.
2873 static ir_node *gen_be_FrameLoad(ir_node *node) {
2874 ir_node *block = be_transform_node(get_nodes_block(node));
2875 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2876 ir_node *new_mem = be_transform_node(mem);
2877 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2878 ir_node *new_ptr = be_transform_node(ptr);
2879 ir_node *new_op = NULL;
2880 ir_graph *irg = current_ir_graph;
2881 dbg_info *dbgi = get_irn_dbg_info(node);
2882 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2883 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2884 ir_mode *mode = get_type_mode(get_entity_type(ent));
2885 ir_node *projs[pn_Load_max];
2887 ia32_collect_Projs(node, projs, pn_Load_max);
2889 if (mode_is_float(mode)) {
2891 if (USE_SSE2(env_cg)) {
2892 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2895 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2899 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2902 set_irn_pinned(new_op, op_pin_state_floats);
2903 set_ia32_frame_ent(new_op, ent);
2904 set_ia32_use_frame(new_op);
2906 set_ia32_op_type(new_op, ia32_AddrModeS);
2907 set_ia32_am_flavour(new_op, ia32_am_B);
2908 set_ia32_ls_mode(new_op, mode);
2909 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2911 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2918 * Transforms a FrameStore into an ia32 Store.
2920 static ir_node *gen_be_FrameStore(ir_node *node) {
2921 ir_node *block = be_transform_node(get_nodes_block(node));
2922 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2923 ir_node *new_mem = be_transform_node(mem);
2924 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2925 ir_node *new_ptr = be_transform_node(ptr);
2926 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2927 ir_node *new_val = be_transform_node(val);
2928 ir_node *new_op = NULL;
2929 ir_graph *irg = current_ir_graph;
2930 dbg_info *dbgi = get_irn_dbg_info(node);
2931 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2932 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2933 ir_mode *mode = get_irn_mode(val);
2935 if (mode_is_float(mode)) {
2937 if (USE_SSE2(env_cg)) {
2938 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2940 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2942 } else if (get_mode_size_bits(mode) == 8) {
2943 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2945 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2948 set_ia32_frame_ent(new_op, ent);
2949 set_ia32_use_frame(new_op);
2951 set_ia32_op_type(new_op, ia32_AddrModeD);
2952 set_ia32_am_flavour(new_op, ia32_am_B);
2953 set_ia32_ls_mode(new_op, mode);
2955 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2961 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2963 static ir_node *gen_be_Return(ir_node *node) {
2964 ir_graph *irg = current_ir_graph;
2965 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2966 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2967 ir_entity *ent = get_irg_entity(irg);
2968 ir_type *tp = get_entity_type(ent);
2973 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2974 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2977 int pn_ret_val, pn_ret_mem, arity, i;
2979 assert(ret_val != NULL);
2980 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2981 return be_duplicate_node(node);
2984 res_type = get_method_res_type(tp, 0);
2986 if (! is_Primitive_type(res_type)) {
2987 return be_duplicate_node(node);
2990 mode = get_type_mode(res_type);
2991 if (! mode_is_float(mode)) {
2992 return be_duplicate_node(node);
2995 assert(get_method_n_ress(tp) == 1);
2997 pn_ret_val = get_Proj_proj(ret_val);
2998 pn_ret_mem = get_Proj_proj(ret_mem);
3000 /* get the Barrier */
3001 barrier = get_Proj_pred(ret_val);
3003 /* get result input of the Barrier */
3004 ret_val = get_irn_n(barrier, pn_ret_val);
3005 new_ret_val = be_transform_node(ret_val);
3007 /* get memory input of the Barrier */
3008 ret_mem = get_irn_n(barrier, pn_ret_mem);
3009 new_ret_mem = be_transform_node(ret_mem);
3011 frame = get_irg_frame(irg);
3013 dbgi = get_irn_dbg_info(barrier);
3014 block = be_transform_node(get_nodes_block(barrier));
3016 noreg = ia32_new_NoReg_gp(env_cg);
3018 /* store xmm0 onto stack */
3019 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3020 set_ia32_ls_mode(sse_store, mode);
3021 set_ia32_op_type(sse_store, ia32_AddrModeD);
3022 set_ia32_use_frame(sse_store);
3023 set_ia32_am_flavour(sse_store, ia32_am_B);
3026 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3027 set_ia32_ls_mode(fld, mode);
3028 set_ia32_op_type(fld, ia32_AddrModeS);
3029 set_ia32_use_frame(fld);
3030 set_ia32_am_flavour(fld, ia32_am_B);
3032 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3033 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3034 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3036 /* create a new barrier */
3037 arity = get_irn_arity(barrier);
3038 in = alloca(arity * sizeof(in[0]));
3039 for (i = 0; i < arity; ++i) {
3042 if (i == pn_ret_val) {
3044 } else if (i == pn_ret_mem) {
3047 ir_node *in = get_irn_n(barrier, i);
3048 new_in = be_transform_node(in);
3053 new_barrier = new_ir_node(dbgi, irg, block,
3054 get_irn_op(barrier), get_irn_mode(barrier),
3056 copy_node_attr(barrier, new_barrier);
3057 be_duplicate_deps(barrier, new_barrier);
3058 be_set_transformed_node(barrier, new_barrier);
3059 mark_irn_visited(barrier);
3061 /* transform normally */
3062 return be_duplicate_node(node);
3066 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3068 static ir_node *gen_be_AddSP(ir_node *node) {
3069 ir_node *block = be_transform_node(get_nodes_block(node));
3070 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3072 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3073 ir_node *new_sp = be_transform_node(sp);
3074 ir_graph *irg = current_ir_graph;
3075 dbg_info *dbgi = get_irn_dbg_info(node);
3076 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3077 ir_node *nomem = new_NoMem();
3080 new_sz = create_immediate_or_transform(sz, 0);
3082 /* ia32 stack grows in reverse direction, make a SubSP */
3083 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3085 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3086 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3092 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3094 static ir_node *gen_be_SubSP(ir_node *node) {
3095 ir_node *block = be_transform_node(get_nodes_block(node));
3096 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3098 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3099 ir_node *new_sp = be_transform_node(sp);
3100 ir_graph *irg = current_ir_graph;
3101 dbg_info *dbgi = get_irn_dbg_info(node);
3102 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3103 ir_node *nomem = new_NoMem();
3106 new_sz = create_immediate_or_transform(sz, 0);
3108 /* ia32 stack grows in reverse direction, make an AddSP */
3109 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3110 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3111 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3117 * This function just sets the register for the Unknown node
3118 * as this is not done during register allocation because Unknown
3119 * is an "ignore" node.
3121 static ir_node *gen_Unknown(ir_node *node) {
3122 ir_mode *mode = get_irn_mode(node);
3124 if (mode_is_float(mode)) {
3125 if (USE_SSE2(env_cg))
3126 return ia32_new_Unknown_xmm(env_cg);
3128 return ia32_new_Unknown_vfp(env_cg);
3129 } else if (mode_needs_gp_reg(mode)) {
3130 return ia32_new_Unknown_gp(env_cg);
3132 assert(0 && "unsupported Unknown-Mode");
3139 * Change some phi modes
3141 static ir_node *gen_Phi(ir_node *node) {
3142 ir_node *block = be_transform_node(get_nodes_block(node));
3143 ir_graph *irg = current_ir_graph;
3144 dbg_info *dbgi = get_irn_dbg_info(node);
3145 ir_mode *mode = get_irn_mode(node);
3148 if(mode_needs_gp_reg(mode)) {
3149 /* we shouldn't have any 64bit stuff around anymore */
3150 assert(get_mode_size_bits(mode) <= 32);
3151 /* all integer operations are on 32bit registers now */
3153 } else if(mode_is_float(mode)) {
3154 if (USE_SSE2(env_cg)) {
3161 /* phi nodes allow loops, so we use the old arguments for now
3162 * and fix this later */
3163 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3164 copy_node_attr(node, phi);
3165 be_duplicate_deps(node, phi);
3167 be_set_transformed_node(node, phi);
3168 be_enqueue_preds(node);
3173 /**********************************************************************
3176 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3177 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3178 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3179 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3181 **********************************************************************/
3183 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3185 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3188 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3189 ir_node *val, ir_node *mem);
3192 * Transforms a lowered Load into a "real" one.
3194 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3195 ir_node *block = be_transform_node(get_nodes_block(node));
3196 ir_node *ptr = get_irn_n(node, 0);
3197 ir_node *new_ptr = be_transform_node(ptr);
3198 ir_node *mem = get_irn_n(node, 1);
3199 ir_node *new_mem = be_transform_node(mem);
3200 ir_graph *irg = current_ir_graph;
3201 dbg_info *dbgi = get_irn_dbg_info(node);
3202 ir_mode *mode = get_ia32_ls_mode(node);
3203 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3207 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3208 lowering we have x87 nodes, so we need to enforce simulation.
3210 if (mode_is_float(mode)) {
3212 if (fp_unit == fp_x87)
3216 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3218 set_ia32_op_type(new_op, ia32_AddrModeS);
3219 set_ia32_am_flavour(new_op, ia32_am_OB);
3220 set_ia32_am_offs_int(new_op, 0);
3221 set_ia32_am_scale(new_op, 1);
3222 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3223 if (is_ia32_am_sc_sign(node))
3224 set_ia32_am_sc_sign(new_op);
3225 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3226 if (is_ia32_use_frame(node)) {
3227 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3228 set_ia32_use_frame(new_op);
3231 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3237 * Transforms a lowered Store into a "real" one.
3239 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3240 ir_node *block = be_transform_node(get_nodes_block(node));
3241 ir_node *ptr = get_irn_n(node, 0);
3242 ir_node *new_ptr = be_transform_node(ptr);
3243 ir_node *val = get_irn_n(node, 1);
3244 ir_node *new_val = be_transform_node(val);
3245 ir_node *mem = get_irn_n(node, 2);
3246 ir_node *new_mem = be_transform_node(mem);
3247 ir_graph *irg = current_ir_graph;
3248 dbg_info *dbgi = get_irn_dbg_info(node);
3249 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3250 ir_mode *mode = get_ia32_ls_mode(node);
3253 ia32_am_flavour_t am_flav = ia32_B;
3256 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3257 lowering we have x87 nodes, so we need to enforce simulation.
3259 if (mode_is_float(mode)) {
3261 if (fp_unit == fp_x87)
3265 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3267 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3269 add_ia32_am_offs_int(new_op, am_offs);
3272 set_ia32_op_type(new_op, ia32_AddrModeD);
3273 set_ia32_am_flavour(new_op, am_flav);
3274 set_ia32_ls_mode(new_op, mode);
3275 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3276 set_ia32_use_frame(new_op);
3278 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3285 * Transforms an ia32_l_XXX into a "real" XXX node
3287 * @param env The transformation environment
3288 * @return the created ia32 XXX node
3290 #define GEN_LOWERED_OP(op) \
3291 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3292 ir_mode *mode = get_irn_mode(node); \
3293 if (mode_is_float(mode)) \
3295 return gen_binop(node, get_binop_left(node), \
3296 get_binop_right(node), new_rd_ia32_##op,0); \
3299 #define GEN_LOWERED_x87_OP(op) \
3300 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3302 FORCE_x87(env_cg); \
3303 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3304 get_binop_right(node), new_rd_ia32_##op); \
3308 #define GEN_LOWERED_UNOP(op) \
3309 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3310 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3313 #define GEN_LOWERED_SHIFT_OP(op) \
3314 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3315 return gen_shift_binop(node, get_binop_left(node), \
3316 get_binop_right(node), new_rd_ia32_##op); \
3319 #define GEN_LOWERED_LOAD(op, fp_unit) \
3320 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3321 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3324 #define GEN_LOWERED_STORE(op, fp_unit) \
3325 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3326 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3333 GEN_LOWERED_OP(IMul)
3335 GEN_LOWERED_x87_OP(vfprem)
3336 GEN_LOWERED_x87_OP(vfmul)
3337 GEN_LOWERED_x87_OP(vfsub)
3339 GEN_LOWERED_UNOP(Neg)
3341 GEN_LOWERED_LOAD(vfild, fp_x87)
3342 GEN_LOWERED_LOAD(Load, fp_none)
3343 /*GEN_LOWERED_STORE(vfist, fp_x87)
3346 GEN_LOWERED_STORE(Store, fp_none)
3348 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3349 ir_node *block = be_transform_node(get_nodes_block(node));
3350 ir_node *left = get_binop_left(node);
3351 ir_node *new_left = be_transform_node(left);
3352 ir_node *right = get_binop_right(node);
3353 ir_node *new_right = be_transform_node(right);
3354 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3355 ir_graph *irg = current_ir_graph;
3356 dbg_info *dbgi = get_irn_dbg_info(node);
3357 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3358 &ia32_fp_cw_regs[REG_FPCW]);
3361 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3362 new_right, new_NoMem(), fpcw);
3363 clear_ia32_commutative(vfdiv);
3364 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3366 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3374 * Transforms a l_MulS into a "real" MulS node.
3376 * @param env The transformation environment
3377 * @return the created ia32 Mul node
3379 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3380 ir_node *block = be_transform_node(get_nodes_block(node));
3381 ir_node *left = get_binop_left(node);
3382 ir_node *new_left = be_transform_node(left);
3383 ir_node *right = get_binop_right(node);
3384 ir_node *new_right = be_transform_node(right);
3385 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3386 ir_graph *irg = current_ir_graph;
3387 dbg_info *dbgi = get_irn_dbg_info(node);
3390 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3391 /* and then skip the result Proj, because all needed Projs are already there. */
3392 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3393 new_right, new_NoMem());
3394 clear_ia32_commutative(muls);
3395 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3397 /* check if EAX and EDX proj exist, add missing one */
3398 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3399 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3400 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3402 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3407 GEN_LOWERED_SHIFT_OP(Shl)
3408 GEN_LOWERED_SHIFT_OP(Shr)
3409 GEN_LOWERED_SHIFT_OP(Sar)
3412 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3413 * op1 - target to be shifted
3414 * op2 - contains bits to be shifted into target
3416 * Only op3 can be an immediate.
3418 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3419 ir_node *op2, ir_node *count)
3421 ir_node *block = be_transform_node(get_nodes_block(node));
3422 ir_node *new_op1 = be_transform_node(op1);
3423 ir_node *new_op2 = be_transform_node(op2);
3424 ir_node *new_count = be_transform_node(count);
3425 ir_node *new_op = NULL;
3426 ir_graph *irg = current_ir_graph;
3427 dbg_info *dbgi = get_irn_dbg_info(node);
3428 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3429 ir_node *nomem = new_NoMem();
3433 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3435 /* Check if immediate optimization is on and */
3436 /* if it's an operation with immediate. */
3437 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3439 /* Limit imm_op within range imm8 */
3441 tv = get_ia32_Immop_tarval(imm_op);
3444 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3445 set_ia32_Immop_tarval(imm_op, tv);
3452 /* integer operations */
3454 /* This is ShiftD with const */
3455 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3457 if (is_ia32_l_ShlD(node))
3458 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3459 new_op1, new_op2, noreg, nomem);
3461 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3462 new_op1, new_op2, noreg, nomem);
3463 copy_ia32_Immop_attr(new_op, imm_op);
3466 /* This is a normal ShiftD */
3467 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3468 if (is_ia32_l_ShlD(node))
3469 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3470 new_op1, new_op2, new_count, nomem);
3472 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3473 new_op1, new_op2, new_count, nomem);
3476 /* set AM support */
3477 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3479 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3481 set_ia32_emit_cl(new_op);
3486 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3487 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3488 get_irn_n(node, 1), get_irn_n(node, 2));
3491 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3492 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3493 get_irn_n(node, 1), get_irn_n(node, 2));
3497 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3499 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3500 ir_node *block = be_transform_node(get_nodes_block(node));
3501 ir_node *val = get_irn_n(node, 1);
3502 ir_node *new_val = be_transform_node(val);
3503 ia32_code_gen_t *cg = env_cg;
3504 ir_node *res = NULL;
3505 ir_graph *irg = current_ir_graph;
3507 ir_node *noreg, *new_ptr, *new_mem;
3514 mem = get_irn_n(node, 2);
3515 new_mem = be_transform_node(mem);
3516 ptr = get_irn_n(node, 0);
3517 new_ptr = be_transform_node(ptr);
3518 noreg = ia32_new_NoReg_gp(cg);
3519 dbgi = get_irn_dbg_info(node);
3521 /* Store x87 -> MEM */
3522 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3523 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3524 set_ia32_use_frame(res);
3525 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3526 set_ia32_am_flavour(res, ia32_B);
3527 set_ia32_op_type(res, ia32_AddrModeD);
3529 /* Load MEM -> SSE */
3530 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3531 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3532 set_ia32_use_frame(res);
3533 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3534 set_ia32_am_flavour(res, ia32_B);
3535 set_ia32_op_type(res, ia32_AddrModeS);
3536 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3542 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3544 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3545 ir_node *block = be_transform_node(get_nodes_block(node));
3546 ir_node *val = get_irn_n(node, 1);
3547 ir_node *new_val = be_transform_node(val);
3548 ia32_code_gen_t *cg = env_cg;
3549 ir_graph *irg = current_ir_graph;
3550 ir_node *res = NULL;
3551 ir_entity *fent = get_ia32_frame_ent(node);
3552 ir_mode *lsmode = get_ia32_ls_mode(node);
3554 ir_node *noreg, *new_ptr, *new_mem;
3558 if (! USE_SSE2(cg)) {
3559 /* SSE unit is not used -> skip this node. */
3563 ptr = get_irn_n(node, 0);
3564 new_ptr = be_transform_node(ptr);
3565 mem = get_irn_n(node, 2);
3566 new_mem = be_transform_node(mem);
3567 noreg = ia32_new_NoReg_gp(cg);
3568 dbgi = get_irn_dbg_info(node);
3570 /* Store SSE -> MEM */
3571 if (is_ia32_xLoad(skip_Proj(new_val))) {
3572 ir_node *ld = skip_Proj(new_val);
3574 /* we can vfld the value directly into the fpu */
3575 fent = get_ia32_frame_ent(ld);
3576 ptr = get_irn_n(ld, 0);
3577 offs = get_ia32_am_offs_int(ld);
3579 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3580 set_ia32_frame_ent(res, fent);
3581 set_ia32_use_frame(res);
3582 set_ia32_ls_mode(res, lsmode);
3583 set_ia32_am_flavour(res, ia32_B);
3584 set_ia32_op_type(res, ia32_AddrModeD);
3588 /* Load MEM -> x87 */
3589 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3590 set_ia32_frame_ent(res, fent);
3591 set_ia32_use_frame(res);
3592 add_ia32_am_offs_int(res, offs);
3593 set_ia32_am_flavour(res, ia32_B);
3594 set_ia32_op_type(res, ia32_AddrModeS);
3595 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3600 /*********************************************************
3603 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3604 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3605 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3606 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3608 *********************************************************/
3611 * the BAD transformer.
3613 static ir_node *bad_transform(ir_node *node) {
3614 panic("No transform function for %+F available.\n", node);
3619 * Transform the Projs of an AddSP.
3621 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3622 ir_node *block = be_transform_node(get_nodes_block(node));
3623 ir_node *pred = get_Proj_pred(node);
3624 ir_node *new_pred = be_transform_node(pred);
3625 ir_graph *irg = current_ir_graph;
3626 dbg_info *dbgi = get_irn_dbg_info(node);
3627 long proj = get_Proj_proj(node);
3629 if (proj == pn_be_AddSP_res) {
3630 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3631 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3633 } else if (proj == pn_be_AddSP_M) {
3634 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3638 return new_rd_Unknown(irg, get_irn_mode(node));
3642 * Transform the Projs of a SubSP.
3644 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3645 ir_node *block = be_transform_node(get_nodes_block(node));
3646 ir_node *pred = get_Proj_pred(node);
3647 ir_node *new_pred = be_transform_node(pred);
3648 ir_graph *irg = current_ir_graph;
3649 dbg_info *dbgi = get_irn_dbg_info(node);
3650 long proj = get_Proj_proj(node);
3652 if (proj == pn_be_SubSP_res) {
3653 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3654 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3656 } else if (proj == pn_be_SubSP_M) {
3657 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3661 return new_rd_Unknown(irg, get_irn_mode(node));
3665 * Transform and renumber the Projs from a Load.
3667 static ir_node *gen_Proj_Load(ir_node *node) {
3668 ir_node *block = be_transform_node(get_nodes_block(node));
3669 ir_node *pred = get_Proj_pred(node);
3670 ir_node *new_pred = be_transform_node(pred);
3671 ir_graph *irg = current_ir_graph;
3672 dbg_info *dbgi = get_irn_dbg_info(node);
3673 long proj = get_Proj_proj(node);
3675 /* renumber the proj */
3676 if (is_ia32_Load(new_pred)) {
3677 if (proj == pn_Load_res) {
3678 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3679 } else if (proj == pn_Load_M) {
3680 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3682 } else if (is_ia32_xLoad(new_pred)) {
3683 if (proj == pn_Load_res) {
3684 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3685 } else if (proj == pn_Load_M) {
3686 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3688 } else if (is_ia32_vfld(new_pred)) {
3689 if (proj == pn_Load_res) {
3690 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3691 } else if (proj == pn_Load_M) {
3692 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3697 return new_rd_Unknown(irg, get_irn_mode(node));
3701 * Transform and renumber the Projs from a DivMod like instruction.
3703 static ir_node *gen_Proj_DivMod(ir_node *node) {
3704 ir_node *block = be_transform_node(get_nodes_block(node));
3705 ir_node *pred = get_Proj_pred(node);
3706 ir_node *new_pred = be_transform_node(pred);
3707 ir_graph *irg = current_ir_graph;
3708 dbg_info *dbgi = get_irn_dbg_info(node);
3709 ir_mode *mode = get_irn_mode(node);
3710 long proj = get_Proj_proj(node);
3712 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3714 switch (get_irn_opcode(pred)) {
3718 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3720 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3728 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3730 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3739 case pn_DivMod_res_div:
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3741 case pn_DivMod_res_mod:
3742 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3752 return new_rd_Unknown(irg, mode);
3756 * Transform and renumber the Projs from a CopyB.
3758 static ir_node *gen_Proj_CopyB(ir_node *node) {
3759 ir_node *block = be_transform_node(get_nodes_block(node));
3760 ir_node *pred = get_Proj_pred(node);
3761 ir_node *new_pred = be_transform_node(pred);
3762 ir_graph *irg = current_ir_graph;
3763 dbg_info *dbgi = get_irn_dbg_info(node);
3764 ir_mode *mode = get_irn_mode(node);
3765 long proj = get_Proj_proj(node);
3768 case pn_CopyB_M_regular:
3769 if (is_ia32_CopyB_i(new_pred)) {
3770 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3771 } else if (is_ia32_CopyB(new_pred)) {
3772 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3780 return new_rd_Unknown(irg, mode);
3784 * Transform and renumber the Projs from a vfdiv.
3786 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3787 ir_node *block = be_transform_node(get_nodes_block(node));
3788 ir_node *pred = get_Proj_pred(node);
3789 ir_node *new_pred = be_transform_node(pred);
3790 ir_graph *irg = current_ir_graph;
3791 dbg_info *dbgi = get_irn_dbg_info(node);
3792 ir_mode *mode = get_irn_mode(node);
3793 long proj = get_Proj_proj(node);
3796 case pn_ia32_l_vfdiv_M:
3797 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3798 case pn_ia32_l_vfdiv_res:
3799 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3804 return new_rd_Unknown(irg, mode);
3808 * Transform and renumber the Projs from a Quot.
3810 static ir_node *gen_Proj_Quot(ir_node *node) {
3811 ir_node *block = be_transform_node(get_nodes_block(node));
3812 ir_node *pred = get_Proj_pred(node);
3813 ir_node *new_pred = be_transform_node(pred);
3814 ir_graph *irg = current_ir_graph;
3815 dbg_info *dbgi = get_irn_dbg_info(node);
3816 ir_mode *mode = get_irn_mode(node);
3817 long proj = get_Proj_proj(node);
3821 if (is_ia32_xDiv(new_pred)) {
3822 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3823 } else if (is_ia32_vfdiv(new_pred)) {
3824 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3828 if (is_ia32_xDiv(new_pred)) {
3829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3830 } else if (is_ia32_vfdiv(new_pred)) {
3831 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3839 return new_rd_Unknown(irg, mode);
3843 * Transform the Thread Local Storage Proj.
3845 static ir_node *gen_Proj_tls(ir_node *node) {
3846 ir_node *block = be_transform_node(get_nodes_block(node));
3847 ir_graph *irg = current_ir_graph;
3848 dbg_info *dbgi = NULL;
3849 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3855 * Transform the Projs from a be_Call.
3857 static ir_node *gen_Proj_be_Call(ir_node *node) {
3858 ir_node *block = be_transform_node(get_nodes_block(node));
3859 ir_node *call = get_Proj_pred(node);
3860 ir_node *new_call = be_transform_node(call);
3861 ir_graph *irg = current_ir_graph;
3862 dbg_info *dbgi = get_irn_dbg_info(node);
3863 long proj = get_Proj_proj(node);
3864 ir_mode *mode = get_irn_mode(node);
3866 const arch_register_class_t *cls;
3868 /* The following is kinda tricky: If we're using SSE, then we have to
3869 * move the result value of the call in floating point registers to an
3870 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3871 * after the call, we have to make sure to correctly make the
3872 * MemProj and the result Proj use these 2 nodes
3874 if (proj == pn_be_Call_M_regular) {
3875 // get new node for result, are we doing the sse load/store hack?
3876 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3877 ir_node *call_res_new;
3878 ir_node *call_res_pred = NULL;
3880 if (call_res != NULL) {
3881 call_res_new = be_transform_node(call_res);
3882 call_res_pred = get_Proj_pred(call_res_new);
3885 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3886 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3888 assert(is_ia32_xLoad(call_res_pred));
3889 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3892 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3894 ir_node *frame = get_irg_frame(irg);
3895 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3897 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3899 const arch_register_class_t *cls;
3901 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3902 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3904 /* store st(0) onto stack */
3905 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3907 set_ia32_ls_mode(fstp, mode);
3908 set_ia32_op_type(fstp, ia32_AddrModeD);
3909 set_ia32_use_frame(fstp);
3910 set_ia32_am_flavour(fstp, ia32_am_B);
3912 /* load into SSE register */
3913 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3914 set_ia32_ls_mode(sse_load, mode);
3915 set_ia32_op_type(sse_load, ia32_AddrModeS);
3916 set_ia32_use_frame(sse_load);
3917 set_ia32_am_flavour(sse_load, ia32_am_B);
3919 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3921 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3923 /* get a Proj representing a caller save register */
3924 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3925 assert(is_Proj(p) && "Proj expected.");
3927 /* user of the the proj is the Keep */
3928 p = get_edge_src_irn(get_irn_out_edge_first(p));
3929 assert(be_is_Keep(p) && "Keep expected.");
3931 /* keep the result */
3932 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3933 keepin[0] = sse_load;
3934 be_new_Keep(cls, irg, block, 1, keepin);
3939 /* transform call modes */
3940 if (mode_is_data(mode)) {
3941 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3945 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3949 * Transform the Projs from a Cmp.
3951 static ir_node *gen_Proj_Cmp(ir_node *node)
3953 /* normally Cmps are processed when looking at Cond nodes, but this case
3954 * can happen in complicated Psi conditions */
3956 ir_graph *irg = current_ir_graph;
3957 dbg_info *dbgi = get_irn_dbg_info(node);
3958 ir_node *block = be_transform_node(get_nodes_block(node));
3959 ir_node *cmp = get_Proj_pred(node);
3960 long pnc = get_Proj_proj(node);
3961 ir_node *cmp_left = get_Cmp_left(cmp);
3962 ir_node *cmp_right = get_Cmp_right(cmp);
3963 ir_node *new_cmp_left;
3964 ir_node *new_cmp_right;
3965 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3966 ir_node *nomem = new_rd_NoMem(irg);
3967 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3970 assert(!mode_is_float(cmp_mode));
3972 /* (a != b) -> (a ^ b) */
3973 if(pnc == pn_Cmp_Lg) {
3974 if(is_Const_0(cmp_left)) {
3975 new_op = be_transform_node(cmp_right);
3976 } else if(is_Const_0(cmp_right)) {
3977 new_op = be_transform_node(cmp_left);
3979 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
3985 * (a == b) -> !(a ^ b)
3986 * (a < 0) -> (a & 0x80000000) oder a >> 31
3987 * (a >= 0) -> (a >> 31) ^ 1
3990 if(!mode_is_signed(cmp_mode)) {
3991 pnc |= ia32_pn_Cmp_Unsigned;
3994 new_cmp_left = be_transform_node(cmp_left);
3995 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
3997 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
3998 new_cmp_right, nomem, pnc);
3999 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4005 * Transform and potentially renumber Proj nodes.
4007 static ir_node *gen_Proj(ir_node *node) {
4008 ir_graph *irg = current_ir_graph;
4009 dbg_info *dbgi = get_irn_dbg_info(node);
4010 ir_node *pred = get_Proj_pred(node);
4011 long proj = get_Proj_proj(node);
4013 if (is_Store(pred) || be_is_FrameStore(pred)) {
4014 if (proj == pn_Store_M) {
4015 return be_transform_node(pred);
4018 return new_r_Bad(irg);
4020 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4021 return gen_Proj_Load(node);
4022 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4023 return gen_Proj_DivMod(node);
4024 } else if (is_CopyB(pred)) {
4025 return gen_Proj_CopyB(node);
4026 } else if (is_Quot(pred)) {
4027 return gen_Proj_Quot(node);
4028 } else if (is_ia32_l_vfdiv(pred)) {
4029 return gen_Proj_l_vfdiv(node);
4030 } else if (be_is_SubSP(pred)) {
4031 return gen_Proj_be_SubSP(node);
4032 } else if (be_is_AddSP(pred)) {
4033 return gen_Proj_be_AddSP(node);
4034 } else if (be_is_Call(pred)) {
4035 return gen_Proj_be_Call(node);
4036 } else if (is_Cmp(pred)) {
4037 return gen_Proj_Cmp(node);
4038 } else if (get_irn_op(pred) == op_Start) {
4039 if (proj == pn_Start_X_initial_exec) {
4040 ir_node *block = get_nodes_block(pred);
4043 /* we exchange the ProjX with a jump */
4044 block = be_transform_node(block);
4045 jump = new_rd_Jmp(dbgi, irg, block);
4048 if (node == be_get_old_anchor(anchor_tls)) {
4049 return gen_Proj_tls(node);
4052 ir_node *new_pred = be_transform_node(pred);
4053 ir_node *block = be_transform_node(get_nodes_block(node));
4054 ir_mode *mode = get_irn_mode(node);
4055 if (mode_needs_gp_reg(mode)) {
4056 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4057 get_Proj_proj(node));
4058 #ifdef DEBUG_libfirm
4059 new_proj->node_nr = node->node_nr;
4065 return be_duplicate_node(node);
4069 * Enters all transform functions into the generic pointer
4071 static void register_transformers(void) {
4072 ir_op *op_Max, *op_Min, *op_Mulh;
4074 /* first clear the generic function pointer for all ops */
4075 clear_irp_opcodes_generic_func();
4077 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4078 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4115 /* transform ops from intrinsic lowering */
4135 /* GEN(ia32_l_vfist); TODO */
4137 GEN(ia32_l_X87toSSE);
4138 GEN(ia32_l_SSEtoX87);
4143 /* we should never see these nodes */
4158 /* handle generic backend nodes */
4169 /* set the register for all Unknown nodes */
4172 op_Max = get_op_Max();
4175 op_Min = get_op_Min();
4178 op_Mulh = get_op_Mulh();
4187 * Pre-transform all unknown and noreg nodes.
4189 static void ia32_pretransform_node(void *arch_cg) {
4190 ia32_code_gen_t *cg = arch_cg;
4192 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4193 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4194 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4195 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4196 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4197 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4200 /* do the transformation */
4201 void ia32_transform_graph(ia32_code_gen_t *cg) {
4202 register_transformers();
4204 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4207 void ia32_init_transform(void)
4209 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");