2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "archop.h" /* we need this for Min and Max nodes */
57 #include "../benode_t.h"
58 #include "../besched.h"
60 #include "../beutil.h"
61 #include "../beirg_t.h"
63 #include "bearch_ia32_t.h"
64 #include "ia32_nodes_attr.h"
65 #include "ia32_transform.h"
66 #include "ia32_new_nodes.h"
67 #include "ia32_map_regs.h"
68 #include "ia32_dbg_stat.h"
69 #include "ia32_optimize.h"
70 #include "ia32_util.h"
72 #include "gen_ia32_regalloc_if.h"
74 #define SFP_SIGN "0x80000000"
75 #define DFP_SIGN "0x8000000000000000"
76 #define SFP_ABS "0x7FFFFFFF"
77 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 typedef struct ia32_transform_env_t {
95 ir_graph *irg; /**< The irg, the node should be created in */
96 ia32_code_gen_t *cg; /**< The code generator */
97 int visited; /**< visited count that indicates whether a
98 node is already transformed */
99 pdeq *worklist; /**< worklist of nodes that still need to be
101 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
102 } ia32_transform_env_t;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
127 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
128 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
131 static INLINE int mode_needs_gp_reg(ir_mode *mode)
133 if(mode == mode_fpcw)
136 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
139 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
141 set_irn_link(old_node, new_node);
144 static INLINE ir_node *get_new_node(ir_node *old_node)
146 assert(irn_visited(old_node));
147 return (ir_node*) get_irn_link(old_node);
151 * Returns 1 if irn is a Const representing 0, 0 otherwise
153 static INLINE int is_ia32_Const_0(ir_node *irn) {
154 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
155 && tarval_is_null(get_ia32_Immop_tarval(irn));
159 * Returns 1 if irn is a Const representing 1, 0 otherwise
161 static INLINE int is_ia32_Const_1(ir_node *irn) {
162 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
163 && tarval_is_one(get_ia32_Immop_tarval(irn));
167 * Collects all Projs of a node into the node array. Index is the projnum.
168 * BEWARE: The caller has to assure the appropriate array size!
170 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
171 const ir_edge_t *edge;
172 assert(get_irn_mode(irn) == mode_T && "need mode_T");
174 memset(projs, 0, size * sizeof(projs[0]));
176 foreach_out_edge(irn, edge) {
177 ir_node *proj = get_edge_src_irn(edge);
178 int proj_proj = get_Proj_proj(proj);
179 assert(proj_proj < size);
180 projs[proj_proj] = proj;
185 * Renumbers the proj having pn_old in the array tp pn_new
186 * and removes the proj from the array.
188 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
189 fprintf(stderr, "Warning: renumber_Proj used!\n");
191 set_Proj_proj(projs[pn_old], pn_new);
192 projs[pn_old] = NULL;
197 * creates a unique ident by adding a number to a tag
199 * @param tag the tag string, must contain a %d if a number
202 static ident *unique_id(const char *tag)
204 static unsigned id = 0;
207 snprintf(str, sizeof(str), tag, ++id);
208 return new_id_from_str(str);
212 * Get a primitive type for a mode.
214 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
216 pmap_entry *e = pmap_find(types, mode);
221 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
222 res = new_type_primitive(new_id_from_str(buf), mode);
223 pmap_insert(types, mode, res);
231 * Get an entity that is initialized with a tarval
233 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
235 tarval *tv = get_Const_tarval(cnst);
236 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
241 ir_mode *mode = get_irn_mode(cnst);
242 ir_type *tp = get_Const_type(cnst);
243 if (tp == firm_unknown_type)
244 tp = get_prim_type(cg->isa->types, mode);
246 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
248 set_entity_ld_ident(res, get_entity_ident(res));
249 set_entity_visibility(res, visibility_local);
250 set_entity_variability(res, variability_constant);
251 set_entity_allocation(res, allocation_static);
253 /* we create a new entity here: It's initialization must resist on the
255 rem = current_ir_graph;
256 current_ir_graph = get_const_code_irg();
257 set_atomic_ent_value(res, new_Const_type(tv, tp));
258 current_ir_graph = rem;
260 pmap_insert(cg->isa->tv_ent, tv, res);
269 * Transforms a Const.
271 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
272 ir_graph *irg = env->irg;
273 ir_node *block = transform_node(env, get_nodes_block(node));
274 dbg_info *dbgi = get_irn_dbg_info(node);
275 ir_mode *mode = get_irn_mode(node);
277 if (mode_is_float(mode)) {
279 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
280 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env->cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env->cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
298 set_ia32_am_support(load, ia32_am_Source);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env->cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_am_support(load, ia32_am_Source);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(load, get_irg_frame(irg));
327 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
330 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
337 set_ia32_Const_attr(cnst, node);
338 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
343 return new_r_Bad(irg);
347 * Transforms a SymConst.
349 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
350 ir_graph *irg = env->irg;
351 ir_node *block = transform_node(env, get_nodes_block(node));
352 dbg_info *dbgi = get_irn_dbg_info(node);
353 ir_mode *mode = get_irn_mode(node);
356 if (mode_is_float(mode)) {
358 if (USE_SSE2(env->cg))
359 cnst = new_rd_ia32_xConst(dbgi, irg, block);
361 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
362 set_ia32_ls_mode(cnst, mode);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
381 * SSE convert of an integer node into a floating point node.
383 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
384 ir_graph *irg, ir_node *block,
385 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
387 ir_node *noreg = ia32_new_NoReg_gp(cg);
388 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *old_pred = get_Cmp_left(old_node);
390 ir_mode *in_mode = get_irn_mode(old_pred);
391 int in_bits = get_mode_size_bits(in_mode);
392 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_ls_mode(conv, tgt_mode);
396 set_ia32_am_support(conv, ia32_am_Source);
398 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
404 * SSE convert of an float node into a double node.
406 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
407 ir_graph *irg, ir_node *block,
408 ir_node *in, ir_node *old_node)
410 ir_node *noreg = ia32_new_NoReg_gp(cg);
411 ir_node *nomem = new_rd_NoMem(irg);
412 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
414 set_ia32_am_support(conv, ia32_am_Source);
415 set_ia32_ls_mode(conv, mode_xmm);
416 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
421 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
422 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
423 static const struct {
425 const char *ent_name;
426 const char *cnst_str;
427 } names [ia32_known_const_max] = {
428 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
429 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
430 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
431 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
433 static ir_entity *ent_cache[ia32_known_const_max];
435 const char *tp_name, *ent_name, *cnst_str;
443 ent_name = names[kct].ent_name;
444 if (! ent_cache[kct]) {
445 tp_name = names[kct].tp_name;
446 cnst_str = names[kct].cnst_str;
448 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
450 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
451 tp = new_type_primitive(new_id_from_str(tp_name), mode);
452 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
454 set_entity_ld_ident(ent, get_entity_ident(ent));
455 set_entity_visibility(ent, visibility_local);
456 set_entity_variability(ent, variability_constant);
457 set_entity_allocation(ent, allocation_static);
459 /* we create a new entity here: It's initialization must resist on the
461 rem = current_ir_graph;
462 current_ir_graph = get_const_code_irg();
463 cnst = new_Const(mode, tv);
464 current_ir_graph = rem;
466 set_atomic_ent_value(ent, cnst);
468 /* cache the entry */
469 ent_cache[kct] = ent;
472 return ent_cache[kct];
477 * Prints the old node name on cg obst and returns a pointer to it.
479 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
480 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
482 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
483 obstack_1grow(isa->name_obst, 0);
484 return obstack_finish(isa->name_obst);
488 /* determine if one operator is an Imm */
489 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
491 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
493 return is_ia32_Cnst(op2) ? op2 : NULL;
497 /* determine if one operator is not an Imm */
498 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
499 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
502 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
506 if (! (env->cg->opt & IA32_OPT_IMMOPS))
509 left = get_irn_n(node, in1);
510 right = get_irn_n(node, in2);
511 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
512 /* we can only set right operand to immediate */
513 if(!is_ia32_commutative(node))
515 /* exchange left/right */
516 set_irn_n(node, in1, right);
517 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
518 copy_ia32_Immop_attr(node, left);
519 } else if(is_ia32_Cnst(right)) {
520 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
521 copy_ia32_Immop_attr(node, right);
526 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param env The transformation environment
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
539 ir_node *op1, ir_node *op2,
540 construct_binop_func *func)
542 ir_node *block = transform_node(env, get_nodes_block(node));
543 ir_node *new_op1 = transform_node(env, op1);
544 ir_node *new_op2 = transform_node(env, op2);
545 ir_node *new_node = NULL;
546 ir_graph *irg = env->irg;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
549 ir_node *nomem = new_NoMem();
551 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
552 if (func == new_rd_ia32_IMul) {
553 set_ia32_am_support(new_node, ia32_am_Source);
555 set_ia32_am_support(new_node, ia32_am_Full);
558 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
559 if (is_op_commutative(get_irn_op(node))) {
560 set_ia32_commutative(new_node);
562 fold_immediate(env, new_node, 2, 3);
568 * Construct a standard binary operation, set AM and immediate if required.
570 * @param env The transformation environment
571 * @param op1 The first operand
572 * @param op2 The second operand
573 * @param func The node constructor function
574 * @return The constructed ia32 node.
576 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
577 ir_node *op1, ir_node *op2,
578 construct_binop_func *func)
580 ir_node *block = transform_node(env, get_nodes_block(node));
581 ir_node *new_op1 = transform_node(env, op1);
582 ir_node *new_op2 = transform_node(env, op2);
583 ir_node *new_node = NULL;
584 dbg_info *dbgi = get_irn_dbg_info(node);
585 ir_graph *irg = env->irg;
586 ir_mode *mode = get_irn_mode(node);
587 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
588 ir_node *nomem = new_NoMem();
590 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
591 set_ia32_am_support(new_node, ia32_am_Source);
592 if (is_op_commutative(get_irn_op(node))) {
593 set_ia32_commutative(new_node);
595 if (USE_SSE2(env->cg)) {
596 set_ia32_ls_mode(new_node, mode);
599 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
606 * Construct a shift/rotate binary operation, sets AM and immediate if required.
608 * @param env The transformation environment
609 * @param op1 The first operand
610 * @param op2 The second operand
611 * @param func The node constructor function
612 * @return The constructed ia32 node.
614 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
615 ir_node *op1, ir_node *op2,
616 construct_binop_func *func)
618 ir_node *block = transform_node(env, get_nodes_block(node));
619 ir_node *new_op1 = transform_node(env, op1);
620 ir_node *new_op2 = transform_node(env, op2);
621 ir_node *new_op = NULL;
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_graph *irg = env->irg;
624 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
625 ir_node *nomem = new_NoMem();
630 assert(! mode_is_float(get_irn_mode(node))
631 && "Shift/Rotate with float not supported");
633 /* Check if immediate optimization is on and */
634 /* if it's an operation with immediate. */
635 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
636 expr_op = get_expr_op(new_op1, new_op2);
638 assert((expr_op || imm_op) && "invalid operands");
641 /* We have two consts here: not yet supported */
645 /* Limit imm_op within range imm8 */
647 tv = get_ia32_Immop_tarval(imm_op);
650 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
651 set_ia32_Immop_tarval(imm_op, tv);
658 /* integer operations */
660 /* This is shift/rot with const */
661 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
663 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
664 copy_ia32_Immop_attr(new_op, imm_op);
666 /* This is a normal shift/rot */
667 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
668 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
672 set_ia32_am_support(new_op, ia32_am_Dest);
674 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
676 set_ia32_emit_cl(new_op);
683 * Construct a standard unary operation, set AM and immediate if required.
685 * @param env The transformation environment
686 * @param op The operand
687 * @param func The node constructor function
688 * @return The constructed ia32 node.
690 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
691 construct_unop_func *func)
693 ir_node *block = transform_node(env, get_nodes_block(node));
694 ir_node *new_op = transform_node(env, op);
695 ir_node *new_node = NULL;
696 ir_graph *irg = env->irg;
697 dbg_info *dbgi = get_irn_dbg_info(node);
698 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
699 ir_node *nomem = new_NoMem();
701 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
702 DB((dbg, LEVEL_1, "INT unop ..."));
703 set_ia32_am_support(new_node, ia32_am_Dest);
705 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
712 * Creates an ia32 Add.
714 * @param env The transformation environment
715 * @return the created ia32 Add node
717 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
718 ir_node *block = transform_node(env, get_nodes_block(node));
719 ir_node *op1 = get_Add_left(node);
720 ir_node *new_op1 = transform_node(env, op1);
721 ir_node *op2 = get_Add_right(node);
722 ir_node *new_op2 = transform_node(env, op2);
723 ir_node *new_op = NULL;
724 ir_graph *irg = env->irg;
725 dbg_info *dbgi = get_irn_dbg_info(node);
726 ir_mode *mode = get_irn_mode(node);
727 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
728 ir_node *nomem = new_NoMem();
729 ir_node *expr_op, *imm_op;
731 /* Check if immediate optimization is on and */
732 /* if it's an operation with immediate. */
733 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
734 expr_op = get_expr_op(new_op1, new_op2);
736 assert((expr_op || imm_op) && "invalid operands");
738 if (mode_is_float(mode)) {
740 if (USE_SSE2(env->cg))
741 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
743 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
748 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
749 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
751 /* No expr_op means, that we have two const - one symconst and */
752 /* one tarval or another symconst - because this case is not */
753 /* covered by constant folding */
754 /* We need to check for: */
755 /* 1) symconst + const -> becomes a LEA */
756 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
757 /* linker doesn't support two symconsts */
759 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
760 /* this is the 2nd case */
761 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
762 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
763 set_ia32_am_flavour(new_op, ia32_am_OB);
764 set_ia32_am_support(new_op, ia32_am_Source);
765 set_ia32_op_type(new_op, ia32_AddrModeS);
767 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
768 } else if (tp1 == ia32_ImmSymConst) {
769 tarval *tv = get_ia32_Immop_tarval(new_op2);
770 long offs = get_tarval_long(tv);
772 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
773 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
775 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
776 add_ia32_am_offs_int(new_op, offs);
777 set_ia32_am_flavour(new_op, ia32_am_O);
778 set_ia32_am_support(new_op, ia32_am_Source);
779 set_ia32_op_type(new_op, ia32_AddrModeS);
780 } else if (tp2 == ia32_ImmSymConst) {
781 tarval *tv = get_ia32_Immop_tarval(new_op1);
782 long offs = get_tarval_long(tv);
784 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
785 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
787 add_ia32_am_offs_int(new_op, offs);
788 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
789 set_ia32_am_flavour(new_op, ia32_am_O);
790 set_ia32_am_support(new_op, ia32_am_Source);
791 set_ia32_op_type(new_op, ia32_AddrModeS);
793 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
794 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
795 tarval *restv = tarval_add(tv1, tv2);
797 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
799 new_op = new_rd_ia32_Const(dbgi, irg, block);
800 set_ia32_Const_tarval(new_op, restv);
801 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
804 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
807 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
808 tarval_classification_t class_tv, class_negtv;
809 tarval *tv = get_ia32_Immop_tarval(imm_op);
811 /* optimize tarvals */
812 class_tv = classify_tarval(tv);
813 class_negtv = classify_tarval(tarval_neg(tv));
815 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
816 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
817 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
818 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
820 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
821 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
822 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
823 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
829 /* This is a normal add */
830 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
833 set_ia32_am_support(new_op, ia32_am_Full);
834 set_ia32_commutative(new_op);
836 fold_immediate(env, new_op, 2, 3);
838 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
844 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
845 ir_graph *irg = env->irg;
846 dbg_info *dbgi = get_irn_dbg_info(node);
847 ir_node *block = transform_node(env, get_nodes_block(node));
848 ir_node *op1 = get_Mul_left(node);
849 ir_node *op2 = get_Mul_right(node);
850 ir_node *new_op1 = transform_node(env, op1);
851 ir_node *new_op2 = transform_node(env, op2);
852 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
853 ir_node *proj_EAX, *proj_EDX, *res;
856 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source);
860 /* imediates are not supported, so no fold_immediate */
861 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
862 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
866 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
874 * Creates an ia32 Mul.
876 * @param env The transformation environment
877 * @return the created ia32 Mul node
879 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
880 ir_node *op1 = get_Mul_left(node);
881 ir_node *op2 = get_Mul_right(node);
882 ir_mode *mode = get_irn_mode(node);
884 if (mode_is_float(mode)) {
886 if (USE_SSE2(env->cg))
887 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
889 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
893 for the lower 32bit of the result it doesn't matter whether we use
894 signed or unsigned multiplication so we use IMul as it has fewer
897 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
901 * Creates an ia32 Mulh.
902 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
903 * this result while Mul returns the lower 32 bit.
905 * @param env The transformation environment
906 * @return the created ia32 Mulh node
908 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
909 ir_node *block = transform_node(env, get_nodes_block(node));
910 ir_node *op1 = get_irn_n(node, 0);
911 ir_node *new_op1 = transform_node(env, op1);
912 ir_node *op2 = get_irn_n(node, 1);
913 ir_node *new_op2 = transform_node(env, op2);
914 ir_graph *irg = env->irg;
915 dbg_info *dbgi = get_irn_dbg_info(node);
916 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
917 ir_mode *mode = get_irn_mode(node);
918 ir_node *proj_EAX, *proj_EDX, *res;
921 assert(!mode_is_float(mode) && "Mulh with float not supported");
922 if (mode_is_signed(mode)) {
923 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
925 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
928 set_ia32_commutative(res);
929 set_ia32_am_support(res, ia32_am_Source);
931 set_ia32_am_support(res, ia32_am_Source);
933 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
934 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
938 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
946 * Creates an ia32 And.
948 * @param env The transformation environment
949 * @return The created ia32 And node
951 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
952 ir_node *op1 = get_And_left(node);
953 ir_node *op2 = get_And_right(node);
955 assert (! mode_is_float(get_irn_mode(node)));
956 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
962 * Creates an ia32 Or.
964 * @param env The transformation environment
965 * @return The created ia32 Or node
967 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
968 ir_node *op1 = get_Or_left(node);
969 ir_node *op2 = get_Or_right(node);
971 assert (! mode_is_float(get_irn_mode(node)));
972 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
978 * Creates an ia32 Eor.
980 * @param env The transformation environment
981 * @return The created ia32 Eor node
983 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
984 ir_node *op1 = get_Eor_left(node);
985 ir_node *op2 = get_Eor_right(node);
987 assert(! mode_is_float(get_irn_mode(node)));
988 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
994 * Creates an ia32 Max.
996 * @param env The transformation environment
997 * @return the created ia32 Max node
999 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
1000 ir_node *block = transform_node(env, get_nodes_block(node));
1001 ir_node *op1 = get_irn_n(node, 0);
1002 ir_node *new_op1 = transform_node(env, op1);
1003 ir_node *op2 = get_irn_n(node, 1);
1004 ir_node *new_op2 = transform_node(env, op2);
1005 ir_graph *irg = env->irg;
1006 ir_mode *mode = get_irn_mode(node);
1007 dbg_info *dbgi = get_irn_dbg_info(node);
1008 ir_mode *op_mode = get_irn_mode(op1);
1011 assert(get_mode_size_bits(mode) == 32);
1013 if (mode_is_float(mode)) {
1015 if (USE_SSE2(env->cg)) {
1016 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1018 panic("Can't create Max node");
1021 long pnc = pn_Cmp_Gt;
1022 if (! mode_is_signed(op_mode)) {
1023 pnc |= ia32_pn_Cmp_Unsigned;
1025 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1026 set_ia32_pncode(new_op, pnc);
1027 set_ia32_am_support(new_op, ia32_am_None);
1029 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1035 * Creates an ia32 Min.
1037 * @param env The transformation environment
1038 * @return the created ia32 Min node
1040 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1041 ir_node *block = transform_node(env, get_nodes_block(node));
1042 ir_node *op1 = get_irn_n(node, 0);
1043 ir_node *new_op1 = transform_node(env, op1);
1044 ir_node *op2 = get_irn_n(node, 1);
1045 ir_node *new_op2 = transform_node(env, op2);
1046 ir_graph *irg = env->irg;
1047 ir_mode *mode = get_irn_mode(node);
1048 dbg_info *dbgi = get_irn_dbg_info(node);
1049 ir_mode *op_mode = get_irn_mode(op1);
1052 assert(get_mode_size_bits(mode) == 32);
1054 if (mode_is_float(mode)) {
1056 if (USE_SSE2(env->cg)) {
1057 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1059 panic("can't create Min node");
1062 long pnc = pn_Cmp_Lt;
1063 if (! mode_is_signed(op_mode)) {
1064 pnc |= ia32_pn_Cmp_Unsigned;
1066 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1067 set_ia32_pncode(new_op, pnc);
1068 set_ia32_am_support(new_op, ia32_am_None);
1070 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1077 * Creates an ia32 Sub.
1079 * @param env The transformation environment
1080 * @return The created ia32 Sub node
1082 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1083 ir_node *block = transform_node(env, get_nodes_block(node));
1084 ir_node *op1 = get_Sub_left(node);
1085 ir_node *new_op1 = transform_node(env, op1);
1086 ir_node *op2 = get_Sub_right(node);
1087 ir_node *new_op2 = transform_node(env, op2);
1088 ir_node *new_op = NULL;
1089 ir_graph *irg = env->irg;
1090 dbg_info *dbgi = get_irn_dbg_info(node);
1091 ir_mode *mode = get_irn_mode(node);
1092 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1093 ir_node *nomem = new_NoMem();
1094 ir_node *expr_op, *imm_op;
1096 /* Check if immediate optimization is on and */
1097 /* if it's an operation with immediate. */
1098 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1099 expr_op = get_expr_op(new_op1, new_op2);
1101 assert((expr_op || imm_op) && "invalid operands");
1103 if (mode_is_float(mode)) {
1105 if (USE_SSE2(env->cg))
1106 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1108 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1113 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1114 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1116 /* No expr_op means, that we have two const - one symconst and */
1117 /* one tarval or another symconst - because this case is not */
1118 /* covered by constant folding */
1119 /* We need to check for: */
1120 /* 1) symconst - const -> becomes a LEA */
1121 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1122 /* linker doesn't support two symconsts */
1123 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1124 /* this is the 2nd case */
1125 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1126 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1127 set_ia32_am_sc_sign(new_op);
1128 set_ia32_am_flavour(new_op, ia32_am_OB);
1130 DBG_OPT_LEA3(op1, op2, node, new_op);
1131 } else if (tp1 == ia32_ImmSymConst) {
1132 tarval *tv = get_ia32_Immop_tarval(new_op2);
1133 long offs = get_tarval_long(tv);
1135 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1136 DBG_OPT_LEA3(op1, op2, node, new_op);
1138 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1139 add_ia32_am_offs_int(new_op, -offs);
1140 set_ia32_am_flavour(new_op, ia32_am_O);
1141 set_ia32_am_support(new_op, ia32_am_Source);
1142 set_ia32_op_type(new_op, ia32_AddrModeS);
1143 } else if (tp2 == ia32_ImmSymConst) {
1144 tarval *tv = get_ia32_Immop_tarval(new_op1);
1145 long offs = get_tarval_long(tv);
1147 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1148 DBG_OPT_LEA3(op1, op2, node, new_op);
1150 add_ia32_am_offs_int(new_op, offs);
1151 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1152 set_ia32_am_sc_sign(new_op);
1153 set_ia32_am_flavour(new_op, ia32_am_O);
1154 set_ia32_am_support(new_op, ia32_am_Source);
1155 set_ia32_op_type(new_op, ia32_AddrModeS);
1157 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1158 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1159 tarval *restv = tarval_sub(tv1, tv2);
1161 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1163 new_op = new_rd_ia32_Const(dbgi, irg, block);
1164 set_ia32_Const_tarval(new_op, restv);
1165 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1168 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1170 } else if (imm_op) {
1171 if ((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1172 tarval_classification_t class_tv, class_negtv;
1173 tarval *tv = get_ia32_Immop_tarval(imm_op);
1175 /* optimize tarvals */
1176 class_tv = classify_tarval(tv);
1177 class_negtv = classify_tarval(tarval_neg(tv));
1179 if (class_tv == TV_CLASSIFY_ONE) {
1180 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1181 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1184 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1185 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1186 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1187 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1193 /* This is a normal sub */
1194 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1196 /* set AM support */
1197 set_ia32_am_support(new_op, ia32_am_Full);
1199 fold_immediate(env, new_op, 2, 3);
1201 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1209 * Generates an ia32 DivMod with additional infrastructure for the
1210 * register allocator if needed.
1212 * @param env The transformation environment
1213 * @param dividend -no comment- :)
1214 * @param divisor -no comment- :)
1215 * @param dm_flav flavour_Div/Mod/DivMod
1216 * @return The created ia32 DivMod node
1218 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1219 ir_node *dividend, ir_node *divisor,
1220 ia32_op_flavour_t dm_flav)
1222 ir_node *block = transform_node(env, get_nodes_block(node));
1223 ir_node *new_dividend = transform_node(env, dividend);
1224 ir_node *new_divisor = transform_node(env, divisor);
1225 ir_graph *irg = env->irg;
1226 dbg_info *dbgi = get_irn_dbg_info(node);
1227 ir_mode *mode = get_irn_mode(node);
1228 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1229 ir_node *res, *proj_div, *proj_mod;
1230 ir_node *edx_node, *cltd;
1231 ir_node *in_keep[2];
1232 ir_node *mem, *new_mem;
1233 ir_node *projs[pn_DivMod_max];
1236 ia32_collect_Projs(node, projs, pn_DivMod_max);
1240 mem = get_Div_mem(node);
1241 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1242 if (proj_div == NULL) {
1243 /* this can happen when we have divs left that could
1244 throw a division by zero exception... */
1247 mode = get_irn_mode(proj_div);
1251 mem = get_Mod_mem(node);
1252 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1253 if (proj_mod == NULL) {
1254 /* this can happen when we have divs left that could
1255 throw a division by zero exception... */
1258 mode = get_irn_mode(proj_mod);
1261 case flavour_DivMod:
1262 mem = get_DivMod_mem(node);
1263 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1264 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1265 if (proj_div != NULL) {
1266 mode = get_irn_mode(proj_div);
1267 } else if(proj_mod != NULL) {
1268 mode = get_irn_mode(proj_mod);
1270 /* this can happen when we have divs left that could
1271 throw a division by zero exception... */
1276 panic("invalid divmod flavour!");
1278 new_mem = transform_node(env, mem);
1280 if (mode_is_signed(mode)) {
1281 /* in signed mode, we need to sign extend the dividend */
1282 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1283 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1284 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1286 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1287 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1288 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1291 if (mode_is_signed(mode)) {
1292 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1294 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1297 /* Matze: code can't handle this at the moment... */
1299 /* set AM support */
1300 set_ia32_am_support(res, ia32_am_Source);
1303 set_ia32_n_res(res, 2);
1305 /* check, which Proj-Keep, we need to add */
1307 if (proj_div == NULL) {
1308 /* We have only mod result: add div res Proj-Keep */
1309 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1312 if (proj_mod == NULL) {
1313 /* We have only div result: add mod res Proj-Keep */
1314 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1318 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1327 * Wrapper for generate_DivMod. Sets flavour_Mod.
1329 * @param env The transformation environment
1331 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1332 return generate_DivMod(env, node, get_Mod_left(node),
1333 get_Mod_right(node), flavour_Mod);
1337 * Wrapper for generate_DivMod. Sets flavour_Div.
1339 * @param env The transformation environment
1341 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1342 return generate_DivMod(env, node, get_Div_left(node),
1343 get_Div_right(node), flavour_Div);
1347 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1349 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1350 return generate_DivMod(env, node, get_DivMod_left(node),
1351 get_DivMod_right(node), flavour_DivMod);
1357 * Creates an ia32 floating Div.
1359 * @param env The transformation environment
1360 * @return The created ia32 xDiv node
1362 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1363 ir_node *block = transform_node(env, get_nodes_block(node));
1364 ir_node *op1 = get_Quot_left(node);
1365 ir_node *new_op1 = transform_node(env, op1);
1366 ir_node *op2 = get_Quot_right(node);
1367 ir_node *new_op2 = transform_node(env, op2);
1368 ir_graph *irg = env->irg;
1369 dbg_info *dbgi = get_irn_dbg_info(node);
1370 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1371 ir_node *nomem = new_rd_NoMem(env->irg);
1375 if (USE_SSE2(env->cg)) {
1376 ir_mode *mode = get_irn_mode(op1);
1377 if (is_ia32_xConst(new_op2)) {
1378 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1379 set_ia32_am_support(new_op, ia32_am_None);
1380 copy_ia32_Immop_attr(new_op, new_op2);
1382 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1383 // Matze: disabled for now, spillslot coalescer fails
1384 //set_ia32_am_support(new_op, ia32_am_Source);
1386 set_ia32_ls_mode(new_op, mode);
1388 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1389 // Matze: disabled for now (spillslot coalescer fails)
1390 //set_ia32_am_support(new_op, ia32_am_Source);
1392 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1398 * Creates an ia32 Shl.
1400 * @param env The transformation environment
1401 * @return The created ia32 Shl node
1403 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1404 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1411 * Creates an ia32 Shr.
1413 * @param env The transformation environment
1414 * @return The created ia32 Shr node
1416 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1417 return gen_shift_binop(env, node, get_Shr_left(node),
1418 get_Shr_right(node), new_rd_ia32_Shr);
1424 * Creates an ia32 Sar.
1426 * @param env The transformation environment
1427 * @return The created ia32 Shrs node
1429 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1430 return gen_shift_binop(env, node, get_Shrs_left(node),
1431 get_Shrs_right(node), new_rd_ia32_Sar);
1437 * Creates an ia32 RotL.
1439 * @param env The transformation environment
1440 * @param op1 The first operator
1441 * @param op2 The second operator
1442 * @return The created ia32 RotL node
1444 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1445 ir_node *op1, ir_node *op2) {
1446 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1452 * Creates an ia32 RotR.
1453 * NOTE: There is no RotR with immediate because this would always be a RotL
1454 * "imm-mode_size_bits" which can be pre-calculated.
1456 * @param env The transformation environment
1457 * @param op1 The first operator
1458 * @param op2 The second operator
1459 * @return The created ia32 RotR node
1461 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1463 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1469 * Creates an ia32 RotR or RotL (depending on the found pattern).
1471 * @param env The transformation environment
1472 * @return The created ia32 RotL or RotR node
1474 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1475 ir_node *rotate = NULL;
1476 ir_node *op1 = get_Rot_left(node);
1477 ir_node *op2 = get_Rot_right(node);
1479 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1480 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1481 that means we can create a RotR instead of an Add and a RotL */
1483 if (get_irn_op(op2) == op_Add) {
1485 ir_node *left = get_Add_left(add);
1486 ir_node *right = get_Add_right(add);
1487 if (is_Const(right)) {
1488 tarval *tv = get_Const_tarval(right);
1489 ir_mode *mode = get_irn_mode(node);
1490 long bits = get_mode_size_bits(mode);
1492 if (get_irn_op(left) == op_Minus &&
1493 tarval_is_long(tv) &&
1494 get_tarval_long(tv) == bits)
1496 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1497 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1502 if (rotate == NULL) {
1503 rotate = gen_RotL(env, node, op1, op2);
1512 * Transforms a Minus node.
1514 * @param env The transformation environment
1515 * @param op The Minus operand
1516 * @return The created ia32 Minus node
1518 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1519 ir_node *block = transform_node(env, get_nodes_block(node));
1520 ir_graph *irg = env->irg;
1521 dbg_info *dbgi = get_irn_dbg_info(node);
1522 ir_mode *mode = get_irn_mode(node);
1527 if (mode_is_float(mode)) {
1528 ir_node *new_op = transform_node(env, op);
1530 if (USE_SSE2(env->cg)) {
1531 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1532 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1533 ir_node *nomem = new_rd_NoMem(irg);
1535 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1537 size = get_mode_size_bits(mode);
1538 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1540 set_ia32_am_sc(res, ent);
1541 set_ia32_op_type(res, ia32_AddrModeS);
1542 set_ia32_ls_mode(res, mode);
1544 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1547 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1550 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1556 * Transforms a Minus node.
1558 * @param env The transformation environment
1559 * @return The created ia32 Minus node
1561 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1562 return gen_Minus_ex(env, node, get_Minus_op(node));
1567 * Transforms a Not node.
1569 * @param env The transformation environment
1570 * @return The created ia32 Not node
1572 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1573 ir_node *op = get_Not_op(node);
1575 assert (! mode_is_float(get_irn_mode(node)));
1576 return gen_unop(env, node, op, new_rd_ia32_Not);
1582 * Transforms an Abs node.
1584 * @param env The transformation environment
1585 * @return The created ia32 Abs node
1587 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1588 ir_node *block = transform_node(env, get_nodes_block(node));
1589 ir_node *op = get_Abs_op(node);
1590 ir_node *new_op = transform_node(env, op);
1591 ir_graph *irg = env->irg;
1592 dbg_info *dbgi = get_irn_dbg_info(node);
1593 ir_mode *mode = get_irn_mode(node);
1594 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1595 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1596 ir_node *nomem = new_NoMem();
1597 ir_node *res, *p_eax, *p_edx;
1601 if (mode_is_float(mode)) {
1603 if (USE_SSE2(env->cg)) {
1604 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1606 size = get_mode_size_bits(mode);
1607 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1609 set_ia32_am_sc(res, ent);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1613 set_ia32_op_type(res, ia32_AddrModeS);
1614 set_ia32_ls_mode(res, mode);
1617 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1618 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1622 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1623 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1625 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1626 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1628 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1629 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1631 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1632 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1641 * Transforms a Load.
1643 * @param env The transformation environment
1644 * @return the created ia32 Load node
1646 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1647 ir_node *block = transform_node(env, get_nodes_block(node));
1648 ir_node *ptr = get_Load_ptr(node);
1649 ir_node *new_ptr = transform_node(env, ptr);
1650 ir_node *mem = get_Load_mem(node);
1651 ir_node *new_mem = transform_node(env, mem);
1652 ir_graph *irg = env->irg;
1653 dbg_info *dbgi = get_irn_dbg_info(node);
1654 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1655 ir_mode *mode = get_Load_mode(node);
1656 ir_node *lptr = new_ptr;
1659 ir_node *projs[pn_Load_max];
1660 ia32_am_flavour_t am_flav = ia32_am_B;
1662 ia32_collect_Projs(node, projs, pn_Load_max);
1665 check for special case: the loaded value might not be used (optimized, volatile, ...)
1666 we add a Proj + Keep for volatile loads and ignore all other cases
1668 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1669 /* add a result proj and a Keep to produce a pseudo use */
1670 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1671 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1674 /* address might be a constant (symconst or absolute address) */
1675 if (is_ia32_Const(new_ptr)) {
1680 if (mode_is_float(mode)) {
1682 if (USE_SSE2(env->cg)) {
1683 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1685 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1688 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1691 /* base is a constant address */
1693 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1694 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1695 am_flav = ia32_am_N;
1697 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1698 long offs = get_tarval_long(tv);
1700 add_ia32_am_offs_int(new_op, offs);
1701 am_flav = ia32_am_O;
1705 set_ia32_am_support(new_op, ia32_am_Source);
1706 set_ia32_op_type(new_op, ia32_AddrModeS);
1707 set_ia32_am_flavour(new_op, am_flav);
1708 set_ia32_ls_mode(new_op, mode);
1710 /* make sure we are scheduled behind the initial IncSP/Barrier
1711 * to avoid spills being placed before it
1713 if (block == get_irg_start_block(irg)) {
1714 add_irn_dep(new_op, get_irg_frame(irg));
1717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1725 * Transforms a Store.
1727 * @param env The transformation environment
1728 * @return the created ia32 Store node
1730 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1731 ir_node *block = transform_node(env, get_nodes_block(node));
1732 ir_node *ptr = get_Store_ptr(node);
1733 ir_node *new_ptr = transform_node(env, ptr);
1734 ir_node *val = get_Store_value(node);
1735 ir_node *new_val = transform_node(env, val);
1736 ir_node *mem = get_Store_mem(node);
1737 ir_node *new_mem = transform_node(env, mem);
1738 ir_graph *irg = env->irg;
1739 dbg_info *dbgi = get_irn_dbg_info(node);
1740 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1741 ir_node *sptr = new_ptr;
1742 ir_mode *mode = get_irn_mode(val);
1743 ir_node *sval = new_val;
1746 ia32_am_flavour_t am_flav = ia32_am_B;
1748 if (is_ia32_Const(new_val)) {
1749 assert(!mode_is_float(mode));
1753 /* address might be a constant (symconst or absolute address) */
1754 if (is_ia32_Const(new_ptr)) {
1759 if (mode_is_float(mode)) {
1761 if (USE_SSE2(env->cg)) {
1762 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1764 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1766 } else if (get_mode_size_bits(mode) == 8) {
1767 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1769 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1772 /* stored const is an immediate value */
1773 if (is_ia32_Const(new_val)) {
1774 assert(!mode_is_float(mode));
1775 copy_ia32_Immop_attr(new_op, new_val);
1778 /* base is an constant address */
1780 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1781 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1782 am_flav = ia32_am_N;
1784 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1785 long offs = get_tarval_long(tv);
1787 add_ia32_am_offs_int(new_op, offs);
1788 am_flav = ia32_am_O;
1792 set_ia32_am_support(new_op, ia32_am_Dest);
1793 set_ia32_op_type(new_op, ia32_AddrModeD);
1794 set_ia32_am_flavour(new_op, am_flav);
1795 set_ia32_ls_mode(new_op, mode);
1797 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1805 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1807 * @param env The transformation environment
1808 * @return The transformed node.
1810 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1811 ir_node *block = transform_node(env, get_nodes_block(node));
1812 ir_graph *irg = env->irg;
1813 dbg_info *dbgi = get_irn_dbg_info(node);
1814 ir_node *sel = get_Cond_selector(node);
1815 ir_mode *sel_mode = get_irn_mode(sel);
1816 ir_node *res = NULL;
1817 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1818 ir_node *cnst, *expr;
1820 if (is_Proj(sel) && sel_mode == mode_b) {
1821 ir_node *pred = get_Proj_pred(sel);
1822 ir_node *cmp_a = get_Cmp_left(pred);
1823 ir_node *new_cmp_a = transform_node(env, cmp_a);
1824 ir_node *cmp_b = get_Cmp_right(pred);
1825 ir_node *new_cmp_b = transform_node(env, cmp_b);
1826 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1827 ir_node *nomem = new_NoMem();
1829 int pnc = get_Proj_proj(sel);
1830 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1831 pnc |= ia32_pn_Cmp_Unsigned;
1834 /* check if we can use a CondJmp with immediate */
1835 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1836 expr = get_expr_op(new_cmp_a, new_cmp_b);
1838 if (cnst != NULL && expr != NULL) {
1839 /* immop has to be the right operand, we might need to flip pnc */
1840 if(cnst != new_cmp_b) {
1841 pnc = get_inversed_pnc(pnc);
1844 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1845 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1846 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1848 /* a Cmp A =/!= 0 */
1849 ir_node *op1 = expr;
1850 ir_node *op2 = expr;
1853 /* check, if expr is an only once used And operation */
1854 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1855 op1 = get_irn_n(expr, 2);
1856 op2 = get_irn_n(expr, 3);
1858 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1860 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1861 set_ia32_pncode(res, pnc);
1864 copy_ia32_Immop_attr(res, expr);
1867 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1872 if (mode_is_float(cmp_mode)) {
1874 if (USE_SSE2(env->cg)) {
1875 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1876 set_ia32_ls_mode(res, cmp_mode);
1882 assert(get_mode_size_bits(cmp_mode) == 32);
1883 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1885 copy_ia32_Immop_attr(res, cnst);
1888 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1890 if (mode_is_float(cmp_mode)) {
1892 if (USE_SSE2(env->cg)) {
1893 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1894 set_ia32_ls_mode(res, cmp_mode);
1897 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1898 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1899 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1903 assert(get_mode_size_bits(cmp_mode) == 32);
1904 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1905 set_ia32_commutative(res);
1909 set_ia32_pncode(res, pnc);
1910 // Matze: disabled for now, because the default collect_spills_walker
1911 // is not able to detect the mode of the spilled value
1912 // moreover, the lea optimize phase freely exchanges left/right
1913 // without updating the pnc
1914 //set_ia32_am_support(res, ia32_am_Source);
1917 /* determine the smallest switch case value */
1918 ir_node *new_sel = transform_node(env, sel);
1919 int switch_min = INT_MAX;
1920 const ir_edge_t *edge;
1922 foreach_out_edge(node, edge) {
1923 int pn = get_Proj_proj(get_edge_src_irn(edge));
1924 switch_min = pn < switch_min ? pn : switch_min;
1928 /* if smallest switch case is not 0 we need an additional sub */
1929 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1930 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1931 add_ia32_am_offs_int(res, -switch_min);
1932 set_ia32_am_flavour(res, ia32_am_OB);
1933 set_ia32_am_support(res, ia32_am_Source);
1934 set_ia32_op_type(res, ia32_AddrModeS);
1937 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1938 set_ia32_pncode(res, get_Cond_defaultProj(node));
1941 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1948 * Transforms a CopyB node.
1950 * @param env The transformation environment
1951 * @return The transformed node.
1953 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1954 ir_node *block = transform_node(env, get_nodes_block(node));
1955 ir_node *src = get_CopyB_src(node);
1956 ir_node *new_src = transform_node(env, src);
1957 ir_node *dst = get_CopyB_dst(node);
1958 ir_node *new_dst = transform_node(env, dst);
1959 ir_node *mem = get_CopyB_mem(node);
1960 ir_node *new_mem = transform_node(env, mem);
1961 ir_node *res = NULL;
1962 ir_graph *irg = env->irg;
1963 dbg_info *dbgi = get_irn_dbg_info(node);
1964 int size = get_type_size_bytes(get_CopyB_type(node));
1965 ir_mode *dst_mode = get_irn_mode(dst);
1966 ir_mode *src_mode = get_irn_mode(src);
1970 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1971 /* then we need the size explicitly in ECX. */
1972 if (size >= 32 * 4) {
1973 rem = size & 0x3; /* size % 4 */
1976 res = new_rd_ia32_Const(dbgi, irg, block);
1977 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1978 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1980 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1981 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1983 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1984 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1985 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1986 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1987 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1990 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1991 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1993 /* ok: now attach Proj's because movsd will destroy esi and edi */
1994 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1995 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1996 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1999 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2007 * Transforms a Mux node into CMov.
2009 * @param env The transformation environment
2010 * @return The transformed node.
2012 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
2013 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
2014 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2016 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2022 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2023 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2024 ir_node *psi_default);
2027 * Transforms a Psi node into CMov.
2029 * @param env The transformation environment
2030 * @return The transformed node.
2032 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2033 ir_node *block = transform_node(env, get_nodes_block(node));
2034 ir_node *psi_true = get_Psi_val(node, 0);
2035 ir_node *new_psi_true = transform_node(env, psi_true);
2036 ir_node *psi_default = get_Psi_default(node);
2037 ir_node *new_psi_default = transform_node(env, psi_default);
2038 ia32_code_gen_t *cg = env->cg;
2039 ir_graph *irg = env->irg;
2040 dbg_info *dbgi = get_irn_dbg_info(node);
2041 ir_mode *mode = get_irn_mode(node);
2042 ir_node *cmp_proj = get_Mux_sel(node);
2043 ir_node *noreg = ia32_new_NoReg_gp(cg);
2044 ir_node *nomem = new_rd_NoMem(irg);
2045 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2046 ir_node *new_cmp_a, *new_cmp_b;
2050 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2052 cmp = get_Proj_pred(cmp_proj);
2053 cmp_a = get_Cmp_left(cmp);
2054 cmp_b = get_Cmp_right(cmp);
2055 cmp_mode = get_irn_mode(cmp_a);
2056 new_cmp_a = transform_node(env, cmp_a);
2057 new_cmp_b = transform_node(env, cmp_b);
2059 pnc = get_Proj_proj(cmp_proj);
2060 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2061 pnc |= ia32_pn_Cmp_Unsigned;
2064 if (mode_is_float(mode)) {
2065 /* floating point psi */
2068 /* 1st case: compare operands are float too */
2070 /* psi(cmp(a, b), t, f) can be done as: */
2071 /* tmp = cmp a, b */
2072 /* tmp2 = t and tmp */
2073 /* tmp3 = f and not tmp */
2074 /* res = tmp2 or tmp3 */
2076 /* in case the compare operands are int, we move them into xmm register */
2077 if (! mode_is_float(get_irn_mode(cmp_a))) {
2078 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2079 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2081 pnc |= 8; /* transform integer compare to fp compare */
2084 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2085 set_ia32_pncode(new_op, pnc);
2086 set_ia32_am_support(new_op, ia32_am_Source);
2087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2089 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2090 set_ia32_am_support(and1, ia32_am_None);
2091 set_ia32_commutative(and1);
2092 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2094 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2095 set_ia32_am_support(and2, ia32_am_None);
2096 set_ia32_commutative(and2);
2097 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2099 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2100 set_ia32_am_support(new_op, ia32_am_None);
2101 set_ia32_commutative(new_op);
2102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2106 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2107 set_ia32_pncode(new_op, pnc);
2108 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2113 construct_binop_func *set_func = NULL;
2114 cmov_func_t *cmov_func = NULL;
2116 if (mode_is_float(get_irn_mode(cmp_a))) {
2117 /* 1st case: compare operands are floats */
2122 set_func = new_rd_ia32_xCmpSet;
2123 cmov_func = new_rd_ia32_xCmpCMov;
2127 set_func = new_rd_ia32_vfCmpSet;
2128 cmov_func = new_rd_ia32_vfCmpCMov;
2131 pnc &= ~0x8; /* fp compare -> int compare */
2134 /* 2nd case: compare operand are integer too */
2135 set_func = new_rd_ia32_CmpSet;
2136 cmov_func = new_rd_ia32_CmpCMov;
2139 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2140 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2141 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2142 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2143 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2144 set_ia32_pncode(new_op, pnc);
2146 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2147 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2148 /* we invert condition and set default to 0 */
2149 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2150 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2153 /* otherwise: use CMOVcc */
2154 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2155 set_ia32_pncode(new_op, pnc);
2158 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2161 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2162 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2163 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2164 set_ia32_pncode(new_op, pnc);
2165 set_ia32_am_support(new_op, ia32_am_Source);
2167 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2168 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2169 /* we invert condition and set default to 0 */
2170 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2171 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2172 set_ia32_am_support(new_op, ia32_am_Source);
2175 /* otherwise: use CMOVcc */
2176 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2177 set_ia32_pncode(new_op, pnc);
2178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2188 * Following conversion rules apply:
2192 * 1) n bit -> m bit n > m (downscale)
2194 * 2) n bit -> m bit n == m (sign change)
2196 * 3) n bit -> m bit n < m (upscale)
2197 * a) source is signed: movsx
2198 * b) source is unsigned: and with lower bits sets
2202 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2206 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2210 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2211 * x87 is mode_E internally, conversions happen only at load and store
2212 * in non-strict semantic
2216 * Create a conversion from x87 state register to general purpose.
2218 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2219 ir_node *block = transform_node(env, get_nodes_block(node));
2220 ir_node *op = get_Conv_op(node);
2221 ir_node *new_op = transform_node(env, op);
2222 ia32_code_gen_t *cg = env->cg;
2223 ir_graph *irg = env->irg;
2224 dbg_info *dbgi = get_irn_dbg_info(node);
2225 ir_node *noreg = ia32_new_NoReg_gp(cg);
2226 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2227 ir_node *fist, *load;
2230 fist = new_rd_ia32_vfist(dbgi, irg, block,
2231 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2233 set_ia32_use_frame(fist);
2234 set_ia32_am_support(fist, ia32_am_Dest);
2235 set_ia32_op_type(fist, ia32_AddrModeD);
2236 set_ia32_am_flavour(fist, ia32_am_B);
2237 set_ia32_ls_mode(fist, mode_Iu);
2238 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2241 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2243 set_ia32_use_frame(load);
2244 set_ia32_am_support(load, ia32_am_Source);
2245 set_ia32_op_type(load, ia32_AddrModeS);
2246 set_ia32_am_flavour(load, ia32_am_B);
2247 set_ia32_ls_mode(load, mode_Iu);
2248 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2250 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2254 * Create a conversion from general purpose to x87 register
2256 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2257 ir_node *block = transform_node(env, get_nodes_block(node));
2258 ir_node *op = get_Conv_op(node);
2259 ir_node *new_op = transform_node(env, op);
2260 ir_graph *irg = env->irg;
2261 dbg_info *dbgi = get_irn_dbg_info(node);
2262 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2263 ir_node *nomem = new_NoMem();
2264 ir_node *fild, *store;
2267 /* first convert to 32 bit if necessary */
2268 src_bits = get_mode_size_bits(src_mode);
2269 if (src_bits == 8) {
2270 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2271 set_ia32_am_support(new_op, ia32_am_Source);
2272 set_ia32_ls_mode(new_op, src_mode);
2273 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2274 } else if (src_bits < 32) {
2275 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2276 set_ia32_am_support(new_op, ia32_am_Source);
2277 set_ia32_ls_mode(new_op, src_mode);
2278 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2282 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2284 set_ia32_use_frame(store);
2285 set_ia32_am_support(store, ia32_am_Dest);
2286 set_ia32_op_type(store, ia32_AddrModeD);
2287 set_ia32_am_flavour(store, ia32_am_OB);
2288 set_ia32_ls_mode(store, mode_Iu);
2291 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2293 set_ia32_use_frame(fild);
2294 set_ia32_am_support(fild, ia32_am_Source);
2295 set_ia32_op_type(fild, ia32_AddrModeS);
2296 set_ia32_am_flavour(fild, ia32_am_OB);
2297 set_ia32_ls_mode(fild, mode_Iu);
2299 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2303 * Transforms a Conv node.
2305 * @param env The transformation environment
2306 * @return The created ia32 Conv node
2308 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2309 ir_node *block = transform_node(env, get_nodes_block(node));
2310 ir_node *op = get_Conv_op(node);
2311 ir_node *new_op = transform_node(env, op);
2312 ir_graph *irg = env->irg;
2313 dbg_info *dbgi = get_irn_dbg_info(node);
2314 ir_mode *src_mode = get_irn_mode(op);
2315 ir_mode *tgt_mode = get_irn_mode(node);
2316 int src_bits = get_mode_size_bits(src_mode);
2317 int tgt_bits = get_mode_size_bits(tgt_mode);
2318 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2319 ir_node *nomem = new_rd_NoMem(irg);
2322 if (src_mode == tgt_mode) {
2323 if (get_Conv_strict(node)) {
2324 if (USE_SSE2(env->cg)) {
2325 /* when we are in SSE mode, we can kill all strict no-op conversion */
2329 /* this should be optimized already, but who knows... */
2330 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2331 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2336 if (mode_is_float(src_mode)) {
2337 /* we convert from float ... */
2338 if (mode_is_float(tgt_mode)) {
2340 if (USE_SSE2(env->cg)) {
2341 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2342 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2343 set_ia32_ls_mode(res, tgt_mode);
2345 // Matze: TODO what about strict convs?
2346 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2347 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2352 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2353 if (USE_SSE2(env->cg)) {
2354 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2355 set_ia32_ls_mode(res, src_mode);
2357 return gen_x87_fp_to_gp(env, node);
2361 /* we convert from int ... */
2362 if (mode_is_float(tgt_mode)) {
2365 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2366 if (USE_SSE2(env->cg)) {
2367 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2368 set_ia32_ls_mode(res, tgt_mode);
2369 if(src_bits == 32) {
2370 set_ia32_am_support(res, ia32_am_Source);
2373 return gen_x87_gp_to_fp(env, node, src_mode);
2377 ir_mode *smaller_mode;
2380 if (src_bits == tgt_bits) {
2381 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2385 if (src_bits < tgt_bits) {
2386 smaller_mode = src_mode;
2387 smaller_bits = src_bits;
2389 smaller_mode = tgt_mode;
2390 smaller_bits = tgt_bits;
2394 The following is not correct, we can't change the mode,
2395 maybe others are using the load too
2396 better move this to a separate phase!
2400 if(is_Proj(new_op)) {
2401 /* load operations do already sign/zero extend, so we have
2402 * nothing left to do */
2403 ir_node *pred = get_Proj_pred(new_op);
2404 if(is_ia32_Load(pred)) {
2405 set_ia32_ls_mode(pred, smaller_mode);
2411 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2412 if (smaller_bits == 8) {
2413 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2414 set_ia32_ls_mode(res, smaller_mode);
2416 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2417 set_ia32_ls_mode(res, smaller_mode);
2419 set_ia32_am_support(res, ia32_am_Source);
2423 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2430 /********************************************
2433 * | |__ ___ _ __ ___ __| | ___ ___
2434 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2435 * | |_) | __/ | | | (_) | (_| | __/\__ \
2436 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2438 ********************************************/
2440 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2441 ir_node *block = transform_node(env, get_nodes_block(node));
2442 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2443 ir_node *new_ptr = transform_node(env, ptr);
2444 ir_node *new_op = NULL;
2445 ir_graph *irg = env->irg;
2446 dbg_info *dbgi = get_irn_dbg_info(node);
2447 ir_node *nomem = new_rd_NoMem(env->irg);
2448 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2449 ir_mode *load_mode = get_irn_mode(node);
2450 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2454 if (mode_is_float(load_mode)) {
2456 if (USE_SSE2(env->cg)) {
2457 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2458 pn_res = pn_ia32_xLoad_res;
2459 proj_mode = mode_xmm;
2461 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2462 pn_res = pn_ia32_vfld_res;
2463 proj_mode = mode_vfp;
2466 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2467 proj_mode = mode_Iu;
2468 pn_res = pn_ia32_Load_res;
2471 set_ia32_frame_ent(new_op, ent);
2472 set_ia32_use_frame(new_op);
2474 set_ia32_am_support(new_op, ia32_am_Source);
2475 set_ia32_op_type(new_op, ia32_AddrModeS);
2476 set_ia32_am_flavour(new_op, ia32_am_B);
2477 set_ia32_ls_mode(new_op, load_mode);
2478 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2480 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2482 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2486 * Transforms a FrameAddr into an ia32 Add.
2488 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2489 ir_node *block = transform_node(env, get_nodes_block(node));
2490 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2491 ir_node *new_op = transform_node(env, op);
2492 ir_graph *irg = env->irg;
2493 dbg_info *dbgi = get_irn_dbg_info(node);
2494 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2497 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2498 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2499 set_ia32_am_support(res, ia32_am_Full);
2500 set_ia32_use_frame(res);
2501 set_ia32_am_flavour(res, ia32_am_OB);
2503 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2509 * Transforms a FrameLoad into an ia32 Load.
2511 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2512 ir_node *block = transform_node(env, get_nodes_block(node));
2513 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2514 ir_node *new_mem = transform_node(env, mem);
2515 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2516 ir_node *new_ptr = transform_node(env, ptr);
2517 ir_node *new_op = NULL;
2518 ir_graph *irg = env->irg;
2519 dbg_info *dbgi = get_irn_dbg_info(node);
2520 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2521 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2522 ir_mode *mode = get_type_mode(get_entity_type(ent));
2523 ir_node *projs[pn_Load_max];
2525 ia32_collect_Projs(node, projs, pn_Load_max);
2527 if (mode_is_float(mode)) {
2529 if (USE_SSE2(env->cg)) {
2530 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2533 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2537 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2540 set_ia32_frame_ent(new_op, ent);
2541 set_ia32_use_frame(new_op);
2543 set_ia32_am_support(new_op, ia32_am_Source);
2544 set_ia32_op_type(new_op, ia32_AddrModeS);
2545 set_ia32_am_flavour(new_op, ia32_am_B);
2546 set_ia32_ls_mode(new_op, mode);
2548 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2555 * Transforms a FrameStore into an ia32 Store.
2557 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2558 ir_node *block = transform_node(env, get_nodes_block(node));
2559 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2560 ir_node *new_mem = transform_node(env, mem);
2561 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2562 ir_node *new_ptr = transform_node(env, ptr);
2563 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2564 ir_node *new_val = transform_node(env, val);
2565 ir_node *new_op = NULL;
2566 ir_graph *irg = env->irg;
2567 dbg_info *dbgi = get_irn_dbg_info(node);
2568 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2569 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2570 ir_mode *mode = get_irn_mode(val);
2572 if (mode_is_float(mode)) {
2574 if (USE_SSE2(env->cg)) {
2575 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2577 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2579 } else if (get_mode_size_bits(mode) == 8) {
2580 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2582 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2585 set_ia32_frame_ent(new_op, ent);
2586 set_ia32_use_frame(new_op);
2588 set_ia32_am_support(new_op, ia32_am_Dest);
2589 set_ia32_op_type(new_op, ia32_AddrModeD);
2590 set_ia32_am_flavour(new_op, ia32_am_B);
2591 set_ia32_ls_mode(new_op, mode);
2593 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2599 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2601 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2602 ir_graph *irg = env->irg;
2603 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2604 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2605 ir_entity *ent = get_irg_entity(irg);
2606 ir_type *tp = get_entity_type(ent);
2611 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2612 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2614 int pn_ret_val, pn_ret_mem, arity, i;
2616 assert(ret_val != NULL);
2617 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2618 return duplicate_node(env, node);
2621 res_type = get_method_res_type(tp, 0);
2623 if (! is_Primitive_type(res_type)) {
2624 return duplicate_node(env, node);
2627 mode = get_type_mode(res_type);
2628 if (! mode_is_float(mode)) {
2629 return duplicate_node(env, node);
2632 assert(get_method_n_ress(tp) == 1);
2634 pn_ret_val = get_Proj_proj(ret_val);
2635 pn_ret_mem = get_Proj_proj(ret_mem);
2637 /* get the Barrier */
2638 barrier = get_Proj_pred(ret_val);
2640 /* get result input of the Barrier */
2641 ret_val = get_irn_n(barrier, pn_ret_val);
2642 new_ret_val = transform_node(env, ret_val);
2644 /* get memory input of the Barrier */
2645 ret_mem = get_irn_n(barrier, pn_ret_mem);
2646 new_ret_mem = transform_node(env, ret_mem);
2648 frame = get_irg_frame(irg);
2650 dbgi = get_irn_dbg_info(barrier);
2651 block = transform_node(env, get_nodes_block(barrier));
2653 /* store xmm0 onto stack */
2654 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2655 set_ia32_ls_mode(sse_store, mode);
2656 set_ia32_op_type(sse_store, ia32_AddrModeD);
2657 set_ia32_use_frame(sse_store);
2658 set_ia32_am_flavour(sse_store, ia32_am_B);
2659 set_ia32_am_support(sse_store, ia32_am_Dest);
2662 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2663 set_ia32_ls_mode(fld, mode);
2664 set_ia32_op_type(fld, ia32_AddrModeS);
2665 set_ia32_use_frame(fld);
2666 set_ia32_am_flavour(fld, ia32_am_B);
2667 set_ia32_am_support(fld, ia32_am_Source);
2669 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2670 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2671 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2673 /* create a new barrier */
2674 arity = get_irn_arity(barrier);
2675 in = alloca(arity * sizeof(in[0]));
2676 for (i = 0; i < arity; ++i) {
2679 if (i == pn_ret_val) {
2681 } else if (i == pn_ret_mem) {
2684 ir_node *in = get_irn_n(barrier, i);
2685 new_in = transform_node(env, in);
2690 new_barrier = new_ir_node(dbgi, irg, block,
2691 get_irn_op(barrier), get_irn_mode(barrier),
2693 copy_node_attr(barrier, new_barrier);
2694 duplicate_deps(env, barrier, new_barrier);
2695 set_new_node(barrier, new_barrier);
2696 mark_irn_visited(barrier);
2698 /* transform normally */
2699 return duplicate_node(env, node);
2703 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2705 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2706 ir_node *block = transform_node(env, get_nodes_block(node));
2707 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2708 ir_node *new_sz = transform_node(env, sz);
2709 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2710 ir_node *new_sp = transform_node(env, sp);
2711 ir_graph *irg = env->irg;
2712 dbg_info *dbgi = get_irn_dbg_info(node);
2713 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2714 ir_node *nomem = new_NoMem();
2717 /* ia32 stack grows in reverse direction, make a SubSP */
2718 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2719 set_ia32_am_support(new_op, ia32_am_Source);
2720 fold_immediate(env, new_op, 2, 3);
2722 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2728 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2730 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2731 ir_node *block = transform_node(env, get_nodes_block(node));
2732 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2733 ir_node *new_sz = transform_node(env, sz);
2734 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2735 ir_node *new_sp = transform_node(env, sp);
2736 ir_graph *irg = env->irg;
2737 dbg_info *dbgi = get_irn_dbg_info(node);
2738 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2739 ir_node *nomem = new_NoMem();
2742 /* ia32 stack grows in reverse direction, make an AddSP */
2743 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2744 set_ia32_am_support(new_op, ia32_am_Source);
2745 fold_immediate(env, new_op, 2, 3);
2747 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2753 * This function just sets the register for the Unknown node
2754 * as this is not done during register allocation because Unknown
2755 * is an "ignore" node.
2757 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2758 ir_mode *mode = get_irn_mode(node);
2760 if (mode_is_float(mode)) {
2761 if (USE_SSE2(env->cg))
2762 return ia32_new_Unknown_xmm(env->cg);
2764 return ia32_new_Unknown_vfp(env->cg);
2765 } else if (mode_needs_gp_reg(mode)) {
2766 return ia32_new_Unknown_gp(env->cg);
2768 assert(0 && "unsupported Unknown-Mode");
2775 * Change some phi modes
2777 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2778 ir_node *block = transform_node(env, get_nodes_block(node));
2779 ir_graph *irg = env->irg;
2780 dbg_info *dbgi = get_irn_dbg_info(node);
2781 ir_mode *mode = get_irn_mode(node);
2785 if(mode_needs_gp_reg(mode)) {
2786 /* we shouldn't have any 64bit stuff around anymore */
2787 assert(get_mode_size_bits(mode) <= 32);
2788 /* all integer operations are on 32bit registers now */
2790 } else if(mode_is_float(mode)) {
2791 assert(mode == mode_D || mode == mode_F);
2792 if (USE_SSE2(env->cg)) {
2799 /* phi nodes allow loops, so we use the old arguments for now
2800 * and fix this later */
2801 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
2802 copy_node_attr(node, phi);
2803 duplicate_deps(env, node, phi);
2805 set_new_node(node, phi);
2807 /* put the preds in the worklist */
2808 arity = get_irn_arity(node);
2809 for (i = 0; i < arity; ++i) {
2810 ir_node *pred = get_irn_n(node, i);
2811 pdeq_putr(env->worklist, pred);
2817 /**********************************************************************
2820 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2821 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2822 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2823 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2825 **********************************************************************/
2827 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2829 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2832 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2833 ir_node *val, ir_node *mem);
2836 * Transforms a lowered Load into a "real" one.
2838 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2839 ir_node *block = transform_node(env, get_nodes_block(node));
2840 ir_node *ptr = get_irn_n(node, 0);
2841 ir_node *new_ptr = transform_node(env, ptr);
2842 ir_node *mem = get_irn_n(node, 1);
2843 ir_node *new_mem = transform_node(env, mem);
2844 ir_graph *irg = env->irg;
2845 dbg_info *dbgi = get_irn_dbg_info(node);
2846 ir_mode *mode = get_ia32_ls_mode(node);
2847 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2851 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2852 lowering we have x87 nodes, so we need to enforce simulation.
2854 if (mode_is_float(mode)) {
2856 if (fp_unit == fp_x87)
2860 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2862 set_ia32_am_support(new_op, ia32_am_Source);
2863 set_ia32_op_type(new_op, ia32_AddrModeS);
2864 set_ia32_am_flavour(new_op, ia32_am_OB);
2865 set_ia32_am_offs_int(new_op, 0);
2866 set_ia32_am_scale(new_op, 1);
2867 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2868 if (is_ia32_am_sc_sign(node))
2869 set_ia32_am_sc_sign(new_op);
2870 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2871 if (is_ia32_use_frame(node)) {
2872 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2873 set_ia32_use_frame(new_op);
2876 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2882 * Transforms a lowered Store into a "real" one.
2884 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2885 ir_node *block = transform_node(env, get_nodes_block(node));
2886 ir_node *ptr = get_irn_n(node, 0);
2887 ir_node *new_ptr = transform_node(env, ptr);
2888 ir_node *val = get_irn_n(node, 1);
2889 ir_node *new_val = transform_node(env, val);
2890 ir_node *mem = get_irn_n(node, 2);
2891 ir_node *new_mem = transform_node(env, mem);
2892 ir_graph *irg = env->irg;
2893 dbg_info *dbgi = get_irn_dbg_info(node);
2894 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2895 ir_mode *mode = get_ia32_ls_mode(node);
2898 ia32_am_flavour_t am_flav = ia32_B;
2901 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2902 lowering we have x87 nodes, so we need to enforce simulation.
2904 if (mode_is_float(mode)) {
2906 if (fp_unit == fp_x87)
2910 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2912 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2914 add_ia32_am_offs_int(new_op, am_offs);
2917 set_ia32_am_support(new_op, ia32_am_Dest);
2918 set_ia32_op_type(new_op, ia32_AddrModeD);
2919 set_ia32_am_flavour(new_op, am_flav);
2920 set_ia32_ls_mode(new_op, mode);
2921 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2922 set_ia32_use_frame(new_op);
2924 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2931 * Transforms an ia32_l_XXX into a "real" XXX node
2933 * @param env The transformation environment
2934 * @return the created ia32 XXX node
2936 #define GEN_LOWERED_OP(op) \
2937 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2938 ir_mode *mode = get_irn_mode(node); \
2939 if (mode_is_float(mode)) \
2941 return gen_binop(env, node, get_binop_left(node), \
2942 get_binop_right(node), new_rd_ia32_##op); \
2945 #define GEN_LOWERED_x87_OP(op) \
2946 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2948 FORCE_x87(env->cg); \
2949 new_op = gen_binop_float(env, node, get_binop_left(node), \
2950 get_binop_right(node), new_rd_ia32_##op); \
2954 #define GEN_LOWERED_UNOP(op) \
2955 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2956 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2959 #define GEN_LOWERED_SHIFT_OP(op) \
2960 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2961 return gen_shift_binop(env, node, get_binop_left(node), \
2962 get_binop_right(node), new_rd_ia32_##op); \
2965 #define GEN_LOWERED_LOAD(op, fp_unit) \
2966 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2967 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2970 #define GEN_LOWERED_STORE(op, fp_unit) \
2971 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2972 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2979 GEN_LOWERED_OP(IMul)
2981 GEN_LOWERED_x87_OP(vfprem)
2982 GEN_LOWERED_x87_OP(vfmul)
2983 GEN_LOWERED_x87_OP(vfsub)
2985 GEN_LOWERED_UNOP(Neg)
2987 GEN_LOWERED_LOAD(vfild, fp_x87)
2988 GEN_LOWERED_LOAD(Load, fp_none)
2989 /*GEN_LOWERED_STORE(vfist, fp_x87)
2992 GEN_LOWERED_STORE(Store, fp_none)
2994 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2995 ir_node *block = transform_node(env, get_nodes_block(node));
2996 ir_node *left = get_binop_left(node);
2997 ir_node *new_left = transform_node(env, left);
2998 ir_node *right = get_binop_right(node);
2999 ir_node *new_right = transform_node(env, right);
3000 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3001 ir_graph *irg = env->irg;
3002 dbg_info *dbgi = get_irn_dbg_info(node);
3005 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3006 clear_ia32_commutative(vfdiv);
3007 set_ia32_am_support(vfdiv, ia32_am_Source);
3008 fold_immediate(env, vfdiv, 2, 3);
3010 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3018 * Transforms a l_MulS into a "real" MulS node.
3020 * @param env The transformation environment
3021 * @return the created ia32 Mul node
3023 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3024 ir_node *block = transform_node(env, get_nodes_block(node));
3025 ir_node *left = get_binop_left(node);
3026 ir_node *new_left = transform_node(env, left);
3027 ir_node *right = get_binop_right(node);
3028 ir_node *new_right = transform_node(env, right);
3029 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3030 ir_graph *irg = env->irg;
3031 dbg_info *dbgi = get_irn_dbg_info(node);
3034 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3035 /* and then skip the result Proj, because all needed Projs are already there. */
3036 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3037 clear_ia32_commutative(muls);
3038 set_ia32_am_support(muls, ia32_am_Source);
3039 fold_immediate(env, muls, 2, 3);
3041 /* check if EAX and EDX proj exist, add missing one */
3042 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3043 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3044 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3046 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3051 GEN_LOWERED_SHIFT_OP(Shl)
3052 GEN_LOWERED_SHIFT_OP(Shr)
3053 GEN_LOWERED_SHIFT_OP(Sar)
3056 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3057 * op1 - target to be shifted
3058 * op2 - contains bits to be shifted into target
3060 * Only op3 can be an immediate.
3062 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3063 ir_node *op1, ir_node *op2,
3066 ir_node *block = transform_node(env, get_nodes_block(node));
3067 ir_node *new_op1 = transform_node(env, op1);
3068 ir_node *new_op2 = transform_node(env, op2);
3069 ir_node *new_count = transform_node(env, count);
3070 ir_node *new_op = NULL;
3071 ir_graph *irg = env->irg;
3072 dbg_info *dbgi = get_irn_dbg_info(node);
3073 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3074 ir_node *nomem = new_NoMem();
3078 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3080 /* Check if immediate optimization is on and */
3081 /* if it's an operation with immediate. */
3082 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3084 /* Limit imm_op within range imm8 */
3086 tv = get_ia32_Immop_tarval(imm_op);
3089 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3090 set_ia32_Immop_tarval(imm_op, tv);
3097 /* integer operations */
3099 /* This is ShiftD with const */
3100 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3102 if (is_ia32_l_ShlD(node))
3103 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3104 new_op1, new_op2, noreg, nomem);
3106 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3107 new_op1, new_op2, noreg, nomem);
3108 copy_ia32_Immop_attr(new_op, imm_op);
3111 /* This is a normal ShiftD */
3112 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3113 if (is_ia32_l_ShlD(node))
3114 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3115 new_op1, new_op2, new_count, nomem);
3117 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3118 new_op1, new_op2, new_count, nomem);
3121 /* set AM support */
3122 // Matze: node has unsupported format (6inputs)
3123 //set_ia32_am_support(new_op, ia32_am_Dest);
3125 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3127 set_ia32_emit_cl(new_op);
3132 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3133 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3134 get_irn_n(node, 1), get_irn_n(node, 2));
3137 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3138 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3139 get_irn_n(node, 1), get_irn_n(node, 2));
3143 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3145 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3146 ir_node *block = transform_node(env, get_nodes_block(node));
3147 ir_node *val = get_irn_n(node, 1);
3148 ir_node *new_val = transform_node(env, val);
3149 ia32_code_gen_t *cg = env->cg;
3150 ir_node *res = NULL;
3151 ir_graph *irg = env->irg;
3153 ir_node *noreg, *new_ptr, *new_mem;
3160 mem = get_irn_n(node, 2);
3161 new_mem = transform_node(env, mem);
3162 ptr = get_irn_n(node, 0);
3163 new_ptr = transform_node(env, ptr);
3164 noreg = ia32_new_NoReg_gp(cg);
3165 dbgi = get_irn_dbg_info(node);
3167 /* Store x87 -> MEM */
3168 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3169 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3170 set_ia32_use_frame(res);
3171 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3172 set_ia32_am_support(res, ia32_am_Dest);
3173 set_ia32_am_flavour(res, ia32_B);
3174 set_ia32_op_type(res, ia32_AddrModeD);
3176 /* Load MEM -> SSE */
3177 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3178 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3179 set_ia32_use_frame(res);
3180 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3181 set_ia32_am_support(res, ia32_am_Source);
3182 set_ia32_am_flavour(res, ia32_B);
3183 set_ia32_op_type(res, ia32_AddrModeS);
3184 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3190 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3192 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3193 ir_node *block = transform_node(env, get_nodes_block(node));
3194 ir_node *val = get_irn_n(node, 1);
3195 ir_node *new_val = transform_node(env, val);
3196 ia32_code_gen_t *cg = env->cg;
3197 ir_graph *irg = env->irg;
3198 ir_node *res = NULL;
3199 ir_entity *fent = get_ia32_frame_ent(node);
3200 ir_mode *lsmode = get_ia32_ls_mode(node);
3202 ir_node *noreg, *new_ptr, *new_mem;
3206 if (! USE_SSE2(cg)) {
3207 /* SSE unit is not used -> skip this node. */
3211 ptr = get_irn_n(node, 0);
3212 new_ptr = transform_node(env, ptr);
3213 mem = get_irn_n(node, 2);
3214 new_mem = transform_node(env, mem);
3215 noreg = ia32_new_NoReg_gp(cg);
3216 dbgi = get_irn_dbg_info(node);
3218 /* Store SSE -> MEM */
3219 if (is_ia32_xLoad(skip_Proj(new_val))) {
3220 ir_node *ld = skip_Proj(new_val);
3222 /* we can vfld the value directly into the fpu */
3223 fent = get_ia32_frame_ent(ld);
3224 ptr = get_irn_n(ld, 0);
3225 offs = get_ia32_am_offs_int(ld);
3227 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3228 set_ia32_frame_ent(res, fent);
3229 set_ia32_use_frame(res);
3230 set_ia32_ls_mode(res, lsmode);
3231 set_ia32_am_support(res, ia32_am_Dest);
3232 set_ia32_am_flavour(res, ia32_B);
3233 set_ia32_op_type(res, ia32_AddrModeD);
3237 /* Load MEM -> x87 */
3238 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3239 set_ia32_frame_ent(res, fent);
3240 set_ia32_use_frame(res);
3241 set_ia32_ls_mode(res, lsmode);
3242 add_ia32_am_offs_int(res, offs);
3243 set_ia32_am_support(res, ia32_am_Source);
3244 set_ia32_am_flavour(res, ia32_B);
3245 set_ia32_op_type(res, ia32_AddrModeS);
3246 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3251 /*********************************************************
3254 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3255 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3256 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3257 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3259 *********************************************************/
3262 * the BAD transformer.
3264 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3265 panic("No transform function for %+F available.\n", node);
3269 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3270 /* end has to be duplicated manually because we need a dynamic in array */
3271 ir_graph *irg = env->irg;
3272 dbg_info *dbgi = get_irn_dbg_info(node);
3273 ir_node *block = transform_node(env, get_nodes_block(node));
3277 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3278 copy_node_attr(node, new_end);
3279 duplicate_deps(env, node, new_end);
3281 set_irg_end(irg, new_end);
3282 set_new_node(new_end, new_end);
3284 /* transform preds */
3285 arity = get_irn_arity(node);
3286 for (i = 0; i < arity; ++i) {
3287 ir_node *in = get_irn_n(node, i);
3288 ir_node *new_in = transform_node(env, in);
3290 add_End_keepalive(new_end, new_in);
3296 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3297 ir_graph *irg = env->irg;
3298 dbg_info *dbgi = get_irn_dbg_info(node);
3299 ir_node *start_block = env->old_anchors[anchor_start_block];
3304 * We replace the ProjX from the start node with a jump,
3305 * so the startblock has no preds anymore now
3307 if (node == start_block) {
3308 return new_rd_Block(dbgi, irg, 0, NULL);
3311 /* we use the old blocks for now, because jumps allow cycles in the graph
3312 * we have to fix this later */
3313 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3314 get_irn_arity(node), get_irn_in(node) + 1);
3315 copy_node_attr(node, block);
3317 #ifdef DEBUG_libfirm
3318 block->node_nr = node->node_nr;
3320 set_new_node(node, block);
3322 /* put the preds in the worklist */
3323 arity = get_irn_arity(node);
3324 for (i = 0; i < arity; ++i) {
3325 ir_node *in = get_irn_n(node, i);
3326 pdeq_putr(env->worklist, in);
3332 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3333 ir_node *block = transform_node(env, get_nodes_block(node));
3334 ir_node *pred = get_Proj_pred(node);
3335 ir_node *new_pred = transform_node(env, pred);
3336 ir_graph *irg = env->irg;
3337 dbg_info *dbgi = get_irn_dbg_info(node);
3338 long proj = get_Proj_proj(node);
3340 if (proj == pn_be_AddSP_res) {
3341 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3342 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3344 } else if (proj == pn_be_AddSP_M) {
3345 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3349 return new_rd_Unknown(irg, get_irn_mode(node));
3352 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3353 ir_node *block = transform_node(env, get_nodes_block(node));
3354 ir_node *pred = get_Proj_pred(node);
3355 ir_node *new_pred = transform_node(env, pred);
3356 ir_graph *irg = env->irg;
3357 dbg_info *dbgi = get_irn_dbg_info(node);
3358 long proj = get_Proj_proj(node);
3360 if (proj == pn_be_SubSP_res) {
3361 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3362 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3364 } else if (proj == pn_be_SubSP_M) {
3365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3369 return new_rd_Unknown(irg, get_irn_mode(node));
3372 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3373 ir_node *block = transform_node(env, get_nodes_block(node));
3374 ir_node *pred = get_Proj_pred(node);
3375 ir_node *new_pred = transform_node(env, pred);
3376 ir_graph *irg = env->irg;
3377 dbg_info *dbgi = get_irn_dbg_info(node);
3378 long proj = get_Proj_proj(node);
3380 /* renumber the proj */
3381 if (is_ia32_Load(new_pred)) {
3382 if (proj == pn_Load_res) {
3383 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3384 } else if (proj == pn_Load_M) {
3385 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3387 } else if (is_ia32_xLoad(new_pred)) {
3388 if (proj == pn_Load_res) {
3389 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3390 } else if (proj == pn_Load_M) {
3391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3393 } else if (is_ia32_vfld(new_pred)) {
3394 if (proj == pn_Load_res) {
3395 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3396 } else if (proj == pn_Load_M) {
3397 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3402 return new_rd_Unknown(irg, get_irn_mode(node));
3405 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3406 ir_node *block = transform_node(env, get_nodes_block(node));
3407 ir_node *pred = get_Proj_pred(node);
3408 ir_node *new_pred = transform_node(env, pred);
3409 ir_graph *irg = env->irg;
3410 dbg_info *dbgi = get_irn_dbg_info(node);
3411 ir_mode *mode = get_irn_mode(node);
3412 long proj = get_Proj_proj(node);
3414 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3416 switch (get_irn_opcode(pred)) {
3420 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3422 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3430 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3432 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3440 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3441 case pn_DivMod_res_div:
3442 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3443 case pn_DivMod_res_mod:
3444 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3454 return new_rd_Unknown(irg, mode);
3457 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node) {
3458 ir_node *block = transform_node(env, get_nodes_block(node));
3459 ir_node *pred = get_Proj_pred(node);
3460 ir_node *new_pred = transform_node(env, pred);
3461 ir_graph *irg = env->irg;
3462 dbg_info *dbgi = get_irn_dbg_info(node);
3463 ir_mode *mode = get_irn_mode(node);
3464 long proj = get_Proj_proj(node);
3467 case pn_CopyB_M_regular:
3468 if (is_ia32_CopyB_i(new_pred)) {
3469 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3470 } else if (is_ia32_CopyB(new_pred)) {
3471 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3479 return new_rd_Unknown(irg, mode);
3482 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3483 ir_node *block = transform_node(env, get_nodes_block(node));
3484 ir_node *pred = get_Proj_pred(node);
3485 ir_node *new_pred = transform_node(env, pred);
3486 ir_graph *irg = env->irg;
3487 dbg_info *dbgi = get_irn_dbg_info(node);
3488 ir_mode *mode = get_irn_mode(node);
3489 long proj = get_Proj_proj(node);
3492 case pn_ia32_l_vfdiv_M:
3493 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3494 case pn_ia32_l_vfdiv_res:
3495 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3500 return new_rd_Unknown(irg, mode);
3503 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node) {
3504 ir_node *block = transform_node(env, get_nodes_block(node));
3505 ir_node *pred = get_Proj_pred(node);
3506 ir_node *new_pred = transform_node(env, pred);
3507 ir_graph *irg = env->irg;
3508 dbg_info *dbgi = get_irn_dbg_info(node);
3509 ir_mode *mode = get_irn_mode(node);
3510 long proj = get_Proj_proj(node);
3514 if (is_ia32_xDiv(new_pred)) {
3515 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3516 } else if (is_ia32_vfdiv(new_pred)) {
3517 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3521 if (is_ia32_xDiv(new_pred)) {
3522 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3523 } else if (is_ia32_vfdiv(new_pred)) {
3524 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3532 return new_rd_Unknown(irg, mode);
3535 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3536 ir_node *block = transform_node(env, get_nodes_block(node));
3537 ir_graph *irg = env->irg;
3538 dbg_info *dbgi = NULL;
3539 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3544 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3545 ir_node *block = transform_node(env, get_nodes_block(node));
3546 ir_node *call = get_Proj_pred(node);
3547 ir_node *new_call = transform_node(env, call);
3548 ir_graph *irg = env->irg;
3549 dbg_info *dbgi = get_irn_dbg_info(node);
3550 long proj = get_Proj_proj(node);
3551 ir_mode *mode = get_irn_mode(node);
3553 const arch_register_class_t *cls;
3555 /* The following is kinda tricky: If we're using SSE, then we have to
3556 * move the result value of the call in floating point registers to an
3557 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3558 * after the call, we have to make sure to correctly make the
3559 * MemProj and the result Proj use these 2 nodes
3561 if (proj == pn_be_Call_M_regular) {
3562 // get new node for result, are we doing the sse load/store hack?
3563 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3564 ir_node *call_res_new;
3565 ir_node *call_res_pred = NULL;
3567 if (call_res != NULL) {
3568 call_res_new = transform_node(env, call_res);
3569 call_res_pred = get_Proj_pred(call_res_new);
3572 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3573 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3575 assert(is_ia32_xLoad(call_res_pred));
3576 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3579 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env->cg)) {
3581 ir_node *frame = get_irg_frame(irg);
3582 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3584 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3586 const arch_register_class_t *cls;
3588 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3589 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3591 /* store st(0) onto stack */
3592 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3594 set_ia32_ls_mode(fstp, mode);
3595 set_ia32_op_type(fstp, ia32_AddrModeD);
3596 set_ia32_use_frame(fstp);
3597 set_ia32_am_flavour(fstp, ia32_am_B);
3598 set_ia32_am_support(fstp, ia32_am_Dest);
3600 /* load into SSE register */
3601 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3602 set_ia32_ls_mode(sse_load, mode);
3603 set_ia32_op_type(sse_load, ia32_AddrModeS);
3604 set_ia32_use_frame(sse_load);
3605 set_ia32_am_flavour(sse_load, ia32_am_B);
3606 set_ia32_am_support(sse_load, ia32_am_Source);
3608 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3610 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3612 /* get a Proj representing a caller save register */
3613 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3614 assert(is_Proj(p) && "Proj expected.");
3616 /* user of the the proj is the Keep */
3617 p = get_edge_src_irn(get_irn_out_edge_first(p));
3618 assert(be_is_Keep(p) && "Keep expected.");
3620 /* keep the result */
3621 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3622 keepin[0] = sse_load;
3623 be_new_Keep(cls, irg, block, 1, keepin);
3628 /* transform call modes */
3629 if (mode_is_data(mode)) {
3630 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3634 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3637 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3638 ir_graph *irg = env->irg;
3639 dbg_info *dbgi = get_irn_dbg_info(node);
3640 ir_node *pred = get_Proj_pred(node);
3641 long proj = get_Proj_proj(node);
3643 if (is_Store(pred) || be_is_FrameStore(pred)) {
3644 if (proj == pn_Store_M) {
3645 return transform_node(env, pred);
3648 return new_r_Bad(irg);
3650 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3651 return gen_Proj_Load(env, node);
3652 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3653 return gen_Proj_DivMod(env, node);
3654 } else if (is_CopyB(pred)) {
3655 return gen_Proj_CopyB(env, node);
3656 } else if (is_Quot(pred)) {
3657 return gen_Proj_Quot(env, node);
3658 } else if (is_ia32_l_vfdiv(pred)) {
3659 return gen_Proj_l_vfdiv(env, node);
3660 } else if (be_is_SubSP(pred)) {
3661 return gen_Proj_be_SubSP(env, node);
3662 } else if (be_is_AddSP(pred)) {
3663 return gen_Proj_be_AddSP(env, node);
3664 } else if (be_is_Call(pred)) {
3665 return gen_Proj_be_Call(env, node);
3666 } else if (get_irn_op(pred) == op_Start) {
3667 if (proj == pn_Start_X_initial_exec) {
3668 ir_node *block = get_nodes_block(pred);
3671 /* we exchange the ProjX with a jump */
3672 block = transform_node(env, block);
3673 jump = new_rd_Jmp(dbgi, irg, block);
3674 ir_fprintf(stderr, "created jump: %+F\n", jump);
3677 if (node == env->old_anchors[anchor_tls]) {
3678 return gen_Proj_tls(env, node);
3681 ir_node *new_pred = transform_node(env, pred);
3682 ir_node *block = transform_node(env, get_nodes_block(node));
3683 ir_mode *mode = get_irn_mode(node);
3684 if (mode_needs_gp_reg(mode)) {
3685 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3686 get_Proj_proj(node));
3687 #ifdef DEBUG_libfirm
3688 new_proj->node_nr = node->node_nr;
3694 return duplicate_node(env, node);
3698 * Enters all transform functions into the generic pointer
3700 static void register_transformers(void) {
3701 ir_op *op_Max, *op_Min, *op_Mulh;
3703 /* first clear the generic function pointer for all ops */
3704 clear_irp_opcodes_generic_func();
3706 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3707 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3746 /* transform ops from intrinsic lowering */
3766 /* GEN(ia32_l_vfist); TODO */
3768 GEN(ia32_l_X87toSSE);
3769 GEN(ia32_l_SSEtoX87);
3774 /* we should never see these nodes */
3789 /* handle generic backend nodes */
3799 /* set the register for all Unknown nodes */
3802 op_Max = get_op_Max();
3805 op_Min = get_op_Min();
3808 op_Mulh = get_op_Mulh();
3816 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3820 int deps = get_irn_deps(old_node);
3822 for (i = 0; i < deps; ++i) {
3823 ir_node *dep = get_irn_dep(old_node, i);
3824 ir_node *new_dep = transform_node(env, dep);
3826 add_irn_dep(new_node, new_dep);
3830 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3832 ir_node *block = transform_node(env, get_nodes_block(node));
3833 ir_graph *irg = env->irg;
3834 dbg_info *dbgi = get_irn_dbg_info(node);
3835 ir_mode *mode = get_irn_mode(node);
3836 ir_op *op = get_irn_op(node);
3840 arity = get_irn_arity(node);
3841 if (op->opar == oparity_dynamic) {
3842 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3843 for (i = 0; i < arity; ++i) {
3844 ir_node *in = get_irn_n(node, i);
3845 in = transform_node(env, in);
3846 add_irn_n(new_node, in);
3849 ir_node **ins = alloca(arity * sizeof(ins[0]));
3850 for (i = 0; i < arity; ++i) {
3851 ir_node *in = get_irn_n(node, i);
3852 ins[i] = transform_node(env, in);
3855 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3858 copy_node_attr(node, new_node);
3859 duplicate_deps(env, node, new_node);
3861 #ifdef DEBUG_libfirm
3862 new_node->node_nr = node->node_nr;
3869 * Calls transformation function for given node and marks it visited.
3871 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node) {
3873 ir_op *op = get_irn_op(node);
3875 if (irn_visited(node)) {
3876 assert(get_new_node(node) != NULL);
3877 return get_new_node(node);
3880 mark_irn_visited(node);
3881 DEBUG_ONLY(set_new_node(node, NULL));
3883 if (op->ops.generic) {
3884 transform_func *transform = (transform_func *)op->ops.generic;
3886 new_node = (*transform)(env, node);
3887 assert(new_node != NULL);
3889 new_node = duplicate_node(env, node);
3891 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
3893 set_new_node(node, new_node);
3894 mark_irn_visited(new_node);
3895 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3900 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
3902 static void fix_loops(ia32_transform_env_t *env, ir_node *node) {
3905 if (irn_visited(node))
3908 mark_irn_visited(node);
3910 assert(node_is_in_irgs_storage(env->irg, node));
3912 if (! is_Block(node)) {
3913 ir_node *block = get_nodes_block(node);
3914 ir_node *new_block = (ir_node *)get_irn_link(block);
3916 if (new_block != NULL) {
3917 set_nodes_block(node, new_block);
3921 fix_loops(env, block);
3924 arity = get_irn_arity(node);
3925 for (i = 0; i < arity; ++i) {
3926 ir_node *in = get_irn_n(node, i);
3927 ir_node *nw = (ir_node *)get_irn_link(in);
3929 if (nw != NULL && nw != in) {
3930 set_irn_n(node, i, nw);
3937 arity = get_irn_deps(node);
3938 for (i = 0; i < arity; ++i) {
3939 ir_node *in = get_irn_dep(node, i);
3940 ir_node *nw = (ir_node *)get_irn_link(in);
3942 if (nw != NULL && nw != in) {
3943 set_irn_dep(node, i, nw);
3951 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3956 *place = transform_node(env, *place);
3960 * Transforms all nodes. Deletes the old obstack and creates a new one.
3962 static void transform_nodes(ia32_code_gen_t *cg) {
3964 ir_graph *irg = cg->irg;
3966 ia32_transform_env_t env;
3968 hook_dead_node_elim(irg, 1);
3970 inc_irg_visited(irg);
3974 env.visited = get_irg_visited(irg);
3975 env.worklist = new_pdeq();
3976 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3978 old_end = get_irg_end(irg);
3980 /* put all anchor nodes in the worklist */
3981 for (i = 0; i < anchor_max; ++i) {
3982 ir_node *anchor = irg->anchors[i];
3986 pdeq_putr(env.worklist, anchor);
3988 /* remember anchor */
3989 env.old_anchors[i] = anchor;
3990 /* and set it to NULL to make sure we don't accidently use it */
3991 irg->anchors[i] = NULL;
3994 /* pre transform some anchors (so they are available in the other transform
3996 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3997 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3998 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3999 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
4000 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
4002 pre_transform_node(&cg->unknown_gp, &env);
4003 pre_transform_node(&cg->unknown_vfp, &env);
4004 pre_transform_node(&cg->unknown_xmm, &env);
4005 pre_transform_node(&cg->noreg_gp, &env);
4006 pre_transform_node(&cg->noreg_vfp, &env);
4007 pre_transform_node(&cg->noreg_xmm, &env);
4009 /* process worklist (this should transform all nodes in the graph) */
4010 while (! pdeq_empty(env.worklist)) {
4011 ir_node *node = pdeq_getl(env.worklist);
4012 transform_node(&env, node);
4015 /* fix loops and set new anchors*/
4016 inc_irg_visited(irg);
4017 for (i = 0; i < anchor_max; ++i) {
4018 ir_node *anchor = env.old_anchors[i];
4023 anchor = get_irn_link(anchor);
4024 fix_loops(&env, anchor);
4025 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4026 irg->anchors[i] = anchor;
4029 del_pdeq(env.worklist);
4031 hook_dead_node_elim(irg, 0);
4034 void ia32_transform_graph(ia32_code_gen_t *cg)
4036 ir_graph *irg = cg->irg;
4037 be_irg_t *birg = cg->birg;
4038 ir_graph *old_current_ir_graph = current_ir_graph;
4039 int old_interprocedural_view = get_interprocedural_view();
4040 struct obstack *old_obst = NULL;
4041 struct obstack *new_obst = NULL;
4043 current_ir_graph = irg;
4044 set_interprocedural_view(0);
4045 register_transformers();
4047 /* most analysis info is wrong after transformation */
4048 free_callee_info(irg);
4050 irg->outs_state = outs_none;
4052 free_loop_information(irg);
4053 set_irg_doms_inconsistent(irg);
4054 be_invalidate_liveness(birg);
4055 be_invalidate_dom_front(birg);
4057 /* create a new obstack */
4058 old_obst = irg->obst;
4059 new_obst = xmalloc(sizeof(*new_obst));
4060 obstack_init(new_obst);
4061 irg->obst = new_obst;
4062 irg->last_node_idx = 0;
4064 /* create new value table for CSE */
4065 del_identities(irg->value_table);
4066 irg->value_table = new_identities();
4068 /* do the main transformation */
4069 transform_nodes(cg);
4071 /* we don't want the globals anchor anymore */
4072 set_irg_globals(irg, new_r_Bad(irg));
4074 /* free the old obstack */
4075 obstack_free(old_obst, 0);
4079 current_ir_graph = old_current_ir_graph;
4080 set_interprocedural_view(old_interprocedural_view);
4082 /* recalculate edges */
4083 edges_deactivate(irg);
4084 edges_activate(irg);
4088 * Transforms a psi condition.
4090 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4093 /* if the mode is target mode, we have already seen this part of the tree */
4094 if (get_irn_mode(cond) == mode)
4097 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4099 set_irn_mode(cond, mode);
4101 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4102 ir_node *in = get_irn_n(cond, i);
4104 /* if in is a compare: transform into Set/xCmp */
4106 ir_node *new_op = NULL;
4107 ir_node *cmp = get_Proj_pred(in);
4108 ir_node *cmp_a = get_Cmp_left(cmp);
4109 ir_node *cmp_b = get_Cmp_right(cmp);
4110 dbg_info *dbgi = get_irn_dbg_info(cmp);
4111 ir_graph *irg = get_irn_irg(cmp);
4112 ir_node *block = get_nodes_block(cmp);
4113 ir_node *noreg = ia32_new_NoReg_gp(cg);
4114 ir_node *nomem = new_rd_NoMem(irg);
4115 int pnc = get_Proj_proj(in);
4117 /* this is a compare */
4118 if (mode_is_float(mode)) {
4119 /* Psi is float, we need a floating point compare */
4122 ir_mode *m = get_irn_mode(cmp_a);
4124 if (! mode_is_float(m)) {
4125 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4126 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4127 } else if (m == mode_F) {
4128 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4129 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4130 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4133 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4134 set_ia32_pncode(new_op, pnc);
4135 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4142 construct_binop_func *set_func = NULL;
4144 if (mode_is_float(get_irn_mode(cmp_a))) {
4145 /* 1st case: compare operands are floats */
4150 set_func = new_rd_ia32_xCmpSet;
4153 set_func = new_rd_ia32_vfCmpSet;
4156 pnc &= 7; /* fp compare -> int compare */
4158 /* 2nd case: compare operand are integer too */
4159 set_func = new_rd_ia32_CmpSet;
4162 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4163 if (! mode_is_signed(mode))
4164 pnc |= ia32_pn_Cmp_Unsigned;
4166 set_ia32_pncode(new_op, pnc);
4167 set_ia32_am_support(new_op, ia32_am_Source);
4170 /* the the new compare as in */
4171 set_irn_n(cond, i, new_op);
4173 /* another complex condition */
4174 transform_psi_cond(in, mode, cg);
4180 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4181 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4182 * each compare, which causes the compare result to be stored in a register. The
4183 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4185 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4186 ia32_code_gen_t *cg = env;
4187 ir_node *psi_sel, *new_cmp, *block;
4192 if (get_irn_opcode(node) != iro_Psi)
4195 psi_sel = get_Psi_cond(node, 0);
4197 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4198 if (is_Proj(psi_sel)) {
4199 assert(is_Cmp(get_Proj_pred(psi_sel)));
4203 //mode = get_irn_mode(node);
4204 // TODO probably wrong...
4207 transform_psi_cond(psi_sel, mode, cg);
4209 irg = get_irn_irg(node);
4210 block = get_nodes_block(node);
4212 /* we need to compare the evaluated condition tree with 0 */
4213 mode = get_irn_mode(node);
4214 if (mode_is_float(mode)) {
4215 /* BEWARE: new_r_Const_long works for floating point as well */
4216 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4218 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4219 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4220 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4222 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4223 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4224 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4227 set_Psi_cond(node, 0, new_cmp);
4230 void ia32_init_transform(void)
4232 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");