2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "archop.h" /* we need this for Min and Max nodes */
57 #include "../benode_t.h"
58 #include "../besched.h"
60 #include "../beutil.h"
61 #include "../beirg_t.h"
63 #include "bearch_ia32_t.h"
64 #include "ia32_nodes_attr.h"
65 #include "ia32_transform.h"
66 #include "ia32_new_nodes.h"
67 #include "ia32_map_regs.h"
68 #include "ia32_dbg_stat.h"
69 #include "ia32_optimize.h"
70 #include "ia32_util.h"
72 #include "gen_ia32_regalloc_if.h"
74 #define SFP_SIGN "0x80000000"
75 #define DFP_SIGN "0x8000000000000000"
76 #define SFP_ABS "0x7FFFFFFF"
77 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 typedef struct ia32_transform_env_t {
95 ir_graph *irg; /**< The irg, the node should be created in */
96 ia32_code_gen_t *cg; /**< The code generator */
97 int visited; /**< visited count that indicates whether a
98 node is already transformed */
99 pdeq *worklist; /**< worklist of nodes that still need to be
101 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
102 } ia32_transform_env_t;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
127 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
128 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
131 static INLINE int mode_needs_gp_reg(ir_mode *mode)
133 if(mode == mode_fpcw)
136 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
139 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
141 set_irn_link(old_node, new_node);
144 static INLINE ir_node *get_new_node(ir_node *old_node)
146 assert(irn_visited(old_node));
147 return (ir_node*) get_irn_link(old_node);
151 * Returns 1 if irn is a Const representing 0, 0 otherwise
153 static INLINE int is_ia32_Const_0(ir_node *irn) {
154 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
155 && tarval_is_null(get_ia32_Immop_tarval(irn));
159 * Returns 1 if irn is a Const representing 1, 0 otherwise
161 static INLINE int is_ia32_Const_1(ir_node *irn) {
162 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
163 && tarval_is_one(get_ia32_Immop_tarval(irn));
167 * Collects all Projs of a node into the node array. Index is the projnum.
168 * BEWARE: The caller has to assure the appropriate array size!
170 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
171 const ir_edge_t *edge;
172 assert(get_irn_mode(irn) == mode_T && "need mode_T");
174 memset(projs, 0, size * sizeof(projs[0]));
176 foreach_out_edge(irn, edge) {
177 ir_node *proj = get_edge_src_irn(edge);
178 int proj_proj = get_Proj_proj(proj);
179 assert(proj_proj < size);
180 projs[proj_proj] = proj;
185 * Renumbers the proj having pn_old in the array tp pn_new
186 * and removes the proj from the array.
188 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
189 fprintf(stderr, "Warning: renumber_Proj used!\n");
191 set_Proj_proj(projs[pn_old], pn_new);
192 projs[pn_old] = NULL;
197 * creates a unique ident by adding a number to a tag
199 * @param tag the tag string, must contain a %d if a number
202 static ident *unique_id(const char *tag)
204 static unsigned id = 0;
207 snprintf(str, sizeof(str), tag, ++id);
208 return new_id_from_str(str);
212 * Get a primitive type for a mode.
214 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
216 pmap_entry *e = pmap_find(types, mode);
221 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
222 res = new_type_primitive(new_id_from_str(buf), mode);
223 pmap_insert(types, mode, res);
231 * Get an entity that is initialized with a tarval
233 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
235 tarval *tv = get_Const_tarval(cnst);
236 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
241 ir_mode *mode = get_irn_mode(cnst);
242 ir_type *tp = get_Const_type(cnst);
243 if (tp == firm_unknown_type)
244 tp = get_prim_type(cg->isa->types, mode);
246 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
248 set_entity_ld_ident(res, get_entity_ident(res));
249 set_entity_visibility(res, visibility_local);
250 set_entity_variability(res, variability_constant);
251 set_entity_allocation(res, allocation_static);
253 /* we create a new entity here: It's initialization must resist on the
255 rem = current_ir_graph;
256 current_ir_graph = get_const_code_irg();
257 set_atomic_ent_value(res, new_Const_type(tv, tp));
258 current_ir_graph = rem;
260 pmap_insert(cg->isa->tv_ent, tv, res);
269 * Transforms a Const.
271 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
272 ir_graph *irg = env->irg;
273 dbg_info *dbgi = get_irn_dbg_info(node);
274 ir_mode *mode = get_irn_mode(node);
275 ir_node *block = transform_node(env, get_nodes_block(node));
277 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env->cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env->cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
298 set_ia32_am_support(load, ia32_am_Source);
299 set_ia32_op_type(load, ia32_AddrModeS);
300 set_ia32_am_flavour(load, ia32_am_N);
301 set_ia32_am_sc(load, floatent);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env->cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_am_support(load, ia32_am_Source);
310 set_ia32_op_type(load, ia32_AddrModeS);
311 set_ia32_am_flavour(load, ia32_am_N);
312 set_ia32_am_sc(load, floatent);
313 set_ia32_ls_mode(load, mode);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(load, get_irg_frame(irg));
327 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
330 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
333 if (get_irg_start_block(irg) == block) {
334 add_irn_dep(cnst, get_irg_frame(irg));
337 set_ia32_Const_attr(cnst, node);
338 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
343 return new_r_Bad(irg);
347 * Transforms a SymConst.
349 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
350 ir_graph *irg = env->irg;
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
353 ir_node *block = transform_node(env, get_nodes_block(node));
356 if (mode_is_float(mode)) {
358 if (USE_SSE2(env->cg))
359 cnst = new_rd_ia32_xConst(dbgi, irg, block);
361 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
362 set_ia32_ls_mode(cnst, mode);
364 cnst = new_rd_ia32_Const(dbgi, irg, block);
367 /* Const Nodes before the initial IncSP are a bad idea, because
368 * they could be spilled and we have no SP ready at that point yet
370 if (get_irg_start_block(irg) == block) {
371 add_irn_dep(cnst, get_irg_frame(irg));
374 set_ia32_Const_attr(cnst, node);
375 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
381 * SSE convert of an integer node into a floating point node.
383 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
384 ir_graph *irg, ir_node *block,
385 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
387 ir_node *noreg = ia32_new_NoReg_gp(cg);
388 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *old_pred = get_Cmp_left(old_node);
390 ir_mode *in_mode = get_irn_mode(old_pred);
391 int in_bits = get_mode_size_bits(in_mode);
393 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
394 set_ia32_ls_mode(conv, tgt_mode);
396 set_ia32_am_support(conv, ia32_am_Source);
398 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
404 * SSE convert of an float node into a double node.
406 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
407 ir_graph *irg, ir_node *block,
408 ir_node *in, ir_node *old_node)
410 ir_node *noreg = ia32_new_NoReg_gp(cg);
411 ir_node *nomem = new_rd_NoMem(irg);
413 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
414 set_ia32_am_support(conv, ia32_am_Source);
415 set_ia32_ls_mode(conv, mode_xmm);
416 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
421 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
422 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
423 static const struct {
425 const char *ent_name;
426 const char *cnst_str;
427 } names [ia32_known_const_max] = {
428 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
429 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
430 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
431 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
433 static ir_entity *ent_cache[ia32_known_const_max];
435 const char *tp_name, *ent_name, *cnst_str;
443 ent_name = names[kct].ent_name;
444 if (! ent_cache[kct]) {
445 tp_name = names[kct].tp_name;
446 cnst_str = names[kct].cnst_str;
448 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
450 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
451 tp = new_type_primitive(new_id_from_str(tp_name), mode);
452 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
454 set_entity_ld_ident(ent, get_entity_ident(ent));
455 set_entity_visibility(ent, visibility_local);
456 set_entity_variability(ent, variability_constant);
457 set_entity_allocation(ent, allocation_static);
459 /* we create a new entity here: It's initialization must resist on the
461 rem = current_ir_graph;
462 current_ir_graph = get_const_code_irg();
463 cnst = new_Const(mode, tv);
464 current_ir_graph = rem;
466 set_atomic_ent_value(ent, cnst);
468 /* cache the entry */
469 ent_cache[kct] = ent;
472 return ent_cache[kct];
477 * Prints the old node name on cg obst and returns a pointer to it.
479 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
480 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
482 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
483 obstack_1grow(isa->name_obst, 0);
484 return obstack_finish(isa->name_obst);
488 /* determine if one operator is an Imm */
489 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
491 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
493 return is_ia32_Cnst(op2) ? op2 : NULL;
497 /* determine if one operator is not an Imm */
498 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
499 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
502 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
506 if(! (env->cg->opt & IA32_OPT_IMMOPS))
509 left = get_irn_n(node, in1);
510 right = get_irn_n(node, in2);
511 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
512 /* we can only set right operand to immediate */
513 if(!is_ia32_commutative(node))
515 /* exchange left/right */
516 set_irn_n(node, in1, right);
517 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
518 copy_ia32_Immop_attr(node, left);
519 } else if(is_ia32_Cnst(right)) {
520 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
521 copy_ia32_Immop_attr(node, right);
526 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
530 * Construct a standard binary operation, set AM and immediate if required.
532 * @param env The transformation environment
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
539 ir_node *op1, ir_node *op2,
540 construct_binop_func *func) {
541 ir_node *new_node = NULL;
542 ir_graph *irg = env->irg;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_node *block = transform_node(env, get_nodes_block(node));
545 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
546 ir_node *nomem = new_NoMem();
547 ir_node *new_op1 = transform_node(env, op1);
548 ir_node *new_op2 = transform_node(env, op2);
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
551 if(func == new_rd_ia32_IMul) {
552 set_ia32_am_support(new_node, ia32_am_Source);
554 set_ia32_am_support(new_node, ia32_am_Full);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
558 if (is_op_commutative(get_irn_op(node))) {
559 set_ia32_commutative(new_node);
561 fold_immediate(env, new_node, 2, 3);
567 * Construct a standard binary operation, set AM and immediate if required.
569 * @param env The transformation environment
570 * @param op1 The first operand
571 * @param op2 The second operand
572 * @param func The node constructor function
573 * @return The constructed ia32 node.
575 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
576 ir_node *op1, ir_node *op2,
577 construct_binop_func *func)
579 ir_node *new_node = NULL;
580 dbg_info *dbgi = get_irn_dbg_info(node);
581 ir_graph *irg = env->irg;
582 ir_mode *mode = get_irn_mode(node);
583 ir_node *block = transform_node(env, get_nodes_block(node));
584 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
585 ir_node *nomem = new_NoMem();
586 ir_node *new_op1 = transform_node(env, op1);
587 ir_node *new_op2 = transform_node(env, op2);
589 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
590 set_ia32_am_support(new_node, ia32_am_Source);
591 if (is_op_commutative(get_irn_op(node))) {
592 set_ia32_commutative(new_node);
594 if (USE_SSE2(env->cg)) {
595 set_ia32_ls_mode(new_node, mode);
598 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
605 * Construct a shift/rotate binary operation, sets AM and immediate if required.
607 * @param env The transformation environment
608 * @param op1 The first operand
609 * @param op2 The second operand
610 * @param func The node constructor function
611 * @return The constructed ia32 node.
613 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
614 ir_node *op1, ir_node *op2,
615 construct_binop_func *func) {
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = env->irg;
619 ir_node *block = transform_node(env, get_nodes_block(node));
620 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
621 ir_node *nomem = new_NoMem();
624 ir_node *new_op1 = transform_node(env, op1);
625 ir_node *new_op2 = transform_node(env, op2);
628 assert(! mode_is_float(get_irn_mode(node))
629 && "Shift/Rotate with float not supported");
631 /* Check if immediate optimization is on and */
632 /* if it's an operation with immediate. */
633 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
634 expr_op = get_expr_op(new_op1, new_op2);
636 assert((expr_op || imm_op) && "invalid operands");
639 /* We have two consts here: not yet supported */
643 /* Limit imm_op within range imm8 */
645 tv = get_ia32_Immop_tarval(imm_op);
648 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
649 set_ia32_Immop_tarval(imm_op, tv);
656 /* integer operations */
658 /* This is shift/rot with const */
659 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
661 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
662 copy_ia32_Immop_attr(new_op, imm_op);
664 /* This is a normal shift/rot */
665 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
666 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
670 set_ia32_am_support(new_op, ia32_am_Dest);
672 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
674 set_ia32_emit_cl(new_op);
681 * Construct a standard unary operation, set AM and immediate if required.
683 * @param env The transformation environment
684 * @param op The operand
685 * @param func The node constructor function
686 * @return The constructed ia32 node.
688 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
689 construct_unop_func *func) {
690 ir_node *new_node = NULL;
691 ir_graph *irg = env->irg;
692 dbg_info *dbgi = get_irn_dbg_info(node);
693 ir_node *block = transform_node(env, get_nodes_block(node));
694 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
695 ir_node *nomem = new_NoMem();
696 ir_node *new_op = transform_node(env, op);
698 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
699 DB((dbg, LEVEL_1, "INT unop ..."));
700 set_ia32_am_support(new_node, ia32_am_Dest);
702 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
709 * Creates an ia32 Add.
711 * @param env The transformation environment
712 * @return the created ia32 Add node
714 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
715 ir_node *new_op = NULL;
716 ir_graph *irg = env->irg;
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_mode *mode = get_irn_mode(node);
719 ir_node *block = transform_node(env, get_nodes_block(node));
720 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
721 ir_node *nomem = new_NoMem();
722 ir_node *expr_op, *imm_op;
723 ir_node *op1 = get_Add_left(node);
724 ir_node *op2 = get_Add_right(node);
725 ir_node *new_op1 = transform_node(env, op1);
726 ir_node *new_op2 = transform_node(env, op2);
728 /* Check if immediate optimization is on and */
729 /* if it's an operation with immediate. */
730 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
731 expr_op = get_expr_op(new_op1, new_op2);
733 assert((expr_op || imm_op) && "invalid operands");
735 if (mode_is_float(mode)) {
737 if (USE_SSE2(env->cg))
738 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
740 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
745 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
746 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
748 /* No expr_op means, that we have two const - one symconst and */
749 /* one tarval or another symconst - because this case is not */
750 /* covered by constant folding */
751 /* We need to check for: */
752 /* 1) symconst + const -> becomes a LEA */
753 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
754 /* linker doesn't support two symconsts */
756 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
757 /* this is the 2nd case */
758 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
759 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
760 set_ia32_am_flavour(new_op, ia32_am_OB);
761 set_ia32_am_support(new_op, ia32_am_Source);
762 set_ia32_op_type(new_op, ia32_AddrModeS);
764 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 } else if (tp1 == ia32_ImmSymConst) {
766 tarval *tv = get_ia32_Immop_tarval(new_op2);
767 long offs = get_tarval_long(tv);
769 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
770 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
772 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
773 add_ia32_am_offs_int(new_op, offs);
774 set_ia32_am_flavour(new_op, ia32_am_O);
775 set_ia32_am_support(new_op, ia32_am_Source);
776 set_ia32_op_type(new_op, ia32_AddrModeS);
777 } else if (tp2 == ia32_ImmSymConst) {
778 tarval *tv = get_ia32_Immop_tarval(new_op1);
779 long offs = get_tarval_long(tv);
781 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
782 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
784 add_ia32_am_offs_int(new_op, offs);
785 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
786 set_ia32_am_flavour(new_op, ia32_am_O);
787 set_ia32_am_support(new_op, ia32_am_Source);
788 set_ia32_op_type(new_op, ia32_AddrModeS);
790 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
791 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
792 tarval *restv = tarval_add(tv1, tv2);
794 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
796 new_op = new_rd_ia32_Const(dbgi, irg, block);
797 set_ia32_Const_tarval(new_op, restv);
798 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
801 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
804 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
805 tarval_classification_t class_tv, class_negtv;
806 tarval *tv = get_ia32_Immop_tarval(imm_op);
808 /* optimize tarvals */
809 class_tv = classify_tarval(tv);
810 class_negtv = classify_tarval(tarval_neg(tv));
812 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
813 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
814 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
817 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
818 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
819 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
820 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
826 /* This is a normal add */
827 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
830 set_ia32_am_support(new_op, ia32_am_Full);
831 set_ia32_commutative(new_op);
833 fold_immediate(env, new_op, 2, 3);
835 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
841 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
842 ir_graph *irg = env->irg;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *block = transform_node(env, get_nodes_block(node));
845 ir_node *op1 = get_Mul_left(node);
846 ir_node *op2 = get_Mul_right(node);
847 ir_node *new_op1 = transform_node(env, op1);
848 ir_node *new_op2 = transform_node(env, op2);
849 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
850 ir_node *proj_EAX, *proj_EDX, *res;
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
854 set_ia32_commutative(res);
855 set_ia32_am_support(res, ia32_am_Source);
857 /* imediates are not supported, so no fold_immediate */
858 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
859 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
863 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
871 * Creates an ia32 Mul.
873 * @param env The transformation environment
874 * @return the created ia32 Mul node
876 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
877 ir_node *op1 = get_Mul_left(node);
878 ir_node *op2 = get_Mul_right(node);
879 ir_mode *mode = get_irn_mode(node);
881 if (mode_is_float(mode)) {
883 if (USE_SSE2(env->cg))
884 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
886 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
889 // for the lower 32bit of the result it doesn't matter whether we use
890 // signed or unsigned multiplication so we use IMul as it has fewer
892 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
896 * Creates an ia32 Mulh.
897 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
898 * this result while Mul returns the lower 32 bit.
900 * @param env The transformation environment
901 * @return the created ia32 Mulh node
903 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
904 ir_graph *irg = env->irg;
905 dbg_info *dbgi = get_irn_dbg_info(node);
906 ir_node *block = transform_node(env, get_nodes_block(node));
907 ir_node *op1 = get_irn_n(node, 0);
908 ir_node *op2 = get_irn_n(node, 1);
909 ir_node *new_op1 = transform_node(env, op1);
910 ir_node *new_op2 = transform_node(env, op2);
911 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
912 ir_node *proj_EAX, *proj_EDX, *res;
913 ir_mode *mode = get_irn_mode(node);
916 assert(!mode_is_float(mode) && "Mulh with float not supported");
917 if(mode_is_signed(mode)) {
918 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
920 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
923 set_ia32_commutative(res);
924 set_ia32_am_support(res, ia32_am_Source);
926 set_ia32_am_support(res, ia32_am_Source);
928 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
929 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
933 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
941 * Creates an ia32 And.
943 * @param env The transformation environment
944 * @return The created ia32 And node
946 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
947 ir_node *op1 = get_And_left(node);
948 ir_node *op2 = get_And_right(node);
950 assert (! mode_is_float(get_irn_mode(node)));
951 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
957 * Creates an ia32 Or.
959 * @param env The transformation environment
960 * @return The created ia32 Or node
962 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
963 ir_node *op1 = get_Or_left(node);
964 ir_node *op2 = get_Or_right(node);
966 assert (! mode_is_float(get_irn_mode(node)));
967 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
973 * Creates an ia32 Eor.
975 * @param env The transformation environment
976 * @return The created ia32 Eor node
978 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
979 ir_node *op1 = get_Eor_left(node);
980 ir_node *op2 = get_Eor_right(node);
982 assert(! mode_is_float(get_irn_mode(node)));
983 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
989 * Creates an ia32 Max.
991 * @param env The transformation environment
992 * @return the created ia32 Max node
994 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
995 ir_graph *irg = env->irg;
997 ir_mode *mode = get_irn_mode(node);
998 dbg_info *dbgi = get_irn_dbg_info(node);
999 ir_node *block = transform_node(env, get_nodes_block(node));
1000 ir_node *op1 = get_irn_n(node, 0);
1001 ir_node *op2 = get_irn_n(node, 1);
1002 ir_node *new_op1 = transform_node(env, op1);
1003 ir_node *new_op2 = transform_node(env, op2);
1004 ir_mode *op_mode = get_irn_mode(op1);
1006 assert(get_mode_size_bits(mode) == 32);
1008 if (mode_is_float(mode)) {
1010 if (USE_SSE2(env->cg)) {
1011 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
1013 panic("Can't create Max node");
1016 long pnc = pn_Cmp_Gt;
1017 if(!mode_is_signed(op_mode)) {
1018 pnc |= ia32_pn_Cmp_Unsigned;
1020 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1021 set_ia32_pncode(new_op, pnc);
1022 set_ia32_am_support(new_op, ia32_am_None);
1024 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1030 * Creates an ia32 Min.
1032 * @param env The transformation environment
1033 * @return the created ia32 Min node
1035 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1036 ir_graph *irg = env->irg;
1038 ir_mode *mode = get_irn_mode(node);
1039 dbg_info *dbgi = get_irn_dbg_info(node);
1040 ir_node *block = transform_node(env, get_nodes_block(node));
1041 ir_node *op1 = get_irn_n(node, 0);
1042 ir_node *op2 = get_irn_n(node, 1);
1043 ir_node *new_op1 = transform_node(env, op1);
1044 ir_node *new_op2 = transform_node(env, op2);
1045 ir_mode *op_mode = get_irn_mode(op1);
1047 assert(get_mode_size_bits(mode) == 32);
1049 if (mode_is_float(mode)) {
1051 if (USE_SSE2(env->cg)) {
1052 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1054 panic("can't create Min node");
1057 long pnc = pn_Cmp_Lt;
1058 if(!mode_is_signed(op_mode)) {
1059 pnc |= ia32_pn_Cmp_Unsigned;
1061 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1062 set_ia32_pncode(new_op, pnc);
1063 set_ia32_am_support(new_op, ia32_am_None);
1065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1072 * Creates an ia32 Sub.
1074 * @param env The transformation environment
1075 * @return The created ia32 Sub node
1077 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1078 ir_node *new_op = NULL;
1079 ir_graph *irg = env->irg;
1080 dbg_info *dbgi = get_irn_dbg_info(node);
1081 ir_mode *mode = get_irn_mode(node);
1082 ir_node *block = transform_node(env, get_nodes_block(node));
1083 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1084 ir_node *nomem = new_NoMem();
1085 ir_node *op1 = get_Sub_left(node);
1086 ir_node *op2 = get_Sub_right(node);
1087 ir_node *new_op1 = transform_node(env, op1);
1088 ir_node *new_op2 = transform_node(env, op2);
1089 ir_node *expr_op, *imm_op;
1091 /* Check if immediate optimization is on and */
1092 /* if it's an operation with immediate. */
1093 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1094 expr_op = get_expr_op(new_op1, new_op2);
1096 assert((expr_op || imm_op) && "invalid operands");
1098 if (mode_is_float(mode)) {
1100 if (USE_SSE2(env->cg))
1101 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1103 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1108 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1109 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1111 /* No expr_op means, that we have two const - one symconst and */
1112 /* one tarval or another symconst - because this case is not */
1113 /* covered by constant folding */
1114 /* We need to check for: */
1115 /* 1) symconst - const -> becomes a LEA */
1116 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1117 /* linker doesn't support two symconsts */
1118 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1119 /* this is the 2nd case */
1120 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1121 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1122 set_ia32_am_sc_sign(new_op);
1123 set_ia32_am_flavour(new_op, ia32_am_OB);
1125 DBG_OPT_LEA3(op1, op2, node, new_op);
1126 } else if (tp1 == ia32_ImmSymConst) {
1127 tarval *tv = get_ia32_Immop_tarval(new_op2);
1128 long offs = get_tarval_long(tv);
1130 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1131 DBG_OPT_LEA3(op1, op2, node, new_op);
1133 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1134 add_ia32_am_offs_int(new_op, -offs);
1135 set_ia32_am_flavour(new_op, ia32_am_O);
1136 set_ia32_am_support(new_op, ia32_am_Source);
1137 set_ia32_op_type(new_op, ia32_AddrModeS);
1138 } else if (tp2 == ia32_ImmSymConst) {
1139 tarval *tv = get_ia32_Immop_tarval(new_op1);
1140 long offs = get_tarval_long(tv);
1142 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1143 DBG_OPT_LEA3(op1, op2, node, new_op);
1145 add_ia32_am_offs_int(new_op, offs);
1146 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1147 set_ia32_am_sc_sign(new_op);
1148 set_ia32_am_flavour(new_op, ia32_am_O);
1149 set_ia32_am_support(new_op, ia32_am_Source);
1150 set_ia32_op_type(new_op, ia32_AddrModeS);
1152 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1153 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1154 tarval *restv = tarval_sub(tv1, tv2);
1156 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1158 new_op = new_rd_ia32_Const(dbgi, irg, block);
1159 set_ia32_Const_tarval(new_op, restv);
1160 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1163 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1165 } else if (imm_op) {
1166 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1167 tarval_classification_t class_tv, class_negtv;
1168 tarval *tv = get_ia32_Immop_tarval(imm_op);
1170 /* optimize tarvals */
1171 class_tv = classify_tarval(tv);
1172 class_negtv = classify_tarval(tarval_neg(tv));
1174 if (class_tv == TV_CLASSIFY_ONE) {
1175 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1176 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1177 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1179 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1180 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1181 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1182 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1188 /* This is a normal sub */
1189 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1191 /* set AM support */
1192 set_ia32_am_support(new_op, ia32_am_Full);
1194 fold_immediate(env, new_op, 2, 3);
1196 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1204 * Generates an ia32 DivMod with additional infrastructure for the
1205 * register allocator if needed.
1207 * @param env The transformation environment
1208 * @param dividend -no comment- :)
1209 * @param divisor -no comment- :)
1210 * @param dm_flav flavour_Div/Mod/DivMod
1211 * @return The created ia32 DivMod node
1213 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1214 ir_node *dividend, ir_node *divisor,
1215 ia32_op_flavour_t dm_flav) {
1216 ir_graph *irg = env->irg;
1217 dbg_info *dbgi = get_irn_dbg_info(node);
1218 ir_mode *mode = get_irn_mode(node);
1219 ir_node *block = transform_node(env, get_nodes_block(node));
1220 ir_node *res, *proj_div, *proj_mod;
1221 ir_node *edx_node, *cltd;
1222 ir_node *in_keep[2];
1223 ir_node *mem, *new_mem;
1224 ir_node *projs[pn_DivMod_max];
1225 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1226 ir_node *new_dividend = transform_node(env, dividend);
1227 ir_node *new_divisor = transform_node(env, divisor);
1230 ia32_collect_Projs(node, projs, pn_DivMod_max);
1234 mem = get_Div_mem(node);
1235 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1236 if(proj_div == NULL) {
1237 /* this can happen when we have divs left that could
1238 throw a division by zero exception... */
1241 mode = get_irn_mode(proj_div);
1245 mem = get_Mod_mem(node);
1246 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1247 if(proj_mod == NULL) {
1248 /* this can happen when we have divs left that could
1249 throw a division by zero exception... */
1252 mode = get_irn_mode(proj_mod);
1255 case flavour_DivMod:
1256 mem = get_DivMod_mem(node);
1257 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1258 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1259 if(proj_div != NULL) {
1260 mode = get_irn_mode(proj_div);
1261 } else if(proj_mod != NULL) {
1262 mode = get_irn_mode(proj_mod);
1264 /* this can happen when we have divs left that could
1265 throw a division by zero exception... */
1270 panic("invalid divmod flavour!");
1272 new_mem = transform_node(env, mem);
1274 if (mode_is_signed(mode)) {
1275 /* in signed mode, we need to sign extend the dividend */
1276 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1277 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1278 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1280 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1281 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1282 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1285 if(mode_is_signed(mode)) {
1286 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1288 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1291 /* Matze: code can't handle this at the moment... */
1293 /* set AM support */
1294 set_ia32_am_support(res, ia32_am_Source);
1297 set_ia32_n_res(res, 2);
1299 /* check, which Proj-Keep, we need to add */
1301 if (proj_div == NULL) {
1302 /* We have only mod result: add div res Proj-Keep */
1303 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1306 if (proj_mod == NULL) {
1307 /* We have only div result: add mod res Proj-Keep */
1308 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1312 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1314 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1321 * Wrapper for generate_DivMod. Sets flavour_Mod.
1323 * @param env The transformation environment
1325 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1326 return generate_DivMod(env, node, get_Mod_left(node),
1327 get_Mod_right(node), flavour_Mod);
1331 * Wrapper for generate_DivMod. Sets flavour_Div.
1333 * @param env The transformation environment
1335 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1336 return generate_DivMod(env, node, get_Div_left(node),
1337 get_Div_right(node), flavour_Div);
1341 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1343 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1344 return generate_DivMod(env, node, get_DivMod_left(node),
1345 get_DivMod_right(node), flavour_DivMod);
1351 * Creates an ia32 floating Div.
1353 * @param env The transformation environment
1354 * @return The created ia32 xDiv node
1356 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1357 ir_graph *irg = env->irg;
1358 dbg_info *dbgi = get_irn_dbg_info(node);
1359 ir_node *block = transform_node(env, get_nodes_block(node));
1360 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1362 ir_node *nomem = new_rd_NoMem(env->irg);
1363 ir_node *op1 = get_Quot_left(node);
1364 ir_node *op2 = get_Quot_right(node);
1365 ir_node *new_op1 = transform_node(env, op1);
1366 ir_node *new_op2 = transform_node(env, op2);
1369 if (USE_SSE2(env->cg)) {
1370 ir_mode *mode = get_irn_mode(op1);
1371 if (is_ia32_xConst(new_op2)) {
1372 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1373 set_ia32_am_support(new_op, ia32_am_None);
1374 copy_ia32_Immop_attr(new_op, new_op2);
1376 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1377 // Matze: disabled for now, spillslot coalescer fails
1378 //set_ia32_am_support(new_op, ia32_am_Source);
1380 set_ia32_ls_mode(new_op, mode);
1382 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1383 // Matze: disabled for now (spillslot coalescer fails)
1384 //set_ia32_am_support(new_op, ia32_am_Source);
1386 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1392 * Creates an ia32 Shl.
1394 * @param env The transformation environment
1395 * @return The created ia32 Shl node
1397 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1398 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1405 * Creates an ia32 Shr.
1407 * @param env The transformation environment
1408 * @return The created ia32 Shr node
1410 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1411 return gen_shift_binop(env, node, get_Shr_left(node),
1412 get_Shr_right(node), new_rd_ia32_Shr);
1418 * Creates an ia32 Sar.
1420 * @param env The transformation environment
1421 * @return The created ia32 Shrs node
1423 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1424 return gen_shift_binop(env, node, get_Shrs_left(node),
1425 get_Shrs_right(node), new_rd_ia32_Sar);
1431 * Creates an ia32 RotL.
1433 * @param env The transformation environment
1434 * @param op1 The first operator
1435 * @param op2 The second operator
1436 * @return The created ia32 RotL node
1438 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1439 ir_node *op1, ir_node *op2) {
1440 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1446 * Creates an ia32 RotR.
1447 * NOTE: There is no RotR with immediate because this would always be a RotL
1448 * "imm-mode_size_bits" which can be pre-calculated.
1450 * @param env The transformation environment
1451 * @param op1 The first operator
1452 * @param op2 The second operator
1453 * @return The created ia32 RotR node
1455 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1457 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1463 * Creates an ia32 RotR or RotL (depending on the found pattern).
1465 * @param env The transformation environment
1466 * @return The created ia32 RotL or RotR node
1468 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1469 ir_node *rotate = NULL;
1470 ir_node *op1 = get_Rot_left(node);
1471 ir_node *op2 = get_Rot_right(node);
1473 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1474 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1475 that means we can create a RotR instead of an Add and a RotL */
1477 if (get_irn_op(op2) == op_Add) {
1479 ir_node *left = get_Add_left(add);
1480 ir_node *right = get_Add_right(add);
1481 if (is_Const(right)) {
1482 tarval *tv = get_Const_tarval(right);
1483 ir_mode *mode = get_irn_mode(node);
1484 long bits = get_mode_size_bits(mode);
1486 if (get_irn_op(left) == op_Minus &&
1487 tarval_is_long(tv) &&
1488 get_tarval_long(tv) == bits)
1490 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1491 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1496 if (rotate == NULL) {
1497 rotate = gen_RotL(env, node, op1, op2);
1506 * Transforms a Minus node.
1508 * @param env The transformation environment
1509 * @param op The Minus operand
1510 * @return The created ia32 Minus node
1512 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1515 ir_graph *irg = env->irg;
1516 dbg_info *dbgi = get_irn_dbg_info(node);
1517 ir_node *block = transform_node(env, get_nodes_block(node));
1518 ir_mode *mode = get_irn_mode(node);
1521 if (mode_is_float(mode)) {
1522 ir_node *new_op = transform_node(env, op);
1524 if (USE_SSE2(env->cg)) {
1525 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1526 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1527 ir_node *nomem = new_rd_NoMem(irg);
1529 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1531 size = get_mode_size_bits(mode);
1532 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1534 set_ia32_am_sc(res, ent);
1535 set_ia32_op_type(res, ia32_AddrModeS);
1536 set_ia32_ls_mode(res, mode);
1538 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1541 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1544 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1550 * Transforms a Minus node.
1552 * @param env The transformation environment
1553 * @return The created ia32 Minus node
1555 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1556 return gen_Minus_ex(env, node, get_Minus_op(node));
1561 * Transforms a Not node.
1563 * @param env The transformation environment
1564 * @return The created ia32 Not node
1566 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1567 ir_node *op = get_Not_op(node);
1569 assert (! mode_is_float(get_irn_mode(node)));
1570 return gen_unop(env, node, op, new_rd_ia32_Not);
1576 * Transforms an Abs node.
1578 * @param env The transformation environment
1579 * @return The created ia32 Abs node
1581 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1582 ir_node *res, *p_eax, *p_edx;
1583 ir_graph *irg = env->irg;
1584 dbg_info *dbgi = get_irn_dbg_info(node);
1585 ir_node *block = transform_node(env, get_nodes_block(node));
1586 ir_mode *mode = get_irn_mode(node);
1587 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1588 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1589 ir_node *nomem = new_NoMem();
1590 ir_node *op = get_Abs_op(node);
1591 ir_node *new_op = transform_node(env, op);
1595 if (mode_is_float(mode)) {
1597 if (USE_SSE2(env->cg)) {
1598 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1600 size = get_mode_size_bits(mode);
1601 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1603 set_ia32_am_sc(res, ent);
1605 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1607 set_ia32_op_type(res, ia32_AddrModeS);
1608 set_ia32_ls_mode(res, mode);
1611 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1612 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1616 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1617 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1619 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1620 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1622 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1623 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1625 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1626 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1635 * Transforms a Load.
1637 * @param env The transformation environment
1638 * @return the created ia32 Load node
1640 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1641 ir_graph *irg = env->irg;
1642 dbg_info *dbgi = get_irn_dbg_info(node);
1643 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1644 ir_mode *mode = get_Load_mode(node);
1645 ir_node *block = transform_node(env, get_nodes_block(node));
1646 ir_node *ptr = get_Load_ptr(node);
1647 ir_node *new_ptr = transform_node(env, ptr);
1648 ir_node *lptr = new_ptr;
1649 ir_node *mem = get_Load_mem(node);
1650 ir_node *new_mem = transform_node(env, mem);
1653 ia32_am_flavour_t am_flav = ia32_am_B;
1654 ir_node *projs[pn_Load_max];
1656 ia32_collect_Projs(node, projs, pn_Load_max);
1659 check for special case: the loaded value might not be used (optimized, volatile, ...)
1660 we add a Proj + Keep for volatile loads and ignore all other cases
1662 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1663 /* add a result proj and a Keep to produce a pseudo use */
1664 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1665 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1668 /* address might be a constant (symconst or absolute address) */
1669 if (is_ia32_Const(new_ptr)) {
1674 if (mode_is_float(mode)) {
1676 if (USE_SSE2(env->cg)) {
1677 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1679 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1682 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1685 /* base is a constant address */
1687 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1688 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1689 am_flav = ia32_am_N;
1691 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1692 long offs = get_tarval_long(tv);
1694 add_ia32_am_offs_int(new_op, offs);
1695 am_flav = ia32_am_O;
1699 set_ia32_am_support(new_op, ia32_am_Source);
1700 set_ia32_op_type(new_op, ia32_AddrModeS);
1701 set_ia32_am_flavour(new_op, am_flav);
1702 set_ia32_ls_mode(new_op, mode);
1704 /* make sure we are scheduled behind the intial IncSP/Barrier
1705 * to avoid spills being placed before it
1707 if(block == get_irg_start_block(irg)) {
1708 add_irn_dep(new_op, get_irg_frame(irg));
1711 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1719 * Transforms a Store.
1721 * @param env The transformation environment
1722 * @return the created ia32 Store node
1724 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1725 ir_graph *irg = env->irg;
1726 dbg_info *dbgi = get_irn_dbg_info(node);
1727 ir_node *block = transform_node(env, get_nodes_block(node));
1728 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1729 ir_node *ptr = get_Store_ptr(node);
1730 ir_node *new_ptr = transform_node(env, ptr);
1731 ir_node *sptr = new_ptr;
1732 ir_node *val = get_Store_value(node);
1733 ir_node *new_val = transform_node(env, val);
1734 ir_node *mem = get_Store_mem(node);
1735 ir_node *new_mem = transform_node(env, mem);
1736 ir_mode *mode = get_irn_mode(val);
1737 ir_node *sval = new_val;
1740 ia32_am_flavour_t am_flav = ia32_am_B;
1742 if (is_ia32_Const(new_val)) {
1743 assert(!mode_is_float(mode));
1747 /* address might be a constant (symconst or absolute address) */
1748 if (is_ia32_Const(new_ptr)) {
1753 if (mode_is_float(mode)) {
1755 if (USE_SSE2(env->cg)) {
1756 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1758 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1760 } else if (get_mode_size_bits(mode) == 8) {
1761 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1763 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1766 /* stored const is an immediate value */
1767 if (is_ia32_Const(new_val)) {
1768 assert(!mode_is_float(mode));
1769 copy_ia32_Immop_attr(new_op, new_val);
1772 /* base is an constant address */
1774 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1775 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1776 am_flav = ia32_am_N;
1778 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1779 long offs = get_tarval_long(tv);
1781 add_ia32_am_offs_int(new_op, offs);
1782 am_flav = ia32_am_O;
1786 set_ia32_am_support(new_op, ia32_am_Dest);
1787 set_ia32_op_type(new_op, ia32_AddrModeD);
1788 set_ia32_am_flavour(new_op, am_flav);
1789 set_ia32_ls_mode(new_op, mode);
1791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1799 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1801 * @param env The transformation environment
1802 * @return The transformed node.
1804 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1805 ir_graph *irg = env->irg;
1806 dbg_info *dbgi = get_irn_dbg_info(node);
1807 ir_node *block = transform_node(env, get_nodes_block(node));
1808 ir_node *sel = get_Cond_selector(node);
1809 ir_mode *sel_mode = get_irn_mode(sel);
1810 ir_node *res = NULL;
1811 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1812 ir_node *cnst, *expr;
1814 if (is_Proj(sel) && sel_mode == mode_b) {
1815 ir_node *nomem = new_NoMem();
1816 ir_node *pred = get_Proj_pred(sel);
1817 ir_node *cmp_a = get_Cmp_left(pred);
1818 ir_node *new_cmp_a = transform_node(env, cmp_a);
1819 ir_node *cmp_b = get_Cmp_right(pred);
1820 ir_node *new_cmp_b = transform_node(env, cmp_b);
1821 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1823 int pnc = get_Proj_proj(sel);
1824 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1825 pnc |= ia32_pn_Cmp_Unsigned;
1828 /* check if we can use a CondJmp with immediate */
1829 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1830 expr = get_expr_op(new_cmp_a, new_cmp_b);
1832 if (cnst != NULL && expr != NULL) {
1833 /* immop has to be the right operand, we might need to flip pnc */
1834 if(cnst != new_cmp_b) {
1835 pnc = get_inversed_pnc(pnc);
1838 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1839 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1840 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1842 /* a Cmp A =/!= 0 */
1843 ir_node *op1 = expr;
1844 ir_node *op2 = expr;
1847 /* check, if expr is an only once used And operation */
1848 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1849 op1 = get_irn_n(expr, 2);
1850 op2 = get_irn_n(expr, 3);
1852 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1854 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1855 set_ia32_pncode(res, pnc);
1858 copy_ia32_Immop_attr(res, expr);
1861 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1866 if (mode_is_float(cmp_mode)) {
1868 if (USE_SSE2(env->cg)) {
1869 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1870 set_ia32_ls_mode(res, cmp_mode);
1876 assert(get_mode_size_bits(cmp_mode) == 32);
1877 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1879 copy_ia32_Immop_attr(res, cnst);
1882 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1884 if (mode_is_float(cmp_mode)) {
1886 if (USE_SSE2(env->cg)) {
1887 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1888 set_ia32_ls_mode(res, cmp_mode);
1891 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1892 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1893 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1897 assert(get_mode_size_bits(cmp_mode) == 32);
1898 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1899 set_ia32_commutative(res);
1903 set_ia32_pncode(res, pnc);
1904 // Matze: disabled for now, because the default collect_spills_walker
1905 // is not able to detect the mode of the spilled value
1906 // moreover, the lea optimize phase freely exchanges left/right
1907 // without updating the pnc
1908 //set_ia32_am_support(res, ia32_am_Source);
1911 /* determine the smallest switch case value */
1912 int switch_min = INT_MAX;
1913 const ir_edge_t *edge;
1914 ir_node *new_sel = transform_node(env, sel);
1916 foreach_out_edge(node, edge) {
1917 int pn = get_Proj_proj(get_edge_src_irn(edge));
1918 switch_min = pn < switch_min ? pn : switch_min;
1922 /* if smallest switch case is not 0 we need an additional sub */
1923 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1924 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1925 add_ia32_am_offs_int(res, -switch_min);
1926 set_ia32_am_flavour(res, ia32_am_OB);
1927 set_ia32_am_support(res, ia32_am_Source);
1928 set_ia32_op_type(res, ia32_AddrModeS);
1931 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1932 set_ia32_pncode(res, get_Cond_defaultProj(node));
1935 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1942 * Transforms a CopyB node.
1944 * @param env The transformation environment
1945 * @return The transformed node.
1947 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1948 ir_node *res = NULL;
1949 ir_graph *irg = env->irg;
1950 dbg_info *dbgi = get_irn_dbg_info(node);
1951 ir_node *block = transform_node(env, get_nodes_block(node));
1952 ir_node *src = get_CopyB_src(node);
1953 ir_node *new_src = transform_node(env, src);
1954 ir_node *dst = get_CopyB_dst(node);
1955 ir_node *new_dst = transform_node(env, dst);
1956 ir_node *mem = get_CopyB_mem(node);
1957 ir_node *new_mem = transform_node(env, mem);
1958 int size = get_type_size_bytes(get_CopyB_type(node));
1959 ir_mode *dst_mode = get_irn_mode(dst);
1960 ir_mode *src_mode = get_irn_mode(src);
1964 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1965 /* then we need the size explicitly in ECX. */
1966 if (size >= 32 * 4) {
1967 rem = size & 0x3; /* size % 4 */
1970 res = new_rd_ia32_Const(dbgi, irg, block);
1971 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1972 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1974 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1975 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1977 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1978 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1979 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1980 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1981 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1984 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1985 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1987 /* ok: now attach Proj's because movsd will destroy esi and edi */
1988 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1989 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1990 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1993 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2001 * Transforms a Mux node into CMov.
2003 * @param env The transformation environment
2004 * @return The transformed node.
2006 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
2007 ir_node *new_op = new_rd_ia32_CMov(env->dbgi, env->irg, env->block, \
2008 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
2010 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2016 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2017 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2018 ir_node *psi_default);
2021 * Transforms a Psi node into CMov.
2023 * @param env The transformation environment
2024 * @return The transformed node.
2026 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2027 ia32_code_gen_t *cg = env->cg;
2028 ir_graph *irg = env->irg;
2029 dbg_info *dbgi = get_irn_dbg_info(node);
2030 ir_mode *mode = get_irn_mode(node);
2031 ir_node *block = transform_node(env, get_nodes_block(node));
2032 ir_node *cmp_proj = get_Mux_sel(node);
2033 ir_node *psi_true = get_Psi_val(node, 0);
2034 ir_node *psi_default = get_Psi_default(node);
2035 ir_node *new_psi_true = transform_node(env, psi_true);
2036 ir_node *new_psi_default = transform_node(env, psi_default);
2037 ir_node *noreg = ia32_new_NoReg_gp(cg);
2038 ir_node *nomem = new_rd_NoMem(irg);
2039 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2040 ir_node *new_cmp_a, *new_cmp_b;
2044 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2046 cmp = get_Proj_pred(cmp_proj);
2047 cmp_a = get_Cmp_left(cmp);
2048 cmp_b = get_Cmp_right(cmp);
2049 cmp_mode = get_irn_mode(cmp_a);
2050 new_cmp_a = transform_node(env, cmp_a);
2051 new_cmp_b = transform_node(env, cmp_b);
2053 pnc = get_Proj_proj(cmp_proj);
2054 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2055 pnc |= ia32_pn_Cmp_Unsigned;
2058 if (mode_is_float(mode)) {
2059 /* floating point psi */
2062 /* 1st case: compare operands are float too */
2064 /* psi(cmp(a, b), t, f) can be done as: */
2065 /* tmp = cmp a, b */
2066 /* tmp2 = t and tmp */
2067 /* tmp3 = f and not tmp */
2068 /* res = tmp2 or tmp3 */
2070 /* in case the compare operands are int, we move them into xmm register */
2071 if (! mode_is_float(get_irn_mode(cmp_a))) {
2072 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2073 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2075 pnc |= 8; /* transform integer compare to fp compare */
2078 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2079 set_ia32_pncode(new_op, pnc);
2080 set_ia32_am_support(new_op, ia32_am_Source);
2081 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2083 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2084 set_ia32_am_support(and1, ia32_am_None);
2085 set_ia32_commutative(and1);
2086 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2088 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2089 set_ia32_am_support(and2, ia32_am_None);
2090 set_ia32_commutative(and2);
2091 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2093 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2094 set_ia32_am_support(new_op, ia32_am_None);
2095 set_ia32_commutative(new_op);
2096 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2100 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2101 set_ia32_pncode(new_op, pnc);
2102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2107 construct_binop_func *set_func = NULL;
2108 cmov_func_t *cmov_func = NULL;
2110 if (mode_is_float(get_irn_mode(cmp_a))) {
2111 /* 1st case: compare operands are floats */
2116 set_func = new_rd_ia32_xCmpSet;
2117 cmov_func = new_rd_ia32_xCmpCMov;
2121 set_func = new_rd_ia32_vfCmpSet;
2122 cmov_func = new_rd_ia32_vfCmpCMov;
2125 pnc &= ~0x8; /* fp compare -> int compare */
2128 /* 2nd case: compare operand are integer too */
2129 set_func = new_rd_ia32_CmpSet;
2130 cmov_func = new_rd_ia32_CmpCMov;
2133 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2134 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2135 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2136 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2137 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2138 set_ia32_pncode(new_op, pnc);
2140 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2141 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2142 /* we invert condition and set default to 0 */
2143 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2144 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2147 /* otherwise: use CMOVcc */
2148 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2149 set_ia32_pncode(new_op, pnc);
2152 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2155 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2156 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2157 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2158 set_ia32_pncode(new_op, pnc);
2159 set_ia32_am_support(new_op, ia32_am_Source);
2161 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2162 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2163 /* we invert condition and set default to 0 */
2164 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2165 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2166 set_ia32_am_support(new_op, ia32_am_Source);
2169 /* otherwise: use CMOVcc */
2170 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2171 set_ia32_pncode(new_op, pnc);
2172 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2182 * Following conversion rules apply:
2186 * 1) n bit -> m bit n > m (downscale)
2188 * 2) n bit -> m bit n == m (sign change)
2190 * 3) n bit -> m bit n < m (upscale)
2191 * a) source is signed: movsx
2192 * b) source is unsigned: and with lower bits sets
2196 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2200 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2204 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2205 * x87 is mode_E internally, conversions happen only at load and store
2206 * in non-strict semantic
2210 * Create a conversion from x87 state register to general purpose.
2212 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2213 ia32_code_gen_t *cg = env->cg;
2214 ir_graph *irg = env->irg;
2215 dbg_info *dbgi = get_irn_dbg_info(node);
2216 ir_node *block = transform_node(env, get_nodes_block(node));
2217 ir_node *noreg = ia32_new_NoReg_gp(cg);
2218 ir_node *op = get_Conv_op(node);
2219 ir_node *new_op = transform_node(env, op);
2220 ir_node *fist, *load;
2221 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2224 fist = new_rd_ia32_vfist(dbgi, irg, block,
2225 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2227 set_ia32_use_frame(fist);
2228 set_ia32_am_support(fist, ia32_am_Dest);
2229 set_ia32_op_type(fist, ia32_AddrModeD);
2230 set_ia32_am_flavour(fist, ia32_am_B);
2231 set_ia32_ls_mode(fist, mode_Iu);
2232 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2235 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2237 set_ia32_use_frame(load);
2238 set_ia32_am_support(load, ia32_am_Source);
2239 set_ia32_op_type(load, ia32_AddrModeS);
2240 set_ia32_am_flavour(load, ia32_am_B);
2241 set_ia32_ls_mode(load, mode_Iu);
2242 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2244 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2248 * Create a conversion from general purpose to x87 register
2250 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2252 ia32_code_gen_t *cg = env->cg;
2254 ir_graph *irg = env->irg;
2255 dbg_info *dbgi = get_irn_dbg_info(node);
2256 ir_node *block = transform_node(env, get_nodes_block(node));
2257 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2258 ir_node *nomem = new_NoMem();
2259 ir_node *op = get_Conv_op(node);
2260 ir_node *new_op = transform_node(env, op);
2261 ir_node *fild, *store;
2264 /* first convert to 32 bit if necessary */
2265 src_bits = get_mode_size_bits(src_mode);
2266 if (src_bits == 8) {
2267 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2268 set_ia32_am_support(new_op, ia32_am_Source);
2269 set_ia32_ls_mode(new_op, src_mode);
2270 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2271 } else if (src_bits < 32) {
2272 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2273 set_ia32_am_support(new_op, ia32_am_Source);
2274 set_ia32_ls_mode(new_op, src_mode);
2275 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2279 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2281 set_ia32_use_frame(store);
2282 set_ia32_am_support(store, ia32_am_Dest);
2283 set_ia32_op_type(store, ia32_AddrModeD);
2284 set_ia32_am_flavour(store, ia32_am_OB);
2285 set_ia32_ls_mode(store, mode_Iu);
2288 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2290 set_ia32_use_frame(fild);
2291 set_ia32_am_support(fild, ia32_am_Source);
2292 set_ia32_op_type(fild, ia32_AddrModeS);
2293 set_ia32_am_flavour(fild, ia32_am_OB);
2294 set_ia32_ls_mode(fild, mode_Iu);
2296 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2300 * Transforms a Conv node.
2302 * @param env The transformation environment
2303 * @return The created ia32 Conv node
2305 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2306 ir_graph *irg = env->irg;
2307 dbg_info *dbgi = get_irn_dbg_info(node);
2308 ir_node *op = get_Conv_op(node);
2309 ir_mode *src_mode = get_irn_mode(op);
2310 ir_mode *tgt_mode = get_irn_mode(node);
2311 int src_bits = get_mode_size_bits(src_mode);
2312 int tgt_bits = get_mode_size_bits(tgt_mode);
2313 ir_node *block = transform_node(env, get_nodes_block(node));
2315 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2316 ir_node *nomem = new_rd_NoMem(irg);
2317 ir_node *new_op = transform_node(env, op);
2319 if (src_mode == tgt_mode) {
2320 if (get_Conv_strict(node)) {
2321 if (USE_SSE2(env->cg)) {
2322 /* when we are in SSE mode, we can kill all strict no-op conversion */
2326 /* this should be optimized already, but who knows... */
2327 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2328 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2333 if (mode_is_float(src_mode)) {
2334 /* we convert from float ... */
2335 if (mode_is_float(tgt_mode)) {
2337 if (USE_SSE2(env->cg)) {
2338 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2339 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2340 set_ia32_ls_mode(res, tgt_mode);
2342 // Matze: TODO what about strict convs?
2343 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2344 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2349 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2350 if (USE_SSE2(env->cg)) {
2351 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2352 set_ia32_ls_mode(res, src_mode);
2354 return gen_x87_fp_to_gp(env, node);
2358 /* we convert from int ... */
2359 if (mode_is_float(tgt_mode)) {
2362 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2363 if (USE_SSE2(env->cg)) {
2364 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2365 set_ia32_ls_mode(res, tgt_mode);
2366 if(src_bits == 32) {
2367 set_ia32_am_support(res, ia32_am_Source);
2370 return gen_x87_gp_to_fp(env, node, src_mode);
2374 ir_mode *smaller_mode;
2377 if (src_bits == tgt_bits) {
2378 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2382 if(src_bits < tgt_bits) {
2383 smaller_mode = src_mode;
2384 smaller_bits = src_bits;
2386 smaller_mode = tgt_mode;
2387 smaller_bits = tgt_bits;
2390 // The following is not correct, we can't change the mode,
2391 // maybe others are using the load too
2392 // better move this to a separate phase!
2395 if(is_Proj(new_op)) {
2396 /* load operations do already sign/zero extend, so we have
2397 * nothing left to do */
2398 ir_node *pred = get_Proj_pred(new_op);
2399 if(is_ia32_Load(pred)) {
2400 set_ia32_ls_mode(pred, smaller_mode);
2406 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2407 if (smaller_bits == 8) {
2408 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2409 set_ia32_ls_mode(res, smaller_mode);
2411 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2412 set_ia32_ls_mode(res, smaller_mode);
2414 set_ia32_am_support(res, ia32_am_Source);
2418 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2425 /********************************************
2428 * | |__ ___ _ __ ___ __| | ___ ___
2429 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2430 * | |_) | __/ | | | (_) | (_| | __/\__ \
2431 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2433 ********************************************/
2435 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2436 ir_node *new_op = NULL;
2437 ir_graph *irg = env->irg;
2438 dbg_info *dbgi = get_irn_dbg_info(node);
2439 ir_node *block = transform_node(env, get_nodes_block(node));
2440 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2441 ir_node *nomem = new_rd_NoMem(env->irg);
2442 ir_node *ptr = get_irn_n(node, 0);
2443 ir_node *new_ptr = transform_node(env, ptr);
2444 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2445 ir_mode *load_mode = get_irn_mode(node);
2449 if (mode_is_float(load_mode)) {
2451 if (USE_SSE2(env->cg)) {
2452 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2453 pn_res = pn_ia32_xLoad_res;
2454 proj_mode = mode_xmm;
2456 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2457 pn_res = pn_ia32_vfld_res;
2458 proj_mode = mode_vfp;
2461 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2462 proj_mode = mode_Iu;
2463 pn_res = pn_ia32_Load_res;
2466 set_ia32_frame_ent(new_op, ent);
2467 set_ia32_use_frame(new_op);
2469 set_ia32_am_support(new_op, ia32_am_Source);
2470 set_ia32_op_type(new_op, ia32_AddrModeS);
2471 set_ia32_am_flavour(new_op, ia32_am_B);
2472 set_ia32_ls_mode(new_op, load_mode);
2473 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2475 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2477 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2481 * Transforms a FrameAddr into an ia32 Add.
2483 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2484 ir_graph *irg = env->irg;
2485 dbg_info *dbgi = get_irn_dbg_info(node);
2486 ir_node *block = transform_node(env, get_nodes_block(node));
2487 ir_node *op = get_irn_n(node, 0);
2488 ir_node *new_op = transform_node(env, op);
2490 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2492 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2493 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2494 set_ia32_am_support(res, ia32_am_Full);
2495 set_ia32_use_frame(res);
2496 set_ia32_am_flavour(res, ia32_am_OB);
2498 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2504 * Transforms a FrameLoad into an ia32 Load.
2506 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2507 ir_node *new_op = NULL;
2508 ir_graph *irg = env->irg;
2509 dbg_info *dbgi = get_irn_dbg_info(node);
2510 ir_node *block = transform_node(env, get_nodes_block(node));
2511 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2512 ir_node *mem = get_irn_n(node, 0);
2513 ir_node *ptr = get_irn_n(node, 1);
2514 ir_node *new_mem = transform_node(env, mem);
2515 ir_node *new_ptr = transform_node(env, ptr);
2516 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2517 ir_mode *mode = get_type_mode(get_entity_type(ent));
2518 ir_node *projs[pn_Load_max];
2520 ia32_collect_Projs(node, projs, pn_Load_max);
2522 if (mode_is_float(mode)) {
2524 if (USE_SSE2(env->cg)) {
2525 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2528 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2532 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2535 set_ia32_frame_ent(new_op, ent);
2536 set_ia32_use_frame(new_op);
2538 set_ia32_am_support(new_op, ia32_am_Source);
2539 set_ia32_op_type(new_op, ia32_AddrModeS);
2540 set_ia32_am_flavour(new_op, ia32_am_B);
2541 set_ia32_ls_mode(new_op, mode);
2543 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2550 * Transforms a FrameStore into an ia32 Store.
2552 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2553 ir_node *new_op = NULL;
2554 ir_graph *irg = env->irg;
2555 dbg_info *dbgi = get_irn_dbg_info(node);
2556 ir_node *block = transform_node(env, get_nodes_block(node));
2557 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2558 ir_node *mem = get_irn_n(node, 0);
2559 ir_node *ptr = get_irn_n(node, 1);
2560 ir_node *val = get_irn_n(node, 2);
2561 ir_node *new_mem = transform_node(env, mem);
2562 ir_node *new_ptr = transform_node(env, ptr);
2563 ir_node *new_val = transform_node(env, val);
2564 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2565 ir_mode *mode = get_irn_mode(val);
2567 if (mode_is_float(mode)) {
2569 if (USE_SSE2(env->cg)) {
2570 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2572 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2574 } else if (get_mode_size_bits(mode) == 8) {
2575 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2577 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2580 set_ia32_frame_ent(new_op, ent);
2581 set_ia32_use_frame(new_op);
2583 set_ia32_am_support(new_op, ia32_am_Dest);
2584 set_ia32_op_type(new_op, ia32_AddrModeD);
2585 set_ia32_am_flavour(new_op, ia32_am_B);
2586 set_ia32_ls_mode(new_op, mode);
2588 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2594 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2596 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2597 ir_graph *irg = env->irg;
2600 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2601 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2602 ir_entity *ent = get_irg_entity(irg);
2603 ir_type *tp = get_entity_type(ent);
2606 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2607 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2609 int pn_ret_val, pn_ret_mem, arity, i;
2611 assert(ret_val != NULL);
2612 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2613 return duplicate_node(env, node);
2616 res_type = get_method_res_type(tp, 0);
2618 if (!is_Primitive_type(res_type)) {
2619 return duplicate_node(env, node);
2622 mode = get_type_mode(res_type);
2623 if (!mode_is_float(mode)) {
2624 return duplicate_node(env, node);
2627 assert(get_method_n_ress(tp) == 1);
2629 pn_ret_val = get_Proj_proj(ret_val);
2630 pn_ret_mem = get_Proj_proj(ret_mem);
2632 /* get the Barrier */
2633 barrier = get_Proj_pred(ret_val);
2635 /* get result input of the Barrier */
2636 ret_val = get_irn_n(barrier, pn_ret_val);
2637 new_ret_val = transform_node(env, ret_val);
2639 /* get memory input of the Barrier */
2640 ret_mem = get_irn_n(barrier, pn_ret_mem);
2641 new_ret_mem = transform_node(env, ret_mem);
2643 frame = get_irg_frame(irg);
2645 dbgi = get_irn_dbg_info(barrier);
2646 block = transform_node(env, get_nodes_block(barrier));
2648 /* store xmm0 onto stack */
2649 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, new_ret_val, new_ret_mem);
2650 set_ia32_ls_mode(sse_store, mode);
2651 set_ia32_op_type(sse_store, ia32_AddrModeD);
2652 set_ia32_use_frame(sse_store);
2653 set_ia32_am_flavour(sse_store, ia32_am_B);
2654 set_ia32_am_support(sse_store, ia32_am_Dest);
2657 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, sse_store);
2658 set_ia32_ls_mode(fld, mode);
2659 set_ia32_op_type(fld, ia32_AddrModeS);
2660 set_ia32_use_frame(fld);
2661 set_ia32_am_flavour(fld, ia32_am_B);
2662 set_ia32_am_support(fld, ia32_am_Source);
2664 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2665 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2666 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2668 /* create a new barrier */
2669 arity = get_irn_arity(barrier);
2670 in = alloca(arity * sizeof(in[0]));
2671 for(i = 0; i < arity; ++i) {
2673 if(i == pn_ret_val) {
2675 } else if(i == pn_ret_mem) {
2678 ir_node *in = get_irn_n(barrier, i);
2679 new_in = transform_node(env, in);
2684 new_barrier = new_ir_node(dbgi, irg, block,
2685 get_irn_op(barrier), get_irn_mode(barrier),
2687 copy_node_attr(barrier, new_barrier);
2688 duplicate_deps(env, barrier, new_barrier);
2689 set_new_node(barrier, new_barrier);
2690 mark_irn_visited(barrier);
2692 /* transform normally */
2693 return duplicate_node(env, node);
2697 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2699 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2701 ir_graph *irg = env->irg;
2702 dbg_info *dbgi = get_irn_dbg_info(node);
2703 ir_node *block = transform_node(env, get_nodes_block(node));
2704 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2705 ir_node *new_sz = transform_node(env, sz);
2706 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2707 ir_node *new_sp = transform_node(env, sp);
2708 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2709 ir_node *nomem = new_NoMem();
2711 /* ia32 stack grows in reverse direction, make a SubSP */
2712 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2713 set_ia32_am_support(new_op, ia32_am_Source);
2714 fold_immediate(env, new_op, 2, 3);
2716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2722 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2724 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2726 ir_graph *irg = env->irg;
2727 dbg_info *dbgi = get_irn_dbg_info(node);
2728 ir_node *block = transform_node(env, get_nodes_block(node));
2729 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2730 ir_node *new_sz = transform_node(env, sz);
2731 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2732 ir_node *new_sp = transform_node(env, sp);
2733 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2734 ir_node *nomem = new_NoMem();
2736 /* ia32 stack grows in reverse direction, make an AddSP */
2737 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2738 set_ia32_am_support(new_op, ia32_am_Source);
2739 fold_immediate(env, new_op, 2, 3);
2741 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2747 * This function just sets the register for the Unknown node
2748 * as this is not done during register allocation because Unknown
2749 * is an "ignore" node.
2751 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2752 ir_mode *mode = get_irn_mode(node);
2754 if (mode_is_float(mode)) {
2755 if (USE_SSE2(env->cg))
2756 return ia32_new_Unknown_xmm(env->cg);
2758 return ia32_new_Unknown_vfp(env->cg);
2759 } else if (mode_needs_gp_reg(mode)) {
2760 return ia32_new_Unknown_gp(env->cg);
2762 assert(0 && "unsupported Unknown-Mode");
2769 * Change some phi modes
2771 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2772 ir_graph *irg = env->irg;
2773 dbg_info *dbgi = get_irn_dbg_info(node);
2774 ir_mode *mode = get_irn_mode(node);
2775 ir_node *block = transform_node(env, get_nodes_block(node));
2779 if(mode_needs_gp_reg(mode)) {
2780 // we shouldn't have any 64bit stuff around anymore
2781 assert(get_mode_size_bits(mode) <= 32);
2782 // all integer operations are on 32bit registers now
2784 } else if(mode_is_float(mode)) {
2785 assert(mode == mode_D || mode == mode_F);
2786 if (USE_SSE2(env->cg)) {
2793 /* phi nodes allow loops, so we use the old arguments for now
2794 * and fix this later */
2795 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
2796 get_irn_in(node) + 1);
2797 copy_node_attr(node, phi);
2798 duplicate_deps(env, node, phi);
2800 set_new_node(node, phi);
2802 /* put the preds in the worklist */
2803 arity = get_irn_arity(node);
2804 for(i = 0; i < arity; ++i) {
2805 ir_node *pred = get_irn_n(node, i);
2806 pdeq_putr(env->worklist, pred);
2812 /**********************************************************************
2815 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2816 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2817 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2818 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2820 **********************************************************************/
2822 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2824 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2827 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2828 ir_node *val, ir_node *mem);
2831 * Transforms a lowered Load into a "real" one.
2833 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2834 ir_graph *irg = env->irg;
2835 dbg_info *dbgi = get_irn_dbg_info(node);
2836 ir_node *block = transform_node(env, get_nodes_block(node));
2837 ir_mode *mode = get_ia32_ls_mode(node);
2839 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2840 ir_node *ptr = get_irn_n(node, 0);
2841 ir_node *mem = get_irn_n(node, 1);
2842 ir_node *new_ptr = transform_node(env, ptr);
2843 ir_node *new_mem = transform_node(env, mem);
2846 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2847 lowering we have x87 nodes, so we need to enforce simulation.
2849 if (mode_is_float(mode)) {
2851 if (fp_unit == fp_x87)
2855 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
2857 set_ia32_am_support(new_op, ia32_am_Source);
2858 set_ia32_op_type(new_op, ia32_AddrModeS);
2859 set_ia32_am_flavour(new_op, ia32_am_OB);
2860 set_ia32_am_offs_int(new_op, 0);
2861 set_ia32_am_scale(new_op, 1);
2862 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2863 if(is_ia32_am_sc_sign(node))
2864 set_ia32_am_sc_sign(new_op);
2865 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2866 if(is_ia32_use_frame(node)) {
2867 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2868 set_ia32_use_frame(new_op);
2871 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2877 * Transforms a lowered Store into a "real" one.
2879 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2880 ir_graph *irg = env->irg;
2881 dbg_info *dbgi = get_irn_dbg_info(node);
2882 ir_node *block = transform_node(env, get_nodes_block(node));
2883 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2884 ir_mode *mode = get_ia32_ls_mode(node);
2887 ia32_am_flavour_t am_flav = ia32_B;
2888 ir_node *ptr = get_irn_n(node, 0);
2889 ir_node *val = get_irn_n(node, 1);
2890 ir_node *mem = get_irn_n(node, 2);
2891 ir_node *new_ptr = transform_node(env, ptr);
2892 ir_node *new_val = transform_node(env, val);
2893 ir_node *new_mem = transform_node(env, mem);
2896 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2897 lowering we have x87 nodes, so we need to enforce simulation.
2899 if (mode_is_float(mode)) {
2901 if (fp_unit == fp_x87)
2905 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2907 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2909 add_ia32_am_offs_int(new_op, am_offs);
2912 set_ia32_am_support(new_op, ia32_am_Dest);
2913 set_ia32_op_type(new_op, ia32_AddrModeD);
2914 set_ia32_am_flavour(new_op, am_flav);
2915 set_ia32_ls_mode(new_op, mode);
2916 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2917 set_ia32_use_frame(new_op);
2919 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2926 * Transforms an ia32_l_XXX into a "real" XXX node
2928 * @param env The transformation environment
2929 * @return the created ia32 XXX node
2931 #define GEN_LOWERED_OP(op) \
2932 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2933 ir_mode *mode = get_irn_mode(node); \
2934 if (mode_is_float(mode)) \
2936 return gen_binop(env, node, get_binop_left(node), \
2937 get_binop_right(node), new_rd_ia32_##op); \
2940 #define GEN_LOWERED_x87_OP(op) \
2941 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2943 FORCE_x87(env->cg); \
2944 new_op = gen_binop_float(env, node, get_binop_left(node), \
2945 get_binop_right(node), new_rd_ia32_##op); \
2949 #define GEN_LOWERED_UNOP(op) \
2950 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2951 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2954 #define GEN_LOWERED_SHIFT_OP(op) \
2955 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2956 return gen_shift_binop(env, node, get_binop_left(node), \
2957 get_binop_right(node), new_rd_ia32_##op); \
2960 #define GEN_LOWERED_LOAD(op, fp_unit) \
2961 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2962 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2965 #define GEN_LOWERED_STORE(op, fp_unit) \
2966 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2967 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2974 GEN_LOWERED_OP(IMul)
2976 GEN_LOWERED_x87_OP(vfprem)
2977 GEN_LOWERED_x87_OP(vfmul)
2978 GEN_LOWERED_x87_OP(vfsub)
2980 GEN_LOWERED_UNOP(Neg)
2982 GEN_LOWERED_LOAD(vfild, fp_x87)
2983 GEN_LOWERED_LOAD(Load, fp_none)
2984 /*GEN_LOWERED_STORE(vfist, fp_x87)
2987 GEN_LOWERED_STORE(Store, fp_none)
2989 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2990 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2991 ir_graph *irg = env->irg;
2992 dbg_info *dbgi = get_irn_dbg_info(node);
2993 ir_node *block = transform_node(env, get_nodes_block(node));
2994 ir_node *left = get_binop_left(node);
2995 ir_node *right = get_binop_right(node);
2996 ir_node *new_left = transform_node(env, left);
2997 ir_node *new_right = transform_node(env, right);
3000 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3001 clear_ia32_commutative(vfdiv);
3002 set_ia32_am_support(vfdiv, ia32_am_Source);
3003 fold_immediate(env, vfdiv, 2, 3);
3005 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3013 * Transforms a l_MulS into a "real" MulS node.
3015 * @param env The transformation environment
3016 * @return the created ia32 Mul node
3018 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3019 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3020 ir_graph *irg = env->irg;
3021 dbg_info *dbgi = get_irn_dbg_info(node);
3022 ir_node *block = transform_node(env, get_nodes_block(node));
3023 ir_node *left = get_binop_left(node);
3024 ir_node *right = get_binop_right(node);
3025 ir_node *new_left = transform_node(env, left);
3026 ir_node *new_right = transform_node(env, right);
3029 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3030 /* and then skip the result Proj, because all needed Projs are already there. */
3031 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3032 clear_ia32_commutative(muls);
3033 set_ia32_am_support(muls, ia32_am_Source);
3034 fold_immediate(env, muls, 2, 3);
3036 /* check if EAX and EDX proj exist, add missing one */
3037 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3038 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3039 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3041 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3046 GEN_LOWERED_SHIFT_OP(Shl)
3047 GEN_LOWERED_SHIFT_OP(Shr)
3048 GEN_LOWERED_SHIFT_OP(Sar)
3051 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3052 * op1 - target to be shifted
3053 * op2 - contains bits to be shifted into target
3055 * Only op3 can be an immediate.
3057 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3058 ir_node *op1, ir_node *op2,
3060 ir_node *new_op = NULL;
3061 ir_graph *irg = env->irg;
3062 dbg_info *dbgi = get_irn_dbg_info(node);
3063 ir_node *block = transform_node(env, get_nodes_block(node));
3064 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3065 ir_node *nomem = new_NoMem();
3067 ir_node *new_op1 = transform_node(env, op1);
3068 ir_node *new_op2 = transform_node(env, op2);
3069 ir_node *new_count = transform_node(env, count);
3072 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3074 /* Check if immediate optimization is on and */
3075 /* if it's an operation with immediate. */
3076 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3078 /* Limit imm_op within range imm8 */
3080 tv = get_ia32_Immop_tarval(imm_op);
3083 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3084 set_ia32_Immop_tarval(imm_op, tv);
3091 /* integer operations */
3093 /* This is ShiftD with const */
3094 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3096 if (is_ia32_l_ShlD(node))
3097 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3098 new_op1, new_op2, noreg, nomem);
3100 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3101 new_op1, new_op2, noreg, nomem);
3102 copy_ia32_Immop_attr(new_op, imm_op);
3105 /* This is a normal ShiftD */
3106 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3107 if (is_ia32_l_ShlD(node))
3108 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3109 new_op1, new_op2, new_count, nomem);
3111 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3112 new_op1, new_op2, new_count, nomem);
3115 /* set AM support */
3116 // Matze: node has unsupported format (6inputs)
3117 //set_ia32_am_support(new_op, ia32_am_Dest);
3119 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3121 set_ia32_emit_cl(new_op);
3126 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3127 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3128 get_irn_n(node, 1), get_irn_n(node, 2));
3131 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3132 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3133 get_irn_n(node, 1), get_irn_n(node, 2));
3137 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3139 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3140 ia32_code_gen_t *cg = env->cg;
3141 ir_node *res = NULL;
3142 ir_graph *irg = env->irg;
3143 dbg_info *dbgi = get_irn_dbg_info(node);
3144 ir_node *block = transform_node(env, get_nodes_block(node));
3145 ir_node *ptr = get_irn_n(node, 0);
3146 ir_node *val = get_irn_n(node, 1);
3147 ir_node *new_val = transform_node(env, val);
3148 ir_node *mem = get_irn_n(node, 2);
3149 ir_node *noreg, *new_ptr, *new_mem;
3155 noreg = ia32_new_NoReg_gp(cg);
3156 new_mem = transform_node(env, mem);
3157 new_ptr = transform_node(env, ptr);
3159 /* Store x87 -> MEM */
3160 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3161 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3162 set_ia32_use_frame(res);
3163 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3164 set_ia32_am_support(res, ia32_am_Dest);
3165 set_ia32_am_flavour(res, ia32_B);
3166 set_ia32_op_type(res, ia32_AddrModeD);
3168 /* Load MEM -> SSE */
3169 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3170 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3171 set_ia32_use_frame(res);
3172 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3173 set_ia32_am_support(res, ia32_am_Source);
3174 set_ia32_am_flavour(res, ia32_B);
3175 set_ia32_op_type(res, ia32_AddrModeS);
3176 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3182 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3184 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3185 ia32_code_gen_t *cg = env->cg;
3186 ir_graph *irg = env->irg;
3187 dbg_info *dbgi = get_irn_dbg_info(node);
3188 ir_node *block = transform_node(env, get_nodes_block(node));
3189 ir_node *res = NULL;
3190 ir_node *ptr = get_irn_n(node, 0);
3191 ir_node *val = get_irn_n(node, 1);
3192 ir_node *mem = get_irn_n(node, 2);
3193 ir_entity *fent = get_ia32_frame_ent(node);
3194 ir_mode *lsmode = get_ia32_ls_mode(node);
3195 ir_node *new_val = transform_node(env, val);
3196 ir_node *noreg, *new_ptr, *new_mem;
3199 if (!USE_SSE2(cg)) {
3200 /* SSE unit is not used -> skip this node. */
3204 noreg = ia32_new_NoReg_gp(cg);
3205 new_val = transform_node(env, val);
3206 new_ptr = transform_node(env, ptr);
3207 new_mem = transform_node(env, mem);
3209 /* Store SSE -> MEM */
3210 if (is_ia32_xLoad(skip_Proj(new_val))) {
3211 ir_node *ld = skip_Proj(new_val);
3213 /* we can vfld the value directly into the fpu */
3214 fent = get_ia32_frame_ent(ld);
3215 ptr = get_irn_n(ld, 0);
3216 offs = get_ia32_am_offs_int(ld);
3218 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3219 set_ia32_frame_ent(res, fent);
3220 set_ia32_use_frame(res);
3221 set_ia32_ls_mode(res, lsmode);
3222 set_ia32_am_support(res, ia32_am_Dest);
3223 set_ia32_am_flavour(res, ia32_B);
3224 set_ia32_op_type(res, ia32_AddrModeD);
3228 /* Load MEM -> x87 */
3229 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3230 set_ia32_frame_ent(res, fent);
3231 set_ia32_use_frame(res);
3232 set_ia32_ls_mode(res, lsmode);
3233 add_ia32_am_offs_int(res, offs);
3234 set_ia32_am_support(res, ia32_am_Source);
3235 set_ia32_am_flavour(res, ia32_B);
3236 set_ia32_op_type(res, ia32_AddrModeS);
3237 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3242 /*********************************************************
3245 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3246 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3247 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3248 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3250 *********************************************************/
3253 * the BAD transformer.
3255 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3256 panic("No transform function for %+F available.\n", node);
3260 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3261 /* end has to be duplicated manually because we need a dynamic in array */
3262 ir_graph *irg = env->irg;
3263 dbg_info *dbgi = get_irn_dbg_info(node);
3264 ir_node *block = transform_node(env, get_nodes_block(node));
3268 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3269 copy_node_attr(node, new_end);
3270 duplicate_deps(env, node, new_end);
3272 set_irg_end(irg, new_end);
3273 set_new_node(new_end, new_end);
3275 /* transform preds */
3276 arity = get_irn_arity(node);
3277 for(i = 0; i < arity; ++i) {
3278 ir_node *in = get_irn_n(node, i);
3279 ir_node *new_in = transform_node(env, in);
3281 add_End_keepalive(new_end, new_in);
3287 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3288 ir_graph *irg = env->irg;
3289 dbg_info *dbgi = get_irn_dbg_info(node);
3290 ir_node *start_block = env->old_anchors[anchor_start_block];
3295 * We replace the ProjX from the start node with a jump,
3296 * so the startblock has no preds anymore now
3298 if(node == start_block) {
3299 return new_rd_Block(dbgi, irg, 0, NULL);
3302 /* we use the old blocks for now, because jumps allow cycles in the graph
3303 * we have to fix this later */
3304 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3305 get_irn_arity(node), get_irn_in(node) + 1);
3306 copy_node_attr(node, block);
3308 #ifdef DEBUG_libfirm
3309 block->node_nr = node->node_nr;
3311 set_new_node(node, block);
3313 /* put the preds in the worklist */
3314 arity = get_irn_arity(node);
3315 for(i = 0; i < arity; ++i) {
3316 ir_node *in = get_irn_n(node, i);
3317 pdeq_putr(env->worklist, in);
3323 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3324 ir_graph *irg = env->irg;
3325 ir_node *block = transform_node(env, get_nodes_block(node));
3326 dbg_info *dbgi = get_irn_dbg_info(node);
3327 ir_node *pred = get_Proj_pred(node);
3328 ir_node *new_pred = transform_node(env, pred);
3329 long proj = get_Proj_proj(node);
3331 if(proj == pn_be_AddSP_res) {
3332 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3333 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3335 } else if(proj == pn_be_AddSP_M) {
3336 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3340 return new_rd_Unknown(irg, get_irn_mode(node));
3343 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3344 ir_graph *irg = env->irg;
3345 ir_node *block = transform_node(env, get_nodes_block(node));
3346 dbg_info *dbgi = get_irn_dbg_info(node);
3347 ir_node *pred = get_Proj_pred(node);
3348 ir_node *new_pred = transform_node(env, pred);
3349 long proj = get_Proj_proj(node);
3351 if(proj == pn_be_SubSP_res) {
3352 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3353 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3355 } else if(proj == pn_be_SubSP_M) {
3356 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3360 return new_rd_Unknown(irg, get_irn_mode(node));
3363 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3364 ir_graph *irg = env->irg;
3365 ir_node *block = transform_node(env, get_nodes_block(node));
3366 dbg_info *dbgi = get_irn_dbg_info(node);
3367 ir_node *pred = get_Proj_pred(node);
3368 ir_node *new_pred = transform_node(env, pred);
3369 long proj = get_Proj_proj(node);
3371 /* renumber the proj */
3372 if(is_ia32_Load(new_pred)) {
3373 if(proj == pn_Load_res) {
3374 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3375 } else if(proj == pn_Load_M) {
3376 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3378 } else if(is_ia32_xLoad(new_pred)) {
3379 if(proj == pn_Load_res) {
3380 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3381 } else if(proj == pn_Load_M) {
3382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3384 } else if(is_ia32_vfld(new_pred)) {
3385 if(proj == pn_Load_res) {
3386 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3387 } else if(proj == pn_Load_M) {
3388 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3393 return new_rd_Unknown(irg, get_irn_mode(node));
3396 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3397 ir_graph *irg = env->irg;
3398 dbg_info *dbgi = get_irn_dbg_info(node);
3399 ir_node *block = transform_node(env, get_nodes_block(node));
3400 ir_mode *mode = get_irn_mode(node);
3402 ir_node *pred = get_Proj_pred(node);
3403 ir_node *new_pred = transform_node(env, pred);
3404 long proj = get_Proj_proj(node);
3406 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3408 switch(get_irn_opcode(pred)) {
3412 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3414 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3422 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3424 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3432 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3433 case pn_DivMod_res_div:
3434 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3435 case pn_DivMod_res_mod:
3436 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3446 return new_rd_Unknown(irg, mode);
3449 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3451 ir_graph *irg = env->irg;
3452 dbg_info *dbgi = get_irn_dbg_info(node);
3453 ir_node *block = transform_node(env, get_nodes_block(node));
3454 ir_mode *mode = get_irn_mode(node);
3456 ir_node *pred = get_Proj_pred(node);
3457 ir_node *new_pred = transform_node(env, pred);
3458 long proj = get_Proj_proj(node);
3461 case pn_CopyB_M_regular:
3462 if(is_ia32_CopyB_i(new_pred)) {
3463 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3465 } else if(is_ia32_CopyB(new_pred)) {
3466 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3475 return new_rd_Unknown(irg, mode);
3478 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3480 ir_graph *irg = env->irg;
3481 dbg_info *dbgi = get_irn_dbg_info(node);
3482 ir_node *block = transform_node(env, get_nodes_block(node));
3483 ir_mode *mode = get_irn_mode(node);
3485 ir_node *pred = get_Proj_pred(node);
3486 ir_node *new_pred = transform_node(env, pred);
3487 long proj = get_Proj_proj(node);
3490 case pn_ia32_l_vfdiv_M:
3491 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3492 case pn_ia32_l_vfdiv_res:
3493 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3498 return new_rd_Unknown(irg, mode);
3501 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3503 ir_graph *irg = env->irg;
3504 dbg_info *dbgi = get_irn_dbg_info(node);
3505 ir_node *block = transform_node(env, get_nodes_block(node));
3506 ir_mode *mode = get_irn_mode(node);
3508 ir_node *pred = get_Proj_pred(node);
3509 ir_node *new_pred = transform_node(env, pred);
3510 long proj = get_Proj_proj(node);
3514 if(is_ia32_xDiv(new_pred)) {
3515 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3517 } else if(is_ia32_vfdiv(new_pred)) {
3518 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3523 if(is_ia32_xDiv(new_pred)) {
3524 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3526 } else if(is_ia32_vfdiv(new_pred)) {
3527 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3536 return new_rd_Unknown(irg, mode);
3539 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3540 ir_graph *irg = env->irg;
3541 //dbg_info *dbgi = get_irn_dbg_info(node);
3542 dbg_info *dbgi = NULL;
3543 ir_node *block = transform_node(env, get_nodes_block(node));
3545 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3550 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3551 ir_graph *irg = env->irg;
3552 dbg_info *dbgi = get_irn_dbg_info(node);
3553 long proj = get_Proj_proj(node);
3554 ir_mode *mode = get_irn_mode(node);
3555 ir_node *block = transform_node(env, get_nodes_block(node));
3557 ir_node *call = get_Proj_pred(node);
3558 ir_node *new_call = transform_node(env, call);
3559 const arch_register_class_t *cls;
3561 /* The following is kinda tricky: If we're using SSE, then we have to
3562 * move the result value of the call in floating point registers to an
3563 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3564 * after the call, we have to make sure to correctly make the
3565 * MemProj and the result Proj use these 2 nodes
3567 if(proj == pn_be_Call_M_regular) {
3568 // get new node for result, are we doing the sse load/store hack?
3569 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3570 ir_node *call_res_new;
3571 ir_node *call_res_pred = NULL;
3573 if(call_res != NULL) {
3574 call_res_new = transform_node(env, call_res);
3575 call_res_pred = get_Proj_pred(call_res_new);
3578 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3579 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3581 assert(is_ia32_xLoad(call_res_pred));
3582 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3585 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3586 && USE_SSE2(env->cg)) {
3588 ir_node *frame = get_irg_frame(irg);
3589 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3591 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3593 const arch_register_class_t *cls;
3595 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3596 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3598 /* store st(0) onto stack */
3599 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3601 set_ia32_ls_mode(fstp, mode);
3602 set_ia32_op_type(fstp, ia32_AddrModeD);
3603 set_ia32_use_frame(fstp);
3604 set_ia32_am_flavour(fstp, ia32_am_B);
3605 set_ia32_am_support(fstp, ia32_am_Dest);
3607 /* load into SSE register */
3608 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3609 set_ia32_ls_mode(sse_load, mode);
3610 set_ia32_op_type(sse_load, ia32_AddrModeS);
3611 set_ia32_use_frame(sse_load);
3612 set_ia32_am_flavour(sse_load, ia32_am_B);
3613 set_ia32_am_support(sse_load, ia32_am_Source);
3615 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3617 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3619 /* get a Proj representing a caller save register */
3620 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3621 assert(is_Proj(p) && "Proj expected.");
3623 /* user of the the proj is the Keep */
3624 p = get_edge_src_irn(get_irn_out_edge_first(p));
3625 assert(be_is_Keep(p) && "Keep expected.");
3627 /* keep the result */
3628 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3629 keepin[0] = sse_load;
3630 be_new_Keep(cls, irg, block, 1, keepin);
3635 /* transform call modes */
3636 if (mode_is_data(mode)) {
3637 cls = arch_get_irn_reg_class(env->cg->arch_env, node, -1);
3641 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3644 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3645 ir_graph *irg = env->irg;
3646 dbg_info *dbgi = get_irn_dbg_info(node);
3647 ir_node *pred = get_Proj_pred(node);
3648 long proj = get_Proj_proj(node);
3650 if(is_Store(pred) || be_is_FrameStore(pred)) {
3651 if(proj == pn_Store_M) {
3652 return transform_node(env, pred);
3655 return new_r_Bad(irg);
3657 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3658 return gen_Proj_Load(env, node);
3659 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3660 return gen_Proj_DivMod(env, node);
3661 } else if(is_CopyB(pred)) {
3662 return gen_Proj_CopyB(env, node);
3663 } else if(is_Quot(pred)) {
3664 return gen_Proj_Quot(env, node);
3665 } else if(is_ia32_l_vfdiv(pred)) {
3666 return gen_Proj_l_vfdiv(env, node);
3667 } else if(be_is_SubSP(pred)) {
3668 return gen_Proj_be_SubSP(env, node);
3669 } else if(be_is_AddSP(pred)) {
3670 return gen_Proj_be_AddSP(env, node);
3671 } else if(be_is_Call(pred)) {
3672 return gen_Proj_be_Call(env, node);
3673 } else if(get_irn_op(pred) == op_Start) {
3674 if(proj == pn_Start_X_initial_exec) {
3675 ir_node *block = get_nodes_block(pred);
3678 block = transform_node(env, block);
3679 // we exchange the ProjX with a jump
3680 jump = new_rd_Jmp(dbgi, irg, block);
3681 ir_fprintf(stderr, "created jump: %+F\n", jump);
3684 if(node == env->old_anchors[anchor_tls]) {
3685 return gen_Proj_tls(env, node);
3688 ir_node *new_pred = transform_node(env, pred);
3689 ir_node *block = transform_node(env, get_nodes_block(node));
3690 ir_mode *mode = get_irn_mode(node);
3691 if (mode_needs_gp_reg(mode)) {
3692 return new_r_Proj(irg, block, new_pred, mode_Iu, get_Proj_proj(node));
3696 return duplicate_node(env, node);
3700 * Enters all transform functions into the generic pointer
3702 static void register_transformers(void) {
3703 ir_op *op_Max, *op_Min, *op_Mulh;
3705 /* first clear the generic function pointer for all ops */
3706 clear_irp_opcodes_generic_func();
3708 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3709 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3748 /* transform ops from intrinsic lowering */
3768 /* GEN(ia32_l_vfist); TODO */
3770 GEN(ia32_l_X87toSSE);
3771 GEN(ia32_l_SSEtoX87);
3776 /* we should never see these nodes */
3791 /* handle generic backend nodes */
3801 /* set the register for all Unknown nodes */
3804 op_Max = get_op_Max();
3807 op_Min = get_op_Min();
3810 op_Mulh = get_op_Mulh();
3818 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3822 int deps = get_irn_deps(old_node);
3824 for(i = 0; i < deps; ++i) {
3825 ir_node *dep = get_irn_dep(old_node, i);
3826 ir_node *new_dep = transform_node(env, dep);
3828 add_irn_dep(new_node, new_dep);
3832 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3834 ir_graph *irg = env->irg;
3835 dbg_info *dbgi = get_irn_dbg_info(node);
3836 ir_mode *mode = get_irn_mode(node);
3837 ir_op *op = get_irn_op(node);
3842 block = transform_node(env, get_nodes_block(node));
3844 arity = get_irn_arity(node);
3845 if(op->opar == oparity_dynamic) {
3846 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
3847 for(i = 0; i < arity; ++i) {
3848 ir_node *in = get_irn_n(node, i);
3849 in = transform_node(env, in);
3850 add_irn_n(new_node, in);
3853 ir_node **ins = alloca(arity * sizeof(ins[0]));
3854 for(i = 0; i < arity; ++i) {
3855 ir_node *in = get_irn_n(node, i);
3856 ins[i] = transform_node(env, in);
3859 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
3862 copy_node_attr(node, new_node);
3863 duplicate_deps(env, node, new_node);
3868 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3871 ir_op *op = get_irn_op(node);
3873 if(irn_visited(node)) {
3874 assert(get_new_node(node) != NULL);
3875 return get_new_node(node);
3878 mark_irn_visited(node);
3879 DEBUG_ONLY(set_new_node(node, NULL));
3881 if (op->ops.generic) {
3882 transform_func *transform = (transform_func *)op->ops.generic;
3884 new_node = (*transform)(env, node);
3885 assert(new_node != NULL);
3887 new_node = duplicate_node(env, node);
3889 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3891 set_new_node(node, new_node);
3892 mark_irn_visited(new_node);
3893 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3897 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3901 if(irn_visited(node))
3903 mark_irn_visited(node);
3905 assert(node_is_in_irgs_storage(env->irg, node));
3907 if(!is_Block(node)) {
3908 ir_node *block = get_nodes_block(node);
3909 ir_node *new_block = (ir_node*) get_irn_link(block);
3911 if(new_block != NULL) {
3912 set_nodes_block(node, new_block);
3916 fix_loops(env, block);
3919 arity = get_irn_arity(node);
3920 for(i = 0; i < arity; ++i) {
3921 ir_node *in = get_irn_n(node, i);
3922 ir_node *new = (ir_node*) get_irn_link(in);
3924 if(new != NULL && new != in) {
3925 set_irn_n(node, i, new);
3932 arity = get_irn_deps(node);
3933 for(i = 0; i < arity; ++i) {
3934 ir_node *in = get_irn_dep(node, i);
3935 ir_node *new = (ir_node*) get_irn_link(in);
3937 if(new != NULL && new != in) {
3938 set_irn_dep(node, i, new);
3946 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3951 *place = transform_node(env, *place);
3954 static void transform_nodes(ia32_code_gen_t *cg)
3957 ir_graph *irg = cg->irg;
3959 ia32_transform_env_t env;
3961 hook_dead_node_elim(irg, 1);
3963 inc_irg_visited(irg);
3967 env.visited = get_irg_visited(irg);
3968 env.worklist = new_pdeq();
3969 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3971 old_end = get_irg_end(irg);
3973 /* put all anchor nodes in the worklist */
3974 for(i = 0; i < anchor_max; ++i) {
3975 ir_node *anchor = irg->anchors[i];
3978 pdeq_putr(env.worklist, anchor);
3981 env.old_anchors[i] = anchor;
3982 // and set it to NULL to make sure we don't accidently use it
3983 irg->anchors[i] = NULL;
3986 // pre transform some anchors (so they are available in the other transform
3988 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3989 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3990 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3991 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3992 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3994 pre_transform_node(&cg->unknown_gp, &env);
3995 pre_transform_node(&cg->unknown_vfp, &env);
3996 pre_transform_node(&cg->unknown_xmm, &env);
3997 pre_transform_node(&cg->noreg_gp, &env);
3998 pre_transform_node(&cg->noreg_vfp, &env);
3999 pre_transform_node(&cg->noreg_xmm, &env);
4001 /* process worklist (this should transform all nodes in the graph) */
4002 while(!pdeq_empty(env.worklist)) {
4003 ir_node *node = pdeq_getl(env.worklist);
4004 transform_node(&env, node);
4007 /* fix loops and set new anchors*/
4008 inc_irg_visited(irg);
4009 for(i = 0; i < anchor_max; ++i) {
4010 ir_node *anchor = env.old_anchors[i];
4014 anchor = get_irn_link(anchor);
4015 fix_loops(&env, anchor);
4016 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4017 irg->anchors[i] = anchor;
4020 del_pdeq(env.worklist);
4022 hook_dead_node_elim(irg, 0);
4025 void ia32_transform_graph(ia32_code_gen_t *cg)
4027 ir_graph *irg = cg->irg;
4028 be_irg_t *birg = cg->birg;
4029 ir_graph *old_current_ir_graph = current_ir_graph;
4030 int old_interprocedural_view = get_interprocedural_view();
4031 struct obstack *old_obst = NULL;
4032 struct obstack *new_obst = NULL;
4034 current_ir_graph = irg;
4035 set_interprocedural_view(0);
4036 register_transformers();
4038 /* most analysis info is wrong after transformation */
4039 free_callee_info(irg);
4041 irg->outs_state = outs_none;
4043 free_loop_information(irg);
4044 set_irg_doms_inconsistent(irg);
4045 be_invalidate_liveness(birg);
4046 be_invalidate_dom_front(birg);
4048 /* create a new obstack */
4049 old_obst = irg->obst;
4050 new_obst = xmalloc(sizeof(*new_obst));
4051 obstack_init(new_obst);
4052 irg->obst = new_obst;
4053 irg->last_node_idx = 0;
4055 /* create new value table for CSE */
4056 del_identities(irg->value_table);
4057 irg->value_table = new_identities();
4059 /* do the main transformation */
4060 transform_nodes(cg);
4062 /* we don't want the globals anchor anymore */
4063 set_irg_globals(irg, new_r_Bad(irg));
4065 /* free the old obstack */
4066 obstack_free(old_obst, 0);
4070 current_ir_graph = old_current_ir_graph;
4071 set_interprocedural_view(old_interprocedural_view);
4073 /* recalculate edges */
4074 edges_deactivate(irg);
4075 edges_activate(irg);
4079 * Transforms a psi condition.
4081 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4084 /* if the mode is target mode, we have already seen this part of the tree */
4085 if (get_irn_mode(cond) == mode)
4088 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4090 set_irn_mode(cond, mode);
4092 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4093 ir_node *in = get_irn_n(cond, i);
4095 /* if in is a compare: transform into Set/xCmp */
4097 ir_node *new_op = NULL;
4098 ir_node *cmp = get_Proj_pred(in);
4099 ir_node *cmp_a = get_Cmp_left(cmp);
4100 ir_node *cmp_b = get_Cmp_right(cmp);
4101 dbg_info *dbgi = get_irn_dbg_info(cmp);
4102 ir_graph *irg = get_irn_irg(cmp);
4103 ir_node *block = get_nodes_block(cmp);
4104 ir_node *noreg = ia32_new_NoReg_gp(cg);
4105 ir_node *nomem = new_rd_NoMem(irg);
4106 int pnc = get_Proj_proj(in);
4108 /* this is a compare */
4109 if (mode_is_float(mode)) {
4110 /* Psi is float, we need a floating point compare */
4113 ir_mode *m = get_irn_mode(cmp_a);
4115 if (! mode_is_float(m)) {
4116 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4117 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4118 } else if (m == mode_F) {
4119 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4120 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4121 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4124 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4125 set_ia32_pncode(new_op, pnc);
4126 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4133 construct_binop_func *set_func = NULL;
4135 if (mode_is_float(get_irn_mode(cmp_a))) {
4136 /* 1st case: compare operands are floats */
4141 set_func = new_rd_ia32_xCmpSet;
4144 set_func = new_rd_ia32_vfCmpSet;
4147 pnc &= 7; /* fp compare -> int compare */
4149 /* 2nd case: compare operand are integer too */
4150 set_func = new_rd_ia32_CmpSet;
4153 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4154 if(!mode_is_signed(mode))
4155 pnc |= ia32_pn_Cmp_Unsigned;
4157 set_ia32_pncode(new_op, pnc);
4158 set_ia32_am_support(new_op, ia32_am_Source);
4161 /* the the new compare as in */
4162 set_irn_n(cond, i, new_op);
4164 /* another complex condition */
4165 transform_psi_cond(in, mode, cg);
4171 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4172 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4173 * each compare, which causes the compare result to be stored in a register. The
4174 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4176 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4177 ia32_code_gen_t *cg = env;
4178 ir_node *psi_sel, *new_cmp, *block;
4183 if (get_irn_opcode(node) != iro_Psi)
4186 psi_sel = get_Psi_cond(node, 0);
4188 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4189 if (is_Proj(psi_sel)) {
4190 assert(is_Cmp(get_Proj_pred(psi_sel)));
4194 //mode = get_irn_mode(node);
4195 // TODO probably wrong...
4198 transform_psi_cond(psi_sel, mode, cg);
4200 irg = get_irn_irg(node);
4201 block = get_nodes_block(node);
4203 /* we need to compare the evaluated condition tree with 0 */
4204 mode = get_irn_mode(node);
4205 if (mode_is_float(mode)) {
4206 /* BEWARE: new_r_Const_long works for floating point as well */
4207 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4209 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4210 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4211 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4213 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4214 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4215 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4218 set_Psi_cond(node, 0, new_cmp);
4221 void ia32_init_transform(void)
4223 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");