2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
60 #include "bearch_ia32_t.h"
61 #include "ia32_nodes_attr.h"
62 #include "ia32_transform.h"
63 #include "ia32_new_nodes.h"
64 #include "ia32_map_regs.h"
65 #include "ia32_dbg_stat.h"
66 #include "ia32_optimize.h"
67 #include "ia32_util.h"
68 #include "ia32_address_mode.h"
69 #include "ia32_architecture.h"
71 #include "gen_ia32_regalloc_if.h"
73 #define SFP_SIGN "0x80000000"
74 #define DFP_SIGN "0x8000000000000000"
75 #define SFP_ABS "0x7FFFFFFF"
76 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define DFP_INTMAX "9223372036854775807"
79 #define TP_SFP_SIGN "ia32_sfp_sign"
80 #define TP_DFP_SIGN "ia32_dfp_sign"
81 #define TP_SFP_ABS "ia32_sfp_abs"
82 #define TP_DFP_ABS "ia32_dfp_abs"
83 #define TP_INT_MAX "ia32_int_max"
85 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
86 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
87 #define ENT_SFP_ABS "IA32_SFP_ABS"
88 #define ENT_DFP_ABS "IA32_DFP_ABS"
89 #define ENT_INT_MAX "IA32_INT_MAX"
91 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
92 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
94 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
96 /** hold the current code generator during transformation */
97 static ia32_code_gen_t *env_cg = NULL;
98 static ir_node *initial_fpcw = NULL;
99 static heights_t *heights = NULL;
101 extern ir_op *get_op_Mulh(void);
103 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
104 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
105 ir_node *op1, ir_node *op2);
107 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
108 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
109 ir_node *op1, ir_node *op2, ir_node *flags);
111 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
112 ir_node *block, ir_node *op1, ir_node *op2);
114 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
115 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
119 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
121 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
122 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
123 ir_node *op1, ir_node *op2, ir_node *fpcw);
125 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
126 ir_node *block, ir_node *op);
128 static ir_node *try_create_Immediate(ir_node *node,
129 char immediate_constraint_type);
131 static ir_node *create_immediate_or_transform(ir_node *node,
132 char immediate_constraint_type);
134 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
135 dbg_info *dbgi, ir_node *block,
136 ir_node *op, ir_node *orig_node);
139 * Return true if a mode can be stored in the GP register set
141 int ia32_mode_needs_gp_reg(ir_mode *mode) {
142 if(mode == mode_fpcw)
144 if(get_mode_size_bits(mode) > 32)
146 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
150 * creates a unique ident by adding a number to a tag
152 * @param tag the tag string, must contain a %d if a number
155 static ident *unique_id(const char *tag)
157 static unsigned id = 0;
160 snprintf(str, sizeof(str), tag, ++id);
161 return new_id_from_str(str);
165 * Get a primitive type for a mode.
167 ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
169 pmap_entry *e = pmap_find(types, mode);
174 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
175 res = new_type_primitive(new_id_from_str(buf), mode);
176 set_type_alignment_bytes(res, 16);
177 pmap_insert(types, mode, res);
185 * Creates an immediate.
187 * @param symconst if set, create a SymConst immediate
188 * @param symconst_sign sign for the symconst
189 * @param val integer value for the immediate
191 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
193 ir_graph *irg = current_ir_graph;
194 ir_node *start_block = get_irg_start_block(irg);
195 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
196 symconst, symconst_sign, val);
197 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
203 * Get an atomic entity that is initialized with a tarval forming
206 * @param cnst the node representing the constant
208 static ir_entity *create_float_const_entity(ir_node *cnst)
210 ia32_isa_t *isa = env_cg->isa;
211 tarval *key = get_Const_tarval(cnst);
212 pmap_entry *e = pmap_find(isa->tv_ent, key);
218 ir_mode *mode = get_tarval_mode(tv);
221 if (! ia32_cg_config.use_sse2) {
222 /* try to reduce the mode to produce smaller sized entities */
223 if (mode != mode_F) {
224 if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
226 tv = tarval_convert_to(tv, mode);
227 } else if (mode != mode_D) {
228 if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
230 tv = tarval_convert_to(tv, mode);
236 if (mode == get_irn_mode(cnst)) {
237 /* mode was not changed */
238 tp = get_Const_type(cnst);
239 if (tp == firm_unknown_type)
240 tp = ia32_get_prim_type(isa->types, mode);
242 tp = ia32_get_prim_type(isa->types, mode);
244 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
246 set_entity_ld_ident(res, get_entity_ident(res));
247 set_entity_visibility(res, visibility_local);
248 set_entity_variability(res, variability_constant);
249 set_entity_allocation(res, allocation_static);
251 /* we create a new entity here: It's initialization must resist on the
253 rem = current_ir_graph;
254 current_ir_graph = get_const_code_irg();
255 set_atomic_ent_value(res, new_Const_type(tv, tp));
256 current_ir_graph = rem;
258 pmap_insert(isa->tv_ent, key, res);
266 /** Return non-zero is a node represents the 0 constant. */
267 static int is_Const_0(ir_node *node) {
268 return is_Const(node) && is_Const_null(node);
271 /** Return non-zero is a node represents the 1 constant. */
272 static int is_Const_1(ir_node *node) {
273 return is_Const(node) && is_Const_one(node);
276 /** Return non-zero is a node represents the -1 constant. */
277 static int is_Const_Minus_1(ir_node *node) {
278 return is_Const(node) && is_Const_all_one(node);
282 * returns true if constant can be created with a simple float command
284 static int is_simple_x87_Const(ir_node *node)
286 tarval *tv = get_Const_tarval(node);
287 if (tarval_is_null(tv) || tarval_is_one(tv))
290 /* TODO: match all the other float constants */
295 * returns true if constant can be created with a simple float command
297 static int is_simple_sse_Const(ir_node *node)
299 tarval *tv = get_Const_tarval(node);
300 ir_mode *mode = get_tarval_mode(tv);
305 if (tarval_is_null(tv) || tarval_is_one(tv))
308 if (mode == mode_D) {
309 unsigned val = get_tarval_sub_bits(tv, 0) |
310 (get_tarval_sub_bits(tv, 1) << 8) |
311 (get_tarval_sub_bits(tv, 2) << 16) |
312 (get_tarval_sub_bits(tv, 3) << 24);
314 /* lower 32bit are zero, really a 32bit constant */
318 /* TODO: match all the other float constants */
323 * Transforms a Const.
325 static ir_node *gen_Const(ir_node *node) {
326 ir_graph *irg = current_ir_graph;
327 ir_node *old_block = get_nodes_block(node);
328 ir_node *block = be_transform_node(old_block);
329 dbg_info *dbgi = get_irn_dbg_info(node);
330 ir_mode *mode = get_irn_mode(node);
332 assert(is_Const(node));
334 if (mode_is_float(mode)) {
336 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
337 ir_node *nomem = new_NoMem();
341 if (ia32_cg_config.use_sse2) {
342 tarval *tv = get_Const_tarval(node);
343 if (tarval_is_null(tv)) {
344 load = new_rd_ia32_xZero(dbgi, irg, block);
345 set_ia32_ls_mode(load, mode);
347 } else if (tarval_is_one(tv)) {
348 int cnst = mode == mode_F ? 26 : 55;
349 ir_node *imm1 = create_Immediate(NULL, 0, cnst);
350 ir_node *imm2 = create_Immediate(NULL, 0, 2);
351 ir_node *pslld, *psrld;
353 load = new_rd_ia32_xAllOnes(dbgi, irg, block);
354 set_ia32_ls_mode(load, mode);
355 pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1);
356 set_ia32_ls_mode(pslld, mode);
357 psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2);
358 set_ia32_ls_mode(psrld, mode);
360 } else if (mode == mode_F) {
361 /* we can place any 32bit constant by using a movd gp, sse */
362 unsigned val = get_tarval_sub_bits(tv, 0) |
363 (get_tarval_sub_bits(tv, 1) << 8) |
364 (get_tarval_sub_bits(tv, 2) << 16) |
365 (get_tarval_sub_bits(tv, 3) << 24);
366 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
367 load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
368 set_ia32_ls_mode(load, mode);
371 if (mode == mode_D) {
372 unsigned val = get_tarval_sub_bits(tv, 0) |
373 (get_tarval_sub_bits(tv, 1) << 8) |
374 (get_tarval_sub_bits(tv, 2) << 16) |
375 (get_tarval_sub_bits(tv, 3) << 24);
377 ir_node *imm32 = create_Immediate(NULL, 0, 32);
378 ir_node *cnst, *psllq;
380 /* fine, lower 32bit are zero, produce 32bit value */
381 val = get_tarval_sub_bits(tv, 4) |
382 (get_tarval_sub_bits(tv, 5) << 8) |
383 (get_tarval_sub_bits(tv, 6) << 16) |
384 (get_tarval_sub_bits(tv, 7) << 24);
385 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
386 load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
387 set_ia32_ls_mode(load, mode);
388 psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32);
389 set_ia32_ls_mode(psllq, mode);
394 floatent = create_float_const_entity(node);
396 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
398 set_ia32_op_type(load, ia32_AddrModeS);
399 set_ia32_am_sc(load, floatent);
400 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
401 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
404 if (is_Const_null(node)) {
405 load = new_rd_ia32_vfldz(dbgi, irg, block);
407 set_ia32_ls_mode(load, mode);
408 } else if (is_Const_one(node)) {
409 load = new_rd_ia32_vfld1(dbgi, irg, block);
411 set_ia32_ls_mode(load, mode);
413 floatent = create_float_const_entity(node);
415 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
416 set_ia32_op_type(load, ia32_AddrModeS);
417 set_ia32_am_sc(load, floatent);
418 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
419 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
420 /* take the mode from the entity */
421 set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent)));
425 /* Const Nodes before the initial IncSP are a bad idea, because
426 * they could be spilled and we have no SP ready at that point yet.
427 * So add a dependency to the initial frame pointer calculation to
428 * avoid that situation.
430 if (get_irg_start_block(irg) == block) {
431 add_irn_dep(load, get_irg_frame(irg));
434 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
436 } else { /* non-float mode */
438 tarval *tv = get_Const_tarval(node);
441 tv = tarval_convert_to(tv, mode_Iu);
443 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
445 panic("couldn't convert constant tarval (%+F)", node);
447 val = get_tarval_long(tv);
449 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
450 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
453 if (get_irg_start_block(irg) == block) {
454 add_irn_dep(cnst, get_irg_frame(irg));
462 * Transforms a SymConst.
464 static ir_node *gen_SymConst(ir_node *node) {
465 ir_graph *irg = current_ir_graph;
466 ir_node *old_block = get_nodes_block(node);
467 ir_node *block = be_transform_node(old_block);
468 dbg_info *dbgi = get_irn_dbg_info(node);
469 ir_mode *mode = get_irn_mode(node);
472 if (mode_is_float(mode)) {
473 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
474 ir_node *nomem = new_NoMem();
476 if (ia32_cg_config.use_sse2)
477 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
479 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
480 set_ia32_am_sc(cnst, get_SymConst_entity(node));
481 set_ia32_use_frame(cnst);
485 if(get_SymConst_kind(node) != symconst_addr_ent) {
486 panic("backend only support symconst_addr_ent (at %+F)", node);
488 entity = get_SymConst_entity(node);
489 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
492 /* Const Nodes before the initial IncSP are a bad idea, because
493 * they could be spilled and we have no SP ready at that point yet
495 if (get_irg_start_block(irg) == block) {
496 add_irn_dep(cnst, get_irg_frame(irg));
499 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
504 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
505 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
506 static const struct {
508 const char *ent_name;
509 const char *cnst_str;
512 } names [ia32_known_const_max] = {
513 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
514 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
515 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
516 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
517 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
519 static ir_entity *ent_cache[ia32_known_const_max];
521 const char *tp_name, *ent_name, *cnst_str;
529 ent_name = names[kct].ent_name;
530 if (! ent_cache[kct]) {
531 tp_name = names[kct].tp_name;
532 cnst_str = names[kct].cnst_str;
534 switch (names[kct].mode) {
535 case 0: mode = mode_Iu; break;
536 case 1: mode = mode_Lu; break;
537 default: mode = mode_F; break;
539 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
540 tp = new_type_primitive(new_id_from_str(tp_name), mode);
541 /* set the specified alignment */
542 set_type_alignment_bytes(tp, names[kct].align);
544 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
546 set_entity_ld_ident(ent, get_entity_ident(ent));
547 set_entity_visibility(ent, visibility_local);
548 set_entity_variability(ent, variability_constant);
549 set_entity_allocation(ent, allocation_static);
551 /* we create a new entity here: It's initialization must resist on the
553 rem = current_ir_graph;
554 current_ir_graph = get_const_code_irg();
555 cnst = new_Const(mode, tv);
556 current_ir_graph = rem;
558 set_atomic_ent_value(ent, cnst);
560 /* cache the entry */
561 ent_cache[kct] = ent;
564 return ent_cache[kct];
569 * Prints the old node name on cg obst and returns a pointer to it.
571 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
572 ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
574 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
575 obstack_1grow(isa->name_obst, 0);
576 return obstack_finish(isa->name_obst);
581 * return true if the node is a Proj(Load) and could be used in source address
582 * mode for another node. Will return only true if the @p other node is not
583 * dependent on the memory of the Load (for binary operations use the other
584 * input here, for unary operations use NULL).
586 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
587 ir_node *other, ir_node *other2, match_flags_t flags)
592 /* float constants are always available */
593 if (is_Const(node)) {
594 ir_mode *mode = get_irn_mode(node);
595 if (mode_is_float(mode)) {
596 if (ia32_cg_config.use_sse2) {
597 if (is_simple_sse_Const(node))
600 if (is_simple_x87_Const(node))
603 if (get_irn_n_edges(node) > 1)
611 load = get_Proj_pred(node);
612 pn = get_Proj_proj(node);
613 if (!is_Load(load) || pn != pn_Load_res)
615 if (get_nodes_block(load) != block)
617 /* we only use address mode if we're the only user of the load */
618 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
620 /* in some edge cases with address mode we might reach the load normally
621 * and through some AM sequence, if it is already materialized then we
622 * can't create an AM node from it */
623 if (be_is_transformed(node))
626 /* don't do AM if other node inputs depend on the load (via mem-proj) */
627 if (other != NULL && get_nodes_block(other) == block &&
628 heights_reachable_in_block(heights, other, load))
630 if (other2 != NULL && get_nodes_block(other2) == block &&
631 heights_reachable_in_block(heights, other2, load))
637 typedef struct ia32_address_mode_t ia32_address_mode_t;
638 struct ia32_address_mode_t {
642 ia32_op_type_t op_type;
646 unsigned commutative : 1;
647 unsigned ins_permuted : 1;
650 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
654 /* construct load address */
655 memset(addr, 0, sizeof(addr[0]));
656 ia32_create_address_mode(addr, ptr, /*force=*/0);
658 noreg_gp = ia32_new_NoReg_gp(env_cg);
659 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
660 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
661 addr->mem = be_transform_node(mem);
664 static void build_address(ia32_address_mode_t *am, ir_node *node)
666 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
667 ia32_address_t *addr = &am->addr;
673 if (is_Const(node)) {
674 ir_entity *entity = create_float_const_entity(node);
675 addr->base = noreg_gp;
676 addr->index = noreg_gp;
677 addr->mem = new_NoMem();
678 addr->symconst_ent = entity;
680 am->ls_mode = get_type_mode(get_entity_type(entity));
681 am->pinned = op_pin_state_floats;
685 load = get_Proj_pred(node);
686 ptr = get_Load_ptr(load);
687 mem = get_Load_mem(load);
688 new_mem = be_transform_node(mem);
689 am->pinned = get_irn_pinned(load);
690 am->ls_mode = get_Load_mode(load);
691 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
693 /* construct load address */
694 ia32_create_address_mode(addr, ptr, /*force=*/0);
696 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
697 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
701 static void set_address(ir_node *node, const ia32_address_t *addr)
703 set_ia32_am_scale(node, addr->scale);
704 set_ia32_am_sc(node, addr->symconst_ent);
705 set_ia32_am_offs_int(node, addr->offset);
706 if(addr->symconst_sign)
707 set_ia32_am_sc_sign(node);
709 set_ia32_use_frame(node);
710 set_ia32_frame_ent(node, addr->frame_entity);
714 * Apply attributes of a given address mode to a node.
716 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
718 set_address(node, &am->addr);
720 set_ia32_op_type(node, am->op_type);
721 set_ia32_ls_mode(node, am->ls_mode);
722 if (am->pinned == op_pin_state_pinned) {
723 /* beware: some nodes are already pinned and did not allow to change the state */
724 if (get_irn_pinned(node) != op_pin_state_pinned)
725 set_irn_pinned(node, op_pin_state_pinned);
728 set_ia32_commutative(node);
732 * Check, if a given node is a Down-Conv, ie. a integer Conv
733 * from a mode with a mode with more bits to a mode with lesser bits.
734 * Moreover, we return only true if the node has not more than 1 user.
736 * @param node the node
737 * @return non-zero if node is a Down-Conv
739 static int is_downconv(const ir_node *node)
747 /* we only want to skip the conv when we're the only user
748 * (not optimal but for now...)
750 if(get_irn_n_edges(node) > 1)
753 src_mode = get_irn_mode(get_Conv_op(node));
754 dest_mode = get_irn_mode(node);
755 return ia32_mode_needs_gp_reg(src_mode)
756 && ia32_mode_needs_gp_reg(dest_mode)
757 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
760 /* Skip all Down-Conv's on a given node and return the resulting node. */
761 ir_node *ia32_skip_downconv(ir_node *node) {
762 while (is_downconv(node))
763 node = get_Conv_op(node);
768 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
770 ir_mode *mode = get_irn_mode(node);
775 if(mode_is_signed(mode)) {
780 block = get_nodes_block(node);
781 dbgi = get_irn_dbg_info(node);
783 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
787 * matches operands of a node into ia32 addressing/operand modes. This covers
788 * usage of source address mode, immediates, operations with non 32-bit modes,
790 * The resulting data is filled into the @p am struct. block is the block
791 * of the node whose arguments are matched. op1, op2 are the first and second
792 * input that are matched (op1 may be NULL). other_op is another unrelated
793 * input that is not matched! but which is needed sometimes to check if AM
794 * for op1/op2 is legal.
795 * @p flags describes the supported modes of the operation in detail.
797 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
798 ir_node *op1, ir_node *op2, ir_node *other_op,
801 ia32_address_t *addr = &am->addr;
802 ir_mode *mode = get_irn_mode(op2);
803 int mode_bits = get_mode_size_bits(mode);
804 ir_node *noreg_gp, *new_op1, *new_op2;
806 unsigned commutative;
807 int use_am_and_immediates;
810 memset(am, 0, sizeof(am[0]));
812 commutative = (flags & match_commutative) != 0;
813 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
814 use_am = (flags & match_am) != 0;
815 use_immediate = (flags & match_immediate) != 0;
816 assert(!use_am_and_immediates || use_immediate);
819 assert(!commutative || op1 != NULL);
820 assert(use_am || !(flags & match_8bit_am));
821 assert(use_am || !(flags & match_16bit_am));
823 if (mode_bits == 8) {
824 if (!(flags & match_8bit_am))
826 /* we don't automatically add upconvs yet */
827 assert((flags & match_mode_neutral) || (flags & match_8bit));
828 } else if (mode_bits == 16) {
829 if (!(flags & match_16bit_am))
831 /* we don't automatically add upconvs yet */
832 assert((flags & match_mode_neutral) || (flags & match_16bit));
835 /* we can simply skip downconvs for mode neutral nodes: the upper bits
836 * can be random for these operations */
837 if (flags & match_mode_neutral) {
838 op2 = ia32_skip_downconv(op2);
840 op1 = ia32_skip_downconv(op1);
844 /* match immediates. firm nodes are normalized: constants are always on the
847 if (!(flags & match_try_am) && use_immediate) {
848 new_op2 = try_create_Immediate(op2, 0);
851 noreg_gp = ia32_new_NoReg_gp(env_cg);
852 if (new_op2 == NULL &&
853 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
854 build_address(am, op2);
855 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
856 if (mode_is_float(mode)) {
857 new_op2 = ia32_new_NoReg_vfp(env_cg);
861 am->op_type = ia32_AddrModeS;
862 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
864 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
866 build_address(am, op1);
868 if (mode_is_float(mode)) {
869 noreg = ia32_new_NoReg_vfp(env_cg);
874 if (new_op2 != NULL) {
877 new_op1 = be_transform_node(op2);
879 am->ins_permuted = 1;
881 am->op_type = ia32_AddrModeS;
883 if (flags & match_try_am) {
886 am->op_type = ia32_Normal;
890 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
892 new_op2 = be_transform_node(op2);
893 am->op_type = ia32_Normal;
894 am->ls_mode = get_irn_mode(op2);
895 if (flags & match_mode_neutral)
896 am->ls_mode = mode_Iu;
898 if (addr->base == NULL)
899 addr->base = noreg_gp;
900 if (addr->index == NULL)
901 addr->index = noreg_gp;
902 if (addr->mem == NULL)
903 addr->mem = new_NoMem();
905 am->new_op1 = new_op1;
906 am->new_op2 = new_op2;
907 am->commutative = commutative;
910 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
915 if (am->mem_proj == NULL)
918 /* we have to create a mode_T so the old MemProj can attach to us */
919 mode = get_irn_mode(node);
920 load = get_Proj_pred(am->mem_proj);
922 mark_irn_visited(load);
923 be_set_transformed_node(load, node);
925 if (mode != mode_T) {
926 set_irn_mode(node, mode_T);
927 return new_rd_Proj(NULL, current_ir_graph, get_nodes_block(node), node, mode, pn_ia32_res);
934 * Construct a standard binary operation, set AM and immediate if required.
936 * @param node The original node for which the binop is created
937 * @param op1 The first operand
938 * @param op2 The second operand
939 * @param func The node constructor function
940 * @return The constructed ia32 node.
942 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
943 construct_binop_func *func, match_flags_t flags)
946 ir_node *block, *new_block, *new_node;
947 ia32_address_mode_t am;
948 ia32_address_t *addr = &am.addr;
950 block = get_nodes_block(node);
951 match_arguments(&am, block, op1, op2, NULL, flags);
953 dbgi = get_irn_dbg_info(node);
954 new_block = be_transform_node(block);
955 new_node = func(dbgi, current_ir_graph, new_block,
956 addr->base, addr->index, addr->mem,
957 am.new_op1, am.new_op2);
958 set_am_attributes(new_node, &am);
959 /* we can't use source address mode anymore when using immediates */
960 if (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
961 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
962 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
964 new_node = fix_mem_proj(new_node, &am);
971 n_ia32_l_binop_right,
972 n_ia32_l_binop_eflags
974 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
975 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
976 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
977 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
978 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
979 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
982 * Construct a binary operation which also consumes the eflags.
984 * @param node The node to transform
985 * @param func The node constructor function
986 * @param flags The match flags
987 * @return The constructor ia32 node
989 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
992 ir_node *src_block = get_nodes_block(node);
993 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
994 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
996 ir_node *block, *new_node, *eflags, *new_eflags;
997 ia32_address_mode_t am;
998 ia32_address_t *addr = &am.addr;
1000 match_arguments(&am, src_block, op1, op2, NULL, flags);
1002 dbgi = get_irn_dbg_info(node);
1003 block = be_transform_node(src_block);
1004 eflags = get_irn_n(node, n_ia32_l_binop_eflags);
1005 new_eflags = be_transform_node(eflags);
1006 new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index,
1007 addr->mem, am.new_op1, am.new_op2, new_eflags);
1008 set_am_attributes(new_node, &am);
1009 /* we can't use source address mode anymore when using immediates */
1010 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1011 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1012 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1014 new_node = fix_mem_proj(new_node, &am);
1019 static ir_node *get_fpcw(void)
1022 if (initial_fpcw != NULL)
1023 return initial_fpcw;
1025 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1026 &ia32_fp_cw_regs[REG_FPCW]);
1027 initial_fpcw = be_transform_node(fpcw);
1029 return initial_fpcw;
1033 * Construct a standard binary operation, set AM and immediate if required.
1035 * @param op1 The first operand
1036 * @param op2 The second operand
1037 * @param func The node constructor function
1038 * @return The constructed ia32 node.
1040 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1041 construct_binop_float_func *func,
1042 match_flags_t flags)
1044 ir_mode *mode = get_irn_mode(node);
1046 ir_node *block, *new_block, *new_node;
1047 ia32_address_mode_t am;
1048 ia32_address_t *addr = &am.addr;
1050 /* cannot use address mode with long double on x87 */
1051 if (get_mode_size_bits(mode) > 64)
1054 block = get_nodes_block(node);
1055 match_arguments(&am, block, op1, op2, NULL, flags);
1057 dbgi = get_irn_dbg_info(node);
1058 new_block = be_transform_node(block);
1059 new_node = func(dbgi, current_ir_graph, new_block,
1060 addr->base, addr->index, addr->mem,
1061 am.new_op1, am.new_op2, get_fpcw());
1062 set_am_attributes(new_node, &am);
1064 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1066 new_node = fix_mem_proj(new_node, &am);
1072 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1074 * @param op1 The first operand
1075 * @param op2 The second operand
1076 * @param func The node constructor function
1077 * @return The constructed ia32 node.
1079 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1080 construct_shift_func *func,
1081 match_flags_t flags)
1084 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1086 assert(! mode_is_float(get_irn_mode(node)));
1087 assert(flags & match_immediate);
1088 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1090 if (flags & match_mode_neutral) {
1091 op1 = ia32_skip_downconv(op1);
1092 new_op1 = be_transform_node(op1);
1093 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
1094 new_op1 = create_upconv(op1, node);
1096 new_op1 = be_transform_node(op1);
1099 /* the shift amount can be any mode that is bigger than 5 bits, since all
1100 * other bits are ignored anyway */
1101 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1102 op2 = get_Conv_op(op2);
1103 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1105 new_op2 = create_immediate_or_transform(op2, 0);
1107 dbgi = get_irn_dbg_info(node);
1108 block = get_nodes_block(node);
1109 new_block = be_transform_node(block);
1110 new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2);
1111 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1113 /* lowered shift instruction may have a dependency operand, handle it here */
1114 if (get_irn_arity(node) == 3) {
1115 /* we have a dependency */
1116 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
1117 add_irn_dep(new_node, new_dep);
1125 * Construct a standard unary operation, set AM and immediate if required.
1127 * @param op The operand
1128 * @param func The node constructor function
1129 * @return The constructed ia32 node.
1131 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1132 match_flags_t flags)
1135 ir_node *block, *new_block, *new_op, *new_node;
1137 assert(flags == 0 || flags == match_mode_neutral);
1138 if (flags & match_mode_neutral) {
1139 op = ia32_skip_downconv(op);
1142 new_op = be_transform_node(op);
1143 dbgi = get_irn_dbg_info(node);
1144 block = get_nodes_block(node);
1145 new_block = be_transform_node(block);
1146 new_node = func(dbgi, current_ir_graph, new_block, new_op);
1148 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1153 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1154 ia32_address_t *addr)
1156 ir_node *base, *index, *res;
1160 base = ia32_new_NoReg_gp(env_cg);
1162 base = be_transform_node(base);
1165 index = addr->index;
1166 if (index == NULL) {
1167 index = ia32_new_NoReg_gp(env_cg);
1169 index = be_transform_node(index);
1172 res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index);
1173 set_address(res, addr);
1179 * Returns non-zero if a given address mode has a symbolic or
1180 * numerical offset != 0.
1182 static int am_has_immediates(const ia32_address_t *addr)
1184 return addr->offset != 0 || addr->symconst_ent != NULL
1185 || addr->frame_entity || addr->use_frame;
1189 * Creates an ia32 Add.
1191 * @return the created ia32 Add node
1193 static ir_node *gen_Add(ir_node *node) {
1194 ir_mode *mode = get_irn_mode(node);
1195 ir_node *op1 = get_Add_left(node);
1196 ir_node *op2 = get_Add_right(node);
1198 ir_node *block, *new_block, *new_node, *add_immediate_op;
1199 ia32_address_t addr;
1200 ia32_address_mode_t am;
1202 if (mode_is_float(mode)) {
1203 if (ia32_cg_config.use_sse2)
1204 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1205 match_commutative | match_am);
1207 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1208 match_commutative | match_am);
1211 ia32_mark_non_am(node);
1213 op2 = ia32_skip_downconv(op2);
1214 op1 = ia32_skip_downconv(op1);
1218 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1219 * 1. Add with immediate -> Lea
1220 * 2. Add with possible source address mode -> Add
1221 * 3. Otherwise -> Lea
1223 memset(&addr, 0, sizeof(addr));
1224 ia32_create_address_mode(&addr, node, /*force=*/1);
1225 add_immediate_op = NULL;
1227 dbgi = get_irn_dbg_info(node);
1228 block = get_nodes_block(node);
1229 new_block = be_transform_node(block);
1232 if(addr.base == NULL && addr.index == NULL) {
1233 ir_graph *irg = current_ir_graph;
1234 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1235 addr.symconst_sign, addr.offset);
1236 add_irn_dep(new_node, get_irg_frame(irg));
1237 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1240 /* add with immediate? */
1241 if(addr.index == NULL) {
1242 add_immediate_op = addr.base;
1243 } else if(addr.base == NULL && addr.scale == 0) {
1244 add_immediate_op = addr.index;
1247 if(add_immediate_op != NULL) {
1248 if(!am_has_immediates(&addr)) {
1249 #ifdef DEBUG_libfirm
1250 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1253 return be_transform_node(add_immediate_op);
1256 new_node = create_lea_from_address(dbgi, new_block, &addr);
1257 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1261 /* test if we can use source address mode */
1262 match_arguments(&am, block, op1, op2, NULL, match_commutative
1263 | match_mode_neutral | match_am | match_immediate | match_try_am);
1265 /* construct an Add with source address mode */
1266 if (am.op_type == ia32_AddrModeS) {
1267 ir_graph *irg = current_ir_graph;
1268 ia32_address_t *am_addr = &am.addr;
1269 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1270 am_addr->index, am_addr->mem, am.new_op1,
1272 set_am_attributes(new_node, &am);
1273 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1275 new_node = fix_mem_proj(new_node, &am);
1280 /* otherwise construct a lea */
1281 new_node = create_lea_from_address(dbgi, new_block, &addr);
1282 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1287 * Creates an ia32 Mul.
1289 * @return the created ia32 Mul node
1291 static ir_node *gen_Mul(ir_node *node) {
1292 ir_node *op1 = get_Mul_left(node);
1293 ir_node *op2 = get_Mul_right(node);
1294 ir_mode *mode = get_irn_mode(node);
1296 if (mode_is_float(mode)) {
1297 if (ia32_cg_config.use_sse2)
1298 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1299 match_commutative | match_am);
1301 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1302 match_commutative | match_am);
1304 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1305 match_commutative | match_am | match_mode_neutral |
1306 match_immediate | match_am_and_immediates);
1310 * Creates an ia32 Mulh.
1311 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1312 * this result while Mul returns the lower 32 bit.
1314 * @return the created ia32 Mulh node
1316 static ir_node *gen_Mulh(ir_node *node)
1318 ir_node *block = get_nodes_block(node);
1319 ir_node *new_block = be_transform_node(block);
1320 ir_graph *irg = current_ir_graph;
1321 dbg_info *dbgi = get_irn_dbg_info(node);
1322 ir_mode *mode = get_irn_mode(node);
1323 ir_node *op1 = get_Mulh_left(node);
1324 ir_node *op2 = get_Mulh_right(node);
1325 ir_node *proj_res_high;
1327 ia32_address_mode_t am;
1328 ia32_address_t *addr = &am.addr;
1330 assert(!mode_is_float(mode) && "Mulh with float not supported");
1331 assert(get_mode_size_bits(mode) == 32);
1333 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1335 if (mode_is_signed(mode)) {
1336 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1337 addr->index, addr->mem, am.new_op1,
1340 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1341 addr->index, addr->mem, am.new_op1,
1345 set_am_attributes(new_node, &am);
1346 /* we can't use source address mode anymore when using immediates */
1347 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1348 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1349 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1351 assert(get_irn_mode(new_node) == mode_T);
1353 fix_mem_proj(new_node, &am);
1355 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1356 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1357 mode_Iu, pn_ia32_IMul1OP_res_high);
1359 return proj_res_high;
1365 * Creates an ia32 And.
1367 * @return The created ia32 And node
1369 static ir_node *gen_And(ir_node *node) {
1370 ir_node *op1 = get_And_left(node);
1371 ir_node *op2 = get_And_right(node);
1372 assert(! mode_is_float(get_irn_mode(node)));
1374 /* is it a zero extension? */
1375 if (is_Const(op2)) {
1376 tarval *tv = get_Const_tarval(op2);
1377 long v = get_tarval_long(tv);
1379 if (v == 0xFF || v == 0xFFFF) {
1380 dbg_info *dbgi = get_irn_dbg_info(node);
1381 ir_node *block = get_nodes_block(node);
1388 assert(v == 0xFFFF);
1391 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1396 return gen_binop(node, op1, op2, new_rd_ia32_And,
1397 match_commutative | match_mode_neutral | match_am
1404 * Creates an ia32 Or.
1406 * @return The created ia32 Or node
1408 static ir_node *gen_Or(ir_node *node) {
1409 ir_node *op1 = get_Or_left(node);
1410 ir_node *op2 = get_Or_right(node);
1412 assert (! mode_is_float(get_irn_mode(node)));
1413 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1414 | match_mode_neutral | match_am | match_immediate);
1420 * Creates an ia32 Eor.
1422 * @return The created ia32 Eor node
1424 static ir_node *gen_Eor(ir_node *node) {
1425 ir_node *op1 = get_Eor_left(node);
1426 ir_node *op2 = get_Eor_right(node);
1428 assert(! mode_is_float(get_irn_mode(node)));
1429 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1430 | match_mode_neutral | match_am | match_immediate);
1435 * Creates an ia32 Sub.
1437 * @return The created ia32 Sub node
1439 static ir_node *gen_Sub(ir_node *node) {
1440 ir_node *op1 = get_Sub_left(node);
1441 ir_node *op2 = get_Sub_right(node);
1442 ir_mode *mode = get_irn_mode(node);
1444 if (mode_is_float(mode)) {
1445 if (ia32_cg_config.use_sse2)
1446 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1448 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1452 if (is_Const(op2)) {
1453 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1457 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1458 | match_am | match_immediate);
1462 * Generates an ia32 DivMod with additional infrastructure for the
1463 * register allocator if needed.
1465 static ir_node *create_Div(ir_node *node)
1467 ir_graph *irg = current_ir_graph;
1468 dbg_info *dbgi = get_irn_dbg_info(node);
1469 ir_node *block = get_nodes_block(node);
1470 ir_node *new_block = be_transform_node(block);
1477 ir_node *sign_extension;
1478 ia32_address_mode_t am;
1479 ia32_address_t *addr = &am.addr;
1481 /* the upper bits have random contents for smaller modes */
1482 switch (get_irn_opcode(node)) {
1484 op1 = get_Div_left(node);
1485 op2 = get_Div_right(node);
1486 mem = get_Div_mem(node);
1487 mode = get_Div_resmode(node);
1490 op1 = get_Mod_left(node);
1491 op2 = get_Mod_right(node);
1492 mem = get_Mod_mem(node);
1493 mode = get_Mod_resmode(node);
1496 op1 = get_DivMod_left(node);
1497 op2 = get_DivMod_right(node);
1498 mem = get_DivMod_mem(node);
1499 mode = get_DivMod_resmode(node);
1502 panic("invalid divmod node %+F", node);
1505 match_arguments(&am, block, op1, op2, NULL, match_am);
1507 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1508 is the memory of the consumed address. We can have only the second op as address
1509 in Div nodes, so check only op2. */
1510 if(!is_NoMem(mem) && skip_Proj(mem) != skip_Proj(op2)) {
1511 new_mem = be_transform_node(mem);
1512 if(!is_NoMem(addr->mem)) {
1516 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1519 new_mem = addr->mem;
1522 if (mode_is_signed(mode)) {
1523 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1524 add_irn_dep(produceval, get_irg_frame(irg));
1525 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1528 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1529 addr->index, new_mem, am.new_op2,
1530 am.new_op1, sign_extension);
1532 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1533 add_irn_dep(sign_extension, get_irg_frame(irg));
1535 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1536 addr->index, new_mem, am.new_op2,
1537 am.new_op1, sign_extension);
1540 set_irn_pinned(new_node, get_irn_pinned(node));
1542 set_am_attributes(new_node, &am);
1543 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1545 new_node = fix_mem_proj(new_node, &am);
1551 static ir_node *gen_Mod(ir_node *node) {
1552 return create_Div(node);
1555 static ir_node *gen_Div(ir_node *node) {
1556 return create_Div(node);
1559 static ir_node *gen_DivMod(ir_node *node) {
1560 return create_Div(node);
1566 * Creates an ia32 floating Div.
1568 * @return The created ia32 xDiv node
1570 static ir_node *gen_Quot(ir_node *node)
1572 ir_node *op1 = get_Quot_left(node);
1573 ir_node *op2 = get_Quot_right(node);
1575 if (ia32_cg_config.use_sse2) {
1576 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1578 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1584 * Creates an ia32 Shl.
1586 * @return The created ia32 Shl node
1588 static ir_node *gen_Shl(ir_node *node) {
1589 ir_node *left = get_Shl_left(node);
1590 ir_node *right = get_Shl_right(node);
1592 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1593 match_mode_neutral | match_immediate);
1597 * Creates an ia32 Shr.
1599 * @return The created ia32 Shr node
1601 static ir_node *gen_Shr(ir_node *node) {
1602 ir_node *left = get_Shr_left(node);
1603 ir_node *right = get_Shr_right(node);
1605 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1611 * Creates an ia32 Sar.
1613 * @return The created ia32 Shrs node
1615 static ir_node *gen_Shrs(ir_node *node) {
1616 ir_node *left = get_Shrs_left(node);
1617 ir_node *right = get_Shrs_right(node);
1618 ir_mode *mode = get_irn_mode(node);
1620 if(is_Const(right) && mode == mode_Is) {
1621 tarval *tv = get_Const_tarval(right);
1622 long val = get_tarval_long(tv);
1624 /* this is a sign extension */
1625 ir_graph *irg = current_ir_graph;
1626 dbg_info *dbgi = get_irn_dbg_info(node);
1627 ir_node *block = be_transform_node(get_nodes_block(node));
1629 ir_node *new_op = be_transform_node(op);
1630 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1631 add_irn_dep(pval, get_irg_frame(irg));
1633 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1637 /* 8 or 16 bit sign extension? */
1638 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1639 ir_node *shl_left = get_Shl_left(left);
1640 ir_node *shl_right = get_Shl_right(left);
1641 if(is_Const(shl_right)) {
1642 tarval *tv1 = get_Const_tarval(right);
1643 tarval *tv2 = get_Const_tarval(shl_right);
1644 if(tv1 == tv2 && tarval_is_long(tv1)) {
1645 long val = get_tarval_long(tv1);
1646 if(val == 16 || val == 24) {
1647 dbg_info *dbgi = get_irn_dbg_info(node);
1648 ir_node *block = get_nodes_block(node);
1658 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1667 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1673 * Creates an ia32 Rol.
1675 * @param op1 The first operator
1676 * @param op2 The second operator
1677 * @return The created ia32 RotL node
1679 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
1680 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1686 * Creates an ia32 Ror.
1687 * NOTE: There is no RotR with immediate because this would always be a RotL
1688 * "imm-mode_size_bits" which can be pre-calculated.
1690 * @param op1 The first operator
1691 * @param op2 The second operator
1692 * @return The created ia32 RotR node
1694 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
1695 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1701 * Creates an ia32 RotR or RotL (depending on the found pattern).
1703 * @return The created ia32 RotL or RotR node
1705 static ir_node *gen_Rotl(ir_node *node) {
1706 ir_node *rotate = NULL;
1707 ir_node *op1 = get_Rotl_left(node);
1708 ir_node *op2 = get_Rotl_right(node);
1710 /* Firm has only RotL, so we are looking for a right (op2)
1711 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1712 that means we can create a RotR instead of an Add and a RotL */
1716 ir_node *left = get_Add_left(add);
1717 ir_node *right = get_Add_right(add);
1718 if (is_Const(right)) {
1719 tarval *tv = get_Const_tarval(right);
1720 ir_mode *mode = get_irn_mode(node);
1721 long bits = get_mode_size_bits(mode);
1723 if (is_Minus(left) &&
1724 tarval_is_long(tv) &&
1725 get_tarval_long(tv) == bits &&
1728 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1729 rotate = gen_Ror(node, op1, get_Minus_op(left));
1734 if (rotate == NULL) {
1735 rotate = gen_Rol(node, op1, op2);
1744 * Transforms a Minus node.
1746 * @return The created ia32 Minus node
1748 static ir_node *gen_Minus(ir_node *node)
1750 ir_node *op = get_Minus_op(node);
1751 ir_node *block = be_transform_node(get_nodes_block(node));
1752 ir_graph *irg = current_ir_graph;
1753 dbg_info *dbgi = get_irn_dbg_info(node);
1754 ir_mode *mode = get_irn_mode(node);
1759 if (mode_is_float(mode)) {
1760 ir_node *new_op = be_transform_node(op);
1761 if (ia32_cg_config.use_sse2) {
1762 /* TODO: non-optimal... if we have many xXors, then we should
1763 * rather create a load for the const and use that instead of
1764 * several AM nodes... */
1765 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1766 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1767 ir_node *nomem = new_rd_NoMem(irg);
1769 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1770 nomem, new_op, noreg_xmm);
1772 size = get_mode_size_bits(mode);
1773 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1775 set_ia32_am_sc(new_node, ent);
1776 set_ia32_op_type(new_node, ia32_AddrModeS);
1777 set_ia32_ls_mode(new_node, mode);
1779 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1782 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1785 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1791 * Transforms a Not node.
1793 * @return The created ia32 Not node
1795 static ir_node *gen_Not(ir_node *node) {
1796 ir_node *op = get_Not_op(node);
1798 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1799 assert (! mode_is_float(get_irn_mode(node)));
1801 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1807 * Transforms an Abs node.
1809 * @return The created ia32 Abs node
1811 static ir_node *gen_Abs(ir_node *node)
1813 ir_node *block = get_nodes_block(node);
1814 ir_node *new_block = be_transform_node(block);
1815 ir_node *op = get_Abs_op(node);
1816 ir_graph *irg = current_ir_graph;
1817 dbg_info *dbgi = get_irn_dbg_info(node);
1818 ir_mode *mode = get_irn_mode(node);
1819 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1820 ir_node *nomem = new_NoMem();
1826 if (mode_is_float(mode)) {
1827 new_op = be_transform_node(op);
1829 if (ia32_cg_config.use_sse2) {
1830 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1831 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1832 nomem, new_op, noreg_fp);
1834 size = get_mode_size_bits(mode);
1835 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1837 set_ia32_am_sc(new_node, ent);
1839 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1841 set_ia32_op_type(new_node, ia32_AddrModeS);
1842 set_ia32_ls_mode(new_node, mode);
1844 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1845 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1848 ir_node *xor, *pval, *sign_extension;
1850 if (get_mode_size_bits(mode) == 32) {
1851 new_op = be_transform_node(op);
1853 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1856 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1857 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1860 add_irn_dep(pval, get_irg_frame(irg));
1861 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1863 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1864 nomem, new_op, sign_extension);
1865 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1867 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1868 nomem, xor, sign_extension);
1869 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1876 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1878 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) {
1879 dbg_info *dbgi = get_irn_dbg_info(cmp);
1880 ir_node *block = get_nodes_block(cmp);
1881 ir_node *new_block = be_transform_node(block);
1882 ir_node *op1 = be_transform_node(x);
1883 ir_node *op2 = be_transform_node(n);
1885 return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2);
1889 * Transform a node returning a "flag" result.
1891 * @param node the node to transform
1892 * @param pnc_out the compare mode to use
1894 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1903 /* we have a Cmp as input */
1904 if (is_Proj(node)) {
1905 ir_node *pred = get_Proj_pred(node);
1907 pn_Cmp pnc = get_Proj_proj(node);
1908 if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
1909 ir_node *l = get_Cmp_left(pred);
1910 ir_node *r = get_Cmp_right(pred);
1912 ir_node *la = get_And_left(l);
1913 ir_node *ra = get_And_right(l);
1915 ir_node *c = get_Shl_left(la);
1916 if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
1917 /* (1 << n) & ra) */
1918 ir_node *n = get_Shl_right(la);
1919 flags = gen_bt(pred, ra, n);
1920 /* we must generate a Jc/Jnc jump */
1921 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1924 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1929 ir_node *c = get_Shl_left(ra);
1930 if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
1931 /* la & (1 << n)) */
1932 ir_node *n = get_Shl_right(ra);
1933 flags = gen_bt(pred, la, n);
1934 /* we must generate a Jc/Jnc jump */
1935 pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
1938 *pnc_out = ia32_pn_Cmp_unsigned | pnc;
1944 flags = be_transform_node(pred);
1950 /* a mode_b value, we have to compare it against 0 */
1951 dbgi = get_irn_dbg_info(node);
1952 new_block = be_transform_node(get_nodes_block(node));
1953 new_op = be_transform_node(node);
1954 noreg = ia32_new_NoReg_gp(env_cg);
1955 nomem = new_NoMem();
1956 flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem,
1957 new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
1958 *pnc_out = pn_Cmp_Lg;
1963 * Transforms a Load.
1965 * @return the created ia32 Load node
1967 static ir_node *gen_Load(ir_node *node) {
1968 ir_node *old_block = get_nodes_block(node);
1969 ir_node *block = be_transform_node(old_block);
1970 ir_node *ptr = get_Load_ptr(node);
1971 ir_node *mem = get_Load_mem(node);
1972 ir_node *new_mem = be_transform_node(mem);
1975 ir_graph *irg = current_ir_graph;
1976 dbg_info *dbgi = get_irn_dbg_info(node);
1977 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1978 ir_mode *mode = get_Load_mode(node);
1981 ia32_address_t addr;
1983 /* construct load address */
1984 memset(&addr, 0, sizeof(addr));
1985 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1992 base = be_transform_node(base);
1998 index = be_transform_node(index);
2001 if (mode_is_float(mode)) {
2002 if (ia32_cg_config.use_sse2) {
2003 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
2005 res_mode = mode_xmm;
2007 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
2009 res_mode = mode_vfp;
2012 assert(mode != mode_b);
2014 /* create a conv node with address mode for smaller modes */
2015 if(get_mode_size_bits(mode) < 32) {
2016 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
2017 new_mem, noreg, mode);
2019 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
2024 set_irn_pinned(new_node, get_irn_pinned(node));
2025 set_ia32_op_type(new_node, ia32_AddrModeS);
2026 set_ia32_ls_mode(new_node, mode);
2027 set_address(new_node, &addr);
2029 if(get_irn_pinned(node) == op_pin_state_floats) {
2030 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
2033 /* make sure we are scheduled behind the initial IncSP/Barrier
2034 * to avoid spills being placed before it
2036 if (block == get_irg_start_block(irg)) {
2037 add_irn_dep(new_node, get_irg_frame(irg));
2040 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2045 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2046 ir_node *ptr, ir_node *other)
2053 /* we only use address mode if we're the only user of the load */
2054 if(get_irn_n_edges(node) > 1)
2057 load = get_Proj_pred(node);
2060 if(get_nodes_block(load) != block)
2063 /* Store should be attached to the load */
2064 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
2066 /* store should have the same pointer as the load */
2067 if(get_Load_ptr(load) != ptr)
2070 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2071 if(other != NULL && get_nodes_block(other) == block
2072 && heights_reachable_in_block(heights, other, load))
2078 static void set_transformed_and_mark(ir_node *const old_node, ir_node *const new_node)
2080 mark_irn_visited(old_node);
2081 be_set_transformed_node(old_node, new_node);
2084 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2085 ir_node *mem, ir_node *ptr, ir_mode *mode,
2086 construct_binop_dest_func *func,
2087 construct_binop_dest_func *func8bit,
2088 match_flags_t flags)
2090 ir_node *src_block = get_nodes_block(node);
2092 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
2093 ir_graph *irg = current_ir_graph;
2099 ia32_address_mode_t am;
2100 ia32_address_t *addr = &am.addr;
2101 memset(&am, 0, sizeof(am));
2103 assert(flags & match_dest_am);
2104 assert(flags & match_immediate); /* there is no destam node without... */
2105 commutative = (flags & match_commutative) != 0;
2107 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
2108 build_address(&am, op1);
2109 new_op = create_immediate_or_transform(op2, 0);
2110 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2111 build_address(&am, op2);
2112 new_op = create_immediate_or_transform(op1, 0);
2117 if(addr->base == NULL)
2118 addr->base = noreg_gp;
2119 if(addr->index == NULL)
2120 addr->index = noreg_gp;
2121 if(addr->mem == NULL)
2122 addr->mem = new_NoMem();
2124 dbgi = get_irn_dbg_info(node);
2125 block = be_transform_node(src_block);
2126 if(get_mode_size_bits(mode) == 8) {
2127 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
2130 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
2133 set_address(new_node, addr);
2134 set_ia32_op_type(new_node, ia32_AddrModeD);
2135 set_ia32_ls_mode(new_node, mode);
2136 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2138 set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node);
2139 mem_proj = be_transform_node(am.mem_proj);
2140 set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node);
2145 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2146 ir_node *ptr, ir_mode *mode,
2147 construct_unop_dest_func *func)
2149 ir_graph *irg = current_ir_graph;
2150 ir_node *src_block = get_nodes_block(node);
2155 ia32_address_mode_t am;
2156 ia32_address_t *addr = &am.addr;
2157 memset(&am, 0, sizeof(am));
2159 if(!use_dest_am(src_block, op, mem, ptr, NULL))
2162 build_address(&am, op);
2164 dbgi = get_irn_dbg_info(node);
2165 block = be_transform_node(src_block);
2166 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
2167 set_address(new_node, addr);
2168 set_ia32_op_type(new_node, ia32_AddrModeD);
2169 set_ia32_ls_mode(new_node, mode);
2170 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2172 set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node);
2173 mem_proj = be_transform_node(am.mem_proj);
2174 set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node);
2179 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
2180 ir_mode *mode = get_irn_mode(node);
2181 ir_node *psi_true = get_Psi_val(node, 0);
2182 ir_node *psi_default = get_Psi_default(node);
2193 ia32_address_t addr;
2195 if(get_mode_size_bits(mode) != 8)
2198 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2200 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2206 build_address_ptr(&addr, ptr, mem);
2208 irg = current_ir_graph;
2209 dbgi = get_irn_dbg_info(node);
2210 block = get_nodes_block(node);
2211 new_block = be_transform_node(block);
2212 cond = get_Psi_cond(node, 0);
2213 flags = get_flags_node(cond, &pnc);
2214 new_mem = be_transform_node(mem);
2215 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2216 addr.index, addr.mem, flags, pnc, negated);
2217 set_address(new_node, &addr);
2218 set_ia32_op_type(new_node, ia32_AddrModeD);
2219 set_ia32_ls_mode(new_node, mode);
2220 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2225 static ir_node *try_create_dest_am(ir_node *node) {
2226 ir_node *val = get_Store_value(node);
2227 ir_node *mem = get_Store_mem(node);
2228 ir_node *ptr = get_Store_ptr(node);
2229 ir_mode *mode = get_irn_mode(val);
2230 unsigned bits = get_mode_size_bits(mode);
2235 /* handle only GP modes for now... */
2236 if(!ia32_mode_needs_gp_reg(mode))
2240 /* store must be the only user of the val node */
2241 if(get_irn_n_edges(val) > 1)
2243 /* skip pointless convs */
2245 ir_node *conv_op = get_Conv_op(val);
2246 ir_mode *pred_mode = get_irn_mode(conv_op);
2247 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2255 /* value must be in the same block */
2256 if(get_nodes_block(node) != get_nodes_block(val))
2259 switch (get_irn_opcode(val)) {
2261 op1 = get_Add_left(val);
2262 op2 = get_Add_right(val);
2263 if(is_Const_1(op2)) {
2264 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2265 new_rd_ia32_IncMem);
2267 } else if(is_Const_Minus_1(op2)) {
2268 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2269 new_rd_ia32_DecMem);
2272 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2273 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2274 match_dest_am | match_commutative |
2278 op1 = get_Sub_left(val);
2279 op2 = get_Sub_right(val);
2281 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2284 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2285 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2286 match_dest_am | match_immediate |
2290 op1 = get_And_left(val);
2291 op2 = get_And_right(val);
2292 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2293 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2294 match_dest_am | match_commutative |
2298 op1 = get_Or_left(val);
2299 op2 = get_Or_right(val);
2300 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2301 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2302 match_dest_am | match_commutative |
2306 op1 = get_Eor_left(val);
2307 op2 = get_Eor_right(val);
2308 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2309 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2310 match_dest_am | match_commutative |
2314 op1 = get_Shl_left(val);
2315 op2 = get_Shl_right(val);
2316 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2317 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2318 match_dest_am | match_immediate);
2321 op1 = get_Shr_left(val);
2322 op2 = get_Shr_right(val);
2323 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2324 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2325 match_dest_am | match_immediate);
2328 op1 = get_Shrs_left(val);
2329 op2 = get_Shrs_right(val);
2330 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2331 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2332 match_dest_am | match_immediate);
2335 op1 = get_Rotl_left(val);
2336 op2 = get_Rotl_right(val);
2337 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2338 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2339 match_dest_am | match_immediate);
2341 /* TODO: match ROR patterns... */
2343 new_node = try_create_SetMem(val, ptr, mem);
2346 op1 = get_Minus_op(val);
2347 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2350 /* should be lowered already */
2351 assert(mode != mode_b);
2352 op1 = get_Not_op(val);
2353 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2359 if(new_node != NULL) {
2360 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2361 get_irn_pinned(node) == op_pin_state_pinned) {
2362 set_irn_pinned(new_node, op_pin_state_pinned);
2369 static int is_float_to_int32_conv(const ir_node *node)
2371 ir_mode *mode = get_irn_mode(node);
2375 if(get_mode_size_bits(mode) != 32 || !ia32_mode_needs_gp_reg(mode))
2380 conv_op = get_Conv_op(node);
2381 conv_mode = get_irn_mode(conv_op);
2383 if(!mode_is_float(conv_mode))
2390 * Transform a Store(floatConst).
2392 * @return the created ia32 Store node
2394 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns) {
2395 ir_mode *mode = get_irn_mode(cns);
2396 int size = get_mode_size_bits(mode);
2397 tarval *tv = get_Const_tarval(cns);
2398 ir_node *block = get_nodes_block(node);
2399 ir_node *new_block = be_transform_node(block);
2400 ir_node *ptr = get_Store_ptr(node);
2401 ir_node *mem = get_Store_mem(node);
2402 ir_graph *irg = current_ir_graph;
2403 dbg_info *dbgi = get_irn_dbg_info(node);
2404 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2407 ia32_address_t addr;
2409 unsigned val = get_tarval_sub_bits(tv, 0) |
2410 (get_tarval_sub_bits(tv, 1) << 8) |
2411 (get_tarval_sub_bits(tv, 2) << 16) |
2412 (get_tarval_sub_bits(tv, 3) << 24);
2413 ir_node *imm = create_Immediate(NULL, 0, val);
2415 /* construct store address */
2416 memset(&addr, 0, sizeof(addr));
2417 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2419 if (addr.base == NULL) {
2422 addr.base = be_transform_node(addr.base);
2425 if (addr.index == NULL) {
2428 addr.index = be_transform_node(addr.index);
2430 addr.mem = be_transform_node(mem);
2432 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2433 addr.index, addr.mem, imm);
2435 set_irn_pinned(new_node, get_irn_pinned(node));
2436 set_ia32_op_type(new_node, ia32_AddrModeD);
2437 set_ia32_ls_mode(new_node, mode_Iu);
2439 set_address(new_node, &addr);
2441 /** add more stores if needed */
2443 unsigned val = get_tarval_sub_bits(tv, ofs) |
2444 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2445 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2446 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2447 ir_node *imm = create_Immediate(NULL, 0, val);
2450 addr.mem = new_node;
2452 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2453 addr.index, addr.mem, imm);
2455 set_irn_pinned(new_node, get_irn_pinned(node));
2456 set_ia32_op_type(new_node, ia32_AddrModeD);
2457 set_ia32_ls_mode(new_node, mode_Iu);
2459 set_address(new_node, &addr);
2464 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2469 * Generate a vfist or vfisttp instruction.
2471 static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index,
2472 ir_node *mem, ir_node *val, ir_node **fist)
2476 if (ia32_cg_config.use_fisttp) {
2477 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2478 if other users exists */
2479 const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
2480 ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val);
2481 ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res);
2482 be_new_Keep(reg_class, irg, block, 1, &value);
2484 new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M);
2487 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2490 new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode);
2496 * Transforms a normal Store.
2498 * @return the created ia32 Store node
2500 static ir_node *gen_normal_Store(ir_node *node)
2502 ir_node *val = get_Store_value(node);
2503 ir_mode *mode = get_irn_mode(val);
2504 ir_node *block = get_nodes_block(node);
2505 ir_node *new_block = be_transform_node(block);
2506 ir_node *ptr = get_Store_ptr(node);
2507 ir_node *mem = get_Store_mem(node);
2508 ir_graph *irg = current_ir_graph;
2509 dbg_info *dbgi = get_irn_dbg_info(node);
2510 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2511 ir_node *new_val, *new_node, *store;
2512 ia32_address_t addr;
2514 /* check for destination address mode */
2515 new_node = try_create_dest_am(node);
2516 if (new_node != NULL)
2519 /* construct store address */
2520 memset(&addr, 0, sizeof(addr));
2521 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2523 if (addr.base == NULL) {
2526 addr.base = be_transform_node(addr.base);
2529 if (addr.index == NULL) {
2532 addr.index = be_transform_node(addr.index);
2534 addr.mem = be_transform_node(mem);
2536 if (mode_is_float(mode)) {
2537 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2539 while (is_Conv(val) && mode == get_irn_mode(val)) {
2540 ir_node *op = get_Conv_op(val);
2541 if (!mode_is_float(get_irn_mode(op)))
2545 new_val = be_transform_node(val);
2546 if (ia32_cg_config.use_sse2) {
2547 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2548 addr.index, addr.mem, new_val);
2550 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2551 addr.index, addr.mem, new_val, mode);
2554 } else if (!ia32_cg_config.use_sse2 && is_float_to_int32_conv(val)) {
2555 val = get_Conv_op(val);
2557 /* We can skip ALL Convs (and strict-Convs) before stores. */
2558 while (is_Conv(val)) {
2559 val = get_Conv_op(val);
2561 new_val = be_transform_node(val);
2562 new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store);
2564 new_val = create_immediate_or_transform(val, 0);
2565 assert(mode != mode_b);
2567 if (get_mode_size_bits(mode) == 8) {
2568 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2569 addr.index, addr.mem, new_val);
2571 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2572 addr.index, addr.mem, new_val);
2577 set_irn_pinned(store, get_irn_pinned(node));
2578 set_ia32_op_type(store, ia32_AddrModeD);
2579 set_ia32_ls_mode(store, mode);
2581 set_address(store, &addr);
2582 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2588 * Transforms a Store.
2590 * @return the created ia32 Store node
2592 static ir_node *gen_Store(ir_node *node)
2594 ir_node *val = get_Store_value(node);
2595 ir_mode *mode = get_irn_mode(val);
2597 if (mode_is_float(mode) && is_Const(val)) {
2600 /* we are storing a floating point constant */
2601 if (ia32_cg_config.use_sse2) {
2602 transform = !is_simple_sse_Const(val);
2604 transform = !is_simple_x87_Const(val);
2607 return gen_float_const_Store(node, val);
2609 return gen_normal_Store(node);
2613 * Transforms a Switch.
2615 * @return the created ia32 SwitchJmp node
2617 static ir_node *create_Switch(ir_node *node)
2619 ir_graph *irg = current_ir_graph;
2620 dbg_info *dbgi = get_irn_dbg_info(node);
2621 ir_node *block = be_transform_node(get_nodes_block(node));
2622 ir_node *sel = get_Cond_selector(node);
2623 ir_node *new_sel = be_transform_node(sel);
2624 int switch_min = INT_MAX;
2625 int switch_max = INT_MIN;
2626 long default_pn = get_Cond_defaultProj(node);
2628 const ir_edge_t *edge;
2630 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2632 /* determine the smallest switch case value */
2633 foreach_out_edge(node, edge) {
2634 ir_node *proj = get_edge_src_irn(edge);
2635 long pn = get_Proj_proj(proj);
2636 if(pn == default_pn)
2645 if((unsigned) (switch_max - switch_min) > 256000) {
2646 panic("Size of switch %+F bigger than 256000", node);
2649 if (switch_min != 0) {
2650 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2652 /* if smallest switch case is not 0 we need an additional sub */
2653 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2654 add_ia32_am_offs_int(new_sel, -switch_min);
2655 set_ia32_op_type(new_sel, ia32_AddrModeS);
2657 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2660 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
2661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2667 * Transform a Cond node.
2669 static ir_node *gen_Cond(ir_node *node) {
2670 ir_node *block = get_nodes_block(node);
2671 ir_node *new_block = be_transform_node(block);
2672 ir_graph *irg = current_ir_graph;
2673 dbg_info *dbgi = get_irn_dbg_info(node);
2674 ir_node *sel = get_Cond_selector(node);
2675 ir_mode *sel_mode = get_irn_mode(sel);
2676 ir_node *flags = NULL;
2680 if (sel_mode != mode_b) {
2681 return create_Switch(node);
2684 /* we get flags from a Cmp */
2685 flags = get_flags_node(sel, &pnc);
2687 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2688 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2694 * Transforms a CopyB node.
2696 * @return The transformed node.
2698 static ir_node *gen_CopyB(ir_node *node) {
2699 ir_node *block = be_transform_node(get_nodes_block(node));
2700 ir_node *src = get_CopyB_src(node);
2701 ir_node *new_src = be_transform_node(src);
2702 ir_node *dst = get_CopyB_dst(node);
2703 ir_node *new_dst = be_transform_node(dst);
2704 ir_node *mem = get_CopyB_mem(node);
2705 ir_node *new_mem = be_transform_node(mem);
2706 ir_node *res = NULL;
2707 ir_graph *irg = current_ir_graph;
2708 dbg_info *dbgi = get_irn_dbg_info(node);
2709 int size = get_type_size_bytes(get_CopyB_type(node));
2712 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2713 /* then we need the size explicitly in ECX. */
2714 if (size >= 32 * 4) {
2715 rem = size & 0x3; /* size % 4 */
2718 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2719 add_irn_dep(res, get_irg_frame(irg));
2721 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2724 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2727 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2730 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2735 static ir_node *gen_be_Copy(ir_node *node)
2737 ir_node *new_node = be_duplicate_node(node);
2738 ir_mode *mode = get_irn_mode(new_node);
2740 if (ia32_mode_needs_gp_reg(mode)) {
2741 set_irn_mode(new_node, mode_Iu);
2747 static ir_node *create_Fucom(ir_node *node)
2749 ir_graph *irg = current_ir_graph;
2750 dbg_info *dbgi = get_irn_dbg_info(node);
2751 ir_node *block = get_nodes_block(node);
2752 ir_node *new_block = be_transform_node(block);
2753 ir_node *left = get_Cmp_left(node);
2754 ir_node *new_left = be_transform_node(left);
2755 ir_node *right = get_Cmp_right(node);
2759 if(ia32_cg_config.use_fucomi) {
2760 new_right = be_transform_node(right);
2761 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2763 set_ia32_commutative(new_node);
2764 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2766 if(ia32_cg_config.use_ftst && is_Const_0(right)) {
2767 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2770 new_right = be_transform_node(right);
2771 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2775 set_ia32_commutative(new_node);
2777 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2779 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2780 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2786 static ir_node *create_Ucomi(ir_node *node)
2788 ir_graph *irg = current_ir_graph;
2789 dbg_info *dbgi = get_irn_dbg_info(node);
2790 ir_node *src_block = get_nodes_block(node);
2791 ir_node *new_block = be_transform_node(src_block);
2792 ir_node *left = get_Cmp_left(node);
2793 ir_node *right = get_Cmp_right(node);
2795 ia32_address_mode_t am;
2796 ia32_address_t *addr = &am.addr;
2798 match_arguments(&am, src_block, left, right, NULL,
2799 match_commutative | match_am);
2801 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2802 addr->mem, am.new_op1, am.new_op2,
2804 set_am_attributes(new_node, &am);
2806 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2808 new_node = fix_mem_proj(new_node, &am);
2814 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2815 * to fold an and into a test node
2817 static int can_fold_test_and(ir_node *node)
2819 const ir_edge_t *edge;
2821 /** we can only have eq and lg projs */
2822 foreach_out_edge(node, edge) {
2823 ir_node *proj = get_edge_src_irn(edge);
2824 pn_Cmp pnc = get_Proj_proj(proj);
2825 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2833 * Generate code for a Cmp.
2835 static ir_node *gen_Cmp(ir_node *node)
2837 ir_graph *irg = current_ir_graph;
2838 dbg_info *dbgi = get_irn_dbg_info(node);
2839 ir_node *block = get_nodes_block(node);
2840 ir_node *new_block = be_transform_node(block);
2841 ir_node *left = get_Cmp_left(node);
2842 ir_node *right = get_Cmp_right(node);
2843 ir_mode *cmp_mode = get_irn_mode(left);
2845 ia32_address_mode_t am;
2846 ia32_address_t *addr = &am.addr;
2849 if(mode_is_float(cmp_mode)) {
2850 if (ia32_cg_config.use_sse2) {
2851 return create_Ucomi(node);
2853 return create_Fucom(node);
2857 assert(ia32_mode_needs_gp_reg(cmp_mode));
2859 /* we prefer the Test instruction where possible except cases where
2860 * we can use SourceAM */
2861 cmp_unsigned = !mode_is_signed(cmp_mode);
2862 if (is_Const_0(right)) {
2864 get_irn_n_edges(left) == 1 &&
2865 can_fold_test_and(node)) {
2866 /* Test(and_left, and_right) */
2867 ir_node *and_left = get_And_left(left);
2868 ir_node *and_right = get_And_right(left);
2869 ir_mode *mode = get_irn_mode(and_left);
2871 match_arguments(&am, block, and_left, and_right, NULL,
2873 match_am | match_8bit_am | match_16bit_am |
2874 match_am_and_immediates | match_immediate |
2875 match_8bit | match_16bit);
2876 if (get_mode_size_bits(mode) == 8) {
2877 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2878 addr->index, addr->mem, am.new_op1,
2879 am.new_op2, am.ins_permuted,
2882 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2883 addr->index, addr->mem, am.new_op1,
2884 am.new_op2, am.ins_permuted, cmp_unsigned);
2887 match_arguments(&am, block, NULL, left, NULL,
2888 match_am | match_8bit_am | match_16bit_am |
2889 match_8bit | match_16bit);
2890 if (am.op_type == ia32_AddrModeS) {
2892 ir_node *imm_zero = try_create_Immediate(right, 0);
2893 if (get_mode_size_bits(cmp_mode) == 8) {
2894 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2895 addr->index, addr->mem, am.new_op2,
2896 imm_zero, am.ins_permuted,
2899 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2900 addr->index, addr->mem, am.new_op2,
2901 imm_zero, am.ins_permuted, cmp_unsigned);
2904 /* Test(left, left) */
2905 if (get_mode_size_bits(cmp_mode) == 8) {
2906 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2907 addr->index, addr->mem, am.new_op2,
2908 am.new_op2, am.ins_permuted,
2911 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2912 addr->index, addr->mem, am.new_op2,
2913 am.new_op2, am.ins_permuted,
2919 /* Cmp(left, right) */
2920 match_arguments(&am, block, left, right, NULL,
2921 match_commutative | match_am | match_8bit_am |
2922 match_16bit_am | match_am_and_immediates |
2923 match_immediate | match_8bit | match_16bit);
2924 if (get_mode_size_bits(cmp_mode) == 8) {
2925 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2926 addr->index, addr->mem, am.new_op1,
2927 am.new_op2, am.ins_permuted,
2930 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2931 addr->index, addr->mem, am.new_op1,
2932 am.new_op2, am.ins_permuted, cmp_unsigned);
2935 set_am_attributes(new_node, &am);
2936 assert(cmp_mode != NULL);
2937 set_ia32_ls_mode(new_node, cmp_mode);
2939 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2941 new_node = fix_mem_proj(new_node, &am);
2946 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2949 ir_graph *irg = current_ir_graph;
2950 dbg_info *dbgi = get_irn_dbg_info(node);
2951 ir_node *block = get_nodes_block(node);
2952 ir_node *new_block = be_transform_node(block);
2953 ir_node *val_true = get_Psi_val(node, 0);
2954 ir_node *val_false = get_Psi_default(node);
2956 match_flags_t match_flags;
2957 ia32_address_mode_t am;
2958 ia32_address_t *addr;
2960 assert(ia32_cg_config.use_cmov);
2961 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
2965 match_flags = match_commutative | match_am | match_16bit_am |
2968 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2970 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2971 addr->mem, am.new_op1, am.new_op2, new_flags,
2972 am.ins_permuted, pnc);
2973 set_am_attributes(new_node, &am);
2975 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2977 new_node = fix_mem_proj(new_node, &am);
2983 * Creates a ia32 Setcc instruction.
2985 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2986 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2989 ir_graph *irg = current_ir_graph;
2990 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2991 ir_node *nomem = new_NoMem();
2992 ir_mode *mode = get_irn_mode(orig_node);
2995 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2996 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2998 /* we might need to conv the result up */
2999 if (get_mode_size_bits(mode) > 8) {
3000 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
3001 nomem, new_node, mode_Bu);
3002 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
3009 * Create instruction for an unsigned Difference or Zero.
3011 static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) {
3012 ir_graph *irg = current_ir_graph;
3013 ir_mode *mode = get_irn_mode(psi);
3014 ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem;
3017 new_node = gen_binop(psi, a, b, new_rd_ia32_Sub,
3018 match_mode_neutral | match_am | match_immediate | match_two_users);
3020 block = get_nodes_block(new_node);
3022 if (is_Proj(new_node)) {
3023 sub = get_Proj_pred(new_node);
3024 assert(is_ia32_Sub(sub));
3027 set_irn_mode(sub, mode_T);
3028 new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res);
3030 eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
3032 dbgi = get_irn_dbg_info(psi);
3033 noreg = ia32_new_NoReg_gp(env_cg);
3034 tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block);
3035 nomem = new_NoMem();
3036 sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags);
3038 new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb);
3039 set_ia32_commutative(new_node);
3044 * Transforms a Psi node into CMov.
3046 * @return The transformed node.
3048 static ir_node *gen_Psi(ir_node *node)
3050 dbg_info *dbgi = get_irn_dbg_info(node);
3051 ir_node *block = get_nodes_block(node);
3052 ir_node *new_block = be_transform_node(block);
3053 ir_node *psi_true = get_Psi_val(node, 0);
3054 ir_node *psi_default = get_Psi_default(node);
3055 ir_node *cond = get_Psi_cond(node, 0);
3056 ir_mode *mode = get_irn_mode(node);
3059 assert(get_Psi_n_conds(node) == 1);
3060 assert(get_irn_mode(cond) == mode_b);
3062 /* Note: a Psi node uses a Load two times IFF it's used in the compare AND in the result */
3063 if (mode_is_float(mode)) {
3064 ir_node *cmp = get_Proj_pred(cond);
3065 ir_node *cmp_left = get_Cmp_left(cmp);
3066 ir_node *cmp_right = get_Cmp_right(cmp);
3067 pn_Cmp pnc = get_Proj_proj(cond);
3069 if (ia32_cg_config.use_sse2) {
3070 if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
3071 if (cmp_left == psi_true && cmp_right == psi_default) {
3072 /* psi(a <= b, a, b) => MIN */
3073 return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
3074 match_commutative | match_am | match_two_users);
3075 } else if (cmp_left == psi_default && cmp_right == psi_true) {
3076 /* psi(a <= b, b, a) => MAX */
3077 return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
3078 match_commutative | match_am | match_two_users);
3080 } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
3081 if (cmp_left == psi_true && cmp_right == psi_default) {
3082 /* psi(a >= b, a, b) => MAX */
3083 return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
3084 match_commutative | match_am | match_two_users);
3085 } else if (cmp_left == psi_default && cmp_right == psi_true) {
3086 /* psi(a >= b, b, a) => MIN */
3087 return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
3088 match_commutative | match_am | match_two_users);
3092 panic("cannot transform floating point Psi");
3098 assert(ia32_mode_needs_gp_reg(mode));
3100 if (is_Proj(cond)) {
3101 ir_node *cmp = get_Proj_pred(cond);
3103 ir_node *cmp_left = get_Cmp_left(cmp);
3104 ir_node *cmp_right = get_Cmp_right(cmp);
3105 pn_Cmp pnc = get_Proj_proj(cond);
3107 /* check for unsigned Doz first */
3108 if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
3109 is_Const_0(psi_default) && is_Sub(psi_true) &&
3110 get_Sub_left(psi_true) == cmp_left && get_Sub_right(psi_true) == cmp_right) {
3111 /* Psi(a >=u b, a - b, 0) unsigned Doz */
3112 return create_Doz(node, cmp_left, cmp_right);
3113 } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
3114 is_Const_0(psi_true) && is_Sub(psi_default) &&
3115 get_Sub_left(psi_default) == cmp_left && get_Sub_right(psi_default) == cmp_right) {
3116 /* Psi(a <=u b, 0, a - b) unsigned Doz */
3117 return create_Doz(node, cmp_left, cmp_right);
3122 flags = get_flags_node(cond, &pnc);
3124 if (is_Const(psi_true) && is_Const(psi_default)) {
3125 /* both are const, good */
3126 if (is_Const_1(psi_true) && is_Const_0(psi_default)) {
3127 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
3128 } else if (is_Const_0(psi_true) && is_Const_1(psi_default)) {
3129 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1);
3131 /* Not that simple. */
3136 new_node = create_CMov(node, cond, flags, pnc);
3144 * Create a conversion from x87 state register to general purpose.
3146 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
3147 ir_node *block = be_transform_node(get_nodes_block(node));
3148 ir_node *op = get_Conv_op(node);
3149 ir_node *new_op = be_transform_node(op);
3150 ia32_code_gen_t *cg = env_cg;
3151 ir_graph *irg = current_ir_graph;
3152 dbg_info *dbgi = get_irn_dbg_info(node);
3153 ir_node *noreg = ia32_new_NoReg_gp(cg);
3154 ir_mode *mode = get_irn_mode(node);
3155 ir_node *fist, *load, *mem;
3157 mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist);
3158 set_irn_pinned(fist, op_pin_state_floats);
3159 set_ia32_use_frame(fist);
3160 set_ia32_op_type(fist, ia32_AddrModeD);
3162 assert(get_mode_size_bits(mode) <= 32);
3163 /* exception we can only store signed 32 bit integers, so for unsigned
3164 we store a 64bit (signed) integer and load the lower bits */
3165 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3166 set_ia32_ls_mode(fist, mode_Ls);
3168 set_ia32_ls_mode(fist, mode_Is);
3170 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
3173 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem);
3175 set_irn_pinned(load, op_pin_state_floats);
3176 set_ia32_use_frame(load);
3177 set_ia32_op_type(load, ia32_AddrModeS);
3178 set_ia32_ls_mode(load, mode_Is);
3179 if(get_ia32_ls_mode(fist) == mode_Ls) {
3180 ia32_attr_t *attr = get_ia32_attr(load);
3181 attr->data.need_64bit_stackent = 1;
3183 ia32_attr_t *attr = get_ia32_attr(load);
3184 attr->data.need_32bit_stackent = 1;
3186 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
3188 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
3192 * Creates a x87 strict Conv by placing a Sore and a Load
3194 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3196 ir_node *block = get_nodes_block(node);
3197 ir_graph *irg = current_ir_graph;
3198 dbg_info *dbgi = get_irn_dbg_info(node);
3199 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3200 ir_node *nomem = new_NoMem();
3201 ir_node *frame = get_irg_frame(irg);
3202 ir_node *store, *load;
3205 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
3207 set_ia32_use_frame(store);
3208 set_ia32_op_type(store, ia32_AddrModeD);
3209 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
3211 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
3213 set_ia32_use_frame(load);
3214 set_ia32_op_type(load, ia32_AddrModeS);
3215 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
3217 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
3222 * Create a conversion from general purpose to x87 register
3224 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
3225 ir_node *src_block = get_nodes_block(node);
3226 ir_node *block = be_transform_node(src_block);
3227 ir_graph *irg = current_ir_graph;
3228 dbg_info *dbgi = get_irn_dbg_info(node);
3229 ir_node *op = get_Conv_op(node);
3230 ir_node *new_op = NULL;
3234 ir_mode *store_mode;
3240 /* fild can use source AM if the operand is a signed 32bit integer */
3241 if (src_mode == mode_Is) {
3242 ia32_address_mode_t am;
3244 match_arguments(&am, src_block, NULL, op, NULL,
3245 match_am | match_try_am);
3246 if (am.op_type == ia32_AddrModeS) {
3247 ia32_address_t *addr = &am.addr;
3249 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
3250 addr->index, addr->mem);
3251 new_node = new_r_Proj(irg, block, fild, mode_vfp,
3254 set_am_attributes(fild, &am);
3255 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
3257 fix_mem_proj(fild, &am);
3262 if(new_op == NULL) {
3263 new_op = be_transform_node(op);
3266 noreg = ia32_new_NoReg_gp(env_cg);
3267 nomem = new_NoMem();
3268 mode = get_irn_mode(op);
3270 /* first convert to 32 bit signed if necessary */
3271 src_bits = get_mode_size_bits(src_mode);
3272 if (src_bits == 8) {
3273 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
3275 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3277 } else if (src_bits < 32) {
3278 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
3280 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3284 assert(get_mode_size_bits(mode) == 32);
3287 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
3290 set_ia32_use_frame(store);
3291 set_ia32_op_type(store, ia32_AddrModeD);
3292 set_ia32_ls_mode(store, mode_Iu);
3294 /* exception for 32bit unsigned, do a 64bit spill+load */
3295 if(!mode_is_signed(mode)) {
3298 ir_node *zero_const = create_Immediate(NULL, 0, 0);
3300 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
3301 get_irg_frame(irg), noreg, nomem,
3304 set_ia32_use_frame(zero_store);
3305 set_ia32_op_type(zero_store, ia32_AddrModeD);
3306 add_ia32_am_offs_int(zero_store, 4);
3307 set_ia32_ls_mode(zero_store, mode_Iu);
3312 store = new_rd_Sync(dbgi, irg, block, 2, in);
3313 store_mode = mode_Ls;
3315 store_mode = mode_Is;
3319 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
3321 set_ia32_use_frame(fild);
3322 set_ia32_op_type(fild, ia32_AddrModeS);
3323 set_ia32_ls_mode(fild, store_mode);
3325 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
3331 * Create a conversion from one integer mode into another one
3333 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3334 dbg_info *dbgi, ir_node *block, ir_node *op,
3337 ir_graph *irg = current_ir_graph;
3338 int src_bits = get_mode_size_bits(src_mode);
3339 int tgt_bits = get_mode_size_bits(tgt_mode);
3340 ir_node *new_block = be_transform_node(block);
3342 ir_mode *smaller_mode;
3344 ia32_address_mode_t am;
3345 ia32_address_t *addr = &am.addr;
3348 if (src_bits < tgt_bits) {
3349 smaller_mode = src_mode;
3350 smaller_bits = src_bits;
3352 smaller_mode = tgt_mode;
3353 smaller_bits = tgt_bits;
3356 #ifdef DEBUG_libfirm
3358 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3363 match_arguments(&am, block, NULL, op, NULL,
3364 match_8bit | match_16bit |
3365 match_am | match_8bit_am | match_16bit_am);
3366 if (smaller_bits == 8) {
3367 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
3368 addr->index, addr->mem, am.new_op2,
3371 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
3372 addr->index, addr->mem, am.new_op2,
3375 set_am_attributes(new_node, &am);
3376 /* match_arguments assume that out-mode = in-mode, this isn't true here
3378 set_ia32_ls_mode(new_node, smaller_mode);
3379 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3380 new_node = fix_mem_proj(new_node, &am);
3385 * Transforms a Conv node.
3387 * @return The created ia32 Conv node
3389 static ir_node *gen_Conv(ir_node *node) {
3390 ir_node *block = get_nodes_block(node);
3391 ir_node *new_block = be_transform_node(block);
3392 ir_node *op = get_Conv_op(node);
3393 ir_node *new_op = NULL;
3394 ir_graph *irg = current_ir_graph;
3395 dbg_info *dbgi = get_irn_dbg_info(node);
3396 ir_mode *src_mode = get_irn_mode(op);
3397 ir_mode *tgt_mode = get_irn_mode(node);
3398 int src_bits = get_mode_size_bits(src_mode);
3399 int tgt_bits = get_mode_size_bits(tgt_mode);
3400 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3401 ir_node *nomem = new_rd_NoMem(irg);
3402 ir_node *res = NULL;
3404 if (src_mode == mode_b) {
3405 assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode));
3406 /* nothing to do, we already model bools as 0/1 ints */
3407 return be_transform_node(op);
3410 if (src_mode == tgt_mode) {
3411 if (get_Conv_strict(node)) {
3412 if (ia32_cg_config.use_sse2) {
3413 /* when we are in SSE mode, we can kill all strict no-op conversion */
3414 return be_transform_node(op);
3417 /* this should be optimized already, but who knows... */
3418 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3419 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3420 return be_transform_node(op);
3424 if (mode_is_float(src_mode)) {
3425 new_op = be_transform_node(op);
3426 /* we convert from float ... */
3427 if (mode_is_float(tgt_mode)) {
3428 if(src_mode == mode_E && tgt_mode == mode_D
3429 && !get_Conv_strict(node)) {
3430 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3435 if (ia32_cg_config.use_sse2) {
3436 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3437 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3439 set_ia32_ls_mode(res, tgt_mode);
3441 if(get_Conv_strict(node)) {
3442 res = gen_x87_strict_conv(tgt_mode, new_op);
3443 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3446 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3451 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3452 if (ia32_cg_config.use_sse2) {
3453 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3455 set_ia32_ls_mode(res, src_mode);
3457 return gen_x87_fp_to_gp(node);
3461 /* we convert from int ... */
3462 if (mode_is_float(tgt_mode)) {
3464 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3465 if (ia32_cg_config.use_sse2) {
3466 new_op = be_transform_node(op);
3467 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3469 set_ia32_ls_mode(res, tgt_mode);
3471 res = gen_x87_gp_to_fp(node, src_mode);
3472 if(get_Conv_strict(node)) {
3473 res = gen_x87_strict_conv(tgt_mode, res);
3474 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3475 ia32_get_old_node_name(env_cg, node));
3479 } else if(tgt_mode == mode_b) {
3480 /* mode_b lowering already took care that we only have 0/1 values */
3481 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3482 src_mode, tgt_mode));
3483 return be_transform_node(op);
3486 if (src_bits == tgt_bits) {
3487 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3488 src_mode, tgt_mode));
3489 return be_transform_node(op);
3492 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3500 static int check_immediate_constraint(long val, char immediate_constraint_type)
3502 switch (immediate_constraint_type) {
3506 return val >= 0 && val <= 32;
3508 return val >= 0 && val <= 63;
3510 return val >= -128 && val <= 127;
3512 return val == 0xff || val == 0xffff;
3514 return val >= 0 && val <= 3;
3516 return val >= 0 && val <= 255;
3518 return val >= 0 && val <= 127;
3522 panic("Invalid immediate constraint found");
3526 static ir_node *try_create_Immediate(ir_node *node,
3527 char immediate_constraint_type)
3530 tarval *offset = NULL;
3531 int offset_sign = 0;
3533 ir_entity *symconst_ent = NULL;
3534 int symconst_sign = 0;
3536 ir_node *cnst = NULL;
3537 ir_node *symconst = NULL;
3540 mode = get_irn_mode(node);
3541 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3545 if(is_Minus(node)) {
3547 node = get_Minus_op(node);
3550 if(is_Const(node)) {
3553 offset_sign = minus;
3554 } else if(is_SymConst(node)) {
3557 symconst_sign = minus;
3558 } else if(is_Add(node)) {
3559 ir_node *left = get_Add_left(node);
3560 ir_node *right = get_Add_right(node);
3561 if(is_Const(left) && is_SymConst(right)) {
3564 symconst_sign = minus;
3565 offset_sign = minus;
3566 } else if(is_SymConst(left) && is_Const(right)) {
3569 symconst_sign = minus;
3570 offset_sign = minus;
3572 } else if(is_Sub(node)) {
3573 ir_node *left = get_Sub_left(node);
3574 ir_node *right = get_Sub_right(node);
3575 if(is_Const(left) && is_SymConst(right)) {
3578 symconst_sign = !minus;
3579 offset_sign = minus;
3580 } else if(is_SymConst(left) && is_Const(right)) {
3583 symconst_sign = minus;
3584 offset_sign = !minus;
3591 offset = get_Const_tarval(cnst);
3592 if(tarval_is_long(offset)) {
3593 val = get_tarval_long(offset);
3595 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3600 if(!check_immediate_constraint(val, immediate_constraint_type))
3603 if(symconst != NULL) {
3604 if(immediate_constraint_type != 0) {
3605 /* we need full 32bits for symconsts */
3609 /* unfortunately the assembler/linker doesn't support -symconst */
3613 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3615 symconst_ent = get_SymConst_entity(symconst);
3617 if(cnst == NULL && symconst == NULL)
3620 if(offset_sign && offset != NULL) {
3621 offset = tarval_neg(offset);
3624 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3629 static ir_node *create_immediate_or_transform(ir_node *node,
3630 char immediate_constraint_type)
3632 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3633 if (new_node == NULL) {
3634 new_node = be_transform_node(node);
3639 static const arch_register_req_t no_register_req = {
3640 arch_register_req_type_none,
3641 NULL, /* regclass */
3642 NULL, /* limit bitset */
3644 0 /* different pos */
3648 * An assembler constraint.
3650 typedef struct constraint_t constraint_t;
3651 struct constraint_t {
3654 const arch_register_req_t **out_reqs;
3656 const arch_register_req_t *req;
3657 unsigned immediate_possible;
3658 char immediate_type;
3661 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3663 int immediate_possible = 0;
3664 char immediate_type = 0;
3665 unsigned limited = 0;
3666 const arch_register_class_t *cls = NULL;
3667 ir_graph *irg = current_ir_graph;
3668 struct obstack *obst = get_irg_obstack(irg);
3669 arch_register_req_t *req;
3670 unsigned *limited_ptr = NULL;
3674 /* TODO: replace all the asserts with nice error messages */
3677 /* a memory constraint: no need to do anything in backend about it
3678 * (the dependencies are already respected by the memory edge of
3680 constraint->req = &no_register_req;
3692 assert(cls == NULL ||
3693 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3694 cls = &ia32_reg_classes[CLASS_ia32_gp];
3695 limited |= 1 << REG_EAX;
3698 assert(cls == NULL ||
3699 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3700 cls = &ia32_reg_classes[CLASS_ia32_gp];
3701 limited |= 1 << REG_EBX;
3704 assert(cls == NULL ||
3705 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3706 cls = &ia32_reg_classes[CLASS_ia32_gp];
3707 limited |= 1 << REG_ECX;
3710 assert(cls == NULL ||
3711 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3712 cls = &ia32_reg_classes[CLASS_ia32_gp];
3713 limited |= 1 << REG_EDX;
3716 assert(cls == NULL ||
3717 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3718 cls = &ia32_reg_classes[CLASS_ia32_gp];
3719 limited |= 1 << REG_EDI;
3722 assert(cls == NULL ||
3723 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3724 cls = &ia32_reg_classes[CLASS_ia32_gp];
3725 limited |= 1 << REG_ESI;
3728 case 'q': /* q means lower part of the regs only, this makes no
3729 * difference to Q for us (we only assigne whole registers) */
3730 assert(cls == NULL ||
3731 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3732 cls = &ia32_reg_classes[CLASS_ia32_gp];
3733 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3737 assert(cls == NULL ||
3738 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3739 cls = &ia32_reg_classes[CLASS_ia32_gp];
3740 limited |= 1 << REG_EAX | 1 << REG_EDX;
3743 assert(cls == NULL ||
3744 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3745 cls = &ia32_reg_classes[CLASS_ia32_gp];
3746 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3747 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3754 assert(cls == NULL);
3755 cls = &ia32_reg_classes[CLASS_ia32_gp];
3761 /* TODO: mark values so the x87 simulator knows about t and u */
3762 assert(cls == NULL);
3763 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3768 assert(cls == NULL);
3769 /* TODO: check that sse2 is supported */
3770 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3780 assert(!immediate_possible);
3781 immediate_possible = 1;
3782 immediate_type = *c;
3786 assert(!immediate_possible);
3787 immediate_possible = 1;
3791 assert(!immediate_possible && cls == NULL);
3792 immediate_possible = 1;
3793 cls = &ia32_reg_classes[CLASS_ia32_gp];
3806 assert(constraint->is_in && "can only specify same constraint "
3809 sscanf(c, "%d%n", &same_as, &p);
3819 /* memory constraint no need to do anything in backend about it
3820 * (the dependencies are already respected by the memory edge of
3822 constraint->req = &no_register_req;
3825 case 'E': /* no float consts yet */
3826 case 'F': /* no float consts yet */
3827 case 's': /* makes no sense on x86 */
3828 case 'X': /* we can't support that in firm */
3829 case '<': /* no autodecrement on x86 */
3830 case '>': /* no autoincrement on x86 */
3831 case 'C': /* sse constant not supported yet */
3832 case 'G': /* 80387 constant not supported yet */
3833 case 'y': /* we don't support mmx registers yet */
3834 case 'Z': /* not available in 32 bit mode */
3835 case 'e': /* not available in 32 bit mode */
3836 panic("unsupported asm constraint '%c' found in (%+F)",
3837 *c, current_ir_graph);
3840 panic("unknown asm constraint '%c' found in (%+F)", *c,
3848 const arch_register_req_t *other_constr;
3850 assert(cls == NULL && "same as and register constraint not supported");
3851 assert(!immediate_possible && "same as and immediate constraint not "
3853 assert(same_as < constraint->n_outs && "wrong constraint number in "
3854 "same_as constraint");
3856 other_constr = constraint->out_reqs[same_as];
3858 req = obstack_alloc(obst, sizeof(req[0]));
3859 req->cls = other_constr->cls;
3860 req->type = arch_register_req_type_should_be_same;
3861 req->limited = NULL;
3862 req->other_same = 1U << pos;
3863 req->other_different = 0;
3865 /* switch constraints. This is because in firm we have same_as
3866 * constraints on the output constraints while in the gcc asm syntax
3867 * they are specified on the input constraints */
3868 constraint->req = other_constr;
3869 constraint->out_reqs[same_as] = req;
3870 constraint->immediate_possible = 0;
3874 if(immediate_possible && cls == NULL) {
3875 cls = &ia32_reg_classes[CLASS_ia32_gp];
3877 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3878 assert(cls != NULL);
3880 if(immediate_possible) {
3881 assert(constraint->is_in
3882 && "immediate make no sense for output constraints");
3884 /* todo: check types (no float input on 'r' constrained in and such... */
3887 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3888 limited_ptr = (unsigned*) (req+1);
3890 req = obstack_alloc(obst, sizeof(req[0]));
3892 memset(req, 0, sizeof(req[0]));
3895 req->type = arch_register_req_type_limited;
3896 *limited_ptr = limited;
3897 req->limited = limited_ptr;
3899 req->type = arch_register_req_type_normal;
3903 constraint->req = req;
3904 constraint->immediate_possible = immediate_possible;
3905 constraint->immediate_type = immediate_type;
3908 const arch_register_t *ia32_get_clobber_register(const char *clobber)
3910 const arch_register_t *reg = NULL;
3913 const arch_register_class_t *cls;
3915 /* TODO: construct a hashmap instead of doing linear search for clobber
3917 for(c = 0; c < N_CLASSES; ++c) {
3918 cls = & ia32_reg_classes[c];
3919 for(r = 0; r < cls->n_regs; ++r) {
3920 const arch_register_t *temp_reg = arch_register_for_index(cls, r);
3921 if(strcmp(temp_reg->name, clobber) == 0
3922 || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
3934 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3935 const char *clobber)
3937 ir_graph *irg = get_irn_irg(node);
3938 struct obstack *obst = get_irg_obstack(irg);
3939 const arch_register_t *reg = ia32_get_clobber_register(clobber);
3940 arch_register_req_t *req;
3946 panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
3950 assert(reg->index < 32);
3952 limited = obstack_alloc(obst, sizeof(limited[0]));
3953 *limited = 1 << reg->index;
3955 req = obstack_alloc(obst, sizeof(req[0]));
3956 memset(req, 0, sizeof(req[0]));
3957 req->type = arch_register_req_type_limited;
3958 req->cls = arch_register_get_class(reg);
3959 req->limited = limited;
3961 constraint->req = req;
3962 constraint->immediate_possible = 0;
3963 constraint->immediate_type = 0;
3966 static int is_memory_op(const ir_asm_constraint *constraint)
3968 ident *id = constraint->constraint;
3969 const char *str = get_id_str(id);
3972 for(c = str; *c != '\0'; ++c) {
3981 * generates code for a ASM node
3983 static ir_node *gen_ASM(ir_node *node)
3986 ir_graph *irg = current_ir_graph;
3987 ir_node *block = get_nodes_block(node);
3988 ir_node *new_block = be_transform_node(block);
3989 dbg_info *dbgi = get_irn_dbg_info(node);
3993 int n_out_constraints;
3995 const arch_register_req_t **out_reg_reqs;
3996 const arch_register_req_t **in_reg_reqs;
3997 ia32_asm_reg_t *register_map;
3998 unsigned reg_map_size = 0;
3999 struct obstack *obst;
4000 const ir_asm_constraint *in_constraints;
4001 const ir_asm_constraint *out_constraints;
4003 constraint_t parsed_constraint;
4005 arity = get_irn_arity(node);
4006 in = alloca(arity * sizeof(in[0]));
4007 memset(in, 0, arity * sizeof(in[0]));
4009 n_out_constraints = get_ASM_n_output_constraints(node);
4010 n_clobbers = get_ASM_n_clobbers(node);
4011 out_arity = n_out_constraints + n_clobbers;
4012 /* hack to keep space for mem proj */
4016 in_constraints = get_ASM_input_constraints(node);
4017 out_constraints = get_ASM_output_constraints(node);
4018 clobbers = get_ASM_clobbers(node);
4020 /* construct output constraints */
4021 obst = get_irg_obstack(irg);
4022 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
4023 parsed_constraint.out_reqs = out_reg_reqs;
4024 parsed_constraint.n_outs = n_out_constraints;
4025 parsed_constraint.is_in = 0;
4027 for(i = 0; i < out_arity; ++i) {
4030 if(i < n_out_constraints) {
4031 const ir_asm_constraint *constraint = &out_constraints[i];
4032 c = get_id_str(constraint->constraint);
4033 parse_asm_constraint(i, &parsed_constraint, c);
4035 if(constraint->pos > reg_map_size)
4036 reg_map_size = constraint->pos;
4038 out_reg_reqs[i] = parsed_constraint.req;
4039 } else if(i < out_arity - 1) {
4040 ident *glob_id = clobbers [i - n_out_constraints];
4041 assert(glob_id != NULL);
4042 c = get_id_str(glob_id);
4043 parse_clobber(node, i, &parsed_constraint, c);
4045 out_reg_reqs[i+1] = parsed_constraint.req;
4049 out_reg_reqs[n_out_constraints] = &no_register_req;
4051 /* construct input constraints */
4052 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
4053 parsed_constraint.is_in = 1;
4054 for(i = 0; i < arity; ++i) {
4055 const ir_asm_constraint *constraint = &in_constraints[i];
4056 ident *constr_id = constraint->constraint;
4057 const char *c = get_id_str(constr_id);
4059 parse_asm_constraint(i, &parsed_constraint, c);
4060 in_reg_reqs[i] = parsed_constraint.req;
4062 if(constraint->pos > reg_map_size)
4063 reg_map_size = constraint->pos;
4065 if(parsed_constraint.immediate_possible) {
4066 ir_node *pred = get_irn_n(node, i);
4067 char imm_type = parsed_constraint.immediate_type;
4068 ir_node *immediate = try_create_Immediate(pred, imm_type);
4070 if(immediate != NULL) {
4077 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
4078 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
4080 for(i = 0; i < n_out_constraints; ++i) {
4081 const ir_asm_constraint *constraint = &out_constraints[i];
4082 unsigned pos = constraint->pos;
4084 assert(pos < reg_map_size);
4085 register_map[pos].use_input = 0;
4086 register_map[pos].valid = 1;
4087 register_map[pos].memory = is_memory_op(constraint);
4088 register_map[pos].inout_pos = i;
4089 register_map[pos].mode = constraint->mode;
4092 /* transform inputs */
4093 for(i = 0; i < arity; ++i) {
4094 const ir_asm_constraint *constraint = &in_constraints[i];
4095 unsigned pos = constraint->pos;
4096 ir_node *pred = get_irn_n(node, i);
4097 ir_node *transformed;
4099 assert(pos < reg_map_size);
4100 register_map[pos].use_input = 1;
4101 register_map[pos].valid = 1;
4102 register_map[pos].memory = is_memory_op(constraint);
4103 register_map[pos].inout_pos = i;
4104 register_map[pos].mode = constraint->mode;
4109 transformed = be_transform_node(pred);
4110 in[i] = transformed;
4113 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
4114 get_ASM_text(node), register_map);
4116 set_ia32_out_req_all(new_node, out_reg_reqs);
4117 set_ia32_in_req_all(new_node, in_reg_reqs);
4119 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4125 * Transforms a FrameAddr into an ia32 Add.
4127 static ir_node *gen_be_FrameAddr(ir_node *node) {
4128 ir_node *block = be_transform_node(get_nodes_block(node));
4129 ir_node *op = be_get_FrameAddr_frame(node);
4130 ir_node *new_op = be_transform_node(op);
4131 ir_graph *irg = current_ir_graph;
4132 dbg_info *dbgi = get_irn_dbg_info(node);
4133 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4136 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
4137 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
4138 set_ia32_use_frame(new_node);
4140 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4146 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
4148 static ir_node *gen_be_Return(ir_node *node) {
4149 ir_graph *irg = current_ir_graph;
4150 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
4151 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
4152 ir_entity *ent = get_irg_entity(irg);
4153 ir_type *tp = get_entity_type(ent);
4158 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
4159 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
4162 int pn_ret_val, pn_ret_mem, arity, i;
4164 assert(ret_val != NULL);
4165 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
4166 return be_duplicate_node(node);
4169 res_type = get_method_res_type(tp, 0);
4171 if (! is_Primitive_type(res_type)) {
4172 return be_duplicate_node(node);
4175 mode = get_type_mode(res_type);
4176 if (! mode_is_float(mode)) {
4177 return be_duplicate_node(node);
4180 assert(get_method_n_ress(tp) == 1);
4182 pn_ret_val = get_Proj_proj(ret_val);
4183 pn_ret_mem = get_Proj_proj(ret_mem);
4185 /* get the Barrier */
4186 barrier = get_Proj_pred(ret_val);
4188 /* get result input of the Barrier */
4189 ret_val = get_irn_n(barrier, pn_ret_val);
4190 new_ret_val = be_transform_node(ret_val);
4192 /* get memory input of the Barrier */
4193 ret_mem = get_irn_n(barrier, pn_ret_mem);
4194 new_ret_mem = be_transform_node(ret_mem);
4196 frame = get_irg_frame(irg);
4198 dbgi = get_irn_dbg_info(barrier);
4199 block = be_transform_node(get_nodes_block(barrier));
4201 noreg = ia32_new_NoReg_gp(env_cg);
4203 /* store xmm0 onto stack */
4204 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
4205 new_ret_mem, new_ret_val);
4206 set_ia32_ls_mode(sse_store, mode);
4207 set_ia32_op_type(sse_store, ia32_AddrModeD);
4208 set_ia32_use_frame(sse_store);
4210 /* load into x87 register */
4211 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
4212 set_ia32_op_type(fld, ia32_AddrModeS);
4213 set_ia32_use_frame(fld);
4215 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
4216 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
4218 /* create a new barrier */
4219 arity = get_irn_arity(barrier);
4220 in = alloca(arity * sizeof(in[0]));
4221 for (i = 0; i < arity; ++i) {
4224 if (i == pn_ret_val) {
4226 } else if (i == pn_ret_mem) {
4229 ir_node *in = get_irn_n(barrier, i);
4230 new_in = be_transform_node(in);
4235 new_barrier = new_ir_node(dbgi, irg, block,
4236 get_irn_op(barrier), get_irn_mode(barrier),
4238 copy_node_attr(barrier, new_barrier);
4239 be_duplicate_deps(barrier, new_barrier);
4240 be_set_transformed_node(barrier, new_barrier);
4241 mark_irn_visited(barrier);
4243 /* transform normally */
4244 return be_duplicate_node(node);
4248 * Transform a be_AddSP into an ia32_SubSP.
4250 static ir_node *gen_be_AddSP(ir_node *node)
4252 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
4253 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
4255 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
4259 * Transform a be_SubSP into an ia32_AddSP
4261 static ir_node *gen_be_SubSP(ir_node *node)
4263 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
4264 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
4266 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
4270 * This function just sets the register for the Unknown node
4271 * as this is not done during register allocation because Unknown
4272 * is an "ignore" node.
4274 static ir_node *gen_Unknown(ir_node *node) {
4275 ir_mode *mode = get_irn_mode(node);
4277 if (mode_is_float(mode)) {
4278 if (ia32_cg_config.use_sse2) {
4279 return ia32_new_Unknown_xmm(env_cg);
4281 /* Unknown nodes are buggy in x87 simulator, use zero for now... */
4282 ir_graph *irg = current_ir_graph;
4283 dbg_info *dbgi = get_irn_dbg_info(node);
4284 ir_node *block = get_irg_start_block(irg);
4285 ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
4287 /* Const Nodes before the initial IncSP are a bad idea, because
4288 * they could be spilled and we have no SP ready at that point yet.
4289 * So add a dependency to the initial frame pointer calculation to
4290 * avoid that situation.
4292 add_irn_dep(ret, get_irg_frame(irg));
4295 } else if (ia32_mode_needs_gp_reg(mode)) {
4296 return ia32_new_Unknown_gp(env_cg);
4298 panic("unsupported Unknown-Mode");
4304 * Change some phi modes
4306 static ir_node *gen_Phi(ir_node *node) {
4307 ir_node *block = be_transform_node(get_nodes_block(node));
4308 ir_graph *irg = current_ir_graph;
4309 dbg_info *dbgi = get_irn_dbg_info(node);
4310 ir_mode *mode = get_irn_mode(node);
4313 if(ia32_mode_needs_gp_reg(mode)) {
4314 /* we shouldn't have any 64bit stuff around anymore */
4315 assert(get_mode_size_bits(mode) <= 32);
4316 /* all integer operations are on 32bit registers now */
4318 } else if(mode_is_float(mode)) {
4319 if (ia32_cg_config.use_sse2) {
4326 /* phi nodes allow loops, so we use the old arguments for now
4327 * and fix this later */
4328 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
4329 get_irn_in(node) + 1);
4330 copy_node_attr(node, phi);
4331 be_duplicate_deps(node, phi);
4333 be_set_transformed_node(node, phi);
4334 be_enqueue_preds(node);
4342 static ir_node *gen_IJmp(ir_node *node)
4344 ir_node *block = get_nodes_block(node);
4345 ir_node *new_block = be_transform_node(block);
4346 dbg_info *dbgi = get_irn_dbg_info(node);
4347 ir_node *op = get_IJmp_target(node);
4349 ia32_address_mode_t am;
4350 ia32_address_t *addr = &am.addr;
4352 assert(get_irn_mode(op) == mode_P);
4354 match_arguments(&am, block, NULL, op, NULL,
4355 match_am | match_8bit_am | match_16bit_am |
4356 match_immediate | match_8bit | match_16bit);
4358 new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block,
4359 addr->base, addr->index, addr->mem,
4361 set_am_attributes(new_node, &am);
4362 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4364 new_node = fix_mem_proj(new_node, &am);
4370 * Transform a Bound node.
4372 static ir_node *gen_Bound(ir_node *node)
4375 ir_node *lower = get_Bound_lower(node);
4376 dbg_info *dbgi = get_irn_dbg_info(node);
4378 if (is_Const_0(lower)) {
4379 /* typical case for Java */
4380 ir_node *sub, *res, *flags, *block;
4381 ir_graph *irg = current_ir_graph;
4383 res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
4384 new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
4386 block = get_nodes_block(res);
4387 if (! is_Proj(res)) {
4389 set_irn_mode(sub, mode_T);
4390 res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res);
4392 sub = get_Proj_pred(res);
4394 flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
4395 new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
4396 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4398 panic("generic Bound not supported in ia32 Backend");
4404 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
4407 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
4408 ir_node *val, ir_node *mem);
4411 * Transforms a lowered Load into a "real" one.
4413 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
4415 ir_node *block = be_transform_node(get_nodes_block(node));
4416 ir_node *ptr = get_irn_n(node, 0);
4417 ir_node *new_ptr = be_transform_node(ptr);
4418 ir_node *mem = get_irn_n(node, 1);
4419 ir_node *new_mem = be_transform_node(mem);
4420 ir_graph *irg = current_ir_graph;
4421 dbg_info *dbgi = get_irn_dbg_info(node);
4422 ir_mode *mode = get_ia32_ls_mode(node);
4423 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4426 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
4428 set_ia32_op_type(new_op, ia32_AddrModeS);
4429 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
4430 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
4431 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
4432 if (is_ia32_am_sc_sign(node))
4433 set_ia32_am_sc_sign(new_op);
4434 set_ia32_ls_mode(new_op, mode);
4435 if (is_ia32_use_frame(node)) {
4436 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4437 set_ia32_use_frame(new_op);
4440 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4446 * Transforms a lowered Store into a "real" one.
4448 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
4450 ir_node *block = be_transform_node(get_nodes_block(node));
4451 ir_node *ptr = get_irn_n(node, 0);
4452 ir_node *new_ptr = be_transform_node(ptr);
4453 ir_node *val = get_irn_n(node, 1);
4454 ir_node *new_val = be_transform_node(val);
4455 ir_node *mem = get_irn_n(node, 2);
4456 ir_node *new_mem = be_transform_node(mem);
4457 ir_graph *irg = current_ir_graph;
4458 dbg_info *dbgi = get_irn_dbg_info(node);
4459 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4460 ir_mode *mode = get_ia32_ls_mode(node);
4464 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
4466 am_offs = get_ia32_am_offs_int(node);
4467 add_ia32_am_offs_int(new_op, am_offs);
4469 set_ia32_op_type(new_op, ia32_AddrModeD);
4470 set_ia32_ls_mode(new_op, mode);
4471 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4472 set_ia32_use_frame(new_op);
4474 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4479 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
4481 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
4482 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
4484 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
4485 match_immediate | match_mode_neutral);
4488 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
4490 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
4491 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
4492 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
4496 static ir_node *gen_ia32_l_SarDep(ir_node *node)
4498 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
4499 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
4500 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
4504 static ir_node *gen_ia32_l_Add(ir_node *node) {
4505 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4506 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4507 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
4508 match_commutative | match_am | match_immediate |
4509 match_mode_neutral);
4511 if(is_Proj(lowered)) {
4512 lowered = get_Proj_pred(lowered);
4514 assert(is_ia32_Add(lowered));
4515 set_irn_mode(lowered, mode_T);
4521 static ir_node *gen_ia32_l_Adc(ir_node *node)
4523 return gen_binop_flags(node, new_rd_ia32_Adc,
4524 match_commutative | match_am | match_immediate |
4525 match_mode_neutral);
4529 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4531 * @param node The node to transform
4532 * @return the created ia32 vfild node
4534 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4535 return gen_lowered_Load(node, new_rd_ia32_vfild);
4539 * Transforms an ia32_l_Load into a "real" ia32_Load node
4541 * @param node The node to transform
4542 * @return the created ia32 Load node
4544 static ir_node *gen_ia32_l_Load(ir_node *node) {
4545 return gen_lowered_Load(node, new_rd_ia32_Load);
4549 * Transforms an ia32_l_Store into a "real" ia32_Store node
4551 * @param node The node to transform
4552 * @return the created ia32 Store node
4554 static ir_node *gen_ia32_l_Store(ir_node *node) {
4555 return gen_lowered_Store(node, new_rd_ia32_Store);
4559 * Transforms a l_vfist into a "real" vfist node.
4561 * @param node The node to transform
4562 * @return the created ia32 vfist node
4564 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4565 ir_node *block = be_transform_node(get_nodes_block(node));
4566 ir_node *ptr = get_irn_n(node, 0);
4567 ir_node *new_ptr = be_transform_node(ptr);
4568 ir_node *val = get_irn_n(node, 1);
4569 ir_node *new_val = be_transform_node(val);
4570 ir_node *mem = get_irn_n(node, 2);
4571 ir_node *new_mem = be_transform_node(mem);
4572 ir_graph *irg = current_ir_graph;
4573 dbg_info *dbgi = get_irn_dbg_info(node);
4574 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4575 ir_mode *mode = get_ia32_ls_mode(node);
4576 ir_node *memres, *fist;
4579 memres = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, &fist);
4580 am_offs = get_ia32_am_offs_int(node);
4581 add_ia32_am_offs_int(fist, am_offs);
4583 set_ia32_op_type(fist, ia32_AddrModeD);
4584 set_ia32_ls_mode(fist, mode);
4585 set_ia32_frame_ent(fist, get_ia32_frame_ent(node));
4586 set_ia32_use_frame(fist);
4588 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
4594 * Transforms a l_MulS into a "real" MulS node.
4596 * @return the created ia32 Mul node
4598 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4599 ir_node *left = get_binop_left(node);
4600 ir_node *right = get_binop_right(node);
4602 return gen_binop(node, left, right, new_rd_ia32_Mul,
4603 match_commutative | match_am | match_mode_neutral);
4607 * Transforms a l_IMulS into a "real" IMul1OPS node.
4609 * @return the created ia32 IMul1OP node
4611 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4612 ir_node *left = get_binop_left(node);
4613 ir_node *right = get_binop_right(node);
4615 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4616 match_commutative | match_am | match_mode_neutral);
4619 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4620 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4621 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4622 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4623 match_am | match_immediate | match_mode_neutral);
4625 if(is_Proj(lowered)) {
4626 lowered = get_Proj_pred(lowered);
4628 assert(is_ia32_Sub(lowered));
4629 set_irn_mode(lowered, mode_T);
4635 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4636 return gen_binop_flags(node, new_rd_ia32_Sbb,
4637 match_am | match_immediate | match_mode_neutral);
4641 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4642 * op1 - target to be shifted
4643 * op2 - contains bits to be shifted into target
4645 * Only op3 can be an immediate.
4647 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4648 ir_node *low, ir_node *count)
4650 ir_node *block = get_nodes_block(node);
4651 ir_node *new_block = be_transform_node(block);
4652 ir_graph *irg = current_ir_graph;
4653 dbg_info *dbgi = get_irn_dbg_info(node);
4654 ir_node *new_high = be_transform_node(high);
4655 ir_node *new_low = be_transform_node(low);
4659 /* the shift amount can be any mode that is bigger than 5 bits, since all
4660 * other bits are ignored anyway */
4661 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4662 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4663 count = get_Conv_op(count);
4665 new_count = create_immediate_or_transform(count, 0);
4667 if (is_ia32_l_ShlD(node)) {
4668 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4671 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4674 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4679 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4681 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4682 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4683 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4684 return gen_lowered_64bit_shifts(node, high, low, count);
4687 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4689 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4690 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4691 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4692 return gen_lowered_64bit_shifts(node, high, low, count);
4695 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node) {
4696 ir_node *src_block = get_nodes_block(node);
4697 ir_node *block = be_transform_node(src_block);
4698 ir_graph *irg = current_ir_graph;
4699 dbg_info *dbgi = get_irn_dbg_info(node);
4700 ir_node *frame = get_irg_frame(irg);
4701 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4702 ir_node *nomem = new_NoMem();
4703 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4704 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4705 ir_node *new_val_low = be_transform_node(val_low);
4706 ir_node *new_val_high = be_transform_node(val_high);
4711 ir_node *store_high;
4713 if(!mode_is_signed(get_irn_mode(val_high))) {
4714 panic("unsigned long long -> float not supported yet (%+F)", node);
4718 store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4720 store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
4722 SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node));
4723 SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node));
4725 set_ia32_use_frame(store_low);
4726 set_ia32_use_frame(store_high);
4727 set_ia32_op_type(store_low, ia32_AddrModeD);
4728 set_ia32_op_type(store_high, ia32_AddrModeD);
4729 set_ia32_ls_mode(store_low, mode_Iu);
4730 set_ia32_ls_mode(store_high, mode_Is);
4731 add_ia32_am_offs_int(store_high, 4);
4735 sync = new_rd_Sync(dbgi, irg, block, 2, in);
4738 fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync);
4740 set_ia32_use_frame(fild);
4741 set_ia32_op_type(fild, ia32_AddrModeS);
4742 set_ia32_ls_mode(fild, mode_Ls);
4744 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
4746 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
4749 static ir_node *gen_ia32_l_FloattoLL(ir_node *node) {
4750 ir_node *src_block = get_nodes_block(node);
4751 ir_node *block = be_transform_node(src_block);
4752 ir_graph *irg = current_ir_graph;
4753 dbg_info *dbgi = get_irn_dbg_info(node);
4754 ir_node *frame = get_irg_frame(irg);
4755 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4756 ir_node *nomem = new_NoMem();
4757 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4758 ir_node *new_val = be_transform_node(val);
4759 ir_node *fist, *mem;
4761 mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist);
4762 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
4763 set_ia32_use_frame(fist);
4764 set_ia32_op_type(fist, ia32_AddrModeD);
4765 set_ia32_ls_mode(fist, mode_Ls);
4771 * the BAD transformer.
4773 static ir_node *bad_transform(ir_node *node) {
4774 panic("No transform function for %+F available.\n", node);
4778 static ir_node *gen_Proj_l_FloattoLL(ir_node *node) {
4779 ir_graph *irg = current_ir_graph;
4780 ir_node *block = be_transform_node(get_nodes_block(node));
4781 ir_node *pred = get_Proj_pred(node);
4782 ir_node *new_pred = be_transform_node(pred);
4783 ir_node *frame = get_irg_frame(irg);
4784 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4785 dbg_info *dbgi = get_irn_dbg_info(node);
4786 long pn = get_Proj_proj(node);
4791 load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred);
4792 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
4793 set_ia32_use_frame(load);
4794 set_ia32_op_type(load, ia32_AddrModeS);
4795 set_ia32_ls_mode(load, mode_Iu);
4796 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4797 * 32 bit from it with this particular load */
4798 attr = get_ia32_attr(load);
4799 attr->data.need_64bit_stackent = 1;
4801 if (pn == pn_ia32_l_FloattoLL_res_high) {
4802 add_ia32_am_offs_int(load, 4);
4804 assert(pn == pn_ia32_l_FloattoLL_res_low);
4807 proj = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
4813 * Transform the Projs of an AddSP.
4815 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4816 ir_node *block = be_transform_node(get_nodes_block(node));
4817 ir_node *pred = get_Proj_pred(node);
4818 ir_node *new_pred = be_transform_node(pred);
4819 ir_graph *irg = current_ir_graph;
4820 dbg_info *dbgi = get_irn_dbg_info(node);
4821 long proj = get_Proj_proj(node);
4823 if (proj == pn_be_AddSP_sp) {
4824 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4825 pn_ia32_SubSP_stack);
4826 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4828 } else if(proj == pn_be_AddSP_res) {
4829 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4830 pn_ia32_SubSP_addr);
4831 } else if (proj == pn_be_AddSP_M) {
4832 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4836 return new_rd_Unknown(irg, get_irn_mode(node));
4840 * Transform the Projs of a SubSP.
4842 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4843 ir_node *block = be_transform_node(get_nodes_block(node));
4844 ir_node *pred = get_Proj_pred(node);
4845 ir_node *new_pred = be_transform_node(pred);
4846 ir_graph *irg = current_ir_graph;
4847 dbg_info *dbgi = get_irn_dbg_info(node);
4848 long proj = get_Proj_proj(node);
4850 if (proj == pn_be_SubSP_sp) {
4851 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4852 pn_ia32_AddSP_stack);
4853 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4855 } else if (proj == pn_be_SubSP_M) {
4856 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4860 return new_rd_Unknown(irg, get_irn_mode(node));
4864 * Transform and renumber the Projs from a Load.
4866 static ir_node *gen_Proj_Load(ir_node *node) {
4868 ir_node *block = be_transform_node(get_nodes_block(node));
4869 ir_node *pred = get_Proj_pred(node);
4870 ir_graph *irg = current_ir_graph;
4871 dbg_info *dbgi = get_irn_dbg_info(node);
4872 long proj = get_Proj_proj(node);
4874 /* loads might be part of source address mode matches, so we don't
4875 * transform the ProjMs yet (with the exception of loads whose result is
4878 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4881 /* this is needed, because sometimes we have loops that are only
4882 reachable through the ProjM */
4883 be_enqueue_preds(node);
4884 /* do it in 2 steps, to silence firm verifier */
4885 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4886 set_Proj_proj(res, pn_ia32_mem);
4890 /* renumber the proj */
4891 new_pred = be_transform_node(pred);
4892 if (is_ia32_Load(new_pred)) {
4895 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
4897 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
4898 case pn_Load_X_regular:
4899 return new_rd_Jmp(dbgi, irg, block);
4900 case pn_Load_X_except:
4901 /* This Load might raise an exception. Mark it. */
4902 set_ia32_exc_label(new_pred, 1);
4903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Load_X_exc);
4907 } else if (is_ia32_Conv_I2I(new_pred) ||
4908 is_ia32_Conv_I2I8Bit(new_pred)) {
4909 set_irn_mode(new_pred, mode_T);
4910 if (proj == pn_Load_res) {
4911 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4912 } else if (proj == pn_Load_M) {
4913 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4915 } else if (is_ia32_xLoad(new_pred)) {
4918 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
4920 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
4921 case pn_Load_X_regular:
4922 return new_rd_Jmp(dbgi, irg, block);
4923 case pn_Load_X_except:
4924 /* This Load might raise an exception. Mark it. */
4925 set_ia32_exc_label(new_pred, 1);
4926 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4930 } else if (is_ia32_vfld(new_pred)) {
4933 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
4935 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
4936 case pn_Load_X_regular:
4937 return new_rd_Jmp(dbgi, irg, block);
4938 case pn_Load_X_except:
4939 /* This Load might raise an exception. Mark it. */
4940 set_ia32_exc_label(new_pred, 1);
4941 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4946 /* can happen for ProJMs when source address mode happened for the
4949 /* however it should not be the result proj, as that would mean the
4950 load had multiple users and should not have been used for
4952 if (proj != pn_Load_M) {
4953 panic("internal error: transformed node not a Load");
4955 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4959 return new_rd_Unknown(irg, get_irn_mode(node));
4963 * Transform and renumber the Projs from a DivMod like instruction.
4965 static ir_node *gen_Proj_DivMod(ir_node *node) {
4966 ir_node *block = be_transform_node(get_nodes_block(node));
4967 ir_node *pred = get_Proj_pred(node);
4968 ir_node *new_pred = be_transform_node(pred);
4969 ir_graph *irg = current_ir_graph;
4970 dbg_info *dbgi = get_irn_dbg_info(node);
4971 ir_mode *mode = get_irn_mode(node);
4972 long proj = get_Proj_proj(node);
4974 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4976 switch (get_irn_opcode(pred)) {
4980 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4982 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4983 case pn_Div_X_regular:
4984 return new_rd_Jmp(dbgi, irg, block);
4985 case pn_Div_X_except:
4986 set_ia32_exc_label(new_pred, 1);
4987 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
4995 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4997 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4998 case pn_Mod_X_except:
4999 set_ia32_exc_label(new_pred, 1);
5000 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
5008 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
5009 case pn_DivMod_res_div:
5010 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
5011 case pn_DivMod_res_mod:
5012 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
5013 case pn_DivMod_X_regular:
5014 return new_rd_Jmp(dbgi, irg, block);
5015 case pn_DivMod_X_except:
5016 set_ia32_exc_label(new_pred, 1);
5017 return new_rd_Proj(dbgi, irg, block, new_pred, mode_X, pn_ia32_Div_X_exc);
5027 return new_rd_Unknown(irg, mode);
5031 * Transform and renumber the Projs from a CopyB.
5033 static ir_node *gen_Proj_CopyB(ir_node *node) {
5034 ir_node *block = be_transform_node(get_nodes_block(node));
5035 ir_node *pred = get_Proj_pred(node);
5036 ir_node *new_pred = be_transform_node(pred);
5037 ir_graph *irg = current_ir_graph;
5038 dbg_info *dbgi = get_irn_dbg_info(node);
5039 ir_mode *mode = get_irn_mode(node);
5040 long proj = get_Proj_proj(node);
5043 case pn_CopyB_M_regular:
5044 if (is_ia32_CopyB_i(new_pred)) {
5045 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
5046 } else if (is_ia32_CopyB(new_pred)) {
5047 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
5055 return new_rd_Unknown(irg, mode);
5059 * Transform and renumber the Projs from a Quot.
5061 static ir_node *gen_Proj_Quot(ir_node *node) {
5062 ir_node *block = be_transform_node(get_nodes_block(node));
5063 ir_node *pred = get_Proj_pred(node);
5064 ir_node *new_pred = be_transform_node(pred);
5065 ir_graph *irg = current_ir_graph;
5066 dbg_info *dbgi = get_irn_dbg_info(node);
5067 ir_mode *mode = get_irn_mode(node);
5068 long proj = get_Proj_proj(node);
5072 if (is_ia32_xDiv(new_pred)) {
5073 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
5074 } else if (is_ia32_vfdiv(new_pred)) {
5075 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
5079 if (is_ia32_xDiv(new_pred)) {
5080 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
5081 } else if (is_ia32_vfdiv(new_pred)) {
5082 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
5085 case pn_Quot_X_regular:
5086 case pn_Quot_X_except:
5092 return new_rd_Unknown(irg, mode);
5096 * Transform the Thread Local Storage Proj.
5098 static ir_node *gen_Proj_tls(ir_node *node) {
5099 ir_node *block = be_transform_node(get_nodes_block(node));
5100 ir_graph *irg = current_ir_graph;
5101 dbg_info *dbgi = NULL;
5102 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
5107 static ir_node *gen_be_Call(ir_node *node) {
5108 ir_node *res = be_duplicate_node(node);
5109 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
5114 static ir_node *gen_be_IncSP(ir_node *node) {
5115 ir_node *res = be_duplicate_node(node);
5116 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
5122 * Transform the Projs from a be_Call.
5124 static ir_node *gen_Proj_be_Call(ir_node *node) {
5125 ir_node *block = be_transform_node(get_nodes_block(node));
5126 ir_node *call = get_Proj_pred(node);
5127 ir_node *new_call = be_transform_node(call);
5128 ir_graph *irg = current_ir_graph;
5129 dbg_info *dbgi = get_irn_dbg_info(node);
5130 ir_type *method_type = be_Call_get_type(call);
5131 int n_res = get_method_n_ress(method_type);
5132 long proj = get_Proj_proj(node);
5133 ir_mode *mode = get_irn_mode(node);
5135 const arch_register_class_t *cls;
5137 /* The following is kinda tricky: If we're using SSE, then we have to
5138 * move the result value of the call in floating point registers to an
5139 * xmm register, we therefore construct a GetST0 -> xLoad sequence
5140 * after the call, we have to make sure to correctly make the
5141 * MemProj and the result Proj use these 2 nodes
5143 if (proj == pn_be_Call_M_regular) {
5144 // get new node for result, are we doing the sse load/store hack?
5145 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
5146 ir_node *call_res_new;
5147 ir_node *call_res_pred = NULL;
5149 if (call_res != NULL) {
5150 call_res_new = be_transform_node(call_res);
5151 call_res_pred = get_Proj_pred(call_res_new);
5154 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
5155 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
5156 pn_be_Call_M_regular);
5158 assert(is_ia32_xLoad(call_res_pred));
5159 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
5163 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
5164 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
5166 ir_node *frame = get_irg_frame(irg);
5167 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
5169 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
5172 /* in case there is no memory output: create one to serialize the copy
5174 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
5175 pn_be_Call_M_regular);
5176 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
5177 pn_be_Call_first_res);
5179 /* store st(0) onto stack */
5180 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
5182 set_ia32_op_type(fstp, ia32_AddrModeD);
5183 set_ia32_use_frame(fstp);
5185 /* load into SSE register */
5186 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
5188 set_ia32_op_type(sse_load, ia32_AddrModeS);
5189 set_ia32_use_frame(sse_load);
5191 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
5197 /* transform call modes */
5198 if (mode_is_data(mode)) {
5199 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
5203 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
5207 * Transform the Projs from a Cmp.
5209 static ir_node *gen_Proj_Cmp(ir_node *node)
5211 /* this probably means not all mode_b nodes were lowered... */
5212 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5217 * Transform the Projs from a Bound.
5219 static ir_node *gen_Proj_Bound(ir_node *node)
5221 ir_node *new_node, *block;
5222 ir_node *pred = get_Proj_pred(node);
5224 switch (get_Proj_proj(node)) {
5226 return be_transform_node(get_Bound_mem(pred));
5227 case pn_Bound_X_regular:
5228 new_node = be_transform_node(pred);
5229 block = get_nodes_block(new_node);
5230 return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true);
5231 case pn_Bound_X_except:
5232 new_node = be_transform_node(pred);
5233 block = get_nodes_block(new_node);
5234 return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false);
5236 return be_transform_node(get_Bound_index(pred));
5238 panic("unsupported Proj from Bound");
5243 * Transform and potentially renumber Proj nodes.
5245 static ir_node *gen_Proj(ir_node *node) {
5246 ir_node *pred = get_Proj_pred(node);
5249 switch (get_irn_opcode(pred)) {
5251 proj = get_Proj_proj(node);
5252 if (proj == pn_Store_M) {
5253 return be_transform_node(pred);
5256 return new_r_Bad(current_ir_graph);
5259 return gen_Proj_Load(node);
5263 return gen_Proj_DivMod(node);
5265 return gen_Proj_CopyB(node);
5267 return gen_Proj_Quot(node);
5269 return gen_Proj_be_SubSP(node);
5271 return gen_Proj_be_AddSP(node);
5273 return gen_Proj_be_Call(node);
5275 return gen_Proj_Cmp(node);
5277 return gen_Proj_Bound(node);
5279 proj = get_Proj_proj(node);
5280 if (proj == pn_Start_X_initial_exec) {
5281 ir_node *block = get_nodes_block(pred);
5282 dbg_info *dbgi = get_irn_dbg_info(node);
5285 /* we exchange the ProjX with a jump */
5286 block = be_transform_node(block);
5287 jump = new_rd_Jmp(dbgi, current_ir_graph, block);
5290 if (node == be_get_old_anchor(anchor_tls)) {
5291 return gen_Proj_tls(node);
5296 if (is_ia32_l_FloattoLL(pred)) {
5297 return gen_Proj_l_FloattoLL(node);
5299 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5303 ir_mode *mode = get_irn_mode(node);
5304 if (ia32_mode_needs_gp_reg(mode)) {
5305 ir_node *new_pred = be_transform_node(pred);
5306 ir_node *block = be_transform_node(get_nodes_block(node));
5307 ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred,
5308 mode_Iu, get_Proj_proj(node));
5309 #ifdef DEBUG_libfirm
5310 new_proj->node_nr = node->node_nr;
5316 return be_duplicate_node(node);
5320 * Enters all transform functions into the generic pointer
5322 static void register_transformers(void)
5326 /* first clear the generic function pointer for all ops */
5327 clear_irp_opcodes_generic_func();
5329 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
5330 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
5369 /* transform ops from intrinsic lowering */
5385 GEN(ia32_l_LLtoFloat);
5386 GEN(ia32_l_FloattoLL);
5392 /* we should never see these nodes */
5407 /* handle generic backend nodes */
5416 op_Mulh = get_op_Mulh();
5425 * Pre-transform all unknown and noreg nodes.
5427 static void ia32_pretransform_node(void *arch_cg) {
5428 ia32_code_gen_t *cg = arch_cg;
5430 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
5431 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
5432 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
5433 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
5434 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
5435 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
5440 * Walker, checks if all ia32 nodes producing more than one result have
5441 * its Projs, otherwise creates new Projs and keep them using a be_Keep node.
5443 static void add_missing_keep_walker(ir_node *node, void *data)
5446 unsigned found_projs = 0;
5447 const ir_edge_t *edge;
5448 ir_mode *mode = get_irn_mode(node);
5453 if(!is_ia32_irn(node))
5456 n_outs = get_ia32_n_res(node);
5459 if(is_ia32_SwitchJmp(node))
5462 assert(n_outs < (int) sizeof(unsigned) * 8);
5463 foreach_out_edge(node, edge) {
5464 ir_node *proj = get_edge_src_irn(edge);
5465 int pn = get_Proj_proj(proj);
5467 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
5468 found_projs |= 1 << pn;
5472 /* are keeps missing? */
5474 for(i = 0; i < n_outs; ++i) {
5477 const arch_register_req_t *req;
5478 const arch_register_class_t *cls;
5480 if(found_projs & (1 << i)) {
5484 req = get_ia32_out_req(node, i);
5489 if(cls == &ia32_reg_classes[CLASS_ia32_flags]) {
5493 block = get_nodes_block(node);
5494 in[0] = new_r_Proj(current_ir_graph, block, node,
5495 arch_register_class_mode(cls), i);
5496 if(last_keep != NULL) {
5497 be_Keep_add_node(last_keep, cls, in[0]);
5499 last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in);
5500 if(sched_is_scheduled(node)) {
5501 sched_add_after(node, last_keep);
5508 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
5511 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
5513 ir_graph *irg = be_get_birg_irg(cg->birg);
5514 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
5517 /* do the transformation */
5518 void ia32_transform_graph(ia32_code_gen_t *cg) {
5520 ir_graph *irg = cg->irg;
5522 register_transformers();
5524 initial_fpcw = NULL;
5526 BE_TIMER_PUSH(t_heights);
5527 heights = heights_new(irg);
5528 BE_TIMER_POP(t_heights);
5529 ia32_calculate_non_address_mode_nodes(cg->birg);
5531 /* the transform phase is not safe for CSE (yet) because several nodes get
5532 * attributes set after their creation */
5533 cse_last = get_opt_cse();
5536 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
5538 set_opt_cse(cse_last);
5540 ia32_free_non_address_mode_nodes();
5541 heights_free(heights);
5545 void ia32_init_transform(void)
5547 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");