2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
32 #include "../benode_t.h"
33 #include "../besched.h"
36 #include "bearch_ia32_t.h"
37 #include "ia32_nodes_attr.h"
38 #include "ia32_transform.h"
39 #include "ia32_new_nodes.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_dbg_stat.h"
42 #include "ia32_optimize.h"
43 #include "ia32_util.h"
45 #include "gen_ia32_regalloc_if.h"
47 #define SFP_SIGN "0x80000000"
48 #define DFP_SIGN "0x8000000000000000"
49 #define SFP_ABS "0x7FFFFFFF"
50 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
52 #define TP_SFP_SIGN "ia32_sfp_sign"
53 #define TP_DFP_SIGN "ia32_dfp_sign"
54 #define TP_SFP_ABS "ia32_sfp_abs"
55 #define TP_DFP_ABS "ia32_dfp_abs"
57 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
58 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
59 #define ENT_SFP_ABS "IA32_SFP_ABS"
60 #define ENT_DFP_ABS "IA32_DFP_ABS"
62 extern ir_op *get_op_Mulh(void);
64 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op1, ir_node *op2, ir_node *mem);
67 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
68 ir_node *op, ir_node *mem);
71 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
74 /****************************************************************************************************
76 * | | | | / _| | | (_)
77 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
78 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
79 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
80 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
82 ****************************************************************************************************/
85 * Returns 1 if irn is a Const representing 0, 0 otherwise
87 static INLINE int is_ia32_Const_0(ir_node *irn) {
88 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
89 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
93 * Returns 1 if irn is a Const representing 1, 0 otherwise
95 static INLINE int is_ia32_Const_1(ir_node *irn) {
96 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
97 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
101 * Returns the Proj representing the UNKNOWN register for given mode.
103 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
104 be_abi_irg_t *babi = cg->birg->abi;
105 const arch_register_t *unknwn_reg = NULL;
107 if (mode_is_float(mode)) {
108 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
111 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
114 return be_abi_get_callee_save_irn(babi, unknwn_reg);
118 * Gets the Proj with number pn from irn.
120 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
121 const ir_edge_t *edge;
123 assert(get_irn_mode(irn) == mode_T && "need mode_T");
125 foreach_out_edge(irn, edge) {
126 proj = get_edge_src_irn(edge);
128 if (get_Proj_proj(proj) == pn)
136 * Renumbers the Proj of node irn having pn_old to pn_new.
138 static INLINE void ia32_renumber_Proj(ir_node *irn, long pn_old, long pn_new) {
139 ir_node *proj = get_proj_for_pn(irn, pn_old);
142 set_Proj_proj(proj, pn_new);
146 * SSE convert of an integer node into a floating point node.
148 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
149 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
151 ir_node *noreg = ia32_new_NoReg_gp(cg);
152 ir_node *nomem = new_rd_NoMem(irg);
154 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
155 set_ia32_src_mode(conv, get_irn_mode(in));
156 set_ia32_tgt_mode(conv, tgt_mode);
157 set_ia32_am_support(conv, ia32_am_Source);
158 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
160 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
164 * SSE convert of an float node into a double node.
166 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
167 ir_node *in, ir_node *old_node)
169 ir_node *noreg = ia32_new_NoReg_gp(cg);
170 ir_node *nomem = new_rd_NoMem(irg);
172 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
173 set_ia32_src_mode(conv, mode_F);
174 set_ia32_tgt_mode(conv, mode_D);
175 set_ia32_am_support(conv, ia32_am_Source);
176 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
178 return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res);
181 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
182 static ident *gen_fp_known_const(ia32_known_const_t kct) {
183 static const struct {
185 const char *ent_name;
186 const char *cnst_str;
187 } names [ia32_known_const_max] = {
188 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
189 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
190 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
191 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
193 static entity *ent_cache[ia32_known_const_max];
195 const char *tp_name, *ent_name, *cnst_str;
203 ent_name = names[kct].ent_name;
204 if (! ent_cache[kct]) {
205 tp_name = names[kct].tp_name;
206 cnst_str = names[kct].cnst_str;
208 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
209 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
210 tp = new_type_primitive(new_id_from_str(tp_name), mode);
211 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
213 set_entity_ld_ident(ent, get_entity_ident(ent));
214 set_entity_visibility(ent, visibility_local);
215 set_entity_variability(ent, variability_constant);
216 set_entity_allocation(ent, allocation_static);
218 /* we create a new entity here: It's initialization must resist on the
220 rem = current_ir_graph;
221 current_ir_graph = get_const_code_irg();
222 cnst = new_Const(mode, tv);
223 current_ir_graph = rem;
225 set_atomic_ent_value(ent, cnst);
227 /* cache the entry */
228 ent_cache[kct] = ent;
231 return get_entity_ident(ent_cache[kct]);
236 * Prints the old node name on cg obst and returns a pointer to it.
238 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
239 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
241 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
242 obstack_1grow(isa->name_obst, 0);
243 isa->name_obst_size += obstack_object_size(isa->name_obst);
244 return obstack_finish(isa->name_obst);
248 /* determine if one operator is an Imm */
249 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
251 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
252 else return is_ia32_Cnst(op2) ? op2 : NULL;
255 /* determine if one operator is not an Imm */
256 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
257 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
262 * Construct a standard binary operation, set AM and immediate if required.
264 * @param env The transformation environment
265 * @param op1 The first operand
266 * @param op2 The second operand
267 * @param func The node constructor function
268 * @return The constructed ia32 node.
270 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
271 ir_node *new_op = NULL;
272 ir_mode *mode = env->mode;
273 dbg_info *dbg = env->dbg;
274 ir_graph *irg = env->irg;
275 ir_node *block = env->block;
276 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
277 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
278 ir_node *nomem = new_NoMem();
280 ir_node *expr_op, *imm_op;
281 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
283 /* Check if immediate optimization is on and */
284 /* if it's an operation with immediate. */
285 /* Mul/MulS/Mulh don't support immediates */
286 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
287 func == new_rd_ia32_Mul ||
288 func == new_rd_ia32_Mulh ||
289 func == new_rd_ia32_MulS)
293 /* immediate operations are requested, but we are here: it a mul */
294 if (env->cg->opt & IA32_OPT_IMMOPS)
297 else if (is_op_commutative(get_irn_op(env->irn))) {
298 imm_op = get_immediate_op(op1, op2);
299 expr_op = get_expr_op(op1, op2);
302 imm_op = get_immediate_op(NULL, op2);
303 expr_op = get_expr_op(op1, op2);
306 assert((expr_op || imm_op) && "invalid operands");
309 /* We have two consts here: not yet supported */
313 if (mode_is_float(mode)) {
314 /* floating point operations */
316 DB((mod, LEVEL_1, "FP with immediate ..."));
317 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
318 set_ia32_Immop_attr(new_op, imm_op);
319 set_ia32_am_support(new_op, ia32_am_None);
322 DB((mod, LEVEL_1, "FP binop ..."));
323 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
324 set_ia32_am_support(new_op, ia32_am_Source);
326 set_ia32_ls_mode(new_op, mode);
329 /* integer operations */
331 /* This is expr + const */
332 DB((mod, LEVEL_1, "INT with immediate ..."));
333 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
334 set_ia32_Immop_attr(new_op, imm_op);
337 set_ia32_am_support(new_op, ia32_am_Dest);
340 DB((mod, LEVEL_1, "INT binop ..."));
341 /* This is a normal operation */
342 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
345 set_ia32_am_support(new_op, ia32_am_Full);
348 /* Muls can only have AM source */
350 set_ia32_am_support(new_op, ia32_am_Source);
353 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
355 set_ia32_res_mode(new_op, mode);
357 if (is_op_commutative(get_irn_op(env->irn))) {
358 set_ia32_commutative(new_op);
361 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
367 * Construct a shift/rotate binary operation, sets AM and immediate if required.
369 * @param env The transformation environment
370 * @param op1 The first operand
371 * @param op2 The second operand
372 * @param func The node constructor function
373 * @return The constructed ia32 node.
375 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
376 ir_node *new_op = NULL;
377 ir_mode *mode = env->mode;
378 dbg_info *dbg = env->dbg;
379 ir_graph *irg = env->irg;
380 ir_node *block = env->block;
381 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
382 ir_node *nomem = new_NoMem();
383 ir_node *expr_op, *imm_op;
385 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
387 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
389 /* Check if immediate optimization is on and */
390 /* if it's an operation with immediate. */
391 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
392 expr_op = get_expr_op(op1, op2);
394 assert((expr_op || imm_op) && "invalid operands");
397 /* We have two consts here: not yet supported */
401 /* Limit imm_op within range imm8 */
403 tv = get_ia32_Immop_tarval(imm_op);
406 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
407 set_ia32_Immop_tarval(imm_op, tv);
414 /* integer operations */
416 /* This is shift/rot with const */
417 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
419 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
420 set_ia32_Immop_attr(new_op, imm_op);
423 /* This is a normal shift/rot */
424 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
425 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
429 set_ia32_am_support(new_op, ia32_am_Dest);
431 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
433 set_ia32_res_mode(new_op, mode);
434 set_ia32_emit_cl(new_op);
436 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
441 * Construct a standard unary operation, set AM and immediate if required.
443 * @param env The transformation environment
444 * @param op The operand
445 * @param func The node constructor function
446 * @return The constructed ia32 node.
448 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
449 ir_node *new_op = NULL;
450 ir_mode *mode = env->mode;
451 dbg_info *dbg = env->dbg;
452 ir_graph *irg = env->irg;
453 ir_node *block = env->block;
454 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
455 ir_node *nomem = new_NoMem();
456 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
458 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
460 if (mode_is_float(mode)) {
461 DB((mod, LEVEL_1, "FP unop ..."));
462 /* floating point operations don't support implicit store */
463 set_ia32_am_support(new_op, ia32_am_None);
466 DB((mod, LEVEL_1, "INT unop ..."));
467 set_ia32_am_support(new_op, ia32_am_Dest);
470 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
472 set_ia32_res_mode(new_op, mode);
474 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
480 * Creates an ia32 Add with immediate.
482 * @param env The transformation environment
483 * @param expr_op The expression operator
484 * @param const_op The constant
485 * @return the created ia32 Add node
487 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
488 ir_node *new_op = NULL;
489 tarval *tv = get_ia32_Immop_tarval(const_op);
490 dbg_info *dbg = env->dbg;
491 ir_graph *irg = env->irg;
492 ir_node *block = env->block;
493 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
494 ir_node *nomem = new_NoMem();
496 tarval_classification_t class_tv, class_negtv;
497 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
499 /* try to optimize to inc/dec */
500 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
501 /* optimize tarvals */
502 class_tv = classify_tarval(tv);
503 class_negtv = classify_tarval(tarval_neg(tv));
505 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
506 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
507 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
510 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
511 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
512 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
518 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
519 set_ia32_Immop_attr(new_op, const_op);
520 set_ia32_commutative(new_op);
527 * Creates an ia32 Add.
529 * @param env The transformation environment
530 * @return the created ia32 Add node
532 static ir_node *gen_Add(ia32_transform_env_t *env) {
533 ir_node *new_op = NULL;
534 dbg_info *dbg = env->dbg;
535 ir_mode *mode = env->mode;
536 ir_graph *irg = env->irg;
537 ir_node *block = env->block;
538 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
539 ir_node *nomem = new_NoMem();
540 ir_node *expr_op, *imm_op;
541 ir_node *op1 = get_Add_left(env->irn);
542 ir_node *op2 = get_Add_right(env->irn);
544 /* Check if immediate optimization is on and */
545 /* if it's an operation with immediate. */
546 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
547 expr_op = get_expr_op(op1, op2);
549 assert((expr_op || imm_op) && "invalid operands");
551 if (mode_is_float(mode)) {
553 if (USE_SSE2(env->cg))
554 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
556 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
561 /* No expr_op means, that we have two const - one symconst and */
562 /* one tarval or another symconst - because this case is not */
563 /* covered by constant folding */
564 /* We need to check for: */
565 /* 1) symconst + const -> becomes a LEA */
566 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
567 /* linker doesn't support two symconsts */
569 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
570 /* this is the 2nd case */
571 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
572 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
573 set_ia32_am_flavour(new_op, ia32_am_OB);
575 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
578 /* this is the 1st case */
579 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
581 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
583 if (get_ia32_op_type(op1) == ia32_SymConst) {
584 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
585 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
588 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
589 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
591 set_ia32_am_flavour(new_op, ia32_am_O);
595 set_ia32_am_support(new_op, ia32_am_Source);
596 set_ia32_op_type(new_op, ia32_AddrModeS);
598 /* Lea doesn't need a Proj */
602 /* This is expr + const */
603 new_op = gen_imm_Add(env, expr_op, imm_op);
606 set_ia32_am_support(new_op, ia32_am_Dest);
609 /* This is a normal add */
610 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
613 set_ia32_am_support(new_op, ia32_am_Full);
614 set_ia32_commutative(new_op);
618 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
620 set_ia32_res_mode(new_op, mode);
622 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
628 * Creates an ia32 Mul.
630 * @param env The transformation environment
631 * @return the created ia32 Mul node
633 static ir_node *gen_Mul(ia32_transform_env_t *env) {
634 ir_node *op1 = get_Mul_left(env->irn);
635 ir_node *op2 = get_Mul_right(env->irn);
638 if (mode_is_float(env->mode)) {
640 if (USE_SSE2(env->cg))
641 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
643 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
646 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
655 * Creates an ia32 Mulh.
656 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
657 * this result while Mul returns the lower 32 bit.
659 * @param env The transformation environment
660 * @return the created ia32 Mulh node
662 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
663 ir_node *op1 = get_irn_n(env->irn, 0);
664 ir_node *op2 = get_irn_n(env->irn, 1);
665 ir_node *proj_EAX, *proj_EDX, *mulh;
668 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
669 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
670 mulh = get_Proj_pred(proj_EAX);
671 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
673 /* to be on the save side */
674 set_Proj_proj(proj_EAX, pn_EAX);
676 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
677 /* Mulh with const cannot have AM */
678 set_ia32_am_support(mulh, ia32_am_None);
681 /* Mulh cannot have AM for destination */
682 set_ia32_am_support(mulh, ia32_am_Source);
688 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
696 * Creates an ia32 And.
698 * @param env The transformation environment
699 * @return The created ia32 And node
701 static ir_node *gen_And(ia32_transform_env_t *env) {
702 ir_node *op1 = get_And_left(env->irn);
703 ir_node *op2 = get_And_right(env->irn);
705 assert (! mode_is_float(env->mode));
706 return gen_binop(env, op1, op2, new_rd_ia32_And);
712 * Creates an ia32 Or.
714 * @param env The transformation environment
715 * @return The created ia32 Or node
717 static ir_node *gen_Or(ia32_transform_env_t *env) {
718 ir_node *op1 = get_Or_left(env->irn);
719 ir_node *op2 = get_Or_right(env->irn);
721 assert (! mode_is_float(env->mode));
722 return gen_binop(env, op1, op2, new_rd_ia32_Or);
728 * Creates an ia32 Eor.
730 * @param env The transformation environment
731 * @return The created ia32 Eor node
733 static ir_node *gen_Eor(ia32_transform_env_t *env) {
734 ir_node *op1 = get_Eor_left(env->irn);
735 ir_node *op2 = get_Eor_right(env->irn);
737 assert(! mode_is_float(env->mode));
738 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
744 * Creates an ia32 Max.
746 * @param env The transformation environment
747 * @return the created ia32 Max node
749 static ir_node *gen_Max(ia32_transform_env_t *env) {
750 ir_node *op1 = get_irn_n(env->irn, 0);
751 ir_node *op2 = get_irn_n(env->irn, 1);
754 if (mode_is_float(env->mode)) {
756 if (USE_SSE2(env->cg))
757 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
763 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
764 set_ia32_am_support(new_op, ia32_am_None);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
774 * Creates an ia32 Min.
776 * @param env The transformation environment
777 * @return the created ia32 Min node
779 static ir_node *gen_Min(ia32_transform_env_t *env) {
780 ir_node *op1 = get_irn_n(env->irn, 0);
781 ir_node *op2 = get_irn_n(env->irn, 1);
784 if (mode_is_float(env->mode)) {
786 if (USE_SSE2(env->cg))
787 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
793 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
794 set_ia32_am_support(new_op, ia32_am_None);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
804 * Creates an ia32 Sub with immediate.
806 * @param env The transformation environment
807 * @param expr_op The first operator
808 * @param const_op The constant operator
809 * @return The created ia32 Sub node
811 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
812 ir_node *new_op = NULL;
813 tarval *tv = get_ia32_Immop_tarval(const_op);
814 dbg_info *dbg = env->dbg;
815 ir_graph *irg = env->irg;
816 ir_node *block = env->block;
817 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
818 ir_node *nomem = new_NoMem();
820 tarval_classification_t class_tv, class_negtv;
821 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
823 /* try to optimize to inc/dec */
824 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
825 /* optimize tarvals */
826 class_tv = classify_tarval(tv);
827 class_negtv = classify_tarval(tarval_neg(tv));
829 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
830 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
831 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
834 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
835 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
836 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
842 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
843 set_ia32_Immop_attr(new_op, const_op);
850 * Creates an ia32 Sub.
852 * @param env The transformation environment
853 * @return The created ia32 Sub node
855 static ir_node *gen_Sub(ia32_transform_env_t *env) {
856 ir_node *new_op = NULL;
857 dbg_info *dbg = env->dbg;
858 ir_mode *mode = env->mode;
859 ir_graph *irg = env->irg;
860 ir_node *block = env->block;
861 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
862 ir_node *nomem = new_NoMem();
863 ir_node *op1 = get_Sub_left(env->irn);
864 ir_node *op2 = get_Sub_right(env->irn);
865 ir_node *expr_op, *imm_op;
867 /* Check if immediate optimization is on and */
868 /* if it's an operation with immediate. */
869 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
870 expr_op = get_expr_op(op1, op2);
872 assert((expr_op || imm_op) && "invalid operands");
874 if (mode_is_float(mode)) {
876 if (USE_SSE2(env->cg))
877 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
879 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
884 /* No expr_op means, that we have two const - one symconst and */
885 /* one tarval or another symconst - because this case is not */
886 /* covered by constant folding */
887 /* We need to check for: */
888 /* 1) symconst - const -> becomes a LEA */
889 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
890 /* linker doesn't support two symconsts */
892 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
893 /* this is the 2nd case */
894 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
895 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
896 set_ia32_am_sc_sign(new_op);
897 set_ia32_am_flavour(new_op, ia32_am_OB);
899 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
902 /* this is the 1st case */
903 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
905 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
907 if (get_ia32_op_type(op1) == ia32_SymConst) {
908 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
909 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
912 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
913 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
914 set_ia32_am_sc_sign(new_op);
916 set_ia32_am_flavour(new_op, ia32_am_O);
920 set_ia32_am_support(new_op, ia32_am_Source);
921 set_ia32_op_type(new_op, ia32_AddrModeS);
923 /* Lea doesn't need a Proj */
927 /* This is expr - const */
928 new_op = gen_imm_Sub(env, expr_op, imm_op);
931 set_ia32_am_support(new_op, ia32_am_Dest);
934 /* This is a normal sub */
935 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
938 set_ia32_am_support(new_op, ia32_am_Full);
942 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
944 set_ia32_res_mode(new_op, mode);
946 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
952 * Generates an ia32 DivMod with additional infrastructure for the
953 * register allocator if needed.
955 * @param env The transformation environment
956 * @param dividend -no comment- :)
957 * @param divisor -no comment- :)
958 * @param dm_flav flavour_Div/Mod/DivMod
959 * @return The created ia32 DivMod node
961 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
963 ir_node *edx_node, *cltd;
965 dbg_info *dbg = env->dbg;
966 ir_graph *irg = env->irg;
967 ir_node *block = env->block;
968 ir_mode *mode = env->mode;
969 ir_node *irn = env->irn;
975 mem = get_Div_mem(irn);
976 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
979 mem = get_Mod_mem(irn);
980 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
983 mem = get_DivMod_mem(irn);
984 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
990 if (mode_is_signed(mode)) {
991 /* in signed mode, we need to sign extend the dividend */
992 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
993 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
994 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
997 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
998 set_ia32_Const_type(edx_node, ia32_Const);
999 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1002 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
1004 set_ia32_n_res(res, 2);
1006 /* Only one proj is used -> We must add a second proj and */
1007 /* connect this one to a Keep node to eat up the second */
1008 /* destroyed register. */
1009 n = get_irn_n_edges(irn);
1012 proj = ia32_get_proj_for_mode(irn, mode_M);
1014 /* in case of two projs, one must be the memory proj */
1015 if (n == 1 || (n == 2 && proj)) {
1016 proj = ia32_get_res_proj(irn);
1017 assert(proj && "Result proj expected");
1019 if (get_irn_op(irn) == op_Div) {
1020 set_Proj_proj(proj, pn_DivMod_res_div);
1021 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
1024 set_Proj_proj(proj, pn_DivMod_res_mod);
1025 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
1028 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1031 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1033 ia32_renumber_Proj(env->irn, pn_DivMod_M, pn_ia32_DivMod_M);
1034 ia32_renumber_Proj(env->irn, pn_DivMod_res_mod, pn_ia32_DivMod_mod_res);
1035 ia32_renumber_Proj(env->irn, pn_DivMod_res_div, pn_ia32_DivMod_div_res);
1037 set_ia32_res_mode(res, mode);
1044 * Wrapper for generate_DivMod. Sets flavour_Mod.
1046 * @param env The transformation environment
1048 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1049 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1053 * Wrapper for generate_DivMod. Sets flavour_Div.
1055 * @param env The transformation environment
1057 static ir_node *gen_Div(ia32_transform_env_t *env) {
1058 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1062 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1064 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1065 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1071 * Creates an ia32 floating Div.
1073 * @param env The transformation environment
1074 * @return The created ia32 xDiv node
1076 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1077 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1079 ir_node *nomem = new_rd_NoMem(env->irg);
1080 ir_node *op1 = get_Quot_left(env->irn);
1081 ir_node *op2 = get_Quot_right(env->irn);
1084 if (USE_SSE2(env->cg)) {
1085 if (is_ia32_xConst(op2)) {
1086 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1087 set_ia32_am_support(new_op, ia32_am_None);
1088 set_ia32_Immop_attr(new_op, op2);
1091 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1092 set_ia32_am_support(new_op, ia32_am_Source);
1094 ia32_renumber_Proj(env->irn, pn_Quot_M, pn_ia32_xDiv_M);
1095 ia32_renumber_Proj(env->irn, pn_Quot_res, pn_ia32_xDiv_res);
1098 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1099 set_ia32_am_support(new_op, ia32_am_Source);
1100 ia32_renumber_Proj(env->irn, pn_Quot_M, pn_ia32_vfdiv_M);
1101 ia32_renumber_Proj(env->irn, pn_Quot_res, pn_ia32_vfdiv_res);
1103 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1104 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1111 * Creates an ia32 Shl.
1113 * @param env The transformation environment
1114 * @return The created ia32 Shl node
1116 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1117 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1123 * Creates an ia32 Shr.
1125 * @param env The transformation environment
1126 * @return The created ia32 Shr node
1128 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1129 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1135 * Creates an ia32 Shrs.
1137 * @param env The transformation environment
1138 * @return The created ia32 Shrs node
1140 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1141 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1147 * Creates an ia32 RotL.
1149 * @param env The transformation environment
1150 * @param op1 The first operator
1151 * @param op2 The second operator
1152 * @return The created ia32 RotL node
1154 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1155 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1161 * Creates an ia32 RotR.
1162 * NOTE: There is no RotR with immediate because this would always be a RotL
1163 * "imm-mode_size_bits" which can be pre-calculated.
1165 * @param env The transformation environment
1166 * @param op1 The first operator
1167 * @param op2 The second operator
1168 * @return The created ia32 RotR node
1170 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1171 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1177 * Creates an ia32 RotR or RotL (depending on the found pattern).
1179 * @param env The transformation environment
1180 * @return The created ia32 RotL or RotR node
1182 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1183 ir_node *rotate = NULL;
1184 ir_node *op1 = get_Rot_left(env->irn);
1185 ir_node *op2 = get_Rot_right(env->irn);
1187 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1188 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1189 that means we can create a RotR instead of an Add and a RotL */
1192 ir_node *pred = get_Proj_pred(op2);
1194 if (is_ia32_Add(pred)) {
1195 ir_node *pred_pred = get_irn_n(pred, 2);
1196 tarval *tv = get_ia32_Immop_tarval(pred);
1197 long bits = get_mode_size_bits(env->mode);
1199 if (is_Proj(pred_pred)) {
1200 pred_pred = get_Proj_pred(pred_pred);
1203 if (is_ia32_Minus(pred_pred) &&
1204 tarval_is_long(tv) &&
1205 get_tarval_long(tv) == bits)
1207 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1208 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1215 rotate = gen_RotL(env, op1, op2);
1224 * Transforms a Minus node.
1226 * @param env The transformation environment
1227 * @param op The Minus operand
1228 * @return The created ia32 Minus node
1230 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1235 if (mode_is_float(env->mode)) {
1237 if (USE_SSE2(env->cg)) {
1238 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1239 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1240 ir_node *nomem = new_rd_NoMem(env->irg);
1242 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1244 size = get_mode_size_bits(env->mode);
1245 name = gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1247 set_ia32_am_sc(new_op, name);
1249 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1251 set_ia32_res_mode(new_op, env->mode);
1252 set_ia32_op_type(new_op, ia32_AddrModeS);
1253 set_ia32_ls_mode(new_op, env->mode);
1255 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1258 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1259 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1263 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1270 * Transforms a Minus node.
1272 * @param env The transformation environment
1273 * @return The created ia32 Minus node
1275 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1276 return gen_Minus_ex(env, get_Minus_op(env->irn));
1281 * Transforms a Not node.
1283 * @param env The transformation environment
1284 * @return The created ia32 Not node
1286 static ir_node *gen_Not(ia32_transform_env_t *env) {
1287 assert (! mode_is_float(env->mode));
1288 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1294 * Transforms an Abs node.
1296 * @param env The transformation environment
1297 * @return The created ia32 Abs node
1299 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1300 ir_node *res, *p_eax, *p_edx;
1301 dbg_info *dbg = env->dbg;
1302 ir_mode *mode = env->mode;
1303 ir_graph *irg = env->irg;
1304 ir_node *block = env->block;
1305 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1306 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1307 ir_node *nomem = new_NoMem();
1308 ir_node *op = get_Abs_op(env->irn);
1312 if (mode_is_float(mode)) {
1314 if (USE_SSE2(env->cg)) {
1315 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1317 size = get_mode_size_bits(mode);
1318 name = gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1320 set_ia32_am_sc(res, name);
1322 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1324 set_ia32_res_mode(res, mode);
1325 set_ia32_op_type(res, ia32_AddrModeS);
1326 set_ia32_ls_mode(res, env->mode);
1328 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1331 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1332 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1336 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1337 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1338 set_ia32_res_mode(res, mode);
1340 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1341 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1343 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1344 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1345 set_ia32_res_mode(res, mode);
1347 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1349 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1350 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1351 set_ia32_res_mode(res, mode);
1353 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1362 * Transforms a Load.
1364 * @param env The transformation environment
1365 * @return the created ia32 Load node
1367 static ir_node *gen_Load(ia32_transform_env_t *env) {
1368 ir_node *node = env->irn;
1369 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1370 ir_node *ptr = get_Load_ptr(node);
1371 ir_node *lptr = ptr;
1372 ir_mode *mode = get_Load_mode(node);
1375 ia32_am_flavour_t am_flav = ia32_am_B;
1377 /* address might be a constant (symconst or absolute address) */
1378 if (is_ia32_Const(ptr)) {
1383 if (mode_is_float(mode)) {
1385 if (USE_SSE2(env->cg)) {
1386 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1387 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_xLoad_M);
1388 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_xLoad_res);
1391 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1392 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_vfld_M);
1393 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_vfld_res);
1397 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1398 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_Load_M);
1399 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_Load_res);
1402 /* base is an constant address */
1404 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1405 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1406 am_flav = ia32_am_N;
1409 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1410 am_flav = ia32_am_O;
1414 set_ia32_am_support(new_op, ia32_am_Source);
1415 set_ia32_op_type(new_op, ia32_AddrModeS);
1416 set_ia32_am_flavour(new_op, am_flav);
1417 set_ia32_ls_mode(new_op, mode);
1420 check for special case: the loaded value might not be used (optimized, volatile, ...)
1421 we add a Proj + Keep for volatile loads and ignore all other cases
1423 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1424 /* add a result proj and a Keep to produce a pseudo use */
1425 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1426 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1429 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1437 * Transforms a Store.
1439 * @param env The transformation environment
1440 * @return the created ia32 Store node
1442 static ir_node *gen_Store(ia32_transform_env_t *env) {
1443 ir_node *node = env->irn;
1444 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1445 ir_node *val = get_Store_value(node);
1446 ir_node *ptr = get_Store_ptr(node);
1447 ir_node *sptr = ptr;
1448 ir_node *mem = get_Store_mem(node);
1449 ir_mode *mode = get_irn_mode(val);
1450 ir_node *sval = val;
1453 ia32_am_flavour_t am_flav = ia32_am_B;
1454 ia32_immop_type_t immop = ia32_ImmNone;
1456 if (! mode_is_float(mode)) {
1457 /* in case of storing a const (but not a symconst) -> make it an attribute */
1458 if (is_ia32_Cnst(val)) {
1459 switch (get_ia32_op_type(val)) {
1461 immop = ia32_ImmConst;
1464 immop = ia32_ImmSymConst;
1467 assert(0 && "unsupported Const type");
1473 /* address might be a constant (symconst or absolute address) */
1474 if (is_ia32_Const(ptr)) {
1479 if (mode_is_float(mode)) {
1481 if (USE_SSE2(env->cg)) {
1482 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1483 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_xStore_M);
1486 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1487 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_vfst_M);
1490 else if (get_mode_size_bits(mode) == 8) {
1491 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1492 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store8Bit_M);
1495 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1496 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store_M);
1499 /* stored const is an attribute (saves a register) */
1500 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1501 set_ia32_Immop_attr(new_op, val);
1504 /* base is an constant address */
1506 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1507 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1508 am_flav = ia32_am_N;
1511 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1512 am_flav = ia32_am_O;
1516 set_ia32_am_support(new_op, ia32_am_Dest);
1517 set_ia32_op_type(new_op, ia32_AddrModeD);
1518 set_ia32_am_flavour(new_op, am_flav);
1519 set_ia32_ls_mode(new_op, mode);
1520 set_ia32_immop_type(new_op, immop);
1522 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1530 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1532 * @param env The transformation environment
1533 * @return The transformed node.
1535 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1536 dbg_info *dbg = env->dbg;
1537 ir_graph *irg = env->irg;
1538 ir_node *block = env->block;
1539 ir_node *node = env->irn;
1540 ir_node *sel = get_Cond_selector(node);
1541 ir_mode *sel_mode = get_irn_mode(sel);
1542 ir_node *res = NULL;
1543 ir_node *pred = NULL;
1544 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1545 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1547 if (is_Proj(sel) && sel_mode == mode_b) {
1548 ir_node *nomem = new_NoMem();
1549 pn_Cmp pnc = get_Proj_proj(sel);
1551 pred = get_Proj_pred(sel);
1553 /* get both compare operators */
1554 cmp_a = get_Cmp_left(pred);
1555 cmp_b = get_Cmp_right(pred);
1557 /* check if we can use a CondJmp with immediate */
1558 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1559 expr = get_expr_op(cmp_a, cmp_b);
1562 /* immop has to be the right operand, we might need to flip pnc */
1564 pnc = get_inversed_pnc(pnc);
1567 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1568 if (get_ia32_op_type(cnst) == ia32_Const &&
1569 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1571 /* a Cmp A =/!= 0 */
1572 ir_node *op1 = expr;
1573 ir_node *op2 = expr;
1574 ir_node *and = skip_Proj(expr);
1575 const char *cnst = NULL;
1577 /* check, if expr is an only once used And operation */
1578 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1579 op1 = get_irn_n(and, 2);
1580 op2 = get_irn_n(and, 3);
1582 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1584 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1585 set_ia32_pncode(res, pnc);
1586 set_ia32_res_mode(res, get_irn_mode(op1));
1589 copy_ia32_Immop_attr(res, and);
1592 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1597 if (mode_is_float(get_irn_mode(expr))) {
1599 if (USE_SSE2(env->cg))
1600 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1606 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1608 set_ia32_Immop_attr(res, cnst);
1609 set_ia32_res_mode(res, get_irn_mode(expr));
1612 if (mode_is_float(get_irn_mode(cmp_a))) {
1614 if (USE_SSE2(env->cg))
1615 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1618 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1619 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1620 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1624 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1625 set_ia32_commutative(res);
1627 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1630 set_ia32_pncode(res, pnc);
1631 //set_ia32_am_support(res, ia32_am_Source);
1634 /* determine the smallest switch case value */
1635 int switch_min = INT_MAX;
1636 const ir_edge_t *edge;
1639 foreach_out_edge(node, edge) {
1640 int pn = get_Proj_proj(get_edge_src_irn(edge));
1641 switch_min = pn < switch_min ? pn : switch_min;
1645 /* if smallest switch case is not 0 we need an additional sub */
1646 snprintf(buf, sizeof(buf), "%d", switch_min);
1647 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1648 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1649 sub_ia32_am_offs(res, buf);
1650 set_ia32_am_flavour(res, ia32_am_OB);
1651 set_ia32_am_support(res, ia32_am_Source);
1652 set_ia32_op_type(res, ia32_AddrModeS);
1655 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1656 set_ia32_pncode(res, get_Cond_defaultProj(node));
1657 set_ia32_res_mode(res, get_irn_mode(sel));
1660 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1667 * Transforms a CopyB node.
1669 * @param env The transformation environment
1670 * @return The transformed node.
1672 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1673 ir_node *res = NULL;
1674 dbg_info *dbg = env->dbg;
1675 ir_graph *irg = env->irg;
1676 ir_node *block = env->block;
1677 ir_node *node = env->irn;
1678 ir_node *src = get_CopyB_src(node);
1679 ir_node *dst = get_CopyB_dst(node);
1680 ir_node *mem = get_CopyB_mem(node);
1681 int size = get_type_size_bytes(get_CopyB_type(node));
1682 ir_mode *dst_mode = get_irn_mode(dst);
1683 ir_mode *src_mode = get_irn_mode(src);
1687 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1688 /* then we need the size explicitly in ECX. */
1689 if (size >= 32 * 4) {
1690 rem = size & 0x3; /* size % 4 */
1693 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1694 set_ia32_op_type(res, ia32_Const);
1695 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1697 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
1698 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1700 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1701 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1702 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1703 in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
1704 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1706 ia32_renumber_Proj(env->irn, pn_CopyB_M_regular, pn_ia32_CopyB_M);
1709 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
1710 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1711 set_ia32_immop_type(res, ia32_ImmConst);
1713 /* ok: now attach Proj's because movsd will destroy esi and edi */
1714 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1715 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1716 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1718 ia32_renumber_Proj(env->irn, pn_CopyB_M_regular, pn_ia32_CopyB_i_M);
1721 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1729 * Transforms a Mux node into CMov.
1731 * @param env The transformation environment
1732 * @return The transformed node.
1734 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1736 ir_node *node = env->irn;
1737 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1738 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1740 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1747 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1748 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1751 * Transforms a Psi node into CMov.
1753 * @param env The transformation environment
1754 * @return The transformed node.
1756 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1757 ia32_code_gen_t *cg = env->cg;
1758 dbg_info *dbg = env->dbg;
1759 ir_graph *irg = env->irg;
1760 ir_mode *mode = env->mode;
1761 ir_node *block = env->block;
1762 ir_node *node = env->irn;
1763 ir_node *cmp_proj = get_Mux_sel(node);
1764 ir_node *psi_true = get_Psi_val(node, 0);
1765 ir_node *psi_default = get_Psi_default(node);
1766 ir_node *noreg = ia32_new_NoReg_gp(cg);
1767 ir_node *nomem = new_rd_NoMem(irg);
1768 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1771 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1773 cmp = get_Proj_pred(cmp_proj);
1774 cmp_a = get_Cmp_left(cmp);
1775 cmp_b = get_Cmp_right(cmp);
1776 pnc = get_Proj_proj(cmp_proj);
1778 if (mode_is_float(mode)) {
1779 /* floating point psi */
1782 /* 1st case: compare operands are float too */
1784 /* psi(cmp(a, b), t, f) can be done as: */
1785 /* tmp = cmp a, b */
1786 /* tmp2 = t and tmp */
1787 /* tmp3 = f and not tmp */
1788 /* res = tmp2 or tmp3 */
1790 /* in case the compare operands are int, we move them into xmm register */
1791 if (! mode_is_float(get_irn_mode(cmp_a))) {
1792 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1793 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1795 pnc |= 8; /* transform integer compare to fp compare */
1798 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1799 set_ia32_pncode(new_op, pnc);
1800 set_ia32_am_support(new_op, ia32_am_Source);
1801 set_ia32_res_mode(new_op, mode);
1802 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1803 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1805 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1806 set_ia32_am_support(and1, ia32_am_None);
1807 set_ia32_res_mode(and1, mode);
1808 set_ia32_commutative(and1);
1809 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1810 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1812 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1813 set_ia32_am_support(and2, ia32_am_None);
1814 set_ia32_res_mode(and2, mode);
1815 set_ia32_commutative(and2);
1816 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1817 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1819 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1820 set_ia32_am_support(new_op, ia32_am_None);
1821 set_ia32_res_mode(new_op, mode);
1822 set_ia32_commutative(new_op);
1823 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1824 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1828 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1829 set_ia32_pncode(new_op, pnc);
1830 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1835 construct_binop_func *set_func = NULL;
1836 cmov_func_t *cmov_func = NULL;
1838 if (mode_is_float(get_irn_mode(cmp_a))) {
1839 /* 1st case: compare operands are floats */
1844 set_func = new_rd_ia32_xCmpSet;
1845 cmov_func = new_rd_ia32_xCmpCMov;
1849 set_func = new_rd_ia32_vfCmpSet;
1850 cmov_func = new_rd_ia32_vfCmpCMov;
1853 pnc &= 7; /* fp compare -> int compare */
1856 /* 2nd case: compare operand are integer too */
1857 set_func = new_rd_ia32_CmpSet;
1858 cmov_func = new_rd_ia32_CmpCMov;
1861 /* create the nodes */
1863 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1864 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1865 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1866 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1867 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1868 set_ia32_pncode(new_op, pnc);
1870 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1871 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1872 /* we invert condition and set default to 0 */
1873 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1874 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1877 /* otherwise: use CMOVcc */
1878 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1879 set_ia32_pncode(new_op, pnc);
1882 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1886 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1887 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1888 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1889 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1890 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1892 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1893 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1894 /* we invert condition and set default to 0 */
1895 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1896 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1897 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1900 /* otherwise: use CMOVcc */
1901 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1902 set_ia32_pncode(new_op, pnc);
1903 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1913 * Following conversion rules apply:
1917 * 1) n bit -> m bit n > m (downscale)
1918 * a) target is signed: movsx
1919 * b) target is unsigned: and with lower bits sets
1920 * 2) n bit -> m bit n == m (sign change)
1922 * 3) n bit -> m bit n < m (upscale)
1923 * a) source is signed: movsx
1924 * b) source is unsigned: and with lower bits sets
1928 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1932 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1933 * if target mode < 32bit: additional INT -> INT conversion (see above)
1937 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1938 * x87 is mode_E internally, conversions happen only at load and store
1939 * in non-strict semantic
1943 * Create a conversion from x87 state register to general purpose.
1945 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1946 ia32_code_gen_t *cg = env->cg;
1947 entity *ent = cg->fp_to_gp;
1948 ir_graph *irg = env->irg;
1949 ir_node *block = env->block;
1950 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1951 ir_node *op = get_Conv_op(env->irn);
1952 ir_node *fist, *mem, *load;
1955 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1956 ent = cg->fp_to_gp =
1957 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1961 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1963 set_ia32_frame_ent(fist, ent);
1964 set_ia32_use_frame(fist);
1965 set_ia32_am_support(fist, ia32_am_Dest);
1966 set_ia32_op_type(fist, ia32_AddrModeD);
1967 set_ia32_am_flavour(fist, ia32_B);
1968 set_ia32_ls_mode(fist, mode_F);
1970 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1973 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1975 set_ia32_frame_ent(load, ent);
1976 set_ia32_use_frame(load);
1977 set_ia32_am_support(load, ia32_am_Source);
1978 set_ia32_op_type(load, ia32_AddrModeS);
1979 set_ia32_am_flavour(load, ia32_B);
1980 set_ia32_ls_mode(load, tgt_mode);
1982 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1986 * Create a conversion from x87 state register to general purpose.
1988 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1989 ia32_code_gen_t *cg = env->cg;
1990 entity *ent = cg->gp_to_fp;
1991 ir_graph *irg = env->irg;
1992 ir_node *block = env->block;
1993 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1994 ir_node *nomem = get_irg_no_mem(irg);
1995 ir_node *op = get_Conv_op(env->irn);
1996 ir_node *fild, *store, *mem;
2000 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
2001 ent = cg->gp_to_fp =
2002 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
2005 /* first convert to 32 bit */
2006 src_bits = get_mode_size_bits(src_mode);
2007 if (src_bits == 8) {
2008 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
2009 op = new_r_Proj(irg, block, op, mode_Is, 0);
2011 else if (src_bits < 32) {
2012 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
2013 op = new_r_Proj(irg, block, op, mode_Is, 0);
2017 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
2019 set_ia32_frame_ent(store, ent);
2020 set_ia32_use_frame(store);
2022 set_ia32_am_support(store, ia32_am_Dest);
2023 set_ia32_op_type(store, ia32_AddrModeD);
2024 set_ia32_am_flavour(store, ia32_B);
2025 set_ia32_ls_mode(store, mode_Is);
2027 mem = new_r_Proj(irg, block, store, mode_M, pn_ia32_Store_M);
2030 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
2032 set_ia32_frame_ent(fild, ent);
2033 set_ia32_use_frame(fild);
2034 set_ia32_am_support(fild, ia32_am_Source);
2035 set_ia32_op_type(fild, ia32_AddrModeS);
2036 set_ia32_am_flavour(fild, ia32_B);
2037 set_ia32_ls_mode(fild, mode_F);
2039 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2043 * Transforms a Conv node.
2045 * @param env The transformation environment
2046 * @return The created ia32 Conv node
2048 static ir_node *gen_Conv(ia32_transform_env_t *env) {
2049 dbg_info *dbg = env->dbg;
2050 ir_graph *irg = env->irg;
2051 ir_node *op = get_Conv_op(env->irn);
2052 ir_mode *src_mode = get_irn_mode(op);
2053 ir_mode *tgt_mode = env->mode;
2054 int src_bits = get_mode_size_bits(src_mode);
2055 int tgt_bits = get_mode_size_bits(tgt_mode);
2058 ir_node *block = env->block;
2059 ir_node *new_op = NULL;
2060 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2061 ir_node *nomem = new_rd_NoMem(irg);
2063 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2065 if (src_mode == tgt_mode) {
2066 /* this can happen when changing mode_P to mode_Is */
2067 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2068 edges_reroute(env->irn, op, irg);
2070 else if (mode_is_float(src_mode)) {
2071 /* we convert from float ... */
2072 if (mode_is_float(tgt_mode)) {
2074 if (USE_SSE2(env->cg)) {
2075 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2076 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2077 pn = pn_ia32_Conv_FP2FP_res;
2080 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2082 remark: we create a intermediate conv here, so modes will be spread correctly
2083 these convs will be killed later
2085 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2086 pn = pn_ia32_Conv_FP2FP_res;
2092 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2093 if (USE_SSE2(env->cg)) {
2094 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2095 pn = pn_ia32_Conv_FP2I_res;
2098 return gen_x87_fp_to_gp(env, tgt_mode);
2100 /* if target mode is not int: add an additional downscale convert */
2101 if (tgt_bits < 32) {
2102 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2103 set_ia32_am_support(new_op, ia32_am_Source);
2104 set_ia32_tgt_mode(new_op, mode_Is);
2105 set_ia32_src_mode(new_op, src_mode);
2107 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2109 if (tgt_bits == 8 || src_bits == 8) {
2110 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2111 pn = pn_ia32_Conv_I2I8Bit_res;
2114 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2115 pn = pn_ia32_Conv_I2I_res;
2122 /* we convert from int ... */
2123 if (mode_is_float(tgt_mode)) {
2126 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2127 if (USE_SSE2(env->cg)) {
2128 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2129 pn = pn_ia32_Conv_I2FP_res;
2132 return gen_x87_gp_to_fp(env, src_mode);
2136 if (get_mode_size_bits(src_mode) == tgt_bits) {
2137 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2139 remark: we create a intermediate conv here, so modes will be spread correctly
2140 these convs will be killed later
2142 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2143 pn = pn_ia32_Conv_I2I_res;
2147 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2148 if (tgt_bits == 8 || src_bits == 8) {
2149 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2150 pn = pn_ia32_Conv_I2I8Bit_res;
2153 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2154 pn = pn_ia32_Conv_I2I_res;
2161 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2162 set_ia32_tgt_mode(new_op, tgt_mode);
2163 set_ia32_src_mode(new_op, src_mode);
2165 set_ia32_am_support(new_op, ia32_am_Source);
2167 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2170 nodeset_insert(env->cg->kill_conv, new_op);
2178 /********************************************
2181 * | |__ ___ _ __ ___ __| | ___ ___
2182 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2183 * | |_) | __/ | | | (_) | (_| | __/\__ \
2184 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2186 ********************************************/
2188 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2189 ir_node *new_op = NULL;
2190 ir_node *node = env->irn;
2191 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2192 ir_node *mem = new_rd_NoMem(env->irg);
2193 ir_node *ptr = get_irn_n(node, 0);
2194 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2195 ir_mode *mode = env->mode;
2198 if (mode_is_float(mode)) {
2200 if (USE_SSE2(env->cg)) {
2201 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2202 pn_res = pn_ia32_xLoad_res;
2205 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2206 pn_res = pn_ia32_vfld_res;
2210 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2211 pn_res = pn_ia32_Load_res;
2214 set_ia32_frame_ent(new_op, ent);
2215 set_ia32_use_frame(new_op);
2217 set_ia32_am_support(new_op, ia32_am_Source);
2218 set_ia32_op_type(new_op, ia32_AddrModeS);
2219 set_ia32_am_flavour(new_op, ia32_B);
2220 set_ia32_ls_mode(new_op, mode);
2221 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2223 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2225 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_res);
2229 * Transforms a FrameAddr into an ia32 Add.
2231 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2232 ir_node *new_op = NULL;
2233 ir_node *node = env->irn;
2234 ir_node *op = get_irn_n(node, 0);
2235 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2236 ir_node *nomem = new_rd_NoMem(env->irg);
2238 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2239 set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node));
2240 set_ia32_am_support(new_op, ia32_am_Full);
2241 set_ia32_use_frame(new_op);
2242 set_ia32_immop_type(new_op, ia32_ImmConst);
2243 set_ia32_commutative(new_op);
2245 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2247 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2251 * Transforms a FrameLoad into an ia32 Load.
2253 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2254 ir_node *new_op = NULL;
2255 ir_node *node = env->irn;
2256 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2257 ir_node *mem = get_irn_n(node, 0);
2258 ir_node *ptr = get_irn_n(node, 1);
2259 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2260 ir_mode *mode = get_type_mode(get_entity_type(ent));
2262 if (mode_is_float(mode)) {
2264 if (USE_SSE2(env->cg)) {
2265 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2266 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_xLoad_M);
2267 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_xLoad_res);
2270 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2271 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_vfld_M);
2272 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_vfld_res);
2276 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2277 ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_Load_M);
2278 ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_Load_res);
2281 set_ia32_frame_ent(new_op, ent);
2282 set_ia32_use_frame(new_op);
2284 set_ia32_am_support(new_op, ia32_am_Source);
2285 set_ia32_op_type(new_op, ia32_AddrModeS);
2286 set_ia32_am_flavour(new_op, ia32_B);
2287 set_ia32_ls_mode(new_op, mode);
2289 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2296 * Transforms a FrameStore into an ia32 Store.
2298 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2299 ir_node *new_op = NULL;
2300 ir_node *node = env->irn;
2301 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2302 ir_node *mem = get_irn_n(node, 0);
2303 ir_node *ptr = get_irn_n(node, 1);
2304 ir_node *val = get_irn_n(node, 2);
2305 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2306 ir_mode *mode = get_irn_mode(val);
2308 if (mode_is_float(mode)) {
2310 if (USE_SSE2(env->cg)) {
2311 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2312 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_xStore_M);
2315 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2316 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_vfst_M);
2319 else if (get_mode_size_bits(mode) == 8) {
2320 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2321 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store8Bit_M);
2324 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2325 ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store_M);
2328 set_ia32_frame_ent(new_op, ent);
2329 set_ia32_use_frame(new_op);
2331 set_ia32_am_support(new_op, ia32_am_Dest);
2332 set_ia32_op_type(new_op, ia32_AddrModeD);
2333 set_ia32_am_flavour(new_op, ia32_B);
2334 set_ia32_ls_mode(new_op, mode);
2336 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2342 * In case SSE is used we need to copy the result from FPU TOS.
2344 static ir_node *gen_be_Call(ia32_transform_env_t *env) {
2345 ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
2346 ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
2349 if (! call_res || ! USE_SSE2(env->cg))
2352 mode = get_irn_mode(call_res);
2354 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2356 call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular);
2358 if (mode_is_float(mode)) {
2359 /* store st(0) onto stack */
2360 ir_node *frame = get_irg_frame(env->irg);
2361 ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
2362 ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
2363 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2364 ir_node *sse_load, *p, *bad, *keep;
2368 set_ia32_ls_mode(fstp, mode);
2369 set_ia32_op_type(fstp, ia32_AddrModeD);
2370 set_ia32_use_frame(fstp);
2371 set_ia32_frame_ent(fstp, ent);
2372 set_ia32_am_flavour(fstp, ia32_B);
2373 set_ia32_am_support(fstp, ia32_am_Dest);
2375 /* load into SSE register */
2376 sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
2377 set_ia32_ls_mode(sse_load, mode);
2378 set_ia32_op_type(sse_load, ia32_AddrModeS);
2379 set_ia32_use_frame(sse_load);
2380 set_ia32_frame_ent(sse_load, ent);
2381 set_ia32_am_flavour(sse_load, ia32_B);
2382 set_ia32_am_support(sse_load, ia32_am_Source);
2383 sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
2385 /* reroute all users of the result proj to the sse load */
2386 edges_reroute(call_res, sse_load, env->irg);
2388 /* now: create new Keep whith all former ins and one additional in - the result Proj */
2390 /* get a Proj representing a caller save register */
2391 p = get_proj_for_pn(env->irn, pn_be_Call_first_res + 1);
2392 assert(is_Proj(p) && "Proj expected.");
2394 /* user of the the proj is the Keep */
2395 p = get_edge_src_irn(get_irn_out_edge_first(p));
2396 assert(be_is_Keep(p) && "Keep expected.");
2398 /* copy in array of the old keep and set the result proj as additional in */
2399 keep_arity = get_irn_arity(p) + 1;
2400 NEW_ARR_A(ir_node *, in_keep, keep_arity);
2401 in_keep[keep_arity - 1] = call_res;
2402 for (i = 0; i < keep_arity - 1; ++i)
2403 in_keep[i] = get_irn_n(p, i);
2405 /* create new keep and set the in class requirements properly */
2406 keep = be_new_Keep(NULL, env->irg, env->block, keep_arity, in_keep);
2407 for(i = 0; i < keep_arity; ++i) {
2408 const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
2409 be_node_set_reg_class(keep, i, cls);
2412 /* kill the old keep */
2413 bad = get_irg_bad(env->irg);
2414 for (i = 0; i < keep_arity - 1; i++)
2415 set_irn_n(p, i, bad);
2416 remove_End_keepalive(get_irg_end(env->irg), p);
2423 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2425 static ir_node *gen_be_Return(ia32_transform_env_t *env) {
2426 ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
2427 ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
2428 entity *ent = get_irg_entity(get_irn_irg(ret_val));
2429 ir_type *tp = get_entity_type(ent);
2431 if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
2434 if (get_method_n_ress(tp) == 1) {
2435 ir_type *res_type = get_method_res_type(tp, 0);
2438 if (is_Primitive_type(res_type)) {
2439 mode = get_type_mode(res_type);
2440 if (mode_is_float(mode)) {
2443 ir_node *sse_store, *fld, *mproj, *barrier;
2444 int pn_ret_val = get_Proj_proj(ret_val);
2445 int pn_ret_mem = get_Proj_proj(ret_mem);
2447 /* get the Barrier */
2448 barrier = get_Proj_pred(ret_val);
2450 /* get result input of the Barrier */
2451 ret_val = get_irn_n(barrier, pn_ret_val);
2453 /* get memory input of the Barrier */
2454 ret_mem = get_irn_n(barrier, pn_ret_mem);
2456 frame = get_irg_frame(env->irg);
2457 ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2459 /* store xmm0 onto stack */
2460 sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
2461 set_ia32_ls_mode(sse_store, mode);
2462 set_ia32_op_type(sse_store, ia32_AddrModeD);
2463 set_ia32_use_frame(sse_store);
2464 set_ia32_frame_ent(sse_store, ent);
2465 set_ia32_am_flavour(sse_store, ia32_B);
2466 set_ia32_am_support(sse_store, ia32_am_Dest);
2467 sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
2470 fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
2471 set_ia32_ls_mode(fld, mode);
2472 set_ia32_op_type(fld, ia32_AddrModeS);
2473 set_ia32_use_frame(fld);
2474 set_ia32_frame_ent(fld, ent);
2475 set_ia32_am_flavour(fld, ia32_B);
2476 set_ia32_am_support(fld, ia32_am_Source);
2477 mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
2478 fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
2479 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2481 /* set new return value */
2482 set_irn_n(barrier, pn_ret_val, fld);
2483 set_irn_n(barrier, pn_ret_mem, mproj);
2492 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2494 static ir_node *gen_be_AddSP(ia32_transform_env_t *env) {
2496 const ir_edge_t *edge;
2497 ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size);
2498 ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp);
2500 new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz);
2502 if (is_ia32_Const(sz)) {
2503 set_ia32_Immop_attr(new_op, sz);
2504 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2506 else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
2507 set_ia32_immop_type(new_op, ia32_ImmSymConst);
2508 set_ia32_op_type(new_op, ia32_AddrModeS);
2509 set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
2510 add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
2511 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2515 foreach_out_edge(env->irn, edge) {
2516 ir_node *proj = get_edge_src_irn(edge);
2518 assert(is_Proj(proj));
2520 if (get_Proj_proj(proj) == pn_be_AddSP_res) {
2521 /* the node is not yet exchanged: we need to set the register manually */
2522 ia32_attr_t *attr = get_ia32_attr(new_op);
2523 attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP];
2524 set_Proj_proj(proj, pn_ia32_AddSP_stack);
2526 else if (get_Proj_proj(proj) == pn_be_AddSP_M) {
2527 set_Proj_proj(proj, pn_ia32_AddSP_M);
2534 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2540 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2542 static ir_node *gen_be_SubSP(ia32_transform_env_t *env) {
2544 const ir_edge_t *edge;
2545 ir_node *sz = get_irn_n(env->irn, be_pos_SubSP_size);
2546 ir_node *sp = get_irn_n(env->irn, be_pos_SubSP_old_sp);
2548 new_op = new_rd_ia32_SubSP(env->dbg, env->irg, env->block, sp, sz);
2550 if (is_ia32_Const(sz)) {
2551 set_ia32_Immop_attr(new_op, sz);
2552 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2554 else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
2555 set_ia32_immop_type(new_op, ia32_ImmSymConst);
2556 set_ia32_op_type(new_op, ia32_AddrModeS);
2557 set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
2558 add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
2559 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2563 foreach_out_edge(env->irn, edge) {
2564 ir_node *proj = get_edge_src_irn(edge);
2566 assert(is_Proj(proj));
2568 if (get_Proj_proj(proj) == pn_be_SubSP_res) {
2569 /* the node is not yet exchanged: we need to set the register manually */
2570 ia32_attr_t *attr = get_ia32_attr(new_op);
2571 attr->slots[pn_ia32_SubSP_stack] = &ia32_gp_regs[REG_ESP];
2572 set_Proj_proj(proj, pn_ia32_SubSP_stack);
2574 else if (get_Proj_proj(proj) == pn_be_SubSP_M) {
2575 set_Proj_proj(proj, pn_ia32_SubSP_M);
2582 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2588 * This function just sets the register for the Unknown node
2589 * as this is not done during register allocation because Unknown
2590 * is an "ignore" node.
2592 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2593 ir_mode *mode = env->mode;
2594 ir_node *irn = env->irn;
2596 if (mode_is_float(mode)) {
2597 if (USE_SSE2(env->cg))
2598 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2600 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2602 else if (mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode)) {
2603 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2606 assert(0 && "unsupported Unknown-Mode");
2612 /**********************************************************************
2615 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2616 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2617 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2618 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2620 **********************************************************************/
2622 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2624 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2627 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2628 ir_node *val, ir_node *mem);
2631 * Transforms a lowered Load into a "real" one.
2633 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2634 ir_node *node = env->irn;
2635 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2636 ir_mode *mode = get_ia32_ls_mode(node);
2639 ia32_am_flavour_t am_flav = ia32_B;
2642 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2643 lowering we have x87 nodes, so we need to enforce simulation.
2645 if (mode_is_float(mode)) {
2647 if (fp_unit == fp_x87)
2651 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2652 am_offs = get_ia32_am_offs(node);
2656 add_ia32_am_offs(new_op, am_offs);
2659 set_ia32_am_support(new_op, ia32_am_Source);
2660 set_ia32_op_type(new_op, ia32_AddrModeS);
2661 set_ia32_am_flavour(new_op, am_flav);
2662 set_ia32_ls_mode(new_op, mode);
2663 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2664 set_ia32_use_frame(new_op);
2666 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2672 * Transforms a lowered Store into a "real" one.
2674 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2675 ir_node *node = env->irn;
2676 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2677 ir_mode *mode = get_ia32_ls_mode(node);
2680 ia32_am_flavour_t am_flav = ia32_B;
2683 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2684 lowering we have x87 nodes, so we need to enforce simulation.
2686 if (mode_is_float(mode)) {
2688 if (fp_unit == fp_x87)
2692 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2694 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2696 add_ia32_am_offs(new_op, am_offs);
2699 set_ia32_am_support(new_op, ia32_am_Dest);
2700 set_ia32_op_type(new_op, ia32_AddrModeD);
2701 set_ia32_am_flavour(new_op, am_flav);
2702 set_ia32_ls_mode(new_op, mode);
2703 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2704 set_ia32_use_frame(new_op);
2706 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2713 * Transforms an ia32_l_XXX into a "real" XXX node
2715 * @param env The transformation environment
2716 * @return the created ia32 XXX node
2718 #define GEN_LOWERED_OP(op) \
2719 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2720 if (mode_is_float(env->mode)) \
2722 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2725 #define GEN_LOWERED_x87_OP(op) \
2726 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2728 FORCE_x87(env->cg); \
2729 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2730 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2734 #define GEN_LOWERED_UNOP(op) \
2735 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2736 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2739 #define GEN_LOWERED_SHIFT_OP(op) \
2740 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2741 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2744 #define GEN_LOWERED_LOAD(op, fp_unit) \
2745 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2746 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2749 #define GEN_LOWERED_STORE(op, fp_unit) \
2750 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2751 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2754 GEN_LOWERED_OP(AddC)
2756 GEN_LOWERED_OP(SubC)
2760 GEN_LOWERED_x87_OP(vfdiv)
2761 GEN_LOWERED_x87_OP(vfmul)
2762 GEN_LOWERED_x87_OP(vfsub)
2764 GEN_LOWERED_UNOP(Minus)
2766 GEN_LOWERED_LOAD(vfild, fp_x87)
2767 GEN_LOWERED_LOAD(Load, fp_none)
2768 GEN_LOWERED_STORE(vfist, fp_x87)
2769 GEN_LOWERED_STORE(Store, fp_none)
2772 * Transforms a l_MulS into a "real" MulS node.
2774 * @param env The transformation environment
2775 * @return the created ia32 MulS node
2777 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2779 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2780 /* and then skip the result Proj, because all needed Projs are already there. */
2782 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2783 ir_node *muls = get_Proj_pred(new_op);
2785 /* MulS cannot have AM for destination */
2786 if (get_ia32_am_support(muls) != ia32_am_None)
2787 set_ia32_am_support(muls, ia32_am_Source);
2792 GEN_LOWERED_SHIFT_OP(Shl)
2793 GEN_LOWERED_SHIFT_OP(Shr)
2794 GEN_LOWERED_SHIFT_OP(Shrs)
2797 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2798 * op1 - target to be shifted
2799 * op2 - contains bits to be shifted into target
2801 * Only op3 can be an immediate.
2803 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2804 ir_node *new_op = NULL;
2805 ir_mode *mode = env->mode;
2806 dbg_info *dbg = env->dbg;
2807 ir_graph *irg = env->irg;
2808 ir_node *block = env->block;
2809 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2810 ir_node *nomem = new_NoMem();
2813 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2815 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2817 /* Check if immediate optimization is on and */
2818 /* if it's an operation with immediate. */
2819 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2821 /* Limit imm_op within range imm8 */
2823 tv = get_ia32_Immop_tarval(imm_op);
2826 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2827 set_ia32_Immop_tarval(imm_op, tv);
2834 /* integer operations */
2836 /* This is ShiftD with const */
2837 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2839 if (is_ia32_l_ShlD(env->irn))
2840 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2842 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2843 set_ia32_Immop_attr(new_op, imm_op);
2846 /* This is a normal ShiftD */
2847 DB((mod, LEVEL_1, "ShiftD binop ..."));
2848 if (is_ia32_l_ShlD(env->irn))
2849 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2851 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2854 /* set AM support */
2855 set_ia32_am_support(new_op, ia32_am_Dest);
2857 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2859 set_ia32_res_mode(new_op, mode);
2860 set_ia32_emit_cl(new_op);
2862 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2865 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2866 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2869 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2870 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2874 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2876 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2877 ia32_code_gen_t *cg = env->cg;
2878 ir_node *res = NULL;
2879 ir_node *ptr = get_irn_n(env->irn, 0);
2880 ir_node *val = get_irn_n(env->irn, 1);
2881 ir_node *mem = get_irn_n(env->irn, 2);
2884 ir_node *noreg = ia32_new_NoReg_gp(cg);
2886 /* Store x87 -> MEM */
2887 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2888 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2889 set_ia32_use_frame(res);
2890 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2891 set_ia32_am_support(res, ia32_am_Dest);
2892 set_ia32_am_flavour(res, ia32_B);
2893 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2895 /* Load MEM -> SSE */
2896 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2897 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2898 set_ia32_use_frame(res);
2899 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2900 set_ia32_am_support(res, ia32_am_Source);
2901 set_ia32_am_flavour(res, ia32_B);
2902 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2905 /* SSE unit is not used -> skip this node. */
2908 edges_reroute(env->irn, val, env->irg);
2909 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2910 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2917 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2919 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2920 ia32_code_gen_t *cg = env->cg;
2921 ir_node *res = NULL;
2922 ir_node *ptr = get_irn_n(env->irn, 0);
2923 ir_node *val = get_irn_n(env->irn, 1);
2924 ir_node *mem = get_irn_n(env->irn, 2);
2927 ir_node *noreg = ia32_new_NoReg_gp(cg);
2929 /* Store SSE -> MEM */
2930 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2931 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2932 set_ia32_use_frame(res);
2933 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2934 set_ia32_am_support(res, ia32_am_Dest);
2935 set_ia32_am_flavour(res, ia32_B);
2936 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2938 /* Load MEM -> x87 */
2939 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2940 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2941 set_ia32_use_frame(res);
2942 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2943 set_ia32_am_support(res, ia32_am_Source);
2944 set_ia32_am_flavour(res, ia32_B);
2945 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2948 /* SSE unit is not used -> skip this node. */
2951 edges_reroute(env->irn, val, env->irg);
2952 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2953 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2959 /*********************************************************
2962 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2963 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2964 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2965 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2967 *********************************************************/
2970 * the BAD transformer.
2972 static ir_node *bad_transform(ia32_transform_env_t *env) {
2973 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2979 * Enters all transform functions into the generic pointer
2981 void ia32_register_transformers(void) {
2982 ir_op *op_Max, *op_Min, *op_Mulh;
2984 /* first clear the generic function pointer for all ops */
2985 clear_irp_opcodes_generic_func();
2987 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2988 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3022 /* transform ops from intrinsic lowering */
3043 GEN(ia32_l_X87toSSE);
3044 GEN(ia32_l_SSEtoX87);
3059 /* constant transformation happens earlier */
3064 /* we should never see these nodes */
3079 /* handle generic backend nodes */
3089 /* set the register for all Unknown nodes */
3092 op_Max = get_op_Max();
3095 op_Min = get_op_Min();
3098 op_Mulh = get_op_Mulh();
3107 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
3110 * Transforms the given firm node (and maybe some other related nodes)
3111 * into one or more assembler nodes.
3113 * @param node the firm node
3114 * @param env the debug module
3116 void ia32_transform_node(ir_node *node, void *env) {
3117 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
3118 ir_op *op = get_irn_op(node);
3119 ir_node *asm_node = NULL;
3125 /* link arguments pointing to Unknown to the UNKNOWN Proj */
3126 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
3127 if (is_Unknown(get_irn_n(node, i)))
3128 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
3131 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
3132 if (op->ops.generic) {
3133 ia32_transform_env_t tenv;
3134 transform_func *transform = (transform_func *)op->ops.generic;
3136 tenv.block = get_nodes_block(node);
3137 tenv.dbg = get_irn_dbg_info(node);
3138 tenv.irg = current_ir_graph;
3140 tenv.mode = get_irn_mode(node);
3142 DEBUG_ONLY(tenv.mod = cg->mod;)
3144 asm_node = (*transform)(&tenv);
3147 /* exchange nodes if a new one was generated */
3149 exchange(node, asm_node);
3150 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
3153 DB((cg->mod, LEVEL_1, "ignored\n"));
3158 * Transforms a psi condition.
3160 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
3163 /* if the mode is target mode, we have already seen this part of the tree */
3164 if (get_irn_mode(cond) == mode)
3167 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
3169 set_irn_mode(cond, mode);
3171 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
3172 ir_node *in = get_irn_n(cond, i);
3174 /* if in is a compare: transform into Set/xCmp */
3176 ir_node *new_op = NULL;
3177 ir_node *cmp = get_Proj_pred(in);
3178 ir_node *cmp_a = get_Cmp_left(cmp);
3179 ir_node *cmp_b = get_Cmp_right(cmp);
3180 dbg_info *dbg = get_irn_dbg_info(cmp);
3181 ir_graph *irg = get_irn_irg(cmp);
3182 ir_node *block = get_nodes_block(cmp);
3183 ir_node *noreg = ia32_new_NoReg_gp(cg);
3184 ir_node *nomem = new_rd_NoMem(irg);
3185 int pnc = get_Proj_proj(in);
3187 /* this is a compare */
3188 if (mode_is_float(mode)) {
3189 /* Psi is float, we need a floating point compare */
3192 ir_mode *m = get_irn_mode(cmp_a);
3194 if (! mode_is_float(m)) {
3195 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
3196 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
3198 else if (m == mode_F) {
3199 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
3200 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
3201 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
3204 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
3205 set_ia32_pncode(new_op, pnc);
3206 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
3215 ia32_transform_env_t tenv;
3216 construct_binop_func *set_func = NULL;
3218 if (mode_is_float(get_irn_mode(cmp_a))) {
3219 /* 1st case: compare operands are floats */
3224 set_func = new_rd_ia32_xCmpSet;
3228 set_func = new_rd_ia32_vfCmpSet;
3231 pnc &= 7; /* fp compare -> int compare */
3234 /* 2nd case: compare operand are integer too */
3235 set_func = new_rd_ia32_CmpSet;
3246 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
3247 set_ia32_pncode(get_Proj_pred(new_op), pnc);
3248 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
3251 /* the the new compare as in */
3252 set_irn_n(cond, i, new_op);
3255 /* another complex condition */
3256 transform_psi_cond(in, mode, cg);
3262 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
3263 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
3264 * compare, which causes the compare result to be stores in a register. The
3265 * "And"s and "Or"s are transformed later, we just have to set their mode right.
3267 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
3268 ia32_code_gen_t *cg = env;
3269 ir_node *psi_sel, *new_cmp, *block;
3274 if (get_irn_opcode(node) != iro_Psi)
3277 psi_sel = get_Psi_cond(node, 0);
3279 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
3280 if (is_Proj(psi_sel))
3283 //mode = get_irn_mode(node);
3286 transform_psi_cond(psi_sel, mode, cg);
3288 irg = get_irn_irg(node);
3289 block = get_nodes_block(node);
3291 /* we need to compare the evaluated condition tree with 0 */
3292 mode = get_irn_mode(node);
3293 if (mode_is_float(mode)) {
3294 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
3295 /* BEWARE: new_r_Const_long works for floating point as well */
3296 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
3297 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
3300 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
3301 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
3304 set_Psi_cond(node, 0, new_cmp);