2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
91 extern ir_op *get_op_Mulh(void);
93 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
94 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
95 ir_node *op2, ir_node *mem);
97 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
98 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
99 ir_node *op2, ir_node *mem, ir_node *fpcw);
101 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
105 /****************************************************************************************************
107 * | | | | / _| | | (_)
108 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
109 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
110 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
111 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
113 ****************************************************************************************************/
115 static ir_node *try_create_Immediate(ir_node *node,
116 char immediate_constraint_type);
118 static ir_node *create_immediate_or_transform(ir_node *node,
119 char immediate_constraint_type);
122 * Return true if a mode can be stored in the GP register set
124 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
125 if(mode == mode_fpcw)
127 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
131 * Returns 1 if irn is a Const representing 0, 0 otherwise
133 static INLINE int is_ia32_Const_0(ir_node *irn) {
134 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
135 && tarval_is_null(get_ia32_Immop_tarval(irn));
139 * Returns 1 if irn is a Const representing 1, 0 otherwise
141 static INLINE int is_ia32_Const_1(ir_node *irn) {
142 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
143 && tarval_is_one(get_ia32_Immop_tarval(irn));
147 * Collects all Projs of a node into the node array. Index is the projnum.
148 * BEWARE: The caller has to assure the appropriate array size!
150 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
151 const ir_edge_t *edge;
152 assert(get_irn_mode(irn) == mode_T && "need mode_T");
154 memset(projs, 0, size * sizeof(projs[0]));
156 foreach_out_edge(irn, edge) {
157 ir_node *proj = get_edge_src_irn(edge);
158 int proj_proj = get_Proj_proj(proj);
159 assert(proj_proj < size);
160 projs[proj_proj] = proj;
165 * Renumbers the proj having pn_old in the array tp pn_new
166 * and removes the proj from the array.
168 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
169 fprintf(stderr, "Warning: renumber_Proj used!\n");
171 set_Proj_proj(projs[pn_old], pn_new);
172 projs[pn_old] = NULL;
177 * creates a unique ident by adding a number to a tag
179 * @param tag the tag string, must contain a %d if a number
182 static ident *unique_id(const char *tag)
184 static unsigned id = 0;
187 snprintf(str, sizeof(str), tag, ++id);
188 return new_id_from_str(str);
192 * Get a primitive type for a mode.
194 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
196 pmap_entry *e = pmap_find(types, mode);
201 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
202 res = new_type_primitive(new_id_from_str(buf), mode);
203 set_type_alignment_bytes(res, 16);
204 pmap_insert(types, mode, res);
212 * Get an entity that is initialized with a tarval
214 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
216 tarval *tv = get_Const_tarval(cnst);
217 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
222 ir_mode *mode = get_irn_mode(cnst);
223 ir_type *tp = get_Const_type(cnst);
224 if (tp == firm_unknown_type)
225 tp = get_prim_type(cg->isa->types, mode);
227 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
229 set_entity_ld_ident(res, get_entity_ident(res));
230 set_entity_visibility(res, visibility_local);
231 set_entity_variability(res, variability_constant);
232 set_entity_allocation(res, allocation_static);
234 /* we create a new entity here: It's initialization must resist on the
236 rem = current_ir_graph;
237 current_ir_graph = get_const_code_irg();
238 set_atomic_ent_value(res, new_Const_type(tv, tp));
239 current_ir_graph = rem;
241 pmap_insert(cg->isa->tv_ent, tv, res);
249 static int is_Const_0(ir_node *node) {
253 return classify_Const(node) == CNST_NULL;
256 static int is_Const_1(ir_node *node) {
260 return classify_Const(node) == CNST_ONE;
264 * Transforms a Const.
266 static ir_node *gen_Const(ir_node *node) {
267 ir_graph *irg = current_ir_graph;
268 ir_node *block = be_transform_node(get_nodes_block(node));
269 dbg_info *dbgi = get_irn_dbg_info(node);
270 ir_mode *mode = get_irn_mode(node);
272 if (mode_is_float(mode)) {
274 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
275 ir_node *nomem = new_NoMem();
279 if (! USE_SSE2(env_cg)) {
280 cnst_classify_t clss = classify_Const(node);
282 if (clss == CNST_NULL) {
283 load = new_rd_ia32_vfldz(dbgi, irg, block);
285 } else if (clss == CNST_ONE) {
286 load = new_rd_ia32_vfld1(dbgi, irg, block);
289 floatent = get_entity_for_tv(env_cg, node);
291 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
292 set_ia32_op_type(load, ia32_AddrModeS);
293 set_ia32_am_flavour(load, ia32_am_N);
294 set_ia32_am_sc(load, floatent);
295 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
296 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
298 set_ia32_ls_mode(load, mode);
300 floatent = get_entity_for_tv(env_cg, node);
302 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
303 set_ia32_op_type(load, ia32_AddrModeS);
304 set_ia32_am_flavour(load, ia32_am_N);
305 set_ia32_am_sc(load, floatent);
306 set_ia32_ls_mode(load, mode);
307 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
309 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
312 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
314 /* Const Nodes before the initial IncSP are a bad idea, because
315 * they could be spilled and we have no SP ready at that point yet.
316 * So add a dependency to the initial frame pointer calculation to
317 * avoid that situation.
319 if (get_irg_start_block(irg) == block) {
320 add_irn_dep(load, get_irg_frame(irg));
323 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
326 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
329 if (get_irg_start_block(irg) == block) {
330 add_irn_dep(cnst, get_irg_frame(irg));
333 set_ia32_Const_attr(cnst, node);
334 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 return new_r_Bad(irg);
343 * Transforms a SymConst.
345 static ir_node *gen_SymConst(ir_node *node) {
346 ir_graph *irg = current_ir_graph;
347 ir_node *block = be_transform_node(get_nodes_block(node));
348 dbg_info *dbgi = get_irn_dbg_info(node);
349 ir_mode *mode = get_irn_mode(node);
352 if (mode_is_float(mode)) {
353 if (USE_SSE2(env_cg))
354 cnst = new_rd_ia32_xConst(dbgi, irg, block);
356 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
357 //set_ia32_ls_mode(cnst, mode);
358 set_ia32_ls_mode(cnst, mode_E);
360 cnst = new_rd_ia32_Const(dbgi, irg, block);
363 /* Const Nodes before the initial IncSP are a bad idea, because
364 * they could be spilled and we have no SP ready at that point yet
366 if (get_irg_start_block(irg) == block) {
367 add_irn_dep(cnst, get_irg_frame(irg));
370 set_ia32_Const_attr(cnst, node);
371 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
376 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
377 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
378 static const struct {
380 const char *ent_name;
381 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
388 static ir_entity *ent_cache[ia32_known_const_max];
390 const char *tp_name, *ent_name, *cnst_str;
398 ent_name = names[kct].ent_name;
399 if (! ent_cache[kct]) {
400 tp_name = names[kct].tp_name;
401 cnst_str = names[kct].cnst_str;
403 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
405 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
406 tp = new_type_primitive(new_id_from_str(tp_name), mode);
407 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
409 set_entity_ld_ident(ent, get_entity_ident(ent));
410 set_entity_visibility(ent, visibility_local);
411 set_entity_variability(ent, variability_constant);
412 set_entity_allocation(ent, allocation_static);
414 /* we create a new entity here: It's initialization must resist on the
416 rem = current_ir_graph;
417 current_ir_graph = get_const_code_irg();
418 cnst = new_Const(mode, tv);
419 current_ir_graph = rem;
421 set_atomic_ent_value(ent, cnst);
423 /* cache the entry */
424 ent_cache[kct] = ent;
427 return ent_cache[kct];
432 * Prints the old node name on cg obst and returns a pointer to it.
434 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
435 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
437 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
438 obstack_1grow(isa->name_obst, 0);
439 return obstack_finish(isa->name_obst);
443 /* determine if one operator is an Imm */
444 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
446 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
448 return is_ia32_Cnst(op2) ? op2 : NULL;
452 /* determine if one operator is not an Imm */
453 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
454 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
457 static void fold_immediate(ir_node *node, int in1, int in2) {
461 if (!(env_cg->opt & IA32_OPT_IMMOPS))
464 left = get_irn_n(node, in1);
465 right = get_irn_n(node, in2);
466 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
467 /* we can only set right operand to immediate */
468 if(!is_ia32_commutative(node))
470 /* exchange left/right */
471 set_irn_n(node, in1, right);
472 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
473 copy_ia32_Immop_attr(node, left);
474 } else if(is_ia32_Cnst(right)) {
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, right);
481 clear_ia32_commutative(node);
482 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
483 get_ia32_am_arity(node));
487 * Construct a standard binary operation, set AM and immediate if required.
489 * @param op1 The first operand
490 * @param op2 The second operand
491 * @param func The node constructor function
492 * @return The constructed ia32 node.
494 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
495 construct_binop_func *func, int commutative)
497 ir_node *block = be_transform_node(get_nodes_block(node));
498 ir_graph *irg = current_ir_graph;
499 dbg_info *dbgi = get_irn_dbg_info(node);
500 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
501 ir_node *nomem = new_NoMem();
504 ir_node *new_op1 = be_transform_node(op1);
505 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
506 if (is_ia32_Immediate(new_op2)) {
510 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
511 if (func == new_rd_ia32_IMul) {
512 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
514 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
517 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
519 set_ia32_commutative(new_node);
526 * Construct a standard binary operation, set AM and immediate if required.
528 * @param op1 The first operand
529 * @param op2 The second operand
530 * @param func The node constructor function
531 * @return The constructed ia32 node.
533 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
534 construct_binop_func *func)
536 ir_node *block = be_transform_node(get_nodes_block(node));
537 ir_node *new_op1 = be_transform_node(op1);
538 ir_node *new_op2 = be_transform_node(op2);
539 ir_node *new_node = NULL;
540 dbg_info *dbgi = get_irn_dbg_info(node);
541 ir_graph *irg = current_ir_graph;
542 ir_mode *mode = get_irn_mode(node);
543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
544 ir_node *nomem = new_NoMem();
546 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
548 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
549 if (is_op_commutative(get_irn_op(node))) {
550 set_ia32_commutative(new_node);
552 set_ia32_ls_mode(new_node, mode);
554 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
560 * Construct a standard binary operation, set AM and immediate if required.
562 * @param op1 The first operand
563 * @param op2 The second operand
564 * @param func The node constructor function
565 * @return The constructed ia32 node.
567 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
568 construct_binop_float_func *func)
570 ir_node *block = be_transform_node(get_nodes_block(node));
571 ir_node *new_op1 = be_transform_node(op1);
572 ir_node *new_op2 = be_transform_node(op2);
573 ir_node *new_node = NULL;
574 dbg_info *dbgi = get_irn_dbg_info(node);
575 ir_graph *irg = current_ir_graph;
576 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
577 ir_node *nomem = new_NoMem();
578 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
579 &ia32_fp_cw_regs[REG_FPCW]);
581 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
583 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
584 if (is_op_commutative(get_irn_op(node))) {
585 set_ia32_commutative(new_node);
588 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
594 * Construct a shift/rotate binary operation, sets AM and immediate if required.
596 * @param op1 The first operand
597 * @param op2 The second operand
598 * @param func The node constructor function
599 * @return The constructed ia32 node.
601 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
602 construct_binop_func *func)
604 ir_node *block = be_transform_node(get_nodes_block(node));
605 ir_node *new_op1 = be_transform_node(op1);
607 ir_node *new_op = NULL;
608 dbg_info *dbgi = get_irn_dbg_info(node);
609 ir_graph *irg = current_ir_graph;
610 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
611 ir_node *nomem = new_NoMem();
613 assert(! mode_is_float(get_irn_mode(node))
614 && "Shift/Rotate with float not supported");
616 new_op2 = create_immediate_or_transform(op2, 'N');
618 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
621 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
623 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
625 set_ia32_emit_cl(new_op);
632 * Construct a standard unary operation, set AM and immediate if required.
634 * @param op The operand
635 * @param func The node constructor function
636 * @return The constructed ia32 node.
638 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
640 ir_node *block = be_transform_node(get_nodes_block(node));
641 ir_node *new_op = be_transform_node(op);
642 ir_node *new_node = NULL;
643 ir_graph *irg = current_ir_graph;
644 dbg_info *dbgi = get_irn_dbg_info(node);
645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
646 ir_node *nomem = new_NoMem();
648 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
649 DB((dbg, LEVEL_1, "INT unop ..."));
650 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
652 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
658 * Creates an ia32 Add.
660 * @return the created ia32 Add node
662 static ir_node *gen_Add(ir_node *node) {
663 ir_node *block = be_transform_node(get_nodes_block(node));
664 ir_node *op1 = get_Add_left(node);
665 ir_node *new_op1 = be_transform_node(op1);
666 ir_node *op2 = get_Add_right(node);
667 ir_node *new_op2 = be_transform_node(op2);
668 ir_node *new_op = NULL;
669 ir_graph *irg = current_ir_graph;
670 dbg_info *dbgi = get_irn_dbg_info(node);
671 ir_mode *mode = get_irn_mode(node);
672 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
673 ir_node *nomem = new_NoMem();
674 ir_node *expr_op, *imm_op;
676 /* Check if immediate optimization is on and */
677 /* if it's an operation with immediate. */
678 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
679 expr_op = get_expr_op(new_op1, new_op2);
681 assert((expr_op || imm_op) && "invalid operands");
683 if (mode_is_float(mode)) {
684 if (USE_SSE2(env_cg))
685 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
687 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
692 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
693 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
695 /* No expr_op means, that we have two const - one symconst and */
696 /* one tarval or another symconst - because this case is not */
697 /* covered by constant folding */
698 /* We need to check for: */
699 /* 1) symconst + const -> becomes a LEA */
700 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
701 /* linker doesn't support two symconsts */
703 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
704 /* this is the 2nd case */
705 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
706 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
707 set_ia32_am_flavour(new_op, ia32_am_B);
708 set_ia32_op_type(new_op, ia32_AddrModeS);
710 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
711 } else if (tp1 == ia32_ImmSymConst) {
712 tarval *tv = get_ia32_Immop_tarval(new_op2);
713 long offs = get_tarval_long(tv);
715 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
716 add_irn_dep(new_op, get_irg_frame(irg));
717 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
719 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
720 add_ia32_am_offs_int(new_op, offs);
721 set_ia32_am_flavour(new_op, ia32_am_OB);
722 set_ia32_op_type(new_op, ia32_AddrModeS);
723 } else if (tp2 == ia32_ImmSymConst) {
724 tarval *tv = get_ia32_Immop_tarval(new_op1);
725 long offs = get_tarval_long(tv);
727 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
728 add_irn_dep(new_op, get_irg_frame(irg));
729 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
731 add_ia32_am_offs_int(new_op, offs);
732 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
733 set_ia32_am_flavour(new_op, ia32_am_OB);
734 set_ia32_op_type(new_op, ia32_AddrModeS);
736 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
737 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
738 tarval *restv = tarval_add(tv1, tv2);
740 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
742 new_op = new_rd_ia32_Const(dbgi, irg, block);
743 set_ia32_Const_tarval(new_op, restv);
744 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
747 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
750 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
751 tarval_classification_t class_tv, class_negtv;
752 tarval *tv = get_ia32_Immop_tarval(imm_op);
754 /* optimize tarvals */
755 class_tv = classify_tarval(tv);
756 class_negtv = classify_tarval(tarval_neg(tv));
758 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
759 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
760 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
761 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
763 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
764 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
765 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
766 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
772 /* This is a normal add */
773 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
776 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
777 set_ia32_commutative(new_op);
779 fold_immediate(new_op, 2, 3);
781 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
787 * Creates an ia32 Mul.
789 * @return the created ia32 Mul node
791 static ir_node *gen_Mul(ir_node *node) {
792 ir_node *op1 = get_Mul_left(node);
793 ir_node *op2 = get_Mul_right(node);
794 ir_mode *mode = get_irn_mode(node);
796 if (mode_is_float(mode)) {
797 if (USE_SSE2(env_cg))
798 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
800 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
804 for the lower 32bit of the result it doesn't matter whether we use
805 signed or unsigned multiplication so we use IMul as it has fewer
808 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
812 * Creates an ia32 Mulh.
813 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
814 * this result while Mul returns the lower 32 bit.
816 * @return the created ia32 Mulh node
818 static ir_node *gen_Mulh(ir_node *node) {
819 ir_node *block = be_transform_node(get_nodes_block(node));
820 ir_node *op1 = get_irn_n(node, 0);
821 ir_node *new_op1 = be_transform_node(op1);
822 ir_node *op2 = get_irn_n(node, 1);
823 ir_node *new_op2 = be_transform_node(op2);
824 ir_graph *irg = current_ir_graph;
825 dbg_info *dbgi = get_irn_dbg_info(node);
826 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
827 ir_mode *mode = get_irn_mode(node);
828 ir_node *proj_EDX, *res;
830 assert(!mode_is_float(mode) && "Mulh with float not supported");
831 if (mode_is_signed(mode)) {
832 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
833 new_op2, new_NoMem());
835 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
839 set_ia32_commutative(res);
840 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
842 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
850 * Creates an ia32 And.
852 * @return The created ia32 And node
854 static ir_node *gen_And(ir_node *node) {
855 ir_node *op1 = get_And_left(node);
856 ir_node *op2 = get_And_right(node);
858 assert (! mode_is_float(get_irn_mode(node)));
859 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
865 * Creates an ia32 Or.
867 * @return The created ia32 Or node
869 static ir_node *gen_Or(ir_node *node) {
870 ir_node *op1 = get_Or_left(node);
871 ir_node *op2 = get_Or_right(node);
873 assert (! mode_is_float(get_irn_mode(node)));
874 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
880 * Creates an ia32 Eor.
882 * @return The created ia32 Eor node
884 static ir_node *gen_Eor(ir_node *node) {
885 ir_node *op1 = get_Eor_left(node);
886 ir_node *op2 = get_Eor_right(node);
888 assert(! mode_is_float(get_irn_mode(node)));
889 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
894 * Creates an ia32 Sub.
896 * @return The created ia32 Sub node
898 static ir_node *gen_Sub(ir_node *node) {
899 ir_node *block = be_transform_node(get_nodes_block(node));
900 ir_node *op1 = get_Sub_left(node);
901 ir_node *new_op1 = be_transform_node(op1);
902 ir_node *op2 = get_Sub_right(node);
903 ir_node *new_op2 = be_transform_node(op2);
904 ir_node *new_op = NULL;
905 ir_graph *irg = current_ir_graph;
906 dbg_info *dbgi = get_irn_dbg_info(node);
907 ir_mode *mode = get_irn_mode(node);
908 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
909 ir_node *nomem = new_NoMem();
910 ir_node *expr_op, *imm_op;
912 /* Check if immediate optimization is on and */
913 /* if it's an operation with immediate. */
914 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
915 expr_op = get_expr_op(new_op1, new_op2);
917 assert((expr_op || imm_op) && "invalid operands");
919 if (mode_is_float(mode)) {
920 if (USE_SSE2(env_cg))
921 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
923 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
928 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
929 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
931 /* No expr_op means, that we have two const - one symconst and */
932 /* one tarval or another symconst - because this case is not */
933 /* covered by constant folding */
934 /* We need to check for: */
935 /* 1) symconst - const -> becomes a LEA */
936 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
937 /* linker doesn't support two symconsts */
938 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
939 /* this is the 2nd case */
940 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
941 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
942 set_ia32_am_sc_sign(new_op);
943 set_ia32_am_flavour(new_op, ia32_am_B);
945 DBG_OPT_LEA3(op1, op2, node, new_op);
946 } else if (tp1 == ia32_ImmSymConst) {
947 tarval *tv = get_ia32_Immop_tarval(new_op2);
948 long offs = get_tarval_long(tv);
950 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
951 add_irn_dep(new_op, get_irg_frame(irg));
952 DBG_OPT_LEA3(op1, op2, node, new_op);
954 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
955 add_ia32_am_offs_int(new_op, -offs);
956 set_ia32_am_flavour(new_op, ia32_am_OB);
957 set_ia32_op_type(new_op, ia32_AddrModeS);
958 } else if (tp2 == ia32_ImmSymConst) {
959 tarval *tv = get_ia32_Immop_tarval(new_op1);
960 long offs = get_tarval_long(tv);
962 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
963 add_irn_dep(new_op, get_irg_frame(irg));
964 DBG_OPT_LEA3(op1, op2, node, new_op);
966 add_ia32_am_offs_int(new_op, offs);
967 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
968 set_ia32_am_sc_sign(new_op);
969 set_ia32_am_flavour(new_op, ia32_am_OB);
970 set_ia32_op_type(new_op, ia32_AddrModeS);
972 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
973 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
974 tarval *restv = tarval_sub(tv1, tv2);
976 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
978 new_op = new_rd_ia32_Const(dbgi, irg, block);
979 set_ia32_Const_tarval(new_op, restv);
980 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
983 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
986 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
987 tarval_classification_t class_tv, class_negtv;
988 tarval *tv = get_ia32_Immop_tarval(imm_op);
990 /* optimize tarvals */
991 class_tv = classify_tarval(tv);
992 class_negtv = classify_tarval(tarval_neg(tv));
994 if (class_tv == TV_CLASSIFY_ONE) {
995 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
996 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
999 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1000 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1001 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1002 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1008 /* This is a normal sub */
1009 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1011 /* set AM support */
1012 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1014 fold_immediate(new_op, 2, 3);
1016 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1024 * Generates an ia32 DivMod with additional infrastructure for the
1025 * register allocator if needed.
1027 * @param dividend -no comment- :)
1028 * @param divisor -no comment- :)
1029 * @param dm_flav flavour_Div/Mod/DivMod
1030 * @return The created ia32 DivMod node
1032 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1033 ir_node *divisor, ia32_op_flavour_t dm_flav)
1035 ir_node *block = be_transform_node(get_nodes_block(node));
1036 ir_node *new_dividend = be_transform_node(dividend);
1037 ir_node *new_divisor = be_transform_node(divisor);
1038 ir_graph *irg = current_ir_graph;
1039 dbg_info *dbgi = get_irn_dbg_info(node);
1040 ir_mode *mode = get_irn_mode(node);
1041 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1042 ir_node *res, *proj_div, *proj_mod;
1043 ir_node *sign_extension;
1044 ir_node *mem, *new_mem;
1045 ir_node *projs[pn_DivMod_max];
1048 ia32_collect_Projs(node, projs, pn_DivMod_max);
1050 proj_div = proj_mod = NULL;
1054 mem = get_Div_mem(node);
1055 mode = get_Div_resmode(node);
1056 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1057 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1060 mem = get_Mod_mem(node);
1061 mode = get_Mod_resmode(node);
1062 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1063 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1065 case flavour_DivMod:
1066 mem = get_DivMod_mem(node);
1067 mode = get_DivMod_resmode(node);
1068 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1069 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1070 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1073 panic("invalid divmod flavour!");
1075 new_mem = be_transform_node(mem);
1077 if (mode_is_signed(mode)) {
1078 /* in signed mode, we need to sign extend the dividend */
1079 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1081 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1082 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1084 add_irn_dep(sign_extension, get_irg_frame(irg));
1087 if (mode_is_signed(mode)) {
1088 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1089 sign_extension, new_divisor, new_mem, dm_flav);
1091 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1092 sign_extension, new_divisor, new_mem, dm_flav);
1095 set_ia32_exc_label(res, has_exc);
1096 set_irn_pinned(res, get_irn_pinned(node));
1097 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1099 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1106 * Wrapper for generate_DivMod. Sets flavour_Mod.
1109 static ir_node *gen_Mod(ir_node *node) {
1110 return generate_DivMod(node, get_Mod_left(node),
1111 get_Mod_right(node), flavour_Mod);
1115 * Wrapper for generate_DivMod. Sets flavour_Div.
1118 static ir_node *gen_Div(ir_node *node) {
1119 return generate_DivMod(node, get_Div_left(node),
1120 get_Div_right(node), flavour_Div);
1124 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1126 static ir_node *gen_DivMod(ir_node *node) {
1127 return generate_DivMod(node, get_DivMod_left(node),
1128 get_DivMod_right(node), flavour_DivMod);
1134 * Creates an ia32 floating Div.
1136 * @return The created ia32 xDiv node
1138 static ir_node *gen_Quot(ir_node *node) {
1139 ir_node *block = be_transform_node(get_nodes_block(node));
1140 ir_node *op1 = get_Quot_left(node);
1141 ir_node *new_op1 = be_transform_node(op1);
1142 ir_node *op2 = get_Quot_right(node);
1143 ir_node *new_op2 = be_transform_node(op2);
1144 ir_graph *irg = current_ir_graph;
1145 dbg_info *dbgi = get_irn_dbg_info(node);
1146 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1147 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1150 if (USE_SSE2(env_cg)) {
1151 ir_mode *mode = get_irn_mode(op1);
1152 if (is_ia32_xConst(new_op2)) {
1153 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1154 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1155 copy_ia32_Immop_attr(new_op, new_op2);
1157 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1158 // Matze: disabled for now, spillslot coalescer fails
1159 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1161 set_ia32_ls_mode(new_op, mode);
1163 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1164 &ia32_fp_cw_regs[REG_FPCW]);
1165 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1166 new_op2, nomem, fpcw);
1167 // Matze: disabled for now (spillslot coalescer fails)
1168 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1170 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1176 * Creates an ia32 Shl.
1178 * @return The created ia32 Shl node
1180 static ir_node *gen_Shl(ir_node *node) {
1181 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1188 * Creates an ia32 Shr.
1190 * @return The created ia32 Shr node
1192 static ir_node *gen_Shr(ir_node *node) {
1193 return gen_shift_binop(node, get_Shr_left(node),
1194 get_Shr_right(node), new_rd_ia32_Shr);
1200 * Creates an ia32 Sar.
1202 * @return The created ia32 Shrs node
1204 static ir_node *gen_Shrs(ir_node *node) {
1205 ir_node *left = get_Shrs_left(node);
1206 ir_node *right = get_Shrs_right(node);
1207 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1208 tarval *tv = get_Const_tarval(right);
1209 long val = get_tarval_long(tv);
1211 /* this is a sign extension */
1212 ir_graph *irg = current_ir_graph;
1213 dbg_info *dbgi = get_irn_dbg_info(node);
1214 ir_node *block = be_transform_node(get_nodes_block(node));
1216 ir_node *new_op = be_transform_node(op);
1218 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1222 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1228 * Creates an ia32 RotL.
1230 * @param op1 The first operator
1231 * @param op2 The second operator
1232 * @return The created ia32 RotL node
1234 static ir_node *gen_RotL(ir_node *node,
1235 ir_node *op1, ir_node *op2) {
1236 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1242 * Creates an ia32 RotR.
1243 * NOTE: There is no RotR with immediate because this would always be a RotL
1244 * "imm-mode_size_bits" which can be pre-calculated.
1246 * @param op1 The first operator
1247 * @param op2 The second operator
1248 * @return The created ia32 RotR node
1250 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1252 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1258 * Creates an ia32 RotR or RotL (depending on the found pattern).
1260 * @return The created ia32 RotL or RotR node
1262 static ir_node *gen_Rot(ir_node *node) {
1263 ir_node *rotate = NULL;
1264 ir_node *op1 = get_Rot_left(node);
1265 ir_node *op2 = get_Rot_right(node);
1267 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1268 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1269 that means we can create a RotR instead of an Add and a RotL */
1271 if (get_irn_op(op2) == op_Add) {
1273 ir_node *left = get_Add_left(add);
1274 ir_node *right = get_Add_right(add);
1275 if (is_Const(right)) {
1276 tarval *tv = get_Const_tarval(right);
1277 ir_mode *mode = get_irn_mode(node);
1278 long bits = get_mode_size_bits(mode);
1280 if (get_irn_op(left) == op_Minus &&
1281 tarval_is_long(tv) &&
1282 get_tarval_long(tv) == bits)
1284 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1285 rotate = gen_RotR(node, op1, get_Minus_op(left));
1290 if (rotate == NULL) {
1291 rotate = gen_RotL(node, op1, op2);
1300 * Transforms a Minus node.
1302 * @param op The Minus operand
1303 * @return The created ia32 Minus node
1305 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1306 ir_node *block = be_transform_node(get_nodes_block(node));
1307 ir_graph *irg = current_ir_graph;
1308 dbg_info *dbgi = get_irn_dbg_info(node);
1309 ir_mode *mode = get_irn_mode(node);
1314 if (mode_is_float(mode)) {
1315 ir_node *new_op = be_transform_node(op);
1316 if (USE_SSE2(env_cg)) {
1317 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1318 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1319 ir_node *nomem = new_rd_NoMem(irg);
1321 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1323 size = get_mode_size_bits(mode);
1324 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1326 set_ia32_am_sc(res, ent);
1327 set_ia32_op_type(res, ia32_AddrModeS);
1328 set_ia32_ls_mode(res, mode);
1330 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1333 res = gen_unop(node, op, new_rd_ia32_Neg);
1336 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1342 * Transforms a Minus node.
1344 * @return The created ia32 Minus node
1346 static ir_node *gen_Minus(ir_node *node) {
1347 return gen_Minus_ex(node, get_Minus_op(node));
1350 static ir_node *gen_bin_Not(ir_node *node)
1352 ir_graph *irg = current_ir_graph;
1353 dbg_info *dbgi = get_irn_dbg_info(node);
1354 ir_node *block = be_transform_node(get_nodes_block(node));
1355 ir_node *op = get_Not_op(node);
1356 ir_node *new_op = be_transform_node(op);
1357 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1358 ir_node *nomem = new_NoMem();
1359 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1360 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1362 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1366 * Transforms a Not node.
1368 * @return The created ia32 Not node
1370 static ir_node *gen_Not(ir_node *node) {
1371 ir_node *op = get_Not_op(node);
1372 ir_mode *mode = get_irn_mode(node);
1374 if(mode == mode_b) {
1375 return gen_bin_Not(node);
1378 assert (! mode_is_float(get_irn_mode(node)));
1379 return gen_unop(node, op, new_rd_ia32_Not);
1385 * Transforms an Abs node.
1387 * @return The created ia32 Abs node
1389 static ir_node *gen_Abs(ir_node *node) {
1390 ir_node *block = be_transform_node(get_nodes_block(node));
1391 ir_node *op = get_Abs_op(node);
1392 ir_node *new_op = be_transform_node(op);
1393 ir_graph *irg = current_ir_graph;
1394 dbg_info *dbgi = get_irn_dbg_info(node);
1395 ir_mode *mode = get_irn_mode(node);
1396 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1397 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1398 ir_node *nomem = new_NoMem();
1403 if (mode_is_float(mode)) {
1404 if (USE_SSE2(env_cg)) {
1405 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1407 size = get_mode_size_bits(mode);
1408 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1410 set_ia32_am_sc(res, ent);
1412 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1414 set_ia32_op_type(res, ia32_AddrModeS);
1415 set_ia32_ls_mode(res, mode);
1418 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1419 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1423 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1424 SET_IA32_ORIG_NODE(sign_extension,
1425 ia32_get_old_node_name(env_cg, node));
1427 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1428 sign_extension, nomem);
1429 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1431 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1432 sign_extension, nomem);
1433 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1442 * Transforms a Load.
1444 * @return the created ia32 Load node
1446 static ir_node *gen_Load(ir_node *node) {
1447 ir_node *block = be_transform_node(get_nodes_block(node));
1448 ir_node *ptr = get_Load_ptr(node);
1449 ir_node *new_ptr = be_transform_node(ptr);
1450 ir_node *mem = get_Load_mem(node);
1451 ir_node *new_mem = be_transform_node(mem);
1452 ir_graph *irg = current_ir_graph;
1453 dbg_info *dbgi = get_irn_dbg_info(node);
1454 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1455 ir_mode *mode = get_Load_mode(node);
1457 ir_node *lptr = new_ptr;
1460 ia32_am_flavour_t am_flav = ia32_am_B;
1462 /* address might be a constant (symconst or absolute address) */
1463 if (is_ia32_Const(new_ptr)) {
1468 if (mode_is_float(mode)) {
1469 if (USE_SSE2(env_cg)) {
1470 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1471 res_mode = mode_xmm;
1473 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1474 res_mode = mode_vfp;
1477 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1481 /* base is a constant address */
1483 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1484 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1485 am_flav = ia32_am_N;
1487 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1488 long offs = get_tarval_long(tv);
1490 add_ia32_am_offs_int(new_op, offs);
1491 am_flav = ia32_am_O;
1495 set_irn_pinned(new_op, get_irn_pinned(node));
1496 set_ia32_op_type(new_op, ia32_AddrModeS);
1497 set_ia32_am_flavour(new_op, am_flav);
1498 set_ia32_ls_mode(new_op, mode);
1500 /* make sure we are scheduled behind the initial IncSP/Barrier
1501 * to avoid spills being placed before it
1503 if (block == get_irg_start_block(irg)) {
1504 add_irn_dep(new_op, get_irg_frame(irg));
1507 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1508 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1516 * Transforms a Store.
1518 * @return the created ia32 Store node
1520 static ir_node *gen_Store(ir_node *node) {
1521 ir_node *block = be_transform_node(get_nodes_block(node));
1522 ir_node *ptr = get_Store_ptr(node);
1523 ir_node *new_ptr = be_transform_node(ptr);
1524 ir_node *val = get_Store_value(node);
1526 ir_node *mem = get_Store_mem(node);
1527 ir_node *new_mem = be_transform_node(mem);
1528 ir_graph *irg = current_ir_graph;
1529 dbg_info *dbgi = get_irn_dbg_info(node);
1530 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1531 ir_node *sptr = new_ptr;
1532 ir_mode *mode = get_irn_mode(val);
1535 ia32_am_flavour_t am_flav = ia32_am_B;
1537 /* address might be a constant (symconst or absolute address) */
1538 if (is_ia32_Const(new_ptr)) {
1543 if (mode_is_float(mode)) {
1544 new_val = be_transform_node(val);
1545 if (USE_SSE2(env_cg)) {
1546 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1549 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1553 new_val = create_immediate_or_transform(val, 0);
1555 if (get_mode_size_bits(mode) == 8) {
1556 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1559 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1564 /* base is an constant address */
1566 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1567 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1568 am_flav = ia32_am_N;
1570 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1571 long offs = get_tarval_long(tv);
1573 add_ia32_am_offs_int(new_op, offs);
1574 am_flav = ia32_am_O;
1578 set_irn_pinned(new_op, get_irn_pinned(node));
1579 set_ia32_op_type(new_op, ia32_AddrModeD);
1580 set_ia32_am_flavour(new_op, am_flav);
1581 set_ia32_ls_mode(new_op, mode);
1583 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1584 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1589 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1590 ir_node *cmp_left, ir_node *cmp_right)
1592 ir_node *new_cmp_left;
1593 ir_node *new_cmp_right;
1599 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1601 if(cmp_right != NULL && !is_Const_0(cmp_right))
1604 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1605 and_left = get_And_left(cmp_left);
1606 and_right = get_And_right(cmp_left);
1608 new_cmp_left = be_transform_node(and_left);
1609 new_cmp_right = create_immediate_or_transform(and_right, 0);
1611 new_cmp_left = be_transform_node(cmp_left);
1612 new_cmp_right = be_transform_node(cmp_left);
1615 noreg = ia32_new_NoReg_gp(env_cg);
1616 nomem = new_NoMem();
1618 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1619 new_cmp_left, new_cmp_right, nomem, pnc);
1620 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1625 static ir_node *create_Switch(ir_node *node)
1627 ir_graph *irg = current_ir_graph;
1628 dbg_info *dbgi = get_irn_dbg_info(node);
1629 ir_node *block = be_transform_node(get_nodes_block(node));
1630 ir_node *sel = get_Cond_selector(node);
1631 ir_node *new_sel = be_transform_node(sel);
1633 int switch_min = INT_MAX;
1634 const ir_edge_t *edge;
1636 /* determine the smallest switch case value */
1637 foreach_out_edge(node, edge) {
1638 ir_node *proj = get_edge_src_irn(edge);
1639 int pn = get_Proj_proj(proj);
1644 if (switch_min != 0) {
1645 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1647 /* if smallest switch case is not 0 we need an additional sub */
1648 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1649 add_ia32_am_offs_int(new_sel, -switch_min);
1650 set_ia32_am_flavour(new_sel, ia32_am_OB);
1651 set_ia32_op_type(new_sel, ia32_AddrModeS);
1653 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1656 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1657 set_ia32_pncode(res, get_Cond_defaultProj(node));
1659 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1665 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1667 * @return The transformed node.
1669 static ir_node *gen_Cond(ir_node *node) {
1670 ir_node *block = be_transform_node(get_nodes_block(node));
1671 ir_graph *irg = current_ir_graph;
1672 dbg_info *dbgi = get_irn_dbg_info(node);
1673 ir_node *sel = get_Cond_selector(node);
1674 ir_mode *sel_mode = get_irn_mode(sel);
1675 ir_node *res = NULL;
1676 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1683 ir_node *nomem = new_NoMem();
1686 if (sel_mode != mode_b) {
1687 return create_Switch(node);
1690 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1691 /* it's some mode_b value not a direct comparison -> create a testjmp */
1692 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1693 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1697 cmp = get_Proj_pred(sel);
1698 cmp_a = get_Cmp_left(cmp);
1699 cmp_b = get_Cmp_right(cmp);
1700 cmp_mode = get_irn_mode(cmp_a);
1701 pnc = get_Proj_proj(sel);
1702 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1703 pnc |= ia32_pn_Cmp_Unsigned;
1706 if(mode_needs_gp_reg(cmp_mode)) {
1707 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1709 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1714 new_cmp_a = be_transform_node(cmp_a);
1715 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1717 if (mode_is_float(cmp_mode)) {
1718 if (USE_SSE2(env_cg)) {
1719 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1721 set_ia32_commutative(res);
1722 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1723 set_ia32_ls_mode(res, cmp_mode);
1725 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1726 set_ia32_commutative(res);
1729 assert(get_mode_size_bits(cmp_mode) == 32);
1730 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1731 new_cmp_a, new_cmp_b, nomem, pnc);
1732 set_ia32_commutative(res);
1733 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1736 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1744 * Transforms a CopyB node.
1746 * @return The transformed node.
1748 static ir_node *gen_CopyB(ir_node *node) {
1749 ir_node *block = be_transform_node(get_nodes_block(node));
1750 ir_node *src = get_CopyB_src(node);
1751 ir_node *new_src = be_transform_node(src);
1752 ir_node *dst = get_CopyB_dst(node);
1753 ir_node *new_dst = be_transform_node(dst);
1754 ir_node *mem = get_CopyB_mem(node);
1755 ir_node *new_mem = be_transform_node(mem);
1756 ir_node *res = NULL;
1757 ir_graph *irg = current_ir_graph;
1758 dbg_info *dbgi = get_irn_dbg_info(node);
1759 int size = get_type_size_bytes(get_CopyB_type(node));
1762 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1763 /* then we need the size explicitly in ECX. */
1764 if (size >= 32 * 4) {
1765 rem = size & 0x3; /* size % 4 */
1768 res = new_rd_ia32_Const(dbgi, irg, block);
1769 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1770 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1772 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1773 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1775 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1776 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1779 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1785 ir_node *gen_be_Copy(ir_node *node)
1787 ir_node *result = be_duplicate_node(node);
1788 ir_mode *mode = get_irn_mode(result);
1790 if (mode_needs_gp_reg(mode)) {
1791 set_irn_mode(result, mode_Iu);
1798 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1799 dbg_info *dbgi, ir_node *block)
1801 ir_graph *irg = current_ir_graph;
1802 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1803 ir_node *nomem = new_rd_NoMem(irg);
1804 ir_node *new_cmp_left;
1805 ir_node *new_cmp_right;
1808 /* can we use a test instruction? */
1809 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1810 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1811 if(is_And(cmp_left) &&
1812 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1813 ir_node *and_left = get_And_left(cmp_left);
1814 ir_node *and_right = get_And_right(cmp_left);
1816 new_cmp_left = be_transform_node(and_left);
1817 new_cmp_right = create_immediate_or_transform(and_right, 0);
1819 new_cmp_left = be_transform_node(cmp_left);
1820 new_cmp_right = be_transform_node(cmp_left);
1823 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1824 new_cmp_left, new_cmp_right, nomem, pnc);
1825 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1830 new_cmp_left = be_transform_node(cmp_left);
1831 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1832 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1833 new_cmp_left, new_cmp_right, nomem, pnc);
1838 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1839 ir_node *val_true, ir_node *val_false,
1840 dbg_info *dbgi, ir_node *block)
1842 ir_graph *irg = current_ir_graph;
1843 ir_node *new_val_true = be_transform_node(val_true);
1844 ir_node *new_val_false = be_transform_node(val_false);
1845 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1846 ir_node *nomem = new_NoMem();
1847 ir_node *new_cmp_left;
1848 ir_node *new_cmp_right;
1851 /* cmovs with unknowns are pointless... */
1852 if(is_Unknown(val_true)) {
1853 #ifdef DEBUG_libfirm
1854 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1856 return new_val_false;
1858 if(is_Unknown(val_false)) {
1859 #ifdef DEBUG_libfirm
1860 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1862 return new_val_true;
1865 /* can we use a test instruction? */
1866 if(is_Const_0(cmp_right)) {
1867 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1868 if(is_And(cmp_left) &&
1869 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1870 ir_node *and_left = get_And_left(cmp_left);
1871 ir_node *and_right = get_And_right(cmp_left);
1873 new_cmp_left = be_transform_node(and_left);
1874 new_cmp_right = create_immediate_or_transform(and_right, 0);
1876 new_cmp_left = be_transform_node(cmp_left);
1877 new_cmp_right = be_transform_node(cmp_left);
1880 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1881 new_cmp_left, new_cmp_right, nomem,
1882 new_val_true, new_val_false, pnc);
1883 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1888 new_cmp_left = be_transform_node(cmp_left);
1889 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1891 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1892 new_cmp_right, nomem, new_val_true, new_val_false,
1894 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1901 * Transforms a Psi node into CMov.
1903 * @return The transformed node.
1905 static ir_node *gen_Psi(ir_node *node) {
1906 ir_node *psi_true = get_Psi_val(node, 0);
1907 ir_node *psi_default = get_Psi_default(node);
1908 ia32_code_gen_t *cg = env_cg;
1909 ir_node *cond = get_Psi_cond(node, 0);
1910 ir_node *block = be_transform_node(get_nodes_block(node));
1911 dbg_info *dbgi = get_irn_dbg_info(node);
1918 assert(get_Psi_n_conds(node) == 1);
1919 assert(get_irn_mode(cond) == mode_b);
1921 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1922 /* a mode_b value, we have to compare it against 0 */
1924 cmp_right = new_Const_long(mode_Iu, 0);
1928 ir_node *cmp = get_Proj_pred(cond);
1930 cmp_left = get_Cmp_left(cmp);
1931 cmp_right = get_Cmp_right(cmp);
1932 cmp_mode = get_irn_mode(cmp_left);
1933 pnc = get_Proj_proj(cond);
1935 assert(!mode_is_float(cmp_mode));
1937 if (!mode_is_signed(cmp_mode)) {
1938 pnc |= ia32_pn_Cmp_Unsigned;
1942 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1943 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1944 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1945 pnc = get_negated_pnc(pnc, cmp_mode);
1946 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1948 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1951 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1957 * Following conversion rules apply:
1961 * 1) n bit -> m bit n > m (downscale)
1963 * 2) n bit -> m bit n == m (sign change)
1965 * 3) n bit -> m bit n < m (upscale)
1966 * a) source is signed: movsx
1967 * b) source is unsigned: and with lower bits sets
1971 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1975 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1979 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1980 * x87 is mode_E internally, conversions happen only at load and store
1981 * in non-strict semantic
1985 * Create a conversion from x87 state register to general purpose.
1987 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
1988 ir_node *block = be_transform_node(get_nodes_block(node));
1989 ir_node *op = get_Conv_op(node);
1990 ir_node *new_op = be_transform_node(op);
1991 ia32_code_gen_t *cg = env_cg;
1992 ir_graph *irg = current_ir_graph;
1993 dbg_info *dbgi = get_irn_dbg_info(node);
1994 ir_node *noreg = ia32_new_NoReg_gp(cg);
1995 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
1996 ir_node *fist, *load;
1999 fist = new_rd_ia32_vfist(dbgi, irg, block,
2000 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2002 set_irn_pinned(fist, op_pin_state_floats);
2003 set_ia32_use_frame(fist);
2004 set_ia32_op_type(fist, ia32_AddrModeD);
2005 set_ia32_am_flavour(fist, ia32_am_B);
2006 set_ia32_ls_mode(fist, mode_Iu);
2007 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2010 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2012 set_irn_pinned(load, op_pin_state_floats);
2013 set_ia32_use_frame(load);
2014 set_ia32_op_type(load, ia32_AddrModeS);
2015 set_ia32_am_flavour(load, ia32_am_B);
2016 set_ia32_ls_mode(load, mode_Iu);
2017 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2019 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2023 * Create a conversion from general purpose to x87 register
2025 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2026 ir_node *block = be_transform_node(get_nodes_block(node));
2027 ir_node *op = get_Conv_op(node);
2028 ir_node *new_op = be_transform_node(op);
2029 ir_graph *irg = current_ir_graph;
2030 dbg_info *dbgi = get_irn_dbg_info(node);
2031 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2032 ir_node *nomem = new_NoMem();
2033 ir_node *fild, *store;
2036 /* first convert to 32 bit if necessary */
2037 src_bits = get_mode_size_bits(src_mode);
2038 if (src_bits == 8) {
2039 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2040 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2041 set_ia32_ls_mode(new_op, src_mode);
2042 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2043 } else if (src_bits < 32) {
2044 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2045 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2046 set_ia32_ls_mode(new_op, src_mode);
2047 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2051 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2053 set_ia32_use_frame(store);
2054 set_ia32_op_type(store, ia32_AddrModeD);
2055 set_ia32_am_flavour(store, ia32_am_OB);
2056 set_ia32_ls_mode(store, mode_Iu);
2059 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2061 set_ia32_use_frame(fild);
2062 set_ia32_op_type(fild, ia32_AddrModeS);
2063 set_ia32_am_flavour(fild, ia32_am_OB);
2064 set_ia32_ls_mode(fild, mode_Iu);
2066 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2069 static ir_node *create_strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2072 ir_node *block = get_nodes_block(node);
2073 ir_graph *irg = current_ir_graph;
2074 dbg_info *dbgi = get_irn_dbg_info(node);
2075 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2076 ir_node *nomem = new_NoMem();
2077 int src_bits = get_mode_size_bits(src_mode);
2078 int tgt_bits = get_mode_size_bits(tgt_mode);
2079 ir_node *frame = get_irg_frame(irg);
2080 ir_mode *smaller_mode;
2081 ir_node *store, *load;
2084 if(src_bits <= tgt_bits)
2085 smaller_mode = src_mode;
2087 smaller_mode = tgt_mode;
2089 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2091 set_ia32_use_frame(store);
2092 set_ia32_op_type(store, ia32_AddrModeD);
2093 set_ia32_am_flavour(store, ia32_am_OB);
2095 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2097 set_ia32_use_frame(load);
2098 set_ia32_op_type(load, ia32_AddrModeS);
2099 set_ia32_am_flavour(load, ia32_am_OB);
2101 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2106 * Transforms a Conv node.
2108 * @return The created ia32 Conv node
2110 static ir_node *gen_Conv(ir_node *node) {
2111 ir_node *block = be_transform_node(get_nodes_block(node));
2112 ir_node *op = get_Conv_op(node);
2113 ir_node *new_op = be_transform_node(op);
2114 ir_graph *irg = current_ir_graph;
2115 dbg_info *dbgi = get_irn_dbg_info(node);
2116 ir_mode *src_mode = get_irn_mode(op);
2117 ir_mode *tgt_mode = get_irn_mode(node);
2118 int src_bits = get_mode_size_bits(src_mode);
2119 int tgt_bits = get_mode_size_bits(tgt_mode);
2120 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2121 ir_node *nomem = new_rd_NoMem(irg);
2124 if (src_mode == mode_b) {
2125 assert(mode_is_int(tgt_mode));
2126 /* nothing to do, we already model bools as 0/1 ints */
2130 if (src_mode == tgt_mode) {
2131 if (get_Conv_strict(node)) {
2132 if (USE_SSE2(env_cg)) {
2133 /* when we are in SSE mode, we can kill all strict no-op conversion */
2137 /* this should be optimized already, but who knows... */
2138 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2139 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2144 if (mode_is_float(src_mode)) {
2145 /* we convert from float ... */
2146 if (mode_is_float(tgt_mode)) {
2147 if(src_mode == mode_E && tgt_mode == mode_D
2148 && !get_Conv_strict(node)) {
2149 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2154 if (USE_SSE2(env_cg)) {
2155 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2156 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2157 set_ia32_ls_mode(res, tgt_mode);
2159 // Matze: TODO what about strict convs?
2160 if(get_Conv_strict(node)) {
2161 res = create_strict_conv(src_mode, tgt_mode, new_op);
2162 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2165 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2170 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2171 if (USE_SSE2(env_cg)) {
2172 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2173 set_ia32_ls_mode(res, src_mode);
2175 return gen_x87_fp_to_gp(node);
2179 /* we convert from int ... */
2180 if (mode_is_float(tgt_mode)) {
2182 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2183 if (USE_SSE2(env_cg)) {
2184 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2185 set_ia32_ls_mode(res, tgt_mode);
2186 if(src_bits == 32) {
2187 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2190 return gen_x87_gp_to_fp(node, src_mode);
2192 } else if(tgt_mode == mode_b) {
2195 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2197 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2202 ir_mode *smaller_mode;
2205 if (src_bits == tgt_bits) {
2206 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2207 src_mode, tgt_mode));
2211 if (src_bits < tgt_bits) {
2212 smaller_mode = src_mode;
2213 smaller_bits = src_bits;
2215 smaller_mode = tgt_mode;
2216 smaller_bits = tgt_bits;
2219 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2220 if (smaller_bits == 8) {
2221 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2222 set_ia32_ls_mode(res, smaller_mode);
2224 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2225 set_ia32_ls_mode(res, smaller_mode);
2227 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2237 int check_immediate_constraint(long val, char immediate_constraint_type)
2239 switch (immediate_constraint_type) {
2243 return val >= 0 && val <= 32;
2245 return val >= 0 && val <= 63;
2247 return val >= -128 && val <= 127;
2249 return val == 0xff || val == 0xffff;
2251 return val >= 0 && val <= 3;
2253 return val >= 0 && val <= 255;
2255 return val >= 0 && val <= 127;
2259 panic("Invalid immediate constraint found");
2264 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2267 tarval *offset = NULL;
2268 int offset_sign = 0;
2270 ir_entity *symconst_ent = NULL;
2271 int symconst_sign = 0;
2273 ir_node *cnst = NULL;
2274 ir_node *symconst = NULL;
2280 mode = get_irn_mode(node);
2281 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2285 if(is_Minus(node)) {
2287 node = get_Minus_op(node);
2290 if(is_Const(node)) {
2293 offset_sign = minus;
2294 } else if(is_SymConst(node)) {
2297 symconst_sign = minus;
2298 } else if(is_Add(node)) {
2299 ir_node *left = get_Add_left(node);
2300 ir_node *right = get_Add_right(node);
2301 if(is_Const(left) && is_SymConst(right)) {
2304 symconst_sign = minus;
2305 offset_sign = minus;
2306 } else if(is_SymConst(left) && is_Const(right)) {
2309 symconst_sign = minus;
2310 offset_sign = minus;
2312 } else if(is_Sub(node)) {
2313 ir_node *left = get_Sub_left(node);
2314 ir_node *right = get_Sub_right(node);
2315 if(is_Const(left) && is_SymConst(right)) {
2318 symconst_sign = !minus;
2319 offset_sign = minus;
2320 } else if(is_SymConst(left) && is_Const(right)) {
2323 symconst_sign = minus;
2324 offset_sign = !minus;
2331 offset = get_Const_tarval(cnst);
2332 if(tarval_is_long(offset)) {
2333 val = get_tarval_long(offset);
2334 } else if(tarval_is_null(offset)) {
2337 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2342 if(!check_immediate_constraint(val, immediate_constraint_type))
2345 if(symconst != NULL) {
2346 if(immediate_constraint_type != 0) {
2347 /* we need full 32bits for symconsts */
2351 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2353 symconst_ent = get_SymConst_entity(symconst);
2355 if(cnst == NULL && symconst == NULL)
2358 if(offset_sign && offset != NULL) {
2359 offset = tarval_neg(offset);
2362 irg = current_ir_graph;
2363 dbgi = get_irn_dbg_info(node);
2364 block = get_irg_start_block(irg);
2365 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2367 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2369 /* make sure we don't schedule stuff before the barrier */
2370 add_irn_dep(res, get_irg_frame(irg));
2376 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2378 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2379 if (new_node == NULL) {
2380 new_node = be_transform_node(node);
2385 typedef struct constraint_t constraint_t;
2386 struct constraint_t {
2389 const arch_register_req_t **out_reqs;
2391 const arch_register_req_t *req;
2392 unsigned immediate_possible;
2393 char immediate_type;
2396 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2398 int immediate_possible = 0;
2399 char immediate_type = 0;
2400 unsigned limited = 0;
2401 const arch_register_class_t *cls = NULL;
2403 struct obstack *obst;
2404 arch_register_req_t *req;
2405 unsigned *limited_ptr;
2409 /* TODO: replace all the asserts with nice error messages */
2411 printf("Constraint: %s\n", c);
2421 assert(cls == NULL ||
2422 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2423 cls = &ia32_reg_classes[CLASS_ia32_gp];
2424 limited |= 1 << REG_EAX;
2427 assert(cls == NULL ||
2428 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2429 cls = &ia32_reg_classes[CLASS_ia32_gp];
2430 limited |= 1 << REG_EBX;
2433 assert(cls == NULL ||
2434 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2435 cls = &ia32_reg_classes[CLASS_ia32_gp];
2436 limited |= 1 << REG_ECX;
2439 assert(cls == NULL ||
2440 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2441 cls = &ia32_reg_classes[CLASS_ia32_gp];
2442 limited |= 1 << REG_EDX;
2445 assert(cls == NULL ||
2446 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2447 cls = &ia32_reg_classes[CLASS_ia32_gp];
2448 limited |= 1 << REG_EDI;
2451 assert(cls == NULL ||
2452 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2453 cls = &ia32_reg_classes[CLASS_ia32_gp];
2454 limited |= 1 << REG_ESI;
2457 case 'q': /* q means lower part of the regs only, this makes no
2458 * difference to Q for us (we only assigne whole registers) */
2459 assert(cls == NULL ||
2460 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2461 cls = &ia32_reg_classes[CLASS_ia32_gp];
2462 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2466 assert(cls == NULL ||
2467 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2468 cls = &ia32_reg_classes[CLASS_ia32_gp];
2469 limited |= 1 << REG_EAX | 1 << REG_EDX;
2472 assert(cls == NULL ||
2473 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2474 cls = &ia32_reg_classes[CLASS_ia32_gp];
2475 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2476 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2483 assert(cls == NULL);
2484 cls = &ia32_reg_classes[CLASS_ia32_gp];
2490 /* TODO: mark values so the x87 simulator knows about t and u */
2491 assert(cls == NULL);
2492 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2497 assert(cls == NULL);
2498 /* TODO: check that sse2 is supported */
2499 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2509 assert(!immediate_possible);
2510 immediate_possible = 1;
2511 immediate_type = *c;
2515 assert(!immediate_possible);
2516 immediate_possible = 1;
2520 assert(!immediate_possible && cls == NULL);
2521 immediate_possible = 1;
2522 cls = &ia32_reg_classes[CLASS_ia32_gp];
2535 assert(constraint->is_in && "can only specify same constraint "
2538 sscanf(c, "%d%n", &same_as, &p);
2545 case 'E': /* no float consts yet */
2546 case 'F': /* no float consts yet */
2547 case 's': /* makes no sense on x86 */
2548 case 'X': /* we can't support that in firm */
2552 case '<': /* no autodecrement on x86 */
2553 case '>': /* no autoincrement on x86 */
2554 case 'C': /* sse constant not supported yet */
2555 case 'G': /* 80387 constant not supported yet */
2556 case 'y': /* we don't support mmx registers yet */
2557 case 'Z': /* not available in 32 bit mode */
2558 case 'e': /* not available in 32 bit mode */
2559 assert(0 && "asm constraint not supported");
2562 assert(0 && "unknown asm constraint found");
2569 const arch_register_req_t *other_constr;
2571 assert(cls == NULL && "same as and register constraint not supported");
2572 assert(!immediate_possible && "same as and immediate constraint not "
2574 assert(same_as < constraint->n_outs && "wrong constraint number in "
2575 "same_as constraint");
2577 other_constr = constraint->out_reqs[same_as];
2579 req = obstack_alloc(obst, sizeof(req[0]));
2580 req->cls = other_constr->cls;
2581 req->type = arch_register_req_type_should_be_same;
2582 req->limited = NULL;
2583 req->other_same = pos;
2584 req->other_different = -1;
2586 /* switch constraints. This is because in firm we have same_as
2587 * constraints on the output constraints while in the gcc asm syntax
2588 * they are specified on the input constraints */
2589 constraint->req = other_constr;
2590 constraint->out_reqs[same_as] = req;
2591 constraint->immediate_possible = 0;
2595 if(immediate_possible && cls == NULL) {
2596 cls = &ia32_reg_classes[CLASS_ia32_gp];
2598 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2599 assert(cls != NULL);
2601 if(immediate_possible) {
2602 assert(constraint->is_in
2603 && "imeediates make no sense for output constraints");
2605 /* todo: check types (no float input on 'r' constrainted in and such... */
2607 irg = current_ir_graph;
2608 obst = get_irg_obstack(irg);
2611 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2612 limited_ptr = (unsigned*) (req+1);
2614 req = obstack_alloc(obst, sizeof(req[0]));
2616 memset(req, 0, sizeof(req[0]));
2619 req->type = arch_register_req_type_limited;
2620 *limited_ptr = limited;
2621 req->limited = limited_ptr;
2623 req->type = arch_register_req_type_normal;
2627 constraint->req = req;
2628 constraint->immediate_possible = immediate_possible;
2629 constraint->immediate_type = immediate_type;
2633 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2640 panic("Clobbers not supported yet");
2643 ir_node *gen_ASM(ir_node *node)
2646 ir_graph *irg = current_ir_graph;
2647 ir_node *block = be_transform_node(get_nodes_block(node));
2648 dbg_info *dbgi = get_irn_dbg_info(node);
2655 ia32_asm_attr_t *attr;
2656 const arch_register_req_t **out_reqs;
2657 const arch_register_req_t **in_reqs;
2658 struct obstack *obst;
2659 constraint_t parsed_constraint;
2661 /* transform inputs */
2662 arity = get_irn_arity(node);
2663 in = alloca(arity * sizeof(in[0]));
2664 memset(in, 0, arity * sizeof(in[0]));
2666 n_outs = get_ASM_n_output_constraints(node);
2667 n_clobbers = get_ASM_n_clobbers(node);
2668 out_arity = n_outs + n_clobbers;
2670 /* construct register constraints */
2671 obst = get_irg_obstack(irg);
2672 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2673 parsed_constraint.out_reqs = out_reqs;
2674 parsed_constraint.n_outs = n_outs;
2675 parsed_constraint.is_in = 0;
2676 for(i = 0; i < out_arity; ++i) {
2680 const ir_asm_constraint *constraint;
2681 constraint = & get_ASM_output_constraints(node) [i];
2682 c = get_id_str(constraint->constraint);
2683 parse_asm_constraint(i, &parsed_constraint, c);
2685 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2686 c = get_id_str(glob_id);
2687 parse_clobber(node, i, &parsed_constraint, c);
2689 out_reqs[i] = parsed_constraint.req;
2692 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2693 parsed_constraint.is_in = 1;
2694 for(i = 0; i < arity; ++i) {
2695 const ir_asm_constraint *constraint;
2699 constraint = & get_ASM_input_constraints(node) [i];
2700 constr_id = constraint->constraint;
2701 c = get_id_str(constr_id);
2702 parse_asm_constraint(i, &parsed_constraint, c);
2703 in_reqs[i] = parsed_constraint.req;
2705 if(parsed_constraint.immediate_possible) {
2706 ir_node *pred = get_irn_n(node, i);
2707 char imm_type = parsed_constraint.immediate_type;
2708 ir_node *immediate = try_create_Immediate(pred, imm_type);
2710 if(immediate != NULL) {
2716 /* transform inputs */
2717 for(i = 0; i < arity; ++i) {
2719 ir_node *transformed;
2724 pred = get_irn_n(node, i);
2725 transformed = be_transform_node(pred);
2726 in[i] = transformed;
2729 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2731 generic_attr = get_irn_generic_attr(res);
2732 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2733 attr->asm_text = get_ASM_text(node);
2734 set_ia32_out_req_all(res, out_reqs);
2735 set_ia32_in_req_all(res, in_reqs);
2737 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2742 /********************************************
2745 * | |__ ___ _ __ ___ __| | ___ ___
2746 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2747 * | |_) | __/ | | | (_) | (_| | __/\__ \
2748 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2750 ********************************************/
2752 static ir_node *gen_be_StackParam(ir_node *node) {
2753 ir_node *block = be_transform_node(get_nodes_block(node));
2754 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2755 ir_node *new_ptr = be_transform_node(ptr);
2756 ir_node *new_op = NULL;
2757 ir_graph *irg = current_ir_graph;
2758 dbg_info *dbgi = get_irn_dbg_info(node);
2759 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2760 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2761 ir_mode *load_mode = get_irn_mode(node);
2762 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2766 if (mode_is_float(load_mode)) {
2767 if (USE_SSE2(env_cg)) {
2768 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2769 pn_res = pn_ia32_xLoad_res;
2770 proj_mode = mode_xmm;
2772 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2773 pn_res = pn_ia32_vfld_res;
2774 proj_mode = mode_vfp;
2777 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2778 proj_mode = mode_Iu;
2779 pn_res = pn_ia32_Load_res;
2782 set_irn_pinned(new_op, op_pin_state_floats);
2783 set_ia32_frame_ent(new_op, ent);
2784 set_ia32_use_frame(new_op);
2786 set_ia32_op_type(new_op, ia32_AddrModeS);
2787 set_ia32_am_flavour(new_op, ia32_am_B);
2788 set_ia32_ls_mode(new_op, load_mode);
2789 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2793 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2797 * Transforms a FrameAddr into an ia32 Add.
2799 static ir_node *gen_be_FrameAddr(ir_node *node) {
2800 ir_node *block = be_transform_node(get_nodes_block(node));
2801 ir_node *op = be_get_FrameAddr_frame(node);
2802 ir_node *new_op = be_transform_node(op);
2803 ir_graph *irg = current_ir_graph;
2804 dbg_info *dbgi = get_irn_dbg_info(node);
2805 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2808 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2809 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2810 set_ia32_use_frame(res);
2811 set_ia32_am_flavour(res, ia32_am_OB);
2813 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2819 * Transforms a FrameLoad into an ia32 Load.
2821 static ir_node *gen_be_FrameLoad(ir_node *node) {
2822 ir_node *block = be_transform_node(get_nodes_block(node));
2823 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2824 ir_node *new_mem = be_transform_node(mem);
2825 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2826 ir_node *new_ptr = be_transform_node(ptr);
2827 ir_node *new_op = NULL;
2828 ir_graph *irg = current_ir_graph;
2829 dbg_info *dbgi = get_irn_dbg_info(node);
2830 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2831 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2832 ir_mode *mode = get_type_mode(get_entity_type(ent));
2833 ir_node *projs[pn_Load_max];
2835 ia32_collect_Projs(node, projs, pn_Load_max);
2837 if (mode_is_float(mode)) {
2838 if (USE_SSE2(env_cg)) {
2839 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2842 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2846 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2849 set_irn_pinned(new_op, op_pin_state_floats);
2850 set_ia32_frame_ent(new_op, ent);
2851 set_ia32_use_frame(new_op);
2853 set_ia32_op_type(new_op, ia32_AddrModeS);
2854 set_ia32_am_flavour(new_op, ia32_am_B);
2855 set_ia32_ls_mode(new_op, mode);
2856 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2858 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2865 * Transforms a FrameStore into an ia32 Store.
2867 static ir_node *gen_be_FrameStore(ir_node *node) {
2868 ir_node *block = be_transform_node(get_nodes_block(node));
2869 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2870 ir_node *new_mem = be_transform_node(mem);
2871 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2872 ir_node *new_ptr = be_transform_node(ptr);
2873 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2874 ir_node *new_val = be_transform_node(val);
2875 ir_node *new_op = NULL;
2876 ir_graph *irg = current_ir_graph;
2877 dbg_info *dbgi = get_irn_dbg_info(node);
2878 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2879 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2880 ir_mode *mode = get_irn_mode(val);
2882 if (mode_is_float(mode)) {
2883 if (USE_SSE2(env_cg)) {
2884 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2886 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2888 } else if (get_mode_size_bits(mode) == 8) {
2889 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2891 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2894 set_ia32_frame_ent(new_op, ent);
2895 set_ia32_use_frame(new_op);
2897 set_ia32_op_type(new_op, ia32_AddrModeD);
2898 set_ia32_am_flavour(new_op, ia32_am_B);
2899 set_ia32_ls_mode(new_op, mode);
2901 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2907 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2909 static ir_node *gen_be_Return(ir_node *node) {
2910 ir_graph *irg = current_ir_graph;
2911 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2912 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2913 ir_entity *ent = get_irg_entity(irg);
2914 ir_type *tp = get_entity_type(ent);
2919 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2920 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2923 int pn_ret_val, pn_ret_mem, arity, i;
2925 assert(ret_val != NULL);
2926 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2927 return be_duplicate_node(node);
2930 res_type = get_method_res_type(tp, 0);
2932 if (! is_Primitive_type(res_type)) {
2933 return be_duplicate_node(node);
2936 mode = get_type_mode(res_type);
2937 if (! mode_is_float(mode)) {
2938 return be_duplicate_node(node);
2941 assert(get_method_n_ress(tp) == 1);
2943 pn_ret_val = get_Proj_proj(ret_val);
2944 pn_ret_mem = get_Proj_proj(ret_mem);
2946 /* get the Barrier */
2947 barrier = get_Proj_pred(ret_val);
2949 /* get result input of the Barrier */
2950 ret_val = get_irn_n(barrier, pn_ret_val);
2951 new_ret_val = be_transform_node(ret_val);
2953 /* get memory input of the Barrier */
2954 ret_mem = get_irn_n(barrier, pn_ret_mem);
2955 new_ret_mem = be_transform_node(ret_mem);
2957 frame = get_irg_frame(irg);
2959 dbgi = get_irn_dbg_info(barrier);
2960 block = be_transform_node(get_nodes_block(barrier));
2962 noreg = ia32_new_NoReg_gp(env_cg);
2964 /* store xmm0 onto stack */
2965 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
2966 set_ia32_ls_mode(sse_store, mode);
2967 set_ia32_op_type(sse_store, ia32_AddrModeD);
2968 set_ia32_use_frame(sse_store);
2969 set_ia32_am_flavour(sse_store, ia32_am_B);
2972 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
2973 set_ia32_ls_mode(fld, mode);
2974 set_ia32_op_type(fld, ia32_AddrModeS);
2975 set_ia32_use_frame(fld);
2976 set_ia32_am_flavour(fld, ia32_am_B);
2978 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2979 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2980 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2982 /* create a new barrier */
2983 arity = get_irn_arity(barrier);
2984 in = alloca(arity * sizeof(in[0]));
2985 for (i = 0; i < arity; ++i) {
2988 if (i == pn_ret_val) {
2990 } else if (i == pn_ret_mem) {
2993 ir_node *in = get_irn_n(barrier, i);
2994 new_in = be_transform_node(in);
2999 new_barrier = new_ir_node(dbgi, irg, block,
3000 get_irn_op(barrier), get_irn_mode(barrier),
3002 copy_node_attr(barrier, new_barrier);
3003 be_duplicate_deps(barrier, new_barrier);
3004 be_set_transformed_node(barrier, new_barrier);
3005 mark_irn_visited(barrier);
3007 /* transform normally */
3008 return be_duplicate_node(node);
3012 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3014 static ir_node *gen_be_AddSP(ir_node *node) {
3015 ir_node *block = be_transform_node(get_nodes_block(node));
3016 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3018 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3019 ir_node *new_sp = be_transform_node(sp);
3020 ir_graph *irg = current_ir_graph;
3021 dbg_info *dbgi = get_irn_dbg_info(node);
3022 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3023 ir_node *nomem = new_NoMem();
3026 new_sz = create_immediate_or_transform(sz, 0);
3028 /* ia32 stack grows in reverse direction, make a SubSP */
3029 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3031 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3032 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3038 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3040 static ir_node *gen_be_SubSP(ir_node *node) {
3041 ir_node *block = be_transform_node(get_nodes_block(node));
3042 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3044 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3045 ir_node *new_sp = be_transform_node(sp);
3046 ir_graph *irg = current_ir_graph;
3047 dbg_info *dbgi = get_irn_dbg_info(node);
3048 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3049 ir_node *nomem = new_NoMem();
3052 new_sz = create_immediate_or_transform(sz, 0);
3054 /* ia32 stack grows in reverse direction, make an AddSP */
3055 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3056 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3063 * This function just sets the register for the Unknown node
3064 * as this is not done during register allocation because Unknown
3065 * is an "ignore" node.
3067 static ir_node *gen_Unknown(ir_node *node) {
3068 ir_mode *mode = get_irn_mode(node);
3070 if (mode_is_float(mode)) {
3071 if (USE_SSE2(env_cg))
3072 return ia32_new_Unknown_xmm(env_cg);
3074 return ia32_new_Unknown_vfp(env_cg);
3075 } else if (mode_needs_gp_reg(mode)) {
3076 return ia32_new_Unknown_gp(env_cg);
3078 assert(0 && "unsupported Unknown-Mode");
3085 * Change some phi modes
3087 static ir_node *gen_Phi(ir_node *node) {
3088 ir_node *block = be_transform_node(get_nodes_block(node));
3089 ir_graph *irg = current_ir_graph;
3090 dbg_info *dbgi = get_irn_dbg_info(node);
3091 ir_mode *mode = get_irn_mode(node);
3094 if(mode_needs_gp_reg(mode)) {
3095 /* we shouldn't have any 64bit stuff around anymore */
3096 assert(get_mode_size_bits(mode) <= 32);
3097 /* all integer operations are on 32bit registers now */
3099 } else if(mode_is_float(mode)) {
3100 if (USE_SSE2(env_cg)) {
3107 /* phi nodes allow loops, so we use the old arguments for now
3108 * and fix this later */
3109 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3110 copy_node_attr(node, phi);
3111 be_duplicate_deps(node, phi);
3113 be_set_transformed_node(node, phi);
3114 be_enqueue_preds(node);
3119 /**********************************************************************
3122 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3123 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3124 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3125 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3127 **********************************************************************/
3129 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3131 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3134 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3135 ir_node *val, ir_node *mem);
3138 * Transforms a lowered Load into a "real" one.
3140 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3142 ir_node *block = be_transform_node(get_nodes_block(node));
3143 ir_node *ptr = get_irn_n(node, 0);
3144 ir_node *new_ptr = be_transform_node(ptr);
3145 ir_node *mem = get_irn_n(node, 1);
3146 ir_node *new_mem = be_transform_node(mem);
3147 ir_graph *irg = current_ir_graph;
3148 dbg_info *dbgi = get_irn_dbg_info(node);
3149 ir_mode *mode = get_ia32_ls_mode(node);
3150 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3153 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3155 set_ia32_op_type(new_op, ia32_AddrModeS);
3156 set_ia32_am_flavour(new_op, ia32_am_OB);
3157 set_ia32_am_offs_int(new_op, 0);
3158 set_ia32_am_scale(new_op, 1);
3159 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3160 if (is_ia32_am_sc_sign(node))
3161 set_ia32_am_sc_sign(new_op);
3162 set_ia32_ls_mode(new_op, mode);
3163 if (is_ia32_use_frame(node)) {
3164 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3165 set_ia32_use_frame(new_op);
3168 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3174 * Transforms a lowered Store into a "real" one.
3176 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3178 ir_node *block = be_transform_node(get_nodes_block(node));
3179 ir_node *ptr = get_irn_n(node, 0);
3180 ir_node *new_ptr = be_transform_node(ptr);
3181 ir_node *val = get_irn_n(node, 1);
3182 ir_node *new_val = be_transform_node(val);
3183 ir_node *mem = get_irn_n(node, 2);
3184 ir_node *new_mem = be_transform_node(mem);
3185 ir_graph *irg = current_ir_graph;
3186 dbg_info *dbgi = get_irn_dbg_info(node);
3187 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3188 ir_mode *mode = get_ia32_ls_mode(node);
3191 ia32_am_flavour_t am_flav = ia32_B;
3193 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3195 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3197 add_ia32_am_offs_int(new_op, am_offs);
3200 set_ia32_op_type(new_op, ia32_AddrModeD);
3201 set_ia32_am_flavour(new_op, am_flav);
3202 set_ia32_ls_mode(new_op, mode);
3203 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3204 set_ia32_use_frame(new_op);
3206 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3213 * Transforms an ia32_l_XXX into a "real" XXX node
3215 * @param env The transformation environment
3216 * @return the created ia32 XXX node
3218 #define GEN_LOWERED_OP(op) \
3219 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3220 return gen_binop(node, get_binop_left(node), \
3221 get_binop_right(node), new_rd_ia32_##op,0); \
3224 #define GEN_LOWERED_x87_OP(op) \
3225 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3227 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3228 get_binop_right(node), new_rd_ia32_##op); \
3232 #define GEN_LOWERED_UNOP(op) \
3233 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3234 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3237 #define GEN_LOWERED_SHIFT_OP(op) \
3238 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3239 return gen_shift_binop(node, get_binop_left(node), \
3240 get_binop_right(node), new_rd_ia32_##op); \
3243 #define GEN_LOWERED_LOAD(op) \
3244 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3245 return gen_lowered_Load(node, new_rd_ia32_##op); \
3248 #define GEN_LOWERED_STORE(op) \
3249 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3250 return gen_lowered_Store(node, new_rd_ia32_##op); \
3257 GEN_LOWERED_OP(IMul)
3259 GEN_LOWERED_x87_OP(vfprem)
3260 GEN_LOWERED_x87_OP(vfmul)
3261 GEN_LOWERED_x87_OP(vfsub)
3263 GEN_LOWERED_UNOP(Neg)
3265 GEN_LOWERED_LOAD(vfild)
3266 GEN_LOWERED_LOAD(Load)
3267 // GEN_LOWERED_STORE(vfist) TODO
3268 GEN_LOWERED_STORE(Store)
3270 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3271 ir_node *block = be_transform_node(get_nodes_block(node));
3272 ir_node *left = get_binop_left(node);
3273 ir_node *new_left = be_transform_node(left);
3274 ir_node *right = get_binop_right(node);
3275 ir_node *new_right = be_transform_node(right);
3276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3277 ir_graph *irg = current_ir_graph;
3278 dbg_info *dbgi = get_irn_dbg_info(node);
3279 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3280 &ia32_fp_cw_regs[REG_FPCW]);
3283 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3284 new_right, new_NoMem(), fpcw);
3285 clear_ia32_commutative(vfdiv);
3286 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3288 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3294 * Transforms a l_MulS into a "real" MulS node.
3296 * @param env The transformation environment
3297 * @return the created ia32 Mul node
3299 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3300 ir_node *block = be_transform_node(get_nodes_block(node));
3301 ir_node *left = get_binop_left(node);
3302 ir_node *new_left = be_transform_node(left);
3303 ir_node *right = get_binop_right(node);
3304 ir_node *new_right = be_transform_node(right);
3305 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3306 ir_graph *irg = current_ir_graph;
3307 dbg_info *dbgi = get_irn_dbg_info(node);
3309 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3310 /* and then skip the result Proj, because all needed Projs are already there. */
3311 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3312 new_right, new_NoMem());
3313 clear_ia32_commutative(muls);
3314 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3316 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3321 GEN_LOWERED_SHIFT_OP(Shl)
3322 GEN_LOWERED_SHIFT_OP(Shr)
3323 GEN_LOWERED_SHIFT_OP(Sar)
3326 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3327 * op1 - target to be shifted
3328 * op2 - contains bits to be shifted into target
3330 * Only op3 can be an immediate.
3332 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3333 ir_node *op2, ir_node *count)
3335 ir_node *block = be_transform_node(get_nodes_block(node));
3336 ir_node *new_op1 = be_transform_node(op1);
3337 ir_node *new_op2 = be_transform_node(op2);
3338 ir_node *new_count = be_transform_node(count);
3339 ir_node *new_op = NULL;
3340 ir_graph *irg = current_ir_graph;
3341 dbg_info *dbgi = get_irn_dbg_info(node);
3342 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3343 ir_node *nomem = new_NoMem();
3347 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3349 /* Check if immediate optimization is on and */
3350 /* if it's an operation with immediate. */
3351 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3353 /* Limit imm_op within range imm8 */
3355 tv = get_ia32_Immop_tarval(imm_op);
3358 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3359 set_ia32_Immop_tarval(imm_op, tv);
3366 /* integer operations */
3368 /* This is ShiftD with const */
3369 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3371 if (is_ia32_l_ShlD(node))
3372 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3373 new_op1, new_op2, noreg, nomem);
3375 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3376 new_op1, new_op2, noreg, nomem);
3377 copy_ia32_Immop_attr(new_op, imm_op);
3380 /* This is a normal ShiftD */
3381 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3382 if (is_ia32_l_ShlD(node))
3383 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3384 new_op1, new_op2, new_count, nomem);
3386 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3387 new_op1, new_op2, new_count, nomem);
3390 /* set AM support */
3391 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3393 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3395 set_ia32_emit_cl(new_op);
3400 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3401 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3402 get_irn_n(node, 1), get_irn_n(node, 2));
3405 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3406 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3407 get_irn_n(node, 1), get_irn_n(node, 2));
3411 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3413 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3414 ir_node *block = be_transform_node(get_nodes_block(node));
3415 ir_node *val = get_irn_n(node, 1);
3416 ir_node *new_val = be_transform_node(val);
3417 ia32_code_gen_t *cg = env_cg;
3418 ir_node *res = NULL;
3419 ir_graph *irg = current_ir_graph;
3421 ir_node *noreg, *new_ptr, *new_mem;
3428 mem = get_irn_n(node, 2);
3429 new_mem = be_transform_node(mem);
3430 ptr = get_irn_n(node, 0);
3431 new_ptr = be_transform_node(ptr);
3432 noreg = ia32_new_NoReg_gp(cg);
3433 dbgi = get_irn_dbg_info(node);
3435 /* Store x87 -> MEM */
3436 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3437 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3438 set_ia32_use_frame(res);
3439 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3440 set_ia32_am_flavour(res, ia32_B);
3441 set_ia32_op_type(res, ia32_AddrModeD);
3443 /* Load MEM -> SSE */
3444 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3445 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3446 set_ia32_use_frame(res);
3447 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3448 set_ia32_am_flavour(res, ia32_B);
3449 set_ia32_op_type(res, ia32_AddrModeS);
3450 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3456 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3458 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3459 ir_node *block = be_transform_node(get_nodes_block(node));
3460 ir_node *val = get_irn_n(node, 1);
3461 ir_node *new_val = be_transform_node(val);
3462 ia32_code_gen_t *cg = env_cg;
3463 ir_graph *irg = current_ir_graph;
3464 ir_node *res = NULL;
3465 ir_entity *fent = get_ia32_frame_ent(node);
3466 ir_mode *lsmode = get_ia32_ls_mode(node);
3468 ir_node *noreg, *new_ptr, *new_mem;
3472 if (! USE_SSE2(cg)) {
3473 /* SSE unit is not used -> skip this node. */
3477 ptr = get_irn_n(node, 0);
3478 new_ptr = be_transform_node(ptr);
3479 mem = get_irn_n(node, 2);
3480 new_mem = be_transform_node(mem);
3481 noreg = ia32_new_NoReg_gp(cg);
3482 dbgi = get_irn_dbg_info(node);
3484 /* Store SSE -> MEM */
3485 if (is_ia32_xLoad(skip_Proj(new_val))) {
3486 ir_node *ld = skip_Proj(new_val);
3488 /* we can vfld the value directly into the fpu */
3489 fent = get_ia32_frame_ent(ld);
3490 ptr = get_irn_n(ld, 0);
3491 offs = get_ia32_am_offs_int(ld);
3493 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3494 set_ia32_frame_ent(res, fent);
3495 set_ia32_use_frame(res);
3496 set_ia32_ls_mode(res, lsmode);
3497 set_ia32_am_flavour(res, ia32_B);
3498 set_ia32_op_type(res, ia32_AddrModeD);
3502 /* Load MEM -> x87 */
3503 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3504 set_ia32_frame_ent(res, fent);
3505 set_ia32_use_frame(res);
3506 add_ia32_am_offs_int(res, offs);
3507 set_ia32_am_flavour(res, ia32_B);
3508 set_ia32_op_type(res, ia32_AddrModeS);
3509 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3514 /*********************************************************
3517 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3518 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3519 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3520 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3522 *********************************************************/
3525 * the BAD transformer.
3527 static ir_node *bad_transform(ir_node *node) {
3528 panic("No transform function for %+F available.\n", node);
3533 * Transform the Projs of an AddSP.
3535 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3536 ir_node *block = be_transform_node(get_nodes_block(node));
3537 ir_node *pred = get_Proj_pred(node);
3538 ir_node *new_pred = be_transform_node(pred);
3539 ir_graph *irg = current_ir_graph;
3540 dbg_info *dbgi = get_irn_dbg_info(node);
3541 long proj = get_Proj_proj(node);
3543 if (proj == pn_be_AddSP_res) {
3544 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3545 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3547 } else if (proj == pn_be_AddSP_M) {
3548 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3552 return new_rd_Unknown(irg, get_irn_mode(node));
3556 * Transform the Projs of a SubSP.
3558 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3559 ir_node *block = be_transform_node(get_nodes_block(node));
3560 ir_node *pred = get_Proj_pred(node);
3561 ir_node *new_pred = be_transform_node(pred);
3562 ir_graph *irg = current_ir_graph;
3563 dbg_info *dbgi = get_irn_dbg_info(node);
3564 long proj = get_Proj_proj(node);
3566 if (proj == pn_be_SubSP_res) {
3567 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3568 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3570 } else if (proj == pn_be_SubSP_M) {
3571 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3575 return new_rd_Unknown(irg, get_irn_mode(node));
3579 * Transform and renumber the Projs from a Load.
3581 static ir_node *gen_Proj_Load(ir_node *node) {
3582 ir_node *block = be_transform_node(get_nodes_block(node));
3583 ir_node *pred = get_Proj_pred(node);
3584 ir_node *new_pred = be_transform_node(pred);
3585 ir_graph *irg = current_ir_graph;
3586 dbg_info *dbgi = get_irn_dbg_info(node);
3587 long proj = get_Proj_proj(node);
3589 /* renumber the proj */
3590 if (is_ia32_Load(new_pred)) {
3591 if (proj == pn_Load_res) {
3592 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3593 } else if (proj == pn_Load_M) {
3594 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3596 } else if (is_ia32_xLoad(new_pred)) {
3597 if (proj == pn_Load_res) {
3598 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3599 } else if (proj == pn_Load_M) {
3600 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3602 } else if (is_ia32_vfld(new_pred)) {
3603 if (proj == pn_Load_res) {
3604 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3605 } else if (proj == pn_Load_M) {
3606 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3611 return new_rd_Unknown(irg, get_irn_mode(node));
3615 * Transform and renumber the Projs from a DivMod like instruction.
3617 static ir_node *gen_Proj_DivMod(ir_node *node) {
3618 ir_node *block = be_transform_node(get_nodes_block(node));
3619 ir_node *pred = get_Proj_pred(node);
3620 ir_node *new_pred = be_transform_node(pred);
3621 ir_graph *irg = current_ir_graph;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ir_mode *mode = get_irn_mode(node);
3624 long proj = get_Proj_proj(node);
3626 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3628 switch (get_irn_opcode(pred)) {
3632 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3634 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3642 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3644 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3652 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3653 case pn_DivMod_res_div:
3654 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3655 case pn_DivMod_res_mod:
3656 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3666 return new_rd_Unknown(irg, mode);
3670 * Transform and renumber the Projs from a CopyB.
3672 static ir_node *gen_Proj_CopyB(ir_node *node) {
3673 ir_node *block = be_transform_node(get_nodes_block(node));
3674 ir_node *pred = get_Proj_pred(node);
3675 ir_node *new_pred = be_transform_node(pred);
3676 ir_graph *irg = current_ir_graph;
3677 dbg_info *dbgi = get_irn_dbg_info(node);
3678 ir_mode *mode = get_irn_mode(node);
3679 long proj = get_Proj_proj(node);
3682 case pn_CopyB_M_regular:
3683 if (is_ia32_CopyB_i(new_pred)) {
3684 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3685 } else if (is_ia32_CopyB(new_pred)) {
3686 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3694 return new_rd_Unknown(irg, mode);
3698 * Transform and renumber the Projs from a vfdiv.
3700 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3701 ir_node *block = be_transform_node(get_nodes_block(node));
3702 ir_node *pred = get_Proj_pred(node);
3703 ir_node *new_pred = be_transform_node(pred);
3704 ir_graph *irg = current_ir_graph;
3705 dbg_info *dbgi = get_irn_dbg_info(node);
3706 ir_mode *mode = get_irn_mode(node);
3707 long proj = get_Proj_proj(node);
3710 case pn_ia32_l_vfdiv_M:
3711 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3712 case pn_ia32_l_vfdiv_res:
3713 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3718 return new_rd_Unknown(irg, mode);
3722 * Transform and renumber the Projs from a Quot.
3724 static ir_node *gen_Proj_Quot(ir_node *node) {
3725 ir_node *block = be_transform_node(get_nodes_block(node));
3726 ir_node *pred = get_Proj_pred(node);
3727 ir_node *new_pred = be_transform_node(pred);
3728 ir_graph *irg = current_ir_graph;
3729 dbg_info *dbgi = get_irn_dbg_info(node);
3730 ir_mode *mode = get_irn_mode(node);
3731 long proj = get_Proj_proj(node);
3735 if (is_ia32_xDiv(new_pred)) {
3736 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3737 } else if (is_ia32_vfdiv(new_pred)) {
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3742 if (is_ia32_xDiv(new_pred)) {
3743 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3744 } else if (is_ia32_vfdiv(new_pred)) {
3745 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3753 return new_rd_Unknown(irg, mode);
3757 * Transform the Thread Local Storage Proj.
3759 static ir_node *gen_Proj_tls(ir_node *node) {
3760 ir_node *block = be_transform_node(get_nodes_block(node));
3761 ir_graph *irg = current_ir_graph;
3762 dbg_info *dbgi = NULL;
3763 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3769 * Transform the Projs from a be_Call.
3771 static ir_node *gen_Proj_be_Call(ir_node *node) {
3772 ir_node *block = be_transform_node(get_nodes_block(node));
3773 ir_node *call = get_Proj_pred(node);
3774 ir_node *new_call = be_transform_node(call);
3775 ir_graph *irg = current_ir_graph;
3776 dbg_info *dbgi = get_irn_dbg_info(node);
3777 long proj = get_Proj_proj(node);
3778 ir_mode *mode = get_irn_mode(node);
3780 const arch_register_class_t *cls;
3782 /* The following is kinda tricky: If we're using SSE, then we have to
3783 * move the result value of the call in floating point registers to an
3784 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3785 * after the call, we have to make sure to correctly make the
3786 * MemProj and the result Proj use these 2 nodes
3788 if (proj == pn_be_Call_M_regular) {
3789 // get new node for result, are we doing the sse load/store hack?
3790 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3791 ir_node *call_res_new;
3792 ir_node *call_res_pred = NULL;
3794 if (call_res != NULL) {
3795 call_res_new = be_transform_node(call_res);
3796 call_res_pred = get_Proj_pred(call_res_new);
3799 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3800 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3802 assert(is_ia32_xLoad(call_res_pred));
3803 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3806 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3808 ir_node *frame = get_irg_frame(irg);
3809 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3811 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3813 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3814 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3816 /* store st(0) onto stack */
3817 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3819 set_ia32_ls_mode(fstp, mode);
3820 set_ia32_op_type(fstp, ia32_AddrModeD);
3821 set_ia32_use_frame(fstp);
3822 set_ia32_am_flavour(fstp, ia32_am_B);
3824 /* load into SSE register */
3825 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3826 set_ia32_ls_mode(sse_load, mode);
3827 set_ia32_op_type(sse_load, ia32_AddrModeS);
3828 set_ia32_use_frame(sse_load);
3829 set_ia32_am_flavour(sse_load, ia32_am_B);
3831 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3833 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3835 /* get a Proj representing a caller save register */
3836 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3837 assert(is_Proj(p) && "Proj expected.");
3839 /* user of the the proj is the Keep */
3840 p = get_edge_src_irn(get_irn_out_edge_first(p));
3841 assert(be_is_Keep(p) && "Keep expected.");
3846 /* transform call modes */
3847 if (mode_is_data(mode)) {
3848 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3852 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3856 * Transform the Projs from a Cmp.
3858 static ir_node *gen_Proj_Cmp(ir_node *node)
3860 /* normally Cmps are processed when looking at Cond nodes, but this case
3861 * can happen in complicated Psi conditions */
3863 ir_node *cmp = get_Proj_pred(node);
3864 long pnc = get_Proj_proj(node);
3865 ir_node *cmp_left = get_Cmp_left(cmp);
3866 ir_node *cmp_right = get_Cmp_right(cmp);
3867 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3868 dbg_info *dbgi = get_irn_dbg_info(cmp);
3869 ir_node *block = be_transform_node(get_nodes_block(node));
3872 assert(!mode_is_float(cmp_mode));
3874 if(!mode_is_signed(cmp_mode)) {
3875 pnc |= ia32_pn_Cmp_Unsigned;
3878 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3879 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3885 * Transform and potentially renumber Proj nodes.
3887 static ir_node *gen_Proj(ir_node *node) {
3888 ir_graph *irg = current_ir_graph;
3889 dbg_info *dbgi = get_irn_dbg_info(node);
3890 ir_node *pred = get_Proj_pred(node);
3891 long proj = get_Proj_proj(node);
3893 if (is_Store(pred) || be_is_FrameStore(pred)) {
3894 if (proj == pn_Store_M) {
3895 return be_transform_node(pred);
3898 return new_r_Bad(irg);
3900 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3901 return gen_Proj_Load(node);
3902 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3903 return gen_Proj_DivMod(node);
3904 } else if (is_CopyB(pred)) {
3905 return gen_Proj_CopyB(node);
3906 } else if (is_Quot(pred)) {
3907 return gen_Proj_Quot(node);
3908 } else if (is_ia32_l_vfdiv(pred)) {
3909 return gen_Proj_l_vfdiv(node);
3910 } else if (be_is_SubSP(pred)) {
3911 return gen_Proj_be_SubSP(node);
3912 } else if (be_is_AddSP(pred)) {
3913 return gen_Proj_be_AddSP(node);
3914 } else if (be_is_Call(pred)) {
3915 return gen_Proj_be_Call(node);
3916 } else if (is_Cmp(pred)) {
3917 return gen_Proj_Cmp(node);
3918 } else if (get_irn_op(pred) == op_Start) {
3919 if (proj == pn_Start_X_initial_exec) {
3920 ir_node *block = get_nodes_block(pred);
3923 /* we exchange the ProjX with a jump */
3924 block = be_transform_node(block);
3925 jump = new_rd_Jmp(dbgi, irg, block);
3928 if (node == get_irg_anchor(irg, anchor_tls)) {
3929 return gen_Proj_tls(node);
3932 ir_node *new_pred = be_transform_node(pred);
3933 ir_node *block = be_transform_node(get_nodes_block(node));
3934 ir_mode *mode = get_irn_mode(node);
3935 if (mode_needs_gp_reg(mode)) {
3936 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3937 get_Proj_proj(node));
3938 #ifdef DEBUG_libfirm
3939 new_proj->node_nr = node->node_nr;
3945 return be_duplicate_node(node);
3949 * Enters all transform functions into the generic pointer
3951 static void register_transformers(void)
3955 /* first clear the generic function pointer for all ops */
3956 clear_irp_opcodes_generic_func();
3958 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3959 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3995 /* transform ops from intrinsic lowering */
4015 /* GEN(ia32_l_vfist); TODO */
4017 GEN(ia32_l_X87toSSE);
4018 GEN(ia32_l_SSEtoX87);
4023 /* we should never see these nodes */
4038 /* handle generic backend nodes */
4049 /* set the register for all Unknown nodes */
4052 op_Mulh = get_op_Mulh();
4061 * Pre-transform all unknown and noreg nodes.
4063 static void ia32_pretransform_node(void *arch_cg) {
4064 ia32_code_gen_t *cg = arch_cg;
4066 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4067 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4068 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4069 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4070 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4071 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4075 void add_missing_keep_walker(ir_node *node, void *data)
4078 unsigned found_projs = 0;
4079 const ir_edge_t *edge;
4080 ir_mode *mode = get_irn_mode(node);
4085 if(!is_ia32_irn(node))
4088 n_outs = get_ia32_n_res(node);
4091 if(is_ia32_SwitchJmp(node))
4094 assert(n_outs < (int) sizeof(unsigned) * 8);
4095 foreach_out_edge(node, edge) {
4096 ir_node *proj = get_edge_src_irn(edge);
4097 int pn = get_Proj_proj(proj);
4099 assert(pn < n_outs);
4100 found_projs |= 1 << pn;
4104 /* are keeps missing? */
4106 for(i = 0; i < n_outs; ++i) {
4109 const arch_register_req_t *req;
4110 const arch_register_class_t *class;
4112 if(found_projs & (1 << i)) {
4116 req = get_ia32_out_req(node, i);
4122 block = get_nodes_block(node);
4123 in[0] = new_r_Proj(current_ir_graph, block, node,
4124 arch_register_class_mode(class), i);
4125 if(last_keep != NULL) {
4126 be_Keep_add_node(last_keep, class, in[0]);
4128 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4134 * Adds missing keeps to nodes
4137 void add_missing_keeps(ia32_code_gen_t *cg)
4139 ir_graph *irg = be_get_birg_irg(cg->birg);
4140 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4143 /* do the transformation */
4144 void ia32_transform_graph(ia32_code_gen_t *cg) {
4145 register_transformers();
4147 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4148 edges_verify(cg->irg);
4149 add_missing_keeps(cg);
4150 edges_verify(cg->irg);
4153 void ia32_init_transform(void)
4155 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");