2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
113 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
116 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 ir_node *op1, ir_node *op2, ir_node *fpcw);
120 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *op);
123 /****************************************************************************************************
125 * | | | | / _| | | (_)
126 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
127 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
128 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
129 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
131 ****************************************************************************************************/
133 static ir_node *try_create_Immediate(ir_node *node,
134 char immediate_constraint_type);
136 static ir_node *create_immediate_or_transform(ir_node *node,
137 char immediate_constraint_type);
139 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
140 dbg_info *dbgi, ir_node *block,
141 ir_node *op, ir_node *orig_node);
144 * Return true if a mode can be stored in the GP register set
146 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
147 if(mode == mode_fpcw)
149 if(get_mode_size_bits(mode) > 32)
151 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
155 * creates a unique ident by adding a number to a tag
157 * @param tag the tag string, must contain a %d if a number
160 static ident *unique_id(const char *tag)
162 static unsigned id = 0;
165 snprintf(str, sizeof(str), tag, ++id);
166 return new_id_from_str(str);
170 * Get a primitive type for a mode.
172 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
174 pmap_entry *e = pmap_find(types, mode);
179 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
180 res = new_type_primitive(new_id_from_str(buf), mode);
181 set_type_alignment_bytes(res, 16);
182 pmap_insert(types, mode, res);
190 * Get an atomic entity that is initialized with a tarval
192 static ir_entity *create_float_const_entity(ir_node *cnst)
194 ia32_isa_t *isa = env_cg->isa;
195 tarval *tv = get_Const_tarval(cnst);
196 pmap_entry *e = pmap_find(isa->tv_ent, tv);
201 ir_mode *mode = get_irn_mode(cnst);
202 ir_type *tp = get_Const_type(cnst);
203 if (tp == firm_unknown_type)
204 tp = get_prim_type(isa->types, mode);
206 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
208 set_entity_ld_ident(res, get_entity_ident(res));
209 set_entity_visibility(res, visibility_local);
210 set_entity_variability(res, variability_constant);
211 set_entity_allocation(res, allocation_static);
213 /* we create a new entity here: It's initialization must resist on the
215 rem = current_ir_graph;
216 current_ir_graph = get_const_code_irg();
217 set_atomic_ent_value(res, new_Const_type(tv, tp));
218 current_ir_graph = rem;
220 pmap_insert(isa->tv_ent, tv, res);
228 static int is_Const_0(ir_node *node) {
229 return is_Const(node) && is_Const_null(node);
232 static int is_Const_1(ir_node *node) {
233 return is_Const(node) && is_Const_one(node);
236 static int is_Const_Minus_1(ir_node *node) {
237 return is_Const(node) && is_Const_all_one(node);
241 * returns true if constant can be created with a simple float command
243 static int is_simple_x87_Const(ir_node *node)
245 tarval *tv = get_Const_tarval(node);
247 if(tarval_is_null(tv) || tarval_is_one(tv))
250 /* TODO: match all the other float constants */
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
271 if (USE_SSE2(env_cg)) {
272 if (is_Const_null(node)) {
273 load = new_rd_ia32_xZero(dbgi, irg, block);
274 set_ia32_ls_mode(load, mode);
277 floatent = create_float_const_entity(node);
279 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
287 if (is_Const_null(node)) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (is_Const_one(node)) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = create_float_const_entity(node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_sc(load, floatent);
299 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet.
309 * So add a dependency to the initial frame pointer calculation to
310 * avoid that situation.
312 if (get_irg_start_block(irg) == block) {
313 add_irn_dep(load, get_irg_frame(irg));
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 tarval *tv = get_Const_tarval(node);
323 tv = tarval_convert_to(tv, mode_Iu);
325 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
327 panic("couldn't convert constant tarval (%+F)", node);
329 val = get_tarval_long(tv);
331 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
332 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *old_block = get_nodes_block(node);
349 ir_node *block = be_transform_node(old_block);
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
356 ir_node *nomem = new_NoMem();
358 if (USE_SSE2(env_cg))
359 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
361 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 set_ia32_am_sc(cnst, get_SymConst_entity(node));
363 set_ia32_use_frame(cnst);
367 if(get_SymConst_kind(node) != symconst_addr_ent) {
368 panic("backend only support symconst_addr_ent (at %+F)", node);
370 entity = get_SymConst_entity(node);
371 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
374 /* Const Nodes before the initial IncSP are a bad idea, because
375 * they could be spilled and we have no SP ready at that point yet
377 if (get_irg_start_block(irg) == block) {
378 add_irn_dep(cnst, get_irg_frame(irg));
381 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
386 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
387 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
388 static const struct {
390 const char *ent_name;
391 const char *cnst_str;
394 } names [ia32_known_const_max] = {
395 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
396 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
397 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
398 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
399 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
401 static ir_entity *ent_cache[ia32_known_const_max];
403 const char *tp_name, *ent_name, *cnst_str;
411 ent_name = names[kct].ent_name;
412 if (! ent_cache[kct]) {
413 tp_name = names[kct].tp_name;
414 cnst_str = names[kct].cnst_str;
416 switch (names[kct].mode) {
417 case 0: mode = mode_Iu; break;
418 case 1: mode = mode_Lu; break;
419 default: mode = mode_F; break;
421 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
422 tp = new_type_primitive(new_id_from_str(tp_name), mode);
423 /* set the specified alignment */
424 set_type_alignment_bytes(tp, names[kct].align);
426 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
428 set_entity_ld_ident(ent, get_entity_ident(ent));
429 set_entity_visibility(ent, visibility_local);
430 set_entity_variability(ent, variability_constant);
431 set_entity_allocation(ent, allocation_static);
433 /* we create a new entity here: It's initialization must resist on the
435 rem = current_ir_graph;
436 current_ir_graph = get_const_code_irg();
437 cnst = new_Const(mode, tv);
438 current_ir_graph = rem;
440 set_atomic_ent_value(ent, cnst);
442 /* cache the entry */
443 ent_cache[kct] = ent;
446 return ent_cache[kct];
451 * Prints the old node name on cg obst and returns a pointer to it.
453 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
454 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
456 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
457 obstack_1grow(isa->name_obst, 0);
458 return obstack_finish(isa->name_obst);
462 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
464 ir_mode *mode = get_irn_mode(node);
468 /* float constants are always available */
469 if(is_Const(node) && mode_is_float(mode)
470 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
476 load = get_Proj_pred(node);
477 pn = get_Proj_proj(node);
478 if(!is_Load(load) || pn != pn_Load_res)
480 if(get_nodes_block(load) != block)
482 /* we only use address mode if we're the only user of the load */
483 if(get_irn_n_edges(node) > 1)
486 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
489 /* don't do AM if other node inputs depend on the load (via mem-proj) */
490 if(other != NULL && get_nodes_block(other) == block
491 && heights_reachable_in_block(heights, other, load))
497 typedef struct ia32_address_mode_t ia32_address_mode_t;
498 struct ia32_address_mode_t {
502 ia32_op_type_t op_type;
509 static void build_address(ia32_address_mode_t *am, ir_node *node)
511 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
512 ia32_address_t *addr = &am->addr;
521 ir_entity *entity = create_float_const_entity(node);
522 addr->base = noreg_gp;
523 addr->index = noreg_gp;
524 addr->mem = new_NoMem();
525 addr->symconst_ent = entity;
527 am->ls_mode = get_irn_mode(node);
531 load = get_Proj_pred(node);
532 ptr = get_Load_ptr(load);
533 mem = get_Load_mem(load);
534 new_mem = be_transform_node(mem);
535 am->ls_mode = get_Load_mode(load);
536 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
538 /* construct load address */
539 ia32_create_address_mode(addr, ptr, 0);
546 base = be_transform_node(base);
552 index = be_transform_node(index);
560 static void set_address(ir_node *node, ia32_address_t *addr)
562 set_ia32_am_scale(node, addr->scale);
563 set_ia32_am_sc(node, addr->symconst_ent);
564 set_ia32_am_offs_int(node, addr->offset);
565 if(addr->symconst_sign)
566 set_ia32_am_sc_sign(node);
568 set_ia32_use_frame(node);
569 set_ia32_frame_ent(node, addr->frame_entity);
572 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
574 set_address(node, &am->addr);
576 set_ia32_op_type(node, am->op_type);
577 set_ia32_ls_mode(node, am->ls_mode);
579 set_ia32_commutative(node);
583 match_commutative = 1 << 0,
584 match_am_and_immediates = 1 << 1,
585 match_no_am = 1 << 2,
586 match_8_bit_am = 1 << 3,
587 match_16_bit_am = 1 << 4,
588 match_no_immediate = 1 << 5,
589 match_force_32bit_op = 1 << 6
592 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
593 ir_node *op1, ir_node *op2, match_flags_t flags)
595 ia32_address_t *addr = &am->addr;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
599 ir_mode *mode = get_irn_mode(op2);
602 int use_am_and_immediates;
604 int mode_bits = get_mode_size_bits(mode);
606 memset(am, 0, sizeof(am[0]));
608 commutative = (flags & match_commutative) != 0;
609 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
610 use_am = ! (flags & match_no_am);
611 use_immediate = !(flags & match_no_immediate);
614 assert(!commutative || op1 != NULL);
616 if(mode_bits == 8 && !(flags & match_8_bit_am)) {
618 } else if(mode_bits == 16 && !(flags & match_16_bit_am)) {
622 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
623 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
624 build_address(am, op2);
625 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
626 if(mode_is_float(mode)) {
627 new_op2 = ia32_new_NoReg_vfp(env_cg);
631 am->op_type = ia32_AddrModeS;
632 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
633 use_am && use_source_address_mode(block, op1, op2)) {
635 build_address(am, op1);
637 if(mode_is_float(mode)) {
638 noreg = ia32_new_NoReg_vfp(env_cg);
643 if(new_op2 != NULL) {
646 new_op1 = be_transform_node(op2);
650 am->op_type = ia32_AddrModeS;
652 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
654 new_op2 = be_transform_node(op2);
655 am->op_type = ia32_Normal;
656 if(flags & match_force_32bit_op) {
657 am->ls_mode = mode_Iu;
659 am->ls_mode = get_irn_mode(op2);
662 if(addr->base == NULL)
663 addr->base = noreg_gp;
664 if(addr->index == NULL)
665 addr->index = noreg_gp;
666 if(addr->mem == NULL)
667 addr->mem = new_NoMem();
669 am->new_op1 = new_op1;
670 am->new_op2 = new_op2;
671 am->commutative = commutative;
674 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
676 ir_graph *irg = current_ir_graph;
680 if(am->mem_proj == NULL)
683 /* we have to create a mode_T so the old MemProj can attach to us */
684 mode = get_irn_mode(node);
685 load = get_Proj_pred(am->mem_proj);
687 mark_irn_visited(load);
688 be_set_transformed_node(load, node);
691 set_irn_mode(node, mode_T);
692 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
699 * Construct a standard binary operation, set AM and immediate if required.
701 * @param op1 The first operand
702 * @param op2 The second operand
703 * @param func The node constructor function
704 * @return The constructed ia32 node.
706 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
707 construct_binop_func *func, match_flags_t flags)
709 ir_node *block = get_nodes_block(node);
710 ir_node *new_block = be_transform_node(block);
711 ir_graph *irg = current_ir_graph;
712 dbg_info *dbgi = get_irn_dbg_info(node);
714 ia32_address_mode_t am;
715 ia32_address_t *addr = &am.addr;
717 flags |= match_force_32bit_op;
719 match_arguments(&am, block, op1, op2, flags);
721 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
722 am.new_op1, am.new_op2);
723 set_am_attributes(new_node, &am);
724 /* we can't use source address mode anymore when using immediates */
725 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
726 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
727 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
729 new_node = fix_mem_proj(new_node, &am);
735 * Construct a standard binary operation, set AM and immediate if required.
737 * @param op1 The first operand
738 * @param op2 The second operand
739 * @param func The node constructor function
740 * @return The constructed ia32 node.
742 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
743 construct_binop_func *func,
746 ir_node *block = get_nodes_block(node);
747 ir_node *new_block = be_transform_node(block);
748 dbg_info *dbgi = get_irn_dbg_info(node);
749 ir_graph *irg = current_ir_graph;
751 ia32_address_mode_t am;
752 ia32_address_t *addr = &am.addr;
754 match_arguments(&am, block, op1, op2, flags);
756 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
757 am.new_op1, am.new_op2);
758 set_am_attributes(new_node, &am);
760 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
762 new_node = fix_mem_proj(new_node, &am);
767 static ir_node *get_fpcw(void)
770 if(initial_fpcw != NULL)
773 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
774 &ia32_fp_cw_regs[REG_FPCW]);
775 initial_fpcw = be_transform_node(fpcw);
781 * Construct a standard binary operation, set AM and immediate if required.
783 * @param op1 The first operand
784 * @param op2 The second operand
785 * @param func The node constructor function
786 * @return The constructed ia32 node.
788 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
789 construct_binop_float_func *func,
792 ir_graph *irg = current_ir_graph;
793 dbg_info *dbgi = get_irn_dbg_info(node);
794 ir_node *block = get_nodes_block(node);
795 ir_node *new_block = be_transform_node(block);
797 ia32_address_mode_t am;
798 ia32_address_t *addr = &am.addr;
800 match_arguments(&am, block, op1, op2, flags);
802 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
803 am.new_op1, am.new_op2, get_fpcw());
804 set_am_attributes(new_node, &am);
806 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
808 new_node = fix_mem_proj(new_node, &am);
814 * Construct a shift/rotate binary operation, sets AM and immediate if required.
816 * @param op1 The first operand
817 * @param op2 The second operand
818 * @param func The node constructor function
819 * @return The constructed ia32 node.
821 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
822 construct_shift_func *func)
824 dbg_info *dbgi = get_irn_dbg_info(node);
825 ir_graph *irg = current_ir_graph;
826 ir_node *block = get_nodes_block(node);
827 ir_node *new_block = be_transform_node(block);
828 ir_node *new_op1 = be_transform_node(op1);
829 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
832 assert(! mode_is_float(get_irn_mode(node))
833 && "Shift/Rotate with float not supported");
835 res = func(dbgi, irg, new_block, new_op1, new_op2);
836 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
838 /* lowered shift instruction may have a dependency operand, handle it here */
839 if (get_irn_arity(node) == 3) {
840 /* we have a dependency */
841 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
842 add_irn_dep(res, new_dep);
850 * Construct a standard unary operation, set AM and immediate if required.
852 * @param op The operand
853 * @param func The node constructor function
854 * @return The constructed ia32 node.
856 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
858 ir_node *block = be_transform_node(get_nodes_block(node));
859 ir_node *new_op = be_transform_node(op);
860 ir_node *new_node = NULL;
861 ir_graph *irg = current_ir_graph;
862 dbg_info *dbgi = get_irn_dbg_info(node);
864 new_node = func(dbgi, irg, block, new_op);
866 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
871 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
872 ia32_address_t *addr)
874 ir_graph *irg = current_ir_graph;
875 ir_node *base = addr->base;
876 ir_node *index = addr->index;
880 base = ia32_new_NoReg_gp(env_cg);
882 base = be_transform_node(base);
886 index = ia32_new_NoReg_gp(env_cg);
888 index = be_transform_node(index);
891 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
892 set_address(res, addr);
897 static int am_has_immediates(const ia32_address_t *addr)
899 return addr->offset != 0 || addr->symconst_ent != NULL
900 || addr->frame_entity || addr->use_frame;
904 * Creates an ia32 Add.
906 * @return the created ia32 Add node
908 static ir_node *gen_Add(ir_node *node) {
909 ir_graph *irg = current_ir_graph;
910 dbg_info *dbgi = get_irn_dbg_info(node);
911 ir_node *block = get_nodes_block(node);
912 ir_node *new_block = be_transform_node(block);
913 ir_node *op1 = get_Add_left(node);
914 ir_node *op2 = get_Add_right(node);
915 ir_mode *mode = get_irn_mode(node);
916 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
919 ir_node *add_immediate_op;
921 ia32_address_mode_t am;
923 if (mode_is_float(mode)) {
924 if (USE_SSE2(env_cg))
925 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, match_commutative);
927 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, match_commutative);
932 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
933 * 1. Add with immediate -> Lea
934 * 2. Add with possible source address mode -> Add
935 * 3. Otherwise -> Lea
937 memset(&addr, 0, sizeof(addr));
938 ia32_create_address_mode(&addr, node, 1);
939 add_immediate_op = NULL;
941 if(addr.base == NULL && addr.index == NULL) {
942 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
943 addr.symconst_sign, addr.offset);
944 add_irn_dep(new_node, get_irg_frame(irg));
945 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
948 /* add with immediate? */
949 if(addr.index == NULL) {
950 add_immediate_op = addr.base;
951 } else if(addr.base == NULL && addr.scale == 0) {
952 add_immediate_op = addr.index;
955 if(add_immediate_op != NULL) {
956 if(!am_has_immediates(&addr)) {
958 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
961 return be_transform_node(add_immediate_op);
964 new_node = create_lea_from_address(dbgi, new_block, &addr);
965 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
969 /* test if we can use source address mode */
970 memset(&am, 0, sizeof(am));
972 if(use_source_address_mode(block, op2, op1)) {
973 build_address(&am, op2);
974 new_op1 = be_transform_node(op1);
975 } else if(use_source_address_mode(block, op1, op2)) {
976 build_address(&am, op1);
977 new_op1 = be_transform_node(op2);
979 /* construct an Add with source address mode */
980 if(new_op1 != NULL) {
981 ia32_address_t *am_addr = &am.addr;
982 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
983 am_addr->index, am_addr->mem, new_op1, noreg);
984 set_address(new_node, am_addr);
985 set_ia32_op_type(new_node, ia32_AddrModeS);
986 set_ia32_ls_mode(new_node, am.ls_mode);
987 set_ia32_commutative(new_node);
988 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
990 new_node = fix_mem_proj(new_node, &am);
995 /* otherwise construct a lea */
996 new_node = create_lea_from_address(dbgi, new_block, &addr);
997 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1002 * Creates an ia32 Mul.
1004 * @return the created ia32 Mul node
1006 static ir_node *gen_Mul(ir_node *node) {
1007 ir_node *op1 = get_Mul_left(node);
1008 ir_node *op2 = get_Mul_right(node);
1009 ir_mode *mode = get_irn_mode(node);
1011 if (mode_is_float(mode)) {
1012 if (USE_SSE2(env_cg))
1013 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, match_commutative);
1015 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, match_commutative);
1019 for the lower 32bit of the result it doesn't matter whether we use
1020 signed or unsigned multiplication so we use IMul as it has fewer
1023 return gen_binop(node, op1, op2, new_rd_ia32_IMul, match_commutative);
1027 * Creates an ia32 Mulh.
1028 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1029 * this result while Mul returns the lower 32 bit.
1031 * @return the created ia32 Mulh node
1033 static ir_node *gen_Mulh(ir_node *node) {
1034 ir_node *block = be_transform_node(get_nodes_block(node));
1035 ir_node *op1 = get_irn_n(node, 0);
1036 ir_node *new_op1 = be_transform_node(op1);
1037 ir_node *op2 = get_irn_n(node, 1);
1038 ir_node *new_op2 = be_transform_node(op2);
1039 ir_graph *irg = current_ir_graph;
1040 dbg_info *dbgi = get_irn_dbg_info(node);
1041 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1042 ir_mode *mode = get_irn_mode(node);
1043 ir_node *proj_EDX, *res;
1045 assert(!mode_is_float(mode) && "Mulh with float not supported");
1046 if (mode_is_signed(mode)) {
1047 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1050 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1054 set_ia32_commutative(res);
1056 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_IMul1OP_EDX);
1064 * Creates an ia32 And.
1066 * @return The created ia32 And node
1068 static ir_node *gen_And(ir_node *node) {
1069 ir_node *op1 = get_And_left(node);
1070 ir_node *op2 = get_And_right(node);
1071 assert(! mode_is_float(get_irn_mode(node)));
1073 /* is it a zero extension? */
1074 if (is_Const(op2)) {
1075 tarval *tv = get_Const_tarval(op2);
1076 long v = get_tarval_long(tv);
1078 if (v == 0xFF || v == 0xFFFF) {
1079 dbg_info *dbgi = get_irn_dbg_info(node);
1080 ir_node *block = get_nodes_block(node);
1087 assert(v == 0xFFFF);
1090 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1096 return gen_binop(node, op1, op2, new_rd_ia32_And, match_commutative);
1102 * Creates an ia32 Or.
1104 * @return The created ia32 Or node
1106 static ir_node *gen_Or(ir_node *node) {
1107 ir_node *op1 = get_Or_left(node);
1108 ir_node *op2 = get_Or_right(node);
1110 assert (! mode_is_float(get_irn_mode(node)));
1111 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative);
1117 * Creates an ia32 Eor.
1119 * @return The created ia32 Eor node
1121 static ir_node *gen_Eor(ir_node *node) {
1122 ir_node *op1 = get_Eor_left(node);
1123 ir_node *op2 = get_Eor_right(node);
1125 assert(! mode_is_float(get_irn_mode(node)));
1126 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative);
1131 * Creates an ia32 Sub.
1133 * @return The created ia32 Sub node
1135 static ir_node *gen_Sub(ir_node *node) {
1136 ir_node *op1 = get_Sub_left(node);
1137 ir_node *op2 = get_Sub_right(node);
1138 ir_mode *mode = get_irn_mode(node);
1140 if (mode_is_float(mode)) {
1141 if (USE_SSE2(env_cg))
1142 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1144 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1148 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1152 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1155 typedef enum { flavour_Div = 1, flavour_Mod, flavour_DivMod } ia32_op_flavour_t;
1158 * Generates an ia32 DivMod with additional infrastructure for the
1159 * register allocator if needed.
1161 * @param dividend -no comment- :)
1162 * @param divisor -no comment- :)
1163 * @param dm_flav flavour_Div/Mod/DivMod
1164 * @return The created ia32 DivMod node
1166 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1167 ir_node *divisor, ia32_op_flavour_t dm_flav)
1169 ir_node *block = be_transform_node(get_nodes_block(node));
1170 ir_node *new_dividend = be_transform_node(dividend);
1171 ir_node *new_divisor = be_transform_node(divisor);
1172 ir_graph *irg = current_ir_graph;
1173 dbg_info *dbgi = get_irn_dbg_info(node);
1174 ir_mode *mode = get_irn_mode(node);
1175 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1176 ir_node *res, *proj_div, *proj_mod;
1177 ir_node *sign_extension;
1178 ir_node *mem, *new_mem;
1181 proj_div = proj_mod = NULL;
1185 mem = get_Div_mem(node);
1186 mode = get_Div_resmode(node);
1187 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1188 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1191 mem = get_Mod_mem(node);
1192 mode = get_Mod_resmode(node);
1193 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1194 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1196 case flavour_DivMod:
1197 mem = get_DivMod_mem(node);
1198 mode = get_DivMod_resmode(node);
1199 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1200 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1201 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1204 panic("invalid divmod flavour!");
1206 new_mem = be_transform_node(mem);
1208 if (mode_is_signed(mode)) {
1209 /* in signed mode, we need to sign extend the dividend */
1210 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1211 add_irn_dep(produceval, get_irg_frame(irg));
1212 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1215 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1216 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1217 add_irn_dep(sign_extension, get_irg_frame(irg));
1220 if (mode_is_signed(mode)) {
1221 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1222 new_dividend, sign_extension, new_divisor);
1224 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem,
1225 new_dividend, sign_extension, new_divisor);
1228 set_ia32_exc_label(res, has_exc);
1229 set_irn_pinned(res, get_irn_pinned(node));
1231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1238 * Wrapper for generate_DivMod. Sets flavour_Mod.
1241 static ir_node *gen_Mod(ir_node *node) {
1242 return generate_DivMod(node, get_Mod_left(node),
1243 get_Mod_right(node), flavour_Mod);
1247 * Wrapper for generate_DivMod. Sets flavour_Div.
1250 static ir_node *gen_Div(ir_node *node) {
1251 return generate_DivMod(node, get_Div_left(node),
1252 get_Div_right(node), flavour_Div);
1256 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1258 static ir_node *gen_DivMod(ir_node *node) {
1259 return generate_DivMod(node, get_DivMod_left(node),
1260 get_DivMod_right(node), flavour_DivMod);
1266 * Creates an ia32 floating Div.
1268 * @return The created ia32 xDiv node
1270 static ir_node *gen_Quot(ir_node *node)
1272 ir_node *op1 = get_Quot_left(node);
1273 ir_node *op2 = get_Quot_right(node);
1275 if (USE_SSE2(env_cg)) {
1276 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1278 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1284 * Creates an ia32 Shl.
1286 * @return The created ia32 Shl node
1288 static ir_node *gen_Shl(ir_node *node) {
1289 ir_node *right = get_Shl_right(node);
1291 /* test whether we can build a lea */
1292 if(is_Const(right)) {
1293 tarval *tv = get_Const_tarval(right);
1294 if(tarval_is_long(tv)) {
1295 long val = get_tarval_long(tv);
1296 if(val >= 0 && val <= 3) {
1297 ir_graph *irg = current_ir_graph;
1298 dbg_info *dbgi = get_irn_dbg_info(node);
1299 ir_node *block = be_transform_node(get_nodes_block(node));
1300 ir_node *base = ia32_new_NoReg_gp(env_cg);
1301 ir_node *index = be_transform_node(get_Shl_left(node));
1302 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1303 set_ia32_am_scale(res, val);
1304 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1310 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1317 * Creates an ia32 Shr.
1319 * @return The created ia32 Shr node
1321 static ir_node *gen_Shr(ir_node *node) {
1322 return gen_shift_binop(node, get_Shr_left(node),
1323 get_Shr_right(node), new_rd_ia32_Shr);
1329 * Creates an ia32 Sar.
1331 * @return The created ia32 Shrs node
1333 static ir_node *gen_Shrs(ir_node *node) {
1334 ir_node *left = get_Shrs_left(node);
1335 ir_node *right = get_Shrs_right(node);
1336 ir_mode *mode = get_irn_mode(node);
1337 if(is_Const(right) && mode == mode_Is) {
1338 tarval *tv = get_Const_tarval(right);
1339 long val = get_tarval_long(tv);
1341 /* this is a sign extension */
1342 ir_graph *irg = current_ir_graph;
1343 dbg_info *dbgi = get_irn_dbg_info(node);
1344 ir_node *block = be_transform_node(get_nodes_block(node));
1346 ir_node *new_op = be_transform_node(op);
1347 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1348 add_irn_dep(pval, get_irg_frame(irg));
1350 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1354 /* 8 or 16 bit sign extension? */
1355 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1356 ir_node *shl_left = get_Shl_left(left);
1357 ir_node *shl_right = get_Shl_right(left);
1358 if(is_Const(shl_right)) {
1359 tarval *tv1 = get_Const_tarval(right);
1360 tarval *tv2 = get_Const_tarval(shl_right);
1361 if(tv1 == tv2 && tarval_is_long(tv1)) {
1362 long val = get_tarval_long(tv1);
1363 if(val == 16 || val == 24) {
1364 dbg_info *dbgi = get_irn_dbg_info(node);
1365 ir_node *block = get_nodes_block(node);
1375 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1384 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1390 * Creates an ia32 RotL.
1392 * @param op1 The first operator
1393 * @param op2 The second operator
1394 * @return The created ia32 RotL node
1396 static ir_node *gen_RotL(ir_node *node,
1397 ir_node *op1, ir_node *op2) {
1398 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1404 * Creates an ia32 RotR.
1405 * NOTE: There is no RotR with immediate because this would always be a RotL
1406 * "imm-mode_size_bits" which can be pre-calculated.
1408 * @param op1 The first operator
1409 * @param op2 The second operator
1410 * @return The created ia32 RotR node
1412 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1414 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1420 * Creates an ia32 RotR or RotL (depending on the found pattern).
1422 * @return The created ia32 RotL or RotR node
1424 static ir_node *gen_Rot(ir_node *node) {
1425 ir_node *rotate = NULL;
1426 ir_node *op1 = get_Rot_left(node);
1427 ir_node *op2 = get_Rot_right(node);
1429 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1430 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1431 that means we can create a RotR instead of an Add and a RotL */
1433 if (get_irn_op(op2) == op_Add) {
1435 ir_node *left = get_Add_left(add);
1436 ir_node *right = get_Add_right(add);
1437 if (is_Const(right)) {
1438 tarval *tv = get_Const_tarval(right);
1439 ir_mode *mode = get_irn_mode(node);
1440 long bits = get_mode_size_bits(mode);
1442 if (get_irn_op(left) == op_Minus &&
1443 tarval_is_long(tv) &&
1444 get_tarval_long(tv) == bits)
1446 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1447 rotate = gen_RotR(node, op1, get_Minus_op(left));
1452 if (rotate == NULL) {
1453 rotate = gen_RotL(node, op1, op2);
1462 * Transforms a Minus node.
1464 * @return The created ia32 Minus node
1466 static ir_node *gen_Minus(ir_node *node)
1468 ir_node *op = get_Minus_op(node);
1469 ir_node *block = be_transform_node(get_nodes_block(node));
1470 ir_graph *irg = current_ir_graph;
1471 dbg_info *dbgi = get_irn_dbg_info(node);
1472 ir_mode *mode = get_irn_mode(node);
1477 if (mode_is_float(mode)) {
1478 ir_node *new_op = be_transform_node(op);
1479 if (USE_SSE2(env_cg)) {
1480 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1481 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1482 ir_node *nomem = new_rd_NoMem(irg);
1484 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1487 size = get_mode_size_bits(mode);
1488 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1490 set_ia32_am_sc(res, ent);
1491 set_ia32_op_type(res, ia32_AddrModeS);
1492 set_ia32_ls_mode(res, mode);
1494 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1497 res = gen_unop(node, op, new_rd_ia32_Neg);
1500 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1506 * Transforms a Not node.
1508 * @return The created ia32 Not node
1510 static ir_node *gen_Not(ir_node *node) {
1511 ir_node *op = get_Not_op(node);
1512 ir_mode *mode = get_irn_mode(node);
1514 assert(mode != mode_b); /* should be lowered already */
1516 assert (! mode_is_float(get_irn_mode(node)));
1517 return gen_unop(node, op, new_rd_ia32_Not);
1523 * Transforms an Abs node.
1525 * @return The created ia32 Abs node
1527 static ir_node *gen_Abs(ir_node *node)
1529 ir_node *block = be_transform_node(get_nodes_block(node));
1530 ir_node *op = get_Abs_op(node);
1531 ir_node *new_op = be_transform_node(op);
1532 ir_graph *irg = current_ir_graph;
1533 dbg_info *dbgi = get_irn_dbg_info(node);
1534 ir_mode *mode = get_irn_mode(node);
1535 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1536 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1537 ir_node *nomem = new_NoMem();
1542 if (mode_is_float(mode)) {
1543 if (USE_SSE2(env_cg)) {
1544 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1546 size = get_mode_size_bits(mode);
1547 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1549 set_ia32_am_sc(res, ent);
1551 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1553 set_ia32_op_type(res, ia32_AddrModeS);
1554 set_ia32_ls_mode(res, mode);
1556 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1557 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1561 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1562 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1565 add_irn_dep(pval, get_irg_frame(irg));
1566 SET_IA32_ORIG_NODE(sign_extension,
1567 ia32_get_old_node_name(env_cg, node));
1569 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1571 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1573 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1575 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1582 * Transforms a Load.
1584 * @return the created ia32 Load node
1586 static ir_node *gen_Load(ir_node *node) {
1587 ir_node *old_block = get_nodes_block(node);
1588 ir_node *block = be_transform_node(old_block);
1589 ir_node *ptr = get_Load_ptr(node);
1590 ir_node *mem = get_Load_mem(node);
1591 ir_node *new_mem = be_transform_node(mem);
1594 ir_graph *irg = current_ir_graph;
1595 dbg_info *dbgi = get_irn_dbg_info(node);
1596 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1597 ir_mode *mode = get_Load_mode(node);
1600 ia32_address_t addr;
1602 /* construct load address */
1603 memset(&addr, 0, sizeof(addr));
1604 ia32_create_address_mode(&addr, ptr, 0);
1611 base = be_transform_node(base);
1617 index = be_transform_node(index);
1620 if (mode_is_float(mode)) {
1621 if (USE_SSE2(env_cg)) {
1622 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1624 res_mode = mode_xmm;
1626 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1628 res_mode = mode_vfp;
1634 /* create a conv node with address mode for smaller modes */
1635 if(get_mode_size_bits(mode) < 32) {
1636 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1637 new_mem, noreg, mode);
1639 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1644 set_irn_pinned(new_op, get_irn_pinned(node));
1645 set_ia32_op_type(new_op, ia32_AddrModeS);
1646 set_ia32_ls_mode(new_op, mode);
1647 set_address(new_op, &addr);
1649 /* make sure we are scheduled behind the initial IncSP/Barrier
1650 * to avoid spills being placed before it
1652 if (block == get_irg_start_block(irg)) {
1653 add_irn_dep(new_op, get_irg_frame(irg));
1656 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1657 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1662 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1663 ir_node *ptr, ir_mode *mode, ir_node *other)
1670 /* we only use address mode if we're the only user of the load */
1671 if(get_irn_n_edges(node) > 1)
1674 load = get_Proj_pred(node);
1677 if(get_nodes_block(load) != block)
1680 /* Store should be attached to the load */
1681 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1683 /* store should have the same pointer as the load */
1684 if(get_Load_ptr(load) != ptr)
1687 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1688 if(other != NULL && get_nodes_block(other) == block
1689 && heights_reachable_in_block(heights, other, load))
1692 assert(get_Load_mode(load) == mode);
1697 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1698 ir_node *mem, ir_node *ptr, ir_mode *mode,
1699 construct_binop_dest_func *func,
1700 construct_binop_dest_func *func8bit,
1703 ir_node *src_block = get_nodes_block(node);
1705 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1706 ir_graph *irg = current_ir_graph;
1710 ia32_address_mode_t am;
1711 ia32_address_t *addr = &am.addr;
1712 memset(&am, 0, sizeof(am));
1714 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1715 build_address(&am, op1);
1716 new_op = create_immediate_or_transform(op2, 0);
1717 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1718 build_address(&am, op2);
1719 new_op = create_immediate_or_transform(op1, 0);
1724 if(addr->base == NULL)
1725 addr->base = noreg_gp;
1726 if(addr->index == NULL)
1727 addr->index = noreg_gp;
1728 if(addr->mem == NULL)
1729 addr->mem = new_NoMem();
1731 dbgi = get_irn_dbg_info(node);
1732 block = be_transform_node(src_block);
1733 if(get_mode_size_bits(mode) == 8) {
1734 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1737 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1740 set_address(new_node, addr);
1741 set_ia32_op_type(new_node, ia32_AddrModeD);
1742 set_ia32_ls_mode(new_node, mode);
1743 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1748 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1749 ir_node *ptr, ir_mode *mode,
1750 construct_unop_dest_func *func)
1752 ir_node *src_block = get_nodes_block(node);
1754 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1755 ir_graph *irg = current_ir_graph;
1758 ia32_address_mode_t am;
1759 ia32_address_t *addr = &am.addr;
1760 memset(&am, 0, sizeof(am));
1762 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1765 build_address(&am, op);
1767 if(addr->base == NULL)
1768 addr->base = noreg_gp;
1769 if(addr->index == NULL)
1770 addr->index = noreg_gp;
1771 if(addr->mem == NULL)
1772 addr->mem = new_NoMem();
1774 dbgi = get_irn_dbg_info(node);
1775 block = be_transform_node(src_block);
1776 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1777 set_address(new_node, addr);
1778 set_ia32_op_type(new_node, ia32_AddrModeD);
1779 set_ia32_ls_mode(new_node, mode);
1780 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1785 static ir_node *try_create_dest_am(ir_node *node) {
1786 ir_node *val = get_Store_value(node);
1787 ir_node *mem = get_Store_mem(node);
1788 ir_node *ptr = get_Store_ptr(node);
1789 ir_mode *mode = get_irn_mode(val);
1794 /* handle only GP modes for now... */
1795 if(!mode_needs_gp_reg(mode))
1798 /* store must be the only user of the val node */
1799 if(get_irn_n_edges(val) > 1)
1802 switch(get_irn_opcode(val)) {
1804 op1 = get_Add_left(val);
1805 op2 = get_Add_right(val);
1806 if(is_Const_1(op2)) {
1807 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1808 new_rd_ia32_IncMem);
1810 } else if(is_Const_Minus_1(op2)) {
1811 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1812 new_rd_ia32_DecMem);
1815 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1816 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1819 op1 = get_Sub_left(val);
1820 op2 = get_Sub_right(val);
1822 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1825 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1826 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1829 op1 = get_And_left(val);
1830 op2 = get_And_right(val);
1831 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1832 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1835 op1 = get_Or_left(val);
1836 op2 = get_Or_right(val);
1837 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1838 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1841 op1 = get_Eor_left(val);
1842 op2 = get_Eor_right(val);
1843 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1844 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1847 op1 = get_Shl_left(val);
1848 op2 = get_Shl_right(val);
1849 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1850 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1853 op1 = get_Shr_left(val);
1854 op2 = get_Shr_right(val);
1855 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1856 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1859 op1 = get_Shrs_left(val);
1860 op2 = get_Shrs_right(val);
1861 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1862 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1865 op1 = get_Rot_left(val);
1866 op2 = get_Rot_right(val);
1867 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1868 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1870 /* TODO: match ROR patterns... */
1872 op1 = get_Minus_op(val);
1873 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1876 /* should be lowered already */
1877 assert(mode != mode_b);
1878 op1 = get_Not_op(val);
1879 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1889 * Transforms a Store.
1891 * @return the created ia32 Store node
1893 static ir_node *gen_Store(ir_node *node) {
1894 ir_node *block = be_transform_node(get_nodes_block(node));
1895 ir_node *ptr = get_Store_ptr(node);
1898 ir_node *val = get_Store_value(node);
1900 ir_node *mem = get_Store_mem(node);
1901 ir_node *new_mem = be_transform_node(mem);
1902 ir_graph *irg = current_ir_graph;
1903 dbg_info *dbgi = get_irn_dbg_info(node);
1904 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1905 ir_mode *mode = get_irn_mode(val);
1907 ia32_address_t addr;
1909 /* check for destination address mode */
1910 new_op = try_create_dest_am(node);
1914 /* construct store address */
1915 memset(&addr, 0, sizeof(addr));
1916 ia32_create_address_mode(&addr, ptr, 0);
1923 base = be_transform_node(base);
1929 index = be_transform_node(index);
1932 if (mode_is_float(mode)) {
1933 new_val = be_transform_node(val);
1934 if (USE_SSE2(env_cg)) {
1935 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1938 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1942 new_val = create_immediate_or_transform(val, 0);
1946 if (get_mode_size_bits(mode) == 8) {
1947 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1950 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1955 set_irn_pinned(new_op, get_irn_pinned(node));
1956 set_ia32_op_type(new_op, ia32_AddrModeD);
1957 set_ia32_ls_mode(new_op, mode);
1959 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1960 set_address(new_op, &addr);
1961 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1966 static ir_node *create_Switch(ir_node *node)
1968 ir_graph *irg = current_ir_graph;
1969 dbg_info *dbgi = get_irn_dbg_info(node);
1970 ir_node *block = be_transform_node(get_nodes_block(node));
1971 ir_node *sel = get_Cond_selector(node);
1972 ir_node *new_sel = be_transform_node(sel);
1974 int switch_min = INT_MAX;
1975 const ir_edge_t *edge;
1977 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1979 /* determine the smallest switch case value */
1980 foreach_out_edge(node, edge) {
1981 ir_node *proj = get_edge_src_irn(edge);
1982 int pn = get_Proj_proj(proj);
1987 if (switch_min != 0) {
1988 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1990 /* if smallest switch case is not 0 we need an additional sub */
1991 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1992 add_ia32_am_offs_int(new_sel, -switch_min);
1993 set_ia32_op_type(new_sel, ia32_AddrModeS);
1995 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1998 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1999 set_ia32_pncode(res, get_Cond_defaultProj(node));
2001 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2006 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2008 ir_graph *irg = current_ir_graph;
2016 /* we have a Cmp as input */
2018 ir_node *pred = get_Proj_pred(node);
2020 flags = be_transform_node(pred);
2021 *pnc_out = get_Proj_proj(node);
2026 /* a mode_b value, we have to compare it against 0 */
2027 dbgi = get_irn_dbg_info(node);
2028 new_block = be_transform_node(get_nodes_block(node));
2029 new_op = be_transform_node(node);
2030 noreg = ia32_new_NoReg_gp(env_cg);
2031 nomem = new_NoMem();
2032 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2033 new_op, new_op, 0, 0);
2034 *pnc_out = pn_Cmp_Lg;
2038 static ir_node *gen_Cond(ir_node *node) {
2039 ir_node *block = get_nodes_block(node);
2040 ir_node *new_block = be_transform_node(block);
2041 ir_graph *irg = current_ir_graph;
2042 dbg_info *dbgi = get_irn_dbg_info(node);
2043 ir_node *sel = get_Cond_selector(node);
2044 ir_mode *sel_mode = get_irn_mode(sel);
2046 ir_node *flags = NULL;
2049 if (sel_mode != mode_b) {
2050 return create_Switch(node);
2053 /* we get flags from a cmp */
2054 flags = get_flags_node(sel, &pnc);
2056 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2057 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2065 * Transforms a CopyB node.
2067 * @return The transformed node.
2069 static ir_node *gen_CopyB(ir_node *node) {
2070 ir_node *block = be_transform_node(get_nodes_block(node));
2071 ir_node *src = get_CopyB_src(node);
2072 ir_node *new_src = be_transform_node(src);
2073 ir_node *dst = get_CopyB_dst(node);
2074 ir_node *new_dst = be_transform_node(dst);
2075 ir_node *mem = get_CopyB_mem(node);
2076 ir_node *new_mem = be_transform_node(mem);
2077 ir_node *res = NULL;
2078 ir_graph *irg = current_ir_graph;
2079 dbg_info *dbgi = get_irn_dbg_info(node);
2080 int size = get_type_size_bytes(get_CopyB_type(node));
2083 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2084 /* then we need the size explicitly in ECX. */
2085 if (size >= 32 * 4) {
2086 rem = size & 0x3; /* size % 4 */
2089 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2091 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2093 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2095 add_irn_dep(res, get_irg_frame(irg));
2097 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2098 /* we misuse the pncode field for the copyb size */
2099 set_ia32_pncode(res, rem);
2101 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2102 set_ia32_pncode(res, size);
2105 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2110 static ir_node *gen_be_Copy(ir_node *node)
2112 ir_node *result = be_duplicate_node(node);
2113 ir_mode *mode = get_irn_mode(result);
2115 if (mode_needs_gp_reg(mode)) {
2116 set_irn_mode(result, mode_Iu);
2123 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2124 * to fold an and into a test node
2126 static int can_fold_test_and(ir_node *node)
2128 const ir_edge_t *edge;
2130 /** we can only have eq and lg projs */
2131 foreach_out_edge(node, edge) {
2132 ir_node *proj = get_edge_src_irn(edge);
2133 pn_Cmp pnc = get_Proj_proj(proj);
2134 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2141 static ir_node *try_create_Test(ir_node *node)
2143 ir_graph *irg = current_ir_graph;
2144 dbg_info *dbgi = get_irn_dbg_info(node);
2145 ir_node *block = get_nodes_block(node);
2146 ir_node *new_block = be_transform_node(block);
2147 ir_node *cmp_left = get_Cmp_left(node);
2148 ir_node *cmp_right = get_Cmp_right(node);
2153 ia32_address_mode_t am;
2154 ia32_address_t *addr = &am.addr;
2157 /* can we use a test instruction? */
2158 if(!is_Const_0(cmp_right))
2161 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2162 can_fold_test_and(node)) {
2163 ir_node *and_left = get_And_left(cmp_left);
2164 ir_node *and_right = get_And_right(cmp_left);
2166 mode = get_irn_mode(and_left);
2170 mode = get_irn_mode(cmp_left);
2175 assert(get_mode_size_bits(mode) <= 32);
2177 match_arguments(&am, block, left, right, match_commutative |
2178 match_8_bit_am | match_16_bit_am | match_am_and_immediates);
2180 cmp_unsigned = !mode_is_signed(mode);
2181 if(get_mode_size_bits(mode) == 8) {
2182 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2183 addr->index, addr->mem, am.new_op1,
2184 am.new_op2, am.flipped, cmp_unsigned);
2186 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2187 addr->mem, am.new_op1, am.new_op2, am.flipped,
2190 set_am_attributes(res, &am);
2191 assert(mode != NULL);
2192 set_ia32_ls_mode(res, mode);
2194 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2196 res = fix_mem_proj(res, &am);
2200 static ir_node *create_Fucom(ir_node *node)
2202 ir_graph *irg = current_ir_graph;
2203 dbg_info *dbgi = get_irn_dbg_info(node);
2204 ir_node *block = get_nodes_block(node);
2205 ir_node *new_block = be_transform_node(block);
2206 ir_node *left = get_Cmp_left(node);
2207 ir_node *new_left = be_transform_node(left);
2208 ir_node *right = get_Cmp_right(node);
2212 if(transform_config.use_fucomi) {
2213 new_right = be_transform_node(right);
2214 res = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left, new_right, 0);
2215 set_ia32_commutative(res);
2216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2218 if(transform_config.use_ftst && is_Const_null(right)) {
2219 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2221 new_right = be_transform_node(right);
2222 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2226 set_ia32_commutative(res);
2228 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2230 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2231 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2237 static ir_node *create_Ucomi(ir_node *node)
2239 ir_graph *irg = current_ir_graph;
2240 dbg_info *dbgi = get_irn_dbg_info(node);
2241 ir_node *src_block = get_nodes_block(node);
2242 ir_node *new_block = be_transform_node(src_block);
2243 ir_node *left = get_Cmp_left(node);
2244 ir_node *right = get_Cmp_right(node);
2246 ia32_address_mode_t am;
2247 ia32_address_t *addr = &am.addr;
2249 match_arguments(&am, src_block, left, right, match_commutative);
2251 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2252 addr->mem, am.new_op1, am.new_op2, am.flipped);
2253 set_am_attributes(new_node, &am);
2255 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2257 new_node = fix_mem_proj(new_node, &am);
2262 static ir_node *gen_Cmp(ir_node *node)
2264 ir_graph *irg = current_ir_graph;
2265 dbg_info *dbgi = get_irn_dbg_info(node);
2266 ir_node *block = get_nodes_block(node);
2267 ir_node *new_block = be_transform_node(block);
2268 ir_node *left = get_Cmp_left(node);
2269 ir_node *right = get_Cmp_right(node);
2270 ir_mode *cmp_mode = get_irn_mode(left);
2272 ia32_address_mode_t am;
2273 ia32_address_t *addr = &am.addr;
2276 if(mode_is_float(cmp_mode)) {
2277 if (USE_SSE2(env_cg)) {
2278 return create_Ucomi(node);
2280 return create_Fucom(node);
2284 assert(mode_needs_gp_reg(cmp_mode));
2286 /* we prefer the Test instruction where possible except cases where
2287 * we can use SourceAM */
2288 if(!use_source_address_mode(block, left, right) &&
2289 !use_source_address_mode(block, right, left)) {
2290 res = try_create_Test(node);
2295 match_arguments(&am, block, left, right,
2296 match_commutative | match_8_bit_am | match_16_bit_am |
2297 match_am_and_immediates);
2299 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2300 if(get_mode_size_bits(cmp_mode) == 8) {
2301 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2302 addr->mem, am.new_op1, am.new_op2,
2303 am.flipped, cmp_unsigned);
2305 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2306 addr->mem, am.new_op1, am.new_op2, am.flipped,
2309 set_am_attributes(res, &am);
2310 assert(cmp_mode != NULL);
2311 set_ia32_ls_mode(res, cmp_mode);
2313 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2315 res = fix_mem_proj(res, &am);
2320 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2322 ir_graph *irg = current_ir_graph;
2323 dbg_info *dbgi = get_irn_dbg_info(node);
2324 ir_node *block = get_nodes_block(node);
2325 ir_node *new_block = be_transform_node(block);
2326 ir_node *val_true = get_Psi_val(node, 0);
2327 ir_node *val_false = get_Psi_default(node);
2329 match_flags_t match_flags;
2330 ia32_address_mode_t am;
2331 ia32_address_t *addr;
2333 assert(transform_config.use_cmov);
2334 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2338 match_flags = match_commutative | match_no_immediate | match_16_bit_am
2339 | match_force_32bit_op;
2341 match_arguments(&am, block, val_false, val_true, match_flags);
2343 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2344 addr->mem, am.new_op1, am.new_op2, new_flags,
2346 set_am_attributes(new_node, &am);
2348 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2350 new_node = fix_mem_proj(new_node, &am);
2357 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2358 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2360 ir_graph *irg = current_ir_graph;
2361 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2362 ir_node *nomem = new_NoMem();
2365 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2366 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2367 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2368 nomem, res, mode_Bu);
2369 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2375 * Transforms a Psi node into CMov.
2377 * @return The transformed node.
2379 static ir_node *gen_Psi(ir_node *node)
2381 dbg_info *dbgi = get_irn_dbg_info(node);
2382 ir_node *block = get_nodes_block(node);
2383 ir_node *new_block = be_transform_node(block);
2384 ir_node *psi_true = get_Psi_val(node, 0);
2385 ir_node *psi_default = get_Psi_default(node);
2386 ir_node *cond = get_Psi_cond(node, 0);
2387 ir_node *flags = NULL;
2392 assert(get_Psi_n_conds(node) == 1);
2393 assert(get_irn_mode(cond) == mode_b);
2394 assert(mode_needs_gp_reg(get_irn_mode(node)));
2396 flags = get_flags_node(cond, &pnc);
2398 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2399 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2400 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2401 pnc = get_negated_pnc(pnc, cmp_mode);
2402 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2404 res = create_CMov(node, flags, pnc);
2411 * Create a conversion from x87 state register to general purpose.
2413 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2414 ir_node *block = be_transform_node(get_nodes_block(node));
2415 ir_node *op = get_Conv_op(node);
2416 ir_node *new_op = be_transform_node(op);
2417 ia32_code_gen_t *cg = env_cg;
2418 ir_graph *irg = current_ir_graph;
2419 dbg_info *dbgi = get_irn_dbg_info(node);
2420 ir_node *noreg = ia32_new_NoReg_gp(cg);
2421 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2422 ir_mode *mode = get_irn_mode(node);
2423 ir_node *fist, *load;
2426 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2427 new_NoMem(), new_op, trunc_mode);
2429 set_irn_pinned(fist, op_pin_state_floats);
2430 set_ia32_use_frame(fist);
2431 set_ia32_op_type(fist, ia32_AddrModeD);
2433 assert(get_mode_size_bits(mode) <= 32);
2434 /* exception we can only store signed 32 bit integers, so for unsigned
2435 we store a 64bit (signed) integer and load the lower bits */
2436 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2437 set_ia32_ls_mode(fist, mode_Ls);
2439 set_ia32_ls_mode(fist, mode_Is);
2441 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2444 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2446 set_irn_pinned(load, op_pin_state_floats);
2447 set_ia32_use_frame(load);
2448 set_ia32_op_type(load, ia32_AddrModeS);
2449 set_ia32_ls_mode(load, mode_Is);
2450 if(get_ia32_ls_mode(fist) == mode_Ls) {
2451 ia32_attr_t *attr = get_ia32_attr(load);
2452 attr->data.need_64bit_stackent = 1;
2454 ia32_attr_t *attr = get_ia32_attr(load);
2455 attr->data.need_32bit_stackent = 1;
2457 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2459 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2463 * Creates a x87 strict Conv by placing a Sore and a Load
2465 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2467 ir_node *block = get_nodes_block(node);
2468 ir_graph *irg = current_ir_graph;
2469 dbg_info *dbgi = get_irn_dbg_info(node);
2470 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2471 ir_node *nomem = new_NoMem();
2472 ir_node *frame = get_irg_frame(irg);
2473 ir_node *store, *load;
2476 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2478 set_ia32_use_frame(store);
2479 set_ia32_op_type(store, ia32_AddrModeD);
2480 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2482 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2484 set_ia32_use_frame(load);
2485 set_ia32_op_type(load, ia32_AddrModeS);
2486 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2488 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2492 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2494 ir_graph *irg = current_ir_graph;
2495 ir_node *start_block = get_irg_start_block(irg);
2496 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2497 symconst, symconst_sign, val);
2498 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2504 * Create a conversion from general purpose to x87 register
2506 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2507 ir_node *src_block = get_nodes_block(node);
2508 ir_node *block = be_transform_node(src_block);
2509 ir_graph *irg = current_ir_graph;
2510 dbg_info *dbgi = get_irn_dbg_info(node);
2511 ir_node *op = get_Conv_op(node);
2516 ir_mode *store_mode;
2522 /* fild can use source AM if the operand is a signed 32bit integer */
2523 if (src_mode == mode_Is) {
2524 ia32_address_mode_t am;
2526 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2527 if (am.op_type == ia32_AddrModeS) {
2528 ia32_address_t *addr = &am.addr;
2530 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2531 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2533 set_am_attributes(fild, &am);
2534 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2536 fix_mem_proj(fild, &am);
2540 new_op = am.new_op2;
2542 new_op = be_transform_node(op);
2545 noreg = ia32_new_NoReg_gp(env_cg);
2546 nomem = new_NoMem();
2547 mode = get_irn_mode(op);
2549 /* first convert to 32 bit signed if necessary */
2550 src_bits = get_mode_size_bits(src_mode);
2551 if (src_bits == 8) {
2552 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2554 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2556 } else if (src_bits < 32) {
2557 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2559 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2563 assert(get_mode_size_bits(mode) == 32);
2566 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2569 set_ia32_use_frame(store);
2570 set_ia32_op_type(store, ia32_AddrModeD);
2571 set_ia32_ls_mode(store, mode_Iu);
2573 /* exception for 32bit unsigned, do a 64bit spill+load */
2574 if(!mode_is_signed(mode)) {
2577 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2579 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2580 get_irg_frame(irg), noreg, nomem,
2583 set_ia32_use_frame(zero_store);
2584 set_ia32_op_type(zero_store, ia32_AddrModeD);
2585 add_ia32_am_offs_int(zero_store, 4);
2586 set_ia32_ls_mode(zero_store, mode_Iu);
2591 store = new_rd_Sync(dbgi, irg, block, 2, in);
2592 store_mode = mode_Ls;
2594 store_mode = mode_Is;
2598 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2600 set_ia32_use_frame(fild);
2601 set_ia32_op_type(fild, ia32_AddrModeS);
2602 set_ia32_ls_mode(fild, store_mode);
2604 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2610 * Crete a conversion from one integer mode into another one
2612 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2613 dbg_info *dbgi, ir_node *block, ir_node *op,
2616 ir_graph *irg = current_ir_graph;
2617 int src_bits = get_mode_size_bits(src_mode);
2618 int tgt_bits = get_mode_size_bits(tgt_mode);
2619 ir_node *new_block = be_transform_node(block);
2620 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2623 ir_mode *smaller_mode;
2625 ia32_address_mode_t am;
2626 ia32_address_t *addr = &am.addr;
2628 if (src_bits < tgt_bits) {
2629 smaller_mode = src_mode;
2630 smaller_bits = src_bits;
2632 smaller_mode = tgt_mode;
2633 smaller_bits = tgt_bits;
2636 memset(&am, 0, sizeof(am));
2637 if(use_source_address_mode(block, op, NULL)) {
2638 build_address(&am, op);
2640 am.op_type = ia32_AddrModeS;
2642 new_op = be_transform_node(op);
2643 am.op_type = ia32_Normal;
2645 if(addr->base == NULL)
2647 if(addr->index == NULL)
2648 addr->index = noreg;
2649 if(addr->mem == NULL)
2650 addr->mem = new_NoMem();
2652 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2653 if (smaller_bits == 8) {
2654 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2655 addr->index, addr->mem, new_op,
2658 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2659 addr->index, addr->mem, new_op,
2663 set_am_attributes(res, &am);
2664 set_ia32_ls_mode(res, smaller_mode);
2665 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2666 res = fix_mem_proj(res, &am);
2672 * Transforms a Conv node.
2674 * @return The created ia32 Conv node
2676 static ir_node *gen_Conv(ir_node *node) {
2677 ir_node *block = get_nodes_block(node);
2678 ir_node *new_block = be_transform_node(block);
2679 ir_node *op = get_Conv_op(node);
2680 ir_node *new_op = NULL;
2681 ir_graph *irg = current_ir_graph;
2682 dbg_info *dbgi = get_irn_dbg_info(node);
2683 ir_mode *src_mode = get_irn_mode(op);
2684 ir_mode *tgt_mode = get_irn_mode(node);
2685 int src_bits = get_mode_size_bits(src_mode);
2686 int tgt_bits = get_mode_size_bits(tgt_mode);
2687 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2688 ir_node *nomem = new_rd_NoMem(irg);
2689 ir_node *res = NULL;
2691 if (src_mode == mode_b) {
2692 assert(mode_is_int(tgt_mode));
2693 /* nothing to do, we already model bools as 0/1 ints */
2694 return be_transform_node(op);
2697 if (src_mode == tgt_mode) {
2698 if (get_Conv_strict(node)) {
2699 if (USE_SSE2(env_cg)) {
2700 /* when we are in SSE mode, we can kill all strict no-op conversion */
2701 return be_transform_node(op);
2704 /* this should be optimized already, but who knows... */
2705 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2706 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2707 return be_transform_node(op);
2711 if (mode_is_float(src_mode)) {
2712 new_op = be_transform_node(op);
2713 /* we convert from float ... */
2714 if (mode_is_float(tgt_mode)) {
2715 if(src_mode == mode_E && tgt_mode == mode_D
2716 && !get_Conv_strict(node)) {
2717 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2722 if (USE_SSE2(env_cg)) {
2723 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2724 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2726 set_ia32_ls_mode(res, tgt_mode);
2728 if(get_Conv_strict(node)) {
2729 res = gen_x87_strict_conv(tgt_mode, new_op);
2730 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2733 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2738 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2739 if (USE_SSE2(env_cg)) {
2740 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2742 set_ia32_ls_mode(res, src_mode);
2744 return gen_x87_fp_to_gp(node);
2748 /* we convert from int ... */
2749 if (mode_is_float(tgt_mode)) {
2751 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2752 if (USE_SSE2(env_cg)) {
2753 new_op = be_transform_node(op);
2754 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2756 set_ia32_ls_mode(res, tgt_mode);
2758 res = gen_x87_gp_to_fp(node, src_mode);
2759 if(get_Conv_strict(node)) {
2760 res = gen_x87_strict_conv(tgt_mode, res);
2761 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2762 ia32_get_old_node_name(env_cg, node));
2766 } else if(tgt_mode == mode_b) {
2767 /* mode_b lowering already took care that we only have 0/1 values */
2768 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2769 src_mode, tgt_mode));
2770 return be_transform_node(op);
2773 if (src_bits == tgt_bits) {
2774 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2775 src_mode, tgt_mode));
2776 return be_transform_node(op);
2779 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2787 static int check_immediate_constraint(long val, char immediate_constraint_type)
2789 switch (immediate_constraint_type) {
2793 return val >= 0 && val <= 32;
2795 return val >= 0 && val <= 63;
2797 return val >= -128 && val <= 127;
2799 return val == 0xff || val == 0xffff;
2801 return val >= 0 && val <= 3;
2803 return val >= 0 && val <= 255;
2805 return val >= 0 && val <= 127;
2809 panic("Invalid immediate constraint found");
2813 static ir_node *try_create_Immediate(ir_node *node,
2814 char immediate_constraint_type)
2817 tarval *offset = NULL;
2818 int offset_sign = 0;
2820 ir_entity *symconst_ent = NULL;
2821 int symconst_sign = 0;
2823 ir_node *cnst = NULL;
2824 ir_node *symconst = NULL;
2827 mode = get_irn_mode(node);
2828 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2832 if(is_Minus(node)) {
2834 node = get_Minus_op(node);
2837 if(is_Const(node)) {
2840 offset_sign = minus;
2841 } else if(is_SymConst(node)) {
2844 symconst_sign = minus;
2845 } else if(is_Add(node)) {
2846 ir_node *left = get_Add_left(node);
2847 ir_node *right = get_Add_right(node);
2848 if(is_Const(left) && is_SymConst(right)) {
2851 symconst_sign = minus;
2852 offset_sign = minus;
2853 } else if(is_SymConst(left) && is_Const(right)) {
2856 symconst_sign = minus;
2857 offset_sign = minus;
2859 } else if(is_Sub(node)) {
2860 ir_node *left = get_Sub_left(node);
2861 ir_node *right = get_Sub_right(node);
2862 if(is_Const(left) && is_SymConst(right)) {
2865 symconst_sign = !minus;
2866 offset_sign = minus;
2867 } else if(is_SymConst(left) && is_Const(right)) {
2870 symconst_sign = minus;
2871 offset_sign = !minus;
2878 offset = get_Const_tarval(cnst);
2879 if(tarval_is_long(offset)) {
2880 val = get_tarval_long(offset);
2882 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2887 if(!check_immediate_constraint(val, immediate_constraint_type))
2890 if(symconst != NULL) {
2891 if(immediate_constraint_type != 0) {
2892 /* we need full 32bits for symconsts */
2896 /* unfortunately the assembler/linker doesn't support -symconst */
2900 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2902 symconst_ent = get_SymConst_entity(symconst);
2904 if(cnst == NULL && symconst == NULL)
2907 if(offset_sign && offset != NULL) {
2908 offset = tarval_neg(offset);
2911 res = create_Immediate(symconst_ent, symconst_sign, val);
2916 static ir_node *create_immediate_or_transform(ir_node *node,
2917 char immediate_constraint_type)
2919 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2920 if (new_node == NULL) {
2921 new_node = be_transform_node(node);
2926 typedef struct constraint_t constraint_t;
2927 struct constraint_t {
2930 const arch_register_req_t **out_reqs;
2932 const arch_register_req_t *req;
2933 unsigned immediate_possible;
2934 char immediate_type;
2937 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2939 int immediate_possible = 0;
2940 char immediate_type = 0;
2941 unsigned limited = 0;
2942 const arch_register_class_t *cls = NULL;
2943 ir_graph *irg = current_ir_graph;
2944 struct obstack *obst = get_irg_obstack(irg);
2945 arch_register_req_t *req;
2946 unsigned *limited_ptr;
2950 /* TODO: replace all the asserts with nice error messages */
2952 printf("Constraint: %s\n", c);
2962 assert(cls == NULL ||
2963 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2964 cls = &ia32_reg_classes[CLASS_ia32_gp];
2965 limited |= 1 << REG_EAX;
2968 assert(cls == NULL ||
2969 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2970 cls = &ia32_reg_classes[CLASS_ia32_gp];
2971 limited |= 1 << REG_EBX;
2974 assert(cls == NULL ||
2975 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2976 cls = &ia32_reg_classes[CLASS_ia32_gp];
2977 limited |= 1 << REG_ECX;
2980 assert(cls == NULL ||
2981 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2982 cls = &ia32_reg_classes[CLASS_ia32_gp];
2983 limited |= 1 << REG_EDX;
2986 assert(cls == NULL ||
2987 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2988 cls = &ia32_reg_classes[CLASS_ia32_gp];
2989 limited |= 1 << REG_EDI;
2992 assert(cls == NULL ||
2993 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2994 cls = &ia32_reg_classes[CLASS_ia32_gp];
2995 limited |= 1 << REG_ESI;
2998 case 'q': /* q means lower part of the regs only, this makes no
2999 * difference to Q for us (we only assigne whole registers) */
3000 assert(cls == NULL ||
3001 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3002 cls = &ia32_reg_classes[CLASS_ia32_gp];
3003 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3007 assert(cls == NULL ||
3008 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3009 cls = &ia32_reg_classes[CLASS_ia32_gp];
3010 limited |= 1 << REG_EAX | 1 << REG_EDX;
3013 assert(cls == NULL ||
3014 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3015 cls = &ia32_reg_classes[CLASS_ia32_gp];
3016 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3017 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3024 assert(cls == NULL);
3025 cls = &ia32_reg_classes[CLASS_ia32_gp];
3031 /* TODO: mark values so the x87 simulator knows about t and u */
3032 assert(cls == NULL);
3033 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3038 assert(cls == NULL);
3039 /* TODO: check that sse2 is supported */
3040 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3050 assert(!immediate_possible);
3051 immediate_possible = 1;
3052 immediate_type = *c;
3056 assert(!immediate_possible);
3057 immediate_possible = 1;
3061 assert(!immediate_possible && cls == NULL);
3062 immediate_possible = 1;
3063 cls = &ia32_reg_classes[CLASS_ia32_gp];
3076 assert(constraint->is_in && "can only specify same constraint "
3079 sscanf(c, "%d%n", &same_as, &p);
3086 case 'E': /* no float consts yet */
3087 case 'F': /* no float consts yet */
3088 case 's': /* makes no sense on x86 */
3089 case 'X': /* we can't support that in firm */
3093 case '<': /* no autodecrement on x86 */
3094 case '>': /* no autoincrement on x86 */
3095 case 'C': /* sse constant not supported yet */
3096 case 'G': /* 80387 constant not supported yet */
3097 case 'y': /* we don't support mmx registers yet */
3098 case 'Z': /* not available in 32 bit mode */
3099 case 'e': /* not available in 32 bit mode */
3100 panic("unsupported asm constraint '%c' found in (%+F)",
3101 *c, current_ir_graph);
3104 panic("unknown asm constraint '%c' found in (%+F)", *c,
3112 const arch_register_req_t *other_constr;
3114 assert(cls == NULL && "same as and register constraint not supported");
3115 assert(!immediate_possible && "same as and immediate constraint not "
3117 assert(same_as < constraint->n_outs && "wrong constraint number in "
3118 "same_as constraint");
3120 other_constr = constraint->out_reqs[same_as];
3122 req = obstack_alloc(obst, sizeof(req[0]));
3123 req->cls = other_constr->cls;
3124 req->type = arch_register_req_type_should_be_same;
3125 req->limited = NULL;
3126 req->other_same[0] = pos;
3127 req->other_same[1] = -1;
3128 req->other_different = -1;
3130 /* switch constraints. This is because in firm we have same_as
3131 * constraints on the output constraints while in the gcc asm syntax
3132 * they are specified on the input constraints */
3133 constraint->req = other_constr;
3134 constraint->out_reqs[same_as] = req;
3135 constraint->immediate_possible = 0;
3139 if(immediate_possible && cls == NULL) {
3140 cls = &ia32_reg_classes[CLASS_ia32_gp];
3142 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3143 assert(cls != NULL);
3145 if(immediate_possible) {
3146 assert(constraint->is_in
3147 && "imeediates make no sense for output constraints");
3149 /* todo: check types (no float input on 'r' constrained in and such... */
3152 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3153 limited_ptr = (unsigned*) (req+1);
3155 req = obstack_alloc(obst, sizeof(req[0]));
3157 memset(req, 0, sizeof(req[0]));
3160 req->type = arch_register_req_type_limited;
3161 *limited_ptr = limited;
3162 req->limited = limited_ptr;
3164 req->type = arch_register_req_type_normal;
3168 constraint->req = req;
3169 constraint->immediate_possible = immediate_possible;
3170 constraint->immediate_type = immediate_type;
3173 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3180 panic("Clobbers not supported yet");
3184 * generates code for a ASM node
3186 static ir_node *gen_ASM(ir_node *node)
3189 ir_graph *irg = current_ir_graph;
3190 ir_node *block = be_transform_node(get_nodes_block(node));
3191 dbg_info *dbgi = get_irn_dbg_info(node);
3198 ia32_asm_attr_t *attr;
3199 const arch_register_req_t **out_reqs;
3200 const arch_register_req_t **in_reqs;
3201 struct obstack *obst;
3202 constraint_t parsed_constraint;
3204 /* transform inputs */
3205 arity = get_irn_arity(node);
3206 in = alloca(arity * sizeof(in[0]));
3207 memset(in, 0, arity * sizeof(in[0]));
3209 n_outs = get_ASM_n_output_constraints(node);
3210 n_clobbers = get_ASM_n_clobbers(node);
3211 out_arity = n_outs + n_clobbers;
3213 /* construct register constraints */
3214 obst = get_irg_obstack(irg);
3215 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3216 parsed_constraint.out_reqs = out_reqs;
3217 parsed_constraint.n_outs = n_outs;
3218 parsed_constraint.is_in = 0;
3219 for(i = 0; i < out_arity; ++i) {
3223 const ir_asm_constraint *constraint;
3224 constraint = & get_ASM_output_constraints(node) [i];
3225 c = get_id_str(constraint->constraint);
3226 parse_asm_constraint(i, &parsed_constraint, c);
3228 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3229 c = get_id_str(glob_id);
3230 parse_clobber(node, i, &parsed_constraint, c);
3232 out_reqs[i] = parsed_constraint.req;
3235 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3236 parsed_constraint.is_in = 1;
3237 for(i = 0; i < arity; ++i) {
3238 const ir_asm_constraint *constraint;
3242 constraint = & get_ASM_input_constraints(node) [i];
3243 constr_id = constraint->constraint;
3244 c = get_id_str(constr_id);
3245 parse_asm_constraint(i, &parsed_constraint, c);
3246 in_reqs[i] = parsed_constraint.req;
3248 if(parsed_constraint.immediate_possible) {
3249 ir_node *pred = get_irn_n(node, i);
3250 char imm_type = parsed_constraint.immediate_type;
3251 ir_node *immediate = try_create_Immediate(pred, imm_type);
3253 if(immediate != NULL) {
3259 /* transform inputs */
3260 for(i = 0; i < arity; ++i) {
3262 ir_node *transformed;
3267 pred = get_irn_n(node, i);
3268 transformed = be_transform_node(pred);
3269 in[i] = transformed;
3272 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3274 generic_attr = get_irn_generic_attr(res);
3275 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3276 attr->asm_text = get_ASM_text(node);
3277 set_ia32_out_req_all(res, out_reqs);
3278 set_ia32_in_req_all(res, in_reqs);
3280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3285 /********************************************
3288 * | |__ ___ _ __ ___ __| | ___ ___
3289 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3290 * | |_) | __/ | | | (_) | (_| | __/\__ \
3291 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3293 ********************************************/
3296 * Transforms a FrameAddr into an ia32 Add.
3298 static ir_node *gen_be_FrameAddr(ir_node *node) {
3299 ir_node *block = be_transform_node(get_nodes_block(node));
3300 ir_node *op = be_get_FrameAddr_frame(node);
3301 ir_node *new_op = be_transform_node(op);
3302 ir_graph *irg = current_ir_graph;
3303 dbg_info *dbgi = get_irn_dbg_info(node);
3304 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3307 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3308 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3309 set_ia32_use_frame(res);
3311 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3317 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3319 static ir_node *gen_be_Return(ir_node *node) {
3320 ir_graph *irg = current_ir_graph;
3321 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3322 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3323 ir_entity *ent = get_irg_entity(irg);
3324 ir_type *tp = get_entity_type(ent);
3329 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3330 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3333 int pn_ret_val, pn_ret_mem, arity, i;
3335 assert(ret_val != NULL);
3336 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3337 return be_duplicate_node(node);
3340 res_type = get_method_res_type(tp, 0);
3342 if (! is_Primitive_type(res_type)) {
3343 return be_duplicate_node(node);
3346 mode = get_type_mode(res_type);
3347 if (! mode_is_float(mode)) {
3348 return be_duplicate_node(node);
3351 assert(get_method_n_ress(tp) == 1);
3353 pn_ret_val = get_Proj_proj(ret_val);
3354 pn_ret_mem = get_Proj_proj(ret_mem);
3356 /* get the Barrier */
3357 barrier = get_Proj_pred(ret_val);
3359 /* get result input of the Barrier */
3360 ret_val = get_irn_n(barrier, pn_ret_val);
3361 new_ret_val = be_transform_node(ret_val);
3363 /* get memory input of the Barrier */
3364 ret_mem = get_irn_n(barrier, pn_ret_mem);
3365 new_ret_mem = be_transform_node(ret_mem);
3367 frame = get_irg_frame(irg);
3369 dbgi = get_irn_dbg_info(barrier);
3370 block = be_transform_node(get_nodes_block(barrier));
3372 noreg = ia32_new_NoReg_gp(env_cg);
3374 /* store xmm0 onto stack */
3375 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3376 new_ret_mem, new_ret_val);
3377 set_ia32_ls_mode(sse_store, mode);
3378 set_ia32_op_type(sse_store, ia32_AddrModeD);
3379 set_ia32_use_frame(sse_store);
3381 /* load into x87 register */
3382 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3383 set_ia32_op_type(fld, ia32_AddrModeS);
3384 set_ia32_use_frame(fld);
3386 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3387 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3389 /* create a new barrier */
3390 arity = get_irn_arity(barrier);
3391 in = alloca(arity * sizeof(in[0]));
3392 for (i = 0; i < arity; ++i) {
3395 if (i == pn_ret_val) {
3397 } else if (i == pn_ret_mem) {
3400 ir_node *in = get_irn_n(barrier, i);
3401 new_in = be_transform_node(in);
3406 new_barrier = new_ir_node(dbgi, irg, block,
3407 get_irn_op(barrier), get_irn_mode(barrier),
3409 copy_node_attr(barrier, new_barrier);
3410 be_duplicate_deps(barrier, new_barrier);
3411 be_set_transformed_node(barrier, new_barrier);
3412 mark_irn_visited(barrier);
3414 /* transform normally */
3415 return be_duplicate_node(node);
3419 * Transform a be_AddSP into an ia32_SubSP.
3421 static ir_node *gen_be_AddSP(ir_node *node)
3423 ir_node *src_block = get_nodes_block(node);
3424 ir_node *new_block = be_transform_node(src_block);
3425 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3426 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3427 ir_graph *irg = current_ir_graph;
3428 dbg_info *dbgi = get_irn_dbg_info(node);
3430 ia32_address_mode_t am;
3431 ia32_address_t *addr = &am.addr;
3432 match_flags_t flags = 0;
3434 match_arguments(&am, src_block, sp, sz, flags);
3436 new_node = new_rd_ia32_SubSP(dbgi, irg, new_block, addr->base, addr->index,
3437 addr->mem, am.new_op1, am.new_op2);
3438 set_am_attributes(new_node, &am);
3439 /* we can't use source address mode anymore when using immediates */
3440 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3441 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3442 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3444 new_node = fix_mem_proj(new_node, &am);
3450 * Transform a be_SubSP into an ia32_AddSP
3452 static ir_node *gen_be_SubSP(ir_node *node)
3454 ir_node *src_block = get_nodes_block(node);
3455 ir_node *new_block = be_transform_node(src_block);
3456 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3457 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3458 ir_graph *irg = current_ir_graph;
3459 dbg_info *dbgi = get_irn_dbg_info(node);
3461 ia32_address_mode_t am;
3462 ia32_address_t *addr = &am.addr;
3463 match_flags_t flags = 0;
3465 match_arguments(&am, src_block, sp, sz, flags);
3467 new_node = new_rd_ia32_AddSP(dbgi, irg, new_block, addr->base, addr->index,
3468 addr->mem, am.new_op1, am.new_op2);
3469 set_am_attributes(new_node, &am);
3470 /* we can't use source address mode anymore when using immediates */
3471 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3472 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3473 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3475 new_node = fix_mem_proj(new_node, &am);
3481 * This function just sets the register for the Unknown node
3482 * as this is not done during register allocation because Unknown
3483 * is an "ignore" node.
3485 static ir_node *gen_Unknown(ir_node *node) {
3486 ir_mode *mode = get_irn_mode(node);
3488 if (mode_is_float(mode)) {
3489 if (USE_SSE2(env_cg)) {
3490 return ia32_new_Unknown_xmm(env_cg);
3492 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3493 ir_graph *irg = current_ir_graph;
3494 dbg_info *dbgi = get_irn_dbg_info(node);
3495 ir_node *block = get_irg_start_block(irg);
3496 return new_rd_ia32_vfldz(dbgi, irg, block);
3498 } else if (mode_needs_gp_reg(mode)) {
3499 return ia32_new_Unknown_gp(env_cg);
3501 assert(0 && "unsupported Unknown-Mode");
3508 * Change some phi modes
3510 static ir_node *gen_Phi(ir_node *node) {
3511 ir_node *block = be_transform_node(get_nodes_block(node));
3512 ir_graph *irg = current_ir_graph;
3513 dbg_info *dbgi = get_irn_dbg_info(node);
3514 ir_mode *mode = get_irn_mode(node);
3517 if(mode_needs_gp_reg(mode)) {
3518 /* we shouldn't have any 64bit stuff around anymore */
3519 assert(get_mode_size_bits(mode) <= 32);
3520 /* all integer operations are on 32bit registers now */
3522 } else if(mode_is_float(mode)) {
3523 if (USE_SSE2(env_cg)) {
3530 /* phi nodes allow loops, so we use the old arguments for now
3531 * and fix this later */
3532 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3533 get_irn_in(node) + 1);
3534 copy_node_attr(node, phi);
3535 be_duplicate_deps(node, phi);
3537 be_set_transformed_node(node, phi);
3538 be_enqueue_preds(node);
3546 static ir_node *gen_IJmp(ir_node *node) {
3547 /* TODO: support AM */
3548 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3552 /**********************************************************************
3555 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3556 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3557 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3558 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3560 **********************************************************************/
3562 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3564 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3567 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3568 ir_node *val, ir_node *mem);
3571 * Transforms a lowered Load into a "real" one.
3573 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3575 ir_node *block = be_transform_node(get_nodes_block(node));
3576 ir_node *ptr = get_irn_n(node, 0);
3577 ir_node *new_ptr = be_transform_node(ptr);
3578 ir_node *mem = get_irn_n(node, 1);
3579 ir_node *new_mem = be_transform_node(mem);
3580 ir_graph *irg = current_ir_graph;
3581 dbg_info *dbgi = get_irn_dbg_info(node);
3582 ir_mode *mode = get_ia32_ls_mode(node);
3583 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3586 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3588 set_ia32_op_type(new_op, ia32_AddrModeS);
3589 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3590 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3591 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3592 if (is_ia32_am_sc_sign(node))
3593 set_ia32_am_sc_sign(new_op);
3594 set_ia32_ls_mode(new_op, mode);
3595 if (is_ia32_use_frame(node)) {
3596 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3597 set_ia32_use_frame(new_op);
3600 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3606 * Transforms a lowered Store into a "real" one.
3608 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3610 ir_node *block = be_transform_node(get_nodes_block(node));
3611 ir_node *ptr = get_irn_n(node, 0);
3612 ir_node *new_ptr = be_transform_node(ptr);
3613 ir_node *val = get_irn_n(node, 1);
3614 ir_node *new_val = be_transform_node(val);
3615 ir_node *mem = get_irn_n(node, 2);
3616 ir_node *new_mem = be_transform_node(mem);
3617 ir_graph *irg = current_ir_graph;
3618 dbg_info *dbgi = get_irn_dbg_info(node);
3619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3620 ir_mode *mode = get_ia32_ls_mode(node);
3624 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3626 am_offs = get_ia32_am_offs_int(node);
3627 add_ia32_am_offs_int(new_op, am_offs);
3629 set_ia32_op_type(new_op, ia32_AddrModeD);
3630 set_ia32_ls_mode(new_op, mode);
3631 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3632 set_ia32_use_frame(new_op);
3634 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3641 * Transforms an ia32_l_XXX into a "real" XXX node
3643 * @param node The node to transform
3644 * @return the created ia32 XXX node
3646 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3647 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3648 return gen_shift_binop(node, get_irn_n(node, 0), \
3649 get_irn_n(node, 1), new_rd_ia32_##op); \
3652 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3653 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3654 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3656 static ir_node *gen_ia32_l_Add(ir_node *node) {
3657 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3658 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3659 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, match_commutative);
3661 if(is_Proj(lowered)) {
3662 lowered = get_Proj_pred(lowered);
3664 assert(is_ia32_Add(lowered));
3665 set_irn_mode(lowered, mode_T);
3671 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3672 ir_node *src_block = get_nodes_block(node);
3673 ir_node *block = be_transform_node(src_block);
3674 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3675 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3676 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3677 ir_node *new_flags = be_transform_node(flags);
3678 ir_graph *irg = current_ir_graph;
3679 dbg_info *dbgi = get_irn_dbg_info(node);
3681 ia32_address_mode_t am;
3682 ia32_address_t *addr = &am.addr;
3684 match_arguments(&am, src_block, op1, op2, match_commutative);
3686 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3687 addr->mem, am.new_op1, am.new_op2, new_flags);
3688 set_am_attributes(new_node, &am);
3689 /* we can't use source address mode anymore when using immediates */
3690 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3691 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3692 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3694 new_node = fix_mem_proj(new_node, &am);
3700 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3702 * @param node The node to transform
3703 * @return the created ia32 Neg node
3705 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3706 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3710 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3712 * @param node The node to transform
3713 * @return the created ia32 vfild node
3715 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3716 return gen_lowered_Load(node, new_rd_ia32_vfild);
3720 * Transforms an ia32_l_Load into a "real" ia32_Load node
3722 * @param node The node to transform
3723 * @return the created ia32 Load node
3725 static ir_node *gen_ia32_l_Load(ir_node *node) {
3726 return gen_lowered_Load(node, new_rd_ia32_Load);
3730 * Transforms an ia32_l_Store into a "real" ia32_Store node
3732 * @param node The node to transform
3733 * @return the created ia32 Store node
3735 static ir_node *gen_ia32_l_Store(ir_node *node) {
3736 return gen_lowered_Store(node, new_rd_ia32_Store);
3740 * Transforms a l_vfist into a "real" vfist node.
3742 * @param node The node to transform
3743 * @return the created ia32 vfist node
3745 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3746 ir_node *block = be_transform_node(get_nodes_block(node));
3747 ir_node *ptr = get_irn_n(node, 0);
3748 ir_node *new_ptr = be_transform_node(ptr);
3749 ir_node *val = get_irn_n(node, 1);
3750 ir_node *new_val = be_transform_node(val);
3751 ir_node *mem = get_irn_n(node, 2);
3752 ir_node *new_mem = be_transform_node(mem);
3753 ir_graph *irg = current_ir_graph;
3754 dbg_info *dbgi = get_irn_dbg_info(node);
3755 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3756 ir_mode *mode = get_ia32_ls_mode(node);
3757 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3761 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3762 new_val, trunc_mode);
3764 am_offs = get_ia32_am_offs_int(node);
3765 add_ia32_am_offs_int(new_op, am_offs);
3767 set_ia32_op_type(new_op, ia32_AddrModeD);
3768 set_ia32_ls_mode(new_op, mode);
3769 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3770 set_ia32_use_frame(new_op);
3772 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3778 * Transforms a l_MulS into a "real" MulS node.
3780 * @return the created ia32 Mul node
3782 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3783 ir_node *block = be_transform_node(get_nodes_block(node));
3784 ir_node *left = get_binop_left(node);
3785 ir_node *new_left = be_transform_node(left);
3786 ir_node *right = get_binop_right(node);
3787 ir_node *new_right = be_transform_node(right);
3788 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3789 ir_graph *irg = current_ir_graph;
3790 dbg_info *dbgi = get_irn_dbg_info(node);
3792 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3793 /* and then skip the result Proj, because all needed Projs are already there. */
3794 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3795 new_left, new_right);
3796 clear_ia32_commutative(muls);
3798 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3804 * Transforms a l_IMulS into a "real" IMul1OPS node.
3806 * @return the created ia32 IMul1OP node
3808 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3809 ir_node *block = be_transform_node(get_nodes_block(node));
3810 ir_node *left = get_binop_left(node);
3811 ir_node *new_left = be_transform_node(left);
3812 ir_node *right = get_binop_right(node);
3813 ir_node *new_right = be_transform_node(right);
3814 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3815 ir_graph *irg = current_ir_graph;
3816 dbg_info *dbgi = get_irn_dbg_info(node);
3818 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3819 /* and then skip the result Proj, because all needed Projs are already there. */
3820 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3821 new_NoMem(), new_left, new_right);
3822 clear_ia32_commutative(muls);
3824 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3829 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3830 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3831 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3832 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3834 if(is_Proj(lowered)) {
3835 lowered = get_Proj_pred(lowered);
3837 assert(is_ia32_Sub(lowered));
3838 set_irn_mode(lowered, mode_T);
3844 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3845 ir_node *src_block = get_nodes_block(node);
3846 ir_node *block = be_transform_node(src_block);
3847 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3848 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3849 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3850 ir_node *new_flags = be_transform_node(flags);
3851 ir_graph *irg = current_ir_graph;
3852 dbg_info *dbgi = get_irn_dbg_info(node);
3854 ia32_address_mode_t am;
3855 ia32_address_t *addr = &am.addr;
3857 match_arguments(&am, src_block, op1, op2, match_commutative);
3859 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3860 addr->mem, am.new_op1, am.new_op2, new_flags);
3861 set_am_attributes(new_node, &am);
3862 /* we can't use source address mode anymore when using immediates */
3863 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3864 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3865 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3867 new_node = fix_mem_proj(new_node, &am);
3873 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3874 * op1 - target to be shifted
3875 * op2 - contains bits to be shifted into target
3877 * Only op3 can be an immediate.
3879 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3880 ir_node *op2, ir_node *count)
3882 ir_node *block = be_transform_node(get_nodes_block(node));
3883 ir_node *new_op = NULL;
3884 ir_graph *irg = current_ir_graph;
3885 dbg_info *dbgi = get_irn_dbg_info(node);
3886 ir_node *new_op1 = be_transform_node(op1);
3887 ir_node *new_op2 = be_transform_node(op2);
3888 ir_node *new_count = create_immediate_or_transform(count, 'I');
3890 /* TODO proper AM support */
3892 if (is_ia32_l_ShlD(node))
3893 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3895 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3897 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3902 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3903 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3904 get_irn_n(node, 1), get_irn_n(node, 2));
3907 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3908 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3909 get_irn_n(node, 1), get_irn_n(node, 2));
3913 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3915 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3916 ir_node *block = be_transform_node(get_nodes_block(node));
3917 ir_node *val = get_irn_n(node, 1);
3918 ir_node *new_val = be_transform_node(val);
3919 ia32_code_gen_t *cg = env_cg;
3920 ir_node *res = NULL;
3921 ir_graph *irg = current_ir_graph;
3923 ir_node *noreg, *new_ptr, *new_mem;
3930 mem = get_irn_n(node, 2);
3931 new_mem = be_transform_node(mem);
3932 ptr = get_irn_n(node, 0);
3933 new_ptr = be_transform_node(ptr);
3934 noreg = ia32_new_NoReg_gp(cg);
3935 dbgi = get_irn_dbg_info(node);
3937 /* Store x87 -> MEM */
3938 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3939 get_ia32_ls_mode(node));
3940 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3941 set_ia32_use_frame(res);
3942 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3943 set_ia32_op_type(res, ia32_AddrModeD);
3945 /* Load MEM -> SSE */
3946 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3947 get_ia32_ls_mode(node));
3948 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3949 set_ia32_use_frame(res);
3950 set_ia32_op_type(res, ia32_AddrModeS);
3951 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3957 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3959 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3960 ir_node *block = be_transform_node(get_nodes_block(node));
3961 ir_node *val = get_irn_n(node, 1);
3962 ir_node *new_val = be_transform_node(val);
3963 ia32_code_gen_t *cg = env_cg;
3964 ir_graph *irg = current_ir_graph;
3965 ir_node *res = NULL;
3966 ir_entity *fent = get_ia32_frame_ent(node);
3967 ir_mode *lsmode = get_ia32_ls_mode(node);
3969 ir_node *noreg, *new_ptr, *new_mem;
3973 if (! USE_SSE2(cg)) {
3974 /* SSE unit is not used -> skip this node. */
3978 ptr = get_irn_n(node, 0);
3979 new_ptr = be_transform_node(ptr);
3980 mem = get_irn_n(node, 2);
3981 new_mem = be_transform_node(mem);
3982 noreg = ia32_new_NoReg_gp(cg);
3983 dbgi = get_irn_dbg_info(node);
3985 /* Store SSE -> MEM */
3986 if (is_ia32_xLoad(skip_Proj(new_val))) {
3987 ir_node *ld = skip_Proj(new_val);
3989 /* we can vfld the value directly into the fpu */
3990 fent = get_ia32_frame_ent(ld);
3991 ptr = get_irn_n(ld, 0);
3992 offs = get_ia32_am_offs_int(ld);
3994 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3996 set_ia32_frame_ent(res, fent);
3997 set_ia32_use_frame(res);
3998 set_ia32_ls_mode(res, lsmode);
3999 set_ia32_op_type(res, ia32_AddrModeD);
4003 /* Load MEM -> x87 */
4004 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4005 set_ia32_frame_ent(res, fent);
4006 set_ia32_use_frame(res);
4007 add_ia32_am_offs_int(res, offs);
4008 set_ia32_op_type(res, ia32_AddrModeS);
4009 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4014 /*********************************************************
4017 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4018 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4019 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4020 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4022 *********************************************************/
4025 * the BAD transformer.
4027 static ir_node *bad_transform(ir_node *node) {
4028 panic("No transform function for %+F available.\n", node);
4033 * Transform the Projs of an AddSP.
4035 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4036 ir_node *block = be_transform_node(get_nodes_block(node));
4037 ir_node *pred = get_Proj_pred(node);
4038 ir_node *new_pred = be_transform_node(pred);
4039 ir_graph *irg = current_ir_graph;
4040 dbg_info *dbgi = get_irn_dbg_info(node);
4041 long proj = get_Proj_proj(node);
4043 if (proj == pn_be_AddSP_sp) {
4044 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4045 pn_ia32_SubSP_stack);
4046 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4048 } else if(proj == pn_be_AddSP_res) {
4049 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4050 pn_ia32_SubSP_addr);
4051 } else if (proj == pn_be_AddSP_M) {
4052 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4056 return new_rd_Unknown(irg, get_irn_mode(node));
4060 * Transform the Projs of a SubSP.
4062 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4063 ir_node *block = be_transform_node(get_nodes_block(node));
4064 ir_node *pred = get_Proj_pred(node);
4065 ir_node *new_pred = be_transform_node(pred);
4066 ir_graph *irg = current_ir_graph;
4067 dbg_info *dbgi = get_irn_dbg_info(node);
4068 long proj = get_Proj_proj(node);
4070 if (proj == pn_be_SubSP_sp) {
4071 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4072 pn_ia32_AddSP_stack);
4073 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4075 } else if (proj == pn_be_SubSP_M) {
4076 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4080 return new_rd_Unknown(irg, get_irn_mode(node));
4084 * Transform and renumber the Projs from a Load.
4086 static ir_node *gen_Proj_Load(ir_node *node) {
4088 ir_node *block = be_transform_node(get_nodes_block(node));
4089 ir_node *pred = get_Proj_pred(node);
4090 ir_graph *irg = current_ir_graph;
4091 dbg_info *dbgi = get_irn_dbg_info(node);
4092 long proj = get_Proj_proj(node);
4095 /* loads might be part of source address mode matches, so we don't
4096 transform the ProjMs yet (with the exception of loads whose result is
4099 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4102 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4104 /* this is needed, because sometimes we have loops that are only
4105 reachable through the ProjM */
4106 be_enqueue_preds(node);
4107 /* do it in 2 steps, to silence firm verifier */
4108 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4109 set_Proj_proj(res, pn_ia32_Load_M);
4113 /* renumber the proj */
4114 new_pred = be_transform_node(pred);
4115 if (is_ia32_Load(new_pred)) {
4116 if (proj == pn_Load_res) {
4117 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4119 } else if (proj == pn_Load_M) {
4120 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4123 } else if(is_ia32_Conv_I2I(new_pred)) {
4124 set_irn_mode(new_pred, mode_T);
4125 if (proj == pn_Load_res) {
4126 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4127 } else if (proj == pn_Load_M) {
4128 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4130 } else if (is_ia32_xLoad(new_pred)) {
4131 if (proj == pn_Load_res) {
4132 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4134 } else if (proj == pn_Load_M) {
4135 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4138 } else if (is_ia32_vfld(new_pred)) {
4139 if (proj == pn_Load_res) {
4140 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4142 } else if (proj == pn_Load_M) {
4143 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4147 /* can happen for ProJMs when source address mode happened for the
4150 /* however it should not be the result proj, as that would mean the
4151 load had multiple users and should not have been used for
4153 if(proj != pn_Load_M) {
4154 panic("internal error: transformed node not a Load");
4156 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4160 return new_rd_Unknown(irg, get_irn_mode(node));
4164 * Transform and renumber the Projs from a DivMod like instruction.
4166 static ir_node *gen_Proj_DivMod(ir_node *node) {
4167 ir_node *block = be_transform_node(get_nodes_block(node));
4168 ir_node *pred = get_Proj_pred(node);
4169 ir_node *new_pred = be_transform_node(pred);
4170 ir_graph *irg = current_ir_graph;
4171 dbg_info *dbgi = get_irn_dbg_info(node);
4172 ir_mode *mode = get_irn_mode(node);
4173 long proj = get_Proj_proj(node);
4175 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4177 switch (get_irn_opcode(pred)) {
4181 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4183 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4191 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4193 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4201 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4202 case pn_DivMod_res_div:
4203 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4204 case pn_DivMod_res_mod:
4205 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4215 return new_rd_Unknown(irg, mode);
4219 * Transform and renumber the Projs from a CopyB.
4221 static ir_node *gen_Proj_CopyB(ir_node *node) {
4222 ir_node *block = be_transform_node(get_nodes_block(node));
4223 ir_node *pred = get_Proj_pred(node);
4224 ir_node *new_pred = be_transform_node(pred);
4225 ir_graph *irg = current_ir_graph;
4226 dbg_info *dbgi = get_irn_dbg_info(node);
4227 ir_mode *mode = get_irn_mode(node);
4228 long proj = get_Proj_proj(node);
4231 case pn_CopyB_M_regular:
4232 if (is_ia32_CopyB_i(new_pred)) {
4233 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4234 } else if (is_ia32_CopyB(new_pred)) {
4235 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4243 return new_rd_Unknown(irg, mode);
4247 * Transform and renumber the Projs from a Quot.
4249 static ir_node *gen_Proj_Quot(ir_node *node) {
4250 ir_node *block = be_transform_node(get_nodes_block(node));
4251 ir_node *pred = get_Proj_pred(node);
4252 ir_node *new_pred = be_transform_node(pred);
4253 ir_graph *irg = current_ir_graph;
4254 dbg_info *dbgi = get_irn_dbg_info(node);
4255 ir_mode *mode = get_irn_mode(node);
4256 long proj = get_Proj_proj(node);
4260 if (is_ia32_xDiv(new_pred)) {
4261 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4262 } else if (is_ia32_vfdiv(new_pred)) {
4263 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4267 if (is_ia32_xDiv(new_pred)) {
4268 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4269 } else if (is_ia32_vfdiv(new_pred)) {
4270 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4278 return new_rd_Unknown(irg, mode);
4282 * Transform the Thread Local Storage Proj.
4284 static ir_node *gen_Proj_tls(ir_node *node) {
4285 ir_node *block = be_transform_node(get_nodes_block(node));
4286 ir_graph *irg = current_ir_graph;
4287 dbg_info *dbgi = NULL;
4288 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4293 static ir_node *gen_be_Call(ir_node *node) {
4294 ir_node *res = be_duplicate_node(node);
4295 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4300 static ir_node *gen_be_IncSP(ir_node *node) {
4301 ir_node *res = be_duplicate_node(node);
4302 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4308 * Transform the Projs from a be_Call.
4310 static ir_node *gen_Proj_be_Call(ir_node *node) {
4311 ir_node *block = be_transform_node(get_nodes_block(node));
4312 ir_node *call = get_Proj_pred(node);
4313 ir_node *new_call = be_transform_node(call);
4314 ir_graph *irg = current_ir_graph;
4315 dbg_info *dbgi = get_irn_dbg_info(node);
4316 ir_type *method_type = be_Call_get_type(call);
4317 int n_res = get_method_n_ress(method_type);
4318 long proj = get_Proj_proj(node);
4319 ir_mode *mode = get_irn_mode(node);
4321 const arch_register_class_t *cls;
4323 /* The following is kinda tricky: If we're using SSE, then we have to
4324 * move the result value of the call in floating point registers to an
4325 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4326 * after the call, we have to make sure to correctly make the
4327 * MemProj and the result Proj use these 2 nodes
4329 if (proj == pn_be_Call_M_regular) {
4330 // get new node for result, are we doing the sse load/store hack?
4331 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4332 ir_node *call_res_new;
4333 ir_node *call_res_pred = NULL;
4335 if (call_res != NULL) {
4336 call_res_new = be_transform_node(call_res);
4337 call_res_pred = get_Proj_pred(call_res_new);
4340 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4341 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4342 pn_be_Call_M_regular);
4344 assert(is_ia32_xLoad(call_res_pred));
4345 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4349 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4350 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4351 && USE_SSE2(env_cg)) {
4353 ir_node *frame = get_irg_frame(irg);
4354 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4356 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4359 /* in case there is no memory output: create one to serialize the copy
4361 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4362 pn_be_Call_M_regular);
4363 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4364 pn_be_Call_first_res);
4366 /* store st(0) onto stack */
4367 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4369 set_ia32_op_type(fstp, ia32_AddrModeD);
4370 set_ia32_use_frame(fstp);
4372 /* load into SSE register */
4373 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4375 set_ia32_op_type(sse_load, ia32_AddrModeS);
4376 set_ia32_use_frame(sse_load);
4378 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4384 /* transform call modes */
4385 if (mode_is_data(mode)) {
4386 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4390 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4394 * Transform the Projs from a Cmp.
4396 static ir_node *gen_Proj_Cmp(ir_node *node)
4398 /* normally Cmps are processed when looking at Cond nodes, but this case
4399 * can happen in complicated Psi conditions */
4400 dbg_info *dbgi = get_irn_dbg_info(node);
4401 ir_node *block = get_nodes_block(node);
4402 ir_node *new_block = be_transform_node(block);
4403 ir_node *cmp = get_Proj_pred(node);
4404 ir_node *new_cmp = be_transform_node(cmp);
4405 long pnc = get_Proj_proj(node);
4408 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4414 * Transform and potentially renumber Proj nodes.
4416 static ir_node *gen_Proj(ir_node *node) {
4417 ir_graph *irg = current_ir_graph;
4418 dbg_info *dbgi = get_irn_dbg_info(node);
4419 ir_node *pred = get_Proj_pred(node);
4420 long proj = get_Proj_proj(node);
4422 if (is_Store(pred)) {
4423 if (proj == pn_Store_M) {
4424 return be_transform_node(pred);
4427 return new_r_Bad(irg);
4429 } else if (is_Load(pred)) {
4430 return gen_Proj_Load(node);
4431 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4432 return gen_Proj_DivMod(node);
4433 } else if (is_CopyB(pred)) {
4434 return gen_Proj_CopyB(node);
4435 } else if (is_Quot(pred)) {
4436 return gen_Proj_Quot(node);
4437 } else if (be_is_SubSP(pred)) {
4438 return gen_Proj_be_SubSP(node);
4439 } else if (be_is_AddSP(pred)) {
4440 return gen_Proj_be_AddSP(node);
4441 } else if (be_is_Call(pred)) {
4442 return gen_Proj_be_Call(node);
4443 } else if (is_Cmp(pred)) {
4444 return gen_Proj_Cmp(node);
4445 } else if (get_irn_op(pred) == op_Start) {
4446 if (proj == pn_Start_X_initial_exec) {
4447 ir_node *block = get_nodes_block(pred);
4450 /* we exchange the ProjX with a jump */
4451 block = be_transform_node(block);
4452 jump = new_rd_Jmp(dbgi, irg, block);
4455 if (node == be_get_old_anchor(anchor_tls)) {
4456 return gen_Proj_tls(node);
4459 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4463 ir_node *new_pred = be_transform_node(pred);
4464 ir_node *block = be_transform_node(get_nodes_block(node));
4465 ir_mode *mode = get_irn_mode(node);
4466 if (mode_needs_gp_reg(mode)) {
4467 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4468 get_Proj_proj(node));
4469 #ifdef DEBUG_libfirm
4470 new_proj->node_nr = node->node_nr;
4476 return be_duplicate_node(node);
4480 * Enters all transform functions into the generic pointer
4482 static void register_transformers(void)
4486 /* first clear the generic function pointer for all ops */
4487 clear_irp_opcodes_generic_func();
4489 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4490 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4528 /* transform ops from intrinsic lowering */
4545 GEN(ia32_l_X87toSSE);
4546 GEN(ia32_l_SSEtoX87);
4552 /* we should never see these nodes */
4567 /* handle generic backend nodes */
4576 op_Mulh = get_op_Mulh();
4585 * Pre-transform all unknown and noreg nodes.
4587 static void ia32_pretransform_node(void *arch_cg) {
4588 ia32_code_gen_t *cg = arch_cg;
4590 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4591 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4592 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4593 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4594 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4595 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4600 * Walker, checks if all ia32 nodes producing more than one result have
4601 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4603 static void add_missing_keep_walker(ir_node *node, void *data)
4606 unsigned found_projs = 0;
4607 const ir_edge_t *edge;
4608 ir_mode *mode = get_irn_mode(node);
4613 if(!is_ia32_irn(node))
4616 n_outs = get_ia32_n_res(node);
4619 if(is_ia32_SwitchJmp(node))
4622 assert(n_outs < (int) sizeof(unsigned) * 8);
4623 foreach_out_edge(node, edge) {
4624 ir_node *proj = get_edge_src_irn(edge);
4625 int pn = get_Proj_proj(proj);
4627 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4628 found_projs |= 1 << pn;
4632 /* are keeps missing? */
4634 for(i = 0; i < n_outs; ++i) {
4637 const arch_register_req_t *req;
4638 const arch_register_class_t *class;
4640 if(found_projs & (1 << i)) {
4644 req = get_ia32_out_req(node, i);
4649 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4653 block = get_nodes_block(node);
4654 in[0] = new_r_Proj(current_ir_graph, block, node,
4655 arch_register_class_mode(class), i);
4656 if(last_keep != NULL) {
4657 be_Keep_add_node(last_keep, class, in[0]);
4659 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4660 if(sched_is_scheduled(node)) {
4661 sched_add_after(node, last_keep);
4668 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4671 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4673 ir_graph *irg = be_get_birg_irg(cg->birg);
4674 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4677 /* do the transformation */
4678 void ia32_transform_graph(ia32_code_gen_t *cg) {
4679 ir_graph *irg = cg->irg;
4681 /* TODO: look at cpu and fill transform config in with that... */
4682 transform_config.use_incdec = 1;
4683 transform_config.use_sse2 = 0;
4684 transform_config.use_ffreep = 0;
4685 transform_config.use_ftst = 0;
4686 transform_config.use_femms = 0;
4687 transform_config.use_fucomi = 1;
4688 transform_config.use_cmov = 1;
4690 register_transformers();
4692 initial_fpcw = NULL;
4694 heights = heights_new(irg);
4695 calculate_non_address_mode_nodes(irg);
4697 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4699 free_non_address_mode_nodes();
4700 heights_free(heights);
4704 void ia32_init_transform(void)
4706 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");