2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
102 /****************************************************************************************************
104 * | | | | / _| | | (_)
105 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
106 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
107 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
108 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
110 ****************************************************************************************************/
112 static ir_node *try_create_Immediate(ir_node *node,
113 char immediate_constraint_type);
116 * Return true if a mode can be stored in the GP register set
118 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
119 if(mode == mode_fpcw)
121 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
125 * Returns 1 if irn is a Const representing 0, 0 otherwise
127 static INLINE int is_ia32_Const_0(ir_node *irn) {
128 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
129 && tarval_is_null(get_ia32_Immop_tarval(irn));
133 * Returns 1 if irn is a Const representing 1, 0 otherwise
135 static INLINE int is_ia32_Const_1(ir_node *irn) {
136 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
137 && tarval_is_one(get_ia32_Immop_tarval(irn));
141 * Collects all Projs of a node into the node array. Index is the projnum.
142 * BEWARE: The caller has to assure the appropriate array size!
144 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
145 const ir_edge_t *edge;
146 assert(get_irn_mode(irn) == mode_T && "need mode_T");
148 memset(projs, 0, size * sizeof(projs[0]));
150 foreach_out_edge(irn, edge) {
151 ir_node *proj = get_edge_src_irn(edge);
152 int proj_proj = get_Proj_proj(proj);
153 assert(proj_proj < size);
154 projs[proj_proj] = proj;
159 * Renumbers the proj having pn_old in the array tp pn_new
160 * and removes the proj from the array.
162 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
163 fprintf(stderr, "Warning: renumber_Proj used!\n");
165 set_Proj_proj(projs[pn_old], pn_new);
166 projs[pn_old] = NULL;
171 * creates a unique ident by adding a number to a tag
173 * @param tag the tag string, must contain a %d if a number
176 static ident *unique_id(const char *tag)
178 static unsigned id = 0;
181 snprintf(str, sizeof(str), tag, ++id);
182 return new_id_from_str(str);
186 * Get a primitive type for a mode.
188 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
190 pmap_entry *e = pmap_find(types, mode);
195 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
196 res = new_type_primitive(new_id_from_str(buf), mode);
197 set_type_alignment_bytes(res, 16);
198 pmap_insert(types, mode, res);
206 * Get an entity that is initialized with a tarval
208 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
210 tarval *tv = get_Const_tarval(cnst);
211 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
216 ir_mode *mode = get_irn_mode(cnst);
217 ir_type *tp = get_Const_type(cnst);
218 if (tp == firm_unknown_type)
219 tp = get_prim_type(cg->isa->types, mode);
221 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
223 set_entity_ld_ident(res, get_entity_ident(res));
224 set_entity_visibility(res, visibility_local);
225 set_entity_variability(res, variability_constant);
226 set_entity_allocation(res, allocation_static);
228 /* we create a new entity here: It's initialization must resist on the
230 rem = current_ir_graph;
231 current_ir_graph = get_const_code_irg();
232 set_atomic_ent_value(res, new_Const_type(tv, tp));
233 current_ir_graph = rem;
235 pmap_insert(cg->isa->tv_ent, tv, res);
243 static int is_Const_0(ir_node *node) {
247 return classify_Const(node) == CNST_NULL;
250 static int is_Const_1(ir_node *node) {
254 return classify_Const(node) == CNST_ONE;
258 * Transforms a Const.
260 static ir_node *gen_Const(ir_node *node) {
261 ir_graph *irg = current_ir_graph;
262 ir_node *block = be_transform_node(get_nodes_block(node));
263 dbg_info *dbgi = get_irn_dbg_info(node);
264 ir_mode *mode = get_irn_mode(node);
266 if (mode_is_float(mode)) {
268 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
269 ir_node *nomem = new_NoMem();
274 if (! USE_SSE2(env_cg)) {
275 cnst_classify_t clss = classify_Const(node);
277 if (clss == CNST_NULL) {
278 load = new_rd_ia32_vfldz(dbgi, irg, block);
280 } else if (clss == CNST_ONE) {
281 load = new_rd_ia32_vfld1(dbgi, irg, block);
284 floatent = get_entity_for_tv(env_cg, node);
286 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
287 set_ia32_am_support(load, ia32_am_Source);
288 set_ia32_op_type(load, ia32_AddrModeS);
289 set_ia32_am_flavour(load, ia32_am_N);
290 set_ia32_am_sc(load, floatent);
291 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
292 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
294 set_ia32_ls_mode(load, mode);
296 floatent = get_entity_for_tv(env_cg, node);
298 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
299 set_ia32_am_support(load, ia32_am_Source);
300 set_ia32_op_type(load, ia32_AddrModeS);
301 set_ia32_am_flavour(load, ia32_am_N);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_ls_mode(load, mode);
304 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
306 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
323 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
326 if (get_irg_start_block(irg) == block) {
327 add_irn_dep(cnst, get_irg_frame(irg));
330 set_ia32_Const_attr(cnst, node);
331 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
336 return new_r_Bad(irg);
340 * Transforms a SymConst.
342 static ir_node *gen_SymConst(ir_node *node) {
343 ir_graph *irg = current_ir_graph;
344 ir_node *block = be_transform_node(get_nodes_block(node));
345 dbg_info *dbgi = get_irn_dbg_info(node);
346 ir_mode *mode = get_irn_mode(node);
349 if (mode_is_float(mode)) {
351 if (USE_SSE2(env_cg))
352 cnst = new_rd_ia32_xConst(dbgi, irg, block);
354 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
355 //set_ia32_ls_mode(cnst, mode);
356 set_ia32_ls_mode(cnst, mode_E);
358 cnst = new_rd_ia32_Const(dbgi, irg, block);
361 /* Const Nodes before the initial IncSP are a bad idea, because
362 * they could be spilled and we have no SP ready at that point yet
364 if (get_irg_start_block(irg) == block) {
365 add_irn_dep(cnst, get_irg_frame(irg));
368 set_ia32_Const_attr(cnst, node);
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
376 * SSE convert of an integer node into a floating point node.
378 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
379 ir_graph *irg, ir_node *block,
380 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
382 ir_node *noreg = ia32_new_NoReg_gp(cg);
383 ir_node *nomem = new_rd_NoMem(irg);
384 ir_node *old_pred = get_Cmp_left(old_node);
385 ir_mode *in_mode = get_irn_mode(old_pred);
386 int in_bits = get_mode_size_bits(in_mode);
387 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
389 set_ia32_ls_mode(conv, tgt_mode);
391 set_ia32_am_support(conv, ia32_am_Source);
393 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
399 * SSE convert of an float node into a double node.
401 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
402 ir_graph *irg, ir_node *block,
403 ir_node *in, ir_node *old_node)
405 ir_node *noreg = ia32_new_NoReg_gp(cg);
406 ir_node *nomem = new_rd_NoMem(irg);
407 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
409 set_ia32_am_support(conv, ia32_am_Source);
410 set_ia32_ls_mode(conv, mode_xmm);
411 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
417 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
418 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
419 static const struct {
421 const char *ent_name;
422 const char *cnst_str;
423 } names [ia32_known_const_max] = {
424 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
425 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
426 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
427 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
429 static ir_entity *ent_cache[ia32_known_const_max];
431 const char *tp_name, *ent_name, *cnst_str;
439 ent_name = names[kct].ent_name;
440 if (! ent_cache[kct]) {
441 tp_name = names[kct].tp_name;
442 cnst_str = names[kct].cnst_str;
444 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
446 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
447 tp = new_type_primitive(new_id_from_str(tp_name), mode);
448 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
450 set_entity_ld_ident(ent, get_entity_ident(ent));
451 set_entity_visibility(ent, visibility_local);
452 set_entity_variability(ent, variability_constant);
453 set_entity_allocation(ent, allocation_static);
455 /* we create a new entity here: It's initialization must resist on the
457 rem = current_ir_graph;
458 current_ir_graph = get_const_code_irg();
459 cnst = new_Const(mode, tv);
460 current_ir_graph = rem;
462 set_atomic_ent_value(ent, cnst);
464 /* cache the entry */
465 ent_cache[kct] = ent;
468 return ent_cache[kct];
473 * Prints the old node name on cg obst and returns a pointer to it.
475 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
476 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
478 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
479 obstack_1grow(isa->name_obst, 0);
480 return obstack_finish(isa->name_obst);
484 /* determine if one operator is an Imm */
485 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
487 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
489 return is_ia32_Cnst(op2) ? op2 : NULL;
493 /* determine if one operator is not an Imm */
494 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
495 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
498 static void fold_immediate(ir_node *node, int in1, int in2) {
502 if (!(env_cg->opt & IA32_OPT_IMMOPS))
505 left = get_irn_n(node, in1);
506 right = get_irn_n(node, in2);
507 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
508 /* we can only set right operand to immediate */
509 if(!is_ia32_commutative(node))
511 /* exchange left/right */
512 set_irn_n(node, in1, right);
513 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
514 copy_ia32_Immop_attr(node, left);
515 } else if(is_ia32_Cnst(right)) {
516 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
517 copy_ia32_Immop_attr(node, right);
522 clear_ia32_commutative(node);
523 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
527 * Construct a standard binary operation, set AM and immediate if required.
529 * @param op1 The first operand
530 * @param op2 The second operand
531 * @param func The node constructor function
532 * @return The constructed ia32 node.
534 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
535 construct_binop_func *func, int commutative)
537 ir_node *block = be_transform_node(get_nodes_block(node));
538 ir_node *new_op1 = NULL;
539 ir_node *new_op2 = NULL;
540 ir_node *new_node = NULL;
541 ir_graph *irg = current_ir_graph;
542 dbg_info *dbgi = get_irn_dbg_info(node);
543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
544 ir_node *nomem = new_NoMem();
547 new_op2 = try_create_Immediate(op1, 0);
548 if(new_op2 != NULL) {
549 new_op1 = be_transform_node(op2);
554 if(new_op2 == NULL) {
555 new_op2 = try_create_Immediate(op2, 0);
556 if(new_op2 != NULL) {
557 new_op1 = be_transform_node(op1);
562 if(new_op2 == NULL) {
563 new_op1 = be_transform_node(op1);
564 new_op2 = be_transform_node(op2);
567 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
568 if (func == new_rd_ia32_IMul) {
569 set_ia32_am_support(new_node, ia32_am_Source);
571 set_ia32_am_support(new_node, ia32_am_Full);
574 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
576 set_ia32_commutative(new_node);
583 * Construct a standard binary operation, set AM and immediate if required.
585 * @param op1 The first operand
586 * @param op2 The second operand
587 * @param func The node constructor function
588 * @return The constructed ia32 node.
590 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
591 construct_binop_func *func)
593 ir_node *block = be_transform_node(get_nodes_block(node));
594 ir_node *new_op1 = be_transform_node(op1);
595 ir_node *new_op2 = be_transform_node(op2);
596 ir_node *new_node = NULL;
597 dbg_info *dbgi = get_irn_dbg_info(node);
598 ir_graph *irg = current_ir_graph;
599 ir_mode *mode = get_irn_mode(node);
600 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
601 ir_node *nomem = new_NoMem();
603 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
604 set_ia32_am_support(new_node, ia32_am_Source);
605 if (is_op_commutative(get_irn_op(node))) {
606 set_ia32_commutative(new_node);
608 if (USE_SSE2(env_cg)) {
609 set_ia32_ls_mode(new_node, mode);
612 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
619 * Construct a shift/rotate binary operation, sets AM and immediate if required.
621 * @param op1 The first operand
622 * @param op2 The second operand
623 * @param func The node constructor function
624 * @return The constructed ia32 node.
626 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
627 construct_binop_func *func)
629 ir_node *block = be_transform_node(get_nodes_block(node));
630 ir_node *new_op1 = be_transform_node(op1);
632 ir_node *new_op = NULL;
633 dbg_info *dbgi = get_irn_dbg_info(node);
634 ir_graph *irg = current_ir_graph;
635 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
636 ir_node *nomem = new_NoMem();
638 assert(! mode_is_float(get_irn_mode(node))
639 && "Shift/Rotate with float not supported");
641 new_op2 = try_create_Immediate(op2, 'N');
642 if(new_op2 == NULL) {
643 new_op2 = be_transform_node(op2);
646 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
649 set_ia32_am_support(new_op, ia32_am_Dest);
651 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
653 set_ia32_emit_cl(new_op);
660 * Construct a standard unary operation, set AM and immediate if required.
662 * @param op The operand
663 * @param func The node constructor function
664 * @return The constructed ia32 node.
666 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
668 ir_node *block = be_transform_node(get_nodes_block(node));
669 ir_node *new_op = be_transform_node(op);
670 ir_node *new_node = NULL;
671 ir_graph *irg = current_ir_graph;
672 dbg_info *dbgi = get_irn_dbg_info(node);
673 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
674 ir_node *nomem = new_NoMem();
676 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
677 DB((dbg, LEVEL_1, "INT unop ..."));
678 set_ia32_am_support(new_node, ia32_am_Dest);
680 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
686 * Creates an ia32 Add.
688 * @return the created ia32 Add node
690 static ir_node *gen_Add(ir_node *node) {
691 ir_node *block = be_transform_node(get_nodes_block(node));
692 ir_node *op1 = get_Add_left(node);
693 ir_node *new_op1 = be_transform_node(op1);
694 ir_node *op2 = get_Add_right(node);
695 ir_node *new_op2 = be_transform_node(op2);
696 ir_node *new_op = NULL;
697 ir_graph *irg = current_ir_graph;
698 dbg_info *dbgi = get_irn_dbg_info(node);
699 ir_mode *mode = get_irn_mode(node);
700 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
701 ir_node *nomem = new_NoMem();
702 ir_node *expr_op, *imm_op;
704 /* Check if immediate optimization is on and */
705 /* if it's an operation with immediate. */
706 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
707 expr_op = get_expr_op(new_op1, new_op2);
709 assert((expr_op || imm_op) && "invalid operands");
711 if (mode_is_float(mode)) {
713 if (USE_SSE2(env_cg))
714 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
716 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
721 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
722 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
724 /* No expr_op means, that we have two const - one symconst and */
725 /* one tarval or another symconst - because this case is not */
726 /* covered by constant folding */
727 /* We need to check for: */
728 /* 1) symconst + const -> becomes a LEA */
729 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
730 /* linker doesn't support two symconsts */
732 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
733 /* this is the 2nd case */
734 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
735 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
736 set_ia32_am_flavour(new_op, ia32_am_B);
737 set_ia32_am_support(new_op, ia32_am_Source);
738 set_ia32_op_type(new_op, ia32_AddrModeS);
740 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 } else if (tp1 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op2);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
750 add_ia32_am_offs_int(new_op, offs);
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_am_support(new_op, ia32_am_Source);
753 set_ia32_op_type(new_op, ia32_AddrModeS);
754 } else if (tp2 == ia32_ImmSymConst) {
755 tarval *tv = get_ia32_Immop_tarval(new_op1);
756 long offs = get_tarval_long(tv);
758 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
759 add_irn_dep(new_op, get_irg_frame(irg));
760 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
762 add_ia32_am_offs_int(new_op, offs);
763 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
764 set_ia32_am_flavour(new_op, ia32_am_OB);
765 set_ia32_am_support(new_op, ia32_am_Source);
766 set_ia32_op_type(new_op, ia32_AddrModeS);
768 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
769 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
770 tarval *restv = tarval_add(tv1, tv2);
772 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
774 new_op = new_rd_ia32_Const(dbgi, irg, block);
775 set_ia32_Const_tarval(new_op, restv);
776 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
782 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
783 tarval_classification_t class_tv, class_negtv;
784 tarval *tv = get_ia32_Immop_tarval(imm_op);
786 /* optimize tarvals */
787 class_tv = classify_tarval(tv);
788 class_negtv = classify_tarval(tarval_neg(tv));
790 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
791 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
792 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
793 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
795 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
796 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
797 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
798 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
804 /* This is a normal add */
805 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
808 set_ia32_am_support(new_op, ia32_am_Full);
809 set_ia32_commutative(new_op);
811 fold_immediate(new_op, 2, 3);
813 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
819 static ir_node *create_ia32_Mul(ir_node *node) {
820 ir_graph *irg = current_ir_graph;
821 dbg_info *dbgi = get_irn_dbg_info(node);
822 ir_node *block = be_transform_node(get_nodes_block(node));
823 ir_node *op1 = get_Mul_left(node);
824 ir_node *op2 = get_Mul_right(node);
825 ir_node *new_op1 = be_transform_node(op1);
826 ir_node *new_op2 = be_transform_node(op2);
827 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
828 ir_node *proj_EAX, *proj_EDX, *res;
831 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
832 set_ia32_commutative(res);
833 set_ia32_am_support(res, ia32_am_Source);
835 /* imediates are not supported, so no fold_immediate */
836 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
837 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
841 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
849 * Creates an ia32 Mul.
851 * @return the created ia32 Mul node
853 static ir_node *gen_Mul(ir_node *node) {
854 ir_node *op1 = get_Mul_left(node);
855 ir_node *op2 = get_Mul_right(node);
856 ir_mode *mode = get_irn_mode(node);
858 if (mode_is_float(mode)) {
860 if (USE_SSE2(env_cg))
861 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
863 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
867 for the lower 32bit of the result it doesn't matter whether we use
868 signed or unsigned multiplication so we use IMul as it has fewer
871 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
875 * Creates an ia32 Mulh.
876 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
877 * this result while Mul returns the lower 32 bit.
879 * @return the created ia32 Mulh node
881 static ir_node *gen_Mulh(ir_node *node) {
882 ir_node *block = be_transform_node(get_nodes_block(node));
883 ir_node *op1 = get_irn_n(node, 0);
884 ir_node *new_op1 = be_transform_node(op1);
885 ir_node *op2 = get_irn_n(node, 1);
886 ir_node *new_op2 = be_transform_node(op2);
887 ir_graph *irg = current_ir_graph;
888 dbg_info *dbgi = get_irn_dbg_info(node);
889 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
890 ir_mode *mode = get_irn_mode(node);
891 ir_node *proj_EAX, *proj_EDX, *res;
894 assert(!mode_is_float(mode) && "Mulh with float not supported");
895 if (mode_is_signed(mode)) {
896 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
898 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
901 set_ia32_commutative(res);
902 set_ia32_am_support(res, ia32_am_Source);
904 set_ia32_am_support(res, ia32_am_Source);
906 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
907 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
911 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
919 * Creates an ia32 And.
921 * @return The created ia32 And node
923 static ir_node *gen_And(ir_node *node) {
924 ir_node *op1 = get_And_left(node);
925 ir_node *op2 = get_And_right(node);
927 assert (! mode_is_float(get_irn_mode(node)));
928 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
934 * Creates an ia32 Or.
936 * @return The created ia32 Or node
938 static ir_node *gen_Or(ir_node *node) {
939 ir_node *op1 = get_Or_left(node);
940 ir_node *op2 = get_Or_right(node);
942 assert (! mode_is_float(get_irn_mode(node)));
943 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
949 * Creates an ia32 Eor.
951 * @return The created ia32 Eor node
953 static ir_node *gen_Eor(ir_node *node) {
954 ir_node *op1 = get_Eor_left(node);
955 ir_node *op2 = get_Eor_right(node);
957 assert(! mode_is_float(get_irn_mode(node)));
958 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
964 * Creates an ia32 Max.
966 * @return the created ia32 Max node
968 static ir_node *gen_Max(ir_node *node) {
969 ir_node *block = be_transform_node(get_nodes_block(node));
970 ir_node *op1 = get_irn_n(node, 0);
971 ir_node *new_op1 = be_transform_node(op1);
972 ir_node *op2 = get_irn_n(node, 1);
973 ir_node *new_op2 = be_transform_node(op2);
974 ir_graph *irg = current_ir_graph;
975 ir_mode *mode = get_irn_mode(node);
976 dbg_info *dbgi = get_irn_dbg_info(node);
977 ir_mode *op_mode = get_irn_mode(op1);
980 assert(get_mode_size_bits(mode) == 32);
982 if (mode_is_float(mode)) {
984 if (USE_SSE2(env_cg)) {
985 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
987 panic("Can't create Max node");
990 long pnc = pn_Cmp_Gt;
991 if (! mode_is_signed(op_mode)) {
992 pnc |= ia32_pn_Cmp_Unsigned;
994 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
995 new_op1, new_op2, pnc);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1003 * Creates an ia32 Min.
1005 * @return the created ia32 Min node
1007 static ir_node *gen_Min(ir_node *node) {
1008 ir_node *block = be_transform_node(get_nodes_block(node));
1009 ir_node *op1 = get_irn_n(node, 0);
1010 ir_node *new_op1 = be_transform_node(op1);
1011 ir_node *op2 = get_irn_n(node, 1);
1012 ir_node *new_op2 = be_transform_node(op2);
1013 ir_graph *irg = current_ir_graph;
1014 ir_mode *mode = get_irn_mode(node);
1015 dbg_info *dbgi = get_irn_dbg_info(node);
1016 ir_mode *op_mode = get_irn_mode(op1);
1019 assert(get_mode_size_bits(mode) == 32);
1021 if (mode_is_float(mode)) {
1023 if (USE_SSE2(env_cg)) {
1024 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1026 panic("can't create Min node");
1029 long pnc = pn_Cmp_Lt;
1030 if (! mode_is_signed(op_mode)) {
1031 pnc |= ia32_pn_Cmp_Unsigned;
1033 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1034 new_op1, new_op2, pnc);
1036 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1043 * Creates an ia32 Sub.
1045 * @return The created ia32 Sub node
1047 static ir_node *gen_Sub(ir_node *node) {
1048 ir_node *block = be_transform_node(get_nodes_block(node));
1049 ir_node *op1 = get_Sub_left(node);
1050 ir_node *new_op1 = be_transform_node(op1);
1051 ir_node *op2 = get_Sub_right(node);
1052 ir_node *new_op2 = be_transform_node(op2);
1053 ir_node *new_op = NULL;
1054 ir_graph *irg = current_ir_graph;
1055 dbg_info *dbgi = get_irn_dbg_info(node);
1056 ir_mode *mode = get_irn_mode(node);
1057 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1058 ir_node *nomem = new_NoMem();
1059 ir_node *expr_op, *imm_op;
1061 /* Check if immediate optimization is on and */
1062 /* if it's an operation with immediate. */
1063 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1064 expr_op = get_expr_op(new_op1, new_op2);
1066 assert((expr_op || imm_op) && "invalid operands");
1068 if (mode_is_float(mode)) {
1070 if (USE_SSE2(env_cg))
1071 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1073 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1078 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1079 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1081 /* No expr_op means, that we have two const - one symconst and */
1082 /* one tarval or another symconst - because this case is not */
1083 /* covered by constant folding */
1084 /* We need to check for: */
1085 /* 1) symconst - const -> becomes a LEA */
1086 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1087 /* linker doesn't support two symconsts */
1088 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1089 /* this is the 2nd case */
1090 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1091 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1092 set_ia32_am_sc_sign(new_op);
1093 set_ia32_am_flavour(new_op, ia32_am_B);
1095 DBG_OPT_LEA3(op1, op2, node, new_op);
1096 } else if (tp1 == ia32_ImmSymConst) {
1097 tarval *tv = get_ia32_Immop_tarval(new_op2);
1098 long offs = get_tarval_long(tv);
1100 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1101 add_irn_dep(new_op, get_irg_frame(irg));
1102 DBG_OPT_LEA3(op1, op2, node, new_op);
1104 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1105 add_ia32_am_offs_int(new_op, -offs);
1106 set_ia32_am_flavour(new_op, ia32_am_OB);
1107 set_ia32_am_support(new_op, ia32_am_Source);
1108 set_ia32_op_type(new_op, ia32_AddrModeS);
1109 } else if (tp2 == ia32_ImmSymConst) {
1110 tarval *tv = get_ia32_Immop_tarval(new_op1);
1111 long offs = get_tarval_long(tv);
1113 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1114 add_irn_dep(new_op, get_irg_frame(irg));
1115 DBG_OPT_LEA3(op1, op2, node, new_op);
1117 add_ia32_am_offs_int(new_op, offs);
1118 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1119 set_ia32_am_sc_sign(new_op);
1120 set_ia32_am_flavour(new_op, ia32_am_OB);
1121 set_ia32_am_support(new_op, ia32_am_Source);
1122 set_ia32_op_type(new_op, ia32_AddrModeS);
1124 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1125 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1126 tarval *restv = tarval_sub(tv1, tv2);
1128 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1130 new_op = new_rd_ia32_Const(dbgi, irg, block);
1131 set_ia32_Const_tarval(new_op, restv);
1132 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1135 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1137 } else if (imm_op) {
1138 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1139 tarval_classification_t class_tv, class_negtv;
1140 tarval *tv = get_ia32_Immop_tarval(imm_op);
1142 /* optimize tarvals */
1143 class_tv = classify_tarval(tv);
1144 class_negtv = classify_tarval(tarval_neg(tv));
1146 if (class_tv == TV_CLASSIFY_ONE) {
1147 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1148 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1149 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1151 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1152 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1153 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1154 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1160 /* This is a normal sub */
1161 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1163 /* set AM support */
1164 set_ia32_am_support(new_op, ia32_am_Full);
1166 fold_immediate(new_op, 2, 3);
1168 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1176 * Generates an ia32 DivMod with additional infrastructure for the
1177 * register allocator if needed.
1179 * @param dividend -no comment- :)
1180 * @param divisor -no comment- :)
1181 * @param dm_flav flavour_Div/Mod/DivMod
1182 * @return The created ia32 DivMod node
1184 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1185 ir_node *divisor, ia32_op_flavour_t dm_flav)
1187 ir_node *block = be_transform_node(get_nodes_block(node));
1188 ir_node *new_dividend = be_transform_node(dividend);
1189 ir_node *new_divisor = be_transform_node(divisor);
1190 ir_graph *irg = current_ir_graph;
1191 dbg_info *dbgi = get_irn_dbg_info(node);
1192 ir_mode *mode = get_irn_mode(node);
1193 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1194 ir_node *res, *proj_div, *proj_mod;
1195 ir_node *sign_extension;
1196 ir_node *in_keep[2];
1197 ir_node *mem, *new_mem;
1198 ir_node *projs[pn_DivMod_max];
1201 ia32_collect_Projs(node, projs, pn_DivMod_max);
1203 proj_div = proj_mod = NULL;
1207 mem = get_Div_mem(node);
1208 mode = get_Div_resmode(node);
1209 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1210 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1213 mem = get_Mod_mem(node);
1214 mode = get_Mod_resmode(node);
1215 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1216 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1218 case flavour_DivMod:
1219 mem = get_DivMod_mem(node);
1220 mode = get_DivMod_resmode(node);
1221 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1222 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1223 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1226 panic("invalid divmod flavour!");
1228 new_mem = be_transform_node(mem);
1230 if (mode_is_signed(mode)) {
1231 /* in signed mode, we need to sign extend the dividend */
1232 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1234 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1235 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1237 add_irn_dep(sign_extension, get_irg_frame(irg));
1240 if (mode_is_signed(mode)) {
1241 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1242 sign_extension, new_divisor, new_mem, dm_flav);
1244 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1245 sign_extension, new_divisor, new_mem, dm_flav);
1248 set_ia32_exc_label(res, has_exc);
1249 set_irn_pinned(res, get_irn_pinned(node));
1251 /* Matze: code can't handle this at the moment... */
1253 /* set AM support */
1254 set_ia32_am_support(res, ia32_am_Source);
1257 /* check, which Proj-Keep, we need to add */
1259 if (proj_div == NULL) {
1260 /* We have only mod result: add div res Proj-Keep */
1261 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1264 if (proj_mod == NULL) {
1265 /* We have only div result: add mod res Proj-Keep */
1266 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1270 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1272 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1279 * Wrapper for generate_DivMod. Sets flavour_Mod.
1282 static ir_node *gen_Mod(ir_node *node) {
1283 return generate_DivMod(node, get_Mod_left(node),
1284 get_Mod_right(node), flavour_Mod);
1288 * Wrapper for generate_DivMod. Sets flavour_Div.
1291 static ir_node *gen_Div(ir_node *node) {
1292 return generate_DivMod(node, get_Div_left(node),
1293 get_Div_right(node), flavour_Div);
1297 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1299 static ir_node *gen_DivMod(ir_node *node) {
1300 return generate_DivMod(node, get_DivMod_left(node),
1301 get_DivMod_right(node), flavour_DivMod);
1307 * Creates an ia32 floating Div.
1309 * @return The created ia32 xDiv node
1311 static ir_node *gen_Quot(ir_node *node) {
1312 ir_node *block = be_transform_node(get_nodes_block(node));
1313 ir_node *op1 = get_Quot_left(node);
1314 ir_node *new_op1 = be_transform_node(op1);
1315 ir_node *op2 = get_Quot_right(node);
1316 ir_node *new_op2 = be_transform_node(op2);
1317 ir_graph *irg = current_ir_graph;
1318 dbg_info *dbgi = get_irn_dbg_info(node);
1319 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1320 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1324 if (USE_SSE2(env_cg)) {
1325 ir_mode *mode = get_irn_mode(op1);
1326 if (is_ia32_xConst(new_op2)) {
1327 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1328 set_ia32_am_support(new_op, ia32_am_None);
1329 copy_ia32_Immop_attr(new_op, new_op2);
1331 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1332 // Matze: disabled for now, spillslot coalescer fails
1333 //set_ia32_am_support(new_op, ia32_am_Source);
1335 set_ia32_ls_mode(new_op, mode);
1337 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1338 // Matze: disabled for now (spillslot coalescer fails)
1339 //set_ia32_am_support(new_op, ia32_am_Source);
1341 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1347 * Creates an ia32 Shl.
1349 * @return The created ia32 Shl node
1351 static ir_node *gen_Shl(ir_node *node) {
1352 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1359 * Creates an ia32 Shr.
1361 * @return The created ia32 Shr node
1363 static ir_node *gen_Shr(ir_node *node) {
1364 return gen_shift_binop(node, get_Shr_left(node),
1365 get_Shr_right(node), new_rd_ia32_Shr);
1371 * Creates an ia32 Sar.
1373 * @return The created ia32 Shrs node
1375 static ir_node *gen_Shrs(ir_node *node) {
1376 ir_node *left = get_Shrs_left(node);
1377 ir_node *right = get_Shrs_right(node);
1378 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1379 tarval *tv = get_Const_tarval(right);
1380 long val = get_tarval_long(tv);
1382 /* this is a sign extension */
1383 ir_graph *irg = current_ir_graph;
1384 dbg_info *dbgi = get_irn_dbg_info(node);
1385 ir_node *block = be_transform_node(get_nodes_block(node));
1387 ir_node *new_op = be_transform_node(op);
1389 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1393 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1399 * Creates an ia32 RotL.
1401 * @param op1 The first operator
1402 * @param op2 The second operator
1403 * @return The created ia32 RotL node
1405 static ir_node *gen_RotL(ir_node *node,
1406 ir_node *op1, ir_node *op2) {
1407 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1413 * Creates an ia32 RotR.
1414 * NOTE: There is no RotR with immediate because this would always be a RotL
1415 * "imm-mode_size_bits" which can be pre-calculated.
1417 * @param op1 The first operator
1418 * @param op2 The second operator
1419 * @return The created ia32 RotR node
1421 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1423 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1429 * Creates an ia32 RotR or RotL (depending on the found pattern).
1431 * @return The created ia32 RotL or RotR node
1433 static ir_node *gen_Rot(ir_node *node) {
1434 ir_node *rotate = NULL;
1435 ir_node *op1 = get_Rot_left(node);
1436 ir_node *op2 = get_Rot_right(node);
1438 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1439 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1440 that means we can create a RotR instead of an Add and a RotL */
1442 if (get_irn_op(op2) == op_Add) {
1444 ir_node *left = get_Add_left(add);
1445 ir_node *right = get_Add_right(add);
1446 if (is_Const(right)) {
1447 tarval *tv = get_Const_tarval(right);
1448 ir_mode *mode = get_irn_mode(node);
1449 long bits = get_mode_size_bits(mode);
1451 if (get_irn_op(left) == op_Minus &&
1452 tarval_is_long(tv) &&
1453 get_tarval_long(tv) == bits)
1455 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1456 rotate = gen_RotR(node, op1, get_Minus_op(left));
1461 if (rotate == NULL) {
1462 rotate = gen_RotL(node, op1, op2);
1471 * Transforms a Minus node.
1473 * @param op The Minus operand
1474 * @return The created ia32 Minus node
1476 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1477 ir_node *block = be_transform_node(get_nodes_block(node));
1478 ir_graph *irg = current_ir_graph;
1479 dbg_info *dbgi = get_irn_dbg_info(node);
1480 ir_mode *mode = get_irn_mode(node);
1485 if (mode_is_float(mode)) {
1486 ir_node *new_op = be_transform_node(op);
1488 if (USE_SSE2(env_cg)) {
1489 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1490 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1491 ir_node *nomem = new_rd_NoMem(irg);
1493 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1495 size = get_mode_size_bits(mode);
1496 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1498 set_ia32_am_sc(res, ent);
1499 set_ia32_op_type(res, ia32_AddrModeS);
1500 set_ia32_ls_mode(res, mode);
1502 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1505 res = gen_unop(node, op, new_rd_ia32_Neg);
1508 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1514 * Transforms a Minus node.
1516 * @return The created ia32 Minus node
1518 static ir_node *gen_Minus(ir_node *node) {
1519 return gen_Minus_ex(node, get_Minus_op(node));
1524 * Transforms a Not node.
1526 * @return The created ia32 Not node
1528 static ir_node *gen_Not(ir_node *node) {
1529 ir_node *op = get_Not_op(node);
1531 assert (! mode_is_float(get_irn_mode(node)));
1532 return gen_unop(node, op, new_rd_ia32_Not);
1538 * Transforms an Abs node.
1540 * @return The created ia32 Abs node
1542 static ir_node *gen_Abs(ir_node *node) {
1543 ir_node *block = be_transform_node(get_nodes_block(node));
1544 ir_node *op = get_Abs_op(node);
1545 ir_node *new_op = be_transform_node(op);
1546 ir_graph *irg = current_ir_graph;
1547 dbg_info *dbgi = get_irn_dbg_info(node);
1548 ir_mode *mode = get_irn_mode(node);
1549 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1550 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1551 ir_node *nomem = new_NoMem();
1556 if (mode_is_float(mode)) {
1558 if (USE_SSE2(env_cg)) {
1559 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1561 size = get_mode_size_bits(mode);
1562 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1564 set_ia32_am_sc(res, ent);
1566 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1568 set_ia32_op_type(res, ia32_AddrModeS);
1569 set_ia32_ls_mode(res, mode);
1572 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1573 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1577 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1578 SET_IA32_ORIG_NODE(sign_extension,
1579 ia32_get_old_node_name(env_cg, node));
1581 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1582 sign_extension, nomem);
1583 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1585 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1586 sign_extension, nomem);
1587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1596 * Transforms a Load.
1598 * @return the created ia32 Load node
1600 static ir_node *gen_Load(ir_node *node) {
1601 ir_node *block = be_transform_node(get_nodes_block(node));
1602 ir_node *ptr = get_Load_ptr(node);
1603 ir_node *new_ptr = be_transform_node(ptr);
1604 ir_node *mem = get_Load_mem(node);
1605 ir_node *new_mem = be_transform_node(mem);
1606 ir_graph *irg = current_ir_graph;
1607 dbg_info *dbgi = get_irn_dbg_info(node);
1608 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1609 ir_mode *mode = get_Load_mode(node);
1611 ir_node *lptr = new_ptr;
1614 ir_node *projs[pn_Load_max];
1615 ia32_am_flavour_t am_flav = ia32_am_B;
1617 ia32_collect_Projs(node, projs, pn_Load_max);
1619 /* address might be a constant (symconst or absolute address) */
1620 if (is_ia32_Const(new_ptr)) {
1625 if (mode_is_float(mode)) {
1627 if (USE_SSE2(env_cg)) {
1628 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1629 res_mode = mode_xmm;
1631 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1632 res_mode = mode_vfp;
1635 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1640 check for special case: the loaded value might not be used
1642 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1643 /* add a result proj and a Keep to produce a pseudo use */
1644 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1646 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1649 /* base is a constant address */
1651 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1652 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1653 am_flav = ia32_am_N;
1655 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1656 long offs = get_tarval_long(tv);
1658 add_ia32_am_offs_int(new_op, offs);
1659 am_flav = ia32_am_O;
1663 set_irn_pinned(new_op, get_irn_pinned(node));
1664 set_ia32_am_support(new_op, ia32_am_Source);
1665 set_ia32_op_type(new_op, ia32_AddrModeS);
1666 set_ia32_am_flavour(new_op, am_flav);
1667 set_ia32_ls_mode(new_op, mode);
1669 /* make sure we are scheduled behind the initial IncSP/Barrier
1670 * to avoid spills being placed before it
1672 if (block == get_irg_start_block(irg)) {
1673 add_irn_dep(new_op, get_irg_frame(irg));
1676 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1677 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1685 * Transforms a Store.
1687 * @return the created ia32 Store node
1689 static ir_node *gen_Store(ir_node *node) {
1690 ir_node *block = be_transform_node(get_nodes_block(node));
1691 ir_node *ptr = get_Store_ptr(node);
1692 ir_node *new_ptr = be_transform_node(ptr);
1693 ir_node *val = get_Store_value(node);
1695 ir_node *mem = get_Store_mem(node);
1696 ir_node *new_mem = be_transform_node(mem);
1697 ir_graph *irg = current_ir_graph;
1698 dbg_info *dbgi = get_irn_dbg_info(node);
1699 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1700 ir_node *sptr = new_ptr;
1701 ir_mode *mode = get_irn_mode(val);
1704 ia32_am_flavour_t am_flav = ia32_am_B;
1706 /* address might be a constant (symconst or absolute address) */
1707 if (is_ia32_Const(new_ptr)) {
1712 if (mode_is_float(mode)) {
1715 new_val = be_transform_node(val);
1716 if (USE_SSE2(env_cg)) {
1717 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1720 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1724 new_val = try_create_Immediate(val, 0);
1725 if(new_val == NULL) {
1726 new_val = be_transform_node(val);
1729 if (get_mode_size_bits(mode) == 8) {
1730 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1733 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1738 /* base is an constant address */
1740 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1741 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1742 am_flav = ia32_am_N;
1744 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1745 long offs = get_tarval_long(tv);
1747 add_ia32_am_offs_int(new_op, offs);
1748 am_flav = ia32_am_O;
1752 set_irn_pinned(new_op, get_irn_pinned(node));
1753 set_ia32_am_support(new_op, ia32_am_Dest);
1754 set_ia32_op_type(new_op, ia32_AddrModeD);
1755 set_ia32_am_flavour(new_op, am_flav);
1756 set_ia32_ls_mode(new_op, mode);
1758 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1759 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1767 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1769 * @return The transformed node.
1771 static ir_node *gen_Cond(ir_node *node) {
1772 ir_node *block = be_transform_node(get_nodes_block(node));
1773 ir_graph *irg = current_ir_graph;
1774 dbg_info *dbgi = get_irn_dbg_info(node);
1775 ir_node *sel = get_Cond_selector(node);
1776 ir_mode *sel_mode = get_irn_mode(sel);
1777 ir_node *res = NULL;
1778 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1779 ir_node *cnst, *expr;
1781 if (is_Proj(sel) && sel_mode == mode_b) {
1782 ir_node *pred = get_Proj_pred(sel);
1783 ir_node *cmp_a = get_Cmp_left(pred);
1784 ir_node *new_cmp_a = be_transform_node(cmp_a);
1785 ir_node *cmp_b = get_Cmp_right(pred);
1786 ir_node *new_cmp_b = be_transform_node(cmp_b);
1787 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1788 ir_node *nomem = new_NoMem();
1790 int pnc = get_Proj_proj(sel);
1791 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1792 pnc |= ia32_pn_Cmp_Unsigned;
1795 /* check if we can use a CondJmp with immediate */
1796 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1797 expr = get_expr_op(new_cmp_a, new_cmp_b);
1799 if (cnst != NULL && expr != NULL) {
1800 /* immop has to be the right operand, we might need to flip pnc */
1801 if(cnst != new_cmp_b) {
1802 pnc = get_inversed_pnc(pnc);
1805 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1806 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1807 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1809 /* a Cmp A =/!= 0 */
1810 ir_node *op1 = expr;
1811 ir_node *op2 = expr;
1814 /* check, if expr is an only once used And operation */
1815 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1816 op1 = get_irn_n(expr, 2);
1817 op2 = get_irn_n(expr, 3);
1819 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1821 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1822 set_ia32_pncode(res, pnc);
1825 copy_ia32_Immop_attr(res, expr);
1828 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1833 if (mode_is_float(cmp_mode)) {
1835 if (USE_SSE2(env_cg)) {
1836 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1837 set_ia32_ls_mode(res, cmp_mode);
1843 assert(get_mode_size_bits(cmp_mode) == 32);
1844 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1846 copy_ia32_Immop_attr(res, cnst);
1849 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env_cg)) {
1854 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1858 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1859 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1864 assert(get_mode_size_bits(cmp_mode) == 32);
1865 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1866 set_ia32_commutative(res);
1870 set_ia32_pncode(res, pnc);
1871 // Matze: disabled for now, because the default collect_spills_walker
1872 // is not able to detect the mode of the spilled value
1873 // moreover, the lea optimize phase freely exchanges left/right
1874 // without updating the pnc
1875 //set_ia32_am_support(res, ia32_am_Source);
1878 /* determine the smallest switch case value */
1879 ir_node *new_sel = be_transform_node(sel);
1880 int switch_min = INT_MAX;
1881 const ir_edge_t *edge;
1883 foreach_out_edge(node, edge) {
1884 int pn = get_Proj_proj(get_edge_src_irn(edge));
1885 switch_min = pn < switch_min ? pn : switch_min;
1889 /* if smallest switch case is not 0 we need an additional sub */
1890 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1891 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1892 add_ia32_am_offs_int(res, -switch_min);
1893 set_ia32_am_flavour(res, ia32_am_OB);
1894 set_ia32_am_support(res, ia32_am_Source);
1895 set_ia32_op_type(res, ia32_AddrModeS);
1898 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1899 set_ia32_pncode(res, get_Cond_defaultProj(node));
1902 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1909 * Transforms a CopyB node.
1911 * @return The transformed node.
1913 static ir_node *gen_CopyB(ir_node *node) {
1914 ir_node *block = be_transform_node(get_nodes_block(node));
1915 ir_node *src = get_CopyB_src(node);
1916 ir_node *new_src = be_transform_node(src);
1917 ir_node *dst = get_CopyB_dst(node);
1918 ir_node *new_dst = be_transform_node(dst);
1919 ir_node *mem = get_CopyB_mem(node);
1920 ir_node *new_mem = be_transform_node(mem);
1921 ir_node *res = NULL;
1922 ir_graph *irg = current_ir_graph;
1923 dbg_info *dbgi = get_irn_dbg_info(node);
1924 int size = get_type_size_bytes(get_CopyB_type(node));
1925 ir_mode *dst_mode = get_irn_mode(dst);
1926 ir_mode *src_mode = get_irn_mode(src);
1930 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1931 /* then we need the size explicitly in ECX. */
1932 if (size >= 32 * 4) {
1933 rem = size & 0x3; /* size % 4 */
1936 res = new_rd_ia32_Const(dbgi, irg, block);
1937 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1938 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1940 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1941 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1943 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1944 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1945 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1946 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1947 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1950 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1953 /* ok: now attach Proj's because movsd will destroy esi and edi */
1954 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1955 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1956 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1959 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1965 ir_node *gen_be_Copy(ir_node *node)
1967 ir_node *result = be_duplicate_node(node);
1968 ir_mode *mode = get_irn_mode(result);
1970 if (mode_needs_gp_reg(mode)) {
1971 set_irn_mode(result, mode_Iu);
1980 * Transforms a Mux node into CMov.
1982 * @return The transformed node.
1984 static ir_node *gen_Mux(ir_node *node) {
1985 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1986 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1988 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1994 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1995 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1996 ir_node *psi_default);
1999 * Transforms a Psi node into CMov.
2001 * @return The transformed node.
2003 static ir_node *gen_Psi(ir_node *node) {
2004 ir_node *block = be_transform_node(get_nodes_block(node));
2005 ir_node *psi_true = get_Psi_val(node, 0);
2006 ir_node *psi_default = get_Psi_default(node);
2007 ia32_code_gen_t *cg = env_cg;
2008 ir_graph *irg = current_ir_graph;
2009 dbg_info *dbgi = get_irn_dbg_info(node);
2010 ir_node *cond = get_Psi_cond(node, 0);
2011 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2012 ir_node *nomem = new_NoMem();
2014 ir_node *cmp, *cmp_a, *cmp_b;
2015 ir_node *new_cmp_a, *new_cmp_b;
2019 assert(get_Psi_n_conds(node) == 1);
2020 assert(get_irn_mode(cond) == mode_b);
2022 if(is_And(cond) || is_Or(cond)) {
2023 ir_node *new_cond = be_transform_node(cond);
2024 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
2025 arch_set_irn_register(env_cg->arch_env, zero,
2026 &ia32_gp_regs[REG_GP_NOREG]);
2028 /* we have to compare the result against zero */
2029 new_cmp_a = new_cond;
2034 cmp = get_Proj_pred(cond);
2035 cmp_a = get_Cmp_left(cmp);
2036 cmp_b = get_Cmp_right(cmp);
2037 cmp_mode = get_irn_mode(cmp_a);
2038 pnc = get_Proj_proj(cond);
2040 new_cmp_b = try_create_Immediate(cmp_b, 0);
2041 if(new_cmp_b == NULL) {
2042 new_cmp_b = try_create_Immediate(cmp_a, 0);
2043 if(new_cmp_b != NULL) {
2044 pnc = get_inversed_pnc(pnc);
2045 new_cmp_a = be_transform_node(cmp_b);
2048 new_cmp_a = be_transform_node(cmp_a);
2050 if(new_cmp_b == NULL) {
2051 new_cmp_a = be_transform_node(cmp_a);
2052 new_cmp_b = be_transform_node(cmp_b);
2055 if (!mode_is_signed(cmp_mode)) {
2056 pnc |= ia32_pn_Cmp_Unsigned;
2060 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2061 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2062 new_cmp_a, new_cmp_b, nomem, pnc);
2063 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2064 pnc = get_negated_pnc(pnc, cmp_mode);
2065 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2066 new_cmp_a, new_cmp_b, nomem, pnc);
2068 ir_node *new_psi_true = be_transform_node(psi_true);
2069 ir_node *new_psi_default = be_transform_node(psi_default);
2070 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2071 new_psi_true, new_psi_default, pnc);
2073 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2079 * Following conversion rules apply:
2083 * 1) n bit -> m bit n > m (downscale)
2085 * 2) n bit -> m bit n == m (sign change)
2087 * 3) n bit -> m bit n < m (upscale)
2088 * a) source is signed: movsx
2089 * b) source is unsigned: and with lower bits sets
2093 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2097 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2101 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2102 * x87 is mode_E internally, conversions happen only at load and store
2103 * in non-strict semantic
2107 * Create a conversion from x87 state register to general purpose.
2109 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2110 ir_node *block = be_transform_node(get_nodes_block(node));
2111 ir_node *op = get_Conv_op(node);
2112 ir_node *new_op = be_transform_node(op);
2113 ia32_code_gen_t *cg = env_cg;
2114 ir_graph *irg = current_ir_graph;
2115 dbg_info *dbgi = get_irn_dbg_info(node);
2116 ir_node *noreg = ia32_new_NoReg_gp(cg);
2117 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2118 ir_node *fist, *load;
2121 fist = new_rd_ia32_vfist(dbgi, irg, block,
2122 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2124 set_irn_pinned(fist, op_pin_state_floats);
2125 set_ia32_use_frame(fist);
2126 set_ia32_am_support(fist, ia32_am_Dest);
2127 set_ia32_op_type(fist, ia32_AddrModeD);
2128 set_ia32_am_flavour(fist, ia32_am_B);
2129 set_ia32_ls_mode(fist, mode_Iu);
2130 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2133 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2135 set_irn_pinned(load, op_pin_state_floats);
2136 set_ia32_use_frame(load);
2137 set_ia32_am_support(load, ia32_am_Source);
2138 set_ia32_op_type(load, ia32_AddrModeS);
2139 set_ia32_am_flavour(load, ia32_am_B);
2140 set_ia32_ls_mode(load, mode_Iu);
2141 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2143 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2147 * Create a conversion from general purpose to x87 register
2149 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2150 ir_node *block = be_transform_node(get_nodes_block(node));
2151 ir_node *op = get_Conv_op(node);
2152 ir_node *new_op = be_transform_node(op);
2153 ir_graph *irg = current_ir_graph;
2154 dbg_info *dbgi = get_irn_dbg_info(node);
2155 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2156 ir_node *nomem = new_NoMem();
2157 ir_node *fild, *store;
2160 /* first convert to 32 bit if necessary */
2161 src_bits = get_mode_size_bits(src_mode);
2162 if (src_bits == 8) {
2163 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2164 set_ia32_am_support(new_op, ia32_am_Source);
2165 set_ia32_ls_mode(new_op, src_mode);
2166 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2167 } else if (src_bits < 32) {
2168 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2169 set_ia32_am_support(new_op, ia32_am_Source);
2170 set_ia32_ls_mode(new_op, src_mode);
2171 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2175 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2177 set_ia32_use_frame(store);
2178 set_ia32_am_support(store, ia32_am_Dest);
2179 set_ia32_op_type(store, ia32_AddrModeD);
2180 set_ia32_am_flavour(store, ia32_am_OB);
2181 set_ia32_ls_mode(store, mode_Iu);
2184 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2186 set_ia32_use_frame(fild);
2187 set_ia32_am_support(fild, ia32_am_Source);
2188 set_ia32_op_type(fild, ia32_AddrModeS);
2189 set_ia32_am_flavour(fild, ia32_am_OB);
2190 set_ia32_ls_mode(fild, mode_Iu);
2192 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2195 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2198 ir_node *block = get_nodes_block(node);
2199 ir_graph *irg = current_ir_graph;
2200 dbg_info *dbgi = get_irn_dbg_info(node);
2201 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2202 ir_node *nomem = new_NoMem();
2203 int src_bits = get_mode_size_bits(src_mode);
2204 int tgt_bits = get_mode_size_bits(tgt_mode);
2205 ir_node *frame = get_irg_frame(irg);
2206 ir_mode *smaller_mode;
2207 ir_node *store, *load;
2210 if(src_bits <= tgt_bits)
2211 smaller_mode = src_mode;
2213 smaller_mode = tgt_mode;
2215 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2217 set_ia32_use_frame(store);
2218 set_ia32_am_support(store, ia32_am_Dest);
2219 set_ia32_op_type(store, ia32_AddrModeD);
2220 set_ia32_am_flavour(store, ia32_am_OB);
2222 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2224 set_ia32_use_frame(load);
2225 set_ia32_am_support(load, ia32_am_Source);
2226 set_ia32_op_type(load, ia32_AddrModeS);
2227 set_ia32_am_flavour(load, ia32_am_OB);
2229 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2234 * Transforms a Conv node.
2236 * @return The created ia32 Conv node
2238 static ir_node *gen_Conv(ir_node *node) {
2239 ir_node *block = be_transform_node(get_nodes_block(node));
2240 ir_node *op = get_Conv_op(node);
2241 ir_node *new_op = be_transform_node(op);
2242 ir_graph *irg = current_ir_graph;
2243 dbg_info *dbgi = get_irn_dbg_info(node);
2244 ir_mode *src_mode = get_irn_mode(op);
2245 ir_mode *tgt_mode = get_irn_mode(node);
2246 int src_bits = get_mode_size_bits(src_mode);
2247 int tgt_bits = get_mode_size_bits(tgt_mode);
2248 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2249 ir_node *nomem = new_rd_NoMem(irg);
2252 if (src_mode == tgt_mode) {
2253 if (get_Conv_strict(node)) {
2254 if (USE_SSE2(env_cg)) {
2255 /* when we are in SSE mode, we can kill all strict no-op conversion */
2259 /* this should be optimized already, but who knows... */
2260 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2261 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2266 if (mode_is_float(src_mode)) {
2267 /* we convert from float ... */
2268 if (mode_is_float(tgt_mode)) {
2269 if(src_mode == mode_E && tgt_mode == mode_D
2270 && !get_Conv_strict(node)) {
2271 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2276 if (USE_SSE2(env_cg)) {
2277 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2278 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2279 set_ia32_ls_mode(res, tgt_mode);
2281 // Matze: TODO what about strict convs?
2282 if(get_Conv_strict(node)) {
2283 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2284 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2287 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2292 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2293 if (USE_SSE2(env_cg)) {
2294 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2295 set_ia32_ls_mode(res, src_mode);
2297 return gen_x87_fp_to_gp(node);
2301 /* we convert from int ... */
2302 if (mode_is_float(tgt_mode)) {
2305 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2306 if (USE_SSE2(env_cg)) {
2307 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2308 set_ia32_ls_mode(res, tgt_mode);
2309 if(src_bits == 32) {
2310 set_ia32_am_support(res, ia32_am_Source);
2313 return gen_x87_gp_to_fp(node, src_mode);
2317 ir_mode *smaller_mode;
2320 if (src_bits == tgt_bits) {
2321 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2325 if (src_bits < tgt_bits) {
2326 smaller_mode = src_mode;
2327 smaller_bits = src_bits;
2329 smaller_mode = tgt_mode;
2330 smaller_bits = tgt_bits;
2333 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2334 if (smaller_bits == 8) {
2335 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2336 set_ia32_ls_mode(res, smaller_mode);
2338 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2339 set_ia32_ls_mode(res, smaller_mode);
2341 set_ia32_am_support(res, ia32_am_Source);
2345 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2351 int check_immediate_constraint(long val, char immediate_constraint_type)
2353 switch (immediate_constraint_type) {
2357 return val >= 0 && val <= 32;
2359 return val >= 0 && val <= 63;
2361 return val >= -128 && val <= 127;
2363 return val == 0xff || val == 0xffff;
2365 return val >= 0 && val <= 3;
2367 return val >= 0 && val <= 255;
2369 return val >= 0 && val <= 127;
2373 panic("Invalid immediate constraint found");
2378 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2381 tarval *offset = NULL;
2382 int offset_sign = 0;
2384 ir_entity *symconst_ent = NULL;
2385 int symconst_sign = 0;
2387 ir_node *cnst = NULL;
2388 ir_node *symconst = NULL;
2394 mode = get_irn_mode(node);
2395 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2396 !mode_is_reference(mode)) {
2400 if(is_Minus(node)) {
2402 node = get_Minus_op(node);
2405 if(is_Const(node)) {
2408 offset_sign = minus;
2409 } else if(is_SymConst(node)) {
2412 symconst_sign = minus;
2413 } else if(is_Add(node)) {
2414 ir_node *left = get_Add_left(node);
2415 ir_node *right = get_Add_right(node);
2416 if(is_Const(left) && is_SymConst(right)) {
2419 symconst_sign = minus;
2420 offset_sign = minus;
2421 } else if(is_SymConst(left) && is_Const(right)) {
2424 symconst_sign = minus;
2425 offset_sign = minus;
2427 } else if(is_Sub(node)) {
2428 ir_node *left = get_Sub_left(node);
2429 ir_node *right = get_Sub_right(node);
2430 if(is_Const(left) && is_SymConst(right)) {
2433 symconst_sign = !minus;
2434 offset_sign = minus;
2435 } else if(is_SymConst(left) && is_Const(right)) {
2438 symconst_sign = minus;
2439 offset_sign = !minus;
2446 offset = get_Const_tarval(cnst);
2447 if(tarval_is_long(offset)) {
2448 val = get_tarval_long(offset);
2449 } else if(tarval_is_null(offset)) {
2452 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2457 if(!check_immediate_constraint(val, immediate_constraint_type))
2460 if(symconst != NULL) {
2461 if(immediate_constraint_type != 0) {
2462 /* we need full 32bits for symconsts */
2466 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2468 symconst_ent = get_SymConst_entity(symconst);
2470 if(cnst == NULL && symconst == NULL)
2473 if(offset_sign && offset != NULL) {
2474 offset = tarval_neg(offset);
2477 irg = current_ir_graph;
2478 dbgi = get_irn_dbg_info(node);
2479 block = get_irg_start_block(irg);
2480 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2482 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2484 /* make sure we don't schedule stuff before the barrier */
2485 add_irn_dep(res, get_irg_frame(irg));
2490 typedef struct constraint_t constraint_t;
2491 struct constraint_t {
2494 const arch_register_req_t **out_reqs;
2496 const arch_register_req_t *req;
2497 unsigned immediate_possible;
2498 char immediate_type;
2501 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2503 int immediate_possible = 0;
2504 char immediate_type = 0;
2505 unsigned limited = 0;
2506 const arch_register_class_t *cls = NULL;
2508 struct obstack *obst;
2509 arch_register_req_t *req;
2510 unsigned *limited_ptr;
2514 /* TODO: replace all the asserts with nice error messages */
2516 printf("Constraint: %s\n", c);
2526 assert(cls == NULL ||
2527 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2528 cls = &ia32_reg_classes[CLASS_ia32_gp];
2529 limited |= 1 << REG_EAX;
2532 assert(cls == NULL ||
2533 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2534 cls = &ia32_reg_classes[CLASS_ia32_gp];
2535 limited |= 1 << REG_EBX;
2538 assert(cls == NULL ||
2539 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2540 cls = &ia32_reg_classes[CLASS_ia32_gp];
2541 limited |= 1 << REG_ECX;
2544 assert(cls == NULL ||
2545 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2546 cls = &ia32_reg_classes[CLASS_ia32_gp];
2547 limited |= 1 << REG_EDX;
2550 assert(cls == NULL ||
2551 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2552 cls = &ia32_reg_classes[CLASS_ia32_gp];
2553 limited |= 1 << REG_EDI;
2556 assert(cls == NULL ||
2557 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2558 cls = &ia32_reg_classes[CLASS_ia32_gp];
2559 limited |= 1 << REG_ESI;
2562 case 'q': /* q means lower part of the regs only, this makes no
2563 * difference to Q for us (we only assigne whole registers) */
2564 assert(cls == NULL ||
2565 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2566 cls = &ia32_reg_classes[CLASS_ia32_gp];
2567 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2571 assert(cls == NULL ||
2572 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2573 cls = &ia32_reg_classes[CLASS_ia32_gp];
2574 limited |= 1 << REG_EAX | 1 << REG_EDX;
2577 assert(cls == NULL ||
2578 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2579 cls = &ia32_reg_classes[CLASS_ia32_gp];
2580 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2581 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2588 assert(cls == NULL);
2589 cls = &ia32_reg_classes[CLASS_ia32_gp];
2595 /* TODO: mark values so the x87 simulator knows about t and u */
2596 assert(cls == NULL);
2597 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2602 assert(cls == NULL);
2603 /* TODO: check that sse2 is supported */
2604 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2614 assert(!immediate_possible);
2615 immediate_possible = 1;
2616 immediate_type = *c;
2620 assert(!immediate_possible);
2621 immediate_possible = 1;
2625 assert(!immediate_possible && cls == NULL);
2626 immediate_possible = 1;
2627 cls = &ia32_reg_classes[CLASS_ia32_gp];
2640 assert(constraint->is_in && "can only specify same constraint "
2643 sscanf(c, "%d%n", &same_as, &p);
2650 case 'E': /* no float consts yet */
2651 case 'F': /* no float consts yet */
2652 case 's': /* makes no sense on x86 */
2653 case 'X': /* we can't support that in firm */
2657 case '<': /* no autodecrement on x86 */
2658 case '>': /* no autoincrement on x86 */
2659 case 'C': /* sse constant not supported yet */
2660 case 'G': /* 80387 constant not supported yet */
2661 case 'y': /* we don't support mmx registers yet */
2662 case 'Z': /* not available in 32 bit mode */
2663 case 'e': /* not available in 32 bit mode */
2664 assert(0 && "asm constraint not supported");
2667 assert(0 && "unknown asm constraint found");
2674 const arch_register_req_t *other_constr;
2676 assert(cls == NULL && "same as and register constraint not supported");
2677 assert(!immediate_possible && "same as and immediate constraint not "
2679 assert(same_as < constraint->n_outs && "wrong constraint number in "
2680 "same_as constraint");
2682 other_constr = constraint->out_reqs[same_as];
2684 req = obstack_alloc(obst, sizeof(req[0]));
2685 req->cls = other_constr->cls;
2686 req->type = arch_register_req_type_should_be_same;
2687 req->limited = NULL;
2688 req->other_same = pos;
2689 req->other_different = -1;
2691 /* switch constraints. This is because in firm we have same_as
2692 * constraints on the output constraints while in the gcc asm syntax
2693 * they are specified on the input constraints */
2694 constraint->req = other_constr;
2695 constraint->out_reqs[same_as] = req;
2696 constraint->immediate_possible = 0;
2700 if(immediate_possible && cls == NULL) {
2701 cls = &ia32_reg_classes[CLASS_ia32_gp];
2703 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2704 assert(cls != NULL);
2706 if(immediate_possible) {
2707 assert(constraint->is_in
2708 && "imeediates make no sense for output constraints");
2710 /* todo: check types (no float input on 'r' constrainted in and such... */
2712 irg = current_ir_graph;
2713 obst = get_irg_obstack(irg);
2716 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2717 limited_ptr = (unsigned*) (req+1);
2719 req = obstack_alloc(obst, sizeof(req[0]));
2721 memset(req, 0, sizeof(req[0]));
2724 req->type = arch_register_req_type_limited;
2725 *limited_ptr = limited;
2726 req->limited = limited_ptr;
2728 req->type = arch_register_req_type_normal;
2732 constraint->req = req;
2733 constraint->immediate_possible = immediate_possible;
2734 constraint->immediate_type = immediate_type;
2738 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2745 panic("Clobbers not supported yet");
2748 ir_node *gen_ASM(ir_node *node)
2751 ir_graph *irg = current_ir_graph;
2752 ir_node *block = be_transform_node(get_nodes_block(node));
2753 dbg_info *dbgi = get_irn_dbg_info(node);
2760 ia32_asm_attr_t *attr;
2761 const arch_register_req_t **out_reqs;
2762 const arch_register_req_t **in_reqs;
2763 struct obstack *obst;
2764 constraint_t parsed_constraint;
2766 /* assembler could contain float statements */
2769 /* transform inputs */
2770 arity = get_irn_arity(node);
2771 in = alloca(arity * sizeof(in[0]));
2772 memset(in, 0, arity * sizeof(in[0]));
2774 n_outs = get_ASM_n_output_constraints(node);
2775 n_clobbers = get_ASM_n_clobbers(node);
2776 out_arity = n_outs + n_clobbers;
2778 /* construct register constraints */
2779 obst = get_irg_obstack(irg);
2780 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2781 parsed_constraint.out_reqs = out_reqs;
2782 parsed_constraint.n_outs = n_outs;
2783 parsed_constraint.is_in = 0;
2784 for(i = 0; i < out_arity; ++i) {
2788 const ir_asm_constraint *constraint;
2789 constraint = & get_ASM_output_constraints(node) [i];
2790 c = get_id_str(constraint->constraint);
2791 parse_asm_constraint(i, &parsed_constraint, c);
2793 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2794 c = get_id_str(glob_id);
2795 parse_clobber(node, i, &parsed_constraint, c);
2797 out_reqs[i] = parsed_constraint.req;
2800 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2801 parsed_constraint.is_in = 1;
2802 for(i = 0; i < arity; ++i) {
2803 const ir_asm_constraint *constraint;
2807 constraint = & get_ASM_input_constraints(node) [i];
2808 constr_id = constraint->constraint;
2809 c = get_id_str(constr_id);
2810 parse_asm_constraint(i, &parsed_constraint, c);
2811 in_reqs[i] = parsed_constraint.req;
2813 if(parsed_constraint.immediate_possible) {
2814 ir_node *pred = get_irn_n(node, i);
2815 char imm_type = parsed_constraint.immediate_type;
2816 ir_node *immediate = try_create_Immediate(pred, imm_type);
2818 if(immediate != NULL) {
2824 /* transform inputs */
2825 for(i = 0; i < arity; ++i) {
2827 ir_node *transformed;
2832 pred = get_irn_n(node, i);
2833 transformed = be_transform_node(pred);
2834 in[i] = transformed;
2837 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2839 generic_attr = get_irn_generic_attr(res);
2840 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2841 attr->asm_text = get_ASM_text(node);
2842 set_ia32_out_req_all(res, out_reqs);
2843 set_ia32_in_req_all(res, in_reqs);
2845 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2850 /********************************************
2853 * | |__ ___ _ __ ___ __| | ___ ___
2854 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2855 * | |_) | __/ | | | (_) | (_| | __/\__ \
2856 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2858 ********************************************/
2860 static ir_node *gen_be_StackParam(ir_node *node) {
2861 ir_node *block = be_transform_node(get_nodes_block(node));
2862 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2863 ir_node *new_ptr = be_transform_node(ptr);
2864 ir_node *new_op = NULL;
2865 ir_graph *irg = current_ir_graph;
2866 dbg_info *dbgi = get_irn_dbg_info(node);
2867 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2868 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2869 ir_mode *load_mode = get_irn_mode(node);
2870 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2874 if (mode_is_float(load_mode)) {
2876 if (USE_SSE2(env_cg)) {
2877 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2878 pn_res = pn_ia32_xLoad_res;
2879 proj_mode = mode_xmm;
2881 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2882 pn_res = pn_ia32_vfld_res;
2883 proj_mode = mode_vfp;
2886 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2887 proj_mode = mode_Iu;
2888 pn_res = pn_ia32_Load_res;
2891 set_irn_pinned(new_op, op_pin_state_floats);
2892 set_ia32_frame_ent(new_op, ent);
2893 set_ia32_use_frame(new_op);
2895 set_ia32_am_support(new_op, ia32_am_Source);
2896 set_ia32_op_type(new_op, ia32_AddrModeS);
2897 set_ia32_am_flavour(new_op, ia32_am_B);
2898 set_ia32_ls_mode(new_op, load_mode);
2899 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2901 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2903 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2907 * Transforms a FrameAddr into an ia32 Add.
2909 static ir_node *gen_be_FrameAddr(ir_node *node) {
2910 ir_node *block = be_transform_node(get_nodes_block(node));
2911 ir_node *op = be_get_FrameAddr_frame(node);
2912 ir_node *new_op = be_transform_node(op);
2913 ir_graph *irg = current_ir_graph;
2914 dbg_info *dbgi = get_irn_dbg_info(node);
2915 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2918 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2919 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2920 set_ia32_am_support(res, ia32_am_Full);
2921 set_ia32_use_frame(res);
2922 set_ia32_am_flavour(res, ia32_am_OB);
2924 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2930 * Transforms a FrameLoad into an ia32 Load.
2932 static ir_node *gen_be_FrameLoad(ir_node *node) {
2933 ir_node *block = be_transform_node(get_nodes_block(node));
2934 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2935 ir_node *new_mem = be_transform_node(mem);
2936 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2937 ir_node *new_ptr = be_transform_node(ptr);
2938 ir_node *new_op = NULL;
2939 ir_graph *irg = current_ir_graph;
2940 dbg_info *dbgi = get_irn_dbg_info(node);
2941 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2942 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2943 ir_mode *mode = get_type_mode(get_entity_type(ent));
2944 ir_node *projs[pn_Load_max];
2946 ia32_collect_Projs(node, projs, pn_Load_max);
2948 if (mode_is_float(mode)) {
2950 if (USE_SSE2(env_cg)) {
2951 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2954 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2958 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2961 set_irn_pinned(new_op, op_pin_state_floats);
2962 set_ia32_frame_ent(new_op, ent);
2963 set_ia32_use_frame(new_op);
2965 set_ia32_am_support(new_op, ia32_am_Source);
2966 set_ia32_op_type(new_op, ia32_AddrModeS);
2967 set_ia32_am_flavour(new_op, ia32_am_B);
2968 set_ia32_ls_mode(new_op, mode);
2969 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2971 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2978 * Transforms a FrameStore into an ia32 Store.
2980 static ir_node *gen_be_FrameStore(ir_node *node) {
2981 ir_node *block = be_transform_node(get_nodes_block(node));
2982 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2983 ir_node *new_mem = be_transform_node(mem);
2984 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2985 ir_node *new_ptr = be_transform_node(ptr);
2986 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2987 ir_node *new_val = be_transform_node(val);
2988 ir_node *new_op = NULL;
2989 ir_graph *irg = current_ir_graph;
2990 dbg_info *dbgi = get_irn_dbg_info(node);
2991 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2992 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2993 ir_mode *mode = get_irn_mode(val);
2995 if (mode_is_float(mode)) {
2997 if (USE_SSE2(env_cg)) {
2998 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3000 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3002 } else if (get_mode_size_bits(mode) == 8) {
3003 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3005 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3008 set_ia32_frame_ent(new_op, ent);
3009 set_ia32_use_frame(new_op);
3011 set_ia32_am_support(new_op, ia32_am_Dest);
3012 set_ia32_op_type(new_op, ia32_AddrModeD);
3013 set_ia32_am_flavour(new_op, ia32_am_B);
3014 set_ia32_ls_mode(new_op, mode);
3016 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3022 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3024 static ir_node *gen_be_Return(ir_node *node) {
3025 ir_graph *irg = current_ir_graph;
3026 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3027 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3028 ir_entity *ent = get_irg_entity(irg);
3029 ir_type *tp = get_entity_type(ent);
3034 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3035 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3038 int pn_ret_val, pn_ret_mem, arity, i;
3040 assert(ret_val != NULL);
3041 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3042 return be_duplicate_node(node);
3045 res_type = get_method_res_type(tp, 0);
3047 if (! is_Primitive_type(res_type)) {
3048 return be_duplicate_node(node);
3051 mode = get_type_mode(res_type);
3052 if (! mode_is_float(mode)) {
3053 return be_duplicate_node(node);
3056 assert(get_method_n_ress(tp) == 1);
3058 pn_ret_val = get_Proj_proj(ret_val);
3059 pn_ret_mem = get_Proj_proj(ret_mem);
3061 /* get the Barrier */
3062 barrier = get_Proj_pred(ret_val);
3064 /* get result input of the Barrier */
3065 ret_val = get_irn_n(barrier, pn_ret_val);
3066 new_ret_val = be_transform_node(ret_val);
3068 /* get memory input of the Barrier */
3069 ret_mem = get_irn_n(barrier, pn_ret_mem);
3070 new_ret_mem = be_transform_node(ret_mem);
3072 frame = get_irg_frame(irg);
3074 dbgi = get_irn_dbg_info(barrier);
3075 block = be_transform_node(get_nodes_block(barrier));
3077 noreg = ia32_new_NoReg_gp(env_cg);
3079 /* store xmm0 onto stack */
3080 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3081 set_ia32_ls_mode(sse_store, mode);
3082 set_ia32_op_type(sse_store, ia32_AddrModeD);
3083 set_ia32_use_frame(sse_store);
3084 set_ia32_am_flavour(sse_store, ia32_am_B);
3085 set_ia32_am_support(sse_store, ia32_am_Dest);
3088 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3089 set_ia32_ls_mode(fld, mode);
3090 set_ia32_op_type(fld, ia32_AddrModeS);
3091 set_ia32_use_frame(fld);
3092 set_ia32_am_flavour(fld, ia32_am_B);
3093 set_ia32_am_support(fld, ia32_am_Source);
3095 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3096 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3097 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3099 /* create a new barrier */
3100 arity = get_irn_arity(barrier);
3101 in = alloca(arity * sizeof(in[0]));
3102 for (i = 0; i < arity; ++i) {
3105 if (i == pn_ret_val) {
3107 } else if (i == pn_ret_mem) {
3110 ir_node *in = get_irn_n(barrier, i);
3111 new_in = be_transform_node(in);
3116 new_barrier = new_ir_node(dbgi, irg, block,
3117 get_irn_op(barrier), get_irn_mode(barrier),
3119 copy_node_attr(barrier, new_barrier);
3120 be_duplicate_deps(barrier, new_barrier);
3121 be_set_transformed_node(barrier, new_barrier);
3122 mark_irn_visited(barrier);
3124 /* transform normally */
3125 return be_duplicate_node(node);
3129 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3131 static ir_node *gen_be_AddSP(ir_node *node) {
3132 ir_node *block = be_transform_node(get_nodes_block(node));
3133 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3135 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3136 ir_node *new_sp = be_transform_node(sp);
3137 ir_graph *irg = current_ir_graph;
3138 dbg_info *dbgi = get_irn_dbg_info(node);
3139 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3140 ir_node *nomem = new_NoMem();
3143 new_sz = try_create_Immediate(sz, 0);
3144 if(new_sz == NULL) {
3145 new_sz = be_transform_node(sz);
3148 /* ia32 stack grows in reverse direction, make a SubSP */
3149 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3151 set_ia32_am_support(new_op, ia32_am_Source);
3152 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3158 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3160 static ir_node *gen_be_SubSP(ir_node *node) {
3161 ir_node *block = be_transform_node(get_nodes_block(node));
3162 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3164 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3165 ir_node *new_sp = be_transform_node(sp);
3166 ir_graph *irg = current_ir_graph;
3167 dbg_info *dbgi = get_irn_dbg_info(node);
3168 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3169 ir_node *nomem = new_NoMem();
3172 new_sz = try_create_Immediate(sz, 0);
3173 if(new_sz == NULL) {
3174 new_sz = be_transform_node(sz);
3177 /* ia32 stack grows in reverse direction, make an AddSP */
3178 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3179 set_ia32_am_support(new_op, ia32_am_Source);
3180 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3186 * This function just sets the register for the Unknown node
3187 * as this is not done during register allocation because Unknown
3188 * is an "ignore" node.
3190 static ir_node *gen_Unknown(ir_node *node) {
3191 ir_mode *mode = get_irn_mode(node);
3193 if (mode_is_float(mode)) {
3194 if (USE_SSE2(env_cg))
3195 return ia32_new_Unknown_xmm(env_cg);
3197 return ia32_new_Unknown_vfp(env_cg);
3198 } else if (mode_needs_gp_reg(mode)) {
3199 return ia32_new_Unknown_gp(env_cg);
3201 assert(0 && "unsupported Unknown-Mode");
3208 * Change some phi modes
3210 static ir_node *gen_Phi(ir_node *node) {
3211 ir_node *block = be_transform_node(get_nodes_block(node));
3212 ir_graph *irg = current_ir_graph;
3213 dbg_info *dbgi = get_irn_dbg_info(node);
3214 ir_mode *mode = get_irn_mode(node);
3217 if(mode_needs_gp_reg(mode)) {
3218 /* we shouldn't have any 64bit stuff around anymore */
3219 assert(get_mode_size_bits(mode) <= 32);
3220 /* all integer operations are on 32bit registers now */
3222 } else if(mode_is_float(mode)) {
3223 if (USE_SSE2(env_cg)) {
3230 /* phi nodes allow loops, so we use the old arguments for now
3231 * and fix this later */
3232 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3233 copy_node_attr(node, phi);
3234 be_duplicate_deps(node, phi);
3236 be_set_transformed_node(node, phi);
3237 be_enqueue_preds(node);
3242 /**********************************************************************
3245 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3246 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3247 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3248 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3250 **********************************************************************/
3252 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3254 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3257 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3258 ir_node *val, ir_node *mem);
3261 * Transforms a lowered Load into a "real" one.
3263 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3264 ir_node *block = be_transform_node(get_nodes_block(node));
3265 ir_node *ptr = get_irn_n(node, 0);
3266 ir_node *new_ptr = be_transform_node(ptr);
3267 ir_node *mem = get_irn_n(node, 1);
3268 ir_node *new_mem = be_transform_node(mem);
3269 ir_graph *irg = current_ir_graph;
3270 dbg_info *dbgi = get_irn_dbg_info(node);
3271 ir_mode *mode = get_ia32_ls_mode(node);
3272 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3276 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3277 lowering we have x87 nodes, so we need to enforce simulation.
3279 if (mode_is_float(mode)) {
3281 if (fp_unit == fp_x87)
3285 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3287 set_ia32_am_support(new_op, ia32_am_Source);
3288 set_ia32_op_type(new_op, ia32_AddrModeS);
3289 set_ia32_am_flavour(new_op, ia32_am_OB);
3290 set_ia32_am_offs_int(new_op, 0);
3291 set_ia32_am_scale(new_op, 1);
3292 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3293 if (is_ia32_am_sc_sign(node))
3294 set_ia32_am_sc_sign(new_op);
3295 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3296 if (is_ia32_use_frame(node)) {
3297 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3298 set_ia32_use_frame(new_op);
3301 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3307 * Transforms a lowered Store into a "real" one.
3309 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3310 ir_node *block = be_transform_node(get_nodes_block(node));
3311 ir_node *ptr = get_irn_n(node, 0);
3312 ir_node *new_ptr = be_transform_node(ptr);
3313 ir_node *val = get_irn_n(node, 1);
3314 ir_node *new_val = be_transform_node(val);
3315 ir_node *mem = get_irn_n(node, 2);
3316 ir_node *new_mem = be_transform_node(mem);
3317 ir_graph *irg = current_ir_graph;
3318 dbg_info *dbgi = get_irn_dbg_info(node);
3319 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3320 ir_mode *mode = get_ia32_ls_mode(node);
3323 ia32_am_flavour_t am_flav = ia32_B;
3326 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3327 lowering we have x87 nodes, so we need to enforce simulation.
3329 if (mode_is_float(mode)) {
3331 if (fp_unit == fp_x87)
3335 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3337 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3339 add_ia32_am_offs_int(new_op, am_offs);
3342 set_ia32_am_support(new_op, ia32_am_Dest);
3343 set_ia32_op_type(new_op, ia32_AddrModeD);
3344 set_ia32_am_flavour(new_op, am_flav);
3345 set_ia32_ls_mode(new_op, mode);
3346 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3347 set_ia32_use_frame(new_op);
3349 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3356 * Transforms an ia32_l_XXX into a "real" XXX node
3358 * @param env The transformation environment
3359 * @return the created ia32 XXX node
3361 #define GEN_LOWERED_OP(op) \
3362 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3363 ir_mode *mode = get_irn_mode(node); \
3364 if (mode_is_float(mode)) \
3366 return gen_binop(node, get_binop_left(node), \
3367 get_binop_right(node), new_rd_ia32_##op,0); \
3370 #define GEN_LOWERED_x87_OP(op) \
3371 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3373 FORCE_x87(env_cg); \
3374 new_op = gen_binop_float(node, get_binop_left(node), \
3375 get_binop_right(node), new_rd_ia32_##op); \
3379 #define GEN_LOWERED_UNOP(op) \
3380 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3381 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3384 #define GEN_LOWERED_SHIFT_OP(op) \
3385 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3386 return gen_shift_binop(node, get_binop_left(node), \
3387 get_binop_right(node), new_rd_ia32_##op); \
3390 #define GEN_LOWERED_LOAD(op, fp_unit) \
3391 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3392 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3395 #define GEN_LOWERED_STORE(op, fp_unit) \
3396 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3397 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3404 GEN_LOWERED_OP(IMul)
3406 GEN_LOWERED_x87_OP(vfprem)
3407 GEN_LOWERED_x87_OP(vfmul)
3408 GEN_LOWERED_x87_OP(vfsub)
3410 GEN_LOWERED_UNOP(Neg)
3412 GEN_LOWERED_LOAD(vfild, fp_x87)
3413 GEN_LOWERED_LOAD(Load, fp_none)
3414 /*GEN_LOWERED_STORE(vfist, fp_x87)
3417 GEN_LOWERED_STORE(Store, fp_none)
3419 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3420 ir_node *block = be_transform_node(get_nodes_block(node));
3421 ir_node *left = get_binop_left(node);
3422 ir_node *new_left = be_transform_node(left);
3423 ir_node *right = get_binop_right(node);
3424 ir_node *new_right = be_transform_node(right);
3425 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3426 ir_graph *irg = current_ir_graph;
3427 dbg_info *dbgi = get_irn_dbg_info(node);
3430 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3431 clear_ia32_commutative(vfdiv);
3432 set_ia32_am_support(vfdiv, ia32_am_Source);
3434 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3442 * Transforms a l_MulS into a "real" MulS node.
3444 * @param env The transformation environment
3445 * @return the created ia32 Mul node
3447 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3448 ir_node *block = be_transform_node(get_nodes_block(node));
3449 ir_node *left = get_binop_left(node);
3450 ir_node *new_left = be_transform_node(left);
3451 ir_node *right = get_binop_right(node);
3452 ir_node *new_right = be_transform_node(right);
3453 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3454 ir_graph *irg = current_ir_graph;
3455 dbg_info *dbgi = get_irn_dbg_info(node);
3458 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3459 /* and then skip the result Proj, because all needed Projs are already there. */
3460 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3461 clear_ia32_commutative(muls);
3462 set_ia32_am_support(muls, ia32_am_Source);
3464 /* check if EAX and EDX proj exist, add missing one */
3465 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3466 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3467 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3469 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3474 GEN_LOWERED_SHIFT_OP(Shl)
3475 GEN_LOWERED_SHIFT_OP(Shr)
3476 GEN_LOWERED_SHIFT_OP(Sar)
3479 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3480 * op1 - target to be shifted
3481 * op2 - contains bits to be shifted into target
3483 * Only op3 can be an immediate.
3485 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3486 ir_node *op2, ir_node *count)
3488 ir_node *block = be_transform_node(get_nodes_block(node));
3489 ir_node *new_op1 = be_transform_node(op1);
3490 ir_node *new_op2 = be_transform_node(op2);
3491 ir_node *new_count = be_transform_node(count);
3492 ir_node *new_op = NULL;
3493 ir_graph *irg = current_ir_graph;
3494 dbg_info *dbgi = get_irn_dbg_info(node);
3495 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3496 ir_node *nomem = new_NoMem();
3500 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3502 /* Check if immediate optimization is on and */
3503 /* if it's an operation with immediate. */
3504 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3506 /* Limit imm_op within range imm8 */
3508 tv = get_ia32_Immop_tarval(imm_op);
3511 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3512 set_ia32_Immop_tarval(imm_op, tv);
3519 /* integer operations */
3521 /* This is ShiftD with const */
3522 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3524 if (is_ia32_l_ShlD(node))
3525 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3526 new_op1, new_op2, noreg, nomem);
3528 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3529 new_op1, new_op2, noreg, nomem);
3530 copy_ia32_Immop_attr(new_op, imm_op);
3533 /* This is a normal ShiftD */
3534 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3535 if (is_ia32_l_ShlD(node))
3536 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3537 new_op1, new_op2, new_count, nomem);
3539 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3540 new_op1, new_op2, new_count, nomem);
3543 /* set AM support */
3544 // Matze: node has unsupported format (6inputs)
3545 //set_ia32_am_support(new_op, ia32_am_Dest);
3547 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3549 set_ia32_emit_cl(new_op);
3554 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3555 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3556 get_irn_n(node, 1), get_irn_n(node, 2));
3559 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3560 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3561 get_irn_n(node, 1), get_irn_n(node, 2));
3565 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3567 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3568 ir_node *block = be_transform_node(get_nodes_block(node));
3569 ir_node *val = get_irn_n(node, 1);
3570 ir_node *new_val = be_transform_node(val);
3571 ia32_code_gen_t *cg = env_cg;
3572 ir_node *res = NULL;
3573 ir_graph *irg = current_ir_graph;
3575 ir_node *noreg, *new_ptr, *new_mem;
3582 mem = get_irn_n(node, 2);
3583 new_mem = be_transform_node(mem);
3584 ptr = get_irn_n(node, 0);
3585 new_ptr = be_transform_node(ptr);
3586 noreg = ia32_new_NoReg_gp(cg);
3587 dbgi = get_irn_dbg_info(node);
3589 /* Store x87 -> MEM */
3590 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3591 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3592 set_ia32_use_frame(res);
3593 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3594 set_ia32_am_support(res, ia32_am_Dest);
3595 set_ia32_am_flavour(res, ia32_B);
3596 set_ia32_op_type(res, ia32_AddrModeD);
3598 /* Load MEM -> SSE */
3599 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3600 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3601 set_ia32_use_frame(res);
3602 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3603 set_ia32_am_support(res, ia32_am_Source);
3604 set_ia32_am_flavour(res, ia32_B);
3605 set_ia32_op_type(res, ia32_AddrModeS);
3606 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3612 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3614 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3615 ir_node *block = be_transform_node(get_nodes_block(node));
3616 ir_node *val = get_irn_n(node, 1);
3617 ir_node *new_val = be_transform_node(val);
3618 ia32_code_gen_t *cg = env_cg;
3619 ir_graph *irg = current_ir_graph;
3620 ir_node *res = NULL;
3621 ir_entity *fent = get_ia32_frame_ent(node);
3622 ir_mode *lsmode = get_ia32_ls_mode(node);
3624 ir_node *noreg, *new_ptr, *new_mem;
3628 if (! USE_SSE2(cg)) {
3629 /* SSE unit is not used -> skip this node. */
3633 ptr = get_irn_n(node, 0);
3634 new_ptr = be_transform_node(ptr);
3635 mem = get_irn_n(node, 2);
3636 new_mem = be_transform_node(mem);
3637 noreg = ia32_new_NoReg_gp(cg);
3638 dbgi = get_irn_dbg_info(node);
3640 /* Store SSE -> MEM */
3641 if (is_ia32_xLoad(skip_Proj(new_val))) {
3642 ir_node *ld = skip_Proj(new_val);
3644 /* we can vfld the value directly into the fpu */
3645 fent = get_ia32_frame_ent(ld);
3646 ptr = get_irn_n(ld, 0);
3647 offs = get_ia32_am_offs_int(ld);
3649 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3650 set_ia32_frame_ent(res, fent);
3651 set_ia32_use_frame(res);
3652 set_ia32_ls_mode(res, lsmode);
3653 set_ia32_am_support(res, ia32_am_Dest);
3654 set_ia32_am_flavour(res, ia32_B);
3655 set_ia32_op_type(res, ia32_AddrModeD);
3659 /* Load MEM -> x87 */
3660 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3661 set_ia32_frame_ent(res, fent);
3662 set_ia32_use_frame(res);
3663 add_ia32_am_offs_int(res, offs);
3664 set_ia32_am_support(res, ia32_am_Source);
3665 set_ia32_am_flavour(res, ia32_B);
3666 set_ia32_op_type(res, ia32_AddrModeS);
3667 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3672 /*********************************************************
3675 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3676 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3677 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3678 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3680 *********************************************************/
3683 * the BAD transformer.
3685 static ir_node *bad_transform(ir_node *node) {
3686 panic("No transform function for %+F available.\n", node);
3691 * Transform the Projs of an AddSP.
3693 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3694 ir_node *block = be_transform_node(get_nodes_block(node));
3695 ir_node *pred = get_Proj_pred(node);
3696 ir_node *new_pred = be_transform_node(pred);
3697 ir_graph *irg = current_ir_graph;
3698 dbg_info *dbgi = get_irn_dbg_info(node);
3699 long proj = get_Proj_proj(node);
3701 if (proj == pn_be_AddSP_res) {
3702 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3703 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3705 } else if (proj == pn_be_AddSP_M) {
3706 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3710 return new_rd_Unknown(irg, get_irn_mode(node));
3714 * Transform the Projs of a SubSP.
3716 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3717 ir_node *block = be_transform_node(get_nodes_block(node));
3718 ir_node *pred = get_Proj_pred(node);
3719 ir_node *new_pred = be_transform_node(pred);
3720 ir_graph *irg = current_ir_graph;
3721 dbg_info *dbgi = get_irn_dbg_info(node);
3722 long proj = get_Proj_proj(node);
3724 if (proj == pn_be_SubSP_res) {
3725 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3726 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3728 } else if (proj == pn_be_SubSP_M) {
3729 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3733 return new_rd_Unknown(irg, get_irn_mode(node));
3737 * Transform and renumber the Projs from a Load.
3739 static ir_node *gen_Proj_Load(ir_node *node) {
3740 ir_node *block = be_transform_node(get_nodes_block(node));
3741 ir_node *pred = get_Proj_pred(node);
3742 ir_node *new_pred = be_transform_node(pred);
3743 ir_graph *irg = current_ir_graph;
3744 dbg_info *dbgi = get_irn_dbg_info(node);
3745 long proj = get_Proj_proj(node);
3747 /* renumber the proj */
3748 if (is_ia32_Load(new_pred)) {
3749 if (proj == pn_Load_res) {
3750 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3751 } else if (proj == pn_Load_M) {
3752 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3754 } else if (is_ia32_xLoad(new_pred)) {
3755 if (proj == pn_Load_res) {
3756 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3757 } else if (proj == pn_Load_M) {
3758 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3760 } else if (is_ia32_vfld(new_pred)) {
3761 if (proj == pn_Load_res) {
3762 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3763 } else if (proj == pn_Load_M) {
3764 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3769 return new_rd_Unknown(irg, get_irn_mode(node));
3773 * Transform and renumber the Projs from a DivMod like instruction.
3775 static ir_node *gen_Proj_DivMod(ir_node *node) {
3776 ir_node *block = be_transform_node(get_nodes_block(node));
3777 ir_node *pred = get_Proj_pred(node);
3778 ir_node *new_pred = be_transform_node(pred);
3779 ir_graph *irg = current_ir_graph;
3780 dbg_info *dbgi = get_irn_dbg_info(node);
3781 ir_mode *mode = get_irn_mode(node);
3782 long proj = get_Proj_proj(node);
3784 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3786 switch (get_irn_opcode(pred)) {
3790 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3792 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3800 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3802 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3810 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3811 case pn_DivMod_res_div:
3812 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3813 case pn_DivMod_res_mod:
3814 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3824 return new_rd_Unknown(irg, mode);
3828 * Transform and renumber the Projs from a CopyB.
3830 static ir_node *gen_Proj_CopyB(ir_node *node) {
3831 ir_node *block = be_transform_node(get_nodes_block(node));
3832 ir_node *pred = get_Proj_pred(node);
3833 ir_node *new_pred = be_transform_node(pred);
3834 ir_graph *irg = current_ir_graph;
3835 dbg_info *dbgi = get_irn_dbg_info(node);
3836 ir_mode *mode = get_irn_mode(node);
3837 long proj = get_Proj_proj(node);
3840 case pn_CopyB_M_regular:
3841 if (is_ia32_CopyB_i(new_pred)) {
3842 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3843 } else if (is_ia32_CopyB(new_pred)) {
3844 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3852 return new_rd_Unknown(irg, mode);
3856 * Transform and renumber the Projs from a vfdiv.
3858 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3859 ir_node *block = be_transform_node(get_nodes_block(node));
3860 ir_node *pred = get_Proj_pred(node);
3861 ir_node *new_pred = be_transform_node(pred);
3862 ir_graph *irg = current_ir_graph;
3863 dbg_info *dbgi = get_irn_dbg_info(node);
3864 ir_mode *mode = get_irn_mode(node);
3865 long proj = get_Proj_proj(node);
3868 case pn_ia32_l_vfdiv_M:
3869 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3870 case pn_ia32_l_vfdiv_res:
3871 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3876 return new_rd_Unknown(irg, mode);
3880 * Transform and renumber the Projs from a Quot.
3882 static ir_node *gen_Proj_Quot(ir_node *node) {
3883 ir_node *block = be_transform_node(get_nodes_block(node));
3884 ir_node *pred = get_Proj_pred(node);
3885 ir_node *new_pred = be_transform_node(pred);
3886 ir_graph *irg = current_ir_graph;
3887 dbg_info *dbgi = get_irn_dbg_info(node);
3888 ir_mode *mode = get_irn_mode(node);
3889 long proj = get_Proj_proj(node);
3893 if (is_ia32_xDiv(new_pred)) {
3894 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3895 } else if (is_ia32_vfdiv(new_pred)) {
3896 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3900 if (is_ia32_xDiv(new_pred)) {
3901 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3902 } else if (is_ia32_vfdiv(new_pred)) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3911 return new_rd_Unknown(irg, mode);
3915 * Transform the Thread Local Storage Proj.
3917 static ir_node *gen_Proj_tls(ir_node *node) {
3918 ir_node *block = be_transform_node(get_nodes_block(node));
3919 ir_graph *irg = current_ir_graph;
3920 dbg_info *dbgi = NULL;
3921 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3927 * Transform the Projs from a be_Call.
3929 static ir_node *gen_Proj_be_Call(ir_node *node) {
3930 ir_node *block = be_transform_node(get_nodes_block(node));
3931 ir_node *call = get_Proj_pred(node);
3932 ir_node *new_call = be_transform_node(call);
3933 ir_graph *irg = current_ir_graph;
3934 dbg_info *dbgi = get_irn_dbg_info(node);
3935 long proj = get_Proj_proj(node);
3936 ir_mode *mode = get_irn_mode(node);
3938 const arch_register_class_t *cls;
3940 /* The following is kinda tricky: If we're using SSE, then we have to
3941 * move the result value of the call in floating point registers to an
3942 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3943 * after the call, we have to make sure to correctly make the
3944 * MemProj and the result Proj use these 2 nodes
3946 if (proj == pn_be_Call_M_regular) {
3947 // get new node for result, are we doing the sse load/store hack?
3948 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3949 ir_node *call_res_new;
3950 ir_node *call_res_pred = NULL;
3952 if (call_res != NULL) {
3953 call_res_new = be_transform_node(call_res);
3954 call_res_pred = get_Proj_pred(call_res_new);
3957 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3958 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3960 assert(is_ia32_xLoad(call_res_pred));
3961 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3964 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3966 ir_node *frame = get_irg_frame(irg);
3967 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3969 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3971 const arch_register_class_t *cls;
3973 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3974 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3976 /* store st(0) onto stack */
3977 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3979 set_ia32_ls_mode(fstp, mode);
3980 set_ia32_op_type(fstp, ia32_AddrModeD);
3981 set_ia32_use_frame(fstp);
3982 set_ia32_am_flavour(fstp, ia32_am_B);
3983 set_ia32_am_support(fstp, ia32_am_Dest);
3985 /* load into SSE register */
3986 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3987 set_ia32_ls_mode(sse_load, mode);
3988 set_ia32_op_type(sse_load, ia32_AddrModeS);
3989 set_ia32_use_frame(sse_load);
3990 set_ia32_am_flavour(sse_load, ia32_am_B);
3991 set_ia32_am_support(sse_load, ia32_am_Source);
3993 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3995 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3997 /* get a Proj representing a caller save register */
3998 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3999 assert(is_Proj(p) && "Proj expected.");
4001 /* user of the the proj is the Keep */
4002 p = get_edge_src_irn(get_irn_out_edge_first(p));
4003 assert(be_is_Keep(p) && "Keep expected.");
4005 /* keep the result */
4006 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
4007 keepin[0] = sse_load;
4008 be_new_Keep(cls, irg, block, 1, keepin);
4013 /* transform call modes */
4014 if (mode_is_data(mode)) {
4015 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4019 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4023 * Transform the Projs from a Cmp.
4025 static ir_node *gen_Proj_Cmp(ir_node *node)
4027 /* normally Cmps are processed when looking at Cond nodes, but this case
4028 * can happen in complicated Psi conditions */
4030 ir_graph *irg = current_ir_graph;
4031 dbg_info *dbgi = get_irn_dbg_info(node);
4032 ir_node *block = be_transform_node(get_nodes_block(node));
4033 ir_node *cmp = get_Proj_pred(node);
4034 long pnc = get_Proj_proj(node);
4035 ir_node *cmp_left = get_Cmp_left(cmp);
4036 ir_node *cmp_right = get_Cmp_right(cmp);
4037 ir_node *new_cmp_left;
4038 ir_node *new_cmp_right;
4039 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4040 ir_node *nomem = new_rd_NoMem(irg);
4041 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4044 assert(!mode_is_float(cmp_mode));
4046 /* (a != b) -> (a ^ b) */
4047 if(pnc == pn_Cmp_Lg) {
4048 if(is_Const_0(cmp_left)) {
4049 new_op = be_transform_node(cmp_right);
4050 } else if(is_Const_0(cmp_right)) {
4051 new_op = be_transform_node(cmp_left);
4053 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4059 * (a == b) -> !(a ^ b)
4060 * (a < 0) -> (a & 0x80000000)
4061 * (a <= 0) -> !(a & 0x7fffffff)
4062 * (a > 0) -> (a & 0x7fffffff)
4063 * (a >= 0) -> !(a & 0x80000000)
4066 if(!mode_is_signed(cmp_mode)) {
4067 pnc |= ia32_pn_Cmp_Unsigned;
4070 new_cmp_right = try_create_Immediate(cmp_right, 0);
4071 if(new_cmp_right == NULL) {
4072 new_cmp_right = try_create_Immediate(cmp_left, 0);
4073 if(new_cmp_right != NULL) {
4074 pnc = get_inversed_pnc(pnc);
4075 new_cmp_left = be_transform_node(cmp_right);
4078 new_cmp_left = be_transform_node(cmp_left);
4080 if(new_cmp_right == NULL) {
4081 new_cmp_left = be_transform_node(cmp_left);
4082 new_cmp_right = be_transform_node(cmp_right);
4085 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4086 new_cmp_right, nomem, pnc);
4087 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4093 * Transform and potentially renumber Proj nodes.
4095 static ir_node *gen_Proj(ir_node *node) {
4096 ir_graph *irg = current_ir_graph;
4097 dbg_info *dbgi = get_irn_dbg_info(node);
4098 ir_node *pred = get_Proj_pred(node);
4099 long proj = get_Proj_proj(node);
4101 if (is_Store(pred) || be_is_FrameStore(pred)) {
4102 if (proj == pn_Store_M) {
4103 return be_transform_node(pred);
4106 return new_r_Bad(irg);
4108 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4109 return gen_Proj_Load(node);
4110 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4111 return gen_Proj_DivMod(node);
4112 } else if (is_CopyB(pred)) {
4113 return gen_Proj_CopyB(node);
4114 } else if (is_Quot(pred)) {
4115 return gen_Proj_Quot(node);
4116 } else if (is_ia32_l_vfdiv(pred)) {
4117 return gen_Proj_l_vfdiv(node);
4118 } else if (be_is_SubSP(pred)) {
4119 return gen_Proj_be_SubSP(node);
4120 } else if (be_is_AddSP(pred)) {
4121 return gen_Proj_be_AddSP(node);
4122 } else if (be_is_Call(pred)) {
4123 return gen_Proj_be_Call(node);
4124 } else if (is_Cmp(pred)) {
4125 return gen_Proj_Cmp(node);
4126 } else if (get_irn_op(pred) == op_Start) {
4127 if (proj == pn_Start_X_initial_exec) {
4128 ir_node *block = get_nodes_block(pred);
4131 /* we exchange the ProjX with a jump */
4132 block = be_transform_node(block);
4133 jump = new_rd_Jmp(dbgi, irg, block);
4136 if (node == be_get_old_anchor(anchor_tls)) {
4137 return gen_Proj_tls(node);
4140 ir_node *new_pred = be_transform_node(pred);
4141 ir_node *block = be_transform_node(get_nodes_block(node));
4142 ir_mode *mode = get_irn_mode(node);
4143 if (mode_needs_gp_reg(mode)) {
4144 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4145 get_Proj_proj(node));
4146 #ifdef DEBUG_libfirm
4147 new_proj->node_nr = node->node_nr;
4153 return be_duplicate_node(node);
4157 * Enters all transform functions into the generic pointer
4159 static void register_transformers(void) {
4160 ir_op *op_Max, *op_Min, *op_Mulh;
4162 /* first clear the generic function pointer for all ops */
4163 clear_irp_opcodes_generic_func();
4165 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4166 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4203 /* transform ops from intrinsic lowering */
4223 /* GEN(ia32_l_vfist); TODO */
4225 GEN(ia32_l_X87toSSE);
4226 GEN(ia32_l_SSEtoX87);
4231 /* we should never see these nodes */
4246 /* handle generic backend nodes */
4257 /* set the register for all Unknown nodes */
4260 op_Max = get_op_Max();
4263 op_Min = get_op_Min();
4266 op_Mulh = get_op_Mulh();
4275 * Pre-transform all unknown and noreg nodes.
4277 static void ia32_pretransform_node(void *arch_cg) {
4278 ia32_code_gen_t *cg = arch_cg;
4280 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4281 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4282 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4283 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4284 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4285 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4288 /* do the transformation */
4289 void ia32_transform_graph(ia32_code_gen_t *cg) {
4290 register_transformers();
4292 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4295 void ia32_init_transform(void)
4297 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");