2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "bearch_ia32_t.h"
37 #include "ia32_nodes_attr.h"
38 #include "ia32_transform.h"
39 #include "ia32_new_nodes.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_dbg_stat.h"
42 #include "ia32_optimize.h"
44 #include "gen_ia32_regalloc_if.h"
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
84 * Returns 1 if irn is a Const representing 0, 0 otherwise
86 static INLINE int is_ia32_Const_0(ir_node *irn) {
87 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
91 * Returns 1 if irn is a Const representing 1, 0 otherwise
93 static INLINE int is_ia32_Const_1(ir_node *irn) {
94 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
98 * Returns the Proj representing the UNKNOWN register for given mode.
100 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
101 be_abi_irg_t *babi = cg->birg->abi;
102 const arch_register_t *unknwn_reg = NULL;
104 if (mode_is_float(mode)) {
105 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
108 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
111 return be_abi_get_callee_save_irn(babi, unknwn_reg);
115 * Gets the Proj with number pn from irn.
117 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
118 const ir_edge_t *edge;
120 assert(get_irn_mode(irn) == mode_T && "need mode_T");
122 foreach_out_edge(irn, edge) {
123 proj = get_edge_src_irn(edge);
125 if (get_Proj_proj(proj) == pn)
133 * SSE convert of an integer node into a floating point node.
135 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
136 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
138 ir_node *noreg = ia32_new_NoReg_gp(cg);
139 ir_node *nomem = new_rd_NoMem(irg);
141 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
142 set_ia32_src_mode(conv, get_irn_mode(in));
143 set_ia32_tgt_mode(conv, tgt_mode);
144 set_ia32_am_support(conv, ia32_am_Source);
145 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
147 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
150 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
151 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
152 static const struct {
154 const char *ent_name;
155 const char *cnst_str;
156 } names [ia32_known_const_max] = {
157 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
158 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
159 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
160 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
162 static struct entity *ent_cache[ia32_known_const_max];
164 const char *tp_name, *ent_name, *cnst_str;
171 ent_name = names[kct].ent_name;
172 if (! ent_cache[kct]) {
173 tp_name = names[kct].tp_name;
174 cnst_str = names[kct].cnst_str;
176 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
177 tp = new_type_primitive(new_id_from_str(tp_name), mode);
178 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
180 set_entity_ld_ident(ent, get_entity_ident(ent));
181 set_entity_visibility(ent, visibility_local);
182 set_entity_variability(ent, variability_constant);
183 set_entity_allocation(ent, allocation_static);
185 /* we create a new entity here: It's initialization must resist on the
187 rem = current_ir_graph;
188 current_ir_graph = get_const_code_irg();
189 cnst = new_Const(mode, tv);
190 current_ir_graph = rem;
192 set_atomic_ent_value(ent, cnst);
194 /* cache the entry */
195 ent_cache[kct] = ent;
198 return get_entity_ident(ent_cache[kct]);
203 * Prints the old node name on cg obst and returns a pointer to it.
205 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
206 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
208 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
209 obstack_1grow(isa->name_obst, 0);
210 isa->name_obst_size += obstack_object_size(isa->name_obst);
211 return obstack_finish(isa->name_obst);
215 /* determine if one operator is an Imm */
216 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
218 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
219 else return is_ia32_Cnst(op2) ? op2 : NULL;
222 /* determine if one operator is not an Imm */
223 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
224 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
229 * Construct a standard binary operation, set AM and immediate if required.
231 * @param env The transformation environment
232 * @param op1 The first operand
233 * @param op2 The second operand
234 * @param func The node constructor function
235 * @return The constructed ia32 node.
237 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
238 ir_node *new_op = NULL;
239 ir_mode *mode = env->mode;
240 dbg_info *dbg = env->dbg;
241 ir_graph *irg = env->irg;
242 ir_node *block = env->block;
243 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
244 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
245 ir_node *nomem = new_NoMem();
246 ir_node *expr_op, *imm_op;
247 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
249 /* Check if immediate optimization is on and */
250 /* if it's an operation with immediate. */
251 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
255 else if (is_op_commutative(get_irn_op(env->irn))) {
256 imm_op = get_immediate_op(op1, op2);
257 expr_op = get_expr_op(op1, op2);
260 imm_op = get_immediate_op(NULL, op2);
261 expr_op = get_expr_op(op1, op2);
264 assert((expr_op || imm_op) && "invalid operands");
267 /* We have two consts here: not yet supported */
271 if (mode_is_float(mode)) {
272 /* floating point operations */
274 DB((mod, LEVEL_1, "FP with immediate ..."));
275 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
276 set_ia32_Immop_attr(new_op, imm_op);
277 set_ia32_am_support(new_op, ia32_am_None);
280 DB((mod, LEVEL_1, "FP binop ..."));
281 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
282 set_ia32_am_support(new_op, ia32_am_Source);
284 set_ia32_ls_mode(new_op, mode);
287 /* integer operations */
289 /* This is expr + const */
290 DB((mod, LEVEL_1, "INT with immediate ..."));
291 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
292 set_ia32_Immop_attr(new_op, imm_op);
295 set_ia32_am_support(new_op, ia32_am_Dest);
298 DB((mod, LEVEL_1, "INT binop ..."));
299 /* This is a normal operation */
300 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
303 set_ia32_am_support(new_op, ia32_am_Full);
307 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
309 set_ia32_res_mode(new_op, mode);
311 if (is_op_commutative(get_irn_op(env->irn))) {
312 set_ia32_commutative(new_op);
315 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
321 * Construct a shift/rotate binary operation, sets AM and immediate if required.
323 * @param env The transformation environment
324 * @param op1 The first operand
325 * @param op2 The second operand
326 * @param func The node constructor function
327 * @return The constructed ia32 node.
329 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
330 ir_node *new_op = NULL;
331 ir_mode *mode = env->mode;
332 dbg_info *dbg = env->dbg;
333 ir_graph *irg = env->irg;
334 ir_node *block = env->block;
335 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
336 ir_node *nomem = new_NoMem();
337 ir_node *expr_op, *imm_op;
339 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
341 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
343 /* Check if immediate optimization is on and */
344 /* if it's an operation with immediate. */
345 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
346 expr_op = get_expr_op(op1, op2);
348 assert((expr_op || imm_op) && "invalid operands");
351 /* We have two consts here: not yet supported */
355 /* Limit imm_op within range imm8 */
357 tv = get_ia32_Immop_tarval(imm_op);
360 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
367 /* integer operations */
369 /* This is shift/rot with const */
370 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
372 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
373 set_ia32_Immop_attr(new_op, imm_op);
376 /* This is a normal shift/rot */
377 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
378 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
382 set_ia32_am_support(new_op, ia32_am_Dest);
384 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
386 set_ia32_res_mode(new_op, mode);
387 set_ia32_emit_cl(new_op);
389 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
394 * Construct a standard unary operation, set AM and immediate if required.
396 * @param env The transformation environment
397 * @param op The operand
398 * @param func The node constructor function
399 * @return The constructed ia32 node.
401 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
402 ir_node *new_op = NULL;
403 ir_mode *mode = env->mode;
404 dbg_info *dbg = env->dbg;
405 ir_graph *irg = env->irg;
406 ir_node *block = env->block;
407 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
408 ir_node *nomem = new_NoMem();
409 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
411 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
413 if (mode_is_float(mode)) {
414 DB((mod, LEVEL_1, "FP unop ..."));
415 /* floating point operations don't support implicit store */
416 set_ia32_am_support(new_op, ia32_am_None);
419 DB((mod, LEVEL_1, "INT unop ..."));
420 set_ia32_am_support(new_op, ia32_am_Dest);
423 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
425 set_ia32_res_mode(new_op, mode);
427 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
433 * Creates an ia32 Add with immediate.
435 * @param env The transformation environment
436 * @param expr_op The expression operator
437 * @param const_op The constant
438 * @return the created ia32 Add node
440 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
441 ir_node *new_op = NULL;
442 tarval *tv = get_ia32_Immop_tarval(const_op);
443 dbg_info *dbg = env->dbg;
444 ir_graph *irg = env->irg;
445 ir_node *block = env->block;
446 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
447 ir_node *nomem = new_NoMem();
449 tarval_classification_t class_tv, class_negtv;
450 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
452 /* try to optimize to inc/dec */
453 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
454 /* optimize tarvals */
455 class_tv = classify_tarval(tv);
456 class_negtv = classify_tarval(tarval_neg(tv));
458 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
459 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
460 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
463 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
464 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
465 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
471 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
472 set_ia32_Immop_attr(new_op, const_op);
473 set_ia32_commutative(new_op);
480 * Creates an ia32 Add.
482 * @param env The transformation environment
483 * @return the created ia32 Add node
485 static ir_node *gen_Add(ia32_transform_env_t *env) {
486 ir_node *new_op = NULL;
487 dbg_info *dbg = env->dbg;
488 ir_mode *mode = env->mode;
489 ir_graph *irg = env->irg;
490 ir_node *block = env->block;
491 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
492 ir_node *nomem = new_NoMem();
493 ir_node *expr_op, *imm_op;
494 ir_node *op1 = get_Add_left(env->irn);
495 ir_node *op2 = get_Add_right(env->irn);
497 /* Check if immediate optimization is on and */
498 /* if it's an operation with immediate. */
499 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
500 expr_op = get_expr_op(op1, op2);
502 assert((expr_op || imm_op) && "invalid operands");
504 if (mode_is_float(mode)) {
506 if (USE_SSE2(env->cg))
507 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
509 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
514 /* No expr_op means, that we have two const - one symconst and */
515 /* one tarval or another symconst - because this case is not */
516 /* covered by constant folding */
517 /* We need to check for: */
518 /* 1) symconst + const -> becomes a LEA */
519 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
520 /* linker doesn't support two symconsts */
522 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
523 /* this is the 2nd case */
524 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
525 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
526 set_ia32_am_flavour(new_op, ia32_am_OB);
528 DBG_OPT_LEA1(op2, new_op);
531 /* this is the 1st case */
532 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
534 DBG_OPT_LEA2(op1, op2, new_op);
536 if (get_ia32_op_type(op1) == ia32_SymConst) {
537 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
538 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
541 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
542 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
544 set_ia32_am_flavour(new_op, ia32_am_O);
548 set_ia32_am_support(new_op, ia32_am_Source);
549 set_ia32_op_type(new_op, ia32_AddrModeS);
551 /* Lea doesn't need a Proj */
555 /* This is expr + const */
556 new_op = gen_imm_Add(env, expr_op, imm_op);
559 set_ia32_am_support(new_op, ia32_am_Dest);
562 /* This is a normal add */
563 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
566 set_ia32_am_support(new_op, ia32_am_Full);
567 set_ia32_commutative(new_op);
571 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
573 set_ia32_res_mode(new_op, mode);
575 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
581 * Creates an ia32 Mul.
583 * @param env The transformation environment
584 * @return the created ia32 Mul node
586 static ir_node *gen_Mul(ia32_transform_env_t *env) {
587 ir_node *op1 = get_Mul_left(env->irn);
588 ir_node *op2 = get_Mul_right(env->irn);
591 if (mode_is_float(env->mode)) {
593 if (USE_SSE2(env->cg))
594 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
596 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
599 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
608 * Creates an ia32 Mulh.
609 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
610 * this result while Mul returns the lower 32 bit.
612 * @param env The transformation environment
613 * @return the created ia32 Mulh node
615 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
616 ir_node *op1 = get_irn_n(env->irn, 0);
617 ir_node *op2 = get_irn_n(env->irn, 1);
618 ir_node *proj_EAX, *proj_EDX, *mulh;
621 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
622 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
623 mulh = get_Proj_pred(proj_EAX);
624 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
626 /* to be on the save side */
627 set_Proj_proj(proj_EAX, pn_EAX);
629 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
630 /* Mulh with const cannot have AM */
631 set_ia32_am_support(mulh, ia32_am_None);
634 /* Mulh cannot have AM for destination */
635 set_ia32_am_support(mulh, ia32_am_Source);
641 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
649 * Creates an ia32 And.
651 * @param env The transformation environment
652 * @return The created ia32 And node
654 static ir_node *gen_And(ia32_transform_env_t *env) {
655 ir_node *op1 = get_And_left(env->irn);
656 ir_node *op2 = get_And_right(env->irn);
658 assert (! mode_is_float(env->mode));
659 return gen_binop(env, op1, op2, new_rd_ia32_And);
665 * Creates an ia32 Or.
667 * @param env The transformation environment
668 * @return The created ia32 Or node
670 static ir_node *gen_Or(ia32_transform_env_t *env) {
671 ir_node *op1 = get_Or_left(env->irn);
672 ir_node *op2 = get_Or_right(env->irn);
674 assert (! mode_is_float(env->mode));
675 return gen_binop(env, op1, op2, new_rd_ia32_Or);
681 * Creates an ia32 Eor.
683 * @param env The transformation environment
684 * @return The created ia32 Eor node
686 static ir_node *gen_Eor(ia32_transform_env_t *env) {
687 ir_node *op1 = get_Eor_left(env->irn);
688 ir_node *op2 = get_Eor_right(env->irn);
690 assert(! mode_is_float(env->mode));
691 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
697 * Creates an ia32 Max.
699 * @param env The transformation environment
700 * @return the created ia32 Max node
702 static ir_node *gen_Max(ia32_transform_env_t *env) {
703 ir_node *op1 = get_irn_n(env->irn, 0);
704 ir_node *op2 = get_irn_n(env->irn, 1);
707 if (mode_is_float(env->mode)) {
709 if (USE_SSE2(env->cg))
710 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
716 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
717 set_ia32_am_support(new_op, ia32_am_None);
718 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
727 * Creates an ia32 Min.
729 * @param env The transformation environment
730 * @return the created ia32 Min node
732 static ir_node *gen_Min(ia32_transform_env_t *env) {
733 ir_node *op1 = get_irn_n(env->irn, 0);
734 ir_node *op2 = get_irn_n(env->irn, 1);
737 if (mode_is_float(env->mode)) {
739 if (USE_SSE2(env->cg))
740 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
746 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
747 set_ia32_am_support(new_op, ia32_am_None);
748 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
757 * Creates an ia32 Sub with immediate.
759 * @param env The transformation environment
760 * @param expr_op The first operator
761 * @param const_op The constant operator
762 * @return The created ia32 Sub node
764 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
765 ir_node *new_op = NULL;
766 tarval *tv = get_ia32_Immop_tarval(const_op);
767 dbg_info *dbg = env->dbg;
768 ir_graph *irg = env->irg;
769 ir_node *block = env->block;
770 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
771 ir_node *nomem = new_NoMem();
773 tarval_classification_t class_tv, class_negtv;
774 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
776 /* try to optimize to inc/dec */
777 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
778 /* optimize tarvals */
779 class_tv = classify_tarval(tv);
780 class_negtv = classify_tarval(tarval_neg(tv));
782 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
783 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
784 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
787 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
788 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
789 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
795 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
796 set_ia32_Immop_attr(new_op, const_op);
803 * Creates an ia32 Sub.
805 * @param env The transformation environment
806 * @return The created ia32 Sub node
808 static ir_node *gen_Sub(ia32_transform_env_t *env) {
809 ir_node *new_op = NULL;
810 dbg_info *dbg = env->dbg;
811 ir_mode *mode = env->mode;
812 ir_graph *irg = env->irg;
813 ir_node *block = env->block;
814 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
815 ir_node *nomem = new_NoMem();
816 ir_node *op1 = get_Sub_left(env->irn);
817 ir_node *op2 = get_Sub_right(env->irn);
818 ir_node *expr_op, *imm_op;
820 /* Check if immediate optimization is on and */
821 /* if it's an operation with immediate. */
822 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
823 expr_op = get_expr_op(op1, op2);
825 assert((expr_op || imm_op) && "invalid operands");
827 if (mode_is_float(mode)) {
829 if (USE_SSE2(env->cg))
830 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
832 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
837 /* No expr_op means, that we have two const - one symconst and */
838 /* one tarval or another symconst - because this case is not */
839 /* covered by constant folding */
840 /* We need to check for: */
841 /* 1) symconst + const -> becomes a LEA */
842 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
843 /* linker doesn't support two symconsts */
845 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
846 /* this is the 2nd case */
847 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
848 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
849 set_ia32_am_sc_sign(new_op);
850 set_ia32_am_flavour(new_op, ia32_am_OB);
852 DBG_OPT_LEA1(op2, new_op);
855 /* this is the 1st case */
856 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
858 DBG_OPT_LEA2(op1, op2, new_op);
860 if (get_ia32_op_type(op1) == ia32_SymConst) {
861 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
862 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
865 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
866 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
867 set_ia32_am_sc_sign(new_op);
869 set_ia32_am_flavour(new_op, ia32_am_O);
873 set_ia32_am_support(new_op, ia32_am_Source);
874 set_ia32_op_type(new_op, ia32_AddrModeS);
876 /* Lea doesn't need a Proj */
880 /* This is expr - const */
881 new_op = gen_imm_Sub(env, expr_op, imm_op);
884 set_ia32_am_support(new_op, ia32_am_Dest);
887 /* This is a normal sub */
888 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
891 set_ia32_am_support(new_op, ia32_am_Full);
895 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
897 set_ia32_res_mode(new_op, mode);
899 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
905 * Generates an ia32 DivMod with additional infrastructure for the
906 * register allocator if needed.
908 * @param env The transformation environment
909 * @param dividend -no comment- :)
910 * @param divisor -no comment- :)
911 * @param dm_flav flavour_Div/Mod/DivMod
912 * @return The created ia32 DivMod node
914 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
916 ir_node *edx_node, *cltd;
918 dbg_info *dbg = env->dbg;
919 ir_graph *irg = env->irg;
920 ir_node *block = env->block;
921 ir_mode *mode = env->mode;
922 ir_node *irn = env->irn;
927 mem = get_Div_mem(irn);
928 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
931 mem = get_Mod_mem(irn);
932 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
935 mem = get_DivMod_mem(irn);
936 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
942 if (mode_is_signed(mode)) {
943 /* in signed mode, we need to sign extend the dividend */
944 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
945 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
946 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
949 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
950 set_ia32_Const_type(edx_node, ia32_Const);
951 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
954 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
956 set_ia32_n_res(res, 2);
958 /* Only one proj is used -> We must add a second proj and */
959 /* connect this one to a Keep node to eat up the second */
960 /* destroyed register. */
961 if (get_irn_n_edges(irn) == 1) {
962 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
963 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
965 if (get_irn_op(irn) == op_Div) {
966 set_Proj_proj(proj, pn_DivMod_res_div);
967 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
970 set_Proj_proj(proj, pn_DivMod_res_mod);
971 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
974 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
977 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
979 set_ia32_res_mode(res, mode_Is);
986 * Wrapper for generate_DivMod. Sets flavour_Mod.
988 * @param env The transformation environment
990 static ir_node *gen_Mod(ia32_transform_env_t *env) {
991 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
995 * Wrapper for generate_DivMod. Sets flavour_Div.
997 * @param env The transformation environment
999 static ir_node *gen_Div(ia32_transform_env_t *env) {
1000 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1004 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1006 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1007 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1013 * Creates an ia32 floating Div.
1015 * @param env The transformation environment
1016 * @return The created ia32 xDiv node
1018 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1019 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1021 ir_node *nomem = new_rd_NoMem(env->irg);
1022 ir_node *op1 = get_Quot_left(env->irn);
1023 ir_node *op2 = get_Quot_right(env->irn);
1026 if (USE_SSE2(env->cg)) {
1027 if (is_ia32_xConst(op2)) {
1028 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1029 set_ia32_am_support(new_op, ia32_am_None);
1030 set_ia32_Immop_attr(new_op, op2);
1033 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1034 set_ia32_am_support(new_op, ia32_am_Source);
1038 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1039 set_ia32_am_support(new_op, ia32_am_Source);
1041 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1042 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1050 * Creates an ia32 Shl.
1052 * @param env The transformation environment
1053 * @return The created ia32 Shl node
1055 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1056 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1062 * Creates an ia32 Shr.
1064 * @param env The transformation environment
1065 * @return The created ia32 Shr node
1067 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1068 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1074 * Creates an ia32 Shrs.
1076 * @param env The transformation environment
1077 * @return The created ia32 Shrs node
1079 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1080 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1086 * Creates an ia32 RotL.
1088 * @param env The transformation environment
1089 * @param op1 The first operator
1090 * @param op2 The second operator
1091 * @return The created ia32 RotL node
1093 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1094 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1100 * Creates an ia32 RotR.
1101 * NOTE: There is no RotR with immediate because this would always be a RotL
1102 * "imm-mode_size_bits" which can be pre-calculated.
1104 * @param env The transformation environment
1105 * @param op1 The first operator
1106 * @param op2 The second operator
1107 * @return The created ia32 RotR node
1109 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1110 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1116 * Creates an ia32 RotR or RotL (depending on the found pattern).
1118 * @param env The transformation environment
1119 * @return The created ia32 RotL or RotR node
1121 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1122 ir_node *rotate = NULL;
1123 ir_node *op1 = get_Rot_left(env->irn);
1124 ir_node *op2 = get_Rot_right(env->irn);
1126 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1127 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1128 that means we can create a RotR instead of an Add and a RotL */
1131 ir_node *pred = get_Proj_pred(op2);
1133 if (is_ia32_Add(pred)) {
1134 ir_node *pred_pred = get_irn_n(pred, 2);
1135 tarval *tv = get_ia32_Immop_tarval(pred);
1136 long bits = get_mode_size_bits(env->mode);
1138 if (is_Proj(pred_pred)) {
1139 pred_pred = get_Proj_pred(pred_pred);
1142 if (is_ia32_Minus(pred_pred) &&
1143 tarval_is_long(tv) &&
1144 get_tarval_long(tv) == bits)
1146 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1147 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1154 rotate = gen_RotL(env, op1, op2);
1163 * Transforms a Minus node.
1165 * @param env The transformation environment
1166 * @param op The Minus operand
1167 * @return The created ia32 Minus node
1169 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1174 if (mode_is_float(env->mode)) {
1176 if (USE_SSE2(env->cg)) {
1177 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1178 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1179 ir_node *nomem = new_rd_NoMem(env->irg);
1181 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1183 size = get_mode_size_bits(env->mode);
1184 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1186 set_ia32_sc(new_op, name);
1188 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1190 set_ia32_res_mode(new_op, env->mode);
1191 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1193 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1196 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1197 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1201 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1208 * Transforms a Minus node.
1210 * @param env The transformation environment
1211 * @return The created ia32 Minus node
1213 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1214 return gen_Minus_ex(env, get_Minus_op(env->irn));
1219 * Transforms a Not node.
1221 * @param env The transformation environment
1222 * @return The created ia32 Not node
1224 static ir_node *gen_Not(ia32_transform_env_t *env) {
1225 assert (! mode_is_float(env->mode));
1226 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1232 * Transforms an Abs node.
1234 * @param env The transformation environment
1235 * @return The created ia32 Abs node
1237 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1238 ir_node *res, *p_eax, *p_edx;
1239 dbg_info *dbg = env->dbg;
1240 ir_mode *mode = env->mode;
1241 ir_graph *irg = env->irg;
1242 ir_node *block = env->block;
1243 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1244 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1245 ir_node *nomem = new_NoMem();
1246 ir_node *op = get_Abs_op(env->irn);
1250 if (mode_is_float(mode)) {
1252 if (USE_SSE2(env->cg)) {
1253 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1255 size = get_mode_size_bits(mode);
1256 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1258 set_ia32_sc(res, name);
1260 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1262 set_ia32_res_mode(res, mode);
1263 set_ia32_immop_type(res, ia32_ImmSymConst);
1265 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1268 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1269 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1273 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1274 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1275 set_ia32_res_mode(res, mode);
1277 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1278 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1280 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1281 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1282 set_ia32_res_mode(res, mode);
1284 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1286 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1287 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1288 set_ia32_res_mode(res, mode);
1290 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1299 * Transforms a Load.
1301 * @param env The transformation environment
1302 * @return the created ia32 Load node
1304 static ir_node *gen_Load(ia32_transform_env_t *env) {
1305 ir_node *node = env->irn;
1306 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1307 ir_node *ptr = get_Load_ptr(node);
1308 ir_node *lptr = ptr;
1309 ir_mode *mode = get_Load_mode(node);
1312 ia32_am_flavour_t am_flav = ia32_B;
1314 /* address might be a constant (symconst or absolute address) */
1315 if (is_ia32_Const(ptr)) {
1320 if (mode_is_float(mode)) {
1322 if (USE_SSE2(env->cg))
1323 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1325 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1328 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1331 /* base is an constant address */
1333 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1334 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1337 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1343 set_ia32_am_support(new_op, ia32_am_Source);
1344 set_ia32_op_type(new_op, ia32_AddrModeS);
1345 set_ia32_am_flavour(new_op, am_flav);
1346 set_ia32_ls_mode(new_op, mode);
1348 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1356 * Transforms a Store.
1358 * @param env The transformation environment
1359 * @return the created ia32 Store node
1361 static ir_node *gen_Store(ia32_transform_env_t *env) {
1362 ir_node *node = env->irn;
1363 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1364 ir_node *val = get_Store_value(node);
1365 ir_node *ptr = get_Store_ptr(node);
1366 ir_node *sptr = ptr;
1367 ir_node *mem = get_Store_mem(node);
1368 ir_mode *mode = get_irn_mode(val);
1369 ir_node *sval = val;
1372 ia32_am_flavour_t am_flav = ia32_B;
1373 ia32_immop_type_t immop = ia32_ImmNone;
1375 if (! mode_is_float(mode)) {
1376 /* in case of storing a const (but not a symconst) -> make it an attribute */
1377 if (is_ia32_Cnst(val)) {
1378 switch (get_ia32_op_type(val)) {
1380 immop = ia32_ImmConst;
1383 immop = ia32_ImmSymConst;
1386 assert(0 && "unsupported Const type");
1392 /* address might be a constant (symconst or absolute address) */
1393 if (is_ia32_Const(ptr)) {
1398 if (mode_is_float(mode)) {
1400 if (USE_SSE2(env->cg))
1401 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1403 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1405 else if (get_mode_size_bits(mode) == 8) {
1406 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1409 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1412 /* stored const is an attribute (saves a register) */
1413 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1414 set_ia32_Immop_attr(new_op, val);
1417 /* base is an constant address */
1419 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1420 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1423 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1429 set_ia32_am_support(new_op, ia32_am_Dest);
1430 set_ia32_op_type(new_op, ia32_AddrModeD);
1431 set_ia32_am_flavour(new_op, am_flav);
1432 set_ia32_ls_mode(new_op, get_irn_mode(val));
1433 set_ia32_immop_type(new_op, immop);
1435 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1443 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1445 * @param env The transformation environment
1446 * @return The transformed node.
1448 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1449 dbg_info *dbg = env->dbg;
1450 ir_graph *irg = env->irg;
1451 ir_node *block = env->block;
1452 ir_node *node = env->irn;
1453 ir_node *sel = get_Cond_selector(node);
1454 ir_mode *sel_mode = get_irn_mode(sel);
1455 ir_node *res = NULL;
1456 ir_node *pred = NULL;
1457 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1458 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1460 if (is_Proj(sel) && sel_mode == mode_b) {
1461 ir_node *nomem = new_NoMem();
1463 pred = get_Proj_pred(sel);
1465 /* get both compare operators */
1466 cmp_a = get_Cmp_left(pred);
1467 cmp_b = get_Cmp_right(pred);
1469 /* check if we can use a CondJmp with immediate */
1470 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1471 expr = get_expr_op(cmp_a, cmp_b);
1474 pn_Cmp pnc = get_Proj_proj(sel);
1476 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1477 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1478 /* a Cmp A =/!= 0 */
1479 ir_node *op1 = expr;
1480 ir_node *op2 = expr;
1481 ir_node *and = skip_Proj(expr);
1482 const char *cnst = NULL;
1484 /* check, if expr is an only once used And operation */
1485 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1486 op1 = get_irn_n(and, 2);
1487 op2 = get_irn_n(and, 3);
1489 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1491 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1492 set_ia32_pncode(res, get_Proj_proj(sel));
1493 set_ia32_res_mode(res, get_irn_mode(op1));
1496 copy_ia32_Immop_attr(res, and);
1499 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1504 if (mode_is_float(get_irn_mode(expr))) {
1506 if (USE_SSE2(env->cg))
1507 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1513 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1515 set_ia32_Immop_attr(res, cnst);
1516 set_ia32_res_mode(res, get_irn_mode(expr));
1519 if (mode_is_float(get_irn_mode(cmp_a))) {
1521 if (USE_SSE2(env->cg))
1522 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1525 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1526 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1527 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1531 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1532 set_ia32_commutative(res);
1534 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1537 set_ia32_pncode(res, get_Proj_proj(sel));
1538 //set_ia32_am_support(res, ia32_am_Source);
1541 /* determine the smallest switch case value */
1542 int switch_min = INT_MAX;
1543 const ir_edge_t *edge;
1546 foreach_out_edge(node, edge) {
1547 int pn = get_Proj_proj(get_edge_src_irn(edge));
1548 switch_min = pn < switch_min ? pn : switch_min;
1552 /* if smallest switch case is not 0 we need an additional sub */
1553 snprintf(buf, sizeof(buf), "%d", switch_min);
1554 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1555 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1556 sub_ia32_am_offs(res, buf);
1557 set_ia32_am_flavour(res, ia32_am_OB);
1558 set_ia32_am_support(res, ia32_am_Source);
1559 set_ia32_op_type(res, ia32_AddrModeS);
1562 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1563 set_ia32_pncode(res, get_Cond_defaultProj(node));
1564 set_ia32_res_mode(res, get_irn_mode(sel));
1567 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1574 * Transforms a CopyB node.
1576 * @param env The transformation environment
1577 * @return The transformed node.
1579 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1580 ir_node *res = NULL;
1581 dbg_info *dbg = env->dbg;
1582 ir_graph *irg = env->irg;
1583 ir_mode *mode = env->mode;
1584 ir_node *block = env->block;
1585 ir_node *node = env->irn;
1586 ir_node *src = get_CopyB_src(node);
1587 ir_node *dst = get_CopyB_dst(node);
1588 ir_node *mem = get_CopyB_mem(node);
1589 int size = get_type_size_bytes(get_CopyB_type(node));
1592 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1593 /* then we need the size explicitly in ECX. */
1594 if (size >= 16 * 4) {
1595 rem = size & 0x3; /* size % 4 */
1598 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1599 set_ia32_op_type(res, ia32_Const);
1600 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1602 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1603 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1606 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1607 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1608 set_ia32_immop_type(res, ia32_ImmConst);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1619 * Transforms a Mux node into CMov.
1621 * @param env The transformation environment
1622 * @return The transformed node.
1624 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1626 ir_node *node = env->irn;
1627 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1628 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1630 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1637 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1638 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1641 * Transforms a Psi node into CMov.
1643 * @param env The transformation environment
1644 * @return The transformed node.
1646 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1647 ia32_code_gen_t *cg = env->cg;
1648 dbg_info *dbg = env->dbg;
1649 ir_graph *irg = env->irg;
1650 ir_mode *mode = env->mode;
1651 ir_node *block = env->block;
1652 ir_node *node = env->irn;
1653 ir_node *cmp_proj = get_Mux_sel(node);
1654 ir_node *psi_true = get_Psi_val(node, 0);
1655 ir_node *psi_default = get_Psi_default(node);
1656 ir_node *noreg = ia32_new_NoReg_gp(cg);
1657 ir_node *nomem = new_rd_NoMem(irg);
1658 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1661 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1663 cmp = get_Proj_pred(cmp_proj);
1664 cmp_a = get_Cmp_left(cmp);
1665 cmp_b = get_Cmp_right(cmp);
1666 pnc = get_Proj_proj(cmp_proj);
1668 if (mode_is_float(mode)) {
1669 /* floating point psi */
1672 /* 1st case: compare operands are float too */
1674 /* psi(cmp(a, b), t, f) can be done as: */
1675 /* tmp = cmp a, b */
1676 /* tmp2 = t and tmp */
1677 /* tmp3 = f and not tmp */
1678 /* res = tmp2 or tmp3 */
1680 /* in case the compare operands are int, we move them into xmm register */
1681 if (! mode_is_float(get_irn_mode(cmp_a))) {
1682 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1683 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1685 pnc |= 8; /* transform integer compare to fp compare */
1688 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1689 set_ia32_pncode(new_op, pnc);
1690 set_ia32_am_support(new_op, ia32_am_Source);
1691 set_ia32_res_mode(new_op, mode);
1692 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1693 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1695 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1696 set_ia32_am_support(and1, ia32_am_Source);
1697 set_ia32_res_mode(and1, mode);
1698 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1699 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1701 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1702 set_ia32_am_support(and2, ia32_am_Source);
1703 set_ia32_res_mode(and2, mode);
1704 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1705 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1707 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1708 set_ia32_am_support(new_op, ia32_am_Source);
1709 set_ia32_res_mode(new_op, mode);
1710 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1711 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1715 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1716 set_ia32_pncode(new_op, pnc);
1717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1722 construct_binop_func *set_func = NULL;
1723 cmov_func_t *cmov_func = NULL;
1725 if (mode_is_float(get_irn_mode(cmp_a))) {
1726 /* 1st case: compare operands are floats */
1731 set_func = new_rd_ia32_xCmpSet;
1732 cmov_func = new_rd_ia32_xCmpCMov;
1736 set_func = new_rd_ia32_vfCmpSet;
1737 cmov_func = new_rd_ia32_vfCmpCMov;
1740 pnc &= 7; /* fp compare -> int compare */
1743 /* 2nd case: compare operand are integer too */
1744 set_func = new_rd_ia32_CmpSet;
1745 cmov_func = new_rd_ia32_CmpCMov;
1748 /* create the nodes */
1750 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1751 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1752 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1753 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1754 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1755 set_ia32_pncode(new_op, pnc);
1757 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1758 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1759 /* we invert condition and set default to 0 */
1760 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1761 set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
1764 /* otherwise: use CMOVcc */
1765 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1766 set_ia32_pncode(new_op, pnc);
1769 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1773 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1774 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1775 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1776 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1777 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1779 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1780 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1781 /* we invert condition and set default to 0 */
1782 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1783 set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
1784 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1787 /* otherwise: use CMOVcc */
1788 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1789 set_ia32_pncode(new_op, pnc);
1790 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1800 * Following conversion rules apply:
1804 * 1) n bit -> m bit n > m (downscale)
1805 * a) target is signed: movsx
1806 * b) target is unsigned: and with lower bits sets
1807 * 2) n bit -> m bit n == m (sign change)
1809 * 3) n bit -> m bit n < m (upscale)
1810 * a) source is signed: movsx
1811 * b) source is unsigned: and with lower bits sets
1815 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1819 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1820 * if target mode < 32bit: additional INT -> INT conversion (see above)
1824 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1825 * x87 is mode_E internally, conversions happen only at load and store
1826 * in non-strict semantic
1830 * Create a conversion from x87 state register to general purpose.
1832 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1833 ia32_code_gen_t *cg = env->cg;
1834 entity *ent = cg->fp_to_gp;
1835 ir_graph *irg = env->irg;
1836 ir_node *block = env->block;
1837 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1838 ir_node *op = get_Conv_op(env->irn);
1839 ir_node *fist, *mem, *load;
1842 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1843 ent = cg->fp_to_gp =
1844 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1848 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1850 set_ia32_frame_ent(fist, ent);
1851 set_ia32_use_frame(fist);
1852 set_ia32_am_support(fist, ia32_am_Dest);
1853 set_ia32_op_type(fist, ia32_AddrModeD);
1854 set_ia32_am_flavour(fist, ia32_B);
1855 set_ia32_ls_mode(fist, mode_E);
1857 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1860 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1862 set_ia32_frame_ent(load, ent);
1863 set_ia32_use_frame(load);
1864 set_ia32_am_support(load, ia32_am_Source);
1865 set_ia32_op_type(load, ia32_AddrModeS);
1866 set_ia32_am_flavour(load, ia32_B);
1867 set_ia32_ls_mode(load, tgt_mode);
1869 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1873 * Create a conversion from x87 state register to general purpose.
1875 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1876 ia32_code_gen_t *cg = env->cg;
1877 entity *ent = cg->gp_to_fp;
1878 ir_graph *irg = env->irg;
1879 ir_node *block = env->block;
1880 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1881 ir_node *nomem = get_irg_no_mem(irg);
1882 ir_node *op = get_Conv_op(env->irn);
1883 ir_node *fild, *store, *mem;
1887 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1888 ent = cg->gp_to_fp =
1889 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1892 /* first convert to 32 bit */
1893 src_bits = get_mode_size_bits(src_mode);
1894 if (src_bits == 8) {
1895 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1896 op = new_r_Proj(irg, block, op, mode_Is, 0);
1898 else if (src_bits < 32) {
1899 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1900 op = new_r_Proj(irg, block, op, mode_Is, 0);
1904 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1906 set_ia32_frame_ent(store, ent);
1907 set_ia32_use_frame(store);
1909 set_ia32_am_support(store, ia32_am_Dest);
1910 set_ia32_op_type(store, ia32_AddrModeD);
1911 set_ia32_am_flavour(store, ia32_B);
1912 set_ia32_ls_mode(store, mode_Is);
1914 mem = new_r_Proj(irg, block, store, mode_M, 0);
1917 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1919 set_ia32_frame_ent(fild, ent);
1920 set_ia32_use_frame(fild);
1921 set_ia32_am_support(fild, ia32_am_Source);
1922 set_ia32_op_type(fild, ia32_AddrModeS);
1923 set_ia32_am_flavour(fild, ia32_B);
1924 set_ia32_ls_mode(fild, mode_E);
1926 return new_r_Proj(irg, block, fild, mode_E, 0);
1930 * Transforms a Conv node.
1932 * @param env The transformation environment
1933 * @return The created ia32 Conv node
1935 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1936 dbg_info *dbg = env->dbg;
1937 ir_graph *irg = env->irg;
1938 ir_node *op = get_Conv_op(env->irn);
1939 ir_mode *src_mode = get_irn_mode(op);
1940 ir_mode *tgt_mode = env->mode;
1941 int src_bits = get_mode_size_bits(src_mode);
1942 int tgt_bits = get_mode_size_bits(tgt_mode);
1944 ir_node *block = env->block;
1945 ir_node *new_op = NULL;
1946 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1947 ir_node *nomem = new_rd_NoMem(irg);
1949 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1951 if (src_mode == tgt_mode) {
1952 /* this can happen when changing mode_P to mode_Is */
1953 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1954 edges_reroute(env->irn, op, irg);
1956 else if (mode_is_float(src_mode)) {
1957 /* we convert from float ... */
1958 if (mode_is_float(tgt_mode)) {
1960 if (USE_SSE2(env->cg)) {
1961 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1962 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1963 pn = pn_ia32_Conv_FP2FP_res;
1966 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1967 edges_reroute(env->irn, op, irg);
1972 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1973 if (USE_SSE2(env->cg)) {
1974 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1975 pn = pn_ia32_Conv_FP2I_res;
1978 return gen_x87_fp_to_gp(env, tgt_mode);
1980 /* if target mode is not int: add an additional downscale convert */
1981 if (tgt_bits < 32) {
1982 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1983 set_ia32_am_support(new_op, ia32_am_Source);
1984 set_ia32_tgt_mode(new_op, tgt_mode);
1985 set_ia32_src_mode(new_op, src_mode);
1987 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
1989 if (tgt_bits == 8 || src_bits == 8) {
1990 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1991 pn = pn_ia32_Conv_I2I8Bit_res;
1994 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1995 pn = pn_ia32_Conv_I2I_res;
2001 /* we convert from int ... */
2002 if (mode_is_float(tgt_mode)) {
2005 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2006 if (USE_SSE2(env->cg)) {
2007 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2008 pn = pn_ia32_Conv_I2FP_res;
2011 return gen_x87_gp_to_fp(env, src_mode);
2015 if (get_mode_size_bits(src_mode) == tgt_bits) {
2016 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2017 edges_reroute(env->irn, op, irg);
2020 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2021 if (tgt_bits == 8 || src_bits == 8) {
2022 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2023 pn = pn_ia32_Conv_I2I8Bit_res;
2026 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2027 pn = pn_ia32_Conv_I2I_res;
2034 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2035 set_ia32_tgt_mode(new_op, tgt_mode);
2036 set_ia32_src_mode(new_op, src_mode);
2038 set_ia32_am_support(new_op, ia32_am_Source);
2040 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2048 /********************************************
2051 * | |__ ___ _ __ ___ __| | ___ ___
2052 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2053 * | |_) | __/ | | | (_) | (_| | __/\__ \
2054 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2056 ********************************************/
2059 * Decides in which block the transformed StackParam should be placed.
2060 * If the StackParam has more than one user, the dominator block of
2061 * the users will be returned. In case of only one user, this is either
2062 * the user block or, in case of a Phi, the predecessor block of the Phi.
2064 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2065 ir_node *dom_bl = NULL;
2067 if (get_irn_n_edges(irn) == 1) {
2068 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2070 if (! is_Phi(src)) {
2071 dom_bl = get_nodes_block(src);
2074 /* Determine on which in position of the Phi the irn is */
2075 /* and get the corresponding cfg predecessor block. */
2077 int i = get_irn_pred_pos(src, irn);
2078 assert(i >= 0 && "kaputt");
2079 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2083 dom_bl = node_users_smallest_common_dominator(irn, 1);
2086 assert(dom_bl && "dominator block not found");
2091 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2092 ir_node *new_op = NULL;
2093 ir_node *node = env->irn;
2094 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2095 ir_node *mem = new_rd_NoMem(env->irg);
2096 ir_node *ptr = get_irn_n(node, 0);
2097 entity *ent = be_get_frame_entity(node);
2098 ir_mode *mode = env->mode;
2100 /* choose the block where to place the load */
2101 env->block = get_block_transformed_stack_param(node);
2103 if (mode_is_float(mode)) {
2105 if (USE_SSE2(env->cg))
2106 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2108 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2111 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2114 set_ia32_frame_ent(new_op, ent);
2115 set_ia32_use_frame(new_op);
2117 set_ia32_am_support(new_op, ia32_am_Source);
2118 set_ia32_op_type(new_op, ia32_AddrModeS);
2119 set_ia32_am_flavour(new_op, ia32_B);
2120 set_ia32_ls_mode(new_op, mode);
2122 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2124 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2128 * Transforms a FrameAddr into an ia32 Add.
2130 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2131 ir_node *new_op = NULL;
2132 ir_node *node = env->irn;
2133 ir_node *op = get_irn_n(node, 0);
2134 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2135 ir_node *nomem = new_rd_NoMem(env->irg);
2137 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2138 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2139 set_ia32_am_support(new_op, ia32_am_Full);
2140 set_ia32_use_frame(new_op);
2141 set_ia32_immop_type(new_op, ia32_ImmConst);
2142 set_ia32_commutative(new_op);
2144 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2146 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2150 * Transforms a FrameLoad into an ia32 Load.
2152 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2153 ir_node *new_op = NULL;
2154 ir_node *node = env->irn;
2155 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2156 ir_node *mem = get_irn_n(node, 0);
2157 ir_node *ptr = get_irn_n(node, 1);
2158 entity *ent = be_get_frame_entity(node);
2159 ir_mode *mode = get_type_mode(get_entity_type(ent));
2161 if (mode_is_float(mode)) {
2163 if (USE_SSE2(env->cg))
2164 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2166 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2169 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2171 set_ia32_frame_ent(new_op, ent);
2172 set_ia32_use_frame(new_op);
2174 set_ia32_am_support(new_op, ia32_am_Source);
2175 set_ia32_op_type(new_op, ia32_AddrModeS);
2176 set_ia32_am_flavour(new_op, ia32_B);
2177 set_ia32_ls_mode(new_op, mode);
2179 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2186 * Transforms a FrameStore into an ia32 Store.
2188 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2189 ir_node *new_op = NULL;
2190 ir_node *node = env->irn;
2191 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2192 ir_node *mem = get_irn_n(node, 0);
2193 ir_node *ptr = get_irn_n(node, 1);
2194 ir_node *val = get_irn_n(node, 2);
2195 entity *ent = be_get_frame_entity(node);
2196 ir_mode *mode = get_irn_mode(val);
2198 if (mode_is_float(mode)) {
2200 if (USE_SSE2(env->cg))
2201 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2203 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2205 else if (get_mode_size_bits(mode) == 8) {
2206 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2209 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2212 set_ia32_frame_ent(new_op, ent);
2213 set_ia32_use_frame(new_op);
2215 set_ia32_am_support(new_op, ia32_am_Dest);
2216 set_ia32_op_type(new_op, ia32_AddrModeD);
2217 set_ia32_am_flavour(new_op, ia32_B);
2218 set_ia32_ls_mode(new_op, mode);
2220 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2226 * This function just sets the register for the Unknown node
2227 * as this is not done during register allocation because Unknown
2228 * is an "ignore" node.
2230 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2231 ir_mode *mode = env->mode;
2232 ir_node *irn = env->irn;
2234 if (mode_is_float(mode)) {
2235 if (USE_SSE2(env->cg))
2236 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2238 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2240 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2241 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2244 assert(0 && "unsupported Unknown-Mode");
2251 /*********************************************************
2254 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2255 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2256 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2257 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2259 *********************************************************/
2262 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2263 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2265 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2266 ia32_transform_env_t tenv;
2267 ir_node *in1, *in2, *noreg, *nomem, *res;
2268 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2270 /* Return if AM node or not a Sub or xSub */
2271 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2274 noreg = ia32_new_NoReg_gp(cg);
2275 nomem = new_rd_NoMem(cg->irg);
2276 in1 = get_irn_n(irn, 2);
2277 in2 = get_irn_n(irn, 3);
2278 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2279 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2280 out_reg = get_ia32_out_reg(irn, 0);
2282 tenv.block = get_nodes_block(irn);
2283 tenv.dbg = get_irn_dbg_info(irn);
2286 tenv.mode = get_ia32_res_mode(irn);
2288 DEBUG_ONLY(tenv.mod = cg->mod;)
2290 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2291 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2292 /* generate the neg src2 */
2293 res = gen_Minus_ex(&tenv, in2);
2294 arch_set_irn_register(cg->arch_env, res, in2_reg);
2296 /* add to schedule */
2297 sched_add_before(irn, res);
2299 /* generate the add */
2300 if (mode_is_float(tenv.mode)) {
2301 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2302 set_ia32_am_support(res, ia32_am_Source);
2305 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2306 set_ia32_am_support(res, ia32_am_Full);
2307 set_ia32_commutative(res);
2309 set_ia32_res_mode(res, tenv.mode);
2311 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2313 slots = get_ia32_slots(res);
2316 /* add to schedule */
2317 sched_add_before(irn, res);
2319 /* remove the old sub */
2322 DBG_OPT_SUB2NEGADD(irn, res);
2324 /* exchange the add and the sub */
2330 * Transforms a LEA into an Add if possible
2331 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2333 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2334 ia32_am_flavour_t am_flav;
2336 ir_node *res = NULL;
2337 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2339 ia32_transform_env_t tenv;
2340 const arch_register_t *out_reg, *base_reg, *index_reg;
2343 if (! is_ia32_Lea(irn))
2346 am_flav = get_ia32_am_flavour(irn);
2348 /* only some LEAs can be transformed to an Add */
2349 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2352 noreg = ia32_new_NoReg_gp(cg);
2353 nomem = new_rd_NoMem(cg->irg);
2356 base = get_irn_n(irn, 0);
2357 index = get_irn_n(irn,1);
2359 offs = get_ia32_am_offs(irn);
2361 /* offset has a explicit sign -> we need to skip + */
2362 if (offs && offs[0] == '+')
2365 out_reg = arch_get_irn_register(cg->arch_env, irn);
2366 base_reg = arch_get_irn_register(cg->arch_env, base);
2367 index_reg = arch_get_irn_register(cg->arch_env, index);
2369 tenv.block = get_nodes_block(irn);
2370 tenv.dbg = get_irn_dbg_info(irn);
2373 DEBUG_ONLY(tenv.mod = cg->mod;)
2374 tenv.mode = get_irn_mode(irn);
2377 switch(get_ia32_am_flavour(irn)) {
2379 /* out register must be same as base register */
2380 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2386 /* out register must be same as base register */
2387 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2394 /* out register must be same as index register */
2395 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2402 /* out register must be same as one in register */
2403 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2407 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2412 /* in registers a different from out -> no Add possible */
2419 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2420 arch_set_irn_register(cg->arch_env, res, out_reg);
2421 set_ia32_op_type(res, ia32_Normal);
2422 set_ia32_commutative(res);
2423 set_ia32_res_mode(res, tenv.mode);
2426 set_ia32_cnst(res, offs);
2427 set_ia32_immop_type(res, ia32_ImmConst);
2430 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2432 /* add Add to schedule */
2433 sched_add_before(irn, res);
2435 DBG_OPT_LEA2ADD(irn, res);
2437 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2439 /* add result Proj to schedule */
2440 sched_add_before(irn, res);
2442 /* remove the old LEA */
2445 /* exchange the Add and the LEA */
2450 * the BAD transformer.
2452 static ir_node *bad_transform(ia32_transform_env_t *env) {
2453 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2459 * Enters all transform functions into the generic pointer
2461 void ia32_register_transformers(void) {
2462 ir_op *op_Max, *op_Min, *op_Mulh;
2464 /* first clear the generic function pointer for all ops */
2465 clear_irp_opcodes_generic_func();
2467 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2468 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2515 /* constant transformation happens earlier */
2539 /* set the register for all Unknown nodes */
2542 op_Max = get_op_Max();
2545 op_Min = get_op_Min();
2548 op_Mulh = get_op_Mulh();
2557 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2560 * Transforms the given firm node (and maybe some other related nodes)
2561 * into one or more assembler nodes.
2563 * @param node the firm node
2564 * @param env the debug module
2566 void ia32_transform_node(ir_node *node, void *env) {
2567 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2568 ir_op *op = get_irn_op(node);
2569 ir_node *asm_node = NULL;
2575 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2576 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2577 if (is_Unknown(get_irn_n(node, i)))
2578 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2581 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2582 if (op->ops.generic) {
2583 ia32_transform_env_t tenv;
2584 transform_func *transform = (transform_func *)op->ops.generic;
2586 tenv.block = get_nodes_block(node);
2587 tenv.dbg = get_irn_dbg_info(node);
2588 tenv.irg = current_ir_graph;
2590 tenv.mode = get_irn_mode(node);
2592 DEBUG_ONLY(tenv.mod = cg->mod;)
2594 asm_node = (*transform)(&tenv);
2597 /* exchange nodes if a new one was generated */
2599 exchange(node, asm_node);
2600 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2603 DB((cg->mod, LEVEL_1, "ignored\n"));
2608 * Transforms a psi condition.
2610 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2613 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2614 set_irn_mode(cond, mode);
2616 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2617 ir_node *in = get_irn_n(cond, i);
2619 /* if in is a compare: transform into Set/xCmp */
2621 ir_node *new_op = NULL;
2622 ir_node *cmp = get_Proj_pred(in);
2623 ir_node *cmp_a = get_Cmp_left(cmp);
2624 ir_node *cmp_b = get_Cmp_right(cmp);
2625 dbg_info *dbg = get_irn_dbg_info(cmp);
2626 ir_graph *irg = get_irn_irg(cmp);
2627 ir_node *block = get_nodes_block(cmp);
2628 ir_node *noreg = ia32_new_NoReg_gp(cg);
2629 ir_node *nomem = new_rd_NoMem(irg);
2630 int pnc = get_Proj_proj(in);
2632 /* this is a compare */
2633 if (mode_is_float(mode)) {
2634 /* Psi is float, we need a floating point compare */
2638 if (! mode_is_float(get_irn_mode(cmp_a))) {
2639 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2640 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2644 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2645 set_ia32_pncode(new_op, pnc);
2646 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2655 ia32_transform_env_t tenv;
2656 construct_binop_func *set_func = NULL;
2658 if (mode_is_float(get_irn_mode(cmp_a))) {
2659 /* 1st case: compare operands are floats */
2664 set_func = new_rd_ia32_xCmpSet;
2668 set_func = new_rd_ia32_vfCmpSet;
2671 pnc &= 7; /* fp compare -> int compare */
2674 /* 2nd case: compare operand are integer too */
2675 set_func = new_rd_ia32_CmpSet;
2686 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2687 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2688 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2691 /* exchange with old compare */
2692 exchange(in, new_op);
2695 /* another complex condition */
2696 transform_psi_cond(in, mode, cg);
2702 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2703 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2704 * compare, which causes the compare result to be stores in a register. The
2705 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2707 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2708 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2709 ir_node *psi_sel, *new_cmp, *block;
2714 if (get_irn_opcode(node) != iro_Psi)
2717 psi_sel = get_Psi_cond(node, 0);
2719 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2720 if (is_Proj(psi_sel))
2723 mode = get_irn_mode(node);
2725 transform_psi_cond(psi_sel, mode, cg);
2727 irg = get_irn_irg(node);
2728 block = get_nodes_block(node);
2730 /* we need to compare the evaluated condition tree with 0 */
2732 /* BEWARE: new_r_Const_long works for floating point as well */
2733 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2734 /* transform the const */
2735 ia32_place_consts_set_modes(new_cmp, cg);
2736 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2738 set_Psi_cond(node, 0, new_cmp);