2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *new_block,
127 * Return true if a mode can be stored in the GP register set
129 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
130 if(mode == mode_fpcw)
132 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
136 * Returns 1 if irn is a Const representing 0, 0 otherwise
138 static INLINE int is_ia32_Const_0(ir_node *irn) {
139 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
140 && tarval_is_null(get_ia32_Immop_tarval(irn));
144 * Returns 1 if irn is a Const representing 1, 0 otherwise
146 static INLINE int is_ia32_Const_1(ir_node *irn) {
147 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
148 && tarval_is_one(get_ia32_Immop_tarval(irn));
152 * Collects all Projs of a node into the node array. Index is the projnum.
153 * BEWARE: The caller has to assure the appropriate array size!
155 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
156 const ir_edge_t *edge;
157 assert(get_irn_mode(irn) == mode_T && "need mode_T");
159 memset(projs, 0, size * sizeof(projs[0]));
161 foreach_out_edge(irn, edge) {
162 ir_node *proj = get_edge_src_irn(edge);
163 int proj_proj = get_Proj_proj(proj);
164 assert(proj_proj < size);
165 projs[proj_proj] = proj;
170 * Renumbers the proj having pn_old in the array tp pn_new
171 * and removes the proj from the array.
173 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
174 fprintf(stderr, "Warning: renumber_Proj used!\n");
176 set_Proj_proj(projs[pn_old], pn_new);
177 projs[pn_old] = NULL;
182 * creates a unique ident by adding a number to a tag
184 * @param tag the tag string, must contain a %d if a number
187 static ident *unique_id(const char *tag)
189 static unsigned id = 0;
192 snprintf(str, sizeof(str), tag, ++id);
193 return new_id_from_str(str);
197 * Get a primitive type for a mode.
199 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
201 pmap_entry *e = pmap_find(types, mode);
206 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
207 res = new_type_primitive(new_id_from_str(buf), mode);
208 set_type_alignment_bytes(res, 16);
209 pmap_insert(types, mode, res);
217 * Get an entity that is initialized with a tarval
219 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
221 tarval *tv = get_Const_tarval(cnst);
222 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
227 ir_mode *mode = get_irn_mode(cnst);
228 ir_type *tp = get_Const_type(cnst);
229 if (tp == firm_unknown_type)
230 tp = get_prim_type(cg->isa->types, mode);
232 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
234 set_entity_ld_ident(res, get_entity_ident(res));
235 set_entity_visibility(res, visibility_local);
236 set_entity_variability(res, variability_constant);
237 set_entity_allocation(res, allocation_static);
239 /* we create a new entity here: It's initialization must resist on the
241 rem = current_ir_graph;
242 current_ir_graph = get_const_code_irg();
243 set_atomic_ent_value(res, new_Const_type(tv, tp));
244 current_ir_graph = rem;
246 pmap_insert(cg->isa->tv_ent, tv, res);
254 static int is_Const_0(ir_node *node) {
258 return classify_Const(node) == CNST_NULL;
261 static int is_Const_1(ir_node *node) {
265 return classify_Const(node) == CNST_ONE;
269 * Transforms a Const.
271 static ir_node *gen_Const(ir_node *node) {
272 ir_graph *irg = current_ir_graph;
273 ir_node *old_block = get_nodes_block(node);
274 ir_node *block = be_transform_node(old_block);
275 dbg_info *dbgi = get_irn_dbg_info(node);
276 ir_mode *mode = get_irn_mode(node);
278 if (mode_is_float(mode)) {
280 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
281 ir_node *nomem = new_NoMem();
285 if (! USE_SSE2(env_cg)) {
286 cnst_classify_t clss = classify_Const(node);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = get_entity_for_tv(env_cg, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
302 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
304 set_ia32_ls_mode(load, mode);
306 floatent = get_entity_for_tv(env_cg, node);
308 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
313 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
315 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
318 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 /* Const Nodes before the initial IncSP are a bad idea, because
321 * they could be spilled and we have no SP ready at that point yet.
322 * So add a dependency to the initial frame pointer calculation to
323 * avoid that situation.
325 if (get_irg_start_block(irg) == block) {
326 add_irn_dep(load, get_irg_frame(irg));
329 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
332 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
339 set_ia32_Const_attr(cnst, node);
340 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
345 return new_r_Bad(irg);
349 * Transforms a SymConst.
351 static ir_node *gen_SymConst(ir_node *node) {
352 ir_graph *irg = current_ir_graph;
353 ir_node *old_block = get_nodes_block(node);
354 ir_node *block = be_transform_node(old_block);
355 dbg_info *dbgi = get_irn_dbg_info(node);
356 ir_mode *mode = get_irn_mode(node);
359 if (mode_is_float(mode)) {
360 if (USE_SSE2(env_cg))
361 cnst = new_rd_ia32_xConst(dbgi, irg, block);
363 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
364 //set_ia32_ls_mode(cnst, mode);
365 set_ia32_ls_mode(cnst, mode_E);
367 cnst = new_rd_ia32_Const(dbgi, irg, block);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 set_ia32_Const_attr(cnst, node);
378 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
383 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
384 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
385 static const struct {
387 const char *ent_name;
388 const char *cnst_str;
389 } names [ia32_known_const_max] = {
390 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
391 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
392 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
393 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
395 static ir_entity *ent_cache[ia32_known_const_max];
397 const char *tp_name, *ent_name, *cnst_str;
405 ent_name = names[kct].ent_name;
406 if (! ent_cache[kct]) {
407 tp_name = names[kct].tp_name;
408 cnst_str = names[kct].cnst_str;
410 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
412 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
413 tp = new_type_primitive(new_id_from_str(tp_name), mode);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 /* determine if one operator is an Imm */
451 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
453 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
455 return is_ia32_Cnst(op2) ? op2 : NULL;
459 /* determine if one operator is not an Imm */
460 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
461 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
464 static void fold_immediate(ir_node *node, int in1, int in2) {
468 if (!(env_cg->opt & IA32_OPT_IMMOPS))
471 left = get_irn_n(node, in1);
472 right = get_irn_n(node, in2);
473 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
474 /* we can only set right operand to immediate */
475 if(!is_ia32_commutative(node))
477 /* exchange left/right */
478 set_irn_n(node, in1, right);
479 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
480 copy_ia32_Immop_attr(node, left);
481 } else if(is_ia32_Cnst(right)) {
482 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
483 copy_ia32_Immop_attr(node, right);
488 clear_ia32_commutative(node);
489 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
490 get_ia32_am_arity(node));
494 * Construct a standard binary operation, set AM and immediate if required.
496 * @param op1 The first operand
497 * @param op2 The second operand
498 * @param func The node constructor function
499 * @return The constructed ia32 node.
501 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
502 construct_binop_func *func, int commutative)
504 ir_node *block = be_transform_node(get_nodes_block(node));
505 ir_graph *irg = current_ir_graph;
506 dbg_info *dbgi = get_irn_dbg_info(node);
507 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
508 ir_node *nomem = new_NoMem();
511 ir_node *new_op1 = be_transform_node(op1);
512 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
513 if (is_ia32_Immediate(new_op2)) {
517 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
518 if (func == new_rd_ia32_IMul) {
519 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
521 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
524 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
526 set_ia32_commutative(new_node);
533 * Construct a standard binary operation, set AM and immediate if required.
535 * @param op1 The first operand
536 * @param op2 The second operand
537 * @param func The node constructor function
538 * @return The constructed ia32 node.
540 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
541 construct_binop_func *func)
543 ir_node *block = be_transform_node(get_nodes_block(node));
544 ir_node *new_op1 = be_transform_node(op1);
545 ir_node *new_op2 = be_transform_node(op2);
546 ir_node *new_node = NULL;
547 dbg_info *dbgi = get_irn_dbg_info(node);
548 ir_graph *irg = current_ir_graph;
549 ir_mode *mode = get_irn_mode(node);
550 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
551 ir_node *nomem = new_NoMem();
553 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
555 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
556 if (is_op_commutative(get_irn_op(node))) {
557 set_ia32_commutative(new_node);
559 set_ia32_ls_mode(new_node, mode);
561 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
566 static ir_node *get_fpcw(void)
569 if(initial_fpcw != NULL)
572 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
573 &ia32_fp_cw_regs[REG_FPCW]);
574 initial_fpcw = be_transform_node(fpcw);
580 * Construct a standard binary operation, set AM and immediate if required.
582 * @param op1 The first operand
583 * @param op2 The second operand
584 * @param func The node constructor function
585 * @return The constructed ia32 node.
587 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
588 construct_binop_float_func *func)
590 ir_node *block = be_transform_node(get_nodes_block(node));
591 ir_node *new_op1 = be_transform_node(op1);
592 ir_node *new_op2 = be_transform_node(op2);
593 ir_node *new_node = NULL;
594 dbg_info *dbgi = get_irn_dbg_info(node);
595 ir_graph *irg = current_ir_graph;
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
601 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
602 if (is_op_commutative(get_irn_op(node))) {
603 set_ia32_commutative(new_node);
606 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
612 * Construct a shift/rotate binary operation, sets AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func)
622 ir_node *block = be_transform_node(get_nodes_block(node));
623 ir_node *new_op1 = be_transform_node(op1);
625 ir_node *new_op = NULL;
626 dbg_info *dbgi = get_irn_dbg_info(node);
627 ir_graph *irg = current_ir_graph;
628 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
629 ir_node *nomem = new_NoMem();
631 assert(! mode_is_float(get_irn_mode(node))
632 && "Shift/Rotate with float not supported");
634 new_op2 = create_immediate_or_transform(op2, 'N');
636 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
639 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
643 set_ia32_emit_cl(new_op);
650 * Construct a standard unary operation, set AM and immediate if required.
652 * @param op The operand
653 * @param func The node constructor function
654 * @return The constructed ia32 node.
656 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
658 ir_node *block = be_transform_node(get_nodes_block(node));
659 ir_node *new_op = be_transform_node(op);
660 ir_node *new_node = NULL;
661 ir_graph *irg = current_ir_graph;
662 dbg_info *dbgi = get_irn_dbg_info(node);
663 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
667 DB((dbg, LEVEL_1, "INT unop ..."));
668 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
670 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
676 * Creates an ia32 Add.
678 * @return the created ia32 Add node
680 static ir_node *gen_Add(ir_node *node) {
681 ir_node *block = be_transform_node(get_nodes_block(node));
682 ir_node *op1 = get_Add_left(node);
683 ir_node *new_op1 = be_transform_node(op1);
684 ir_node *op2 = get_Add_right(node);
685 ir_node *new_op2 = be_transform_node(op2);
686 ir_node *new_op = NULL;
687 ir_graph *irg = current_ir_graph;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_mode *mode = get_irn_mode(node);
690 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
691 ir_node *nomem = new_NoMem();
692 ir_node *expr_op, *imm_op;
694 /* Check if immediate optimization is on and */
695 /* if it's an operation with immediate. */
696 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
697 expr_op = get_expr_op(new_op1, new_op2);
699 assert((expr_op || imm_op) && "invalid operands");
701 if (mode_is_float(mode)) {
702 if (USE_SSE2(env_cg))
703 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
705 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
710 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
711 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
713 /* No expr_op means, that we have two const - one symconst and */
714 /* one tarval or another symconst - because this case is not */
715 /* covered by constant folding */
716 /* We need to check for: */
717 /* 1) symconst + const -> becomes a LEA */
718 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
719 /* linker doesn't support two symconsts */
721 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
722 /* this is the 2nd case */
723 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
724 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
725 set_ia32_am_flavour(new_op, ia32_am_B);
726 set_ia32_op_type(new_op, ia32_AddrModeS);
728 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 } else if (tp1 == ia32_ImmSymConst) {
730 tarval *tv = get_ia32_Immop_tarval(new_op2);
731 long offs = get_tarval_long(tv);
733 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
734 add_irn_dep(new_op, get_irg_frame(irg));
735 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
737 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
738 add_ia32_am_offs_int(new_op, offs);
739 set_ia32_am_flavour(new_op, ia32_am_OB);
740 set_ia32_op_type(new_op, ia32_AddrModeS);
741 } else if (tp2 == ia32_ImmSymConst) {
742 tarval *tv = get_ia32_Immop_tarval(new_op1);
743 long offs = get_tarval_long(tv);
745 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
746 add_irn_dep(new_op, get_irg_frame(irg));
747 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
749 add_ia32_am_offs_int(new_op, offs);
750 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
751 set_ia32_am_flavour(new_op, ia32_am_OB);
752 set_ia32_op_type(new_op, ia32_AddrModeS);
754 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
755 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
756 tarval *restv = tarval_add(tv1, tv2);
758 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
760 new_op = new_rd_ia32_Const(dbgi, irg, block);
761 set_ia32_Const_tarval(new_op, restv);
762 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
765 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
768 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
769 tarval_classification_t class_tv, class_negtv;
770 tarval *tv = get_ia32_Immop_tarval(imm_op);
772 /* optimize tarvals */
773 class_tv = classify_tarval(tv);
774 class_negtv = classify_tarval(tarval_neg(tv));
776 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
777 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
778 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
779 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
781 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
782 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
784 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
790 /* This is a normal add */
791 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
794 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
795 set_ia32_commutative(new_op);
797 fold_immediate(new_op, 2, 3);
799 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
805 * Creates an ia32 Mul.
807 * @return the created ia32 Mul node
809 static ir_node *gen_Mul(ir_node *node) {
810 ir_node *op1 = get_Mul_left(node);
811 ir_node *op2 = get_Mul_right(node);
812 ir_mode *mode = get_irn_mode(node);
814 if (mode_is_float(mode)) {
815 if (USE_SSE2(env_cg))
816 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
818 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
822 for the lower 32bit of the result it doesn't matter whether we use
823 signed or unsigned multiplication so we use IMul as it has fewer
826 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
830 * Creates an ia32 Mulh.
831 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
832 * this result while Mul returns the lower 32 bit.
834 * @return the created ia32 Mulh node
836 static ir_node *gen_Mulh(ir_node *node) {
837 ir_node *block = be_transform_node(get_nodes_block(node));
838 ir_node *op1 = get_irn_n(node, 0);
839 ir_node *new_op1 = be_transform_node(op1);
840 ir_node *op2 = get_irn_n(node, 1);
841 ir_node *new_op2 = be_transform_node(op2);
842 ir_graph *irg = current_ir_graph;
843 dbg_info *dbgi = get_irn_dbg_info(node);
844 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
845 ir_mode *mode = get_irn_mode(node);
846 ir_node *proj_EDX, *res;
848 assert(!mode_is_float(mode) && "Mulh with float not supported");
849 if (mode_is_signed(mode)) {
850 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
851 new_op2, new_NoMem());
853 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
857 set_ia32_commutative(res);
858 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
860 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
868 * Creates an ia32 And.
870 * @return The created ia32 And node
872 static ir_node *gen_And(ir_node *node) {
873 ir_node *op1 = get_And_left(node);
874 ir_node *op2 = get_And_right(node);
875 assert(! mode_is_float(get_irn_mode(node)));
877 /* check for zero extension first */
879 tarval *tv = get_Const_tarval(op2);
880 long v = get_tarval_long(tv);
882 if (v == 0xFF || v == 0xFFFF) {
883 dbg_info *dbgi = get_irn_dbg_info(node);
884 ir_node *block = be_transform_node(get_nodes_block(node));
885 ir_node *new_op = be_transform_node(op1);
895 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
896 ir_fprintf(stderr, "and %+F -> conv %+F\n", node, res);
897 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
903 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
909 * Creates an ia32 Or.
911 * @return The created ia32 Or node
913 static ir_node *gen_Or(ir_node *node) {
914 ir_node *op1 = get_Or_left(node);
915 ir_node *op2 = get_Or_right(node);
917 assert (! mode_is_float(get_irn_mode(node)));
918 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
924 * Creates an ia32 Eor.
926 * @return The created ia32 Eor node
928 static ir_node *gen_Eor(ir_node *node) {
929 ir_node *op1 = get_Eor_left(node);
930 ir_node *op2 = get_Eor_right(node);
932 assert(! mode_is_float(get_irn_mode(node)));
933 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
938 * Creates an ia32 Sub.
940 * @return The created ia32 Sub node
942 static ir_node *gen_Sub(ir_node *node) {
943 ir_node *block = be_transform_node(get_nodes_block(node));
944 ir_node *op1 = get_Sub_left(node);
945 ir_node *new_op1 = be_transform_node(op1);
946 ir_node *op2 = get_Sub_right(node);
947 ir_node *new_op2 = be_transform_node(op2);
948 ir_node *new_op = NULL;
949 ir_graph *irg = current_ir_graph;
950 dbg_info *dbgi = get_irn_dbg_info(node);
951 ir_mode *mode = get_irn_mode(node);
952 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
953 ir_node *nomem = new_NoMem();
954 ir_node *expr_op, *imm_op;
956 /* Check if immediate optimization is on and */
957 /* if it's an operation with immediate. */
958 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
959 expr_op = get_expr_op(new_op1, new_op2);
961 assert((expr_op || imm_op) && "invalid operands");
963 if (mode_is_float(mode)) {
964 if (USE_SSE2(env_cg))
965 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
967 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
972 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
973 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
975 /* No expr_op means, that we have two const - one symconst and */
976 /* one tarval or another symconst - because this case is not */
977 /* covered by constant folding */
978 /* We need to check for: */
979 /* 1) symconst - const -> becomes a LEA */
980 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
981 /* linker doesn't support two symconsts */
982 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
983 /* this is the 2nd case */
984 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
985 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
986 set_ia32_am_sc_sign(new_op);
987 set_ia32_am_flavour(new_op, ia32_am_B);
989 DBG_OPT_LEA3(op1, op2, node, new_op);
990 } else if (tp1 == ia32_ImmSymConst) {
991 tarval *tv = get_ia32_Immop_tarval(new_op2);
992 long offs = get_tarval_long(tv);
994 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
995 add_irn_dep(new_op, get_irg_frame(irg));
996 DBG_OPT_LEA3(op1, op2, node, new_op);
998 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
999 add_ia32_am_offs_int(new_op, -offs);
1000 set_ia32_am_flavour(new_op, ia32_am_OB);
1001 set_ia32_op_type(new_op, ia32_AddrModeS);
1002 } else if (tp2 == ia32_ImmSymConst) {
1003 tarval *tv = get_ia32_Immop_tarval(new_op1);
1004 long offs = get_tarval_long(tv);
1006 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1007 add_irn_dep(new_op, get_irg_frame(irg));
1008 DBG_OPT_LEA3(op1, op2, node, new_op);
1010 add_ia32_am_offs_int(new_op, offs);
1011 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1012 set_ia32_am_sc_sign(new_op);
1013 set_ia32_am_flavour(new_op, ia32_am_OB);
1014 set_ia32_op_type(new_op, ia32_AddrModeS);
1016 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1017 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1018 tarval *restv = tarval_sub(tv1, tv2);
1020 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1022 new_op = new_rd_ia32_Const(dbgi, irg, block);
1023 set_ia32_Const_tarval(new_op, restv);
1024 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1029 } else if (imm_op) {
1030 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1031 tarval_classification_t class_tv, class_negtv;
1032 tarval *tv = get_ia32_Immop_tarval(imm_op);
1034 /* optimize tarvals */
1035 class_tv = classify_tarval(tv);
1036 class_negtv = classify_tarval(tarval_neg(tv));
1038 if (class_tv == TV_CLASSIFY_ONE) {
1039 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1040 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1043 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1044 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1045 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1046 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1052 /* This is a normal sub */
1053 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1055 /* set AM support */
1056 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1058 fold_immediate(new_op, 2, 3);
1060 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1068 * Generates an ia32 DivMod with additional infrastructure for the
1069 * register allocator if needed.
1071 * @param dividend -no comment- :)
1072 * @param divisor -no comment- :)
1073 * @param dm_flav flavour_Div/Mod/DivMod
1074 * @return The created ia32 DivMod node
1076 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1077 ir_node *divisor, ia32_op_flavour_t dm_flav)
1079 ir_node *block = be_transform_node(get_nodes_block(node));
1080 ir_node *new_dividend = be_transform_node(dividend);
1081 ir_node *new_divisor = be_transform_node(divisor);
1082 ir_graph *irg = current_ir_graph;
1083 dbg_info *dbgi = get_irn_dbg_info(node);
1084 ir_mode *mode = get_irn_mode(node);
1085 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1086 ir_node *res, *proj_div, *proj_mod;
1087 ir_node *sign_extension;
1088 ir_node *mem, *new_mem;
1089 ir_node *projs[pn_DivMod_max];
1092 ia32_collect_Projs(node, projs, pn_DivMod_max);
1094 proj_div = proj_mod = NULL;
1098 mem = get_Div_mem(node);
1099 mode = get_Div_resmode(node);
1100 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1101 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1104 mem = get_Mod_mem(node);
1105 mode = get_Mod_resmode(node);
1106 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1107 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1109 case flavour_DivMod:
1110 mem = get_DivMod_mem(node);
1111 mode = get_DivMod_resmode(node);
1112 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1113 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1114 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1117 panic("invalid divmod flavour!");
1119 new_mem = be_transform_node(mem);
1121 if (mode_is_signed(mode)) {
1122 /* in signed mode, we need to sign extend the dividend */
1123 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1124 add_irn_dep(produceval, get_irg_frame(irg));
1125 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1128 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1129 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1131 add_irn_dep(sign_extension, get_irg_frame(irg));
1134 if (mode_is_signed(mode)) {
1135 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1136 sign_extension, new_divisor, new_mem, dm_flav);
1138 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1139 sign_extension, new_divisor, new_mem, dm_flav);
1142 set_ia32_exc_label(res, has_exc);
1143 set_irn_pinned(res, get_irn_pinned(node));
1144 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1146 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1153 * Wrapper for generate_DivMod. Sets flavour_Mod.
1156 static ir_node *gen_Mod(ir_node *node) {
1157 return generate_DivMod(node, get_Mod_left(node),
1158 get_Mod_right(node), flavour_Mod);
1162 * Wrapper for generate_DivMod. Sets flavour_Div.
1165 static ir_node *gen_Div(ir_node *node) {
1166 return generate_DivMod(node, get_Div_left(node),
1167 get_Div_right(node), flavour_Div);
1171 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1173 static ir_node *gen_DivMod(ir_node *node) {
1174 return generate_DivMod(node, get_DivMod_left(node),
1175 get_DivMod_right(node), flavour_DivMod);
1181 * Creates an ia32 floating Div.
1183 * @return The created ia32 xDiv node
1185 static ir_node *gen_Quot(ir_node *node) {
1186 ir_node *block = be_transform_node(get_nodes_block(node));
1187 ir_node *op1 = get_Quot_left(node);
1188 ir_node *new_op1 = be_transform_node(op1);
1189 ir_node *op2 = get_Quot_right(node);
1190 ir_node *new_op2 = be_transform_node(op2);
1191 ir_graph *irg = current_ir_graph;
1192 dbg_info *dbgi = get_irn_dbg_info(node);
1193 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1194 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1197 if (USE_SSE2(env_cg)) {
1198 ir_mode *mode = get_irn_mode(op1);
1199 if (is_ia32_xConst(new_op2)) {
1200 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1201 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1202 copy_ia32_Immop_attr(new_op, new_op2);
1204 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1205 // Matze: disabled for now, spillslot coalescer fails
1206 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1208 set_ia32_ls_mode(new_op, mode);
1210 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1211 new_op2, nomem, get_fpcw());
1212 // Matze: disabled for now (spillslot coalescer fails)
1213 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1215 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1221 * Creates an ia32 Shl.
1223 * @return The created ia32 Shl node
1225 static ir_node *gen_Shl(ir_node *node) {
1226 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1233 * Creates an ia32 Shr.
1235 * @return The created ia32 Shr node
1237 static ir_node *gen_Shr(ir_node *node) {
1238 return gen_shift_binop(node, get_Shr_left(node),
1239 get_Shr_right(node), new_rd_ia32_Shr);
1245 * Creates an ia32 Sar.
1247 * @return The created ia32 Shrs node
1249 static ir_node *gen_Shrs(ir_node *node) {
1250 ir_node *left = get_Shrs_left(node);
1251 ir_node *right = get_Shrs_right(node);
1252 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1253 tarval *tv = get_Const_tarval(right);
1254 long val = get_tarval_long(tv);
1256 /* this is a sign extension */
1257 ir_graph *irg = current_ir_graph;
1258 dbg_info *dbgi = get_irn_dbg_info(node);
1259 ir_node *block = be_transform_node(get_nodes_block(node));
1261 ir_node *new_op = be_transform_node(op);
1262 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1263 add_irn_dep(pval, get_irg_frame(irg));
1265 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1269 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1275 * Creates an ia32 RotL.
1277 * @param op1 The first operator
1278 * @param op2 The second operator
1279 * @return The created ia32 RotL node
1281 static ir_node *gen_RotL(ir_node *node,
1282 ir_node *op1, ir_node *op2) {
1283 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1289 * Creates an ia32 RotR.
1290 * NOTE: There is no RotR with immediate because this would always be a RotL
1291 * "imm-mode_size_bits" which can be pre-calculated.
1293 * @param op1 The first operator
1294 * @param op2 The second operator
1295 * @return The created ia32 RotR node
1297 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1299 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1305 * Creates an ia32 RotR or RotL (depending on the found pattern).
1307 * @return The created ia32 RotL or RotR node
1309 static ir_node *gen_Rot(ir_node *node) {
1310 ir_node *rotate = NULL;
1311 ir_node *op1 = get_Rot_left(node);
1312 ir_node *op2 = get_Rot_right(node);
1314 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1315 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1316 that means we can create a RotR instead of an Add and a RotL */
1318 if (get_irn_op(op2) == op_Add) {
1320 ir_node *left = get_Add_left(add);
1321 ir_node *right = get_Add_right(add);
1322 if (is_Const(right)) {
1323 tarval *tv = get_Const_tarval(right);
1324 ir_mode *mode = get_irn_mode(node);
1325 long bits = get_mode_size_bits(mode);
1327 if (get_irn_op(left) == op_Minus &&
1328 tarval_is_long(tv) &&
1329 get_tarval_long(tv) == bits)
1331 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1332 rotate = gen_RotR(node, op1, get_Minus_op(left));
1337 if (rotate == NULL) {
1338 rotate = gen_RotL(node, op1, op2);
1347 * Transforms a Minus node.
1349 * @param op The Minus operand
1350 * @return The created ia32 Minus node
1352 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1353 ir_node *block = be_transform_node(get_nodes_block(node));
1354 ir_graph *irg = current_ir_graph;
1355 dbg_info *dbgi = get_irn_dbg_info(node);
1356 ir_mode *mode = get_irn_mode(node);
1361 if (mode_is_float(mode)) {
1362 ir_node *new_op = be_transform_node(op);
1363 if (USE_SSE2(env_cg)) {
1364 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1365 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1366 ir_node *nomem = new_rd_NoMem(irg);
1368 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1370 size = get_mode_size_bits(mode);
1371 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1373 set_ia32_am_sc(res, ent);
1374 set_ia32_op_type(res, ia32_AddrModeS);
1375 set_ia32_ls_mode(res, mode);
1377 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1380 res = gen_unop(node, op, new_rd_ia32_Neg);
1383 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1389 * Transforms a Minus node.
1391 * @return The created ia32 Minus node
1393 static ir_node *gen_Minus(ir_node *node) {
1394 return gen_Minus_ex(node, get_Minus_op(node));
1397 static ir_node *gen_bin_Not(ir_node *node)
1399 ir_graph *irg = current_ir_graph;
1400 dbg_info *dbgi = get_irn_dbg_info(node);
1401 ir_node *block = be_transform_node(get_nodes_block(node));
1402 ir_node *op = get_Not_op(node);
1403 ir_node *new_op = be_transform_node(op);
1404 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1405 ir_node *nomem = new_NoMem();
1406 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1407 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1409 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1413 * Transforms a Not node.
1415 * @return The created ia32 Not node
1417 static ir_node *gen_Not(ir_node *node) {
1418 ir_node *op = get_Not_op(node);
1419 ir_mode *mode = get_irn_mode(node);
1421 if(mode == mode_b) {
1422 return gen_bin_Not(node);
1425 assert (! mode_is_float(get_irn_mode(node)));
1426 return gen_unop(node, op, new_rd_ia32_Not);
1432 * Transforms an Abs node.
1434 * @return The created ia32 Abs node
1436 static ir_node *gen_Abs(ir_node *node) {
1437 ir_node *block = be_transform_node(get_nodes_block(node));
1438 ir_node *op = get_Abs_op(node);
1439 ir_node *new_op = be_transform_node(op);
1440 ir_graph *irg = current_ir_graph;
1441 dbg_info *dbgi = get_irn_dbg_info(node);
1442 ir_mode *mode = get_irn_mode(node);
1443 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1444 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1445 ir_node *nomem = new_NoMem();
1450 if (mode_is_float(mode)) {
1451 if (USE_SSE2(env_cg)) {
1452 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1454 size = get_mode_size_bits(mode);
1455 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1457 set_ia32_am_sc(res, ent);
1459 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1461 set_ia32_op_type(res, ia32_AddrModeS);
1462 set_ia32_ls_mode(res, mode);
1465 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1466 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1470 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1471 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1474 add_irn_dep(pval, get_irg_frame(irg));
1475 SET_IA32_ORIG_NODE(sign_extension,
1476 ia32_get_old_node_name(env_cg, node));
1478 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1479 sign_extension, nomem);
1480 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1482 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1483 sign_extension, nomem);
1484 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1493 * Transforms a Load.
1495 * @return the created ia32 Load node
1497 static ir_node *gen_Load(ir_node *node) {
1498 ir_node *old_block = get_nodes_block(node);
1499 ir_node *block = be_transform_node(old_block);
1500 ir_node *ptr = get_Load_ptr(node);
1501 ir_node *new_ptr = be_transform_node(ptr);
1502 ir_node *mem = get_Load_mem(node);
1503 ir_node *new_mem = be_transform_node(mem);
1504 ir_graph *irg = current_ir_graph;
1505 dbg_info *dbgi = get_irn_dbg_info(node);
1506 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1507 ir_mode *mode = get_Load_mode(node);
1509 ir_node *lptr = new_ptr;
1512 ia32_am_flavour_t am_flav = ia32_am_B;
1514 /* address might be a constant (symconst or absolute address) */
1515 if (is_ia32_Const(new_ptr)) {
1520 if (mode_is_float(mode)) {
1521 if (USE_SSE2(env_cg)) {
1522 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1523 res_mode = mode_xmm;
1525 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1526 res_mode = mode_vfp;
1532 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1536 /* base is a constant address */
1538 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1539 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1540 am_flav = ia32_am_N;
1542 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1543 long offs = get_tarval_long(tv);
1545 add_ia32_am_offs_int(new_op, offs);
1546 am_flav = ia32_am_O;
1550 set_irn_pinned(new_op, get_irn_pinned(node));
1551 set_ia32_op_type(new_op, ia32_AddrModeS);
1552 set_ia32_am_flavour(new_op, am_flav);
1553 set_ia32_ls_mode(new_op, mode);
1555 /* make sure we are scheduled behind the initial IncSP/Barrier
1556 * to avoid spills being placed before it
1558 if (block == get_irg_start_block(irg)) {
1559 add_irn_dep(new_op, get_irg_frame(irg));
1562 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1563 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1571 * Transforms a Store.
1573 * @return the created ia32 Store node
1575 static ir_node *gen_Store(ir_node *node) {
1576 ir_node *block = be_transform_node(get_nodes_block(node));
1577 ir_node *ptr = get_Store_ptr(node);
1578 ir_node *new_ptr = be_transform_node(ptr);
1579 ir_node *val = get_Store_value(node);
1581 ir_node *mem = get_Store_mem(node);
1582 ir_node *new_mem = be_transform_node(mem);
1583 ir_graph *irg = current_ir_graph;
1584 dbg_info *dbgi = get_irn_dbg_info(node);
1585 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1586 ir_node *sptr = new_ptr;
1587 ir_mode *mode = get_irn_mode(val);
1590 ia32_am_flavour_t am_flav = ia32_am_B;
1592 /* address might be a constant (symconst or absolute address) */
1593 if (is_ia32_Const(new_ptr)) {
1598 if (mode_is_float(mode)) {
1599 new_val = be_transform_node(val);
1600 if (USE_SSE2(env_cg)) {
1601 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1604 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1608 new_val = create_immediate_or_transform(val, 0);
1612 if (get_mode_size_bits(mode) == 8) {
1613 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1616 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1621 /* base is an constant address */
1623 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1624 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1625 am_flav = ia32_am_N;
1627 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1628 long offs = get_tarval_long(tv);
1630 add_ia32_am_offs_int(new_op, offs);
1631 am_flav = ia32_am_O;
1635 set_irn_pinned(new_op, get_irn_pinned(node));
1636 set_ia32_op_type(new_op, ia32_AddrModeD);
1637 set_ia32_am_flavour(new_op, am_flav);
1638 set_ia32_ls_mode(new_op, mode);
1640 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1641 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1646 static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
1651 if(get_mode_size_bits(mode) == 32)
1655 if(is_ia32_Immediate(new_op))
1658 if(mode_is_signed(mode))
1663 block = get_nodes_block(new_op);
1664 return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
1667 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1668 ir_node *cmp_left, ir_node *cmp_right)
1670 ir_node *new_cmp_left;
1671 ir_node *new_cmp_right;
1678 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1680 if(cmp_right != NULL && !is_Const_0(cmp_right))
1683 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1684 and_left = get_And_left(cmp_left);
1685 and_right = get_And_right(cmp_left);
1687 mode = get_irn_mode(and_left);
1688 new_cmp_left = be_transform_node(and_left);
1689 new_cmp_right = create_immediate_or_transform(and_right, 0);
1691 mode = get_irn_mode(cmp_left);
1692 new_cmp_left = be_transform_node(cmp_left);
1693 new_cmp_right = be_transform_node(cmp_left);
1696 assert(get_mode_size_bits(mode) <= 32);
1697 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1698 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1699 noreg = ia32_new_NoReg_gp(env_cg);
1700 nomem = new_NoMem();
1702 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1703 new_cmp_left, new_cmp_right, nomem, pnc);
1704 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1709 static ir_node *create_Switch(ir_node *node)
1711 ir_graph *irg = current_ir_graph;
1712 dbg_info *dbgi = get_irn_dbg_info(node);
1713 ir_node *block = be_transform_node(get_nodes_block(node));
1714 ir_node *sel = get_Cond_selector(node);
1715 ir_node *new_sel = be_transform_node(sel);
1717 int switch_min = INT_MAX;
1718 const ir_edge_t *edge;
1720 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1722 /* determine the smallest switch case value */
1723 foreach_out_edge(node, edge) {
1724 ir_node *proj = get_edge_src_irn(edge);
1725 int pn = get_Proj_proj(proj);
1730 if (switch_min != 0) {
1731 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1733 /* if smallest switch case is not 0 we need an additional sub */
1734 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1735 add_ia32_am_offs_int(new_sel, -switch_min);
1736 set_ia32_am_flavour(new_sel, ia32_am_OB);
1737 set_ia32_op_type(new_sel, ia32_AddrModeS);
1739 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1742 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1743 set_ia32_pncode(res, get_Cond_defaultProj(node));
1745 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1751 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1753 * @return The transformed node.
1755 static ir_node *gen_Cond(ir_node *node) {
1756 ir_node *block = be_transform_node(get_nodes_block(node));
1757 ir_graph *irg = current_ir_graph;
1758 dbg_info *dbgi = get_irn_dbg_info(node);
1759 ir_node *sel = get_Cond_selector(node);
1760 ir_mode *sel_mode = get_irn_mode(sel);
1761 ir_node *res = NULL;
1762 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1769 ir_node *nomem = new_NoMem();
1772 if (sel_mode != mode_b) {
1773 return create_Switch(node);
1776 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1777 /* it's some mode_b value but not a direct comparison -> create a
1779 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1780 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1784 cmp = get_Proj_pred(sel);
1785 cmp_a = get_Cmp_left(cmp);
1786 cmp_b = get_Cmp_right(cmp);
1787 cmp_mode = get_irn_mode(cmp_a);
1788 pnc = get_Proj_proj(sel);
1789 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1790 pnc |= ia32_pn_Cmp_Unsigned;
1793 if(mode_needs_gp_reg(cmp_mode)) {
1794 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1796 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1801 new_cmp_a = be_transform_node(cmp_a);
1802 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1804 if (mode_is_float(cmp_mode)) {
1805 if (USE_SSE2(env_cg)) {
1806 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1808 set_ia32_commutative(res);
1809 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1810 set_ia32_ls_mode(res, cmp_mode);
1812 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1813 set_ia32_commutative(res);
1816 /** workaround smaller compare modes with converts...
1817 * We could easily support 16bit compares, for 8 bit we have to set
1818 * additional register constraints, which we don't do yet
1820 new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
1821 new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
1823 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1824 new_cmp_a, new_cmp_b, nomem, pnc);
1825 set_ia32_commutative(res);
1826 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1829 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1837 * Transforms a CopyB node.
1839 * @return The transformed node.
1841 static ir_node *gen_CopyB(ir_node *node) {
1842 ir_node *block = be_transform_node(get_nodes_block(node));
1843 ir_node *src = get_CopyB_src(node);
1844 ir_node *new_src = be_transform_node(src);
1845 ir_node *dst = get_CopyB_dst(node);
1846 ir_node *new_dst = be_transform_node(dst);
1847 ir_node *mem = get_CopyB_mem(node);
1848 ir_node *new_mem = be_transform_node(mem);
1849 ir_node *res = NULL;
1850 ir_graph *irg = current_ir_graph;
1851 dbg_info *dbgi = get_irn_dbg_info(node);
1852 int size = get_type_size_bytes(get_CopyB_type(node));
1855 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1856 /* then we need the size explicitly in ECX. */
1857 if (size >= 32 * 4) {
1858 rem = size & 0x3; /* size % 4 */
1861 res = new_rd_ia32_Const(dbgi, irg, block);
1862 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1863 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1865 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1866 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1868 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1869 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1872 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1878 ir_node *gen_be_Copy(ir_node *node)
1880 ir_node *result = be_duplicate_node(node);
1881 ir_mode *mode = get_irn_mode(result);
1883 if (mode_needs_gp_reg(mode)) {
1884 set_irn_mode(result, mode_Iu);
1891 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1892 dbg_info *dbgi, ir_node *block)
1894 ir_graph *irg = current_ir_graph;
1895 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1896 ir_node *nomem = new_rd_NoMem(irg);
1898 ir_node *new_cmp_left;
1899 ir_node *new_cmp_right;
1902 /* can we use a test instruction? */
1903 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1904 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1905 if(is_And(cmp_left) &&
1906 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1907 ir_node *and_left = get_And_left(cmp_left);
1908 ir_node *and_right = get_And_right(cmp_left);
1910 mode = get_irn_mode(and_left);
1911 new_cmp_left = be_transform_node(and_left);
1912 new_cmp_right = create_immediate_or_transform(and_right, 0);
1914 mode = get_irn_mode(cmp_left);
1915 new_cmp_left = be_transform_node(cmp_left);
1916 new_cmp_right = be_transform_node(cmp_left);
1919 assert(get_mode_size_bits(mode) <= 32);
1920 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1921 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1923 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1924 new_cmp_left, new_cmp_right, nomem, pnc);
1925 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1930 mode = get_irn_mode(cmp_left);
1932 new_cmp_left = be_transform_node(cmp_left);
1933 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1935 assert(get_mode_size_bits(mode) <= 32);
1936 new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
1937 new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
1939 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1940 new_cmp_left, new_cmp_right, nomem, pnc);
1945 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1946 ir_node *val_true, ir_node *val_false,
1947 dbg_info *dbgi, ir_node *block)
1949 ir_graph *irg = current_ir_graph;
1950 ir_node *new_val_true = be_transform_node(val_true);
1951 ir_node *new_val_false = be_transform_node(val_false);
1952 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1953 ir_node *nomem = new_NoMem();
1954 ir_node *new_cmp_left;
1955 ir_node *new_cmp_right;
1958 /* cmovs with unknowns are pointless... */
1959 if(is_Unknown(val_true)) {
1960 #ifdef DEBUG_libfirm
1961 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1963 return new_val_false;
1965 if(is_Unknown(val_false)) {
1966 #ifdef DEBUG_libfirm
1967 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1969 return new_val_true;
1972 /* can we use a test instruction? */
1973 if(is_Const_0(cmp_right)) {
1974 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1975 if(is_And(cmp_left) &&
1976 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1977 ir_node *and_left = get_And_left(cmp_left);
1978 ir_node *and_right = get_And_right(cmp_left);
1980 new_cmp_left = be_transform_node(and_left);
1981 new_cmp_right = create_immediate_or_transform(and_right, 0);
1983 new_cmp_left = be_transform_node(cmp_left);
1984 new_cmp_right = be_transform_node(cmp_left);
1987 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1988 new_cmp_left, new_cmp_right, nomem,
1989 new_val_true, new_val_false, pnc);
1990 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1995 new_cmp_left = be_transform_node(cmp_left);
1996 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1998 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1999 new_cmp_right, nomem, new_val_true, new_val_false,
2001 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
2008 * Transforms a Psi node into CMov.
2010 * @return The transformed node.
2012 static ir_node *gen_Psi(ir_node *node) {
2013 ir_node *psi_true = get_Psi_val(node, 0);
2014 ir_node *psi_default = get_Psi_default(node);
2015 ia32_code_gen_t *cg = env_cg;
2016 ir_node *cond = get_Psi_cond(node, 0);
2017 ir_node *block = be_transform_node(get_nodes_block(node));
2018 dbg_info *dbgi = get_irn_dbg_info(node);
2025 assert(get_Psi_n_conds(node) == 1);
2026 assert(get_irn_mode(cond) == mode_b);
2028 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2029 /* a mode_b value, we have to compare it against 0 */
2031 cmp_right = new_Const_long(mode_Iu, 0);
2035 ir_node *cmp = get_Proj_pred(cond);
2037 cmp_left = get_Cmp_left(cmp);
2038 cmp_right = get_Cmp_right(cmp);
2039 cmp_mode = get_irn_mode(cmp_left);
2040 pnc = get_Proj_proj(cond);
2042 assert(!mode_is_float(cmp_mode));
2044 if (!mode_is_signed(cmp_mode)) {
2045 pnc |= ia32_pn_Cmp_Unsigned;
2049 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2050 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2051 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2052 pnc = get_negated_pnc(pnc, cmp_mode);
2053 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2055 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2058 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2064 * Following conversion rules apply:
2068 * 1) n bit -> m bit n > m (downscale)
2070 * 2) n bit -> m bit n == m (sign change)
2072 * 3) n bit -> m bit n < m (upscale)
2073 * a) source is signed: movsx
2074 * b) source is unsigned: and with lower bits sets
2078 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2082 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2086 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2087 * x87 is mode_E internally, conversions happen only at load and store
2088 * in non-strict semantic
2092 * Create a conversion from x87 state register to general purpose.
2094 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2095 ir_node *block = be_transform_node(get_nodes_block(node));
2096 ir_node *op = get_Conv_op(node);
2097 ir_node *new_op = be_transform_node(op);
2098 ia32_code_gen_t *cg = env_cg;
2099 ir_graph *irg = current_ir_graph;
2100 dbg_info *dbgi = get_irn_dbg_info(node);
2101 ir_node *noreg = ia32_new_NoReg_gp(cg);
2102 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2103 ir_node *fist, *load;
2106 fist = new_rd_ia32_vfist(dbgi, irg, block,
2107 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2109 set_irn_pinned(fist, op_pin_state_floats);
2110 set_ia32_use_frame(fist);
2111 set_ia32_op_type(fist, ia32_AddrModeD);
2112 set_ia32_am_flavour(fist, ia32_am_B);
2113 set_ia32_ls_mode(fist, mode_Iu);
2114 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2117 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2119 set_irn_pinned(load, op_pin_state_floats);
2120 set_ia32_use_frame(load);
2121 set_ia32_op_type(load, ia32_AddrModeS);
2122 set_ia32_am_flavour(load, ia32_am_B);
2123 set_ia32_ls_mode(load, mode_Iu);
2124 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2126 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2129 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2131 ir_node *block = get_nodes_block(node);
2132 ir_graph *irg = current_ir_graph;
2133 dbg_info *dbgi = get_irn_dbg_info(node);
2134 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2135 ir_node *nomem = new_NoMem();
2136 ir_node *frame = get_irg_frame(irg);
2137 ir_node *store, *load;
2140 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2142 set_ia32_use_frame(store);
2143 set_ia32_op_type(store, ia32_AddrModeD);
2144 set_ia32_am_flavour(store, ia32_am_OB);
2145 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2147 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2149 set_ia32_use_frame(load);
2150 set_ia32_op_type(load, ia32_AddrModeS);
2151 set_ia32_am_flavour(load, ia32_am_OB);
2152 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2154 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2159 * Create a conversion from general purpose to x87 register
2161 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2162 ir_node *block = be_transform_node(get_nodes_block(node));
2163 ir_node *op = get_Conv_op(node);
2164 ir_node *new_op = be_transform_node(op);
2165 ir_graph *irg = current_ir_graph;
2166 dbg_info *dbgi = get_irn_dbg_info(node);
2167 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2168 ir_node *nomem = new_NoMem();
2169 ir_node *fild, *store;
2173 /* first convert to 32 bit if necessary */
2174 src_bits = get_mode_size_bits(src_mode);
2175 if (src_bits == 8) {
2176 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2177 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2178 set_ia32_ls_mode(new_op, src_mode);
2179 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2180 } else if (src_bits < 32) {
2181 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2182 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2183 set_ia32_ls_mode(new_op, src_mode);
2184 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2188 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2190 set_ia32_use_frame(store);
2191 set_ia32_op_type(store, ia32_AddrModeD);
2192 set_ia32_am_flavour(store, ia32_am_OB);
2193 set_ia32_ls_mode(store, mode_Iu);
2196 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2198 set_ia32_use_frame(fild);
2199 set_ia32_op_type(fild, ia32_AddrModeS);
2200 set_ia32_am_flavour(fild, ia32_am_OB);
2201 set_ia32_ls_mode(fild, mode_Iu);
2203 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2208 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2209 dbg_info *dbgi, ir_node *new_block,
2212 ir_graph *irg = current_ir_graph;
2213 int src_bits = get_mode_size_bits(src_mode);
2214 int tgt_bits = get_mode_size_bits(tgt_mode);
2215 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2216 ir_node *nomem = new_rd_NoMem(irg);
2218 ir_mode *smaller_mode;
2221 if (src_bits < tgt_bits) {
2222 smaller_mode = src_mode;
2223 smaller_bits = src_bits;
2225 smaller_mode = tgt_mode;
2226 smaller_bits = tgt_bits;
2229 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2230 if (smaller_bits == 8) {
2231 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2233 set_ia32_ls_mode(res, smaller_mode);
2235 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2237 set_ia32_ls_mode(res, smaller_mode);
2239 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2245 * Transforms a Conv node.
2247 * @return The created ia32 Conv node
2249 static ir_node *gen_Conv(ir_node *node) {
2250 ir_node *block = be_transform_node(get_nodes_block(node));
2251 ir_node *op = get_Conv_op(node);
2252 ir_node *new_op = be_transform_node(op);
2253 ir_graph *irg = current_ir_graph;
2254 dbg_info *dbgi = get_irn_dbg_info(node);
2255 ir_mode *src_mode = get_irn_mode(op);
2256 ir_mode *tgt_mode = get_irn_mode(node);
2257 int src_bits = get_mode_size_bits(src_mode);
2258 int tgt_bits = get_mode_size_bits(tgt_mode);
2259 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2260 ir_node *nomem = new_rd_NoMem(irg);
2263 if (src_mode == mode_b) {
2264 assert(mode_is_int(tgt_mode));
2265 /* nothing to do, we already model bools as 0/1 ints */
2269 if (src_mode == tgt_mode) {
2270 if (get_Conv_strict(node)) {
2271 if (USE_SSE2(env_cg)) {
2272 /* when we are in SSE mode, we can kill all strict no-op conversion */
2276 /* this should be optimized already, but who knows... */
2277 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2278 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2283 if (mode_is_float(src_mode)) {
2284 /* we convert from float ... */
2285 if (mode_is_float(tgt_mode)) {
2286 if(src_mode == mode_E && tgt_mode == mode_D
2287 && !get_Conv_strict(node)) {
2288 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2293 if (USE_SSE2(env_cg)) {
2294 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2295 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2296 set_ia32_ls_mode(res, tgt_mode);
2298 if(get_Conv_strict(node)) {
2299 res = create_strict_conv(tgt_mode, new_op);
2300 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2303 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2308 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2309 if (USE_SSE2(env_cg)) {
2310 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2311 set_ia32_ls_mode(res, src_mode);
2313 return gen_x87_fp_to_gp(node);
2317 /* we convert from int ... */
2318 if (mode_is_float(tgt_mode)) {
2320 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2321 if (USE_SSE2(env_cg)) {
2322 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2323 set_ia32_ls_mode(res, tgt_mode);
2324 if(src_bits == 32) {
2325 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2328 res = gen_x87_gp_to_fp(node, src_mode);
2329 if(get_Conv_strict(node)) {
2330 res = create_strict_conv(tgt_mode, res);
2331 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2332 ia32_get_old_node_name(env_cg, node));
2336 } else if(tgt_mode == mode_b) {
2337 /* mode_b lowering already took care that we only have 0/1 values */
2338 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2339 src_mode, tgt_mode));
2343 if (src_bits == tgt_bits) {
2344 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2345 src_mode, tgt_mode));
2349 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2353 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2359 int check_immediate_constraint(long val, char immediate_constraint_type)
2361 switch (immediate_constraint_type) {
2365 return val >= 0 && val <= 32;
2367 return val >= 0 && val <= 63;
2369 return val >= -128 && val <= 127;
2371 return val == 0xff || val == 0xffff;
2373 return val >= 0 && val <= 3;
2375 return val >= 0 && val <= 255;
2377 return val >= 0 && val <= 127;
2381 panic("Invalid immediate constraint found");
2386 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2389 tarval *offset = NULL;
2390 int offset_sign = 0;
2392 ir_entity *symconst_ent = NULL;
2393 int symconst_sign = 0;
2395 ir_node *cnst = NULL;
2396 ir_node *symconst = NULL;
2402 mode = get_irn_mode(node);
2403 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2407 if(is_Minus(node)) {
2409 node = get_Minus_op(node);
2412 if(is_Const(node)) {
2415 offset_sign = minus;
2416 } else if(is_SymConst(node)) {
2419 symconst_sign = minus;
2420 } else if(is_Add(node)) {
2421 ir_node *left = get_Add_left(node);
2422 ir_node *right = get_Add_right(node);
2423 if(is_Const(left) && is_SymConst(right)) {
2426 symconst_sign = minus;
2427 offset_sign = minus;
2428 } else if(is_SymConst(left) && is_Const(right)) {
2431 symconst_sign = minus;
2432 offset_sign = minus;
2434 } else if(is_Sub(node)) {
2435 ir_node *left = get_Sub_left(node);
2436 ir_node *right = get_Sub_right(node);
2437 if(is_Const(left) && is_SymConst(right)) {
2440 symconst_sign = !minus;
2441 offset_sign = minus;
2442 } else if(is_SymConst(left) && is_Const(right)) {
2445 symconst_sign = minus;
2446 offset_sign = !minus;
2453 offset = get_Const_tarval(cnst);
2454 if(tarval_is_long(offset)) {
2455 val = get_tarval_long(offset);
2456 } else if(tarval_is_null(offset)) {
2459 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2464 if(!check_immediate_constraint(val, immediate_constraint_type))
2467 if(symconst != NULL) {
2468 if(immediate_constraint_type != 0) {
2469 /* we need full 32bits for symconsts */
2473 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2475 symconst_ent = get_SymConst_entity(symconst);
2477 if(cnst == NULL && symconst == NULL)
2480 if(offset_sign && offset != NULL) {
2481 offset = tarval_neg(offset);
2484 irg = current_ir_graph;
2485 dbgi = get_irn_dbg_info(node);
2486 block = get_irg_start_block(irg);
2487 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2488 symconst_sign, val);
2489 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2495 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2497 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2498 if (new_node == NULL) {
2499 new_node = be_transform_node(node);
2504 typedef struct constraint_t constraint_t;
2505 struct constraint_t {
2508 const arch_register_req_t **out_reqs;
2510 const arch_register_req_t *req;
2511 unsigned immediate_possible;
2512 char immediate_type;
2515 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2517 int immediate_possible = 0;
2518 char immediate_type = 0;
2519 unsigned limited = 0;
2520 const arch_register_class_t *cls = NULL;
2522 struct obstack *obst;
2523 arch_register_req_t *req;
2524 unsigned *limited_ptr;
2528 /* TODO: replace all the asserts with nice error messages */
2530 printf("Constraint: %s\n", c);
2540 assert(cls == NULL ||
2541 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2542 cls = &ia32_reg_classes[CLASS_ia32_gp];
2543 limited |= 1 << REG_EAX;
2546 assert(cls == NULL ||
2547 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2548 cls = &ia32_reg_classes[CLASS_ia32_gp];
2549 limited |= 1 << REG_EBX;
2552 assert(cls == NULL ||
2553 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2554 cls = &ia32_reg_classes[CLASS_ia32_gp];
2555 limited |= 1 << REG_ECX;
2558 assert(cls == NULL ||
2559 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2560 cls = &ia32_reg_classes[CLASS_ia32_gp];
2561 limited |= 1 << REG_EDX;
2564 assert(cls == NULL ||
2565 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2566 cls = &ia32_reg_classes[CLASS_ia32_gp];
2567 limited |= 1 << REG_EDI;
2570 assert(cls == NULL ||
2571 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2572 cls = &ia32_reg_classes[CLASS_ia32_gp];
2573 limited |= 1 << REG_ESI;
2576 case 'q': /* q means lower part of the regs only, this makes no
2577 * difference to Q for us (we only assigne whole registers) */
2578 assert(cls == NULL ||
2579 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2580 cls = &ia32_reg_classes[CLASS_ia32_gp];
2581 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2585 assert(cls == NULL ||
2586 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2587 cls = &ia32_reg_classes[CLASS_ia32_gp];
2588 limited |= 1 << REG_EAX | 1 << REG_EDX;
2591 assert(cls == NULL ||
2592 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2593 cls = &ia32_reg_classes[CLASS_ia32_gp];
2594 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2595 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2602 assert(cls == NULL);
2603 cls = &ia32_reg_classes[CLASS_ia32_gp];
2609 /* TODO: mark values so the x87 simulator knows about t and u */
2610 assert(cls == NULL);
2611 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2616 assert(cls == NULL);
2617 /* TODO: check that sse2 is supported */
2618 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2628 assert(!immediate_possible);
2629 immediate_possible = 1;
2630 immediate_type = *c;
2634 assert(!immediate_possible);
2635 immediate_possible = 1;
2639 assert(!immediate_possible && cls == NULL);
2640 immediate_possible = 1;
2641 cls = &ia32_reg_classes[CLASS_ia32_gp];
2654 assert(constraint->is_in && "can only specify same constraint "
2657 sscanf(c, "%d%n", &same_as, &p);
2664 case 'E': /* no float consts yet */
2665 case 'F': /* no float consts yet */
2666 case 's': /* makes no sense on x86 */
2667 case 'X': /* we can't support that in firm */
2671 case '<': /* no autodecrement on x86 */
2672 case '>': /* no autoincrement on x86 */
2673 case 'C': /* sse constant not supported yet */
2674 case 'G': /* 80387 constant not supported yet */
2675 case 'y': /* we don't support mmx registers yet */
2676 case 'Z': /* not available in 32 bit mode */
2677 case 'e': /* not available in 32 bit mode */
2678 assert(0 && "asm constraint not supported");
2681 assert(0 && "unknown asm constraint found");
2688 const arch_register_req_t *other_constr;
2690 assert(cls == NULL && "same as and register constraint not supported");
2691 assert(!immediate_possible && "same as and immediate constraint not "
2693 assert(same_as < constraint->n_outs && "wrong constraint number in "
2694 "same_as constraint");
2696 other_constr = constraint->out_reqs[same_as];
2698 req = obstack_alloc(obst, sizeof(req[0]));
2699 req->cls = other_constr->cls;
2700 req->type = arch_register_req_type_should_be_same;
2701 req->limited = NULL;
2702 req->other_same = pos;
2703 req->other_different = -1;
2705 /* switch constraints. This is because in firm we have same_as
2706 * constraints on the output constraints while in the gcc asm syntax
2707 * they are specified on the input constraints */
2708 constraint->req = other_constr;
2709 constraint->out_reqs[same_as] = req;
2710 constraint->immediate_possible = 0;
2714 if(immediate_possible && cls == NULL) {
2715 cls = &ia32_reg_classes[CLASS_ia32_gp];
2717 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2718 assert(cls != NULL);
2720 if(immediate_possible) {
2721 assert(constraint->is_in
2722 && "imeediates make no sense for output constraints");
2724 /* todo: check types (no float input on 'r' constrainted in and such... */
2726 irg = current_ir_graph;
2727 obst = get_irg_obstack(irg);
2730 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2731 limited_ptr = (unsigned*) (req+1);
2733 req = obstack_alloc(obst, sizeof(req[0]));
2735 memset(req, 0, sizeof(req[0]));
2738 req->type = arch_register_req_type_limited;
2739 *limited_ptr = limited;
2740 req->limited = limited_ptr;
2742 req->type = arch_register_req_type_normal;
2746 constraint->req = req;
2747 constraint->immediate_possible = immediate_possible;
2748 constraint->immediate_type = immediate_type;
2752 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2759 panic("Clobbers not supported yet");
2762 ir_node *gen_ASM(ir_node *node)
2765 ir_graph *irg = current_ir_graph;
2766 ir_node *block = be_transform_node(get_nodes_block(node));
2767 dbg_info *dbgi = get_irn_dbg_info(node);
2774 ia32_asm_attr_t *attr;
2775 const arch_register_req_t **out_reqs;
2776 const arch_register_req_t **in_reqs;
2777 struct obstack *obst;
2778 constraint_t parsed_constraint;
2780 /* transform inputs */
2781 arity = get_irn_arity(node);
2782 in = alloca(arity * sizeof(in[0]));
2783 memset(in, 0, arity * sizeof(in[0]));
2785 n_outs = get_ASM_n_output_constraints(node);
2786 n_clobbers = get_ASM_n_clobbers(node);
2787 out_arity = n_outs + n_clobbers;
2789 /* construct register constraints */
2790 obst = get_irg_obstack(irg);
2791 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2792 parsed_constraint.out_reqs = out_reqs;
2793 parsed_constraint.n_outs = n_outs;
2794 parsed_constraint.is_in = 0;
2795 for(i = 0; i < out_arity; ++i) {
2799 const ir_asm_constraint *constraint;
2800 constraint = & get_ASM_output_constraints(node) [i];
2801 c = get_id_str(constraint->constraint);
2802 parse_asm_constraint(i, &parsed_constraint, c);
2804 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2805 c = get_id_str(glob_id);
2806 parse_clobber(node, i, &parsed_constraint, c);
2808 out_reqs[i] = parsed_constraint.req;
2811 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2812 parsed_constraint.is_in = 1;
2813 for(i = 0; i < arity; ++i) {
2814 const ir_asm_constraint *constraint;
2818 constraint = & get_ASM_input_constraints(node) [i];
2819 constr_id = constraint->constraint;
2820 c = get_id_str(constr_id);
2821 parse_asm_constraint(i, &parsed_constraint, c);
2822 in_reqs[i] = parsed_constraint.req;
2824 if(parsed_constraint.immediate_possible) {
2825 ir_node *pred = get_irn_n(node, i);
2826 char imm_type = parsed_constraint.immediate_type;
2827 ir_node *immediate = try_create_Immediate(pred, imm_type);
2829 if(immediate != NULL) {
2835 /* transform inputs */
2836 for(i = 0; i < arity; ++i) {
2838 ir_node *transformed;
2843 pred = get_irn_n(node, i);
2844 transformed = be_transform_node(pred);
2845 in[i] = transformed;
2848 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2850 generic_attr = get_irn_generic_attr(res);
2851 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2852 attr->asm_text = get_ASM_text(node);
2853 set_ia32_out_req_all(res, out_reqs);
2854 set_ia32_in_req_all(res, in_reqs);
2856 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2861 /********************************************
2864 * | |__ ___ _ __ ___ __| | ___ ___
2865 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2866 * | |_) | __/ | | | (_) | (_| | __/\__ \
2867 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2869 ********************************************/
2871 static ir_node *gen_be_StackParam(ir_node *node) {
2872 ir_node *block = be_transform_node(get_nodes_block(node));
2873 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2874 ir_node *new_ptr = be_transform_node(ptr);
2875 ir_node *new_op = NULL;
2876 ir_graph *irg = current_ir_graph;
2877 dbg_info *dbgi = get_irn_dbg_info(node);
2878 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2879 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2880 ir_mode *load_mode = get_irn_mode(node);
2881 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2885 if (mode_is_float(load_mode)) {
2886 if (USE_SSE2(env_cg)) {
2887 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2888 pn_res = pn_ia32_xLoad_res;
2889 proj_mode = mode_xmm;
2891 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2892 pn_res = pn_ia32_vfld_res;
2893 proj_mode = mode_vfp;
2896 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2897 proj_mode = mode_Iu;
2898 pn_res = pn_ia32_Load_res;
2901 set_irn_pinned(new_op, op_pin_state_floats);
2902 set_ia32_frame_ent(new_op, ent);
2903 set_ia32_use_frame(new_op);
2905 set_ia32_op_type(new_op, ia32_AddrModeS);
2906 set_ia32_am_flavour(new_op, ia32_am_B);
2907 set_ia32_ls_mode(new_op, load_mode);
2908 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2910 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2912 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2916 * Transforms a FrameAddr into an ia32 Add.
2918 static ir_node *gen_be_FrameAddr(ir_node *node) {
2919 ir_node *block = be_transform_node(get_nodes_block(node));
2920 ir_node *op = be_get_FrameAddr_frame(node);
2921 ir_node *new_op = be_transform_node(op);
2922 ir_graph *irg = current_ir_graph;
2923 dbg_info *dbgi = get_irn_dbg_info(node);
2924 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2927 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2928 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2929 set_ia32_use_frame(res);
2930 set_ia32_am_flavour(res, ia32_am_OB);
2932 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2938 * Transforms a FrameLoad into an ia32 Load.
2940 static ir_node *gen_be_FrameLoad(ir_node *node) {
2941 ir_node *block = be_transform_node(get_nodes_block(node));
2942 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2943 ir_node *new_mem = be_transform_node(mem);
2944 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2945 ir_node *new_ptr = be_transform_node(ptr);
2946 ir_node *new_op = NULL;
2947 ir_graph *irg = current_ir_graph;
2948 dbg_info *dbgi = get_irn_dbg_info(node);
2949 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2950 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2951 ir_mode *mode = get_type_mode(get_entity_type(ent));
2952 ir_node *projs[pn_Load_max];
2954 ia32_collect_Projs(node, projs, pn_Load_max);
2956 if (mode_is_float(mode)) {
2957 if (USE_SSE2(env_cg)) {
2958 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2961 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2965 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2968 set_irn_pinned(new_op, op_pin_state_floats);
2969 set_ia32_frame_ent(new_op, ent);
2970 set_ia32_use_frame(new_op);
2972 set_ia32_op_type(new_op, ia32_AddrModeS);
2973 set_ia32_am_flavour(new_op, ia32_am_B);
2974 set_ia32_ls_mode(new_op, mode);
2975 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2977 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2984 * Transforms a FrameStore into an ia32 Store.
2986 static ir_node *gen_be_FrameStore(ir_node *node) {
2987 ir_node *block = be_transform_node(get_nodes_block(node));
2988 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2989 ir_node *new_mem = be_transform_node(mem);
2990 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2991 ir_node *new_ptr = be_transform_node(ptr);
2992 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2993 ir_node *new_val = be_transform_node(val);
2994 ir_node *new_op = NULL;
2995 ir_graph *irg = current_ir_graph;
2996 dbg_info *dbgi = get_irn_dbg_info(node);
2997 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2998 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2999 ir_mode *mode = get_irn_mode(val);
3001 if (mode_is_float(mode)) {
3002 if (USE_SSE2(env_cg)) {
3003 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3005 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
3007 } else if (get_mode_size_bits(mode) == 8) {
3008 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3010 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3013 set_ia32_frame_ent(new_op, ent);
3014 set_ia32_use_frame(new_op);
3016 set_ia32_op_type(new_op, ia32_AddrModeD);
3017 set_ia32_am_flavour(new_op, ia32_am_B);
3018 set_ia32_ls_mode(new_op, mode);
3020 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3026 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3028 static ir_node *gen_be_Return(ir_node *node) {
3029 ir_graph *irg = current_ir_graph;
3030 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3031 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3032 ir_entity *ent = get_irg_entity(irg);
3033 ir_type *tp = get_entity_type(ent);
3038 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3039 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3042 int pn_ret_val, pn_ret_mem, arity, i;
3044 assert(ret_val != NULL);
3045 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3046 return be_duplicate_node(node);
3049 res_type = get_method_res_type(tp, 0);
3051 if (! is_Primitive_type(res_type)) {
3052 return be_duplicate_node(node);
3055 mode = get_type_mode(res_type);
3056 if (! mode_is_float(mode)) {
3057 return be_duplicate_node(node);
3060 assert(get_method_n_ress(tp) == 1);
3062 pn_ret_val = get_Proj_proj(ret_val);
3063 pn_ret_mem = get_Proj_proj(ret_mem);
3065 /* get the Barrier */
3066 barrier = get_Proj_pred(ret_val);
3068 /* get result input of the Barrier */
3069 ret_val = get_irn_n(barrier, pn_ret_val);
3070 new_ret_val = be_transform_node(ret_val);
3072 /* get memory input of the Barrier */
3073 ret_mem = get_irn_n(barrier, pn_ret_mem);
3074 new_ret_mem = be_transform_node(ret_mem);
3076 frame = get_irg_frame(irg);
3078 dbgi = get_irn_dbg_info(barrier);
3079 block = be_transform_node(get_nodes_block(barrier));
3081 noreg = ia32_new_NoReg_gp(env_cg);
3083 /* store xmm0 onto stack */
3084 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3085 new_ret_val, new_ret_mem);
3086 set_ia32_ls_mode(sse_store, mode);
3087 set_ia32_op_type(sse_store, ia32_AddrModeD);
3088 set_ia32_use_frame(sse_store);
3089 set_ia32_am_flavour(sse_store, ia32_am_B);
3091 /* load into x87 register */
3092 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3093 set_ia32_op_type(fld, ia32_AddrModeS);
3094 set_ia32_use_frame(fld);
3095 set_ia32_am_flavour(fld, ia32_am_B);
3097 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3098 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3100 /* create a new barrier */
3101 arity = get_irn_arity(barrier);
3102 in = alloca(arity * sizeof(in[0]));
3103 for (i = 0; i < arity; ++i) {
3106 if (i == pn_ret_val) {
3108 } else if (i == pn_ret_mem) {
3111 ir_node *in = get_irn_n(barrier, i);
3112 new_in = be_transform_node(in);
3117 new_barrier = new_ir_node(dbgi, irg, block,
3118 get_irn_op(barrier), get_irn_mode(barrier),
3120 copy_node_attr(barrier, new_barrier);
3121 be_duplicate_deps(barrier, new_barrier);
3122 be_set_transformed_node(barrier, new_barrier);
3123 mark_irn_visited(barrier);
3125 /* transform normally */
3126 return be_duplicate_node(node);
3130 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3132 static ir_node *gen_be_AddSP(ir_node *node) {
3133 ir_node *block = be_transform_node(get_nodes_block(node));
3134 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3136 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3137 ir_node *new_sp = be_transform_node(sp);
3138 ir_graph *irg = current_ir_graph;
3139 dbg_info *dbgi = get_irn_dbg_info(node);
3140 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3141 ir_node *nomem = new_NoMem();
3144 new_sz = create_immediate_or_transform(sz, 0);
3146 /* ia32 stack grows in reverse direction, make a SubSP */
3147 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3149 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3150 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3156 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3158 static ir_node *gen_be_SubSP(ir_node *node) {
3159 ir_node *block = be_transform_node(get_nodes_block(node));
3160 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3162 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3163 ir_node *new_sp = be_transform_node(sp);
3164 ir_graph *irg = current_ir_graph;
3165 dbg_info *dbgi = get_irn_dbg_info(node);
3166 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3167 ir_node *nomem = new_NoMem();
3170 new_sz = create_immediate_or_transform(sz, 0);
3172 /* ia32 stack grows in reverse direction, make an AddSP */
3173 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3174 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3175 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3181 * This function just sets the register for the Unknown node
3182 * as this is not done during register allocation because Unknown
3183 * is an "ignore" node.
3185 static ir_node *gen_Unknown(ir_node *node) {
3186 ir_mode *mode = get_irn_mode(node);
3188 if (mode_is_float(mode)) {
3190 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3191 if (USE_SSE2(env_cg))
3192 return ia32_new_Unknown_xmm(env_cg);
3194 return ia32_new_Unknown_vfp(env_cg);
3196 ir_graph *irg = current_ir_graph;
3197 dbg_info *dbgi = get_irn_dbg_info(node);
3198 ir_node *block = get_irg_start_block(irg);
3199 return new_rd_ia32_vfldz(dbgi, irg, block);
3201 } else if (mode_needs_gp_reg(mode)) {
3202 return ia32_new_Unknown_gp(env_cg);
3204 assert(0 && "unsupported Unknown-Mode");
3211 * Change some phi modes
3213 static ir_node *gen_Phi(ir_node *node) {
3214 ir_node *block = be_transform_node(get_nodes_block(node));
3215 ir_graph *irg = current_ir_graph;
3216 dbg_info *dbgi = get_irn_dbg_info(node);
3217 ir_mode *mode = get_irn_mode(node);
3220 if(mode_needs_gp_reg(mode)) {
3221 /* we shouldn't have any 64bit stuff around anymore */
3222 assert(get_mode_size_bits(mode) <= 32);
3223 /* all integer operations are on 32bit registers now */
3225 } else if(mode_is_float(mode)) {
3226 if (USE_SSE2(env_cg)) {
3233 /* phi nodes allow loops, so we use the old arguments for now
3234 * and fix this later */
3235 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3236 copy_node_attr(node, phi);
3237 be_duplicate_deps(node, phi);
3239 be_set_transformed_node(node, phi);
3240 be_enqueue_preds(node);
3248 static ir_node *gen_IJmp(ir_node *node) {
3249 ir_node *block = be_transform_node(get_nodes_block(node));
3250 ir_graph *irg = current_ir_graph;
3251 dbg_info *dbgi = get_irn_dbg_info(node);
3252 ir_node *new_op = be_transform_node(get_IJmp_target(node));
3253 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3254 ir_node *nomem = new_NoMem();
3257 new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
3258 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
3260 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3266 /**********************************************************************
3269 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3270 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3271 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3272 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3274 **********************************************************************/
3276 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3278 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3281 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3282 ir_node *val, ir_node *mem);
3285 * Transforms a lowered Load into a "real" one.
3287 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3289 ir_node *block = be_transform_node(get_nodes_block(node));
3290 ir_node *ptr = get_irn_n(node, 0);
3291 ir_node *new_ptr = be_transform_node(ptr);
3292 ir_node *mem = get_irn_n(node, 1);
3293 ir_node *new_mem = be_transform_node(mem);
3294 ir_graph *irg = current_ir_graph;
3295 dbg_info *dbgi = get_irn_dbg_info(node);
3296 ir_mode *mode = get_ia32_ls_mode(node);
3297 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3300 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3302 set_ia32_op_type(new_op, ia32_AddrModeS);
3303 set_ia32_am_flavour(new_op, ia32_am_OB);
3304 set_ia32_am_offs_int(new_op, 0);
3305 set_ia32_am_scale(new_op, 1);
3306 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3307 if (is_ia32_am_sc_sign(node))
3308 set_ia32_am_sc_sign(new_op);
3309 set_ia32_ls_mode(new_op, mode);
3310 if (is_ia32_use_frame(node)) {
3311 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3312 set_ia32_use_frame(new_op);
3315 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3321 * Transforms a lowered Store into a "real" one.
3323 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3325 ir_node *block = be_transform_node(get_nodes_block(node));
3326 ir_node *ptr = get_irn_n(node, 0);
3327 ir_node *new_ptr = be_transform_node(ptr);
3328 ir_node *val = get_irn_n(node, 1);
3329 ir_node *new_val = be_transform_node(val);
3330 ir_node *mem = get_irn_n(node, 2);
3331 ir_node *new_mem = be_transform_node(mem);
3332 ir_graph *irg = current_ir_graph;
3333 dbg_info *dbgi = get_irn_dbg_info(node);
3334 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3335 ir_mode *mode = get_ia32_ls_mode(node);
3338 ia32_am_flavour_t am_flav = ia32_B;
3340 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3342 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3344 add_ia32_am_offs_int(new_op, am_offs);
3347 set_ia32_op_type(new_op, ia32_AddrModeD);
3348 set_ia32_am_flavour(new_op, am_flav);
3349 set_ia32_ls_mode(new_op, mode);
3350 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3351 set_ia32_use_frame(new_op);
3353 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3360 * Transforms an ia32_l_XXX into a "real" XXX node
3362 * @param env The transformation environment
3363 * @return the created ia32 XXX node
3365 #define GEN_LOWERED_OP(op) \
3366 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3367 return gen_binop(node, get_binop_left(node), \
3368 get_binop_right(node), new_rd_ia32_##op,0); \
3371 #define GEN_LOWERED_x87_OP(op) \
3372 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3374 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3375 get_binop_right(node), new_rd_ia32_##op); \
3379 #define GEN_LOWERED_UNOP(op) \
3380 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3381 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3384 #define GEN_LOWERED_SHIFT_OP(op) \
3385 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3386 return gen_shift_binop(node, get_binop_left(node), \
3387 get_binop_right(node), new_rd_ia32_##op); \
3390 #define GEN_LOWERED_LOAD(op) \
3391 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3392 return gen_lowered_Load(node, new_rd_ia32_##op); \
3395 #define GEN_LOWERED_STORE(op) \
3396 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3397 return gen_lowered_Store(node, new_rd_ia32_##op); \
3404 GEN_LOWERED_OP(IMul)
3406 GEN_LOWERED_x87_OP(vfprem)
3407 GEN_LOWERED_x87_OP(vfmul)
3408 GEN_LOWERED_x87_OP(vfsub)
3410 GEN_LOWERED_UNOP(Neg)
3412 GEN_LOWERED_LOAD(vfild)
3413 GEN_LOWERED_LOAD(Load)
3414 // GEN_LOWERED_STORE(vfist) TODO
3415 GEN_LOWERED_STORE(Store)
3417 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3418 ir_node *block = be_transform_node(get_nodes_block(node));
3419 ir_node *left = get_binop_left(node);
3420 ir_node *new_left = be_transform_node(left);
3421 ir_node *right = get_binop_right(node);
3422 ir_node *new_right = be_transform_node(right);
3423 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3424 ir_graph *irg = current_ir_graph;
3425 dbg_info *dbgi = get_irn_dbg_info(node);
3426 ir_node *fpcw = get_fpcw();
3429 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3430 new_right, new_NoMem(), fpcw);
3431 clear_ia32_commutative(vfdiv);
3432 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3434 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3440 * Transforms a l_MulS into a "real" MulS node.
3442 * @param env The transformation environment
3443 * @return the created ia32 Mul node
3445 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3446 ir_node *block = be_transform_node(get_nodes_block(node));
3447 ir_node *left = get_binop_left(node);
3448 ir_node *new_left = be_transform_node(left);
3449 ir_node *right = get_binop_right(node);
3450 ir_node *new_right = be_transform_node(right);
3451 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3452 ir_graph *irg = current_ir_graph;
3453 dbg_info *dbgi = get_irn_dbg_info(node);
3455 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3456 /* and then skip the result Proj, because all needed Projs are already there. */
3457 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3458 new_right, new_NoMem());
3459 clear_ia32_commutative(muls);
3460 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3462 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3467 GEN_LOWERED_SHIFT_OP(Shl)
3468 GEN_LOWERED_SHIFT_OP(Shr)
3469 GEN_LOWERED_SHIFT_OP(Sar)
3472 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3473 * op1 - target to be shifted
3474 * op2 - contains bits to be shifted into target
3476 * Only op3 can be an immediate.
3478 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3479 ir_node *op2, ir_node *count)
3481 ir_node *block = be_transform_node(get_nodes_block(node));
3482 ir_node *new_op1 = be_transform_node(op1);
3483 ir_node *new_op2 = be_transform_node(op2);
3484 ir_node *new_count = be_transform_node(count);
3485 ir_node *new_op = NULL;
3486 ir_graph *irg = current_ir_graph;
3487 dbg_info *dbgi = get_irn_dbg_info(node);
3488 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3489 ir_node *nomem = new_NoMem();
3493 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3495 /* Check if immediate optimization is on and */
3496 /* if it's an operation with immediate. */
3497 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3499 /* Limit imm_op within range imm8 */
3501 tv = get_ia32_Immop_tarval(imm_op);
3504 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3505 set_ia32_Immop_tarval(imm_op, tv);
3512 /* integer operations */
3514 /* This is ShiftD with const */
3515 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3517 if (is_ia32_l_ShlD(node))
3518 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3519 new_op1, new_op2, noreg, nomem);
3521 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3522 new_op1, new_op2, noreg, nomem);
3523 copy_ia32_Immop_attr(new_op, imm_op);
3526 /* This is a normal ShiftD */
3527 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3528 if (is_ia32_l_ShlD(node))
3529 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3530 new_op1, new_op2, new_count, nomem);
3532 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3533 new_op1, new_op2, new_count, nomem);
3536 /* set AM support */
3537 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3539 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3541 set_ia32_emit_cl(new_op);
3546 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3547 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3548 get_irn_n(node, 1), get_irn_n(node, 2));
3551 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3552 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3553 get_irn_n(node, 1), get_irn_n(node, 2));
3557 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3559 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3560 ir_node *block = be_transform_node(get_nodes_block(node));
3561 ir_node *val = get_irn_n(node, 1);
3562 ir_node *new_val = be_transform_node(val);
3563 ia32_code_gen_t *cg = env_cg;
3564 ir_node *res = NULL;
3565 ir_graph *irg = current_ir_graph;
3567 ir_node *noreg, *new_ptr, *new_mem;
3574 mem = get_irn_n(node, 2);
3575 new_mem = be_transform_node(mem);
3576 ptr = get_irn_n(node, 0);
3577 new_ptr = be_transform_node(ptr);
3578 noreg = ia32_new_NoReg_gp(cg);
3579 dbgi = get_irn_dbg_info(node);
3581 /* Store x87 -> MEM */
3582 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3583 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3584 set_ia32_use_frame(res);
3585 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3586 set_ia32_am_flavour(res, ia32_B);
3587 set_ia32_op_type(res, ia32_AddrModeD);
3589 /* Load MEM -> SSE */
3590 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3591 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3592 set_ia32_use_frame(res);
3593 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3594 set_ia32_am_flavour(res, ia32_B);
3595 set_ia32_op_type(res, ia32_AddrModeS);
3596 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3602 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3604 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3605 ir_node *block = be_transform_node(get_nodes_block(node));
3606 ir_node *val = get_irn_n(node, 1);
3607 ir_node *new_val = be_transform_node(val);
3608 ia32_code_gen_t *cg = env_cg;
3609 ir_graph *irg = current_ir_graph;
3610 ir_node *res = NULL;
3611 ir_entity *fent = get_ia32_frame_ent(node);
3612 ir_mode *lsmode = get_ia32_ls_mode(node);
3614 ir_node *noreg, *new_ptr, *new_mem;
3618 if (! USE_SSE2(cg)) {
3619 /* SSE unit is not used -> skip this node. */
3623 ptr = get_irn_n(node, 0);
3624 new_ptr = be_transform_node(ptr);
3625 mem = get_irn_n(node, 2);
3626 new_mem = be_transform_node(mem);
3627 noreg = ia32_new_NoReg_gp(cg);
3628 dbgi = get_irn_dbg_info(node);
3630 /* Store SSE -> MEM */
3631 if (is_ia32_xLoad(skip_Proj(new_val))) {
3632 ir_node *ld = skip_Proj(new_val);
3634 /* we can vfld the value directly into the fpu */
3635 fent = get_ia32_frame_ent(ld);
3636 ptr = get_irn_n(ld, 0);
3637 offs = get_ia32_am_offs_int(ld);
3639 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3640 set_ia32_frame_ent(res, fent);
3641 set_ia32_use_frame(res);
3642 set_ia32_ls_mode(res, lsmode);
3643 set_ia32_am_flavour(res, ia32_B);
3644 set_ia32_op_type(res, ia32_AddrModeD);
3648 /* Load MEM -> x87 */
3649 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3650 set_ia32_frame_ent(res, fent);
3651 set_ia32_use_frame(res);
3652 add_ia32_am_offs_int(res, offs);
3653 set_ia32_am_flavour(res, ia32_B);
3654 set_ia32_op_type(res, ia32_AddrModeS);
3655 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3660 /*********************************************************
3663 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3664 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3665 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3666 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3668 *********************************************************/
3671 * the BAD transformer.
3673 static ir_node *bad_transform(ir_node *node) {
3674 panic("No transform function for %+F available.\n", node);
3679 * Transform the Projs of an AddSP.
3681 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3682 ir_node *block = be_transform_node(get_nodes_block(node));
3683 ir_node *pred = get_Proj_pred(node);
3684 ir_node *new_pred = be_transform_node(pred);
3685 ir_graph *irg = current_ir_graph;
3686 dbg_info *dbgi = get_irn_dbg_info(node);
3687 long proj = get_Proj_proj(node);
3689 if (proj == pn_be_AddSP_sp) {
3690 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3691 pn_ia32_SubSP_stack);
3692 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3694 } else if(proj == pn_be_AddSP_res) {
3695 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3696 pn_ia32_SubSP_addr);
3697 } else if (proj == pn_be_AddSP_M) {
3698 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3702 return new_rd_Unknown(irg, get_irn_mode(node));
3706 * Transform the Projs of a SubSP.
3708 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3709 ir_node *block = be_transform_node(get_nodes_block(node));
3710 ir_node *pred = get_Proj_pred(node);
3711 ir_node *new_pred = be_transform_node(pred);
3712 ir_graph *irg = current_ir_graph;
3713 dbg_info *dbgi = get_irn_dbg_info(node);
3714 long proj = get_Proj_proj(node);
3716 if (proj == pn_be_SubSP_sp) {
3717 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3718 pn_ia32_AddSP_stack);
3719 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3721 } else if (proj == pn_be_SubSP_M) {
3722 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3726 return new_rd_Unknown(irg, get_irn_mode(node));
3730 * Transform and renumber the Projs from a Load.
3732 static ir_node *gen_Proj_Load(ir_node *node) {
3733 ir_node *block = be_transform_node(get_nodes_block(node));
3734 ir_node *pred = get_Proj_pred(node);
3735 ir_node *new_pred = be_transform_node(pred);
3736 ir_graph *irg = current_ir_graph;
3737 dbg_info *dbgi = get_irn_dbg_info(node);
3738 long proj = get_Proj_proj(node);
3740 /* renumber the proj */
3741 if (is_ia32_Load(new_pred)) {
3742 if (proj == pn_Load_res) {
3743 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3744 } else if (proj == pn_Load_M) {
3745 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3747 } else if (is_ia32_xLoad(new_pred)) {
3748 if (proj == pn_Load_res) {
3749 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3750 } else if (proj == pn_Load_M) {
3751 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3753 } else if (is_ia32_vfld(new_pred)) {
3754 if (proj == pn_Load_res) {
3755 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3756 } else if (proj == pn_Load_M) {
3757 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3762 return new_rd_Unknown(irg, get_irn_mode(node));
3766 * Transform and renumber the Projs from a DivMod like instruction.
3768 static ir_node *gen_Proj_DivMod(ir_node *node) {
3769 ir_node *block = be_transform_node(get_nodes_block(node));
3770 ir_node *pred = get_Proj_pred(node);
3771 ir_node *new_pred = be_transform_node(pred);
3772 ir_graph *irg = current_ir_graph;
3773 dbg_info *dbgi = get_irn_dbg_info(node);
3774 ir_mode *mode = get_irn_mode(node);
3775 long proj = get_Proj_proj(node);
3777 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3779 switch (get_irn_opcode(pred)) {
3783 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3785 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3793 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3795 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3803 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3804 case pn_DivMod_res_div:
3805 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3806 case pn_DivMod_res_mod:
3807 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3817 return new_rd_Unknown(irg, mode);
3821 * Transform and renumber the Projs from a CopyB.
3823 static ir_node *gen_Proj_CopyB(ir_node *node) {
3824 ir_node *block = be_transform_node(get_nodes_block(node));
3825 ir_node *pred = get_Proj_pred(node);
3826 ir_node *new_pred = be_transform_node(pred);
3827 ir_graph *irg = current_ir_graph;
3828 dbg_info *dbgi = get_irn_dbg_info(node);
3829 ir_mode *mode = get_irn_mode(node);
3830 long proj = get_Proj_proj(node);
3833 case pn_CopyB_M_regular:
3834 if (is_ia32_CopyB_i(new_pred)) {
3835 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3836 } else if (is_ia32_CopyB(new_pred)) {
3837 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3845 return new_rd_Unknown(irg, mode);
3849 * Transform and renumber the Projs from a vfdiv.
3851 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3852 ir_node *block = be_transform_node(get_nodes_block(node));
3853 ir_node *pred = get_Proj_pred(node);
3854 ir_node *new_pred = be_transform_node(pred);
3855 ir_graph *irg = current_ir_graph;
3856 dbg_info *dbgi = get_irn_dbg_info(node);
3857 ir_mode *mode = get_irn_mode(node);
3858 long proj = get_Proj_proj(node);
3861 case pn_ia32_l_vfdiv_M:
3862 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3863 case pn_ia32_l_vfdiv_res:
3864 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3869 return new_rd_Unknown(irg, mode);
3873 * Transform and renumber the Projs from a Quot.
3875 static ir_node *gen_Proj_Quot(ir_node *node) {
3876 ir_node *block = be_transform_node(get_nodes_block(node));
3877 ir_node *pred = get_Proj_pred(node);
3878 ir_node *new_pred = be_transform_node(pred);
3879 ir_graph *irg = current_ir_graph;
3880 dbg_info *dbgi = get_irn_dbg_info(node);
3881 ir_mode *mode = get_irn_mode(node);
3882 long proj = get_Proj_proj(node);
3886 if (is_ia32_xDiv(new_pred)) {
3887 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3888 } else if (is_ia32_vfdiv(new_pred)) {
3889 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3893 if (is_ia32_xDiv(new_pred)) {
3894 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3895 } else if (is_ia32_vfdiv(new_pred)) {
3896 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3904 return new_rd_Unknown(irg, mode);
3908 * Transform the Thread Local Storage Proj.
3910 static ir_node *gen_Proj_tls(ir_node *node) {
3911 ir_node *block = be_transform_node(get_nodes_block(node));
3912 ir_graph *irg = current_ir_graph;
3913 dbg_info *dbgi = NULL;
3914 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3920 * Transform the Projs from a be_Call.
3922 static ir_node *gen_Proj_be_Call(ir_node *node) {
3923 ir_node *block = be_transform_node(get_nodes_block(node));
3924 ir_node *call = get_Proj_pred(node);
3925 ir_node *new_call = be_transform_node(call);
3926 ir_graph *irg = current_ir_graph;
3927 dbg_info *dbgi = get_irn_dbg_info(node);
3928 long proj = get_Proj_proj(node);
3929 ir_mode *mode = get_irn_mode(node);
3931 const arch_register_class_t *cls;
3933 /* The following is kinda tricky: If we're using SSE, then we have to
3934 * move the result value of the call in floating point registers to an
3935 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3936 * after the call, we have to make sure to correctly make the
3937 * MemProj and the result Proj use these 2 nodes
3939 if (proj == pn_be_Call_M_regular) {
3940 // get new node for result, are we doing the sse load/store hack?
3941 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3942 ir_node *call_res_new;
3943 ir_node *call_res_pred = NULL;
3945 if (call_res != NULL) {
3946 call_res_new = be_transform_node(call_res);
3947 call_res_pred = get_Proj_pred(call_res_new);
3950 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3951 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3952 pn_be_Call_M_regular);
3954 assert(is_ia32_xLoad(call_res_pred));
3955 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3959 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3961 ir_node *frame = get_irg_frame(irg);
3962 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3964 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3967 /* in case there is no memory output: create one to serialize the copy
3969 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3970 pn_be_Call_M_regular);
3971 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3972 pn_be_Call_first_res);
3974 /* store st(0) onto stack */
3975 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3977 set_ia32_op_type(fstp, ia32_AddrModeD);
3978 set_ia32_use_frame(fstp);
3979 set_ia32_am_flavour(fstp, ia32_am_B);
3981 /* load into SSE register */
3982 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3983 set_ia32_ls_mode(sse_load, mode);
3984 set_ia32_op_type(sse_load, ia32_AddrModeS);
3985 set_ia32_use_frame(sse_load);
3986 set_ia32_am_flavour(sse_load, ia32_am_B);
3988 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3992 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3994 /* get a Proj representing a caller save register */
3995 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3996 assert(is_Proj(p) && "Proj expected.");
3998 /* user of the the proj is the Keep */
3999 p = get_edge_src_irn(get_irn_out_edge_first(p));
4000 assert(be_is_Keep(p) && "Keep expected.");
4006 /* transform call modes */
4007 if (mode_is_data(mode)) {
4008 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4012 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4016 * Transform the Projs from a Cmp.
4018 static ir_node *gen_Proj_Cmp(ir_node *node)
4020 /* normally Cmps are processed when looking at Cond nodes, but this case
4021 * can happen in complicated Psi conditions */
4023 ir_node *cmp = get_Proj_pred(node);
4024 long pnc = get_Proj_proj(node);
4025 ir_node *cmp_left = get_Cmp_left(cmp);
4026 ir_node *cmp_right = get_Cmp_right(cmp);
4027 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4028 dbg_info *dbgi = get_irn_dbg_info(cmp);
4029 ir_node *block = be_transform_node(get_nodes_block(node));
4032 assert(!mode_is_float(cmp_mode));
4034 if(!mode_is_signed(cmp_mode)) {
4035 pnc |= ia32_pn_Cmp_Unsigned;
4038 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4039 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4045 * Transform and potentially renumber Proj nodes.
4047 static ir_node *gen_Proj(ir_node *node) {
4048 ir_graph *irg = current_ir_graph;
4049 dbg_info *dbgi = get_irn_dbg_info(node);
4050 ir_node *pred = get_Proj_pred(node);
4051 long proj = get_Proj_proj(node);
4053 if (is_Store(pred) || be_is_FrameStore(pred)) {
4054 if (proj == pn_Store_M) {
4055 return be_transform_node(pred);
4058 return new_r_Bad(irg);
4060 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4061 return gen_Proj_Load(node);
4062 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4063 return gen_Proj_DivMod(node);
4064 } else if (is_CopyB(pred)) {
4065 return gen_Proj_CopyB(node);
4066 } else if (is_Quot(pred)) {
4067 return gen_Proj_Quot(node);
4068 } else if (is_ia32_l_vfdiv(pred)) {
4069 return gen_Proj_l_vfdiv(node);
4070 } else if (be_is_SubSP(pred)) {
4071 return gen_Proj_be_SubSP(node);
4072 } else if (be_is_AddSP(pred)) {
4073 return gen_Proj_be_AddSP(node);
4074 } else if (be_is_Call(pred)) {
4075 return gen_Proj_be_Call(node);
4076 } else if (is_Cmp(pred)) {
4077 return gen_Proj_Cmp(node);
4078 } else if (get_irn_op(pred) == op_Start) {
4079 if (proj == pn_Start_X_initial_exec) {
4080 ir_node *block = get_nodes_block(pred);
4083 /* we exchange the ProjX with a jump */
4084 block = be_transform_node(block);
4085 jump = new_rd_Jmp(dbgi, irg, block);
4088 if (node == be_get_old_anchor(anchor_tls)) {
4089 return gen_Proj_tls(node);
4092 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4096 ir_node *new_pred = be_transform_node(pred);
4097 ir_node *block = be_transform_node(get_nodes_block(node));
4098 ir_mode *mode = get_irn_mode(node);
4099 if (mode_needs_gp_reg(mode)) {
4100 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4101 get_Proj_proj(node));
4102 #ifdef DEBUG_libfirm
4103 new_proj->node_nr = node->node_nr;
4109 return be_duplicate_node(node);
4113 * Enters all transform functions into the generic pointer
4115 static void register_transformers(void)
4119 /* first clear the generic function pointer for all ops */
4120 clear_irp_opcodes_generic_func();
4122 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4123 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4160 /* transform ops from intrinsic lowering */
4180 /* GEN(ia32_l_vfist); TODO */
4182 GEN(ia32_l_X87toSSE);
4183 GEN(ia32_l_SSEtoX87);
4188 /* we should never see these nodes */
4203 /* handle generic backend nodes */
4214 /* set the register for all Unknown nodes */
4217 op_Mulh = get_op_Mulh();
4226 * Pre-transform all unknown and noreg nodes.
4228 static void ia32_pretransform_node(void *arch_cg) {
4229 ia32_code_gen_t *cg = arch_cg;
4231 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4232 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4233 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4234 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4235 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4236 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4241 void add_missing_keep_walker(ir_node *node, void *data)
4244 unsigned found_projs = 0;
4245 const ir_edge_t *edge;
4246 ir_mode *mode = get_irn_mode(node);
4251 if(!is_ia32_irn(node))
4254 n_outs = get_ia32_n_res(node);
4257 if(is_ia32_SwitchJmp(node))
4260 assert(n_outs < (int) sizeof(unsigned) * 8);
4261 foreach_out_edge(node, edge) {
4262 ir_node *proj = get_edge_src_irn(edge);
4263 int pn = get_Proj_proj(proj);
4265 assert(pn < n_outs);
4266 found_projs |= 1 << pn;
4270 /* are keeps missing? */
4272 for(i = 0; i < n_outs; ++i) {
4275 const arch_register_req_t *req;
4276 const arch_register_class_t *class;
4278 if(found_projs & (1 << i)) {
4282 req = get_ia32_out_req(node, i);
4288 block = get_nodes_block(node);
4289 in[0] = new_r_Proj(current_ir_graph, block, node,
4290 arch_register_class_mode(class), i);
4291 if(last_keep != NULL) {
4292 be_Keep_add_node(last_keep, class, in[0]);
4294 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4300 * Adds missing keeps to nodes
4303 void add_missing_keeps(ia32_code_gen_t *cg)
4305 ir_graph *irg = be_get_birg_irg(cg->birg);
4306 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4309 /* do the transformation */
4310 void ia32_transform_graph(ia32_code_gen_t *cg) {
4311 register_transformers();
4313 initial_fpcw = NULL;
4314 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4315 edges_verify(cg->irg);
4316 add_missing_keeps(cg);
4317 edges_verify(cg->irg);
4320 void ia32_init_transform(void)
4322 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");