2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
103 ir_node *op2, ir_node *mem);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
117 ir_node *op2, ir_node *mem, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *new_block,
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
152 * creates a unique ident by adding a number to a tag
154 * @param tag the tag string, must contain a %d if a number
157 static ident *unique_id(const char *tag)
159 static unsigned id = 0;
162 snprintf(str, sizeof(str), tag, ++id);
163 return new_id_from_str(str);
167 * Get a primitive type for a mode.
169 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
171 pmap_entry *e = pmap_find(types, mode);
176 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
177 res = new_type_primitive(new_id_from_str(buf), mode);
178 set_type_alignment_bytes(res, 16);
179 pmap_insert(types, mode, res);
187 * Get an atomic entity that is initialized with a tarval
189 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
191 tarval *tv = get_Const_tarval(cnst);
192 pmap_entry *e = pmap_find(isa->tv_ent, tv);
197 ir_mode *mode = get_irn_mode(cnst);
198 ir_type *tp = get_Const_type(cnst);
199 if (tp == firm_unknown_type)
200 tp = get_prim_type(isa->types, mode);
202 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
204 set_entity_ld_ident(res, get_entity_ident(res));
205 set_entity_visibility(res, visibility_local);
206 set_entity_variability(res, variability_constant);
207 set_entity_allocation(res, allocation_static);
209 /* we create a new entity here: It's initialization must resist on the
211 rem = current_ir_graph;
212 current_ir_graph = get_const_code_irg();
213 set_atomic_ent_value(res, new_Const_type(tv, tp));
214 current_ir_graph = rem;
216 pmap_insert(isa->tv_ent, tv, res);
224 static int is_Const_0(ir_node *node) {
228 return classify_Const(node) == CNST_NULL;
231 static int is_Const_1(ir_node *node) {
235 return classify_Const(node) == CNST_ONE;
238 static int is_Const_Minus_1(ir_node *node) {
244 mode = get_irn_mode(node);
245 if(!mode_is_signed(mode))
248 tv = get_Const_tarval(node);
251 return classify_tarval(tv) == CNST_ONE;
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
270 cnst_classify_t clss = classify_Const(node);
272 if (USE_SSE2(env_cg)) {
273 if (clss == CNST_NULL) {
274 load = new_rd_ia32_xZero(dbgi, irg, block);
275 set_ia32_ls_mode(load, mode);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
282 set_ia32_op_type(load, ia32_AddrModeS);
283 set_ia32_am_sc(load, floatent);
284 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
285 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_sc(load, floatent);
300 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
306 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
308 /* Const Nodes before the initial IncSP are a bad idea, because
309 * they could be spilled and we have no SP ready at that point yet.
310 * So add a dependency to the initial frame pointer calculation to
311 * avoid that situation.
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(load, get_irg_frame(irg));
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 tarval *tv = get_Const_tarval(node);
324 tv = tarval_convert_to(tv, mode_Iu);
326 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
328 panic("couldn't convert constant tarval (%+F)", node);
330 val = get_tarval_long(tv);
332 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
333 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
336 if (get_irg_start_block(irg) == block) {
337 add_irn_dep(cnst, get_irg_frame(irg));
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *old_block = get_nodes_block(node);
350 ir_node *block = be_transform_node(old_block);
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
356 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
357 ir_node *nomem = new_NoMem();
359 if (USE_SSE2(env_cg))
360 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
363 set_ia32_am_sc(cnst, get_SymConst_entity(node));
364 set_ia32_use_frame(cnst);
368 if(get_SymConst_kind(node) != symconst_addr_ent) {
369 panic("backend only support symconst_addr_ent (at %+F)", node);
371 entity = get_SymConst_entity(node);
372 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
375 /* Const Nodes before the initial IncSP are a bad idea, because
376 * they could be spilled and we have no SP ready at that point yet
378 if (get_irg_start_block(irg) == block) {
379 add_irn_dep(cnst, get_irg_frame(irg));
382 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
387 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
388 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
389 static const struct {
391 const char *ent_name;
392 const char *cnst_str;
395 } names [ia32_known_const_max] = {
396 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
397 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
398 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
399 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
400 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
402 static ir_entity *ent_cache[ia32_known_const_max];
404 const char *tp_name, *ent_name, *cnst_str;
412 ent_name = names[kct].ent_name;
413 if (! ent_cache[kct]) {
414 tp_name = names[kct].tp_name;
415 cnst_str = names[kct].cnst_str;
417 switch (names[kct].mode) {
418 case 0: mode = mode_Iu; break;
419 case 1: mode = mode_Lu; break;
420 default: mode = mode_F; break;
422 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
423 tp = new_type_primitive(new_id_from_str(tp_name), mode);
424 /* set the specified alignment */
425 set_type_alignment_bytes(tp, names[kct].align);
427 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
429 set_entity_ld_ident(ent, get_entity_ident(ent));
430 set_entity_visibility(ent, visibility_local);
431 set_entity_variability(ent, variability_constant);
432 set_entity_allocation(ent, allocation_static);
434 /* we create a new entity here: It's initialization must resist on the
436 rem = current_ir_graph;
437 current_ir_graph = get_const_code_irg();
438 cnst = new_Const(mode, tv);
439 current_ir_graph = rem;
441 set_atomic_ent_value(ent, cnst);
443 /* cache the entry */
444 ent_cache[kct] = ent;
447 return ent_cache[kct];
452 * Prints the old node name on cg obst and returns a pointer to it.
454 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
455 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
457 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
458 obstack_1grow(isa->name_obst, 0);
459 return obstack_finish(isa->name_obst);
463 static int use_source_address_mode(ir_node *block, ir_node *node,
472 load = get_Proj_pred(node);
473 pn = get_Proj_proj(node);
474 if(!is_Load(load) || pn != pn_Load_res)
476 if(get_nodes_block(load) != block)
478 /* we only use address mode if we're the only user of the load */
479 if(get_irn_n_edges(node) > 1)
482 mode = get_irn_mode(node);
483 if(!mode_needs_gp_reg(mode))
485 if(get_mode_size_bits(mode) != 32)
488 /* don't do AM if other node inputs depend on the load (via mem-proj) */
489 if(other != NULL && get_nodes_block(other) == block
490 && heights_reachable_in_block(heights, other, load))
496 typedef struct ia32_address_mode_t ia32_address_mode_t;
497 struct ia32_address_mode_t {
501 ia32_op_type_t op_type;
508 static void build_address(ia32_address_mode_t *am, ir_node *node)
510 ia32_address_t *addr = &am->addr;
511 ir_node *load = get_Proj_pred(node);
512 ir_node *ptr = get_Load_ptr(load);
513 ir_node *mem = get_Load_mem(load);
514 ir_node *new_mem = be_transform_node(mem);
518 am->ls_mode = get_Load_mode(load);
519 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
521 /* construct load address */
522 ia32_create_address_mode(addr, ptr, 0);
527 base = ia32_new_NoReg_gp(env_cg);
529 base = be_transform_node(base);
533 index = ia32_new_NoReg_gp(env_cg);
535 index = be_transform_node(index);
543 static void set_address(ir_node *node, ia32_address_t *addr)
545 set_ia32_am_scale(node, addr->scale);
546 set_ia32_am_sc(node, addr->symconst_ent);
547 set_ia32_am_offs_int(node, addr->offset);
548 if(addr->symconst_sign)
549 set_ia32_am_sc_sign(node);
551 set_ia32_use_frame(node);
552 set_ia32_frame_ent(node, addr->frame_entity);
555 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
557 set_address(node, &am->addr);
559 set_ia32_op_type(node, am->op_type);
560 set_ia32_ls_mode(node, am->ls_mode);
562 set_ia32_commutative(node);
565 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
566 ir_node *op1, ir_node *op2, int commutative,
567 int use_am_and_immediates, int use_am)
569 ia32_address_t *addr = &am->addr;
570 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
574 memset(am, 0, sizeof(am[0]));
576 new_op2 = try_create_Immediate(op2, 0);
577 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
578 build_address(am, op2);
579 new_op1 = be_transform_node(op1);
581 am->op_type = ia32_AddrModeS;
582 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
583 use_am && use_source_address_mode(block, op1, op2)) {
584 build_address(am, op1);
585 if(new_op2 != NULL) {
588 new_op1 = be_transform_node(op2);
592 am->op_type = ia32_AddrModeS;
594 new_op1 = be_transform_node(op1);
596 new_op2 = be_transform_node(op2);
597 am->op_type = ia32_Normal;
599 if(addr->base == NULL)
600 addr->base = noreg_gp;
601 if(addr->index == NULL)
602 addr->index = noreg_gp;
603 if(addr->mem == NULL)
604 addr->mem = new_NoMem();
606 am->new_op1 = new_op1;
607 am->new_op2 = new_op2;
608 am->commutative = commutative;
611 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
613 ir_graph *irg = current_ir_graph;
617 if(am->mem_proj == NULL)
620 /* we have to create a mode_T so the old MemProj can attach to us */
621 mode = get_irn_mode(node);
622 load = get_Proj_pred(am->mem_proj);
624 mark_irn_visited(load);
625 be_set_transformed_node(load, node);
628 set_irn_mode(node, mode_T);
629 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
636 * Construct a standard binary operation, set AM and immediate if required.
638 * @param op1 The first operand
639 * @param op2 The second operand
640 * @param func The node constructor function
641 * @return The constructed ia32 node.
643 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
644 construct_binop_func *func, int commutative)
646 ir_node *src_block = get_nodes_block(node);
647 ir_node *block = be_transform_node(src_block);
648 ir_graph *irg = current_ir_graph;
649 dbg_info *dbgi = get_irn_dbg_info(node);
651 ia32_address_mode_t am;
652 ia32_address_t *addr = &am.addr;
654 match_arguments(&am, src_block, op1, op2, commutative, 0, 1);
656 new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
657 am.new_op2, addr->mem);
658 set_am_attributes(new_node, &am);
659 /* we can't use source address mode anymore when using immediates */
660 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
661 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
662 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
664 new_node = fix_mem_proj(new_node, &am);
670 * Construct a standard binary operation, set AM and immediate if required.
672 * @param op1 The first operand
673 * @param op2 The second operand
674 * @param func The node constructor function
675 * @return The constructed ia32 node.
677 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
678 construct_binop_func *func)
680 ir_node *block = be_transform_node(get_nodes_block(node));
681 ir_node *new_op1 = be_transform_node(op1);
682 ir_node *new_op2 = be_transform_node(op2);
683 ir_node *new_node = NULL;
684 dbg_info *dbgi = get_irn_dbg_info(node);
685 ir_graph *irg = current_ir_graph;
686 ir_mode *mode = get_irn_mode(node);
687 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
688 ir_node *nomem = new_NoMem();
690 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
692 if (is_op_commutative(get_irn_op(node))) {
693 set_ia32_commutative(new_node);
695 set_ia32_ls_mode(new_node, mode);
697 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
702 static ir_node *get_fpcw(void)
705 if(initial_fpcw != NULL)
708 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
709 &ia32_fp_cw_regs[REG_FPCW]);
710 initial_fpcw = be_transform_node(fpcw);
716 * Construct a standard binary operation, set AM and immediate if required.
718 * @param op1 The first operand
719 * @param op2 The second operand
720 * @param func The node constructor function
721 * @return The constructed ia32 node.
723 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
724 construct_binop_float_func *func)
726 ir_node *block = be_transform_node(get_nodes_block(node));
727 ir_node *new_op1 = be_transform_node(op1);
728 ir_node *new_op2 = be_transform_node(op2);
729 ir_node *new_node = NULL;
730 dbg_info *dbgi = get_irn_dbg_info(node);
731 ir_graph *irg = current_ir_graph;
732 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
733 ir_node *nomem = new_NoMem();
735 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
737 if (is_op_commutative(get_irn_op(node))) {
738 set_ia32_commutative(new_node);
741 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
747 * Construct a shift/rotate binary operation, sets AM and immediate if required.
749 * @param op1 The first operand
750 * @param op2 The second operand
751 * @param func The node constructor function
752 * @return The constructed ia32 node.
754 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
755 construct_shift_func *func)
757 dbg_info *dbgi = get_irn_dbg_info(node);
758 ir_graph *irg = current_ir_graph;
759 ir_node *block = get_nodes_block(node);
760 ir_node *new_block = be_transform_node(block);
761 ir_node *new_op1 = be_transform_node(op1);
762 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
765 assert(! mode_is_float(get_irn_mode(node))
766 && "Shift/Rotate with float not supported");
768 res = func(dbgi, irg, new_block, new_op1, new_op2);
769 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
771 /* lowered shift instruction may have a dependency operand, handle it here */
772 if (get_irn_arity(node) == 3) {
773 /* we have a dependency */
774 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
775 add_irn_dep(res, new_dep);
783 * Construct a standard unary operation, set AM and immediate if required.
785 * @param op The operand
786 * @param func The node constructor function
787 * @return The constructed ia32 node.
789 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
791 ir_node *block = be_transform_node(get_nodes_block(node));
792 ir_node *new_op = be_transform_node(op);
793 ir_node *new_node = NULL;
794 ir_graph *irg = current_ir_graph;
795 dbg_info *dbgi = get_irn_dbg_info(node);
797 new_node = func(dbgi, irg, block, new_op);
799 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
804 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
805 ia32_address_t *addr)
807 ir_graph *irg = current_ir_graph;
808 ir_node *base = addr->base;
809 ir_node *index = addr->index;
813 base = ia32_new_NoReg_gp(env_cg);
815 base = be_transform_node(base);
819 index = ia32_new_NoReg_gp(env_cg);
821 index = be_transform_node(index);
824 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
825 set_address(res, addr);
830 static int am_has_immediates(const ia32_address_t *addr)
832 return addr->offset != 0 || addr->symconst_ent != NULL
833 || addr->frame_entity || addr->use_frame;
837 * Creates an ia32 Add.
839 * @return the created ia32 Add node
841 static ir_node *gen_Add(ir_node *node) {
842 ir_node *block = be_transform_node(get_nodes_block(node));
843 ir_node *op1 = get_Add_left(node);
844 ir_node *op2 = get_Add_right(node);
847 ir_graph *irg = current_ir_graph;
848 dbg_info *dbgi = get_irn_dbg_info(node);
849 ir_mode *mode = get_irn_mode(node);
850 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
851 ir_node *src_block = get_nodes_block(node);
852 ir_node *add_immediate_op;
854 ia32_address_mode_t am;
856 if (mode_is_float(mode)) {
857 if (USE_SSE2(env_cg))
858 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
860 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
865 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
866 * 1. Add with immediate -> Lea
867 * 2. Add with possible source address mode -> Add
868 * 3. Otherwise -> Lea
870 memset(&addr, 0, sizeof(addr));
871 ia32_create_address_mode(&addr, node, 1);
872 add_immediate_op = NULL;
874 if(addr.base == NULL && addr.index == NULL) {
875 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
876 addr.symconst_sign, addr.offset);
877 add_irn_dep(new_op, get_irg_frame(irg));
878 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
881 /* add with immediate? */
882 if(addr.index == NULL) {
883 add_immediate_op = addr.base;
884 } else if(addr.base == NULL && addr.scale == 0) {
885 add_immediate_op = addr.index;
888 if(add_immediate_op != NULL) {
889 if(!am_has_immediates(&addr)) {
891 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
894 return be_transform_node(add_immediate_op);
897 new_op = create_lea_from_address(dbgi, block, &addr);
898 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
902 /* test if we can use source address mode */
903 memset(&am, 0, sizeof(am));
905 if(use_source_address_mode(src_block, op2, op1)) {
906 build_address(&am, op2);
907 new_op1 = be_transform_node(op1);
908 } else if(use_source_address_mode(src_block, op1, op2)) {
909 build_address(&am, op1);
910 new_op1 = be_transform_node(op2);
912 /* construct an Add with source address mode */
913 if(new_op1 != NULL) {
914 ia32_address_t *am_addr = &am.addr;
915 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
916 am_addr->index, new_op1, noreg, am_addr->mem);
917 set_address(new_op, am_addr);
918 set_ia32_op_type(new_op, ia32_AddrModeS);
919 set_ia32_ls_mode(new_op, am.ls_mode);
920 set_ia32_commutative(new_op);
921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
923 new_op = fix_mem_proj(new_op, &am);
928 /* otherwise construct a lea */
929 new_op = create_lea_from_address(dbgi, block, &addr);
930 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
935 * Creates an ia32 Mul.
937 * @return the created ia32 Mul node
939 static ir_node *gen_Mul(ir_node *node) {
940 ir_node *op1 = get_Mul_left(node);
941 ir_node *op2 = get_Mul_right(node);
942 ir_mode *mode = get_irn_mode(node);
944 if (mode_is_float(mode)) {
945 if (USE_SSE2(env_cg))
946 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
948 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
952 for the lower 32bit of the result it doesn't matter whether we use
953 signed or unsigned multiplication so we use IMul as it has fewer
956 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
960 * Creates an ia32 Mulh.
961 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
962 * this result while Mul returns the lower 32 bit.
964 * @return the created ia32 Mulh node
966 static ir_node *gen_Mulh(ir_node *node) {
967 ir_node *block = be_transform_node(get_nodes_block(node));
968 ir_node *op1 = get_irn_n(node, 0);
969 ir_node *new_op1 = be_transform_node(op1);
970 ir_node *op2 = get_irn_n(node, 1);
971 ir_node *new_op2 = be_transform_node(op2);
972 ir_graph *irg = current_ir_graph;
973 dbg_info *dbgi = get_irn_dbg_info(node);
974 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
975 ir_mode *mode = get_irn_mode(node);
976 ir_node *proj_EDX, *res;
978 assert(!mode_is_float(mode) && "Mulh with float not supported");
979 if (mode_is_signed(mode)) {
980 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
981 new_op2, new_NoMem());
983 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
987 set_ia32_commutative(res);
989 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
997 * Creates an ia32 And.
999 * @return The created ia32 And node
1001 static ir_node *gen_And(ir_node *node) {
1002 ir_node *op1 = get_And_left(node);
1003 ir_node *op2 = get_And_right(node);
1004 assert(! mode_is_float(get_irn_mode(node)));
1006 /* is it a zero extension? */
1007 if (is_Const(op2)) {
1008 tarval *tv = get_Const_tarval(op2);
1009 long v = get_tarval_long(tv);
1011 if (v == 0xFF || v == 0xFFFF) {
1012 dbg_info *dbgi = get_irn_dbg_info(node);
1013 ir_node *block = be_transform_node(get_nodes_block(node));
1014 ir_node *new_op = be_transform_node(op1);
1021 assert(v == 0xFFFF);
1024 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
1025 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1031 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1037 * Creates an ia32 Or.
1039 * @return The created ia32 Or node
1041 static ir_node *gen_Or(ir_node *node) {
1042 ir_node *op1 = get_Or_left(node);
1043 ir_node *op2 = get_Or_right(node);
1045 assert (! mode_is_float(get_irn_mode(node)));
1046 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1052 * Creates an ia32 Eor.
1054 * @return The created ia32 Eor node
1056 static ir_node *gen_Eor(ir_node *node) {
1057 ir_node *op1 = get_Eor_left(node);
1058 ir_node *op2 = get_Eor_right(node);
1060 assert(! mode_is_float(get_irn_mode(node)));
1061 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1066 * Creates an ia32 Sub.
1068 * @return The created ia32 Sub node
1070 static ir_node *gen_Sub(ir_node *node) {
1071 ir_node *op1 = get_Sub_left(node);
1072 ir_node *op2 = get_Sub_right(node);
1073 ir_mode *mode = get_irn_mode(node);
1075 if (mode_is_float(mode)) {
1076 if (USE_SSE2(env_cg))
1077 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1079 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1083 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1087 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1093 * Generates an ia32 DivMod with additional infrastructure for the
1094 * register allocator if needed.
1096 * @param dividend -no comment- :)
1097 * @param divisor -no comment- :)
1098 * @param dm_flav flavour_Div/Mod/DivMod
1099 * @return The created ia32 DivMod node
1101 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1102 ir_node *divisor, ia32_op_flavour_t dm_flav)
1104 ir_node *block = be_transform_node(get_nodes_block(node));
1105 ir_node *new_dividend = be_transform_node(dividend);
1106 ir_node *new_divisor = be_transform_node(divisor);
1107 ir_graph *irg = current_ir_graph;
1108 dbg_info *dbgi = get_irn_dbg_info(node);
1109 ir_mode *mode = get_irn_mode(node);
1110 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1111 ir_node *res, *proj_div, *proj_mod;
1112 ir_node *sign_extension;
1113 ir_node *mem, *new_mem;
1116 proj_div = proj_mod = NULL;
1120 mem = get_Div_mem(node);
1121 mode = get_Div_resmode(node);
1122 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1123 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1126 mem = get_Mod_mem(node);
1127 mode = get_Mod_resmode(node);
1128 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1129 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1131 case flavour_DivMod:
1132 mem = get_DivMod_mem(node);
1133 mode = get_DivMod_resmode(node);
1134 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1135 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1136 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1139 panic("invalid divmod flavour!");
1141 new_mem = be_transform_node(mem);
1143 if (mode_is_signed(mode)) {
1144 /* in signed mode, we need to sign extend the dividend */
1145 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1146 add_irn_dep(produceval, get_irg_frame(irg));
1147 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1150 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1151 add_irn_dep(sign_extension, get_irg_frame(irg));
1154 if (mode_is_signed(mode)) {
1155 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1156 sign_extension, new_divisor, new_mem, dm_flav);
1158 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1159 sign_extension, new_divisor, new_mem, dm_flav);
1162 set_ia32_exc_label(res, has_exc);
1163 set_irn_pinned(res, get_irn_pinned(node));
1165 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1172 * Wrapper for generate_DivMod. Sets flavour_Mod.
1175 static ir_node *gen_Mod(ir_node *node) {
1176 return generate_DivMod(node, get_Mod_left(node),
1177 get_Mod_right(node), flavour_Mod);
1181 * Wrapper for generate_DivMod. Sets flavour_Div.
1184 static ir_node *gen_Div(ir_node *node) {
1185 return generate_DivMod(node, get_Div_left(node),
1186 get_Div_right(node), flavour_Div);
1190 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1192 static ir_node *gen_DivMod(ir_node *node) {
1193 return generate_DivMod(node, get_DivMod_left(node),
1194 get_DivMod_right(node), flavour_DivMod);
1200 * Creates an ia32 floating Div.
1202 * @return The created ia32 xDiv node
1204 static ir_node *gen_Quot(ir_node *node) {
1205 ir_node *block = be_transform_node(get_nodes_block(node));
1206 ir_node *op1 = get_Quot_left(node);
1207 ir_node *new_op1 = be_transform_node(op1);
1208 ir_node *op2 = get_Quot_right(node);
1209 ir_node *new_op2 = be_transform_node(op2);
1210 ir_graph *irg = current_ir_graph;
1211 dbg_info *dbgi = get_irn_dbg_info(node);
1212 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1213 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1216 if (USE_SSE2(env_cg)) {
1217 ir_mode *mode = get_irn_mode(op1);
1218 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
1220 set_ia32_ls_mode(new_op, mode);
1222 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1223 new_op2, nomem, get_fpcw());
1225 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1231 * Creates an ia32 Shl.
1233 * @return The created ia32 Shl node
1235 static ir_node *gen_Shl(ir_node *node) {
1236 ir_node *right = get_Shl_right(node);
1238 /* test whether we can build a lea */
1239 if(is_Const(right)) {
1240 tarval *tv = get_Const_tarval(right);
1241 if(tarval_is_long(tv)) {
1242 long val = get_tarval_long(tv);
1243 if(val >= 0 && val <= 3) {
1244 ir_graph *irg = current_ir_graph;
1245 dbg_info *dbgi = get_irn_dbg_info(node);
1246 ir_node *block = be_transform_node(get_nodes_block(node));
1247 ir_node *base = ia32_new_NoReg_gp(env_cg);
1248 ir_node *index = be_transform_node(get_Shl_left(node));
1251 = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1252 set_ia32_am_scale(res, val);
1253 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1259 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1266 * Creates an ia32 Shr.
1268 * @return The created ia32 Shr node
1270 static ir_node *gen_Shr(ir_node *node) {
1271 return gen_shift_binop(node, get_Shr_left(node),
1272 get_Shr_right(node), new_rd_ia32_Shr);
1278 * Creates an ia32 Sar.
1280 * @return The created ia32 Shrs node
1282 static ir_node *gen_Shrs(ir_node *node) {
1283 ir_node *left = get_Shrs_left(node);
1284 ir_node *right = get_Shrs_right(node);
1285 ir_mode *mode = get_irn_mode(node);
1286 if(is_Const(right) && mode == mode_Is) {
1287 tarval *tv = get_Const_tarval(right);
1288 long val = get_tarval_long(tv);
1290 /* this is a sign extension */
1291 ir_graph *irg = current_ir_graph;
1292 dbg_info *dbgi = get_irn_dbg_info(node);
1293 ir_node *block = be_transform_node(get_nodes_block(node));
1295 ir_node *new_op = be_transform_node(op);
1296 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1297 add_irn_dep(pval, get_irg_frame(irg));
1299 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1303 /* 8 or 16 bit sign extension? */
1304 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1305 ir_node *shl_left = get_Shl_left(left);
1306 ir_node *shl_right = get_Shl_right(left);
1307 if(is_Const(shl_right)) {
1308 tarval *tv1 = get_Const_tarval(right);
1309 tarval *tv2 = get_Const_tarval(shl_right);
1310 if(tv1 == tv2 && tarval_is_long(tv1)) {
1311 long val = get_tarval_long(tv1);
1312 if(val == 16 || val == 24) {
1313 dbg_info *dbgi = get_irn_dbg_info(node);
1314 ir_node *block = be_transform_node(get_nodes_block(node));
1315 ir_node *new_op = be_transform_node(shl_left);
1325 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1327 SET_IA32_ORIG_NODE(res,
1328 ia32_get_old_node_name(env_cg, node));
1336 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1342 * Creates an ia32 RotL.
1344 * @param op1 The first operator
1345 * @param op2 The second operator
1346 * @return The created ia32 RotL node
1348 static ir_node *gen_RotL(ir_node *node,
1349 ir_node *op1, ir_node *op2) {
1350 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1356 * Creates an ia32 RotR.
1357 * NOTE: There is no RotR with immediate because this would always be a RotL
1358 * "imm-mode_size_bits" which can be pre-calculated.
1360 * @param op1 The first operator
1361 * @param op2 The second operator
1362 * @return The created ia32 RotR node
1364 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1366 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1372 * Creates an ia32 RotR or RotL (depending on the found pattern).
1374 * @return The created ia32 RotL or RotR node
1376 static ir_node *gen_Rot(ir_node *node) {
1377 ir_node *rotate = NULL;
1378 ir_node *op1 = get_Rot_left(node);
1379 ir_node *op2 = get_Rot_right(node);
1381 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1382 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1383 that means we can create a RotR instead of an Add and a RotL */
1385 if (get_irn_op(op2) == op_Add) {
1387 ir_node *left = get_Add_left(add);
1388 ir_node *right = get_Add_right(add);
1389 if (is_Const(right)) {
1390 tarval *tv = get_Const_tarval(right);
1391 ir_mode *mode = get_irn_mode(node);
1392 long bits = get_mode_size_bits(mode);
1394 if (get_irn_op(left) == op_Minus &&
1395 tarval_is_long(tv) &&
1396 get_tarval_long(tv) == bits)
1398 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1399 rotate = gen_RotR(node, op1, get_Minus_op(left));
1404 if (rotate == NULL) {
1405 rotate = gen_RotL(node, op1, op2);
1414 * Transforms a Minus node.
1416 * @param op The Minus operand
1417 * @return The created ia32 Minus node
1419 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1420 ir_node *block = be_transform_node(get_nodes_block(node));
1421 ir_graph *irg = current_ir_graph;
1422 dbg_info *dbgi = get_irn_dbg_info(node);
1423 ir_mode *mode = get_irn_mode(node);
1428 if (mode_is_float(mode)) {
1429 ir_node *new_op = be_transform_node(op);
1430 if (USE_SSE2(env_cg)) {
1431 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1432 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1433 ir_node *nomem = new_rd_NoMem(irg);
1435 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1437 size = get_mode_size_bits(mode);
1438 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1440 set_ia32_am_sc(res, ent);
1441 set_ia32_op_type(res, ia32_AddrModeS);
1442 set_ia32_ls_mode(res, mode);
1444 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1447 res = gen_unop(node, op, new_rd_ia32_Neg);
1450 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1456 * Transforms a Minus node.
1458 * @return The created ia32 Minus node
1460 static ir_node *gen_Minus(ir_node *node) {
1461 return gen_Minus_ex(node, get_Minus_op(node));
1464 static ir_node *create_Immediate_from_int(int val)
1466 ir_graph *irg = current_ir_graph;
1467 ir_node *start_block = get_irg_start_block(irg);
1468 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1469 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1474 static ir_node *gen_bin_Not(ir_node *node)
1476 ir_graph *irg = current_ir_graph;
1477 dbg_info *dbgi = get_irn_dbg_info(node);
1478 ir_node *block = be_transform_node(get_nodes_block(node));
1479 ir_node *op = get_Not_op(node);
1480 ir_node *new_op = be_transform_node(op);
1481 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1482 ir_node *nomem = new_NoMem();
1483 ir_node *one = create_Immediate_from_int(1);
1485 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1489 * Transforms a Not node.
1491 * @return The created ia32 Not node
1493 static ir_node *gen_Not(ir_node *node) {
1494 ir_node *op = get_Not_op(node);
1495 ir_mode *mode = get_irn_mode(node);
1497 if(mode == mode_b) {
1498 return gen_bin_Not(node);
1501 assert (! mode_is_float(get_irn_mode(node)));
1502 return gen_unop(node, op, new_rd_ia32_Not);
1508 * Transforms an Abs node.
1510 * @return The created ia32 Abs node
1512 static ir_node *gen_Abs(ir_node *node) {
1513 ir_node *block = be_transform_node(get_nodes_block(node));
1514 ir_node *op = get_Abs_op(node);
1515 ir_node *new_op = be_transform_node(op);
1516 ir_graph *irg = current_ir_graph;
1517 dbg_info *dbgi = get_irn_dbg_info(node);
1518 ir_mode *mode = get_irn_mode(node);
1519 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1520 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1521 ir_node *nomem = new_NoMem();
1526 if (mode_is_float(mode)) {
1527 if (USE_SSE2(env_cg)) {
1528 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1530 size = get_mode_size_bits(mode);
1531 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1533 set_ia32_am_sc(res, ent);
1535 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1537 set_ia32_op_type(res, ia32_AddrModeS);
1538 set_ia32_ls_mode(res, mode);
1541 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1542 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1546 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1547 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1550 add_irn_dep(pval, get_irg_frame(irg));
1551 SET_IA32_ORIG_NODE(sign_extension,
1552 ia32_get_old_node_name(env_cg, node));
1554 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1555 sign_extension, nomem);
1556 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1558 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1559 sign_extension, nomem);
1560 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1567 * Transforms a Load.
1569 * @return the created ia32 Load node
1571 static ir_node *gen_Load(ir_node *node) {
1572 ir_node *old_block = get_nodes_block(node);
1573 ir_node *block = be_transform_node(old_block);
1574 ir_node *ptr = get_Load_ptr(node);
1575 ir_node *mem = get_Load_mem(node);
1576 ir_node *new_mem = be_transform_node(mem);
1579 ir_graph *irg = current_ir_graph;
1580 dbg_info *dbgi = get_irn_dbg_info(node);
1581 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1582 ir_mode *mode = get_Load_mode(node);
1585 ia32_address_t addr;
1587 /* construct load address */
1588 memset(&addr, 0, sizeof(addr));
1589 ia32_create_address_mode(&addr, ptr, 0);
1596 base = be_transform_node(base);
1602 index = be_transform_node(index);
1605 if (mode_is_float(mode)) {
1606 if (USE_SSE2(env_cg)) {
1607 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1609 res_mode = mode_xmm;
1611 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1613 res_mode = mode_vfp;
1619 /* create a conv node with address mode for smaller modes */
1620 if(get_mode_size_bits(mode) < 32) {
1621 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
1624 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1629 set_irn_pinned(new_op, get_irn_pinned(node));
1630 set_ia32_op_type(new_op, ia32_AddrModeS);
1631 set_ia32_ls_mode(new_op, mode);
1632 set_address(new_op, &addr);
1634 /* make sure we are scheduled behind the initial IncSP/Barrier
1635 * to avoid spills being placed before it
1637 if (block == get_irg_start_block(irg)) {
1638 add_irn_dep(new_op, get_irg_frame(irg));
1641 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1642 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1647 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1648 ir_node *ptr, ir_mode *mode, ir_node *other)
1655 /* we only use address mode if we're the only user of the load */
1656 if(get_irn_n_edges(node) > 1)
1659 load = get_Proj_pred(node);
1662 if(get_nodes_block(load) != block)
1665 /* Store should be attached to the load */
1666 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1668 /* store should have the same pointer as the load */
1669 if(get_Load_ptr(load) != ptr)
1672 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1673 if(other != NULL && get_nodes_block(other) == block
1674 && heights_reachable_in_block(heights, other, load))
1677 assert(get_Load_mode(load) == mode);
1682 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1683 ir_node *mem, ir_node *ptr, ir_mode *mode,
1684 construct_binop_dest_func *func, int commutative)
1686 ir_node *src_block = get_nodes_block(node);
1688 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1689 ir_graph *irg = current_ir_graph;
1693 ia32_address_mode_t am;
1694 ia32_address_t *addr = &am.addr;
1695 memset(&am, 0, sizeof(am));
1697 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1698 build_address(&am, op1);
1699 new_op = create_immediate_or_transform(op2, 0);
1700 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1701 build_address(&am, op2);
1702 new_op = create_immediate_or_transform(op1, 0);
1707 if(addr->base == NULL)
1708 addr->base = noreg_gp;
1709 if(addr->index == NULL)
1710 addr->index = noreg_gp;
1711 if(addr->mem == NULL)
1712 addr->mem = new_NoMem();
1714 dbgi = get_irn_dbg_info(node);
1715 block = be_transform_node(src_block);
1716 new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
1718 set_address(new_node, addr);
1719 set_ia32_op_type(new_node, ia32_AddrModeD);
1720 set_ia32_ls_mode(new_node, mode);
1721 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1726 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1727 ir_node *ptr, ir_mode *mode,
1728 construct_unop_dest_func *func)
1730 ir_node *src_block = get_nodes_block(node);
1732 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1733 ir_graph *irg = current_ir_graph;
1736 ia32_address_mode_t am;
1737 ia32_address_t *addr = &am.addr;
1738 memset(&am, 0, sizeof(am));
1740 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1743 build_address(&am, op);
1745 if(addr->base == NULL)
1746 addr->base = noreg_gp;
1747 if(addr->index == NULL)
1748 addr->index = noreg_gp;
1749 if(addr->mem == NULL)
1750 addr->mem = new_NoMem();
1752 dbgi = get_irn_dbg_info(node);
1753 block = be_transform_node(src_block);
1754 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1755 set_address(new_node, addr);
1756 set_ia32_op_type(new_node, ia32_AddrModeD);
1757 set_ia32_ls_mode(new_node, mode);
1758 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1763 static ir_node *try_create_dest_am(ir_node *node) {
1764 ir_node *val = get_Store_value(node);
1765 ir_node *mem = get_Store_mem(node);
1766 ir_node *ptr = get_Store_ptr(node);
1767 ir_mode *mode = get_irn_mode(val);
1772 /* handle only GP modes for now... */
1773 if(!mode_needs_gp_reg(mode))
1775 if(get_mode_size_bits(mode) != 32)
1778 /* store must be the only user of the val node */
1779 if(get_irn_n_edges(val) > 1)
1782 switch(get_irn_opcode(val)) {
1784 op1 = get_Add_left(val);
1785 op2 = get_Add_right(val);
1786 if(is_Const_1(op2)) {
1787 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1788 new_rd_ia32_IncMem);
1790 } else if(is_Const_Minus_1(op2)) {
1791 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1792 new_rd_ia32_DecMem);
1795 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1796 new_rd_ia32_AddMem, 1);
1799 op1 = get_Sub_left(val);
1800 op2 = get_Sub_right(val);
1801 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1802 new_rd_ia32_SubMem, 0);
1805 op1 = get_And_left(val);
1806 op2 = get_And_right(val);
1807 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1808 new_rd_ia32_AndMem, 1);
1811 op1 = get_Or_left(val);
1812 op2 = get_Or_right(val);
1813 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1814 new_rd_ia32_OrMem, 1);
1817 op1 = get_Eor_left(val);
1818 op2 = get_Eor_right(val);
1819 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1820 new_rd_ia32_XorMem, 1);
1823 op1 = get_Shl_left(val);
1824 op2 = get_Shl_right(val);
1825 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1826 new_rd_ia32_ShlMem, 0);
1829 op1 = get_Shr_left(val);
1830 op2 = get_Shr_right(val);
1831 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1832 new_rd_ia32_ShrMem, 0);
1835 op1 = get_Shrs_left(val);
1836 op2 = get_Shrs_right(val);
1837 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1838 new_rd_ia32_SarMem, 0);
1841 op1 = get_Rot_left(val);
1842 op2 = get_Rot_right(val);
1843 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1844 new_rd_ia32_RolMem, 0);
1846 /* TODO: match ROR patterns... */
1848 op1 = get_Minus_op(val);
1849 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1852 /* TODO this would be ^ 1 with DestAM */
1855 op1 = get_Not_op(val);
1856 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1866 * Transforms a Store.
1868 * @return the created ia32 Store node
1870 static ir_node *gen_Store(ir_node *node) {
1871 ir_node *block = be_transform_node(get_nodes_block(node));
1872 ir_node *ptr = get_Store_ptr(node);
1875 ir_node *val = get_Store_value(node);
1877 ir_node *mem = get_Store_mem(node);
1878 ir_node *new_mem = be_transform_node(mem);
1879 ir_graph *irg = current_ir_graph;
1880 dbg_info *dbgi = get_irn_dbg_info(node);
1881 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1882 ir_mode *mode = get_irn_mode(val);
1884 ia32_address_t addr;
1886 /* check for destination address mode */
1887 new_op = try_create_dest_am(node);
1891 /* construct store address */
1892 memset(&addr, 0, sizeof(addr));
1893 ia32_create_address_mode(&addr, ptr, 0);
1900 base = be_transform_node(base);
1906 index = be_transform_node(index);
1909 if (mode_is_float(mode)) {
1910 new_val = be_transform_node(val);
1911 if (USE_SSE2(env_cg)) {
1912 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
1915 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
1919 new_val = create_immediate_or_transform(val, 0);
1923 if (get_mode_size_bits(mode) == 8) {
1924 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
1927 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
1932 set_irn_pinned(new_op, get_irn_pinned(node));
1933 set_ia32_op_type(new_op, ia32_AddrModeD);
1934 set_ia32_ls_mode(new_op, mode);
1936 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1937 set_address(new_op, &addr);
1938 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1943 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1944 ir_node *cmp_left, ir_node *cmp_right,
1951 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1952 ia32_address_mode_t am;
1953 ia32_address_t *addr = &am.addr;
1955 if(cmp_right != NULL && !is_Const_0(cmp_right))
1958 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1959 mode = get_irn_mode(cmp_left);
1960 arg_left = get_And_left(cmp_left);
1961 arg_right = get_And_right(cmp_left);
1963 mode = get_irn_mode(cmp_left);
1964 arg_left = cmp_left;
1965 arg_right = cmp_left;
1971 assert(get_mode_size_bits(mode) <= 32);
1972 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
1974 pnc = get_inversed_pnc(pnc);
1976 if(get_mode_size_bits(mode) == 8) {
1977 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1978 addr->index, am.new_op1, am.new_op2,
1981 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1982 addr->index, am.new_op1, am.new_op2,
1985 set_am_attributes(res, &am);
1986 set_ia32_ls_mode(res, mode);
1988 res = fix_mem_proj(res, &am);
1993 static ir_node *create_Switch(ir_node *node)
1995 ir_graph *irg = current_ir_graph;
1996 dbg_info *dbgi = get_irn_dbg_info(node);
1997 ir_node *block = be_transform_node(get_nodes_block(node));
1998 ir_node *sel = get_Cond_selector(node);
1999 ir_node *new_sel = be_transform_node(sel);
2001 int switch_min = INT_MAX;
2002 const ir_edge_t *edge;
2004 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2006 /* determine the smallest switch case value */
2007 foreach_out_edge(node, edge) {
2008 ir_node *proj = get_edge_src_irn(edge);
2009 int pn = get_Proj_proj(proj);
2014 if (switch_min != 0) {
2015 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2017 /* if smallest switch case is not 0 we need an additional sub */
2018 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2019 add_ia32_am_offs_int(new_sel, -switch_min);
2020 set_ia32_op_type(new_sel, ia32_AddrModeS);
2022 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2025 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2026 set_ia32_pncode(res, get_Cond_defaultProj(node));
2028 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2034 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2036 * @return The transformed node.
2038 static ir_node *gen_Cond(ir_node *node) {
2039 ir_node *src_block = get_nodes_block(node);
2040 ir_node *block = be_transform_node(src_block);
2041 ir_graph *irg = current_ir_graph;
2042 dbg_info *dbgi = get_irn_dbg_info(node);
2043 ir_node *sel = get_Cond_selector(node);
2044 ir_mode *sel_mode = get_irn_mode(sel);
2045 ir_node *res = NULL;
2046 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2047 ir_node *nomem = new_NoMem();
2057 if (sel_mode != mode_b) {
2058 return create_Switch(node);
2061 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2062 /* it's some mode_b value but not a direct comparison -> create a
2064 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2065 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2069 /* address mode makes only sense when we're the only user of the cmp */
2070 use_am = get_irn_n_edges(node) <= 1;
2072 cmp = get_Proj_pred(sel);
2073 cmp_a = get_Cmp_left(cmp);
2074 cmp_b = get_Cmp_right(cmp);
2075 cmp_mode = get_irn_mode(cmp_a);
2076 pnc = get_Proj_proj(sel);
2077 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2078 pnc |= ia32_pn_Cmp_Unsigned;
2081 if(mode_needs_gp_reg(cmp_mode)) {
2082 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2084 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2089 if (mode_is_float(cmp_mode)) {
2090 new_cmp_a = be_transform_node(cmp_a);
2091 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2092 if (USE_SSE2(env_cg)) {
2093 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
2095 set_ia32_commutative(res);
2096 set_ia32_ls_mode(res, cmp_mode);
2098 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2099 set_ia32_commutative(res);
2102 ia32_address_mode_t am;
2103 ia32_address_t *addr = &am.addr;
2104 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am);
2106 pnc = get_inversed_pnc(pnc);
2108 if(get_mode_size_bits(cmp_mode) == 8) {
2109 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
2110 addr->index, am.new_op1, am.new_op2,
2113 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2114 am.new_op1, am.new_op2, addr->mem, pnc);
2116 set_am_attributes(res, &am);
2117 assert(cmp_mode != NULL);
2118 set_ia32_ls_mode(res, cmp_mode);
2120 res = fix_mem_proj(res, &am);
2123 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2131 * Transforms a CopyB node.
2133 * @return The transformed node.
2135 static ir_node *gen_CopyB(ir_node *node) {
2136 ir_node *block = be_transform_node(get_nodes_block(node));
2137 ir_node *src = get_CopyB_src(node);
2138 ir_node *new_src = be_transform_node(src);
2139 ir_node *dst = get_CopyB_dst(node);
2140 ir_node *new_dst = be_transform_node(dst);
2141 ir_node *mem = get_CopyB_mem(node);
2142 ir_node *new_mem = be_transform_node(mem);
2143 ir_node *res = NULL;
2144 ir_graph *irg = current_ir_graph;
2145 dbg_info *dbgi = get_irn_dbg_info(node);
2146 int size = get_type_size_bytes(get_CopyB_type(node));
2149 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2150 /* then we need the size explicitly in ECX. */
2151 if (size >= 32 * 4) {
2152 rem = size & 0x3; /* size % 4 */
2155 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2156 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2158 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2159 /* we misuse the pncode field for the copyb size */
2160 set_ia32_pncode(res, rem);
2162 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2163 set_ia32_pncode(res, size);
2166 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2172 ir_node *gen_be_Copy(ir_node *node)
2174 ir_node *result = be_duplicate_node(node);
2175 ir_mode *mode = get_irn_mode(result);
2177 if (mode_needs_gp_reg(mode)) {
2178 set_irn_mode(result, mode_Iu);
2185 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2186 dbg_info *dbgi, ir_node *block, int use_am)
2188 ir_graph *irg = current_ir_graph;
2189 ir_node *new_block = be_transform_node(block);
2190 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2191 ir_node *nomem = new_rd_NoMem(irg);
2196 ia32_address_mode_t am;
2197 ia32_address_t *addr = &am.addr;
2199 /* can we use a test instruction? */
2200 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2201 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2202 if(is_And(cmp_left) &&
2203 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2204 ir_node *and_left = get_And_left(cmp_left);
2205 ir_node *and_right = get_And_right(cmp_left);
2207 mode = get_irn_mode(and_left);
2208 arg_left = and_left;
2209 arg_right = and_right;
2211 mode = get_irn_mode(cmp_left);
2212 arg_left = cmp_left;
2213 arg_right = cmp_left;
2216 assert(get_mode_size_bits(mode) <= 32);
2218 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
2220 pnc = get_inversed_pnc(pnc);
2222 if(get_mode_size_bits(mode) == 8) {
2223 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2224 addr->index, am.new_op1, am.new_op2,
2227 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
2228 addr->index, am.new_op1, am.new_op2,
2231 set_am_attributes(res, &am);
2232 set_ia32_ls_mode(res, mode);
2234 res = fix_mem_proj(res, &am);
2236 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2242 mode = get_irn_mode(cmp_left);
2243 assert(get_mode_size_bits(mode) <= 32);
2245 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am);
2247 pnc = get_inversed_pnc(pnc);
2249 if(get_mode_size_bits(mode) == 8) {
2250 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
2251 addr->index, am.new_op1, am.new_op2,
2254 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2255 am.new_op1, am.new_op2, addr->mem, pnc);
2257 set_am_attributes(res, &am);
2258 set_ia32_ls_mode(res, mode);
2260 res = fix_mem_proj(res, &am);
2262 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2268 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2269 ir_node *val_true, ir_node *val_false,
2270 dbg_info *dbgi, ir_node *block)
2272 ir_graph *irg = current_ir_graph;
2273 ir_node *new_block = be_transform_node(block);
2274 ir_node *new_val_true = be_transform_node(val_true);
2275 ir_node *new_val_false = be_transform_node(val_false);
2276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2277 ir_node *nomem = new_NoMem();
2278 ir_node *new_cmp_left;
2279 ir_node *new_cmp_right;
2283 /* cmovs with unknowns are pointless... */
2284 if(is_Unknown(val_true)) {
2285 #ifdef DEBUG_libfirm
2286 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2288 return new_val_false;
2290 if(is_Unknown(val_false)) {
2291 #ifdef DEBUG_libfirm
2292 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2294 return new_val_true;
2297 /* can we use a test instruction? */
2298 if(is_Const_0(cmp_right)) {
2299 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2300 if(is_And(cmp_left) &&
2301 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2302 ir_node *and_left = get_And_left(cmp_left);
2303 ir_node *and_right = get_And_right(cmp_left);
2305 mode = get_irn_mode(and_left);
2306 new_cmp_left = be_transform_node(and_left);
2307 new_cmp_right = create_immediate_or_transform(and_right, 0);
2309 mode = get_irn_mode(cmp_left);
2310 new_cmp_left = be_transform_node(cmp_left);
2311 new_cmp_right = be_transform_node(cmp_left);
2314 assert(get_mode_size_bits(mode) <= 32);
2316 if(get_mode_size_bits(mode) == 8) {
2317 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
2318 noreg, noreg, new_cmp_left,
2319 new_cmp_right, nomem, new_val_true,
2320 new_val_false, pnc);
2322 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2323 noreg, new_cmp_left, new_cmp_right,
2324 nomem, new_val_true, new_val_false, pnc);
2326 set_ia32_ls_mode(res, mode);
2331 mode = get_irn_mode(cmp_left);
2332 new_cmp_left = be_transform_node(cmp_left);
2333 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2335 /* no support for 8,16 bit modes yet */
2336 assert(get_mode_size_bits(mode) <= 32);
2338 if(get_mode_size_bits(mode) == 8) {
2339 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
2340 new_cmp_left, new_cmp_right, nomem,
2341 new_val_true, new_val_false, pnc);
2343 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
2344 new_cmp_left, new_cmp_right, nomem,
2345 new_val_true, new_val_false, pnc);
2347 set_ia32_ls_mode(res, mode);
2354 * Transforms a Psi node into CMov.
2356 * @return The transformed node.
2358 static ir_node *gen_Psi(ir_node *node) {
2359 ir_node *psi_true = get_Psi_val(node, 0);
2360 ir_node *psi_default = get_Psi_default(node);
2361 ia32_code_gen_t *cg = env_cg;
2362 ir_node *cond = get_Psi_cond(node, 0);
2363 ir_node *block = get_nodes_block(node);
2364 dbg_info *dbgi = get_irn_dbg_info(node);
2371 assert(get_Psi_n_conds(node) == 1);
2372 assert(get_irn_mode(cond) == mode_b);
2373 assert(mode_needs_gp_reg(get_irn_mode(node)));
2375 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2376 /* a mode_b value, we have to compare it against 0 */
2378 cmp_right = new_Const_long(mode_Iu, 0);
2382 ir_node *cmp = get_Proj_pred(cond);
2384 cmp_left = get_Cmp_left(cmp);
2385 cmp_right = get_Cmp_right(cmp);
2386 cmp_mode = get_irn_mode(cmp_left);
2387 pnc = get_Proj_proj(cond);
2389 assert(!mode_is_float(cmp_mode));
2391 if (!mode_is_signed(cmp_mode)) {
2392 pnc |= ia32_pn_Cmp_Unsigned;
2396 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2397 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2398 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2399 pnc = get_negated_pnc(pnc, cmp_mode);
2400 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2402 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2405 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2411 * Create a conversion from x87 state register to general purpose.
2413 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2414 ir_node *block = be_transform_node(get_nodes_block(node));
2415 ir_node *op = get_Conv_op(node);
2416 ir_node *new_op = be_transform_node(op);
2417 ia32_code_gen_t *cg = env_cg;
2418 ir_graph *irg = current_ir_graph;
2419 dbg_info *dbgi = get_irn_dbg_info(node);
2420 ir_node *noreg = ia32_new_NoReg_gp(cg);
2421 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2422 ir_mode *mode = get_irn_mode(node);
2423 ir_node *fist, *load;
2426 fist = new_rd_ia32_vfist(dbgi, irg, block,
2427 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2429 set_irn_pinned(fist, op_pin_state_floats);
2430 set_ia32_use_frame(fist);
2431 set_ia32_op_type(fist, ia32_AddrModeD);
2433 assert(get_mode_size_bits(mode) <= 32);
2434 /* exception we can only store signed 32 bit integers, so for unsigned
2435 we store a 64bit (signed) integer and load the lower bits */
2436 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2437 set_ia32_ls_mode(fist, mode_Ls);
2439 set_ia32_ls_mode(fist, mode_Is);
2441 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2444 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2446 set_irn_pinned(load, op_pin_state_floats);
2447 set_ia32_use_frame(load);
2448 set_ia32_op_type(load, ia32_AddrModeS);
2449 set_ia32_ls_mode(load, mode_Is);
2450 if(get_ia32_ls_mode(fist) == mode_Ls) {
2451 ia32_attr_t *attr = get_ia32_attr(load);
2452 attr->data.need_64bit_stackent = 1;
2454 ia32_attr_t *attr = get_ia32_attr(load);
2455 attr->data.need_32bit_stackent = 1;
2457 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2459 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2463 * Creates a x87 strict Conv by placing a Sore and a Load
2465 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2467 ir_node *block = get_nodes_block(node);
2468 ir_graph *irg = current_ir_graph;
2469 dbg_info *dbgi = get_irn_dbg_info(node);
2470 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2471 ir_node *nomem = new_NoMem();
2472 ir_node *frame = get_irg_frame(irg);
2473 ir_node *store, *load;
2476 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2478 set_ia32_use_frame(store);
2479 set_ia32_op_type(store, ia32_AddrModeD);
2480 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2482 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2484 set_ia32_use_frame(load);
2485 set_ia32_op_type(load, ia32_AddrModeS);
2486 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2488 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2493 * Create a conversion from general purpose to x87 register
2495 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2496 ir_node *block = be_transform_node(get_nodes_block(node));
2497 ir_node *op = get_Conv_op(node);
2498 ir_node *new_op = be_transform_node(op);
2499 ir_graph *irg = current_ir_graph;
2500 dbg_info *dbgi = get_irn_dbg_info(node);
2501 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2502 ir_node *nomem = new_NoMem();
2503 ir_mode *mode = get_irn_mode(op);
2504 ir_mode *store_mode;
2505 ir_node *fild, *store;
2509 /* first convert to 32 bit signed if necessary */
2510 src_bits = get_mode_size_bits(src_mode);
2511 if (src_bits == 8) {
2512 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2514 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2516 } else if (src_bits < 32) {
2517 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2522 assert(get_mode_size_bits(mode) == 32);
2525 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2527 set_ia32_use_frame(store);
2528 set_ia32_op_type(store, ia32_AddrModeD);
2529 set_ia32_ls_mode(store, mode_Iu);
2531 /* exception for 32bit unsigned, do a 64bit spill+load */
2532 if(!mode_is_signed(mode)) {
2535 ir_node *zero_const = create_Immediate_from_int(0);
2537 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2540 set_ia32_use_frame(zero_store);
2541 set_ia32_op_type(zero_store, ia32_AddrModeD);
2542 add_ia32_am_offs_int(zero_store, 4);
2543 set_ia32_ls_mode(zero_store, mode_Iu);
2548 store = new_rd_Sync(dbgi, irg, block, 2, in);
2549 store_mode = mode_Ls;
2551 store_mode = mode_Is;
2555 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2557 set_ia32_use_frame(fild);
2558 set_ia32_op_type(fild, ia32_AddrModeS);
2559 set_ia32_ls_mode(fild, store_mode);
2561 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2567 * Crete a conversion from one integer mode into another one
2569 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2570 dbg_info *dbgi, ir_node *new_block,
2573 ir_graph *irg = current_ir_graph;
2574 int src_bits = get_mode_size_bits(src_mode);
2575 int tgt_bits = get_mode_size_bits(tgt_mode);
2576 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2577 ir_node *nomem = new_rd_NoMem(irg);
2579 ir_mode *smaller_mode;
2582 if (src_bits < tgt_bits) {
2583 smaller_mode = src_mode;
2584 smaller_bits = src_bits;
2586 smaller_mode = tgt_mode;
2587 smaller_bits = tgt_bits;
2590 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2591 if (smaller_bits == 8) {
2592 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2593 new_op, nomem, smaller_mode);
2595 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2596 nomem, smaller_mode);
2603 * Transforms a Conv node.
2605 * @return The created ia32 Conv node
2607 static ir_node *gen_Conv(ir_node *node) {
2608 ir_node *block = be_transform_node(get_nodes_block(node));
2609 ir_node *op = get_Conv_op(node);
2610 ir_node *new_op = be_transform_node(op);
2611 ir_graph *irg = current_ir_graph;
2612 dbg_info *dbgi = get_irn_dbg_info(node);
2613 ir_mode *src_mode = get_irn_mode(op);
2614 ir_mode *tgt_mode = get_irn_mode(node);
2615 int src_bits = get_mode_size_bits(src_mode);
2616 int tgt_bits = get_mode_size_bits(tgt_mode);
2617 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2618 ir_node *nomem = new_rd_NoMem(irg);
2621 if (src_mode == mode_b) {
2622 assert(mode_is_int(tgt_mode));
2623 /* nothing to do, we already model bools as 0/1 ints */
2627 if (src_mode == tgt_mode) {
2628 if (get_Conv_strict(node)) {
2629 if (USE_SSE2(env_cg)) {
2630 /* when we are in SSE mode, we can kill all strict no-op conversion */
2634 /* this should be optimized already, but who knows... */
2635 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2636 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2641 if (mode_is_float(src_mode)) {
2642 /* we convert from float ... */
2643 if (mode_is_float(tgt_mode)) {
2644 if(src_mode == mode_E && tgt_mode == mode_D
2645 && !get_Conv_strict(node)) {
2646 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2651 if (USE_SSE2(env_cg)) {
2652 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2653 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2654 set_ia32_ls_mode(res, tgt_mode);
2656 if(get_Conv_strict(node)) {
2657 res = gen_x87_strict_conv(tgt_mode, new_op);
2658 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2661 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2666 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2667 if (USE_SSE2(env_cg)) {
2668 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2669 set_ia32_ls_mode(res, src_mode);
2671 return gen_x87_fp_to_gp(node);
2675 /* we convert from int ... */
2676 if (mode_is_float(tgt_mode)) {
2678 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2679 if (USE_SSE2(env_cg)) {
2680 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2681 set_ia32_ls_mode(res, tgt_mode);
2683 res = gen_x87_gp_to_fp(node, src_mode);
2684 if(get_Conv_strict(node)) {
2685 res = gen_x87_strict_conv(tgt_mode, res);
2686 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2687 ia32_get_old_node_name(env_cg, node));
2691 } else if(tgt_mode == mode_b) {
2692 /* mode_b lowering already took care that we only have 0/1 values */
2693 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2694 src_mode, tgt_mode));
2698 if (src_bits == tgt_bits) {
2699 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2700 src_mode, tgt_mode));
2704 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2708 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2714 int check_immediate_constraint(long val, char immediate_constraint_type)
2716 switch (immediate_constraint_type) {
2720 return val >= 0 && val <= 32;
2722 return val >= 0 && val <= 63;
2724 return val >= -128 && val <= 127;
2726 return val == 0xff || val == 0xffff;
2728 return val >= 0 && val <= 3;
2730 return val >= 0 && val <= 255;
2732 return val >= 0 && val <= 127;
2736 panic("Invalid immediate constraint found");
2741 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2744 tarval *offset = NULL;
2745 int offset_sign = 0;
2747 ir_entity *symconst_ent = NULL;
2748 int symconst_sign = 0;
2750 ir_node *cnst = NULL;
2751 ir_node *symconst = NULL;
2757 mode = get_irn_mode(node);
2758 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2762 if(is_Minus(node)) {
2764 node = get_Minus_op(node);
2767 if(is_Const(node)) {
2770 offset_sign = minus;
2771 } else if(is_SymConst(node)) {
2774 symconst_sign = minus;
2775 } else if(is_Add(node)) {
2776 ir_node *left = get_Add_left(node);
2777 ir_node *right = get_Add_right(node);
2778 if(is_Const(left) && is_SymConst(right)) {
2781 symconst_sign = minus;
2782 offset_sign = minus;
2783 } else if(is_SymConst(left) && is_Const(right)) {
2786 symconst_sign = minus;
2787 offset_sign = minus;
2789 } else if(is_Sub(node)) {
2790 ir_node *left = get_Sub_left(node);
2791 ir_node *right = get_Sub_right(node);
2792 if(is_Const(left) && is_SymConst(right)) {
2795 symconst_sign = !minus;
2796 offset_sign = minus;
2797 } else if(is_SymConst(left) && is_Const(right)) {
2800 symconst_sign = minus;
2801 offset_sign = !minus;
2808 offset = get_Const_tarval(cnst);
2809 if(tarval_is_long(offset)) {
2810 val = get_tarval_long(offset);
2811 } else if(tarval_is_null(offset)) {
2814 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2819 if(!check_immediate_constraint(val, immediate_constraint_type))
2822 if(symconst != NULL) {
2823 if(immediate_constraint_type != 0) {
2824 /* we need full 32bits for symconsts */
2828 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2830 symconst_ent = get_SymConst_entity(symconst);
2832 if(cnst == NULL && symconst == NULL)
2835 if(offset_sign && offset != NULL) {
2836 offset = tarval_neg(offset);
2839 irg = current_ir_graph;
2840 dbgi = get_irn_dbg_info(node);
2841 block = get_irg_start_block(irg);
2842 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2843 symconst_sign, val);
2844 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2850 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2852 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2853 if (new_node == NULL) {
2854 new_node = be_transform_node(node);
2859 typedef struct constraint_t constraint_t;
2860 struct constraint_t {
2863 const arch_register_req_t **out_reqs;
2865 const arch_register_req_t *req;
2866 unsigned immediate_possible;
2867 char immediate_type;
2870 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2872 int immediate_possible = 0;
2873 char immediate_type = 0;
2874 unsigned limited = 0;
2875 const arch_register_class_t *cls = NULL;
2876 ir_graph *irg = current_ir_graph;
2877 struct obstack *obst = get_irg_obstack(irg);
2878 arch_register_req_t *req;
2879 unsigned *limited_ptr;
2883 /* TODO: replace all the asserts with nice error messages */
2885 printf("Constraint: %s\n", c);
2895 assert(cls == NULL ||
2896 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2897 cls = &ia32_reg_classes[CLASS_ia32_gp];
2898 limited |= 1 << REG_EAX;
2901 assert(cls == NULL ||
2902 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2903 cls = &ia32_reg_classes[CLASS_ia32_gp];
2904 limited |= 1 << REG_EBX;
2907 assert(cls == NULL ||
2908 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2909 cls = &ia32_reg_classes[CLASS_ia32_gp];
2910 limited |= 1 << REG_ECX;
2913 assert(cls == NULL ||
2914 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2915 cls = &ia32_reg_classes[CLASS_ia32_gp];
2916 limited |= 1 << REG_EDX;
2919 assert(cls == NULL ||
2920 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2921 cls = &ia32_reg_classes[CLASS_ia32_gp];
2922 limited |= 1 << REG_EDI;
2925 assert(cls == NULL ||
2926 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2927 cls = &ia32_reg_classes[CLASS_ia32_gp];
2928 limited |= 1 << REG_ESI;
2931 case 'q': /* q means lower part of the regs only, this makes no
2932 * difference to Q for us (we only assigne whole registers) */
2933 assert(cls == NULL ||
2934 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2935 cls = &ia32_reg_classes[CLASS_ia32_gp];
2936 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2940 assert(cls == NULL ||
2941 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2942 cls = &ia32_reg_classes[CLASS_ia32_gp];
2943 limited |= 1 << REG_EAX | 1 << REG_EDX;
2946 assert(cls == NULL ||
2947 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2948 cls = &ia32_reg_classes[CLASS_ia32_gp];
2949 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2950 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2957 assert(cls == NULL);
2958 cls = &ia32_reg_classes[CLASS_ia32_gp];
2964 /* TODO: mark values so the x87 simulator knows about t and u */
2965 assert(cls == NULL);
2966 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2971 assert(cls == NULL);
2972 /* TODO: check that sse2 is supported */
2973 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2983 assert(!immediate_possible);
2984 immediate_possible = 1;
2985 immediate_type = *c;
2989 assert(!immediate_possible);
2990 immediate_possible = 1;
2994 assert(!immediate_possible && cls == NULL);
2995 immediate_possible = 1;
2996 cls = &ia32_reg_classes[CLASS_ia32_gp];
3009 assert(constraint->is_in && "can only specify same constraint "
3012 sscanf(c, "%d%n", &same_as, &p);
3019 case 'E': /* no float consts yet */
3020 case 'F': /* no float consts yet */
3021 case 's': /* makes no sense on x86 */
3022 case 'X': /* we can't support that in firm */
3026 case '<': /* no autodecrement on x86 */
3027 case '>': /* no autoincrement on x86 */
3028 case 'C': /* sse constant not supported yet */
3029 case 'G': /* 80387 constant not supported yet */
3030 case 'y': /* we don't support mmx registers yet */
3031 case 'Z': /* not available in 32 bit mode */
3032 case 'e': /* not available in 32 bit mode */
3033 assert(0 && "asm constraint not supported");
3036 assert(0 && "unknown asm constraint found");
3043 const arch_register_req_t *other_constr;
3045 assert(cls == NULL && "same as and register constraint not supported");
3046 assert(!immediate_possible && "same as and immediate constraint not "
3048 assert(same_as < constraint->n_outs && "wrong constraint number in "
3049 "same_as constraint");
3051 other_constr = constraint->out_reqs[same_as];
3053 req = obstack_alloc(obst, sizeof(req[0]));
3054 req->cls = other_constr->cls;
3055 req->type = arch_register_req_type_should_be_same;
3056 req->limited = NULL;
3057 req->other_same = pos;
3058 req->other_different = -1;
3060 /* switch constraints. This is because in firm we have same_as
3061 * constraints on the output constraints while in the gcc asm syntax
3062 * they are specified on the input constraints */
3063 constraint->req = other_constr;
3064 constraint->out_reqs[same_as] = req;
3065 constraint->immediate_possible = 0;
3069 if(immediate_possible && cls == NULL) {
3070 cls = &ia32_reg_classes[CLASS_ia32_gp];
3072 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3073 assert(cls != NULL);
3075 if(immediate_possible) {
3076 assert(constraint->is_in
3077 && "imeediates make no sense for output constraints");
3079 /* todo: check types (no float input on 'r' constrained in and such... */
3082 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3083 limited_ptr = (unsigned*) (req+1);
3085 req = obstack_alloc(obst, sizeof(req[0]));
3087 memset(req, 0, sizeof(req[0]));
3090 req->type = arch_register_req_type_limited;
3091 *limited_ptr = limited;
3092 req->limited = limited_ptr;
3094 req->type = arch_register_req_type_normal;
3098 constraint->req = req;
3099 constraint->immediate_possible = immediate_possible;
3100 constraint->immediate_type = immediate_type;
3104 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3111 panic("Clobbers not supported yet");
3115 * generates code for a ASM node
3117 static ir_node *gen_ASM(ir_node *node)
3120 ir_graph *irg = current_ir_graph;
3121 ir_node *block = be_transform_node(get_nodes_block(node));
3122 dbg_info *dbgi = get_irn_dbg_info(node);
3129 ia32_asm_attr_t *attr;
3130 const arch_register_req_t **out_reqs;
3131 const arch_register_req_t **in_reqs;
3132 struct obstack *obst;
3133 constraint_t parsed_constraint;
3135 /* transform inputs */
3136 arity = get_irn_arity(node);
3137 in = alloca(arity * sizeof(in[0]));
3138 memset(in, 0, arity * sizeof(in[0]));
3140 n_outs = get_ASM_n_output_constraints(node);
3141 n_clobbers = get_ASM_n_clobbers(node);
3142 out_arity = n_outs + n_clobbers;
3144 /* construct register constraints */
3145 obst = get_irg_obstack(irg);
3146 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3147 parsed_constraint.out_reqs = out_reqs;
3148 parsed_constraint.n_outs = n_outs;
3149 parsed_constraint.is_in = 0;
3150 for(i = 0; i < out_arity; ++i) {
3154 const ir_asm_constraint *constraint;
3155 constraint = & get_ASM_output_constraints(node) [i];
3156 c = get_id_str(constraint->constraint);
3157 parse_asm_constraint(i, &parsed_constraint, c);
3159 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3160 c = get_id_str(glob_id);
3161 parse_clobber(node, i, &parsed_constraint, c);
3163 out_reqs[i] = parsed_constraint.req;
3166 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3167 parsed_constraint.is_in = 1;
3168 for(i = 0; i < arity; ++i) {
3169 const ir_asm_constraint *constraint;
3173 constraint = & get_ASM_input_constraints(node) [i];
3174 constr_id = constraint->constraint;
3175 c = get_id_str(constr_id);
3176 parse_asm_constraint(i, &parsed_constraint, c);
3177 in_reqs[i] = parsed_constraint.req;
3179 if(parsed_constraint.immediate_possible) {
3180 ir_node *pred = get_irn_n(node, i);
3181 char imm_type = parsed_constraint.immediate_type;
3182 ir_node *immediate = try_create_Immediate(pred, imm_type);
3184 if(immediate != NULL) {
3190 /* transform inputs */
3191 for(i = 0; i < arity; ++i) {
3193 ir_node *transformed;
3198 pred = get_irn_n(node, i);
3199 transformed = be_transform_node(pred);
3200 in[i] = transformed;
3203 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3205 generic_attr = get_irn_generic_attr(res);
3206 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3207 attr->asm_text = get_ASM_text(node);
3208 set_ia32_out_req_all(res, out_reqs);
3209 set_ia32_in_req_all(res, in_reqs);
3211 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3216 /********************************************
3219 * | |__ ___ _ __ ___ __| | ___ ___
3220 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3221 * | |_) | __/ | | | (_) | (_| | __/\__ \
3222 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3224 ********************************************/
3227 * Transforms a FrameAddr into an ia32 Add.
3229 static ir_node *gen_be_FrameAddr(ir_node *node) {
3230 ir_node *block = be_transform_node(get_nodes_block(node));
3231 ir_node *op = be_get_FrameAddr_frame(node);
3232 ir_node *new_op = be_transform_node(op);
3233 ir_graph *irg = current_ir_graph;
3234 dbg_info *dbgi = get_irn_dbg_info(node);
3235 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3238 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3239 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3240 set_ia32_use_frame(res);
3242 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3248 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3250 static ir_node *gen_be_Return(ir_node *node) {
3251 ir_graph *irg = current_ir_graph;
3252 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3253 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3254 ir_entity *ent = get_irg_entity(irg);
3255 ir_type *tp = get_entity_type(ent);
3260 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3261 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3264 int pn_ret_val, pn_ret_mem, arity, i;
3266 assert(ret_val != NULL);
3267 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3268 return be_duplicate_node(node);
3271 res_type = get_method_res_type(tp, 0);
3273 if (! is_Primitive_type(res_type)) {
3274 return be_duplicate_node(node);
3277 mode = get_type_mode(res_type);
3278 if (! mode_is_float(mode)) {
3279 return be_duplicate_node(node);
3282 assert(get_method_n_ress(tp) == 1);
3284 pn_ret_val = get_Proj_proj(ret_val);
3285 pn_ret_mem = get_Proj_proj(ret_mem);
3287 /* get the Barrier */
3288 barrier = get_Proj_pred(ret_val);
3290 /* get result input of the Barrier */
3291 ret_val = get_irn_n(barrier, pn_ret_val);
3292 new_ret_val = be_transform_node(ret_val);
3294 /* get memory input of the Barrier */
3295 ret_mem = get_irn_n(barrier, pn_ret_mem);
3296 new_ret_mem = be_transform_node(ret_mem);
3298 frame = get_irg_frame(irg);
3300 dbgi = get_irn_dbg_info(barrier);
3301 block = be_transform_node(get_nodes_block(barrier));
3303 noreg = ia32_new_NoReg_gp(env_cg);
3305 /* store xmm0 onto stack */
3306 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3307 new_ret_val, new_ret_mem);
3308 set_ia32_ls_mode(sse_store, mode);
3309 set_ia32_op_type(sse_store, ia32_AddrModeD);
3310 set_ia32_use_frame(sse_store);
3312 /* load into x87 register */
3313 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3314 set_ia32_op_type(fld, ia32_AddrModeS);
3315 set_ia32_use_frame(fld);
3317 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3318 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3320 /* create a new barrier */
3321 arity = get_irn_arity(barrier);
3322 in = alloca(arity * sizeof(in[0]));
3323 for (i = 0; i < arity; ++i) {
3326 if (i == pn_ret_val) {
3328 } else if (i == pn_ret_mem) {
3331 ir_node *in = get_irn_n(barrier, i);
3332 new_in = be_transform_node(in);
3337 new_barrier = new_ir_node(dbgi, irg, block,
3338 get_irn_op(barrier), get_irn_mode(barrier),
3340 copy_node_attr(barrier, new_barrier);
3341 be_duplicate_deps(barrier, new_barrier);
3342 be_set_transformed_node(barrier, new_barrier);
3343 mark_irn_visited(barrier);
3345 /* transform normally */
3346 return be_duplicate_node(node);
3350 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3352 static ir_node *gen_be_AddSP(ir_node *node) {
3353 ir_node *block = be_transform_node(get_nodes_block(node));
3354 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3356 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3357 ir_node *new_sp = be_transform_node(sp);
3358 ir_graph *irg = current_ir_graph;
3359 dbg_info *dbgi = get_irn_dbg_info(node);
3360 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3361 ir_node *nomem = new_NoMem();
3364 new_sz = create_immediate_or_transform(sz, 0);
3366 /* ia32 stack grows in reverse direction, make a SubSP */
3367 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3369 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3375 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3377 static ir_node *gen_be_SubSP(ir_node *node) {
3378 ir_node *block = be_transform_node(get_nodes_block(node));
3379 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3381 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3382 ir_node *new_sp = be_transform_node(sp);
3383 ir_graph *irg = current_ir_graph;
3384 dbg_info *dbgi = get_irn_dbg_info(node);
3385 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3386 ir_node *nomem = new_NoMem();
3389 new_sz = create_immediate_or_transform(sz, 0);
3391 /* ia32 stack grows in reverse direction, make an AddSP */
3392 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3393 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3399 * This function just sets the register for the Unknown node
3400 * as this is not done during register allocation because Unknown
3401 * is an "ignore" node.
3403 static ir_node *gen_Unknown(ir_node *node) {
3404 ir_mode *mode = get_irn_mode(node);
3406 if (mode_is_float(mode)) {
3407 if (USE_SSE2(env_cg)) {
3408 return ia32_new_Unknown_xmm(env_cg);
3410 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3411 ir_graph *irg = current_ir_graph;
3412 dbg_info *dbgi = get_irn_dbg_info(node);
3413 ir_node *block = get_irg_start_block(irg);
3414 return new_rd_ia32_vfldz(dbgi, irg, block);
3416 } else if (mode_needs_gp_reg(mode)) {
3417 return ia32_new_Unknown_gp(env_cg);
3419 assert(0 && "unsupported Unknown-Mode");
3426 * Change some phi modes
3428 static ir_node *gen_Phi(ir_node *node) {
3429 ir_node *block = be_transform_node(get_nodes_block(node));
3430 ir_graph *irg = current_ir_graph;
3431 dbg_info *dbgi = get_irn_dbg_info(node);
3432 ir_mode *mode = get_irn_mode(node);
3435 if(mode_needs_gp_reg(mode)) {
3436 /* we shouldn't have any 64bit stuff around anymore */
3437 assert(get_mode_size_bits(mode) <= 32);
3438 /* all integer operations are on 32bit registers now */
3440 } else if(mode_is_float(mode)) {
3441 if (USE_SSE2(env_cg)) {
3448 /* phi nodes allow loops, so we use the old arguments for now
3449 * and fix this later */
3450 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3451 get_irn_in(node) + 1);
3452 copy_node_attr(node, phi);
3453 be_duplicate_deps(node, phi);
3455 be_set_transformed_node(node, phi);
3456 be_enqueue_preds(node);
3464 static ir_node *gen_IJmp(ir_node *node) {
3465 /* TODO: support AM */
3466 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3470 /**********************************************************************
3473 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3474 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3475 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3476 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3478 **********************************************************************/
3480 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3482 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3485 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3486 ir_node *val, ir_node *mem);
3489 * Transforms a lowered Load into a "real" one.
3491 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3493 ir_node *block = be_transform_node(get_nodes_block(node));
3494 ir_node *ptr = get_irn_n(node, 0);
3495 ir_node *new_ptr = be_transform_node(ptr);
3496 ir_node *mem = get_irn_n(node, 1);
3497 ir_node *new_mem = be_transform_node(mem);
3498 ir_graph *irg = current_ir_graph;
3499 dbg_info *dbgi = get_irn_dbg_info(node);
3500 ir_mode *mode = get_ia32_ls_mode(node);
3501 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3504 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3506 set_ia32_op_type(new_op, ia32_AddrModeS);
3507 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3508 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3509 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3510 if (is_ia32_am_sc_sign(node))
3511 set_ia32_am_sc_sign(new_op);
3512 set_ia32_ls_mode(new_op, mode);
3513 if (is_ia32_use_frame(node)) {
3514 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3515 set_ia32_use_frame(new_op);
3518 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3524 * Transforms a lowered Store into a "real" one.
3526 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3528 ir_node *block = be_transform_node(get_nodes_block(node));
3529 ir_node *ptr = get_irn_n(node, 0);
3530 ir_node *new_ptr = be_transform_node(ptr);
3531 ir_node *val = get_irn_n(node, 1);
3532 ir_node *new_val = be_transform_node(val);
3533 ir_node *mem = get_irn_n(node, 2);
3534 ir_node *new_mem = be_transform_node(mem);
3535 ir_graph *irg = current_ir_graph;
3536 dbg_info *dbgi = get_irn_dbg_info(node);
3537 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3538 ir_mode *mode = get_ia32_ls_mode(node);
3542 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3544 am_offs = get_ia32_am_offs_int(node);
3545 add_ia32_am_offs_int(new_op, am_offs);
3547 set_ia32_op_type(new_op, ia32_AddrModeD);
3548 set_ia32_ls_mode(new_op, mode);
3549 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3550 set_ia32_use_frame(new_op);
3552 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3559 * Transforms an ia32_l_XXX into a "real" XXX node
3561 * @param node The node to transform
3562 * @return the created ia32 XXX node
3564 #define GEN_LOWERED_OP(op) \
3565 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3566 return gen_binop(node, get_binop_left(node), \
3567 get_binop_right(node), new_rd_ia32_##op,0); \
3570 #define GEN_LOWERED_x87_OP(op) \
3571 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3573 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3574 get_binop_right(node), new_rd_ia32_##op); \
3578 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3579 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3580 return gen_shift_binop(node, get_irn_n(node, 0), \
3581 get_irn_n(node, 1), new_rd_ia32_##op); \
3584 GEN_LOWERED_x87_OP(vfprem)
3585 GEN_LOWERED_x87_OP(vfmul)
3586 GEN_LOWERED_x87_OP(vfsub)
3587 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3588 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3589 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3590 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3594 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3596 * @param node The node to transform
3597 * @return the created ia32 Neg node
3599 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3600 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3604 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3606 * @param node The node to transform
3607 * @return the created ia32 vfild node
3609 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3610 return gen_lowered_Load(node, new_rd_ia32_vfild);
3614 * Transforms an ia32_l_Load into a "real" ia32_Load node
3616 * @param node The node to transform
3617 * @return the created ia32 Load node
3619 static ir_node *gen_ia32_l_Load(ir_node *node) {
3620 return gen_lowered_Load(node, new_rd_ia32_Load);
3624 * Transforms an ia32_l_Store into a "real" ia32_Store node
3626 * @param node The node to transform
3627 * @return the created ia32 Store node
3629 static ir_node *gen_ia32_l_Store(ir_node *node) {
3630 return gen_lowered_Store(node, new_rd_ia32_Store);
3634 * Transforms a l_vfist into a "real" vfist node.
3636 * @param node The node to transform
3637 * @return the created ia32 vfist node
3639 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3640 ir_node *block = be_transform_node(get_nodes_block(node));
3641 ir_node *ptr = get_irn_n(node, 0);
3642 ir_node *new_ptr = be_transform_node(ptr);
3643 ir_node *val = get_irn_n(node, 1);
3644 ir_node *new_val = be_transform_node(val);
3645 ir_node *mem = get_irn_n(node, 2);
3646 ir_node *new_mem = be_transform_node(mem);
3647 ir_graph *irg = current_ir_graph;
3648 dbg_info *dbgi = get_irn_dbg_info(node);
3649 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3650 ir_mode *mode = get_ia32_ls_mode(node);
3651 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3655 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
3656 trunc_mode, new_mem);
3658 am_offs = get_ia32_am_offs_int(node);
3659 add_ia32_am_offs_int(new_op, am_offs);
3661 set_ia32_op_type(new_op, ia32_AddrModeD);
3662 set_ia32_ls_mode(new_op, mode);
3663 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3664 set_ia32_use_frame(new_op);
3666 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3672 * Transforms a l_vfdiv into a "real" vfdiv node.
3674 * @param env The transformation environment
3675 * @return the created ia32 vfdiv node
3677 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3678 ir_node *block = be_transform_node(get_nodes_block(node));
3679 ir_node *left = get_binop_left(node);
3680 ir_node *new_left = be_transform_node(left);
3681 ir_node *right = get_binop_right(node);
3682 ir_node *new_right = be_transform_node(right);
3683 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3684 ir_graph *irg = current_ir_graph;
3685 dbg_info *dbgi = get_irn_dbg_info(node);
3686 ir_node *fpcw = get_fpcw();
3689 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3690 new_right, new_NoMem(), fpcw);
3691 clear_ia32_commutative(vfdiv);
3693 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3699 * Transforms a l_MulS into a "real" MulS node.
3701 * @param env The transformation environment
3702 * @return the created ia32 Mul node
3704 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3705 ir_node *block = be_transform_node(get_nodes_block(node));
3706 ir_node *left = get_binop_left(node);
3707 ir_node *new_left = be_transform_node(left);
3708 ir_node *right = get_binop_right(node);
3709 ir_node *new_right = be_transform_node(right);
3710 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3711 ir_graph *irg = current_ir_graph;
3712 dbg_info *dbgi = get_irn_dbg_info(node);
3714 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3715 /* and then skip the result Proj, because all needed Projs are already there. */
3716 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3717 new_right, new_NoMem());
3718 clear_ia32_commutative(muls);
3720 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3726 * Transforms a l_IMulS into a "real" IMul1OPS node.
3728 * @param env The transformation environment
3729 * @return the created ia32 IMul1OP node
3731 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3732 ir_node *block = be_transform_node(get_nodes_block(node));
3733 ir_node *left = get_binop_left(node);
3734 ir_node *new_left = be_transform_node(left);
3735 ir_node *right = get_binop_right(node);
3736 ir_node *new_right = be_transform_node(right);
3737 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3738 ir_graph *irg = current_ir_graph;
3739 dbg_info *dbgi = get_irn_dbg_info(node);
3741 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3742 /* and then skip the result Proj, because all needed Projs are already there. */
3743 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
3744 new_right, new_NoMem());
3745 clear_ia32_commutative(muls);
3747 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3752 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3754 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3755 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3756 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3757 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3758 ir_node *block = be_transform_node(get_nodes_block(node));
3759 dbg_info *dbgi = get_irn_dbg_info(node);
3760 ir_graph *irg = current_ir_graph;
3761 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3762 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3766 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3768 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3769 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3770 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3771 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3772 ir_node *block = be_transform_node(get_nodes_block(node));
3773 dbg_info *dbgi = get_irn_dbg_info(node);
3774 ir_graph *irg = current_ir_graph;
3775 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3781 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3782 * op1 - target to be shifted
3783 * op2 - contains bits to be shifted into target
3785 * Only op3 can be an immediate.
3787 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3788 ir_node *op2, ir_node *count)
3790 ir_node *block = be_transform_node(get_nodes_block(node));
3791 ir_node *new_op = NULL;
3792 ir_graph *irg = current_ir_graph;
3793 dbg_info *dbgi = get_irn_dbg_info(node);
3794 ir_node *new_op1 = be_transform_node(op1);
3795 ir_node *new_op2 = be_transform_node(op2);
3796 ir_node *new_count = create_immediate_or_transform(count, 'I');
3798 /* TODO proper AM support */
3800 if (is_ia32_l_ShlD(node))
3801 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3803 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3805 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3810 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3811 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3812 get_irn_n(node, 1), get_irn_n(node, 2));
3815 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3816 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3817 get_irn_n(node, 1), get_irn_n(node, 2));
3821 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3823 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3824 ir_node *block = be_transform_node(get_nodes_block(node));
3825 ir_node *val = get_irn_n(node, 1);
3826 ir_node *new_val = be_transform_node(val);
3827 ia32_code_gen_t *cg = env_cg;
3828 ir_node *res = NULL;
3829 ir_graph *irg = current_ir_graph;
3831 ir_node *noreg, *new_ptr, *new_mem;
3838 mem = get_irn_n(node, 2);
3839 new_mem = be_transform_node(mem);
3840 ptr = get_irn_n(node, 0);
3841 new_ptr = be_transform_node(ptr);
3842 noreg = ia32_new_NoReg_gp(cg);
3843 dbgi = get_irn_dbg_info(node);
3845 /* Store x87 -> MEM */
3846 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3847 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3848 set_ia32_use_frame(res);
3849 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3850 set_ia32_op_type(res, ia32_AddrModeD);
3852 /* Load MEM -> SSE */
3853 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3854 get_ia32_ls_mode(node));
3855 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3856 set_ia32_use_frame(res);
3857 set_ia32_op_type(res, ia32_AddrModeS);
3858 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3864 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3866 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3867 ir_node *block = be_transform_node(get_nodes_block(node));
3868 ir_node *val = get_irn_n(node, 1);
3869 ir_node *new_val = be_transform_node(val);
3870 ia32_code_gen_t *cg = env_cg;
3871 ir_graph *irg = current_ir_graph;
3872 ir_node *res = NULL;
3873 ir_entity *fent = get_ia32_frame_ent(node);
3874 ir_mode *lsmode = get_ia32_ls_mode(node);
3876 ir_node *noreg, *new_ptr, *new_mem;
3880 if (! USE_SSE2(cg)) {
3881 /* SSE unit is not used -> skip this node. */
3885 ptr = get_irn_n(node, 0);
3886 new_ptr = be_transform_node(ptr);
3887 mem = get_irn_n(node, 2);
3888 new_mem = be_transform_node(mem);
3889 noreg = ia32_new_NoReg_gp(cg);
3890 dbgi = get_irn_dbg_info(node);
3892 /* Store SSE -> MEM */
3893 if (is_ia32_xLoad(skip_Proj(new_val))) {
3894 ir_node *ld = skip_Proj(new_val);
3896 /* we can vfld the value directly into the fpu */
3897 fent = get_ia32_frame_ent(ld);
3898 ptr = get_irn_n(ld, 0);
3899 offs = get_ia32_am_offs_int(ld);
3901 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3902 set_ia32_frame_ent(res, fent);
3903 set_ia32_use_frame(res);
3904 set_ia32_ls_mode(res, lsmode);
3905 set_ia32_op_type(res, ia32_AddrModeD);
3909 /* Load MEM -> x87 */
3910 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3911 set_ia32_frame_ent(res, fent);
3912 set_ia32_use_frame(res);
3913 add_ia32_am_offs_int(res, offs);
3914 set_ia32_op_type(res, ia32_AddrModeS);
3915 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3920 /*********************************************************
3923 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3924 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3925 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3926 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3928 *********************************************************/
3931 * the BAD transformer.
3933 static ir_node *bad_transform(ir_node *node) {
3934 panic("No transform function for %+F available.\n", node);
3939 * Transform the Projs of an AddSP.
3941 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3942 ir_node *block = be_transform_node(get_nodes_block(node));
3943 ir_node *pred = get_Proj_pred(node);
3944 ir_node *new_pred = be_transform_node(pred);
3945 ir_graph *irg = current_ir_graph;
3946 dbg_info *dbgi = get_irn_dbg_info(node);
3947 long proj = get_Proj_proj(node);
3949 if (proj == pn_be_AddSP_sp) {
3950 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3951 pn_ia32_SubSP_stack);
3952 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3954 } else if(proj == pn_be_AddSP_res) {
3955 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3956 pn_ia32_SubSP_addr);
3957 } else if (proj == pn_be_AddSP_M) {
3958 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3962 return new_rd_Unknown(irg, get_irn_mode(node));
3966 * Transform the Projs of a SubSP.
3968 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3969 ir_node *block = be_transform_node(get_nodes_block(node));
3970 ir_node *pred = get_Proj_pred(node);
3971 ir_node *new_pred = be_transform_node(pred);
3972 ir_graph *irg = current_ir_graph;
3973 dbg_info *dbgi = get_irn_dbg_info(node);
3974 long proj = get_Proj_proj(node);
3976 if (proj == pn_be_SubSP_sp) {
3977 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3978 pn_ia32_AddSP_stack);
3979 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3981 } else if (proj == pn_be_SubSP_M) {
3982 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3986 return new_rd_Unknown(irg, get_irn_mode(node));
3990 * Transform and renumber the Projs from a Load.
3992 static ir_node *gen_Proj_Load(ir_node *node) {
3994 ir_node *block = be_transform_node(get_nodes_block(node));
3995 ir_node *pred = get_Proj_pred(node);
3996 ir_graph *irg = current_ir_graph;
3997 dbg_info *dbgi = get_irn_dbg_info(node);
3998 long proj = get_Proj_proj(node);
4001 /* loads might be part of source address mode matches, so we don't
4002 transform the ProjMs yet (with the exception of loads whose result is
4005 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4008 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4010 /* this is needed, because sometimes we have loops that are only
4011 reachable through the ProjM */
4012 be_enqueue_preds(node);
4013 /* do it in 2 steps, to silence firm verifier */
4014 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4015 set_Proj_proj(res, pn_ia32_Load_M);
4019 /* renumber the proj */
4020 new_pred = be_transform_node(pred);
4021 if (is_ia32_Load(new_pred)) {
4022 if (proj == pn_Load_res) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4025 } else if (proj == pn_Load_M) {
4026 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4029 } else if(is_ia32_Conv_I2I(new_pred)) {
4030 set_irn_mode(new_pred, mode_T);
4031 if (proj == pn_Load_res) {
4032 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
4033 } else if (proj == pn_Load_M) {
4034 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4036 } else if (is_ia32_xLoad(new_pred)) {
4037 if (proj == pn_Load_res) {
4038 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4040 } else if (proj == pn_Load_M) {
4041 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4044 } else if (is_ia32_vfld(new_pred)) {
4045 if (proj == pn_Load_res) {
4046 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4048 } else if (proj == pn_Load_M) {
4049 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4053 /* can happen for ProJMs when source address mode happened for the
4056 /* however it should not be the result proj, as that would mean the
4057 load had multiple users and should not have been used for
4059 if(proj != pn_Load_M) {
4060 panic("internal error: transformed node not a Load");
4062 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4066 return new_rd_Unknown(irg, get_irn_mode(node));
4070 * Transform and renumber the Projs from a DivMod like instruction.
4072 static ir_node *gen_Proj_DivMod(ir_node *node) {
4073 ir_node *block = be_transform_node(get_nodes_block(node));
4074 ir_node *pred = get_Proj_pred(node);
4075 ir_node *new_pred = be_transform_node(pred);
4076 ir_graph *irg = current_ir_graph;
4077 dbg_info *dbgi = get_irn_dbg_info(node);
4078 ir_mode *mode = get_irn_mode(node);
4079 long proj = get_Proj_proj(node);
4081 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4083 switch (get_irn_opcode(pred)) {
4087 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4089 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4099 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4107 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4108 case pn_DivMod_res_div:
4109 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4110 case pn_DivMod_res_mod:
4111 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4121 return new_rd_Unknown(irg, mode);
4125 * Transform and renumber the Projs from a CopyB.
4127 static ir_node *gen_Proj_CopyB(ir_node *node) {
4128 ir_node *block = be_transform_node(get_nodes_block(node));
4129 ir_node *pred = get_Proj_pred(node);
4130 ir_node *new_pred = be_transform_node(pred);
4131 ir_graph *irg = current_ir_graph;
4132 dbg_info *dbgi = get_irn_dbg_info(node);
4133 ir_mode *mode = get_irn_mode(node);
4134 long proj = get_Proj_proj(node);
4137 case pn_CopyB_M_regular:
4138 if (is_ia32_CopyB_i(new_pred)) {
4139 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4140 } else if (is_ia32_CopyB(new_pred)) {
4141 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4149 return new_rd_Unknown(irg, mode);
4153 * Transform and renumber the Projs from a vfdiv.
4155 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4156 ir_node *block = be_transform_node(get_nodes_block(node));
4157 ir_node *pred = get_Proj_pred(node);
4158 ir_node *new_pred = be_transform_node(pred);
4159 ir_graph *irg = current_ir_graph;
4160 dbg_info *dbgi = get_irn_dbg_info(node);
4161 ir_mode *mode = get_irn_mode(node);
4162 long proj = get_Proj_proj(node);
4165 case pn_ia32_l_vfdiv_M:
4166 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4167 case pn_ia32_l_vfdiv_res:
4168 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4173 return new_rd_Unknown(irg, mode);
4177 * Transform and renumber the Projs from a Quot.
4179 static ir_node *gen_Proj_Quot(ir_node *node) {
4180 ir_node *block = be_transform_node(get_nodes_block(node));
4181 ir_node *pred = get_Proj_pred(node);
4182 ir_node *new_pred = be_transform_node(pred);
4183 ir_graph *irg = current_ir_graph;
4184 dbg_info *dbgi = get_irn_dbg_info(node);
4185 ir_mode *mode = get_irn_mode(node);
4186 long proj = get_Proj_proj(node);
4190 if (is_ia32_xDiv(new_pred)) {
4191 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4192 } else if (is_ia32_vfdiv(new_pred)) {
4193 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4197 if (is_ia32_xDiv(new_pred)) {
4198 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4199 } else if (is_ia32_vfdiv(new_pred)) {
4200 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4208 return new_rd_Unknown(irg, mode);
4212 * Transform the Thread Local Storage Proj.
4214 static ir_node *gen_Proj_tls(ir_node *node) {
4215 ir_node *block = be_transform_node(get_nodes_block(node));
4216 ir_graph *irg = current_ir_graph;
4217 dbg_info *dbgi = NULL;
4218 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4224 * Transform the Projs from a be_Call.
4226 static ir_node *gen_Proj_be_Call(ir_node *node) {
4227 ir_node *block = be_transform_node(get_nodes_block(node));
4228 ir_node *call = get_Proj_pred(node);
4229 ir_node *new_call = be_transform_node(call);
4230 ir_graph *irg = current_ir_graph;
4231 dbg_info *dbgi = get_irn_dbg_info(node);
4232 ir_type *method_type = be_Call_get_type(call);
4233 int n_res = get_method_n_ress(method_type);
4234 long proj = get_Proj_proj(node);
4235 ir_mode *mode = get_irn_mode(node);
4237 const arch_register_class_t *cls;
4239 /* The following is kinda tricky: If we're using SSE, then we have to
4240 * move the result value of the call in floating point registers to an
4241 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4242 * after the call, we have to make sure to correctly make the
4243 * MemProj and the result Proj use these 2 nodes
4245 if (proj == pn_be_Call_M_regular) {
4246 // get new node for result, are we doing the sse load/store hack?
4247 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4248 ir_node *call_res_new;
4249 ir_node *call_res_pred = NULL;
4251 if (call_res != NULL) {
4252 call_res_new = be_transform_node(call_res);
4253 call_res_pred = get_Proj_pred(call_res_new);
4256 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4257 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4258 pn_be_Call_M_regular);
4260 assert(is_ia32_xLoad(call_res_pred));
4261 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4265 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4266 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4267 && USE_SSE2(env_cg)) {
4269 ir_node *frame = get_irg_frame(irg);
4270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4272 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4275 /* in case there is no memory output: create one to serialize the copy
4277 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4278 pn_be_Call_M_regular);
4279 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4280 pn_be_Call_first_res);
4282 /* store st(0) onto stack */
4283 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
4285 set_ia32_op_type(fstp, ia32_AddrModeD);
4286 set_ia32_use_frame(fstp);
4288 /* load into SSE register */
4289 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4291 set_ia32_op_type(sse_load, ia32_AddrModeS);
4292 set_ia32_use_frame(sse_load);
4294 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4300 /* transform call modes */
4301 if (mode_is_data(mode)) {
4302 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4306 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4310 * Transform the Projs from a Cmp.
4312 static ir_node *gen_Proj_Cmp(ir_node *node)
4314 /* normally Cmps are processed when looking at Cond nodes, but this case
4315 * can happen in complicated Psi conditions */
4317 ir_node *cmp = get_Proj_pred(node);
4318 long pnc = get_Proj_proj(node);
4319 ir_node *cmp_left = get_Cmp_left(cmp);
4320 ir_node *cmp_right = get_Cmp_right(cmp);
4321 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4322 dbg_info *dbgi = get_irn_dbg_info(cmp);
4323 ir_node *block = get_nodes_block(node);
4327 assert(!mode_is_float(cmp_mode));
4329 if(!mode_is_signed(cmp_mode)) {
4330 pnc |= ia32_pn_Cmp_Unsigned;
4334 * address mode makes only sense when we'll be the only node using the cmp
4336 use_am = get_irn_n_edges(cmp) <= 1;
4338 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4339 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4345 * Transform and potentially renumber Proj nodes.
4347 static ir_node *gen_Proj(ir_node *node) {
4348 ir_graph *irg = current_ir_graph;
4349 dbg_info *dbgi = get_irn_dbg_info(node);
4350 ir_node *pred = get_Proj_pred(node);
4351 long proj = get_Proj_proj(node);
4353 if (is_Store(pred)) {
4354 if (proj == pn_Store_M) {
4355 return be_transform_node(pred);
4358 return new_r_Bad(irg);
4360 } else if (is_Load(pred)) {
4361 return gen_Proj_Load(node);
4362 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4363 return gen_Proj_DivMod(node);
4364 } else if (is_CopyB(pred)) {
4365 return gen_Proj_CopyB(node);
4366 } else if (is_Quot(pred)) {
4367 return gen_Proj_Quot(node);
4368 } else if (is_ia32_l_vfdiv(pred)) {
4369 return gen_Proj_l_vfdiv(node);
4370 } else if (be_is_SubSP(pred)) {
4371 return gen_Proj_be_SubSP(node);
4372 } else if (be_is_AddSP(pred)) {
4373 return gen_Proj_be_AddSP(node);
4374 } else if (be_is_Call(pred)) {
4375 return gen_Proj_be_Call(node);
4376 } else if (is_Cmp(pred)) {
4377 return gen_Proj_Cmp(node);
4378 } else if (get_irn_op(pred) == op_Start) {
4379 if (proj == pn_Start_X_initial_exec) {
4380 ir_node *block = get_nodes_block(pred);
4383 /* we exchange the ProjX with a jump */
4384 block = be_transform_node(block);
4385 jump = new_rd_Jmp(dbgi, irg, block);
4388 if (node == be_get_old_anchor(anchor_tls)) {
4389 return gen_Proj_tls(node);
4392 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4396 ir_node *new_pred = be_transform_node(pred);
4397 ir_node *block = be_transform_node(get_nodes_block(node));
4398 ir_mode *mode = get_irn_mode(node);
4399 if (mode_needs_gp_reg(mode)) {
4400 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4401 get_Proj_proj(node));
4402 #ifdef DEBUG_libfirm
4403 new_proj->node_nr = node->node_nr;
4409 return be_duplicate_node(node);
4413 * Enters all transform functions into the generic pointer
4415 static void register_transformers(void)
4419 /* first clear the generic function pointer for all ops */
4420 clear_irp_opcodes_generic_func();
4422 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4423 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4460 /* transform ops from intrinsic lowering */
4480 GEN(ia32_l_X87toSSE);
4481 GEN(ia32_l_SSEtoX87);
4487 /* we should never see these nodes */
4502 /* handle generic backend nodes */
4510 op_Mulh = get_op_Mulh();
4519 * Pre-transform all unknown and noreg nodes.
4521 static void ia32_pretransform_node(void *arch_cg) {
4522 ia32_code_gen_t *cg = arch_cg;
4524 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4525 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4526 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4527 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4528 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4529 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4534 * Walker, checks if all ia32 nodes producing more than one result have
4535 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4538 void add_missing_keep_walker(ir_node *node, void *data)
4541 unsigned found_projs = 0;
4542 const ir_edge_t *edge;
4543 ir_mode *mode = get_irn_mode(node);
4548 if(!is_ia32_irn(node))
4551 n_outs = get_ia32_n_res(node);
4554 if(is_ia32_SwitchJmp(node))
4557 assert(n_outs < (int) sizeof(unsigned) * 8);
4558 foreach_out_edge(node, edge) {
4559 ir_node *proj = get_edge_src_irn(edge);
4560 int pn = get_Proj_proj(proj);
4562 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4563 found_projs |= 1 << pn;
4567 /* are keeps missing? */
4569 for(i = 0; i < n_outs; ++i) {
4572 const arch_register_req_t *req;
4573 const arch_register_class_t *class;
4575 if(found_projs & (1 << i)) {
4579 req = get_ia32_out_req(node, i);
4585 block = get_nodes_block(node);
4586 in[0] = new_r_Proj(current_ir_graph, block, node,
4587 arch_register_class_mode(class), i);
4588 if(last_keep != NULL) {
4589 be_Keep_add_node(last_keep, class, in[0]);
4591 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4597 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4601 void add_missing_keeps(ia32_code_gen_t *cg)
4603 ir_graph *irg = be_get_birg_irg(cg->birg);
4604 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4607 /* do the transformation */
4608 void ia32_transform_graph(ia32_code_gen_t *cg) {
4609 register_transformers();
4611 initial_fpcw = NULL;
4613 heights = heights_new(cg->irg);
4615 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4617 heights_free(heights);
4619 add_missing_keeps(cg);
4622 void ia32_init_transform(void)
4624 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");