2 * This file implements the IR transformation from firm into
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
26 #include "../benode_t.h"
27 #include "../besched.h"
29 #include "bearch_ia32_t.h"
31 #include "ia32_nodes_attr.h"
32 #include "../arch/archop.h" /* we need this for Min and Max nodes */
33 #include "ia32_transform.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
37 #include "gen_ia32_regalloc_if.h"
40 #define SET_IA32_ORIG_NODE(n, o)
42 #define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
46 #define SFP_SIGN "0x80000000"
47 #define DFP_SIGN "0x8000000000000000"
48 #define SFP_ABS "0x7FFFFFFF"
49 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
51 #define TP_SFP_SIGN "ia32_sfp_sign"
52 #define TP_DFP_SIGN "ia32_dfp_sign"
53 #define TP_SFP_ABS "ia32_sfp_abs"
54 #define TP_DFP_ABS "ia32_dfp_abs"
56 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
57 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
58 #define ENT_SFP_ABS "IA32_SFP_ABS"
59 #define ENT_DFP_ABS "IA32_DFP_ABS"
61 extern ir_op *get_op_Mulh(void);
63 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
64 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
66 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
67 ir_node *op, ir_node *mem, ir_mode *mode);
70 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
73 /****************************************************************************************************
75 * | | | | / _| | | (_)
76 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
77 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
78 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
79 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
81 ****************************************************************************************************/
83 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
84 static const char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
89 } names [ia32_known_const_max] = {
90 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
91 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
92 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
93 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
95 static struct entity *ent_cache[ia32_known_const_max];
97 const char *tp_name, *ent_name, *cnst_str;
104 ent_name = names[kct].ent_name;
105 if (! ent_cache[kct]) {
106 tp_name = names[kct].tp_name;
107 cnst_str = names[kct].cnst_str;
109 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
110 tp = new_type_primitive(new_id_from_str(tp_name), mode);
111 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
113 set_entity_ld_ident(ent, get_entity_ident(ent));
114 set_entity_visibility(ent, visibility_local);
115 set_entity_variability(ent, variability_constant);
116 set_entity_allocation(ent, allocation_static);
118 /* we create a new entity here: It's initialization must resist on the
120 rem = current_ir_graph;
121 current_ir_graph = get_const_code_irg();
122 cnst = new_Const(mode, tv);
123 current_ir_graph = rem;
125 set_atomic_ent_value(ent, cnst);
127 /* cache the entry */
128 ent_cache[kct] = ent;
135 * Prints the old node name on cg obst and returns a pointer to it.
137 const char *get_old_node_name(ia32_transform_env_t *env) {
138 static int name_cnt = 0;
139 ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
141 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
142 obstack_1grow(isa->name_obst, 0);
143 isa->name_obst_size += obstack_object_size(isa->name_obst);
145 if (name_cnt % 1024 == 0) {
146 printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
148 return obstack_finish(isa->name_obst);
152 /* determine if one operator is an Imm */
153 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
155 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
156 else return is_ia32_Cnst(op2) ? op2 : NULL;
159 /* determine if one operator is not an Imm */
160 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
161 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
166 * Construct a standard binary operation, set AM and immediate if required.
168 * @param env The transformation environment
169 * @param op1 The first operand
170 * @param op2 The second operand
171 * @param func The node constructor function
172 * @return The constructed ia32 node.
174 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
175 ir_node *new_op = NULL;
176 ir_mode *mode = env->mode;
177 dbg_info *dbg = env->dbg;
178 ir_graph *irg = env->irg;
179 ir_node *block = env->block;
180 firm_dbg_module_t *mod = env->mod;
181 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
182 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
183 ir_node *nomem = new_NoMem();
184 ir_node *expr_op, *imm_op;
186 /* Check if immediate optimization is on and */
187 /* if it's an operation with immediate. */
188 if (! env->cg->opt.immops) {
192 else if (is_op_commutative(get_irn_op(env->irn))) {
193 imm_op = get_immediate_op(op1, op2);
194 expr_op = get_expr_op(op1, op2);
197 imm_op = get_immediate_op(NULL, op2);
198 expr_op = get_expr_op(op1, op2);
201 assert((expr_op || imm_op) && "invalid operands");
204 /* We have two consts here: not yet supported */
208 if (mode_is_float(mode)) {
209 /* floating point operations */
211 DB((mod, LEVEL_1, "FP with immediate ..."));
212 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
213 set_ia32_Immop_attr(new_op, imm_op);
214 set_ia32_am_support(new_op, ia32_am_None);
217 DB((mod, LEVEL_1, "FP binop ..."));
218 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
219 set_ia32_am_support(new_op, ia32_am_Source);
223 /* integer operations */
225 /* This is expr + const */
226 DB((mod, LEVEL_1, "INT with immediate ..."));
227 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
228 set_ia32_Immop_attr(new_op, imm_op);
231 set_ia32_am_support(new_op, ia32_am_Dest);
234 DB((mod, LEVEL_1, "INT binop ..."));
235 /* This is a normal operation */
236 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
239 set_ia32_am_support(new_op, ia32_am_Full);
243 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
245 set_ia32_res_mode(new_op, mode);
247 if (is_op_commutative(get_irn_op(env->irn))) {
248 set_ia32_commutative(new_op);
251 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
257 * Construct a shift/rotate binary operation, sets AM and immediate if required.
259 * @param env The transformation environment
260 * @param op1 The first operand
261 * @param op2 The second operand
262 * @param func The node constructor function
263 * @return The constructed ia32 node.
265 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
266 ir_node *new_op = NULL;
267 ir_mode *mode = env->mode;
268 dbg_info *dbg = env->dbg;
269 ir_graph *irg = env->irg;
270 ir_node *block = env->block;
271 firm_dbg_module_t *mod = env->mod;
272 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
273 ir_node *nomem = new_NoMem();
274 ir_node *expr_op, *imm_op;
277 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
279 /* Check if immediate optimization is on and */
280 /* if it's an operation with immediate. */
281 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
282 expr_op = get_expr_op(op1, op2);
284 assert((expr_op || imm_op) && "invalid operands");
287 /* We have two consts here: not yet supported */
291 /* Limit imm_op within range imm8 */
293 tv = get_ia32_Immop_tarval(imm_op);
296 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
303 /* integer operations */
305 /* This is shift/rot with const */
306 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
308 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
309 set_ia32_Immop_attr(new_op, imm_op);
312 /* This is a normal shift/rot */
313 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
314 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
318 set_ia32_am_support(new_op, ia32_am_Dest);
320 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
322 set_ia32_res_mode(new_op, mode);
324 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
329 * Construct a standard unary operation, set AM and immediate if required.
331 * @param env The transformation environment
332 * @param op The operand
333 * @param func The node constructor function
334 * @return The constructed ia32 node.
336 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
337 ir_node *new_op = NULL;
338 ir_mode *mode = env->mode;
339 dbg_info *dbg = env->dbg;
340 firm_dbg_module_t *mod = env->mod;
341 ir_graph *irg = env->irg;
342 ir_node *block = env->block;
343 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
344 ir_node *nomem = new_NoMem();
346 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
348 if (mode_is_float(mode)) {
349 DB((mod, LEVEL_1, "FP unop ..."));
350 /* floating point operations don't support implicit store */
351 set_ia32_am_support(new_op, ia32_am_None);
354 DB((mod, LEVEL_1, "INT unop ..."));
355 set_ia32_am_support(new_op, ia32_am_Dest);
358 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
360 set_ia32_res_mode(new_op, mode);
362 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
368 * Creates an ia32 Add with immediate.
370 * @param env The transformation environment
371 * @param expr_op The expression operator
372 * @param const_op The constant
373 * @return the created ia32 Add node
375 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
376 ir_node *new_op = NULL;
377 tarval *tv = get_ia32_Immop_tarval(const_op);
378 firm_dbg_module_t *mod = env->mod;
379 dbg_info *dbg = env->dbg;
380 ir_graph *irg = env->irg;
381 ir_node *block = env->block;
382 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
383 ir_node *nomem = new_NoMem();
385 tarval_classification_t class_tv, class_negtv;
387 /* try to optimize to inc/dec */
388 if (env->cg->opt.incdec && tv) {
389 /* optimize tarvals */
390 class_tv = classify_tarval(tv);
391 class_negtv = classify_tarval(tarval_neg(tv));
393 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
394 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
395 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
398 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
399 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
400 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
406 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
407 set_ia32_Immop_attr(new_op, const_op);
414 * Creates an ia32 Add.
416 * @param dbg firm node dbg
417 * @param block the block the new node should belong to
418 * @param op1 first operator
419 * @param op2 second operator
420 * @param mode node mode
421 * @return the created ia32 Add node
423 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
424 ir_node *new_op = NULL;
425 dbg_info *dbg = env->dbg;
426 ir_mode *mode = env->mode;
427 ir_graph *irg = env->irg;
428 ir_node *block = env->block;
429 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
430 ir_node *nomem = new_NoMem();
431 ir_node *expr_op, *imm_op;
433 /* Check if immediate optimization is on and */
434 /* if it's an operation with immediate. */
435 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
436 expr_op = get_expr_op(op1, op2);
438 assert((expr_op || imm_op) && "invalid operands");
440 if (mode_is_float(mode)) {
441 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
446 /* No expr_op means, that we have two const - one symconst and */
447 /* one tarval or another symconst - because this case is not */
448 /* covered by constant folding */
450 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
451 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
452 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
455 set_ia32_am_support(new_op, ia32_am_Source);
456 set_ia32_op_type(new_op, ia32_AddrModeS);
457 set_ia32_am_flavour(new_op, ia32_am_O);
459 /* Lea doesn't need a Proj */
463 /* This is expr + const */
464 new_op = gen_imm_Add(env, expr_op, imm_op);
467 set_ia32_am_support(new_op, ia32_am_Dest);
470 /* This is a normal add */
471 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
474 set_ia32_am_support(new_op, ia32_am_Full);
478 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
480 set_ia32_res_mode(new_op, mode);
482 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
488 * Creates an ia32 Mul.
490 * @param dbg firm node dbg
491 * @param block the block the new node should belong to
492 * @param op1 first operator
493 * @param op2 second operator
494 * @param mode node mode
495 * @return the created ia32 Mul node
497 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
500 if (mode_is_float(env->mode)) {
501 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
504 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
513 * Creates an ia32 Mulh.
514 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
515 * this result while Mul returns the lower 32 bit.
517 * @param env The transformation environment
518 * @param op1 The first operator
519 * @param op2 The second operator
520 * @return the created ia32 Mulh node
522 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
523 ir_node *proj_EAX, *proj_EDX, *mulh;
526 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
527 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
528 mulh = get_Proj_pred(proj_EAX);
529 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
531 /* to be on the save side */
532 set_Proj_proj(proj_EAX, pn_EAX);
534 if (get_ia32_cnst(mulh)) {
535 /* Mulh with const cannot have AM */
536 set_ia32_am_support(mulh, ia32_am_None);
539 /* Mulh cannot have AM for destination */
540 set_ia32_am_support(mulh, ia32_am_Source);
546 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
554 * Creates an ia32 And.
556 * @param env The transformation environment
557 * @param op1 The first operator
558 * @param op2 The second operator
559 * @return The created ia32 And node
561 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
562 if (mode_is_float(env->mode)) {
563 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
566 return gen_binop(env, op1, op2, new_rd_ia32_And);
573 * Creates an ia32 Or.
575 * @param env The transformation environment
576 * @param op1 The first operator
577 * @param op2 The second operator
578 * @return The created ia32 Or node
580 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
581 if (mode_is_float(env->mode)) {
582 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
585 return gen_binop(env, op1, op2, new_rd_ia32_Or);
592 * Creates an ia32 Eor.
594 * @param env The transformation environment
595 * @param op1 The first operator
596 * @param op2 The second operator
597 * @return The created ia32 Eor node
599 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
600 if (mode_is_float(env->mode)) {
601 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
604 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
611 * Creates an ia32 Max.
613 * @param env The transformation environment
614 * @param op1 The first operator
615 * @param op2 The second operator
616 * @return the created ia32 Max node
618 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
621 if (mode_is_float(env->mode)) {
622 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
625 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
626 set_ia32_am_support(new_op, ia32_am_None);
627 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
636 * Creates an ia32 Min.
638 * @param env The transformation environment
639 * @param op1 The first operator
640 * @param op2 The second operator
641 * @return the created ia32 Min node
643 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
646 if (mode_is_float(env->mode)) {
647 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
650 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
651 set_ia32_am_support(new_op, ia32_am_None);
652 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
661 * Creates an ia32 Sub with immediate.
663 * @param env The transformation environment
664 * @param op1 The first operator
665 * @param op2 The second operator
666 * @return The created ia32 Sub node
668 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
669 ir_node *new_op = NULL;
670 tarval *tv = get_ia32_Immop_tarval(const_op);
671 firm_dbg_module_t *mod = env->mod;
672 dbg_info *dbg = env->dbg;
673 ir_graph *irg = env->irg;
674 ir_node *block = env->block;
675 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
676 ir_node *nomem = new_NoMem();
678 tarval_classification_t class_tv, class_negtv;
680 /* try to optimize to inc/dec */
681 if (env->cg->opt.incdec && tv) {
682 /* optimize tarvals */
683 class_tv = classify_tarval(tv);
684 class_negtv = classify_tarval(tarval_neg(tv));
686 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
687 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
688 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
691 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
692 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
693 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
699 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
700 set_ia32_Immop_attr(new_op, const_op);
707 * Creates an ia32 Sub.
709 * @param env The transformation environment
710 * @param op1 The first operator
711 * @param op2 The second operator
712 * @return The created ia32 Sub node
714 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
715 ir_node *new_op = NULL;
716 dbg_info *dbg = env->dbg;
717 ir_mode *mode = env->mode;
718 ir_graph *irg = env->irg;
719 ir_node *block = env->block;
720 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
721 ir_node *nomem = new_NoMem();
722 ir_node *expr_op, *imm_op;
724 /* Check if immediate optimization is on and */
725 /* if it's an operation with immediate. */
726 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
727 expr_op = get_expr_op(op1, op2);
729 assert((expr_op || imm_op) && "invalid operands");
731 if (mode_is_float(mode)) {
732 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
737 /* No expr_op means, that we have two const - one symconst and */
738 /* one tarval or another symconst - because this case is not */
739 /* covered by constant folding */
741 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
742 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
743 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
746 set_ia32_am_support(new_op, ia32_am_Source);
747 set_ia32_op_type(new_op, ia32_AddrModeS);
748 set_ia32_am_flavour(new_op, ia32_am_O);
750 /* Lea doesn't need a Proj */
754 /* This is expr - const */
755 new_op = gen_imm_Sub(env, expr_op, imm_op);
758 set_ia32_am_support(new_op, ia32_am_Dest);
761 /* This is a normal sub */
762 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
765 set_ia32_am_support(new_op, ia32_am_Full);
769 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
771 set_ia32_res_mode(new_op, mode);
773 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
776 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
777 const ir_edge_t *edge;
779 assert(get_irn_mode(irn) == mode_T && "need mode_T");
781 foreach_out_edge(irn, edge) {
782 proj = get_edge_src_irn(edge);
784 if (get_Proj_proj(proj) == pn)
792 * Generates an ia32 DivMod with additional infrastructure for the
793 * register allocator if needed.
795 * @param env The transformation environment
796 * @param dividend -no comment- :)
797 * @param divisor -no comment- :)
798 * @param dm_flav flavour_Div/Mod/DivMod
799 * @return The created ia32 DivMod node
801 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
803 ir_node *edx_node, *cltd;
805 dbg_info *dbg = env->dbg;
806 ir_graph *irg = env->irg;
807 ir_node *block = env->block;
808 ir_mode *mode = env->mode;
809 ir_node *irn = env->irn;
814 mem = get_Div_mem(irn);
815 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
818 mem = get_Mod_mem(irn);
819 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
822 mem = get_DivMod_mem(irn);
823 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
829 if (mode_is_signed(mode)) {
830 /* in signed mode, we need to sign extend the dividend */
831 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
832 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
833 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
836 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
837 set_ia32_Const_type(edx_node, ia32_Const);
838 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
841 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
843 set_ia32_flavour(res, dm_flav);
844 set_ia32_n_res(res, 2);
846 /* Only one proj is used -> We must add a second proj and */
847 /* connect this one to a Keep node to eat up the second */
848 /* destroyed register. */
849 if (get_irn_n_edges(irn) == 1) {
850 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
851 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
853 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
854 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
857 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
863 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
865 set_ia32_res_mode(res, mode_Is);
872 * Wrapper for generate_DivMod. Sets flavour_Mod.
874 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
875 return generate_DivMod(env, op1, op2, flavour_Mod);
881 * Wrapper for generate_DivMod. Sets flavour_Div.
883 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
884 return generate_DivMod(env, op1, op2, flavour_Div);
890 * Wrapper for generate_DivMod. Sets flavour_DivMod.
892 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
893 return generate_DivMod(env, op1, op2, flavour_DivMod);
899 * Creates an ia32 floating Div.
901 * @param env The transformation environment
902 * @param op1 The first operator
903 * @param op2 The second operator
904 * @return The created ia32 fDiv node
906 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
907 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
908 ir_node *nomem = new_rd_NoMem(env->irg);
911 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
912 set_ia32_am_support(new_op, ia32_am_Source);
914 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
922 * Creates an ia32 Shl.
924 * @param env The transformation environment
925 * @param op1 The first operator
926 * @param op2 The second operator
927 * @return The created ia32 Shl node
929 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
930 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
936 * Creates an ia32 Shr.
938 * @param env The transformation environment
939 * @param op1 The first operator
940 * @param op2 The second operator
941 * @return The created ia32 Shr node
943 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
944 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
950 * Creates an ia32 Shrs.
952 * @param env The transformation environment
953 * @param op1 The first operator
954 * @param op2 The second operator
955 * @return The created ia32 Shrs node
957 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
958 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
964 * Creates an ia32 RotL.
966 * @param env The transformation environment
967 * @param op1 The first operator
968 * @param op2 The second operator
969 * @return The created ia32 RotL node
971 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
972 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
978 * Creates an ia32 RotR.
979 * NOTE: There is no RotR with immediate because this would always be a RotL
980 * "imm-mode_size_bits" which can be pre-calculated.
982 * @param env The transformation environment
983 * @param op1 The first operator
984 * @param op2 The second operator
985 * @return The created ia32 RotR node
987 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
988 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
994 * Creates an ia32 RotR or RotL (depending on the found pattern).
996 * @param env The transformation environment
997 * @param op1 The first operator
998 * @param op2 The second operator
999 * @return The created ia32 RotL or RotR node
1001 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1002 ir_node *rotate = NULL;
1004 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1005 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1006 that means we can create a RotR instead of an Add and a RotL */
1009 ir_node *pred = get_Proj_pred(op2);
1011 if (is_ia32_Add(pred)) {
1012 ir_node *pred_pred = get_irn_n(pred, 2);
1013 tarval *tv = get_ia32_Immop_tarval(pred);
1014 long bits = get_mode_size_bits(env->mode);
1016 if (is_Proj(pred_pred)) {
1017 pred_pred = get_Proj_pred(pred_pred);
1020 if (is_ia32_Minus(pred_pred) &&
1021 tarval_is_long(tv) &&
1022 get_tarval_long(tv) == bits)
1024 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1025 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1032 rotate = gen_RotL(env, op1, op2);
1041 * Transforms a Minus node.
1043 * @param env The transformation environment
1044 * @param op The operator
1045 * @return The created ia32 Minus node
1047 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1050 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1051 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1052 ir_node *nomem = new_rd_NoMem(env->irg);
1055 if (mode_is_float(env->mode)) {
1056 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1058 size = get_mode_size_bits(env->mode);
1059 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1061 set_ia32_sc(new_op, name);
1063 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1065 set_ia32_res_mode(new_op, env->mode);
1067 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1070 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1079 * Transforms a Not node.
1081 * @param env The transformation environment
1082 * @param op The operator
1083 * @return The created ia32 Not node
1085 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1088 if (mode_is_float(env->mode)) {
1092 new_op = gen_unop(env, op, new_rd_ia32_Not);
1101 * Transforms an Abs node.
1103 * @param env The transformation environment
1104 * @param op The operator
1105 * @return The created ia32 Abs node
1107 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1108 ir_node *res, *p_eax, *p_edx;
1109 dbg_info *dbg = env->dbg;
1110 ir_mode *mode = env->mode;
1111 ir_graph *irg = env->irg;
1112 ir_node *block = env->block;
1113 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1114 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1115 ir_node *nomem = new_NoMem();
1119 if (mode_is_float(mode)) {
1120 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1122 size = get_mode_size_bits(mode);
1123 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1125 set_ia32_sc(res, name);
1127 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1129 set_ia32_res_mode(res, mode);
1131 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1134 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1135 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1136 set_ia32_res_mode(res, mode);
1138 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1139 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1141 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1142 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1143 set_ia32_res_mode(res, mode);
1145 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1147 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1148 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1149 set_ia32_res_mode(res, mode);
1151 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1160 * Transforms a Load.
1162 * @param mod the debug module
1163 * @param block the block the new node should belong to
1164 * @param node the ir Load node
1165 * @param mode node mode
1166 * @return the created ia32 Load node
1168 static ir_node *gen_Load(ia32_transform_env_t *env) {
1169 ir_node *node = env->irn;
1170 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1173 if (mode_is_float(env->mode)) {
1174 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1177 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1180 set_ia32_am_support(new_op, ia32_am_Source);
1181 set_ia32_op_type(new_op, ia32_AddrModeS);
1182 set_ia32_am_flavour(new_op, ia32_B);
1183 set_ia32_ls_mode(new_op, get_Load_mode(node));
1185 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1193 * Transforms a Store.
1195 * @param mod the debug module
1196 * @param block the block the new node should belong to
1197 * @param node the ir Store node
1198 * @param mode node mode
1199 * @return the created ia32 Store node
1201 static ir_node *gen_Store(ia32_transform_env_t *env) {
1202 ir_node *node = env->irn;
1203 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1204 ir_node *val = get_Store_value(node);
1205 ir_node *ptr = get_Store_ptr(node);
1206 ir_node *mem = get_Store_mem(node);
1207 ir_mode *mode = get_irn_mode(val);
1208 ir_node *sval = val;
1211 /* in case of storing a const (but not a symconst) -> make it an attribute */
1212 if (is_ia32_Const(val) && get_ia32_op_type(val) == ia32_Const) {
1216 if (mode_is_float(mode)) {
1217 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1219 else if (get_mode_size_bits(mode) == 8) {
1220 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1223 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1226 /* stored const is an attribute (saves a register) */
1227 if (is_ia32_Const(val) && get_ia32_op_type(val) == ia32_Const) {
1228 set_ia32_Immop_attr(new_op, val);
1231 set_ia32_am_support(new_op, ia32_am_Dest);
1232 set_ia32_op_type(new_op, ia32_AddrModeD);
1233 set_ia32_am_flavour(new_op, ia32_B);
1234 set_ia32_ls_mode(new_op, get_irn_mode(val));
1236 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1244 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1246 * @param env The transformation environment
1247 * @return The transformed node.
1249 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1250 dbg_info *dbg = env->dbg;
1251 ir_graph *irg = env->irg;
1252 ir_node *block = env->block;
1253 ir_node *node = env->irn;
1254 ir_node *sel = get_Cond_selector(node);
1255 ir_mode *sel_mode = get_irn_mode(sel);
1256 ir_node *res = NULL;
1257 ir_node *pred = NULL;
1258 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1259 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1261 if (is_Proj(sel) && sel_mode == mode_b) {
1262 ir_node *nomem = new_NoMem();
1264 pred = get_Proj_pred(sel);
1266 /* get both compare operators */
1267 cmp_a = get_Cmp_left(pred);
1268 cmp_b = get_Cmp_right(pred);
1270 /* check if we can use a CondJmp with immediate */
1271 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1272 expr = get_expr_op(cmp_a, cmp_b);
1275 if (mode_is_int(get_irn_mode(expr))) {
1276 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1278 ir_node *op1 = expr;
1279 ir_node *op2 = expr;
1280 ir_node *and = skip_Proj(expr);
1283 /* check, if expr is an only once used And operation */
1284 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1285 op1 = get_irn_n(and, 2);
1286 op2 = get_irn_n(and, 3);
1288 cnst = get_ia32_cnst(and);
1290 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1291 set_ia32_pncode(res, get_Proj_proj(sel));
1294 copy_ia32_Immop_attr(res, and);
1297 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1301 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1302 set_ia32_Immop_attr(res, cnst);
1305 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1308 set_ia32_pncode(res, get_Proj_proj(sel));
1309 set_ia32_am_support(res, ia32_am_Source);
1312 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1313 set_ia32_pncode(res, get_Cond_defaultProj(node));
1316 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1323 * Transforms a CopyB node.
1325 * @param env The transformation environment
1326 * @return The transformed node.
1328 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1329 ir_node *res = NULL;
1330 dbg_info *dbg = env->dbg;
1331 ir_graph *irg = env->irg;
1332 ir_mode *mode = env->mode;
1333 ir_node *block = env->block;
1334 ir_node *node = env->irn;
1335 ir_node *src = get_CopyB_src(node);
1336 ir_node *dst = get_CopyB_dst(node);
1337 ir_node *mem = get_CopyB_mem(node);
1338 int size = get_type_size_bytes(get_CopyB_type(node));
1341 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1342 /* then we need the size explicitly in ECX. */
1343 if (size >= 16 * 4) {
1344 rem = size & 0x3; /* size % 4 */
1347 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1348 set_ia32_op_type(res, ia32_Const);
1349 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1351 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1352 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1355 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1356 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1359 SET_IA32_ORIG_NODE(res, get_old_node_name(env));
1367 * Transforms a Mux node into CMov.
1369 * @param env The transformation environment
1370 * @return The transformed node.
1372 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1373 ir_node *node = env->irn;
1374 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1375 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1377 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1384 * Following conversion rules apply:
1388 * 1) n bit -> m bit n < m (upscale)
1390 * 2) n bit -> m bit n == m (sign change)
1392 * 3) n bit -> m bit n > m (downscale)
1393 * a) Un -> Um = AND Un, (1 << m) - 1
1394 * b) Sn -> Um same as a)
1395 * c) Un -> Sm same as a)
1396 * d) Sn -> Sm = ASHL Sn, (n - m); ASHR Sn, (n - m)
1400 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1404 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1405 * if target mode < 32bit: additional INT -> INT conversion (see above)
1409 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1412 static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1413 ir_mode *src_mode, ir_mode *tgt_mode)
1415 int n = get_mode_size_bits(src_mode);
1416 int m = get_mode_size_bits(tgt_mode);
1417 dbg_info *dbg = env->dbg;
1418 ir_graph *irg = env->irg;
1419 ir_node *block = env->block;
1420 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1421 ir_node *nomem = new_rd_NoMem(irg);
1422 ir_node *new_op, *proj;
1424 assert(n > m && "downscale expected");
1426 if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1427 /* ASHL Sn, n - m */
1428 new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1429 proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1430 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1431 set_ia32_am_support(new_op, ia32_am_Source);
1432 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1434 /* ASHR Sn, n - m */
1435 new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1436 set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1439 new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1440 set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1447 * Transforms a Conv node.
1449 * @param env The transformation environment
1450 * @param op The operator
1451 * @return The created ia32 Conv node
1453 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1454 dbg_info *dbg = env->dbg;
1455 ir_graph *irg = env->irg;
1456 ir_mode *src_mode = get_irn_mode(op);
1457 ir_mode *tgt_mode = env->mode;
1458 ir_node *block = env->block;
1459 ir_node *new_op = NULL;
1460 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1461 ir_node *nomem = new_rd_NoMem(irg);
1462 firm_dbg_module_t *mod = env->mod;
1465 if (src_mode == tgt_mode) {
1466 /* this can happen when changing mode_P to mode_Is */
1467 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1468 edges_reroute(env->irn, op, irg);
1470 else if (mode_is_float(src_mode)) {
1471 /* we convert from float ... */
1472 if (mode_is_float(tgt_mode)) {
1474 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1475 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1479 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1480 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1481 /* if target mode is not int: add an additional downscale convert */
1482 if (get_mode_size_bits(tgt_mode) < 32) {
1483 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1484 set_ia32_res_mode(new_op, tgt_mode);
1485 set_ia32_am_support(new_op, ia32_am_Source);
1487 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1488 new_op = gen_int_downscale_conv(env, proj, src_mode, tgt_mode);
1493 /* we convert from int ... */
1494 if (mode_is_float(tgt_mode)) {
1496 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1497 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1501 if (get_mode_size_bits(src_mode) <= get_mode_size_bits(tgt_mode)) {
1502 DB((mod, LEVEL_1, "omitting upscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1503 edges_reroute(env->irn, op, irg);
1506 DB((mod, LEVEL_1, "create downscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
1507 new_op = gen_int_downscale_conv(env, op, src_mode, tgt_mode);
1513 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1514 set_ia32_res_mode(new_op, tgt_mode);
1516 set_ia32_am_support(new_op, ia32_am_Source);
1518 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1526 /********************************************
1529 * | |__ ___ _ __ ___ __| | ___ ___
1530 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1531 * | |_) | __/ | | | (_) | (_| | __/\__ \
1532 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1534 ********************************************/
1536 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1537 ir_node *new_op = NULL;
1538 ir_node *node = env->irn;
1539 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1540 ir_node *mem = new_rd_NoMem(env->irg);
1541 ir_node *ptr = get_irn_n(node, 0);
1542 entity *ent = be_get_frame_entity(node);
1543 ir_mode *mode = env->mode;
1545 if (mode_is_float(mode)) {
1546 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1549 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1552 set_ia32_frame_ent(new_op, ent);
1553 set_ia32_use_frame(new_op);
1555 set_ia32_am_support(new_op, ia32_am_Source);
1556 set_ia32_op_type(new_op, ia32_AddrModeS);
1557 set_ia32_am_flavour(new_op, ia32_B);
1558 set_ia32_ls_mode(new_op, mode);
1560 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1562 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1566 * Transforms a FrameAddr into an ia32 Add.
1568 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1569 ir_node *new_op = NULL;
1570 ir_node *node = env->irn;
1571 ir_node *op = get_irn_n(node, 0);
1572 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1573 ir_node *nomem = new_rd_NoMem(env->irg);
1575 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1576 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1577 set_ia32_am_support(new_op, ia32_am_Full);
1578 set_ia32_use_frame(new_op);
1580 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1582 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1586 * Transforms a FrameLoad into an ia32 Load.
1588 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1589 ir_node *new_op = NULL;
1590 ir_node *node = env->irn;
1591 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1592 ir_node *mem = get_irn_n(node, 0);
1593 ir_node *ptr = get_irn_n(node, 1);
1594 entity *ent = be_get_frame_entity(node);
1595 ir_mode *mode = get_type_mode(get_entity_type(ent));
1597 if (mode_is_float(mode)) {
1598 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1601 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1604 set_ia32_frame_ent(new_op, ent);
1605 set_ia32_use_frame(new_op);
1607 set_ia32_am_support(new_op, ia32_am_Source);
1608 set_ia32_op_type(new_op, ia32_AddrModeS);
1609 set_ia32_am_flavour(new_op, ia32_B);
1610 set_ia32_ls_mode(new_op, mode);
1612 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1619 * Transforms a FrameStore into an ia32 Store.
1621 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1622 ir_node *new_op = NULL;
1623 ir_node *node = env->irn;
1624 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1625 ir_node *mem = get_irn_n(node, 0);
1626 ir_node *ptr = get_irn_n(node, 1);
1627 ir_node *val = get_irn_n(node, 2);
1628 entity *ent = be_get_frame_entity(node);
1629 ir_mode *mode = get_irn_mode(val);
1631 if (mode_is_float(mode)) {
1632 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1634 else if (get_mode_size_bits(mode) == 8) {
1635 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1638 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1641 set_ia32_frame_ent(new_op, ent);
1642 set_ia32_use_frame(new_op);
1644 set_ia32_am_support(new_op, ia32_am_Dest);
1645 set_ia32_op_type(new_op, ia32_AddrModeD);
1646 set_ia32_am_flavour(new_op, ia32_B);
1647 set_ia32_ls_mode(new_op, mode);
1649 SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
1656 /*********************************************************
1659 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1660 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1661 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1662 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1664 *********************************************************/
1667 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1668 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1670 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1671 ia32_transform_env_t tenv;
1672 ir_node *in1, *in2, *noreg, *nomem, *res;
1673 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1675 /* Return if AM node or not a Sub or fSub */
1676 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1679 noreg = ia32_new_NoReg_gp(cg);
1680 nomem = new_rd_NoMem(cg->irg);
1681 in1 = get_irn_n(irn, 2);
1682 in2 = get_irn_n(irn, 3);
1683 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1684 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1685 out_reg = get_ia32_out_reg(irn, 0);
1687 tenv.block = get_nodes_block(irn);
1688 tenv.dbg = get_irn_dbg_info(irn);
1692 tenv.mode = get_ia32_res_mode(irn);
1695 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1696 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1697 /* generate the neg src2 */
1698 res = gen_Minus(&tenv, in2);
1699 arch_set_irn_register(cg->arch_env, res, in2_reg);
1701 /* add to schedule */
1702 sched_add_before(irn, res);
1704 /* generate the add */
1705 if (mode_is_float(tenv.mode)) {
1706 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1707 set_ia32_am_support(res, ia32_am_Source);
1710 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1711 set_ia32_am_support(res, ia32_am_Full);
1714 SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
1716 slots = get_ia32_slots(res);
1719 /* add to schedule */
1720 sched_add_before(irn, res);
1722 /* remove the old sub */
1725 /* exchange the add and the sub */
1731 * Transforms the given firm node (and maybe some other related nodes)
1732 * into one or more assembler nodes.
1734 * @param node the firm node
1735 * @param env the debug module
1737 void ia32_transform_node(ir_node *node, void *env) {
1738 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1740 ir_node *asm_node = NULL;
1741 ia32_transform_env_t tenv;
1746 tenv.block = get_nodes_block(node);
1747 tenv.dbg = get_irn_dbg_info(node);
1748 tenv.irg = current_ir_graph;
1750 tenv.mod = cgenv->mod;
1751 tenv.mode = get_irn_mode(node);
1754 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1755 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1756 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1757 #define IGN(a) case iro_##a: break
1758 #define BAD(a) case iro_##a: goto bad
1759 #define OTHER_BIN(a) \
1760 if (get_irn_op(node) == get_op_##a()) { \
1761 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1765 if (be_is_##a(node)) { \
1766 asm_node = gen_##a(&tenv); \
1770 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1772 code = get_irn_opcode(node);
1818 /* constant transformation happens earlier */
1848 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1852 /* exchange nodes if a new one was generated */
1854 exchange(node, asm_node);
1855 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1858 DB((tenv.mod, LEVEL_1, "ignored\n"));