2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
90 static ir_node *initial_fpcw = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *old_block = get_nodes_block(node);
270 ir_node *block = be_transform_node(old_block);
271 dbg_info *dbgi = get_irn_dbg_info(node);
272 ir_mode *mode = get_irn_mode(node);
274 if (mode_is_float(mode)) {
276 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
277 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *old_block = get_nodes_block(node);
350 ir_node *block = be_transform_node(old_block);
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 set_ia32_ls_mode(new_node, mode);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
562 static ir_node *get_fpcw(void)
565 if(initial_fpcw != NULL)
568 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
569 &ia32_fp_cw_regs[REG_FPCW]);
570 initial_fpcw = be_transform_node(fpcw);
576 * Construct a standard binary operation, set AM and immediate if required.
578 * @param op1 The first operand
579 * @param op2 The second operand
580 * @param func The node constructor function
581 * @return The constructed ia32 node.
583 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
584 construct_binop_float_func *func)
586 ir_node *block = be_transform_node(get_nodes_block(node));
587 ir_node *new_op1 = be_transform_node(op1);
588 ir_node *new_op2 = be_transform_node(op2);
589 ir_node *new_node = NULL;
590 dbg_info *dbgi = get_irn_dbg_info(node);
591 ir_graph *irg = current_ir_graph;
592 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
593 ir_node *nomem = new_NoMem();
595 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
597 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
598 if (is_op_commutative(get_irn_op(node))) {
599 set_ia32_commutative(new_node);
602 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
608 * Construct a shift/rotate binary operation, sets AM and immediate if required.
610 * @param op1 The first operand
611 * @param op2 The second operand
612 * @param func The node constructor function
613 * @return The constructed ia32 node.
615 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
616 construct_binop_func *func)
618 ir_node *block = be_transform_node(get_nodes_block(node));
619 ir_node *new_op1 = be_transform_node(op1);
621 ir_node *new_op = NULL;
622 dbg_info *dbgi = get_irn_dbg_info(node);
623 ir_graph *irg = current_ir_graph;
624 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
625 ir_node *nomem = new_NoMem();
627 assert(! mode_is_float(get_irn_mode(node))
628 && "Shift/Rotate with float not supported");
630 new_op2 = create_immediate_or_transform(op2, 'N');
632 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
635 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
637 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
639 set_ia32_emit_cl(new_op);
646 * Construct a standard unary operation, set AM and immediate if required.
648 * @param op The operand
649 * @param func The node constructor function
650 * @return The constructed ia32 node.
652 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
654 ir_node *block = be_transform_node(get_nodes_block(node));
655 ir_node *new_op = be_transform_node(op);
656 ir_node *new_node = NULL;
657 ir_graph *irg = current_ir_graph;
658 dbg_info *dbgi = get_irn_dbg_info(node);
659 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
660 ir_node *nomem = new_NoMem();
662 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
663 DB((dbg, LEVEL_1, "INT unop ..."));
664 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
666 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
672 * Creates an ia32 Add.
674 * @return the created ia32 Add node
676 static ir_node *gen_Add(ir_node *node) {
677 ir_node *block = be_transform_node(get_nodes_block(node));
678 ir_node *op1 = get_Add_left(node);
679 ir_node *new_op1 = be_transform_node(op1);
680 ir_node *op2 = get_Add_right(node);
681 ir_node *new_op2 = be_transform_node(op2);
682 ir_node *new_op = NULL;
683 ir_graph *irg = current_ir_graph;
684 dbg_info *dbgi = get_irn_dbg_info(node);
685 ir_mode *mode = get_irn_mode(node);
686 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
687 ir_node *nomem = new_NoMem();
688 ir_node *expr_op, *imm_op;
690 /* Check if immediate optimization is on and */
691 /* if it's an operation with immediate. */
692 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
693 expr_op = get_expr_op(new_op1, new_op2);
695 assert((expr_op || imm_op) && "invalid operands");
697 if (mode_is_float(mode)) {
698 if (USE_SSE2(env_cg))
699 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
701 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
706 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
707 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
709 /* No expr_op means, that we have two const - one symconst and */
710 /* one tarval or another symconst - because this case is not */
711 /* covered by constant folding */
712 /* We need to check for: */
713 /* 1) symconst + const -> becomes a LEA */
714 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
715 /* linker doesn't support two symconsts */
717 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
718 /* this is the 2nd case */
719 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
720 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
721 set_ia32_am_flavour(new_op, ia32_am_B);
722 set_ia32_op_type(new_op, ia32_AddrModeS);
724 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
725 } else if (tp1 == ia32_ImmSymConst) {
726 tarval *tv = get_ia32_Immop_tarval(new_op2);
727 long offs = get_tarval_long(tv);
729 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
730 add_irn_dep(new_op, get_irg_frame(irg));
731 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
733 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
734 add_ia32_am_offs_int(new_op, offs);
735 set_ia32_am_flavour(new_op, ia32_am_OB);
736 set_ia32_op_type(new_op, ia32_AddrModeS);
737 } else if (tp2 == ia32_ImmSymConst) {
738 tarval *tv = get_ia32_Immop_tarval(new_op1);
739 long offs = get_tarval_long(tv);
741 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
742 add_irn_dep(new_op, get_irg_frame(irg));
743 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
745 add_ia32_am_offs_int(new_op, offs);
746 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
747 set_ia32_am_flavour(new_op, ia32_am_OB);
748 set_ia32_op_type(new_op, ia32_AddrModeS);
750 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
751 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
752 tarval *restv = tarval_add(tv1, tv2);
754 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
756 new_op = new_rd_ia32_Const(dbgi, irg, block);
757 set_ia32_Const_tarval(new_op, restv);
758 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
761 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
764 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
765 tarval_classification_t class_tv, class_negtv;
766 tarval *tv = get_ia32_Immop_tarval(imm_op);
768 /* optimize tarvals */
769 class_tv = classify_tarval(tv);
770 class_negtv = classify_tarval(tarval_neg(tv));
772 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
773 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
774 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
775 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
777 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
778 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
779 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
780 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
786 /* This is a normal add */
787 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
790 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
791 set_ia32_commutative(new_op);
793 fold_immediate(new_op, 2, 3);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
801 * Creates an ia32 Mul.
803 * @return the created ia32 Mul node
805 static ir_node *gen_Mul(ir_node *node) {
806 ir_node *op1 = get_Mul_left(node);
807 ir_node *op2 = get_Mul_right(node);
808 ir_mode *mode = get_irn_mode(node);
810 if (mode_is_float(mode)) {
811 if (USE_SSE2(env_cg))
812 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
814 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
818 for the lower 32bit of the result it doesn't matter whether we use
819 signed or unsigned multiplication so we use IMul as it has fewer
822 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
826 * Creates an ia32 Mulh.
827 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
828 * this result while Mul returns the lower 32 bit.
830 * @return the created ia32 Mulh node
832 static ir_node *gen_Mulh(ir_node *node) {
833 ir_node *block = be_transform_node(get_nodes_block(node));
834 ir_node *op1 = get_irn_n(node, 0);
835 ir_node *new_op1 = be_transform_node(op1);
836 ir_node *op2 = get_irn_n(node, 1);
837 ir_node *new_op2 = be_transform_node(op2);
838 ir_graph *irg = current_ir_graph;
839 dbg_info *dbgi = get_irn_dbg_info(node);
840 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
841 ir_mode *mode = get_irn_mode(node);
842 ir_node *proj_EDX, *res;
844 assert(!mode_is_float(mode) && "Mulh with float not supported");
845 if (mode_is_signed(mode)) {
846 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
847 new_op2, new_NoMem());
849 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
853 set_ia32_commutative(res);
854 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
856 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
864 * Creates an ia32 And.
866 * @return The created ia32 And node
868 static ir_node *gen_And(ir_node *node) {
869 ir_node *op1 = get_And_left(node);
870 ir_node *op2 = get_And_right(node);
872 assert (! mode_is_float(get_irn_mode(node)));
873 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
879 * Creates an ia32 Or.
881 * @return The created ia32 Or node
883 static ir_node *gen_Or(ir_node *node) {
884 ir_node *op1 = get_Or_left(node);
885 ir_node *op2 = get_Or_right(node);
887 assert (! mode_is_float(get_irn_mode(node)));
888 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
894 * Creates an ia32 Eor.
896 * @return The created ia32 Eor node
898 static ir_node *gen_Eor(ir_node *node) {
899 ir_node *op1 = get_Eor_left(node);
900 ir_node *op2 = get_Eor_right(node);
902 assert(! mode_is_float(get_irn_mode(node)));
903 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
908 * Creates an ia32 Sub.
910 * @return The created ia32 Sub node
912 static ir_node *gen_Sub(ir_node *node) {
913 ir_node *block = be_transform_node(get_nodes_block(node));
914 ir_node *op1 = get_Sub_left(node);
915 ir_node *new_op1 = be_transform_node(op1);
916 ir_node *op2 = get_Sub_right(node);
917 ir_node *new_op2 = be_transform_node(op2);
918 ir_node *new_op = NULL;
919 ir_graph *irg = current_ir_graph;
920 dbg_info *dbgi = get_irn_dbg_info(node);
921 ir_mode *mode = get_irn_mode(node);
922 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
923 ir_node *nomem = new_NoMem();
924 ir_node *expr_op, *imm_op;
926 /* Check if immediate optimization is on and */
927 /* if it's an operation with immediate. */
928 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
929 expr_op = get_expr_op(new_op1, new_op2);
931 assert((expr_op || imm_op) && "invalid operands");
933 if (mode_is_float(mode)) {
934 if (USE_SSE2(env_cg))
935 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
937 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
942 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
943 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
945 /* No expr_op means, that we have two const - one symconst and */
946 /* one tarval or another symconst - because this case is not */
947 /* covered by constant folding */
948 /* We need to check for: */
949 /* 1) symconst - const -> becomes a LEA */
950 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
951 /* linker doesn't support two symconsts */
952 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
953 /* this is the 2nd case */
954 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
955 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
956 set_ia32_am_sc_sign(new_op);
957 set_ia32_am_flavour(new_op, ia32_am_B);
959 DBG_OPT_LEA3(op1, op2, node, new_op);
960 } else if (tp1 == ia32_ImmSymConst) {
961 tarval *tv = get_ia32_Immop_tarval(new_op2);
962 long offs = get_tarval_long(tv);
964 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
965 add_irn_dep(new_op, get_irg_frame(irg));
966 DBG_OPT_LEA3(op1, op2, node, new_op);
968 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
969 add_ia32_am_offs_int(new_op, -offs);
970 set_ia32_am_flavour(new_op, ia32_am_OB);
971 set_ia32_op_type(new_op, ia32_AddrModeS);
972 } else if (tp2 == ia32_ImmSymConst) {
973 tarval *tv = get_ia32_Immop_tarval(new_op1);
974 long offs = get_tarval_long(tv);
976 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
977 add_irn_dep(new_op, get_irg_frame(irg));
978 DBG_OPT_LEA3(op1, op2, node, new_op);
980 add_ia32_am_offs_int(new_op, offs);
981 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
982 set_ia32_am_sc_sign(new_op);
983 set_ia32_am_flavour(new_op, ia32_am_OB);
984 set_ia32_op_type(new_op, ia32_AddrModeS);
986 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
987 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
988 tarval *restv = tarval_sub(tv1, tv2);
990 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
992 new_op = new_rd_ia32_Const(dbgi, irg, block);
993 set_ia32_Const_tarval(new_op, restv);
994 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1000 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1001 tarval_classification_t class_tv, class_negtv;
1002 tarval *tv = get_ia32_Immop_tarval(imm_op);
1004 /* optimize tarvals */
1005 class_tv = classify_tarval(tv);
1006 class_negtv = classify_tarval(tarval_neg(tv));
1008 if (class_tv == TV_CLASSIFY_ONE) {
1009 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1010 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1011 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1013 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1014 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1015 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1016 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1022 /* This is a normal sub */
1023 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1025 /* set AM support */
1026 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1028 fold_immediate(new_op, 2, 3);
1030 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1038 * Generates an ia32 DivMod with additional infrastructure for the
1039 * register allocator if needed.
1041 * @param dividend -no comment- :)
1042 * @param divisor -no comment- :)
1043 * @param dm_flav flavour_Div/Mod/DivMod
1044 * @return The created ia32 DivMod node
1046 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1047 ir_node *divisor, ia32_op_flavour_t dm_flav)
1049 ir_node *block = be_transform_node(get_nodes_block(node));
1050 ir_node *new_dividend = be_transform_node(dividend);
1051 ir_node *new_divisor = be_transform_node(divisor);
1052 ir_graph *irg = current_ir_graph;
1053 dbg_info *dbgi = get_irn_dbg_info(node);
1054 ir_mode *mode = get_irn_mode(node);
1055 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1056 ir_node *res, *proj_div, *proj_mod;
1057 ir_node *sign_extension;
1058 ir_node *mem, *new_mem;
1059 ir_node *projs[pn_DivMod_max];
1062 ia32_collect_Projs(node, projs, pn_DivMod_max);
1064 proj_div = proj_mod = NULL;
1068 mem = get_Div_mem(node);
1069 mode = get_Div_resmode(node);
1070 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1071 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1074 mem = get_Mod_mem(node);
1075 mode = get_Mod_resmode(node);
1076 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1077 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1079 case flavour_DivMod:
1080 mem = get_DivMod_mem(node);
1081 mode = get_DivMod_resmode(node);
1082 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1083 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1084 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1087 panic("invalid divmod flavour!");
1089 new_mem = be_transform_node(mem);
1091 if (mode_is_signed(mode)) {
1092 /* in signed mode, we need to sign extend the dividend */
1093 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1094 add_irn_dep(produceval, get_irg_frame(irg));
1095 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1098 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1099 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1101 add_irn_dep(sign_extension, get_irg_frame(irg));
1104 if (mode_is_signed(mode)) {
1105 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1106 sign_extension, new_divisor, new_mem, dm_flav);
1108 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1109 sign_extension, new_divisor, new_mem, dm_flav);
1112 set_ia32_exc_label(res, has_exc);
1113 set_irn_pinned(res, get_irn_pinned(node));
1114 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1116 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1123 * Wrapper for generate_DivMod. Sets flavour_Mod.
1126 static ir_node *gen_Mod(ir_node *node) {
1127 return generate_DivMod(node, get_Mod_left(node),
1128 get_Mod_right(node), flavour_Mod);
1132 * Wrapper for generate_DivMod. Sets flavour_Div.
1135 static ir_node *gen_Div(ir_node *node) {
1136 return generate_DivMod(node, get_Div_left(node),
1137 get_Div_right(node), flavour_Div);
1141 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1143 static ir_node *gen_DivMod(ir_node *node) {
1144 return generate_DivMod(node, get_DivMod_left(node),
1145 get_DivMod_right(node), flavour_DivMod);
1151 * Creates an ia32 floating Div.
1153 * @return The created ia32 xDiv node
1155 static ir_node *gen_Quot(ir_node *node) {
1156 ir_node *block = be_transform_node(get_nodes_block(node));
1157 ir_node *op1 = get_Quot_left(node);
1158 ir_node *new_op1 = be_transform_node(op1);
1159 ir_node *op2 = get_Quot_right(node);
1160 ir_node *new_op2 = be_transform_node(op2);
1161 ir_graph *irg = current_ir_graph;
1162 dbg_info *dbgi = get_irn_dbg_info(node);
1163 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1164 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1167 if (USE_SSE2(env_cg)) {
1168 ir_mode *mode = get_irn_mode(op1);
1169 if (is_ia32_xConst(new_op2)) {
1170 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1171 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1172 copy_ia32_Immop_attr(new_op, new_op2);
1174 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1175 // Matze: disabled for now, spillslot coalescer fails
1176 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1178 set_ia32_ls_mode(new_op, mode);
1180 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1181 new_op2, nomem, get_fpcw());
1182 // Matze: disabled for now (spillslot coalescer fails)
1183 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
1185 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1191 * Creates an ia32 Shl.
1193 * @return The created ia32 Shl node
1195 static ir_node *gen_Shl(ir_node *node) {
1196 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1203 * Creates an ia32 Shr.
1205 * @return The created ia32 Shr node
1207 static ir_node *gen_Shr(ir_node *node) {
1208 return gen_shift_binop(node, get_Shr_left(node),
1209 get_Shr_right(node), new_rd_ia32_Shr);
1215 * Creates an ia32 Sar.
1217 * @return The created ia32 Shrs node
1219 static ir_node *gen_Shrs(ir_node *node) {
1220 ir_node *left = get_Shrs_left(node);
1221 ir_node *right = get_Shrs_right(node);
1222 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1223 tarval *tv = get_Const_tarval(right);
1224 long val = get_tarval_long(tv);
1226 /* this is a sign extension */
1227 ir_graph *irg = current_ir_graph;
1228 dbg_info *dbgi = get_irn_dbg_info(node);
1229 ir_node *block = be_transform_node(get_nodes_block(node));
1231 ir_node *new_op = be_transform_node(op);
1232 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1233 add_irn_dep(pval, get_irg_frame(irg));
1235 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1239 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1245 * Creates an ia32 RotL.
1247 * @param op1 The first operator
1248 * @param op2 The second operator
1249 * @return The created ia32 RotL node
1251 static ir_node *gen_RotL(ir_node *node,
1252 ir_node *op1, ir_node *op2) {
1253 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1259 * Creates an ia32 RotR.
1260 * NOTE: There is no RotR with immediate because this would always be a RotL
1261 * "imm-mode_size_bits" which can be pre-calculated.
1263 * @param op1 The first operator
1264 * @param op2 The second operator
1265 * @return The created ia32 RotR node
1267 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1269 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1275 * Creates an ia32 RotR or RotL (depending on the found pattern).
1277 * @return The created ia32 RotL or RotR node
1279 static ir_node *gen_Rot(ir_node *node) {
1280 ir_node *rotate = NULL;
1281 ir_node *op1 = get_Rot_left(node);
1282 ir_node *op2 = get_Rot_right(node);
1284 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1285 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1286 that means we can create a RotR instead of an Add and a RotL */
1288 if (get_irn_op(op2) == op_Add) {
1290 ir_node *left = get_Add_left(add);
1291 ir_node *right = get_Add_right(add);
1292 if (is_Const(right)) {
1293 tarval *tv = get_Const_tarval(right);
1294 ir_mode *mode = get_irn_mode(node);
1295 long bits = get_mode_size_bits(mode);
1297 if (get_irn_op(left) == op_Minus &&
1298 tarval_is_long(tv) &&
1299 get_tarval_long(tv) == bits)
1301 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1302 rotate = gen_RotR(node, op1, get_Minus_op(left));
1307 if (rotate == NULL) {
1308 rotate = gen_RotL(node, op1, op2);
1317 * Transforms a Minus node.
1319 * @param op The Minus operand
1320 * @return The created ia32 Minus node
1322 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1323 ir_node *block = be_transform_node(get_nodes_block(node));
1324 ir_graph *irg = current_ir_graph;
1325 dbg_info *dbgi = get_irn_dbg_info(node);
1326 ir_mode *mode = get_irn_mode(node);
1331 if (mode_is_float(mode)) {
1332 ir_node *new_op = be_transform_node(op);
1333 if (USE_SSE2(env_cg)) {
1334 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1335 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1336 ir_node *nomem = new_rd_NoMem(irg);
1338 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1340 size = get_mode_size_bits(mode);
1341 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1343 set_ia32_am_sc(res, ent);
1344 set_ia32_op_type(res, ia32_AddrModeS);
1345 set_ia32_ls_mode(res, mode);
1347 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1350 res = gen_unop(node, op, new_rd_ia32_Neg);
1353 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1359 * Transforms a Minus node.
1361 * @return The created ia32 Minus node
1363 static ir_node *gen_Minus(ir_node *node) {
1364 return gen_Minus_ex(node, get_Minus_op(node));
1367 static ir_node *gen_bin_Not(ir_node *node)
1369 ir_graph *irg = current_ir_graph;
1370 dbg_info *dbgi = get_irn_dbg_info(node);
1371 ir_node *block = be_transform_node(get_nodes_block(node));
1372 ir_node *op = get_Not_op(node);
1373 ir_node *new_op = be_transform_node(op);
1374 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1375 ir_node *nomem = new_NoMem();
1376 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1377 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1379 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1383 * Transforms a Not node.
1385 * @return The created ia32 Not node
1387 static ir_node *gen_Not(ir_node *node) {
1388 ir_node *op = get_Not_op(node);
1389 ir_mode *mode = get_irn_mode(node);
1391 if(mode == mode_b) {
1392 return gen_bin_Not(node);
1395 assert (! mode_is_float(get_irn_mode(node)));
1396 return gen_unop(node, op, new_rd_ia32_Not);
1402 * Transforms an Abs node.
1404 * @return The created ia32 Abs node
1406 static ir_node *gen_Abs(ir_node *node) {
1407 ir_node *block = be_transform_node(get_nodes_block(node));
1408 ir_node *op = get_Abs_op(node);
1409 ir_node *new_op = be_transform_node(op);
1410 ir_graph *irg = current_ir_graph;
1411 dbg_info *dbgi = get_irn_dbg_info(node);
1412 ir_mode *mode = get_irn_mode(node);
1413 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1414 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1415 ir_node *nomem = new_NoMem();
1420 if (mode_is_float(mode)) {
1421 if (USE_SSE2(env_cg)) {
1422 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1424 size = get_mode_size_bits(mode);
1425 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1427 set_ia32_am_sc(res, ent);
1429 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1431 set_ia32_op_type(res, ia32_AddrModeS);
1432 set_ia32_ls_mode(res, mode);
1435 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1436 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1440 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1441 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1444 add_irn_dep(pval, get_irg_frame(irg));
1445 SET_IA32_ORIG_NODE(sign_extension,
1446 ia32_get_old_node_name(env_cg, node));
1448 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1449 sign_extension, nomem);
1450 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1452 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1453 sign_extension, nomem);
1454 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1463 * Transforms a Load.
1465 * @return the created ia32 Load node
1467 static ir_node *gen_Load(ir_node *node) {
1468 ir_node *old_block = get_nodes_block(node);
1469 ir_node *block = be_transform_node(old_block);
1470 ir_node *ptr = get_Load_ptr(node);
1471 ir_node *new_ptr = be_transform_node(ptr);
1472 ir_node *mem = get_Load_mem(node);
1473 ir_node *new_mem = be_transform_node(mem);
1474 ir_graph *irg = current_ir_graph;
1475 dbg_info *dbgi = get_irn_dbg_info(node);
1476 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1477 ir_mode *mode = get_Load_mode(node);
1479 ir_node *lptr = new_ptr;
1482 ia32_am_flavour_t am_flav = ia32_am_B;
1484 /* address might be a constant (symconst or absolute address) */
1485 if (is_ia32_Const(new_ptr)) {
1490 if (mode_is_float(mode)) {
1491 if (USE_SSE2(env_cg)) {
1492 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1493 res_mode = mode_xmm;
1495 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1496 res_mode = mode_vfp;
1499 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1503 /* base is a constant address */
1505 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1506 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1507 am_flav = ia32_am_N;
1509 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1510 long offs = get_tarval_long(tv);
1512 add_ia32_am_offs_int(new_op, offs);
1513 am_flav = ia32_am_O;
1517 set_irn_pinned(new_op, get_irn_pinned(node));
1518 set_ia32_op_type(new_op, ia32_AddrModeS);
1519 set_ia32_am_flavour(new_op, am_flav);
1520 set_ia32_ls_mode(new_op, mode);
1522 /* make sure we are scheduled behind the initial IncSP/Barrier
1523 * to avoid spills being placed before it
1525 if (block == get_irg_start_block(irg)) {
1526 add_irn_dep(new_op, get_irg_frame(irg));
1529 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1530 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1538 * Transforms a Store.
1540 * @return the created ia32 Store node
1542 static ir_node *gen_Store(ir_node *node) {
1543 ir_node *block = be_transform_node(get_nodes_block(node));
1544 ir_node *ptr = get_Store_ptr(node);
1545 ir_node *new_ptr = be_transform_node(ptr);
1546 ir_node *val = get_Store_value(node);
1548 ir_node *mem = get_Store_mem(node);
1549 ir_node *new_mem = be_transform_node(mem);
1550 ir_graph *irg = current_ir_graph;
1551 dbg_info *dbgi = get_irn_dbg_info(node);
1552 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1553 ir_node *sptr = new_ptr;
1554 ir_mode *mode = get_irn_mode(val);
1557 ia32_am_flavour_t am_flav = ia32_am_B;
1559 /* address might be a constant (symconst or absolute address) */
1560 if (is_ia32_Const(new_ptr)) {
1565 if (mode_is_float(mode)) {
1566 new_val = be_transform_node(val);
1567 if (USE_SSE2(env_cg)) {
1568 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1571 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1575 new_val = create_immediate_or_transform(val, 0);
1577 if (get_mode_size_bits(mode) == 8) {
1578 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1581 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1586 /* base is an constant address */
1588 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1589 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1590 am_flav = ia32_am_N;
1592 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1593 long offs = get_tarval_long(tv);
1595 add_ia32_am_offs_int(new_op, offs);
1596 am_flav = ia32_am_O;
1600 set_irn_pinned(new_op, get_irn_pinned(node));
1601 set_ia32_op_type(new_op, ia32_AddrModeD);
1602 set_ia32_am_flavour(new_op, am_flav);
1603 set_ia32_ls_mode(new_op, mode);
1605 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1606 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1611 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1612 ir_node *cmp_left, ir_node *cmp_right)
1614 ir_node *new_cmp_left;
1615 ir_node *new_cmp_right;
1621 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1623 if(cmp_right != NULL && !is_Const_0(cmp_right))
1626 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1627 and_left = get_And_left(cmp_left);
1628 and_right = get_And_right(cmp_left);
1630 new_cmp_left = be_transform_node(and_left);
1631 new_cmp_right = create_immediate_or_transform(and_right, 0);
1633 new_cmp_left = be_transform_node(cmp_left);
1634 new_cmp_right = be_transform_node(cmp_left);
1637 noreg = ia32_new_NoReg_gp(env_cg);
1638 nomem = new_NoMem();
1640 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1641 new_cmp_left, new_cmp_right, nomem, pnc);
1642 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1647 static ir_node *create_Switch(ir_node *node)
1649 ir_graph *irg = current_ir_graph;
1650 dbg_info *dbgi = get_irn_dbg_info(node);
1651 ir_node *block = be_transform_node(get_nodes_block(node));
1652 ir_node *sel = get_Cond_selector(node);
1653 ir_node *new_sel = be_transform_node(sel);
1655 int switch_min = INT_MAX;
1656 const ir_edge_t *edge;
1658 /* determine the smallest switch case value */
1659 foreach_out_edge(node, edge) {
1660 ir_node *proj = get_edge_src_irn(edge);
1661 int pn = get_Proj_proj(proj);
1666 if (switch_min != 0) {
1667 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1669 /* if smallest switch case is not 0 we need an additional sub */
1670 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1671 add_ia32_am_offs_int(new_sel, -switch_min);
1672 set_ia32_am_flavour(new_sel, ia32_am_OB);
1673 set_ia32_op_type(new_sel, ia32_AddrModeS);
1675 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1678 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1679 set_ia32_pncode(res, get_Cond_defaultProj(node));
1681 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1687 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1689 * @return The transformed node.
1691 static ir_node *gen_Cond(ir_node *node) {
1692 ir_node *block = be_transform_node(get_nodes_block(node));
1693 ir_graph *irg = current_ir_graph;
1694 dbg_info *dbgi = get_irn_dbg_info(node);
1695 ir_node *sel = get_Cond_selector(node);
1696 ir_mode *sel_mode = get_irn_mode(sel);
1697 ir_node *res = NULL;
1698 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1705 ir_node *nomem = new_NoMem();
1708 if (sel_mode != mode_b) {
1709 return create_Switch(node);
1712 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1713 /* it's some mode_b value not a direct comparison -> create a testjmp */
1714 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1715 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1719 cmp = get_Proj_pred(sel);
1720 cmp_a = get_Cmp_left(cmp);
1721 cmp_b = get_Cmp_right(cmp);
1722 cmp_mode = get_irn_mode(cmp_a);
1723 pnc = get_Proj_proj(sel);
1724 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1725 pnc |= ia32_pn_Cmp_Unsigned;
1728 if(mode_needs_gp_reg(cmp_mode)) {
1729 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1731 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1736 new_cmp_a = be_transform_node(cmp_a);
1737 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1739 if (mode_is_float(cmp_mode)) {
1740 if (USE_SSE2(env_cg)) {
1741 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1743 set_ia32_commutative(res);
1744 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1745 set_ia32_ls_mode(res, cmp_mode);
1747 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1748 set_ia32_commutative(res);
1751 assert(get_mode_size_bits(cmp_mode) == 32);
1752 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1753 new_cmp_a, new_cmp_b, nomem, pnc);
1754 set_ia32_commutative(res);
1755 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1758 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1766 * Transforms a CopyB node.
1768 * @return The transformed node.
1770 static ir_node *gen_CopyB(ir_node *node) {
1771 ir_node *block = be_transform_node(get_nodes_block(node));
1772 ir_node *src = get_CopyB_src(node);
1773 ir_node *new_src = be_transform_node(src);
1774 ir_node *dst = get_CopyB_dst(node);
1775 ir_node *new_dst = be_transform_node(dst);
1776 ir_node *mem = get_CopyB_mem(node);
1777 ir_node *new_mem = be_transform_node(mem);
1778 ir_node *res = NULL;
1779 ir_graph *irg = current_ir_graph;
1780 dbg_info *dbgi = get_irn_dbg_info(node);
1781 int size = get_type_size_bytes(get_CopyB_type(node));
1784 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1785 /* then we need the size explicitly in ECX. */
1786 if (size >= 32 * 4) {
1787 rem = size & 0x3; /* size % 4 */
1790 res = new_rd_ia32_Const(dbgi, irg, block);
1791 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1792 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1794 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1795 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1797 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1798 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1801 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1807 ir_node *gen_be_Copy(ir_node *node)
1809 ir_node *result = be_duplicate_node(node);
1810 ir_mode *mode = get_irn_mode(result);
1812 if (mode_needs_gp_reg(mode)) {
1813 set_irn_mode(result, mode_Iu);
1820 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1821 dbg_info *dbgi, ir_node *block)
1823 ir_graph *irg = current_ir_graph;
1824 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1825 ir_node *nomem = new_rd_NoMem(irg);
1826 ir_node *new_cmp_left;
1827 ir_node *new_cmp_right;
1830 /* can we use a test instruction? */
1831 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1832 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1833 if(is_And(cmp_left) &&
1834 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1835 ir_node *and_left = get_And_left(cmp_left);
1836 ir_node *and_right = get_And_right(cmp_left);
1838 new_cmp_left = be_transform_node(and_left);
1839 new_cmp_right = create_immediate_or_transform(and_right, 0);
1841 new_cmp_left = be_transform_node(cmp_left);
1842 new_cmp_right = be_transform_node(cmp_left);
1845 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1846 new_cmp_left, new_cmp_right, nomem, pnc);
1847 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1852 new_cmp_left = be_transform_node(cmp_left);
1853 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1854 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1855 new_cmp_left, new_cmp_right, nomem, pnc);
1860 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1861 ir_node *val_true, ir_node *val_false,
1862 dbg_info *dbgi, ir_node *block)
1864 ir_graph *irg = current_ir_graph;
1865 ir_node *new_val_true = be_transform_node(val_true);
1866 ir_node *new_val_false = be_transform_node(val_false);
1867 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1868 ir_node *nomem = new_NoMem();
1869 ir_node *new_cmp_left;
1870 ir_node *new_cmp_right;
1873 /* cmovs with unknowns are pointless... */
1874 if(is_Unknown(val_true)) {
1875 #ifdef DEBUG_libfirm
1876 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1878 return new_val_false;
1880 if(is_Unknown(val_false)) {
1881 #ifdef DEBUG_libfirm
1882 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1884 return new_val_true;
1887 /* can we use a test instruction? */
1888 if(is_Const_0(cmp_right)) {
1889 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1890 if(is_And(cmp_left) &&
1891 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1892 ir_node *and_left = get_And_left(cmp_left);
1893 ir_node *and_right = get_And_right(cmp_left);
1895 new_cmp_left = be_transform_node(and_left);
1896 new_cmp_right = create_immediate_or_transform(and_right, 0);
1898 new_cmp_left = be_transform_node(cmp_left);
1899 new_cmp_right = be_transform_node(cmp_left);
1902 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1903 new_cmp_left, new_cmp_right, nomem,
1904 new_val_true, new_val_false, pnc);
1905 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1910 new_cmp_left = be_transform_node(cmp_left);
1911 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1913 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1914 new_cmp_right, nomem, new_val_true, new_val_false,
1916 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1923 * Transforms a Psi node into CMov.
1925 * @return The transformed node.
1927 static ir_node *gen_Psi(ir_node *node) {
1928 ir_node *psi_true = get_Psi_val(node, 0);
1929 ir_node *psi_default = get_Psi_default(node);
1930 ia32_code_gen_t *cg = env_cg;
1931 ir_node *cond = get_Psi_cond(node, 0);
1932 ir_node *block = be_transform_node(get_nodes_block(node));
1933 dbg_info *dbgi = get_irn_dbg_info(node);
1940 assert(get_Psi_n_conds(node) == 1);
1941 assert(get_irn_mode(cond) == mode_b);
1943 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1944 /* a mode_b value, we have to compare it against 0 */
1946 cmp_right = new_Const_long(mode_Iu, 0);
1950 ir_node *cmp = get_Proj_pred(cond);
1952 cmp_left = get_Cmp_left(cmp);
1953 cmp_right = get_Cmp_right(cmp);
1954 cmp_mode = get_irn_mode(cmp_left);
1955 pnc = get_Proj_proj(cond);
1957 assert(!mode_is_float(cmp_mode));
1959 if (!mode_is_signed(cmp_mode)) {
1960 pnc |= ia32_pn_Cmp_Unsigned;
1964 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1965 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1966 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1967 pnc = get_negated_pnc(pnc, cmp_mode);
1968 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1970 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1973 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1979 * Following conversion rules apply:
1983 * 1) n bit -> m bit n > m (downscale)
1985 * 2) n bit -> m bit n == m (sign change)
1987 * 3) n bit -> m bit n < m (upscale)
1988 * a) source is signed: movsx
1989 * b) source is unsigned: and with lower bits sets
1993 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1997 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2001 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2002 * x87 is mode_E internally, conversions happen only at load and store
2003 * in non-strict semantic
2007 * Create a conversion from x87 state register to general purpose.
2009 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2010 ir_node *block = be_transform_node(get_nodes_block(node));
2011 ir_node *op = get_Conv_op(node);
2012 ir_node *new_op = be_transform_node(op);
2013 ia32_code_gen_t *cg = env_cg;
2014 ir_graph *irg = current_ir_graph;
2015 dbg_info *dbgi = get_irn_dbg_info(node);
2016 ir_node *noreg = ia32_new_NoReg_gp(cg);
2017 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2018 ir_node *fist, *load;
2021 fist = new_rd_ia32_vfist(dbgi, irg, block,
2022 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2024 set_irn_pinned(fist, op_pin_state_floats);
2025 set_ia32_use_frame(fist);
2026 set_ia32_op_type(fist, ia32_AddrModeD);
2027 set_ia32_am_flavour(fist, ia32_am_B);
2028 set_ia32_ls_mode(fist, mode_Iu);
2029 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2032 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2034 set_irn_pinned(load, op_pin_state_floats);
2035 set_ia32_use_frame(load);
2036 set_ia32_op_type(load, ia32_AddrModeS);
2037 set_ia32_am_flavour(load, ia32_am_B);
2038 set_ia32_ls_mode(load, mode_Iu);
2039 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2041 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2044 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2046 ir_node *block = get_nodes_block(node);
2047 ir_graph *irg = current_ir_graph;
2048 dbg_info *dbgi = get_irn_dbg_info(node);
2049 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2050 ir_node *nomem = new_NoMem();
2051 ir_node *frame = get_irg_frame(irg);
2052 ir_node *store, *load;
2055 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2057 set_ia32_use_frame(store);
2058 set_ia32_op_type(store, ia32_AddrModeD);
2059 set_ia32_am_flavour(store, ia32_am_OB);
2060 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2062 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2064 set_ia32_use_frame(load);
2065 set_ia32_op_type(load, ia32_AddrModeS);
2066 set_ia32_am_flavour(load, ia32_am_OB);
2067 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2069 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2074 * Create a conversion from general purpose to x87 register
2076 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2077 ir_node *block = be_transform_node(get_nodes_block(node));
2078 ir_node *op = get_Conv_op(node);
2079 ir_node *new_op = be_transform_node(op);
2080 ir_graph *irg = current_ir_graph;
2081 dbg_info *dbgi = get_irn_dbg_info(node);
2082 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2083 ir_node *nomem = new_NoMem();
2084 ir_node *fild, *store;
2088 /* first convert to 32 bit if necessary */
2089 src_bits = get_mode_size_bits(src_mode);
2090 if (src_bits == 8) {
2091 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2092 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2093 set_ia32_ls_mode(new_op, src_mode);
2094 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2095 } else if (src_bits < 32) {
2096 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2097 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2098 set_ia32_ls_mode(new_op, src_mode);
2099 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2103 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2105 set_ia32_use_frame(store);
2106 set_ia32_op_type(store, ia32_AddrModeD);
2107 set_ia32_am_flavour(store, ia32_am_OB);
2108 set_ia32_ls_mode(store, mode_Iu);
2111 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2113 set_ia32_use_frame(fild);
2114 set_ia32_op_type(fild, ia32_AddrModeS);
2115 set_ia32_am_flavour(fild, ia32_am_OB);
2116 set_ia32_ls_mode(fild, mode_Iu);
2118 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2124 * Transforms a Conv node.
2126 * @return The created ia32 Conv node
2128 static ir_node *gen_Conv(ir_node *node) {
2129 ir_node *block = be_transform_node(get_nodes_block(node));
2130 ir_node *op = get_Conv_op(node);
2131 ir_node *new_op = be_transform_node(op);
2132 ir_graph *irg = current_ir_graph;
2133 dbg_info *dbgi = get_irn_dbg_info(node);
2134 ir_mode *src_mode = get_irn_mode(op);
2135 ir_mode *tgt_mode = get_irn_mode(node);
2136 int src_bits = get_mode_size_bits(src_mode);
2137 int tgt_bits = get_mode_size_bits(tgt_mode);
2138 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2139 ir_node *nomem = new_rd_NoMem(irg);
2142 if (src_mode == mode_b) {
2143 assert(mode_is_int(tgt_mode));
2144 /* nothing to do, we already model bools as 0/1 ints */
2148 if (src_mode == tgt_mode) {
2149 if (get_Conv_strict(node)) {
2150 if (USE_SSE2(env_cg)) {
2151 /* when we are in SSE mode, we can kill all strict no-op conversion */
2155 /* this should be optimized already, but who knows... */
2156 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2157 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2162 if (mode_is_float(src_mode)) {
2163 /* we convert from float ... */
2164 if (mode_is_float(tgt_mode)) {
2165 if(src_mode == mode_E && tgt_mode == mode_D
2166 && !get_Conv_strict(node)) {
2167 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2172 if (USE_SSE2(env_cg)) {
2173 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2174 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2175 set_ia32_ls_mode(res, tgt_mode);
2177 if(get_Conv_strict(node)) {
2178 res = create_strict_conv(tgt_mode, new_op);
2179 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2182 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2187 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2188 if (USE_SSE2(env_cg)) {
2189 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2190 set_ia32_ls_mode(res, src_mode);
2192 return gen_x87_fp_to_gp(node);
2196 /* we convert from int ... */
2197 if (mode_is_float(tgt_mode)) {
2199 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2200 if (USE_SSE2(env_cg)) {
2201 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2202 set_ia32_ls_mode(res, tgt_mode);
2203 if(src_bits == 32) {
2204 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2207 res = gen_x87_gp_to_fp(node, src_mode);
2208 if(get_Conv_strict(node)) {
2209 res = create_strict_conv(tgt_mode, res);
2210 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2211 ia32_get_old_node_name(env_cg, node));
2215 } else if(tgt_mode == mode_b) {
2218 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2220 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2225 ir_mode *smaller_mode;
2228 if (src_bits == tgt_bits) {
2229 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2230 src_mode, tgt_mode));
2234 if (src_bits < tgt_bits) {
2235 smaller_mode = src_mode;
2236 smaller_bits = src_bits;
2238 smaller_mode = tgt_mode;
2239 smaller_bits = tgt_bits;
2242 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2243 if (smaller_bits == 8) {
2244 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2245 set_ia32_ls_mode(res, smaller_mode);
2247 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2248 set_ia32_ls_mode(res, smaller_mode);
2250 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2254 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2260 int check_immediate_constraint(long val, char immediate_constraint_type)
2262 switch (immediate_constraint_type) {
2266 return val >= 0 && val <= 32;
2268 return val >= 0 && val <= 63;
2270 return val >= -128 && val <= 127;
2272 return val == 0xff || val == 0xffff;
2274 return val >= 0 && val <= 3;
2276 return val >= 0 && val <= 255;
2278 return val >= 0 && val <= 127;
2282 panic("Invalid immediate constraint found");
2287 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2290 tarval *offset = NULL;
2291 int offset_sign = 0;
2293 ir_entity *symconst_ent = NULL;
2294 int symconst_sign = 0;
2296 ir_node *cnst = NULL;
2297 ir_node *symconst = NULL;
2303 mode = get_irn_mode(node);
2304 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2308 if(is_Minus(node)) {
2310 node = get_Minus_op(node);
2313 if(is_Const(node)) {
2316 offset_sign = minus;
2317 } else if(is_SymConst(node)) {
2320 symconst_sign = minus;
2321 } else if(is_Add(node)) {
2322 ir_node *left = get_Add_left(node);
2323 ir_node *right = get_Add_right(node);
2324 if(is_Const(left) && is_SymConst(right)) {
2327 symconst_sign = minus;
2328 offset_sign = minus;
2329 } else if(is_SymConst(left) && is_Const(right)) {
2332 symconst_sign = minus;
2333 offset_sign = minus;
2335 } else if(is_Sub(node)) {
2336 ir_node *left = get_Sub_left(node);
2337 ir_node *right = get_Sub_right(node);
2338 if(is_Const(left) && is_SymConst(right)) {
2341 symconst_sign = !minus;
2342 offset_sign = minus;
2343 } else if(is_SymConst(left) && is_Const(right)) {
2346 symconst_sign = minus;
2347 offset_sign = !minus;
2354 offset = get_Const_tarval(cnst);
2355 if(tarval_is_long(offset)) {
2356 val = get_tarval_long(offset);
2357 } else if(tarval_is_null(offset)) {
2360 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2365 if(!check_immediate_constraint(val, immediate_constraint_type))
2368 if(symconst != NULL) {
2369 if(immediate_constraint_type != 0) {
2370 /* we need full 32bits for symconsts */
2374 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2376 symconst_ent = get_SymConst_entity(symconst);
2378 if(cnst == NULL && symconst == NULL)
2381 if(offset_sign && offset != NULL) {
2382 offset = tarval_neg(offset);
2385 irg = current_ir_graph;
2386 dbgi = get_irn_dbg_info(node);
2387 block = get_irg_start_block(irg);
2388 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2389 symconst_sign, val);
2390 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2396 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2398 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2399 if (new_node == NULL) {
2400 new_node = be_transform_node(node);
2405 typedef struct constraint_t constraint_t;
2406 struct constraint_t {
2409 const arch_register_req_t **out_reqs;
2411 const arch_register_req_t *req;
2412 unsigned immediate_possible;
2413 char immediate_type;
2416 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2418 int immediate_possible = 0;
2419 char immediate_type = 0;
2420 unsigned limited = 0;
2421 const arch_register_class_t *cls = NULL;
2423 struct obstack *obst;
2424 arch_register_req_t *req;
2425 unsigned *limited_ptr;
2429 /* TODO: replace all the asserts with nice error messages */
2431 printf("Constraint: %s\n", c);
2441 assert(cls == NULL ||
2442 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2443 cls = &ia32_reg_classes[CLASS_ia32_gp];
2444 limited |= 1 << REG_EAX;
2447 assert(cls == NULL ||
2448 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2449 cls = &ia32_reg_classes[CLASS_ia32_gp];
2450 limited |= 1 << REG_EBX;
2453 assert(cls == NULL ||
2454 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2455 cls = &ia32_reg_classes[CLASS_ia32_gp];
2456 limited |= 1 << REG_ECX;
2459 assert(cls == NULL ||
2460 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2461 cls = &ia32_reg_classes[CLASS_ia32_gp];
2462 limited |= 1 << REG_EDX;
2465 assert(cls == NULL ||
2466 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2467 cls = &ia32_reg_classes[CLASS_ia32_gp];
2468 limited |= 1 << REG_EDI;
2471 assert(cls == NULL ||
2472 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2473 cls = &ia32_reg_classes[CLASS_ia32_gp];
2474 limited |= 1 << REG_ESI;
2477 case 'q': /* q means lower part of the regs only, this makes no
2478 * difference to Q for us (we only assigne whole registers) */
2479 assert(cls == NULL ||
2480 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2481 cls = &ia32_reg_classes[CLASS_ia32_gp];
2482 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2486 assert(cls == NULL ||
2487 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2488 cls = &ia32_reg_classes[CLASS_ia32_gp];
2489 limited |= 1 << REG_EAX | 1 << REG_EDX;
2492 assert(cls == NULL ||
2493 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2494 cls = &ia32_reg_classes[CLASS_ia32_gp];
2495 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2496 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2503 assert(cls == NULL);
2504 cls = &ia32_reg_classes[CLASS_ia32_gp];
2510 /* TODO: mark values so the x87 simulator knows about t and u */
2511 assert(cls == NULL);
2512 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2517 assert(cls == NULL);
2518 /* TODO: check that sse2 is supported */
2519 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2529 assert(!immediate_possible);
2530 immediate_possible = 1;
2531 immediate_type = *c;
2535 assert(!immediate_possible);
2536 immediate_possible = 1;
2540 assert(!immediate_possible && cls == NULL);
2541 immediate_possible = 1;
2542 cls = &ia32_reg_classes[CLASS_ia32_gp];
2555 assert(constraint->is_in && "can only specify same constraint "
2558 sscanf(c, "%d%n", &same_as, &p);
2565 case 'E': /* no float consts yet */
2566 case 'F': /* no float consts yet */
2567 case 's': /* makes no sense on x86 */
2568 case 'X': /* we can't support that in firm */
2572 case '<': /* no autodecrement on x86 */
2573 case '>': /* no autoincrement on x86 */
2574 case 'C': /* sse constant not supported yet */
2575 case 'G': /* 80387 constant not supported yet */
2576 case 'y': /* we don't support mmx registers yet */
2577 case 'Z': /* not available in 32 bit mode */
2578 case 'e': /* not available in 32 bit mode */
2579 assert(0 && "asm constraint not supported");
2582 assert(0 && "unknown asm constraint found");
2589 const arch_register_req_t *other_constr;
2591 assert(cls == NULL && "same as and register constraint not supported");
2592 assert(!immediate_possible && "same as and immediate constraint not "
2594 assert(same_as < constraint->n_outs && "wrong constraint number in "
2595 "same_as constraint");
2597 other_constr = constraint->out_reqs[same_as];
2599 req = obstack_alloc(obst, sizeof(req[0]));
2600 req->cls = other_constr->cls;
2601 req->type = arch_register_req_type_should_be_same;
2602 req->limited = NULL;
2603 req->other_same = pos;
2604 req->other_different = -1;
2606 /* switch constraints. This is because in firm we have same_as
2607 * constraints on the output constraints while in the gcc asm syntax
2608 * they are specified on the input constraints */
2609 constraint->req = other_constr;
2610 constraint->out_reqs[same_as] = req;
2611 constraint->immediate_possible = 0;
2615 if(immediate_possible && cls == NULL) {
2616 cls = &ia32_reg_classes[CLASS_ia32_gp];
2618 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2619 assert(cls != NULL);
2621 if(immediate_possible) {
2622 assert(constraint->is_in
2623 && "imeediates make no sense for output constraints");
2625 /* todo: check types (no float input on 'r' constrainted in and such... */
2627 irg = current_ir_graph;
2628 obst = get_irg_obstack(irg);
2631 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2632 limited_ptr = (unsigned*) (req+1);
2634 req = obstack_alloc(obst, sizeof(req[0]));
2636 memset(req, 0, sizeof(req[0]));
2639 req->type = arch_register_req_type_limited;
2640 *limited_ptr = limited;
2641 req->limited = limited_ptr;
2643 req->type = arch_register_req_type_normal;
2647 constraint->req = req;
2648 constraint->immediate_possible = immediate_possible;
2649 constraint->immediate_type = immediate_type;
2653 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2660 panic("Clobbers not supported yet");
2663 ir_node *gen_ASM(ir_node *node)
2666 ir_graph *irg = current_ir_graph;
2667 ir_node *block = be_transform_node(get_nodes_block(node));
2668 dbg_info *dbgi = get_irn_dbg_info(node);
2675 ia32_asm_attr_t *attr;
2676 const arch_register_req_t **out_reqs;
2677 const arch_register_req_t **in_reqs;
2678 struct obstack *obst;
2679 constraint_t parsed_constraint;
2681 /* transform inputs */
2682 arity = get_irn_arity(node);
2683 in = alloca(arity * sizeof(in[0]));
2684 memset(in, 0, arity * sizeof(in[0]));
2686 n_outs = get_ASM_n_output_constraints(node);
2687 n_clobbers = get_ASM_n_clobbers(node);
2688 out_arity = n_outs + n_clobbers;
2690 /* construct register constraints */
2691 obst = get_irg_obstack(irg);
2692 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2693 parsed_constraint.out_reqs = out_reqs;
2694 parsed_constraint.n_outs = n_outs;
2695 parsed_constraint.is_in = 0;
2696 for(i = 0; i < out_arity; ++i) {
2700 const ir_asm_constraint *constraint;
2701 constraint = & get_ASM_output_constraints(node) [i];
2702 c = get_id_str(constraint->constraint);
2703 parse_asm_constraint(i, &parsed_constraint, c);
2705 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2706 c = get_id_str(glob_id);
2707 parse_clobber(node, i, &parsed_constraint, c);
2709 out_reqs[i] = parsed_constraint.req;
2712 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2713 parsed_constraint.is_in = 1;
2714 for(i = 0; i < arity; ++i) {
2715 const ir_asm_constraint *constraint;
2719 constraint = & get_ASM_input_constraints(node) [i];
2720 constr_id = constraint->constraint;
2721 c = get_id_str(constr_id);
2722 parse_asm_constraint(i, &parsed_constraint, c);
2723 in_reqs[i] = parsed_constraint.req;
2725 if(parsed_constraint.immediate_possible) {
2726 ir_node *pred = get_irn_n(node, i);
2727 char imm_type = parsed_constraint.immediate_type;
2728 ir_node *immediate = try_create_Immediate(pred, imm_type);
2730 if(immediate != NULL) {
2736 /* transform inputs */
2737 for(i = 0; i < arity; ++i) {
2739 ir_node *transformed;
2744 pred = get_irn_n(node, i);
2745 transformed = be_transform_node(pred);
2746 in[i] = transformed;
2749 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2751 generic_attr = get_irn_generic_attr(res);
2752 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2753 attr->asm_text = get_ASM_text(node);
2754 set_ia32_out_req_all(res, out_reqs);
2755 set_ia32_in_req_all(res, in_reqs);
2757 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2762 /********************************************
2765 * | |__ ___ _ __ ___ __| | ___ ___
2766 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2767 * | |_) | __/ | | | (_) | (_| | __/\__ \
2768 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2770 ********************************************/
2772 static ir_node *gen_be_StackParam(ir_node *node) {
2773 ir_node *block = be_transform_node(get_nodes_block(node));
2774 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2775 ir_node *new_ptr = be_transform_node(ptr);
2776 ir_node *new_op = NULL;
2777 ir_graph *irg = current_ir_graph;
2778 dbg_info *dbgi = get_irn_dbg_info(node);
2779 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2780 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2781 ir_mode *load_mode = get_irn_mode(node);
2782 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2786 if (mode_is_float(load_mode)) {
2787 if (USE_SSE2(env_cg)) {
2788 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2789 pn_res = pn_ia32_xLoad_res;
2790 proj_mode = mode_xmm;
2792 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2793 pn_res = pn_ia32_vfld_res;
2794 proj_mode = mode_vfp;
2797 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2798 proj_mode = mode_Iu;
2799 pn_res = pn_ia32_Load_res;
2802 set_irn_pinned(new_op, op_pin_state_floats);
2803 set_ia32_frame_ent(new_op, ent);
2804 set_ia32_use_frame(new_op);
2806 set_ia32_op_type(new_op, ia32_AddrModeS);
2807 set_ia32_am_flavour(new_op, ia32_am_B);
2808 set_ia32_ls_mode(new_op, load_mode);
2809 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2811 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2813 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2817 * Transforms a FrameAddr into an ia32 Add.
2819 static ir_node *gen_be_FrameAddr(ir_node *node) {
2820 ir_node *block = be_transform_node(get_nodes_block(node));
2821 ir_node *op = be_get_FrameAddr_frame(node);
2822 ir_node *new_op = be_transform_node(op);
2823 ir_graph *irg = current_ir_graph;
2824 dbg_info *dbgi = get_irn_dbg_info(node);
2825 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2828 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2829 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2830 set_ia32_use_frame(res);
2831 set_ia32_am_flavour(res, ia32_am_OB);
2833 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2839 * Transforms a FrameLoad into an ia32 Load.
2841 static ir_node *gen_be_FrameLoad(ir_node *node) {
2842 ir_node *block = be_transform_node(get_nodes_block(node));
2843 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2844 ir_node *new_mem = be_transform_node(mem);
2845 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2846 ir_node *new_ptr = be_transform_node(ptr);
2847 ir_node *new_op = NULL;
2848 ir_graph *irg = current_ir_graph;
2849 dbg_info *dbgi = get_irn_dbg_info(node);
2850 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2851 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2852 ir_mode *mode = get_type_mode(get_entity_type(ent));
2853 ir_node *projs[pn_Load_max];
2855 ia32_collect_Projs(node, projs, pn_Load_max);
2857 if (mode_is_float(mode)) {
2858 if (USE_SSE2(env_cg)) {
2859 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2862 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2866 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2869 set_irn_pinned(new_op, op_pin_state_floats);
2870 set_ia32_frame_ent(new_op, ent);
2871 set_ia32_use_frame(new_op);
2873 set_ia32_op_type(new_op, ia32_AddrModeS);
2874 set_ia32_am_flavour(new_op, ia32_am_B);
2875 set_ia32_ls_mode(new_op, mode);
2876 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2878 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2885 * Transforms a FrameStore into an ia32 Store.
2887 static ir_node *gen_be_FrameStore(ir_node *node) {
2888 ir_node *block = be_transform_node(get_nodes_block(node));
2889 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2890 ir_node *new_mem = be_transform_node(mem);
2891 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2892 ir_node *new_ptr = be_transform_node(ptr);
2893 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2894 ir_node *new_val = be_transform_node(val);
2895 ir_node *new_op = NULL;
2896 ir_graph *irg = current_ir_graph;
2897 dbg_info *dbgi = get_irn_dbg_info(node);
2898 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2899 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2900 ir_mode *mode = get_irn_mode(val);
2902 if (mode_is_float(mode)) {
2903 if (USE_SSE2(env_cg)) {
2904 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2906 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2908 } else if (get_mode_size_bits(mode) == 8) {
2909 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2911 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2914 set_ia32_frame_ent(new_op, ent);
2915 set_ia32_use_frame(new_op);
2917 set_ia32_op_type(new_op, ia32_AddrModeD);
2918 set_ia32_am_flavour(new_op, ia32_am_B);
2919 set_ia32_ls_mode(new_op, mode);
2921 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2927 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2929 static ir_node *gen_be_Return(ir_node *node) {
2930 ir_graph *irg = current_ir_graph;
2931 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2932 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2933 ir_entity *ent = get_irg_entity(irg);
2934 ir_type *tp = get_entity_type(ent);
2939 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2940 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2943 int pn_ret_val, pn_ret_mem, arity, i;
2945 assert(ret_val != NULL);
2946 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2947 return be_duplicate_node(node);
2950 res_type = get_method_res_type(tp, 0);
2952 if (! is_Primitive_type(res_type)) {
2953 return be_duplicate_node(node);
2956 mode = get_type_mode(res_type);
2957 if (! mode_is_float(mode)) {
2958 return be_duplicate_node(node);
2961 assert(get_method_n_ress(tp) == 1);
2963 pn_ret_val = get_Proj_proj(ret_val);
2964 pn_ret_mem = get_Proj_proj(ret_mem);
2966 /* get the Barrier */
2967 barrier = get_Proj_pred(ret_val);
2969 /* get result input of the Barrier */
2970 ret_val = get_irn_n(barrier, pn_ret_val);
2971 new_ret_val = be_transform_node(ret_val);
2973 /* get memory input of the Barrier */
2974 ret_mem = get_irn_n(barrier, pn_ret_mem);
2975 new_ret_mem = be_transform_node(ret_mem);
2977 frame = get_irg_frame(irg);
2979 dbgi = get_irn_dbg_info(barrier);
2980 block = be_transform_node(get_nodes_block(barrier));
2982 noreg = ia32_new_NoReg_gp(env_cg);
2984 /* store xmm0 onto stack */
2985 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
2986 new_ret_val, new_ret_mem);
2987 set_ia32_ls_mode(sse_store, mode);
2988 set_ia32_op_type(sse_store, ia32_AddrModeD);
2989 set_ia32_use_frame(sse_store);
2990 set_ia32_am_flavour(sse_store, ia32_am_B);
2992 /* load into x87 register */
2993 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
2994 set_ia32_op_type(fld, ia32_AddrModeS);
2995 set_ia32_use_frame(fld);
2996 set_ia32_am_flavour(fld, ia32_am_B);
2998 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
2999 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3001 /* create a new barrier */
3002 arity = get_irn_arity(barrier);
3003 in = alloca(arity * sizeof(in[0]));
3004 for (i = 0; i < arity; ++i) {
3007 if (i == pn_ret_val) {
3009 } else if (i == pn_ret_mem) {
3012 ir_node *in = get_irn_n(barrier, i);
3013 new_in = be_transform_node(in);
3018 new_barrier = new_ir_node(dbgi, irg, block,
3019 get_irn_op(barrier), get_irn_mode(barrier),
3021 copy_node_attr(barrier, new_barrier);
3022 be_duplicate_deps(barrier, new_barrier);
3023 be_set_transformed_node(barrier, new_barrier);
3024 mark_irn_visited(barrier);
3026 /* transform normally */
3027 return be_duplicate_node(node);
3031 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3033 static ir_node *gen_be_AddSP(ir_node *node) {
3034 ir_node *block = be_transform_node(get_nodes_block(node));
3035 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3037 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3038 ir_node *new_sp = be_transform_node(sp);
3039 ir_graph *irg = current_ir_graph;
3040 dbg_info *dbgi = get_irn_dbg_info(node);
3041 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3042 ir_node *nomem = new_NoMem();
3045 new_sz = create_immediate_or_transform(sz, 0);
3047 /* ia32 stack grows in reverse direction, make a SubSP */
3048 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3050 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3051 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3057 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3059 static ir_node *gen_be_SubSP(ir_node *node) {
3060 ir_node *block = be_transform_node(get_nodes_block(node));
3061 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3063 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3064 ir_node *new_sp = be_transform_node(sp);
3065 ir_graph *irg = current_ir_graph;
3066 dbg_info *dbgi = get_irn_dbg_info(node);
3067 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3068 ir_node *nomem = new_NoMem();
3071 new_sz = create_immediate_or_transform(sz, 0);
3073 /* ia32 stack grows in reverse direction, make an AddSP */
3074 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3075 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3076 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3082 * This function just sets the register for the Unknown node
3083 * as this is not done during register allocation because Unknown
3084 * is an "ignore" node.
3086 static ir_node *gen_Unknown(ir_node *node) {
3087 ir_mode *mode = get_irn_mode(node);
3089 if (mode_is_float(mode)) {
3091 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3092 if (USE_SSE2(env_cg))
3093 return ia32_new_Unknown_xmm(env_cg);
3095 return ia32_new_Unknown_vfp(env_cg);
3097 ir_graph *irg = current_ir_graph;
3098 dbg_info *dbgi = get_irn_dbg_info(node);
3099 ir_node *block = get_irg_start_block(irg);
3100 return new_rd_ia32_vfldz(dbgi, irg, block);
3102 } else if (mode_needs_gp_reg(mode)) {
3103 return ia32_new_Unknown_gp(env_cg);
3105 assert(0 && "unsupported Unknown-Mode");
3112 * Change some phi modes
3114 static ir_node *gen_Phi(ir_node *node) {
3115 ir_node *block = be_transform_node(get_nodes_block(node));
3116 ir_graph *irg = current_ir_graph;
3117 dbg_info *dbgi = get_irn_dbg_info(node);
3118 ir_mode *mode = get_irn_mode(node);
3121 if(mode_needs_gp_reg(mode)) {
3122 /* we shouldn't have any 64bit stuff around anymore */
3123 assert(get_mode_size_bits(mode) <= 32);
3124 /* all integer operations are on 32bit registers now */
3126 } else if(mode_is_float(mode)) {
3127 if (USE_SSE2(env_cg)) {
3134 /* phi nodes allow loops, so we use the old arguments for now
3135 * and fix this later */
3136 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3137 copy_node_attr(node, phi);
3138 be_duplicate_deps(node, phi);
3140 be_set_transformed_node(node, phi);
3141 be_enqueue_preds(node);
3146 /**********************************************************************
3149 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3150 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3151 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3152 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3154 **********************************************************************/
3156 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3158 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3161 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3162 ir_node *val, ir_node *mem);
3165 * Transforms a lowered Load into a "real" one.
3167 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3169 ir_node *block = be_transform_node(get_nodes_block(node));
3170 ir_node *ptr = get_irn_n(node, 0);
3171 ir_node *new_ptr = be_transform_node(ptr);
3172 ir_node *mem = get_irn_n(node, 1);
3173 ir_node *new_mem = be_transform_node(mem);
3174 ir_graph *irg = current_ir_graph;
3175 dbg_info *dbgi = get_irn_dbg_info(node);
3176 ir_mode *mode = get_ia32_ls_mode(node);
3177 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3180 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3182 set_ia32_op_type(new_op, ia32_AddrModeS);
3183 set_ia32_am_flavour(new_op, ia32_am_OB);
3184 set_ia32_am_offs_int(new_op, 0);
3185 set_ia32_am_scale(new_op, 1);
3186 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3187 if (is_ia32_am_sc_sign(node))
3188 set_ia32_am_sc_sign(new_op);
3189 set_ia32_ls_mode(new_op, mode);
3190 if (is_ia32_use_frame(node)) {
3191 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3192 set_ia32_use_frame(new_op);
3195 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3201 * Transforms a lowered Store into a "real" one.
3203 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3205 ir_node *block = be_transform_node(get_nodes_block(node));
3206 ir_node *ptr = get_irn_n(node, 0);
3207 ir_node *new_ptr = be_transform_node(ptr);
3208 ir_node *val = get_irn_n(node, 1);
3209 ir_node *new_val = be_transform_node(val);
3210 ir_node *mem = get_irn_n(node, 2);
3211 ir_node *new_mem = be_transform_node(mem);
3212 ir_graph *irg = current_ir_graph;
3213 dbg_info *dbgi = get_irn_dbg_info(node);
3214 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3215 ir_mode *mode = get_ia32_ls_mode(node);
3218 ia32_am_flavour_t am_flav = ia32_B;
3220 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3222 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3224 add_ia32_am_offs_int(new_op, am_offs);
3227 set_ia32_op_type(new_op, ia32_AddrModeD);
3228 set_ia32_am_flavour(new_op, am_flav);
3229 set_ia32_ls_mode(new_op, mode);
3230 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3231 set_ia32_use_frame(new_op);
3233 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3240 * Transforms an ia32_l_XXX into a "real" XXX node
3242 * @param env The transformation environment
3243 * @return the created ia32 XXX node
3245 #define GEN_LOWERED_OP(op) \
3246 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3247 return gen_binop(node, get_binop_left(node), \
3248 get_binop_right(node), new_rd_ia32_##op,0); \
3251 #define GEN_LOWERED_x87_OP(op) \
3252 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3254 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3255 get_binop_right(node), new_rd_ia32_##op); \
3259 #define GEN_LOWERED_UNOP(op) \
3260 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3261 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3264 #define GEN_LOWERED_SHIFT_OP(op) \
3265 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3266 return gen_shift_binop(node, get_binop_left(node), \
3267 get_binop_right(node), new_rd_ia32_##op); \
3270 #define GEN_LOWERED_LOAD(op) \
3271 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3272 return gen_lowered_Load(node, new_rd_ia32_##op); \
3275 #define GEN_LOWERED_STORE(op) \
3276 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3277 return gen_lowered_Store(node, new_rd_ia32_##op); \
3284 GEN_LOWERED_OP(IMul)
3286 GEN_LOWERED_x87_OP(vfprem)
3287 GEN_LOWERED_x87_OP(vfmul)
3288 GEN_LOWERED_x87_OP(vfsub)
3290 GEN_LOWERED_UNOP(Neg)
3292 GEN_LOWERED_LOAD(vfild)
3293 GEN_LOWERED_LOAD(Load)
3294 // GEN_LOWERED_STORE(vfist) TODO
3295 GEN_LOWERED_STORE(Store)
3297 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3298 ir_node *block = be_transform_node(get_nodes_block(node));
3299 ir_node *left = get_binop_left(node);
3300 ir_node *new_left = be_transform_node(left);
3301 ir_node *right = get_binop_right(node);
3302 ir_node *new_right = be_transform_node(right);
3303 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3304 ir_graph *irg = current_ir_graph;
3305 dbg_info *dbgi = get_irn_dbg_info(node);
3306 ir_node *fpcw = get_fpcw();
3309 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3310 new_right, new_NoMem(), fpcw);
3311 clear_ia32_commutative(vfdiv);
3312 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3314 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3320 * Transforms a l_MulS into a "real" MulS node.
3322 * @param env The transformation environment
3323 * @return the created ia32 Mul node
3325 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3326 ir_node *block = be_transform_node(get_nodes_block(node));
3327 ir_node *left = get_binop_left(node);
3328 ir_node *new_left = be_transform_node(left);
3329 ir_node *right = get_binop_right(node);
3330 ir_node *new_right = be_transform_node(right);
3331 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3332 ir_graph *irg = current_ir_graph;
3333 dbg_info *dbgi = get_irn_dbg_info(node);
3335 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3336 /* and then skip the result Proj, because all needed Projs are already there. */
3337 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3338 new_right, new_NoMem());
3339 clear_ia32_commutative(muls);
3340 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3342 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3347 GEN_LOWERED_SHIFT_OP(Shl)
3348 GEN_LOWERED_SHIFT_OP(Shr)
3349 GEN_LOWERED_SHIFT_OP(Sar)
3352 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3353 * op1 - target to be shifted
3354 * op2 - contains bits to be shifted into target
3356 * Only op3 can be an immediate.
3358 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3359 ir_node *op2, ir_node *count)
3361 ir_node *block = be_transform_node(get_nodes_block(node));
3362 ir_node *new_op1 = be_transform_node(op1);
3363 ir_node *new_op2 = be_transform_node(op2);
3364 ir_node *new_count = be_transform_node(count);
3365 ir_node *new_op = NULL;
3366 ir_graph *irg = current_ir_graph;
3367 dbg_info *dbgi = get_irn_dbg_info(node);
3368 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3369 ir_node *nomem = new_NoMem();
3373 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3375 /* Check if immediate optimization is on and */
3376 /* if it's an operation with immediate. */
3377 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3379 /* Limit imm_op within range imm8 */
3381 tv = get_ia32_Immop_tarval(imm_op);
3384 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3385 set_ia32_Immop_tarval(imm_op, tv);
3392 /* integer operations */
3394 /* This is ShiftD with const */
3395 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3397 if (is_ia32_l_ShlD(node))
3398 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3399 new_op1, new_op2, noreg, nomem);
3401 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3402 new_op1, new_op2, noreg, nomem);
3403 copy_ia32_Immop_attr(new_op, imm_op);
3406 /* This is a normal ShiftD */
3407 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3408 if (is_ia32_l_ShlD(node))
3409 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3410 new_op1, new_op2, new_count, nomem);
3412 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3413 new_op1, new_op2, new_count, nomem);
3416 /* set AM support */
3417 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3419 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3421 set_ia32_emit_cl(new_op);
3426 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3427 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3428 get_irn_n(node, 1), get_irn_n(node, 2));
3431 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3432 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3433 get_irn_n(node, 1), get_irn_n(node, 2));
3437 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3439 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3440 ir_node *block = be_transform_node(get_nodes_block(node));
3441 ir_node *val = get_irn_n(node, 1);
3442 ir_node *new_val = be_transform_node(val);
3443 ia32_code_gen_t *cg = env_cg;
3444 ir_node *res = NULL;
3445 ir_graph *irg = current_ir_graph;
3447 ir_node *noreg, *new_ptr, *new_mem;
3454 mem = get_irn_n(node, 2);
3455 new_mem = be_transform_node(mem);
3456 ptr = get_irn_n(node, 0);
3457 new_ptr = be_transform_node(ptr);
3458 noreg = ia32_new_NoReg_gp(cg);
3459 dbgi = get_irn_dbg_info(node);
3461 /* Store x87 -> MEM */
3462 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3463 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3464 set_ia32_use_frame(res);
3465 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3466 set_ia32_am_flavour(res, ia32_B);
3467 set_ia32_op_type(res, ia32_AddrModeD);
3469 /* Load MEM -> SSE */
3470 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3471 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3472 set_ia32_use_frame(res);
3473 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3474 set_ia32_am_flavour(res, ia32_B);
3475 set_ia32_op_type(res, ia32_AddrModeS);
3476 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3482 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3484 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3485 ir_node *block = be_transform_node(get_nodes_block(node));
3486 ir_node *val = get_irn_n(node, 1);
3487 ir_node *new_val = be_transform_node(val);
3488 ia32_code_gen_t *cg = env_cg;
3489 ir_graph *irg = current_ir_graph;
3490 ir_node *res = NULL;
3491 ir_entity *fent = get_ia32_frame_ent(node);
3492 ir_mode *lsmode = get_ia32_ls_mode(node);
3494 ir_node *noreg, *new_ptr, *new_mem;
3498 if (! USE_SSE2(cg)) {
3499 /* SSE unit is not used -> skip this node. */
3503 ptr = get_irn_n(node, 0);
3504 new_ptr = be_transform_node(ptr);
3505 mem = get_irn_n(node, 2);
3506 new_mem = be_transform_node(mem);
3507 noreg = ia32_new_NoReg_gp(cg);
3508 dbgi = get_irn_dbg_info(node);
3510 /* Store SSE -> MEM */
3511 if (is_ia32_xLoad(skip_Proj(new_val))) {
3512 ir_node *ld = skip_Proj(new_val);
3514 /* we can vfld the value directly into the fpu */
3515 fent = get_ia32_frame_ent(ld);
3516 ptr = get_irn_n(ld, 0);
3517 offs = get_ia32_am_offs_int(ld);
3519 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3520 set_ia32_frame_ent(res, fent);
3521 set_ia32_use_frame(res);
3522 set_ia32_ls_mode(res, lsmode);
3523 set_ia32_am_flavour(res, ia32_B);
3524 set_ia32_op_type(res, ia32_AddrModeD);
3528 /* Load MEM -> x87 */
3529 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3530 set_ia32_frame_ent(res, fent);
3531 set_ia32_use_frame(res);
3532 add_ia32_am_offs_int(res, offs);
3533 set_ia32_am_flavour(res, ia32_B);
3534 set_ia32_op_type(res, ia32_AddrModeS);
3535 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3540 /*********************************************************
3543 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3544 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3545 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3546 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3548 *********************************************************/
3551 * the BAD transformer.
3553 static ir_node *bad_transform(ir_node *node) {
3554 panic("No transform function for %+F available.\n", node);
3559 * Transform the Projs of an AddSP.
3561 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3562 ir_node *block = be_transform_node(get_nodes_block(node));
3563 ir_node *pred = get_Proj_pred(node);
3564 ir_node *new_pred = be_transform_node(pred);
3565 ir_graph *irg = current_ir_graph;
3566 dbg_info *dbgi = get_irn_dbg_info(node);
3567 long proj = get_Proj_proj(node);
3569 if (proj == pn_be_AddSP_sp) {
3570 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3571 pn_ia32_SubSP_stack);
3572 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3574 } else if(proj == pn_be_AddSP_res) {
3575 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3576 pn_ia32_SubSP_addr);
3577 } else if (proj == pn_be_AddSP_M) {
3578 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3582 return new_rd_Unknown(irg, get_irn_mode(node));
3586 * Transform the Projs of a SubSP.
3588 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3589 ir_node *block = be_transform_node(get_nodes_block(node));
3590 ir_node *pred = get_Proj_pred(node);
3591 ir_node *new_pred = be_transform_node(pred);
3592 ir_graph *irg = current_ir_graph;
3593 dbg_info *dbgi = get_irn_dbg_info(node);
3594 long proj = get_Proj_proj(node);
3596 if (proj == pn_be_SubSP_sp) {
3597 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3598 pn_ia32_AddSP_stack);
3599 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3601 } else if (proj == pn_be_SubSP_M) {
3602 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3606 return new_rd_Unknown(irg, get_irn_mode(node));
3610 * Transform and renumber the Projs from a Load.
3612 static ir_node *gen_Proj_Load(ir_node *node) {
3613 ir_node *block = be_transform_node(get_nodes_block(node));
3614 ir_node *pred = get_Proj_pred(node);
3615 ir_node *new_pred = be_transform_node(pred);
3616 ir_graph *irg = current_ir_graph;
3617 dbg_info *dbgi = get_irn_dbg_info(node);
3618 long proj = get_Proj_proj(node);
3620 /* renumber the proj */
3621 if (is_ia32_Load(new_pred)) {
3622 if (proj == pn_Load_res) {
3623 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3624 } else if (proj == pn_Load_M) {
3625 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3627 } else if (is_ia32_xLoad(new_pred)) {
3628 if (proj == pn_Load_res) {
3629 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3630 } else if (proj == pn_Load_M) {
3631 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3633 } else if (is_ia32_vfld(new_pred)) {
3634 if (proj == pn_Load_res) {
3635 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3636 } else if (proj == pn_Load_M) {
3637 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3642 return new_rd_Unknown(irg, get_irn_mode(node));
3646 * Transform and renumber the Projs from a DivMod like instruction.
3648 static ir_node *gen_Proj_DivMod(ir_node *node) {
3649 ir_node *block = be_transform_node(get_nodes_block(node));
3650 ir_node *pred = get_Proj_pred(node);
3651 ir_node *new_pred = be_transform_node(pred);
3652 ir_graph *irg = current_ir_graph;
3653 dbg_info *dbgi = get_irn_dbg_info(node);
3654 ir_mode *mode = get_irn_mode(node);
3655 long proj = get_Proj_proj(node);
3657 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3659 switch (get_irn_opcode(pred)) {
3663 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3665 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3673 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3675 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3683 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3684 case pn_DivMod_res_div:
3685 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3686 case pn_DivMod_res_mod:
3687 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3697 return new_rd_Unknown(irg, mode);
3701 * Transform and renumber the Projs from a CopyB.
3703 static ir_node *gen_Proj_CopyB(ir_node *node) {
3704 ir_node *block = be_transform_node(get_nodes_block(node));
3705 ir_node *pred = get_Proj_pred(node);
3706 ir_node *new_pred = be_transform_node(pred);
3707 ir_graph *irg = current_ir_graph;
3708 dbg_info *dbgi = get_irn_dbg_info(node);
3709 ir_mode *mode = get_irn_mode(node);
3710 long proj = get_Proj_proj(node);
3713 case pn_CopyB_M_regular:
3714 if (is_ia32_CopyB_i(new_pred)) {
3715 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3716 } else if (is_ia32_CopyB(new_pred)) {
3717 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3725 return new_rd_Unknown(irg, mode);
3729 * Transform and renumber the Projs from a vfdiv.
3731 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3732 ir_node *block = be_transform_node(get_nodes_block(node));
3733 ir_node *pred = get_Proj_pred(node);
3734 ir_node *new_pred = be_transform_node(pred);
3735 ir_graph *irg = current_ir_graph;
3736 dbg_info *dbgi = get_irn_dbg_info(node);
3737 ir_mode *mode = get_irn_mode(node);
3738 long proj = get_Proj_proj(node);
3741 case pn_ia32_l_vfdiv_M:
3742 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3743 case pn_ia32_l_vfdiv_res:
3744 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3749 return new_rd_Unknown(irg, mode);
3753 * Transform and renumber the Projs from a Quot.
3755 static ir_node *gen_Proj_Quot(ir_node *node) {
3756 ir_node *block = be_transform_node(get_nodes_block(node));
3757 ir_node *pred = get_Proj_pred(node);
3758 ir_node *new_pred = be_transform_node(pred);
3759 ir_graph *irg = current_ir_graph;
3760 dbg_info *dbgi = get_irn_dbg_info(node);
3761 ir_mode *mode = get_irn_mode(node);
3762 long proj = get_Proj_proj(node);
3766 if (is_ia32_xDiv(new_pred)) {
3767 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3768 } else if (is_ia32_vfdiv(new_pred)) {
3769 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3773 if (is_ia32_xDiv(new_pred)) {
3774 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3775 } else if (is_ia32_vfdiv(new_pred)) {
3776 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3784 return new_rd_Unknown(irg, mode);
3788 * Transform the Thread Local Storage Proj.
3790 static ir_node *gen_Proj_tls(ir_node *node) {
3791 ir_node *block = be_transform_node(get_nodes_block(node));
3792 ir_graph *irg = current_ir_graph;
3793 dbg_info *dbgi = NULL;
3794 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3800 * Transform the Projs from a be_Call.
3802 static ir_node *gen_Proj_be_Call(ir_node *node) {
3803 ir_node *block = be_transform_node(get_nodes_block(node));
3804 ir_node *call = get_Proj_pred(node);
3805 ir_node *new_call = be_transform_node(call);
3806 ir_graph *irg = current_ir_graph;
3807 dbg_info *dbgi = get_irn_dbg_info(node);
3808 long proj = get_Proj_proj(node);
3809 ir_mode *mode = get_irn_mode(node);
3811 const arch_register_class_t *cls;
3813 /* The following is kinda tricky: If we're using SSE, then we have to
3814 * move the result value of the call in floating point registers to an
3815 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3816 * after the call, we have to make sure to correctly make the
3817 * MemProj and the result Proj use these 2 nodes
3819 if (proj == pn_be_Call_M_regular) {
3820 // get new node for result, are we doing the sse load/store hack?
3821 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3822 ir_node *call_res_new;
3823 ir_node *call_res_pred = NULL;
3825 if (call_res != NULL) {
3826 call_res_new = be_transform_node(call_res);
3827 call_res_pred = get_Proj_pred(call_res_new);
3830 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3831 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3832 pn_be_Call_M_regular);
3834 assert(is_ia32_xLoad(call_res_pred));
3835 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
3839 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3841 ir_node *frame = get_irg_frame(irg);
3842 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3844 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3847 /* in case there is no memory output: create one to serialize the copy
3849 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
3850 pn_be_Call_M_regular);
3851 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
3852 pn_be_Call_first_res);
3854 /* store st(0) onto stack */
3855 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
3857 set_ia32_op_type(fstp, ia32_AddrModeD);
3858 set_ia32_use_frame(fstp);
3859 set_ia32_am_flavour(fstp, ia32_am_B);
3861 /* load into SSE register */
3862 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3863 set_ia32_ls_mode(sse_load, mode);
3864 set_ia32_op_type(sse_load, ia32_AddrModeS);
3865 set_ia32_use_frame(sse_load);
3866 set_ia32_am_flavour(sse_load, ia32_am_B);
3868 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
3872 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3874 /* get a Proj representing a caller save register */
3875 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3876 assert(is_Proj(p) && "Proj expected.");
3878 /* user of the the proj is the Keep */
3879 p = get_edge_src_irn(get_irn_out_edge_first(p));
3880 assert(be_is_Keep(p) && "Keep expected.");
3886 /* transform call modes */
3887 if (mode_is_data(mode)) {
3888 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3892 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3896 * Transform the Projs from a Cmp.
3898 static ir_node *gen_Proj_Cmp(ir_node *node)
3900 /* normally Cmps are processed when looking at Cond nodes, but this case
3901 * can happen in complicated Psi conditions */
3903 ir_node *cmp = get_Proj_pred(node);
3904 long pnc = get_Proj_proj(node);
3905 ir_node *cmp_left = get_Cmp_left(cmp);
3906 ir_node *cmp_right = get_Cmp_right(cmp);
3907 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3908 dbg_info *dbgi = get_irn_dbg_info(cmp);
3909 ir_node *block = be_transform_node(get_nodes_block(node));
3912 assert(!mode_is_float(cmp_mode));
3914 if(!mode_is_signed(cmp_mode)) {
3915 pnc |= ia32_pn_Cmp_Unsigned;
3918 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3919 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3925 * Transform and potentially renumber Proj nodes.
3927 static ir_node *gen_Proj(ir_node *node) {
3928 ir_graph *irg = current_ir_graph;
3929 dbg_info *dbgi = get_irn_dbg_info(node);
3930 ir_node *pred = get_Proj_pred(node);
3931 long proj = get_Proj_proj(node);
3933 if (is_Store(pred) || be_is_FrameStore(pred)) {
3934 if (proj == pn_Store_M) {
3935 return be_transform_node(pred);
3938 return new_r_Bad(irg);
3940 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3941 return gen_Proj_Load(node);
3942 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3943 return gen_Proj_DivMod(node);
3944 } else if (is_CopyB(pred)) {
3945 return gen_Proj_CopyB(node);
3946 } else if (is_Quot(pred)) {
3947 return gen_Proj_Quot(node);
3948 } else if (is_ia32_l_vfdiv(pred)) {
3949 return gen_Proj_l_vfdiv(node);
3950 } else if (be_is_SubSP(pred)) {
3951 return gen_Proj_be_SubSP(node);
3952 } else if (be_is_AddSP(pred)) {
3953 return gen_Proj_be_AddSP(node);
3954 } else if (be_is_Call(pred)) {
3955 return gen_Proj_be_Call(node);
3956 } else if (is_Cmp(pred)) {
3957 return gen_Proj_Cmp(node);
3958 } else if (get_irn_op(pred) == op_Start) {
3959 if (proj == pn_Start_X_initial_exec) {
3960 ir_node *block = get_nodes_block(pred);
3963 /* we exchange the ProjX with a jump */
3964 block = be_transform_node(block);
3965 jump = new_rd_Jmp(dbgi, irg, block);
3968 if (node == be_get_old_anchor(anchor_tls)) {
3969 return gen_Proj_tls(node);
3972 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
3976 ir_node *new_pred = be_transform_node(pred);
3977 ir_node *block = be_transform_node(get_nodes_block(node));
3978 ir_mode *mode = get_irn_mode(node);
3979 if (mode_needs_gp_reg(mode)) {
3980 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3981 get_Proj_proj(node));
3982 #ifdef DEBUG_libfirm
3983 new_proj->node_nr = node->node_nr;
3989 return be_duplicate_node(node);
3993 * Enters all transform functions into the generic pointer
3995 static void register_transformers(void)
3999 /* first clear the generic function pointer for all ops */
4000 clear_irp_opcodes_generic_func();
4002 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4003 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4039 /* transform ops from intrinsic lowering */
4059 /* GEN(ia32_l_vfist); TODO */
4061 GEN(ia32_l_X87toSSE);
4062 GEN(ia32_l_SSEtoX87);
4067 /* we should never see these nodes */
4082 /* handle generic backend nodes */
4093 /* set the register for all Unknown nodes */
4096 op_Mulh = get_op_Mulh();
4105 * Pre-transform all unknown and noreg nodes.
4107 static void ia32_pretransform_node(void *arch_cg) {
4108 ia32_code_gen_t *cg = arch_cg;
4110 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4111 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4112 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4113 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4114 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4115 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4120 void add_missing_keep_walker(ir_node *node, void *data)
4123 unsigned found_projs = 0;
4124 const ir_edge_t *edge;
4125 ir_mode *mode = get_irn_mode(node);
4130 if(!is_ia32_irn(node))
4133 n_outs = get_ia32_n_res(node);
4136 if(is_ia32_SwitchJmp(node))
4139 assert(n_outs < (int) sizeof(unsigned) * 8);
4140 foreach_out_edge(node, edge) {
4141 ir_node *proj = get_edge_src_irn(edge);
4142 int pn = get_Proj_proj(proj);
4144 assert(pn < n_outs);
4145 found_projs |= 1 << pn;
4149 /* are keeps missing? */
4151 for(i = 0; i < n_outs; ++i) {
4154 const arch_register_req_t *req;
4155 const arch_register_class_t *class;
4157 if(found_projs & (1 << i)) {
4161 req = get_ia32_out_req(node, i);
4167 block = get_nodes_block(node);
4168 in[0] = new_r_Proj(current_ir_graph, block, node,
4169 arch_register_class_mode(class), i);
4170 if(last_keep != NULL) {
4171 be_Keep_add_node(last_keep, class, in[0]);
4173 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4179 * Adds missing keeps to nodes
4182 void add_missing_keeps(ia32_code_gen_t *cg)
4184 ir_graph *irg = be_get_birg_irg(cg->birg);
4185 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4188 /* do the transformation */
4189 void ia32_transform_graph(ia32_code_gen_t *cg) {
4190 register_transformers();
4192 initial_fpcw = NULL;
4193 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4194 edges_verify(cg->irg);
4195 add_missing_keeps(cg);
4196 edges_verify(cg->irg);
4199 void ia32_init_transform(void)
4201 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");