2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
528 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
529 addr->mem = be_transform_node(mem);
532 static void build_address(ia32_address_mode_t *am, ir_node *node)
534 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
535 ia32_address_t *addr = &am->addr;
542 ir_entity *entity = create_float_const_entity(node);
543 addr->base = noreg_gp;
544 addr->index = noreg_gp;
545 addr->mem = new_NoMem();
546 addr->symconst_ent = entity;
548 am->ls_mode = get_irn_mode(node);
549 am->pinned = op_pin_state_floats;
553 load = get_Proj_pred(node);
554 ptr = get_Load_ptr(load);
555 mem = get_Load_mem(load);
556 new_mem = be_transform_node(mem);
557 am->pinned = get_irn_pinned(load);
558 am->ls_mode = get_Load_mode(load);
559 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
561 /* construct load address */
562 ia32_create_address_mode(addr, ptr, /*force=*/0);
564 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
565 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
569 static void set_address(ir_node *node, const ia32_address_t *addr)
571 set_ia32_am_scale(node, addr->scale);
572 set_ia32_am_sc(node, addr->symconst_ent);
573 set_ia32_am_offs_int(node, addr->offset);
574 if(addr->symconst_sign)
575 set_ia32_am_sc_sign(node);
577 set_ia32_use_frame(node);
578 set_ia32_frame_ent(node, addr->frame_entity);
581 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
583 set_address(node, &am->addr);
585 set_ia32_op_type(node, am->op_type);
586 set_ia32_ls_mode(node, am->ls_mode);
587 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
588 set_irn_pinned(node, am->pinned);
591 set_ia32_commutative(node);
595 * Check, if a given node is a Down-Conv, ie. a integer Conv
596 * from a mode with a mode with more bits to a mode with lesser bits.
597 * Moreover, we return only true if the node has not more than 1 user.
599 * @param node the node
600 * @return non-zero if node is a Down-Conv
602 static int is_downconv(const ir_node *node)
610 /* we only want to skip the conv when we're the only user
611 * (not optimal but for now...)
613 if(get_irn_n_edges(node) > 1)
616 src_mode = get_irn_mode(get_Conv_op(node));
617 dest_mode = get_irn_mode(node);
618 return mode_needs_gp_reg(src_mode)
619 && mode_needs_gp_reg(dest_mode)
620 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
623 /* Skip all Down-Conv's on a given node and return the resulting node. */
624 ir_node *ia32_skip_downconv(ir_node *node) {
625 while (is_downconv(node))
626 node = get_Conv_op(node);
632 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
634 ir_mode *mode = get_irn_mode(node);
639 if(mode_is_signed(mode)) {
644 block = get_nodes_block(node);
645 dbgi = get_irn_dbg_info(node);
647 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
651 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
652 ir_node *op1, ir_node *op2, match_flags_t flags)
654 ia32_address_t *addr = &am->addr;
655 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
658 ir_mode *mode = get_irn_mode(op2);
660 unsigned commutative;
661 int use_am_and_immediates;
663 int mode_bits = get_mode_size_bits(mode);
665 memset(am, 0, sizeof(am[0]));
667 commutative = (flags & match_commutative) != 0;
668 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
669 use_am = (flags & match_am) != 0;
670 use_immediate = (flags & match_immediate) != 0;
671 assert(!use_am_and_immediates || use_immediate);
674 assert(!commutative || op1 != NULL);
675 assert(use_am || !(flags & match_8bit_am));
676 assert(use_am || !(flags & match_16bit_am));
679 if (! (flags & match_8bit_am))
681 assert((flags & match_mode_neutral) || (flags & match_8bit));
682 } else if(mode_bits == 16) {
683 if(! (flags & match_16bit_am))
685 assert((flags & match_mode_neutral) || (flags & match_16bit));
688 /* we can simply skip downconvs for mode neutral nodes: the upper bits
689 * can be random for these operations */
690 if(flags & match_mode_neutral) {
691 op2 = ia32_skip_downconv(op2);
693 op1 = ia32_skip_downconv(op1);
697 if(! (flags & match_try_am) && use_immediate)
698 new_op2 = try_create_Immediate(op2, 0);
702 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
703 build_address(am, op2);
704 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
705 if(mode_is_float(mode)) {
706 new_op2 = ia32_new_NoReg_vfp(env_cg);
710 am->op_type = ia32_AddrModeS;
711 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
712 use_am && ia32_use_source_address_mode(block, op1, op2)) {
714 build_address(am, op1);
716 if(mode_is_float(mode)) {
717 noreg = ia32_new_NoReg_vfp(env_cg);
722 if(new_op2 != NULL) {
725 new_op1 = be_transform_node(op2);
727 am->ins_permuted = 1;
729 am->op_type = ia32_AddrModeS;
731 if(flags & match_try_am) {
734 am->op_type = ia32_Normal;
738 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
740 new_op2 = be_transform_node(op2);
741 am->op_type = ia32_Normal;
742 am->ls_mode = get_irn_mode(op2);
743 if(flags & match_mode_neutral)
744 am->ls_mode = mode_Iu;
746 if(addr->base == NULL)
747 addr->base = noreg_gp;
748 if(addr->index == NULL)
749 addr->index = noreg_gp;
750 if(addr->mem == NULL)
751 addr->mem = new_NoMem();
753 am->new_op1 = new_op1;
754 am->new_op2 = new_op2;
755 am->commutative = commutative;
758 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
760 ir_graph *irg = current_ir_graph;
764 if(am->mem_proj == NULL)
767 /* we have to create a mode_T so the old MemProj can attach to us */
768 mode = get_irn_mode(node);
769 load = get_Proj_pred(am->mem_proj);
771 mark_irn_visited(load);
772 be_set_transformed_node(load, node);
775 set_irn_mode(node, mode_T);
776 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
783 * Construct a standard binary operation, set AM and immediate if required.
785 * @param op1 The first operand
786 * @param op2 The second operand
787 * @param func The node constructor function
788 * @return The constructed ia32 node.
790 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
791 construct_binop_func *func, match_flags_t flags)
793 ir_node *block = get_nodes_block(node);
794 ir_node *new_block = be_transform_node(block);
795 ir_graph *irg = current_ir_graph;
796 dbg_info *dbgi = get_irn_dbg_info(node);
798 ia32_address_mode_t am;
799 ia32_address_t *addr = &am.addr;
801 match_arguments(&am, block, op1, op2, flags);
803 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
804 am.new_op1, am.new_op2);
805 set_am_attributes(new_node, &am);
806 /* we can't use source address mode anymore when using immediates */
807 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
808 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
809 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
811 new_node = fix_mem_proj(new_node, &am);
818 n_ia32_l_binop_right,
819 n_ia32_l_binop_eflags
821 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
822 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
823 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
824 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
825 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
826 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
829 * Construct a binary operation which also consumes the eflags.
831 * @param node The node to transform
832 * @param func The node constructor function
833 * @param flags The match flags
834 * @return The constructor ia32 node
836 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
839 ir_node *src_block = get_nodes_block(node);
840 ir_node *block = be_transform_node(src_block);
841 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
842 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
843 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
844 ir_node *new_eflags = be_transform_node(eflags);
845 ir_graph *irg = current_ir_graph;
846 dbg_info *dbgi = get_irn_dbg_info(node);
848 ia32_address_mode_t am;
849 ia32_address_t *addr = &am.addr;
851 match_arguments(&am, src_block, op1, op2, flags);
853 new_node = func(dbgi, irg, block, addr->base, addr->index,
854 addr->mem, am.new_op1, am.new_op2, new_eflags);
855 set_am_attributes(new_node, &am);
856 /* we can't use source address mode anymore when using immediates */
857 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
858 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
859 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
861 new_node = fix_mem_proj(new_node, &am);
866 static ir_node *get_fpcw(void)
869 if(initial_fpcw != NULL)
872 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
873 &ia32_fp_cw_regs[REG_FPCW]);
874 initial_fpcw = be_transform_node(fpcw);
880 * Construct a standard binary operation, set AM and immediate if required.
882 * @param op1 The first operand
883 * @param op2 The second operand
884 * @param func The node constructor function
885 * @return The constructed ia32 node.
887 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
888 construct_binop_float_func *func,
891 ir_graph *irg = current_ir_graph;
892 dbg_info *dbgi = get_irn_dbg_info(node);
893 ir_node *block = get_nodes_block(node);
894 ir_node *new_block = be_transform_node(block);
895 ir_mode *mode = get_irn_mode(node);
897 ia32_address_mode_t am;
898 ia32_address_t *addr = &am.addr;
900 /* cannot use addresmode with long double on x87 */
901 if (get_mode_size_bits(mode) > 64) flags &= ~match_am;
903 match_arguments(&am, block, op1, op2, flags);
905 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
906 am.new_op1, am.new_op2, get_fpcw());
907 set_am_attributes(new_node, &am);
909 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
911 new_node = fix_mem_proj(new_node, &am);
917 * Construct a shift/rotate binary operation, sets AM and immediate if required.
919 * @param op1 The first operand
920 * @param op2 The second operand
921 * @param func The node constructor function
922 * @return The constructed ia32 node.
924 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
925 construct_shift_func *func,
928 dbg_info *dbgi = get_irn_dbg_info(node);
929 ir_graph *irg = current_ir_graph;
930 ir_node *block = get_nodes_block(node);
931 ir_node *new_block = be_transform_node(block);
932 ir_mode *mode = get_irn_mode(node);
937 assert(! mode_is_float(mode));
938 assert(flags & match_immediate);
939 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
941 if(flags & match_mode_neutral) {
942 op1 = ia32_skip_downconv(op1);
944 new_op1 = be_transform_node(op1);
946 /* the shift amount can be any mode that is bigger than 5 bits, since all
947 * other bits are ignored anyway */
948 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
949 op2 = get_Conv_op(op2);
950 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
952 new_op2 = create_immediate_or_transform(op2, 0);
954 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
955 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
957 /* lowered shift instruction may have a dependency operand, handle it here */
958 if (get_irn_arity(node) == 3) {
959 /* we have a dependency */
960 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
961 add_irn_dep(new_node, new_dep);
969 * Construct a standard unary operation, set AM and immediate if required.
971 * @param op The operand
972 * @param func The node constructor function
973 * @return The constructed ia32 node.
975 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
978 ir_graph *irg = current_ir_graph;
979 dbg_info *dbgi = get_irn_dbg_info(node);
980 ir_node *block = get_nodes_block(node);
981 ir_node *new_block = be_transform_node(block);
985 assert(flags == 0 || flags == match_mode_neutral);
986 if(flags & match_mode_neutral) {
987 op = ia32_skip_downconv(op);
990 new_op = be_transform_node(op);
991 new_node = func(dbgi, irg, new_block, new_op);
993 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
998 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
999 ia32_address_t *addr)
1001 ir_graph *irg = current_ir_graph;
1002 ir_node *base = addr->base;
1003 ir_node *index = addr->index;
1007 base = ia32_new_NoReg_gp(env_cg);
1009 base = be_transform_node(base);
1013 index = ia32_new_NoReg_gp(env_cg);
1015 index = be_transform_node(index);
1018 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1019 set_address(res, addr);
1024 static int am_has_immediates(const ia32_address_t *addr)
1026 return addr->offset != 0 || addr->symconst_ent != NULL
1027 || addr->frame_entity || addr->use_frame;
1031 * Creates an ia32 Add.
1033 * @return the created ia32 Add node
1035 static ir_node *gen_Add(ir_node *node) {
1036 ir_graph *irg = current_ir_graph;
1037 dbg_info *dbgi = get_irn_dbg_info(node);
1038 ir_node *block = get_nodes_block(node);
1039 ir_node *new_block = be_transform_node(block);
1040 ir_node *op1 = get_Add_left(node);
1041 ir_node *op2 = get_Add_right(node);
1042 ir_mode *mode = get_irn_mode(node);
1044 ir_node *add_immediate_op;
1045 ia32_address_t addr;
1046 ia32_address_mode_t am;
1048 if (mode_is_float(mode)) {
1049 if (USE_SSE2(env_cg))
1050 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1051 match_commutative | match_am);
1053 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1054 match_commutative | match_am);
1057 ia32_mark_non_am(node);
1059 op2 = ia32_skip_downconv(op2);
1060 op1 = ia32_skip_downconv(op1);
1064 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1065 * 1. Add with immediate -> Lea
1066 * 2. Add with possible source address mode -> Add
1067 * 3. Otherwise -> Lea
1069 memset(&addr, 0, sizeof(addr));
1070 ia32_create_address_mode(&addr, node, /*force=*/1);
1071 add_immediate_op = NULL;
1073 if(addr.base == NULL && addr.index == NULL) {
1074 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1075 addr.symconst_sign, addr.offset);
1076 add_irn_dep(new_node, get_irg_frame(irg));
1077 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1080 /* add with immediate? */
1081 if(addr.index == NULL) {
1082 add_immediate_op = addr.base;
1083 } else if(addr.base == NULL && addr.scale == 0) {
1084 add_immediate_op = addr.index;
1087 if(add_immediate_op != NULL) {
1088 if(!am_has_immediates(&addr)) {
1089 #ifdef DEBUG_libfirm
1090 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1093 return be_transform_node(add_immediate_op);
1096 new_node = create_lea_from_address(dbgi, new_block, &addr);
1097 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1101 /* test if we can use source address mode */
1102 match_arguments(&am, block, op1, op2, match_commutative
1103 | match_mode_neutral | match_am | match_immediate | match_try_am);
1105 /* construct an Add with source address mode */
1106 if (am.op_type == ia32_AddrModeS) {
1107 ia32_address_t *am_addr = &am.addr;
1108 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1109 am_addr->index, am_addr->mem, am.new_op1,
1111 set_am_attributes(new_node, &am);
1112 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1114 new_node = fix_mem_proj(new_node, &am);
1119 /* otherwise construct a lea */
1120 new_node = create_lea_from_address(dbgi, new_block, &addr);
1121 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1126 * Creates an ia32 Mul.
1128 * @return the created ia32 Mul node
1130 static ir_node *gen_Mul(ir_node *node) {
1131 ir_node *op1 = get_Mul_left(node);
1132 ir_node *op2 = get_Mul_right(node);
1133 ir_mode *mode = get_irn_mode(node);
1135 if (mode_is_float(mode)) {
1136 if (USE_SSE2(env_cg))
1137 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1138 match_commutative | match_am);
1140 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1141 match_commutative | match_am);
1145 for the lower 32bit of the result it doesn't matter whether we use
1146 signed or unsigned multiplication so we use IMul as it has fewer
1149 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1150 match_commutative | match_am | match_mode_neutral |
1151 match_immediate | match_am_and_immediates);
1155 * Creates an ia32 Mulh.
1156 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1157 * this result while Mul returns the lower 32 bit.
1159 * @return the created ia32 Mulh node
1161 static ir_node *gen_Mulh(ir_node *node)
1163 ir_node *block = get_nodes_block(node);
1164 ir_node *new_block = be_transform_node(block);
1165 ir_graph *irg = current_ir_graph;
1166 dbg_info *dbgi = get_irn_dbg_info(node);
1167 ir_mode *mode = get_irn_mode(node);
1168 ir_node *op1 = get_Mulh_left(node);
1169 ir_node *op2 = get_Mulh_right(node);
1172 ia32_address_mode_t am;
1173 ia32_address_t *addr = &am.addr;
1175 assert(!mode_is_float(mode) && "Mulh with float not supported");
1176 assert(get_mode_size_bits(mode) == 32);
1178 match_arguments(&am, block, op1, op2, match_commutative | match_am);
1180 if (mode_is_signed(mode)) {
1181 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1182 addr->index, addr->mem, am.new_op1,
1185 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1186 addr->index, addr->mem, am.new_op1,
1190 set_am_attributes(new_node, &am);
1191 /* we can't use source address mode anymore when using immediates */
1192 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1193 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1194 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1196 assert(get_irn_mode(new_node) == mode_T);
1198 fix_mem_proj(new_node, &am);
1200 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1201 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1202 mode_Iu, pn_ia32_IMul1OP_EDX);
1210 * Creates an ia32 And.
1212 * @return The created ia32 And node
1214 static ir_node *gen_And(ir_node *node) {
1215 ir_node *op1 = get_And_left(node);
1216 ir_node *op2 = get_And_right(node);
1217 assert(! mode_is_float(get_irn_mode(node)));
1219 /* is it a zero extension? */
1220 if (is_Const(op2)) {
1221 tarval *tv = get_Const_tarval(op2);
1222 long v = get_tarval_long(tv);
1224 if (v == 0xFF || v == 0xFFFF) {
1225 dbg_info *dbgi = get_irn_dbg_info(node);
1226 ir_node *block = get_nodes_block(node);
1233 assert(v == 0xFFFF);
1236 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1242 return gen_binop(node, op1, op2, new_rd_ia32_And,
1243 match_commutative | match_mode_neutral | match_am
1250 * Creates an ia32 Or.
1252 * @return The created ia32 Or node
1254 static ir_node *gen_Or(ir_node *node) {
1255 ir_node *op1 = get_Or_left(node);
1256 ir_node *op2 = get_Or_right(node);
1258 assert (! mode_is_float(get_irn_mode(node)));
1259 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1260 | match_mode_neutral | match_am | match_immediate);
1266 * Creates an ia32 Eor.
1268 * @return The created ia32 Eor node
1270 static ir_node *gen_Eor(ir_node *node) {
1271 ir_node *op1 = get_Eor_left(node);
1272 ir_node *op2 = get_Eor_right(node);
1274 assert(! mode_is_float(get_irn_mode(node)));
1275 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1276 | match_mode_neutral | match_am | match_immediate);
1281 * Creates an ia32 Sub.
1283 * @return The created ia32 Sub node
1285 static ir_node *gen_Sub(ir_node *node) {
1286 ir_node *op1 = get_Sub_left(node);
1287 ir_node *op2 = get_Sub_right(node);
1288 ir_mode *mode = get_irn_mode(node);
1290 if (mode_is_float(mode)) {
1291 if (USE_SSE2(env_cg))
1292 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1294 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1299 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1303 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1304 | match_am | match_immediate);
1308 * Generates an ia32 DivMod with additional infrastructure for the
1309 * register allocator if needed.
1311 static ir_node *create_Div(ir_node *node)
1313 ir_graph *irg = current_ir_graph;
1314 dbg_info *dbgi = get_irn_dbg_info(node);
1315 ir_node *block = get_nodes_block(node);
1316 ir_node *new_block = be_transform_node(block);
1323 ir_node *sign_extension;
1325 ia32_address_mode_t am;
1326 ia32_address_t *addr = &am.addr;
1328 /* the upper bits have random contents for smaller modes */
1330 switch (get_irn_opcode(node)) {
1332 op1 = get_Div_left(node);
1333 op2 = get_Div_right(node);
1334 mem = get_Div_mem(node);
1335 mode = get_Div_resmode(node);
1336 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1339 op1 = get_Mod_left(node);
1340 op2 = get_Mod_right(node);
1341 mem = get_Mod_mem(node);
1342 mode = get_Mod_resmode(node);
1343 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1346 op1 = get_DivMod_left(node);
1347 op2 = get_DivMod_right(node);
1348 mem = get_DivMod_mem(node);
1349 mode = get_DivMod_resmode(node);
1350 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1353 panic("invalid divmod node %+F", node);
1356 match_arguments(&am, block, op1, op2, match_am);
1358 if(!is_NoMem(mem)) {
1359 new_mem = be_transform_node(mem);
1360 if(!is_NoMem(addr->mem)) {
1364 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1367 new_mem = addr->mem;
1370 if (mode_is_signed(mode)) {
1371 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1372 add_irn_dep(produceval, get_irg_frame(irg));
1373 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1376 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1377 addr->index, new_mem, am.new_op1,
1378 sign_extension, am.new_op2);
1380 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1381 add_irn_dep(sign_extension, get_irg_frame(irg));
1383 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1384 addr->index, new_mem, am.new_op1,
1385 sign_extension, am.new_op2);
1388 set_ia32_exc_label(new_node, has_exc);
1389 set_irn_pinned(new_node, get_irn_pinned(node));
1391 set_am_attributes(new_node, &am);
1392 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1394 new_node = fix_mem_proj(new_node, &am);
1400 static ir_node *gen_Mod(ir_node *node) {
1401 return create_Div(node);
1404 static ir_node *gen_Div(ir_node *node) {
1405 return create_Div(node);
1408 static ir_node *gen_DivMod(ir_node *node) {
1409 return create_Div(node);
1415 * Creates an ia32 floating Div.
1417 * @return The created ia32 xDiv node
1419 static ir_node *gen_Quot(ir_node *node)
1421 ir_node *op1 = get_Quot_left(node);
1422 ir_node *op2 = get_Quot_right(node);
1424 if (USE_SSE2(env_cg)) {
1425 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1427 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1433 * Creates an ia32 Shl.
1435 * @return The created ia32 Shl node
1437 static ir_node *gen_Shl(ir_node *node) {
1438 ir_node *left = get_Shl_left(node);
1439 ir_node *right = get_Shl_right(node);
1441 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1442 match_mode_neutral | match_immediate);
1446 * Creates an ia32 Shr.
1448 * @return The created ia32 Shr node
1450 static ir_node *gen_Shr(ir_node *node) {
1451 ir_node *left = get_Shr_left(node);
1452 ir_node *right = get_Shr_right(node);
1454 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1460 * Creates an ia32 Sar.
1462 * @return The created ia32 Shrs node
1464 static ir_node *gen_Shrs(ir_node *node) {
1465 ir_node *left = get_Shrs_left(node);
1466 ir_node *right = get_Shrs_right(node);
1467 ir_mode *mode = get_irn_mode(node);
1469 if(is_Const(right) && mode == mode_Is) {
1470 tarval *tv = get_Const_tarval(right);
1471 long val = get_tarval_long(tv);
1473 /* this is a sign extension */
1474 ir_graph *irg = current_ir_graph;
1475 dbg_info *dbgi = get_irn_dbg_info(node);
1476 ir_node *block = be_transform_node(get_nodes_block(node));
1478 ir_node *new_op = be_transform_node(op);
1479 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1480 add_irn_dep(pval, get_irg_frame(irg));
1482 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1486 /* 8 or 16 bit sign extension? */
1487 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1488 ir_node *shl_left = get_Shl_left(left);
1489 ir_node *shl_right = get_Shl_right(left);
1490 if(is_Const(shl_right)) {
1491 tarval *tv1 = get_Const_tarval(right);
1492 tarval *tv2 = get_Const_tarval(shl_right);
1493 if(tv1 == tv2 && tarval_is_long(tv1)) {
1494 long val = get_tarval_long(tv1);
1495 if(val == 16 || val == 24) {
1496 dbg_info *dbgi = get_irn_dbg_info(node);
1497 ir_node *block = get_nodes_block(node);
1507 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1516 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1522 * Creates an ia32 RotL.
1524 * @param op1 The first operator
1525 * @param op2 The second operator
1526 * @return The created ia32 RotL node
1528 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1529 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1535 * Creates an ia32 RotR.
1536 * NOTE: There is no RotR with immediate because this would always be a RotL
1537 * "imm-mode_size_bits" which can be pre-calculated.
1539 * @param op1 The first operator
1540 * @param op2 The second operator
1541 * @return The created ia32 RotR node
1543 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1544 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1550 * Creates an ia32 RotR or RotL (depending on the found pattern).
1552 * @return The created ia32 RotL or RotR node
1554 static ir_node *gen_Rot(ir_node *node) {
1555 ir_node *rotate = NULL;
1556 ir_node *op1 = get_Rot_left(node);
1557 ir_node *op2 = get_Rot_right(node);
1559 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1560 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1561 that means we can create a RotR instead of an Add and a RotL */
1563 if (get_irn_op(op2) == op_Add) {
1565 ir_node *left = get_Add_left(add);
1566 ir_node *right = get_Add_right(add);
1567 if (is_Const(right)) {
1568 tarval *tv = get_Const_tarval(right);
1569 ir_mode *mode = get_irn_mode(node);
1570 long bits = get_mode_size_bits(mode);
1572 if (get_irn_op(left) == op_Minus &&
1573 tarval_is_long(tv) &&
1574 get_tarval_long(tv) == bits &&
1577 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1578 rotate = gen_RotR(node, op1, get_Minus_op(left));
1583 if (rotate == NULL) {
1584 rotate = gen_RotL(node, op1, op2);
1593 * Transforms a Minus node.
1595 * @return The created ia32 Minus node
1597 static ir_node *gen_Minus(ir_node *node)
1599 ir_node *op = get_Minus_op(node);
1600 ir_node *block = be_transform_node(get_nodes_block(node));
1601 ir_graph *irg = current_ir_graph;
1602 dbg_info *dbgi = get_irn_dbg_info(node);
1603 ir_mode *mode = get_irn_mode(node);
1608 if (mode_is_float(mode)) {
1609 ir_node *new_op = be_transform_node(op);
1610 if (USE_SSE2(env_cg)) {
1611 /* TODO: non-optimal... if we have many xXors, then we should
1612 * rather create a load for the const and use that instead of
1613 * several AM nodes... */
1614 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1615 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1616 ir_node *nomem = new_rd_NoMem(irg);
1618 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1619 nomem, new_op, noreg_xmm);
1621 size = get_mode_size_bits(mode);
1622 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1624 set_ia32_am_sc(new_node, ent);
1625 set_ia32_op_type(new_node, ia32_AddrModeS);
1626 set_ia32_ls_mode(new_node, mode);
1628 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1631 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1634 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1640 * Transforms a Not node.
1642 * @return The created ia32 Not node
1644 static ir_node *gen_Not(ir_node *node) {
1645 ir_node *op = get_Not_op(node);
1647 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1648 assert (! mode_is_float(get_irn_mode(node)));
1650 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1656 * Transforms an Abs node.
1658 * @return The created ia32 Abs node
1660 static ir_node *gen_Abs(ir_node *node)
1662 ir_node *block = get_nodes_block(node);
1663 ir_node *new_block = be_transform_node(block);
1664 ir_node *op = get_Abs_op(node);
1665 ir_graph *irg = current_ir_graph;
1666 dbg_info *dbgi = get_irn_dbg_info(node);
1667 ir_mode *mode = get_irn_mode(node);
1668 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1669 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1670 ir_node *nomem = new_NoMem();
1676 if (mode_is_float(mode)) {
1677 new_op = be_transform_node(op);
1679 if (USE_SSE2(env_cg)) {
1680 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1681 nomem, new_op, noreg_fp);
1683 size = get_mode_size_bits(mode);
1684 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1686 set_ia32_am_sc(new_node, ent);
1688 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1690 set_ia32_op_type(new_node, ia32_AddrModeS);
1691 set_ia32_ls_mode(new_node, mode);
1693 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1694 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1697 if (get_mode_size_bits(mode) == 32) {
1698 new_op = be_transform_node(op);
1700 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1704 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1705 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1708 add_irn_dep(pval, get_irg_frame(irg));
1709 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1711 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1712 nomem, new_op, sign_extension);
1713 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1715 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1716 nomem, xor, sign_extension);
1717 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1723 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1725 ir_graph *irg = current_ir_graph;
1733 /* we have a Cmp as input */
1735 ir_node *pred = get_Proj_pred(node);
1737 flags = be_transform_node(pred);
1738 *pnc_out = get_Proj_proj(node);
1743 /* a mode_b value, we have to compare it against 0 */
1744 dbgi = get_irn_dbg_info(node);
1745 new_block = be_transform_node(get_nodes_block(node));
1746 new_op = be_transform_node(node);
1747 noreg = ia32_new_NoReg_gp(env_cg);
1748 nomem = new_NoMem();
1749 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1750 new_op, new_op, 0, 0);
1751 *pnc_out = pn_Cmp_Lg;
1756 * Transforms a Load.
1758 * @return the created ia32 Load node
1760 static ir_node *gen_Load(ir_node *node) {
1761 ir_node *old_block = get_nodes_block(node);
1762 ir_node *block = be_transform_node(old_block);
1763 ir_node *ptr = get_Load_ptr(node);
1764 ir_node *mem = get_Load_mem(node);
1765 ir_node *new_mem = be_transform_node(mem);
1768 ir_graph *irg = current_ir_graph;
1769 dbg_info *dbgi = get_irn_dbg_info(node);
1770 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1771 ir_mode *mode = get_Load_mode(node);
1774 ia32_address_t addr;
1776 /* construct load address */
1777 memset(&addr, 0, sizeof(addr));
1778 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1785 base = be_transform_node(base);
1791 index = be_transform_node(index);
1794 if (mode_is_float(mode)) {
1795 if (USE_SSE2(env_cg)) {
1796 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1798 res_mode = mode_xmm;
1800 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1802 res_mode = mode_vfp;
1805 assert(mode != mode_b);
1807 /* create a conv node with address mode for smaller modes */
1808 if(get_mode_size_bits(mode) < 32) {
1809 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1810 new_mem, noreg, mode);
1812 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1817 set_irn_pinned(new_node, get_irn_pinned(node));
1818 set_ia32_op_type(new_node, ia32_AddrModeS);
1819 set_ia32_ls_mode(new_node, mode);
1820 set_address(new_node, &addr);
1822 if(get_irn_pinned(node) == op_pin_state_floats) {
1823 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1826 /* make sure we are scheduled behind the initial IncSP/Barrier
1827 * to avoid spills being placed before it
1829 if (block == get_irg_start_block(irg)) {
1830 add_irn_dep(new_node, get_irg_frame(irg));
1833 set_ia32_exc_label(new_node,
1834 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1835 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1840 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1841 ir_node *ptr, ir_node *other)
1848 /* we only use address mode if we're the only user of the load */
1849 if(get_irn_n_edges(node) > 1)
1852 load = get_Proj_pred(node);
1855 if(get_nodes_block(load) != block)
1858 /* Store should be attached to the load */
1859 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1861 /* store should have the same pointer as the load */
1862 if(get_Load_ptr(load) != ptr)
1865 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1866 if(other != NULL && get_nodes_block(other) == block
1867 && heights_reachable_in_block(heights, other, load))
1873 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1874 ir_node *mem, ir_node *ptr, ir_mode *mode,
1875 construct_binop_dest_func *func,
1876 construct_binop_dest_func *func8bit,
1877 match_flags_t flags)
1879 ir_node *src_block = get_nodes_block(node);
1881 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1882 ir_graph *irg = current_ir_graph;
1887 ia32_address_mode_t am;
1888 ia32_address_t *addr = &am.addr;
1889 memset(&am, 0, sizeof(am));
1891 assert(flags & match_dest_am);
1892 assert(flags & match_immediate); /* there is no destam node without... */
1893 commutative = (flags & match_commutative) != 0;
1895 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1896 build_address(&am, op1);
1897 new_op = create_immediate_or_transform(op2, 0);
1898 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1899 build_address(&am, op2);
1900 new_op = create_immediate_or_transform(op1, 0);
1905 if(addr->base == NULL)
1906 addr->base = noreg_gp;
1907 if(addr->index == NULL)
1908 addr->index = noreg_gp;
1909 if(addr->mem == NULL)
1910 addr->mem = new_NoMem();
1912 dbgi = get_irn_dbg_info(node);
1913 block = be_transform_node(src_block);
1914 if(get_mode_size_bits(mode) == 8) {
1915 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1918 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1921 set_address(new_node, addr);
1922 set_ia32_op_type(new_node, ia32_AddrModeD);
1923 set_ia32_ls_mode(new_node, mode);
1924 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1929 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1930 ir_node *ptr, ir_mode *mode,
1931 construct_unop_dest_func *func)
1933 ir_graph *irg = current_ir_graph;
1934 ir_node *src_block = get_nodes_block(node);
1938 ia32_address_mode_t am;
1939 ia32_address_t *addr = &am.addr;
1940 memset(&am, 0, sizeof(am));
1942 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1945 build_address(&am, op);
1947 dbgi = get_irn_dbg_info(node);
1948 block = be_transform_node(src_block);
1949 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1950 set_address(new_node, addr);
1951 set_ia32_op_type(new_node, ia32_AddrModeD);
1952 set_ia32_ls_mode(new_node, mode);
1953 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1958 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1959 ir_mode *mode = get_irn_mode(node);
1960 ir_node *psi_true = get_Psi_val(node, 0);
1961 ir_node *psi_default = get_Psi_default(node);
1972 ia32_address_t addr;
1974 if(get_mode_size_bits(mode) != 8)
1977 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1979 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1985 build_address_ptr(&addr, ptr, mem);
1987 irg = current_ir_graph;
1988 dbgi = get_irn_dbg_info(node);
1989 block = get_nodes_block(node);
1990 new_block = be_transform_node(block);
1991 cond = get_Psi_cond(node, 0);
1992 flags = get_flags_node(cond, &pnc);
1993 new_mem = be_transform_node(mem);
1994 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
1995 addr.index, addr.mem, flags, pnc, negated);
1996 set_address(new_node, &addr);
1997 set_ia32_op_type(new_node, ia32_AddrModeD);
1998 set_ia32_ls_mode(new_node, mode);
1999 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2004 static ir_node *try_create_dest_am(ir_node *node) {
2005 ir_node *val = get_Store_value(node);
2006 ir_node *mem = get_Store_mem(node);
2007 ir_node *ptr = get_Store_ptr(node);
2008 ir_mode *mode = get_irn_mode(val);
2009 int bits = get_mode_size_bits(mode);
2014 /* handle only GP modes for now... */
2015 if(!mode_needs_gp_reg(mode))
2019 /* store must be the only user of the val node */
2020 if(get_irn_n_edges(val) > 1)
2022 /* skip pointless convs */
2024 ir_node *conv_op = get_Conv_op(val);
2025 ir_mode *pred_mode = get_irn_mode(conv_op);
2026 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2034 /* value must be in the same block */
2035 if(get_nodes_block(node) != get_nodes_block(val))
2038 switch(get_irn_opcode(val)) {
2040 op1 = get_Add_left(val);
2041 op2 = get_Add_right(val);
2042 if(is_Const_1(op2)) {
2043 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2044 new_rd_ia32_IncMem);
2046 } else if(is_Const_Minus_1(op2)) {
2047 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2048 new_rd_ia32_DecMem);
2051 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2052 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2053 match_dest_am | match_commutative |
2057 op1 = get_Sub_left(val);
2058 op2 = get_Sub_right(val);
2060 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2063 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2064 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2065 match_dest_am | match_immediate |
2069 op1 = get_And_left(val);
2070 op2 = get_And_right(val);
2071 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2072 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2073 match_dest_am | match_commutative |
2077 op1 = get_Or_left(val);
2078 op2 = get_Or_right(val);
2079 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2080 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2081 match_dest_am | match_commutative |
2085 op1 = get_Eor_left(val);
2086 op2 = get_Eor_right(val);
2087 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2088 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2089 match_dest_am | match_commutative |
2093 op1 = get_Shl_left(val);
2094 op2 = get_Shl_right(val);
2095 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2096 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2097 match_dest_am | match_immediate);
2100 op1 = get_Shr_left(val);
2101 op2 = get_Shr_right(val);
2102 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2103 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2104 match_dest_am | match_immediate);
2107 op1 = get_Shrs_left(val);
2108 op2 = get_Shrs_right(val);
2109 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2110 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2111 match_dest_am | match_immediate);
2114 op1 = get_Rot_left(val);
2115 op2 = get_Rot_right(val);
2116 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2117 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2118 match_dest_am | match_immediate);
2120 /* TODO: match ROR patterns... */
2122 new_node = try_create_SetMem(val, ptr, mem);
2125 op1 = get_Minus_op(val);
2126 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2129 /* should be lowered already */
2130 assert(mode != mode_b);
2131 op1 = get_Not_op(val);
2132 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2138 if(new_node != NULL) {
2139 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2140 get_irn_pinned(node) == op_pin_state_pinned) {
2141 set_irn_pinned(new_node, op_pin_state_pinned);
2148 static int is_float_to_int32_conv(const ir_node *node)
2150 ir_mode *mode = get_irn_mode(node);
2154 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2159 conv_op = get_Conv_op(node);
2160 conv_mode = get_irn_mode(conv_op);
2162 if(!mode_is_float(conv_mode))
2169 * Transforms a Store.
2171 * @return the created ia32 Store node
2173 static ir_node *gen_Store(ir_node *node)
2175 ir_node *block = get_nodes_block(node);
2176 ir_node *new_block = be_transform_node(block);
2177 ir_node *ptr = get_Store_ptr(node);
2178 ir_node *val = get_Store_value(node);
2179 ir_node *mem = get_Store_mem(node);
2180 ir_graph *irg = current_ir_graph;
2181 dbg_info *dbgi = get_irn_dbg_info(node);
2182 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2183 ir_mode *mode = get_irn_mode(val);
2186 ia32_address_t addr;
2188 /* check for destination address mode */
2189 new_node = try_create_dest_am(node);
2190 if(new_node != NULL)
2193 /* construct store address */
2194 memset(&addr, 0, sizeof(addr));
2195 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2197 if(addr.base == NULL) {
2200 addr.base = be_transform_node(addr.base);
2203 if(addr.index == NULL) {
2206 addr.index = be_transform_node(addr.index);
2208 addr.mem = be_transform_node(mem);
2210 if (mode_is_float(mode)) {
2211 /* convs (and strict-convs) before stores are unnecessary if the mode
2213 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2214 val = get_Conv_op(val);
2216 new_val = be_transform_node(val);
2217 if (USE_SSE2(env_cg)) {
2218 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2219 addr.index, addr.mem, new_val);
2221 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2222 addr.index, addr.mem, new_val, mode);
2224 } else if(is_float_to_int32_conv(val)) {
2225 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2226 val = get_Conv_op(val);
2228 /* convs (and strict-convs) before stores are unnecessary if the mode
2230 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2231 val = get_Conv_op(val);
2233 new_val = be_transform_node(val);
2235 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2236 addr.index, addr.mem, new_val, trunc_mode);
2238 new_val = create_immediate_or_transform(val, 0);
2239 assert(mode != mode_b);
2241 if (get_mode_size_bits(mode) == 8) {
2242 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2243 addr.index, addr.mem, new_val);
2245 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2246 addr.index, addr.mem, new_val);
2250 set_irn_pinned(new_node, get_irn_pinned(node));
2251 set_ia32_op_type(new_node, ia32_AddrModeD);
2252 set_ia32_ls_mode(new_node, mode);
2254 set_ia32_exc_label(new_node,
2255 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2256 set_address(new_node, &addr);
2257 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2262 static ir_node *create_Switch(ir_node *node)
2264 ir_graph *irg = current_ir_graph;
2265 dbg_info *dbgi = get_irn_dbg_info(node);
2266 ir_node *block = be_transform_node(get_nodes_block(node));
2267 ir_node *sel = get_Cond_selector(node);
2268 ir_node *new_sel = be_transform_node(sel);
2269 int switch_min = INT_MAX;
2271 const ir_edge_t *edge;
2273 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2275 /* determine the smallest switch case value */
2276 foreach_out_edge(node, edge) {
2277 ir_node *proj = get_edge_src_irn(edge);
2278 int pn = get_Proj_proj(proj);
2283 if (switch_min != 0) {
2284 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2286 /* if smallest switch case is not 0 we need an additional sub */
2287 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2288 add_ia32_am_offs_int(new_sel, -switch_min);
2289 set_ia32_op_type(new_sel, ia32_AddrModeS);
2291 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2294 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2295 get_Cond_defaultProj(node));
2296 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2301 static ir_node *gen_Cond(ir_node *node) {
2302 ir_node *block = get_nodes_block(node);
2303 ir_node *new_block = be_transform_node(block);
2304 ir_graph *irg = current_ir_graph;
2305 dbg_info *dbgi = get_irn_dbg_info(node);
2306 ir_node *sel = get_Cond_selector(node);
2307 ir_mode *sel_mode = get_irn_mode(sel);
2308 ir_node *flags = NULL;
2312 if (sel_mode != mode_b) {
2313 return create_Switch(node);
2316 /* we get flags from a cmp */
2317 flags = get_flags_node(sel, &pnc);
2319 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2320 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2328 * Transforms a CopyB node.
2330 * @return The transformed node.
2332 static ir_node *gen_CopyB(ir_node *node) {
2333 ir_node *block = be_transform_node(get_nodes_block(node));
2334 ir_node *src = get_CopyB_src(node);
2335 ir_node *new_src = be_transform_node(src);
2336 ir_node *dst = get_CopyB_dst(node);
2337 ir_node *new_dst = be_transform_node(dst);
2338 ir_node *mem = get_CopyB_mem(node);
2339 ir_node *new_mem = be_transform_node(mem);
2340 ir_node *res = NULL;
2341 ir_graph *irg = current_ir_graph;
2342 dbg_info *dbgi = get_irn_dbg_info(node);
2343 int size = get_type_size_bytes(get_CopyB_type(node));
2346 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2347 /* then we need the size explicitly in ECX. */
2348 if (size >= 32 * 4) {
2349 rem = size & 0x3; /* size % 4 */
2352 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2353 add_irn_dep(res, get_irg_frame(irg));
2355 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2358 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2361 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2364 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2369 static ir_node *gen_be_Copy(ir_node *node)
2371 ir_node *new_node = be_duplicate_node(node);
2372 ir_mode *mode = get_irn_mode(new_node);
2374 if (mode_needs_gp_reg(mode)) {
2375 set_irn_mode(new_node, mode_Iu);
2381 static ir_node *create_Fucom(ir_node *node)
2383 ir_graph *irg = current_ir_graph;
2384 dbg_info *dbgi = get_irn_dbg_info(node);
2385 ir_node *block = get_nodes_block(node);
2386 ir_node *new_block = be_transform_node(block);
2387 ir_node *left = get_Cmp_left(node);
2388 ir_node *new_left = be_transform_node(left);
2389 ir_node *right = get_Cmp_right(node);
2393 if(transform_config.use_fucomi) {
2394 new_right = be_transform_node(right);
2395 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2397 set_ia32_commutative(new_node);
2398 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2400 if(transform_config.use_ftst && is_Const_null(right)) {
2401 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2404 new_right = be_transform_node(right);
2405 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2409 set_ia32_commutative(new_node);
2411 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2413 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2414 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2420 static ir_node *create_Ucomi(ir_node *node)
2422 ir_graph *irg = current_ir_graph;
2423 dbg_info *dbgi = get_irn_dbg_info(node);
2424 ir_node *src_block = get_nodes_block(node);
2425 ir_node *new_block = be_transform_node(src_block);
2426 ir_node *left = get_Cmp_left(node);
2427 ir_node *right = get_Cmp_right(node);
2429 ia32_address_mode_t am;
2430 ia32_address_t *addr = &am.addr;
2432 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2434 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2435 addr->mem, am.new_op1, am.new_op2,
2437 set_am_attributes(new_node, &am);
2439 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2441 new_node = fix_mem_proj(new_node, &am);
2447 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2448 * to fold an and into a test node
2450 static int can_fold_test_and(ir_node *node)
2452 const ir_edge_t *edge;
2454 /** we can only have eq and lg projs */
2455 foreach_out_edge(node, edge) {
2456 ir_node *proj = get_edge_src_irn(edge);
2457 pn_Cmp pnc = get_Proj_proj(proj);
2458 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2465 static ir_node *gen_Cmp(ir_node *node)
2467 ir_graph *irg = current_ir_graph;
2468 dbg_info *dbgi = get_irn_dbg_info(node);
2469 ir_node *block = get_nodes_block(node);
2470 ir_node *new_block = be_transform_node(block);
2471 ir_node *left = get_Cmp_left(node);
2472 ir_node *right = get_Cmp_right(node);
2473 ir_mode *cmp_mode = get_irn_mode(left);
2475 ia32_address_mode_t am;
2476 ia32_address_t *addr = &am.addr;
2479 if(mode_is_float(cmp_mode)) {
2480 if (USE_SSE2(env_cg)) {
2481 return create_Ucomi(node);
2483 return create_Fucom(node);
2487 assert(mode_needs_gp_reg(cmp_mode));
2489 /* we prefer the Test instruction where possible except cases where
2490 * we can use SourceAM */
2491 cmp_unsigned = !mode_is_signed(cmp_mode);
2492 if (is_Const_0(right)) {
2494 get_irn_n_edges(left) == 1 &&
2495 can_fold_test_and(node)) {
2496 /* Test(and_left, and_right) */
2497 ir_node *and_left = get_And_left(left);
2498 ir_node *and_right = get_And_right(left);
2499 ir_mode *mode = get_irn_mode(and_left);
2501 match_arguments(&am, block, and_left, and_right, match_commutative |
2502 match_am | match_8bit_am | match_16bit_am |
2503 match_am_and_immediates | match_immediate |
2504 match_8bit | match_16bit);
2505 if (get_mode_size_bits(mode) == 8) {
2506 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2507 addr->index, addr->mem, am.new_op1,
2508 am.new_op2, am.ins_permuted,
2511 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2512 addr->index, addr->mem, am.new_op1,
2513 am.new_op2, am.ins_permuted, cmp_unsigned);
2516 match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
2517 match_16bit_am | match_8bit | match_16bit);
2518 if (am.op_type == ia32_AddrModeS) {
2520 ir_node *imm_zero = try_create_Immediate(right, 0);
2521 if (get_mode_size_bits(cmp_mode) == 8) {
2522 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2523 addr->index, addr->mem, am.new_op2,
2524 imm_zero, am.ins_permuted,
2527 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2528 addr->index, addr->mem, am.new_op2,
2529 imm_zero, am.ins_permuted, cmp_unsigned);
2532 /* Test(left, left) */
2533 if (get_mode_size_bits(cmp_mode) == 8) {
2534 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2535 addr->index, addr->mem, am.new_op2,
2536 am.new_op2, am.ins_permuted,
2539 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2540 addr->index, addr->mem, am.new_op2,
2541 am.new_op2, am.ins_permuted,
2547 /* Cmp(left, right) */
2548 match_arguments(&am, block, left, right, match_commutative | match_am |
2549 match_8bit_am | match_16bit_am | match_am_and_immediates |
2550 match_immediate | match_8bit | match_16bit);
2551 if (get_mode_size_bits(cmp_mode) == 8) {
2552 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2553 addr->index, addr->mem, am.new_op1,
2554 am.new_op2, am.ins_permuted,
2557 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2558 addr->index, addr->mem, am.new_op1,
2559 am.new_op2, am.ins_permuted, cmp_unsigned);
2562 set_am_attributes(new_node, &am);
2563 assert(cmp_mode != NULL);
2564 set_ia32_ls_mode(new_node, cmp_mode);
2566 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2568 new_node = fix_mem_proj(new_node, &am);
2573 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2575 ir_graph *irg = current_ir_graph;
2576 dbg_info *dbgi = get_irn_dbg_info(node);
2577 ir_node *block = get_nodes_block(node);
2578 ir_node *new_block = be_transform_node(block);
2579 ir_node *val_true = get_Psi_val(node, 0);
2580 ir_node *val_false = get_Psi_default(node);
2582 match_flags_t match_flags;
2583 ia32_address_mode_t am;
2584 ia32_address_t *addr;
2586 assert(transform_config.use_cmov);
2587 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2591 match_flags = match_commutative | match_am | match_16bit_am |
2594 match_arguments(&am, block, val_false, val_true, match_flags);
2596 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2597 addr->mem, am.new_op1, am.new_op2, new_flags,
2598 am.ins_permuted, pnc);
2599 set_am_attributes(new_node, &am);
2601 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2603 new_node = fix_mem_proj(new_node, &am);
2610 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2611 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2614 ir_graph *irg = current_ir_graph;
2615 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2616 ir_node *nomem = new_NoMem();
2617 ir_mode *mode = get_irn_mode(orig_node);
2620 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2621 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2623 /* we might need to conv the result up */
2624 if(get_mode_size_bits(mode) > 8) {
2625 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2626 nomem, new_node, mode_Bu);
2627 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2634 * Transforms a Psi node into CMov.
2636 * @return The transformed node.
2638 static ir_node *gen_Psi(ir_node *node)
2640 dbg_info *dbgi = get_irn_dbg_info(node);
2641 ir_node *block = get_nodes_block(node);
2642 ir_node *new_block = be_transform_node(block);
2643 ir_node *psi_true = get_Psi_val(node, 0);
2644 ir_node *psi_default = get_Psi_default(node);
2645 ir_node *cond = get_Psi_cond(node, 0);
2646 ir_node *flags = NULL;
2650 assert(get_Psi_n_conds(node) == 1);
2651 assert(get_irn_mode(cond) == mode_b);
2652 assert(mode_needs_gp_reg(get_irn_mode(node)));
2654 flags = get_flags_node(cond, &pnc);
2656 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2657 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2658 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2659 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2661 new_node = create_CMov(node, flags, pnc);
2668 * Create a conversion from x87 state register to general purpose.
2670 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2671 ir_node *block = be_transform_node(get_nodes_block(node));
2672 ir_node *op = get_Conv_op(node);
2673 ir_node *new_op = be_transform_node(op);
2674 ia32_code_gen_t *cg = env_cg;
2675 ir_graph *irg = current_ir_graph;
2676 dbg_info *dbgi = get_irn_dbg_info(node);
2677 ir_node *noreg = ia32_new_NoReg_gp(cg);
2678 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2679 ir_mode *mode = get_irn_mode(node);
2680 ir_node *fist, *load;
2683 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2684 new_NoMem(), new_op, trunc_mode);
2686 set_irn_pinned(fist, op_pin_state_floats);
2687 set_ia32_use_frame(fist);
2688 set_ia32_op_type(fist, ia32_AddrModeD);
2690 assert(get_mode_size_bits(mode) <= 32);
2691 /* exception we can only store signed 32 bit integers, so for unsigned
2692 we store a 64bit (signed) integer and load the lower bits */
2693 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2694 set_ia32_ls_mode(fist, mode_Ls);
2696 set_ia32_ls_mode(fist, mode_Is);
2698 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2701 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2703 set_irn_pinned(load, op_pin_state_floats);
2704 set_ia32_use_frame(load);
2705 set_ia32_op_type(load, ia32_AddrModeS);
2706 set_ia32_ls_mode(load, mode_Is);
2707 if(get_ia32_ls_mode(fist) == mode_Ls) {
2708 ia32_attr_t *attr = get_ia32_attr(load);
2709 attr->data.need_64bit_stackent = 1;
2711 ia32_attr_t *attr = get_ia32_attr(load);
2712 attr->data.need_32bit_stackent = 1;
2714 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2716 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2720 * Creates a x87 strict Conv by placing a Sore and a Load
2722 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2724 ir_node *block = get_nodes_block(node);
2725 ir_graph *irg = current_ir_graph;
2726 dbg_info *dbgi = get_irn_dbg_info(node);
2727 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2728 ir_node *nomem = new_NoMem();
2729 ir_node *frame = get_irg_frame(irg);
2730 ir_node *store, *load;
2733 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2735 set_ia32_use_frame(store);
2736 set_ia32_op_type(store, ia32_AddrModeD);
2737 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2739 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2741 set_ia32_use_frame(load);
2742 set_ia32_op_type(load, ia32_AddrModeS);
2743 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2745 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2749 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2751 ir_graph *irg = current_ir_graph;
2752 ir_node *start_block = get_irg_start_block(irg);
2753 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2754 symconst, symconst_sign, val);
2755 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2761 * Create a conversion from general purpose to x87 register
2763 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2764 ir_node *src_block = get_nodes_block(node);
2765 ir_node *block = be_transform_node(src_block);
2766 ir_graph *irg = current_ir_graph;
2767 dbg_info *dbgi = get_irn_dbg_info(node);
2768 ir_node *op = get_Conv_op(node);
2769 ir_node *new_op = NULL;
2773 ir_mode *store_mode;
2779 /* fild can use source AM if the operand is a signed 32bit integer */
2780 if (src_mode == mode_Is) {
2781 ia32_address_mode_t am;
2783 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2784 if (am.op_type == ia32_AddrModeS) {
2785 ia32_address_t *addr = &am.addr;
2787 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2788 addr->index, addr->mem);
2789 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2792 set_am_attributes(fild, &am);
2793 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2795 fix_mem_proj(fild, &am);
2800 if(new_op == NULL) {
2801 new_op = be_transform_node(op);
2804 noreg = ia32_new_NoReg_gp(env_cg);
2805 nomem = new_NoMem();
2806 mode = get_irn_mode(op);
2808 /* first convert to 32 bit signed if necessary */
2809 src_bits = get_mode_size_bits(src_mode);
2810 if (src_bits == 8) {
2811 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2813 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2815 } else if (src_bits < 32) {
2816 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2818 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2822 assert(get_mode_size_bits(mode) == 32);
2825 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2828 set_ia32_use_frame(store);
2829 set_ia32_op_type(store, ia32_AddrModeD);
2830 set_ia32_ls_mode(store, mode_Iu);
2832 /* exception for 32bit unsigned, do a 64bit spill+load */
2833 if(!mode_is_signed(mode)) {
2836 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2838 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2839 get_irg_frame(irg), noreg, nomem,
2842 set_ia32_use_frame(zero_store);
2843 set_ia32_op_type(zero_store, ia32_AddrModeD);
2844 add_ia32_am_offs_int(zero_store, 4);
2845 set_ia32_ls_mode(zero_store, mode_Iu);
2850 store = new_rd_Sync(dbgi, irg, block, 2, in);
2851 store_mode = mode_Ls;
2853 store_mode = mode_Is;
2857 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2859 set_ia32_use_frame(fild);
2860 set_ia32_op_type(fild, ia32_AddrModeS);
2861 set_ia32_ls_mode(fild, store_mode);
2863 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2869 * Create a conversion from one integer mode into another one
2871 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2872 dbg_info *dbgi, ir_node *block, ir_node *op,
2875 ir_graph *irg = current_ir_graph;
2876 int src_bits = get_mode_size_bits(src_mode);
2877 int tgt_bits = get_mode_size_bits(tgt_mode);
2878 ir_node *new_block = be_transform_node(block);
2880 ir_mode *smaller_mode;
2882 ia32_address_mode_t am;
2883 ia32_address_t *addr = &am.addr;
2885 if (src_bits < tgt_bits) {
2886 smaller_mode = src_mode;
2887 smaller_bits = src_bits;
2889 smaller_mode = tgt_mode;
2890 smaller_bits = tgt_bits;
2893 #ifdef DEBUG_libfirm
2895 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2900 match_arguments(&am, block, NULL, op, match_8bit | match_16bit | match_am |
2901 match_8bit_am | match_16bit_am);
2902 if (smaller_bits == 8) {
2903 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2904 addr->index, addr->mem, am.new_op2,
2907 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2908 addr->index, addr->mem, am.new_op2,
2911 set_am_attributes(new_node, &am);
2912 /* match_arguments assume that out-mode = in-mode, this isn't true here
2914 set_ia32_ls_mode(new_node, smaller_mode);
2915 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2916 new_node = fix_mem_proj(new_node, &am);
2921 * Transforms a Conv node.
2923 * @return The created ia32 Conv node
2925 static ir_node *gen_Conv(ir_node *node) {
2926 ir_node *block = get_nodes_block(node);
2927 ir_node *new_block = be_transform_node(block);
2928 ir_node *op = get_Conv_op(node);
2929 ir_node *new_op = NULL;
2930 ir_graph *irg = current_ir_graph;
2931 dbg_info *dbgi = get_irn_dbg_info(node);
2932 ir_mode *src_mode = get_irn_mode(op);
2933 ir_mode *tgt_mode = get_irn_mode(node);
2934 int src_bits = get_mode_size_bits(src_mode);
2935 int tgt_bits = get_mode_size_bits(tgt_mode);
2936 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2937 ir_node *nomem = new_rd_NoMem(irg);
2938 ir_node *res = NULL;
2940 if (src_mode == mode_b) {
2941 assert(mode_is_int(tgt_mode));
2942 /* nothing to do, we already model bools as 0/1 ints */
2943 return be_transform_node(op);
2946 if (src_mode == tgt_mode) {
2947 if (get_Conv_strict(node)) {
2948 if (USE_SSE2(env_cg)) {
2949 /* when we are in SSE mode, we can kill all strict no-op conversion */
2950 return be_transform_node(op);
2953 /* this should be optimized already, but who knows... */
2954 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2955 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2956 return be_transform_node(op);
2960 if (mode_is_float(src_mode)) {
2961 new_op = be_transform_node(op);
2962 /* we convert from float ... */
2963 if (mode_is_float(tgt_mode)) {
2964 if(src_mode == mode_E && tgt_mode == mode_D
2965 && !get_Conv_strict(node)) {
2966 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2971 if (USE_SSE2(env_cg)) {
2972 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2973 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2975 set_ia32_ls_mode(res, tgt_mode);
2977 if(get_Conv_strict(node)) {
2978 res = gen_x87_strict_conv(tgt_mode, new_op);
2979 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2982 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2987 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2988 if (USE_SSE2(env_cg)) {
2989 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2991 set_ia32_ls_mode(res, src_mode);
2993 return gen_x87_fp_to_gp(node);
2997 /* we convert from int ... */
2998 if (mode_is_float(tgt_mode)) {
3000 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3001 if (USE_SSE2(env_cg)) {
3002 new_op = be_transform_node(op);
3003 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3005 set_ia32_ls_mode(res, tgt_mode);
3007 res = gen_x87_gp_to_fp(node, src_mode);
3008 if(get_Conv_strict(node)) {
3009 res = gen_x87_strict_conv(tgt_mode, res);
3010 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3011 ia32_get_old_node_name(env_cg, node));
3015 } else if(tgt_mode == mode_b) {
3016 /* mode_b lowering already took care that we only have 0/1 values */
3017 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3018 src_mode, tgt_mode));
3019 return be_transform_node(op);
3022 if (src_bits == tgt_bits) {
3023 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3024 src_mode, tgt_mode));
3025 return be_transform_node(op);
3028 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3036 static int check_immediate_constraint(long val, char immediate_constraint_type)
3038 switch (immediate_constraint_type) {
3042 return val >= 0 && val <= 32;
3044 return val >= 0 && val <= 63;
3046 return val >= -128 && val <= 127;
3048 return val == 0xff || val == 0xffff;
3050 return val >= 0 && val <= 3;
3052 return val >= 0 && val <= 255;
3054 return val >= 0 && val <= 127;
3058 panic("Invalid immediate constraint found");
3062 static ir_node *try_create_Immediate(ir_node *node,
3063 char immediate_constraint_type)
3066 tarval *offset = NULL;
3067 int offset_sign = 0;
3069 ir_entity *symconst_ent = NULL;
3070 int symconst_sign = 0;
3072 ir_node *cnst = NULL;
3073 ir_node *symconst = NULL;
3076 mode = get_irn_mode(node);
3077 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3081 if(is_Minus(node)) {
3083 node = get_Minus_op(node);
3086 if(is_Const(node)) {
3089 offset_sign = minus;
3090 } else if(is_SymConst(node)) {
3093 symconst_sign = minus;
3094 } else if(is_Add(node)) {
3095 ir_node *left = get_Add_left(node);
3096 ir_node *right = get_Add_right(node);
3097 if(is_Const(left) && is_SymConst(right)) {
3100 symconst_sign = minus;
3101 offset_sign = minus;
3102 } else if(is_SymConst(left) && is_Const(right)) {
3105 symconst_sign = minus;
3106 offset_sign = minus;
3108 } else if(is_Sub(node)) {
3109 ir_node *left = get_Sub_left(node);
3110 ir_node *right = get_Sub_right(node);
3111 if(is_Const(left) && is_SymConst(right)) {
3114 symconst_sign = !minus;
3115 offset_sign = minus;
3116 } else if(is_SymConst(left) && is_Const(right)) {
3119 symconst_sign = minus;
3120 offset_sign = !minus;
3127 offset = get_Const_tarval(cnst);
3128 if(tarval_is_long(offset)) {
3129 val = get_tarval_long(offset);
3131 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3136 if(!check_immediate_constraint(val, immediate_constraint_type))
3139 if(symconst != NULL) {
3140 if(immediate_constraint_type != 0) {
3141 /* we need full 32bits for symconsts */
3145 /* unfortunately the assembler/linker doesn't support -symconst */
3149 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3151 symconst_ent = get_SymConst_entity(symconst);
3153 if(cnst == NULL && symconst == NULL)
3156 if(offset_sign && offset != NULL) {
3157 offset = tarval_neg(offset);
3160 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3165 static ir_node *create_immediate_or_transform(ir_node *node,
3166 char immediate_constraint_type)
3168 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3169 if (new_node == NULL) {
3170 new_node = be_transform_node(node);
3175 static const arch_register_req_t no_register_req = {
3176 arch_register_req_type_none,
3177 NULL, /* regclass */
3178 NULL, /* limit bitset */
3180 0 /* different pos */
3184 * An assembler constraint.
3186 typedef struct constraint_t constraint_t;
3187 struct constraint_t {
3190 const arch_register_req_t **out_reqs;
3192 const arch_register_req_t *req;
3193 unsigned immediate_possible;
3194 char immediate_type;
3197 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3199 int immediate_possible = 0;
3200 char immediate_type = 0;
3201 unsigned limited = 0;
3202 const arch_register_class_t *cls = NULL;
3203 ir_graph *irg = current_ir_graph;
3204 struct obstack *obst = get_irg_obstack(irg);
3205 arch_register_req_t *req;
3206 unsigned *limited_ptr = NULL;
3210 /* TODO: replace all the asserts with nice error messages */
3213 /* a memory constraint: no need to do anything in backend about it
3214 * (the dependencies are already respected by the memory edge of
3216 constraint->req = &no_register_req;
3228 assert(cls == NULL ||
3229 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3230 cls = &ia32_reg_classes[CLASS_ia32_gp];
3231 limited |= 1 << REG_EAX;
3234 assert(cls == NULL ||
3235 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3236 cls = &ia32_reg_classes[CLASS_ia32_gp];
3237 limited |= 1 << REG_EBX;
3240 assert(cls == NULL ||
3241 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3242 cls = &ia32_reg_classes[CLASS_ia32_gp];
3243 limited |= 1 << REG_ECX;
3246 assert(cls == NULL ||
3247 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3248 cls = &ia32_reg_classes[CLASS_ia32_gp];
3249 limited |= 1 << REG_EDX;
3252 assert(cls == NULL ||
3253 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3254 cls = &ia32_reg_classes[CLASS_ia32_gp];
3255 limited |= 1 << REG_EDI;
3258 assert(cls == NULL ||
3259 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3260 cls = &ia32_reg_classes[CLASS_ia32_gp];
3261 limited |= 1 << REG_ESI;
3264 case 'q': /* q means lower part of the regs only, this makes no
3265 * difference to Q for us (we only assigne whole registers) */
3266 assert(cls == NULL ||
3267 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3268 cls = &ia32_reg_classes[CLASS_ia32_gp];
3269 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3273 assert(cls == NULL ||
3274 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3275 cls = &ia32_reg_classes[CLASS_ia32_gp];
3276 limited |= 1 << REG_EAX | 1 << REG_EDX;
3279 assert(cls == NULL ||
3280 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3281 cls = &ia32_reg_classes[CLASS_ia32_gp];
3282 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3283 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3290 assert(cls == NULL);
3291 cls = &ia32_reg_classes[CLASS_ia32_gp];
3297 /* TODO: mark values so the x87 simulator knows about t and u */
3298 assert(cls == NULL);
3299 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3304 assert(cls == NULL);
3305 /* TODO: check that sse2 is supported */
3306 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3316 assert(!immediate_possible);
3317 immediate_possible = 1;
3318 immediate_type = *c;
3322 assert(!immediate_possible);
3323 immediate_possible = 1;
3327 assert(!immediate_possible && cls == NULL);
3328 immediate_possible = 1;
3329 cls = &ia32_reg_classes[CLASS_ia32_gp];
3342 assert(constraint->is_in && "can only specify same constraint "
3345 sscanf(c, "%d%n", &same_as, &p);
3353 /* memory constraint no need to do anything in backend about it
3354 * (the dependencies are already respected by the memory edge of
3356 constraint->req = &no_register_req;
3359 case 'E': /* no float consts yet */
3360 case 'F': /* no float consts yet */
3361 case 's': /* makes no sense on x86 */
3362 case 'X': /* we can't support that in firm */
3365 case '<': /* no autodecrement on x86 */
3366 case '>': /* no autoincrement on x86 */
3367 case 'C': /* sse constant not supported yet */
3368 case 'G': /* 80387 constant not supported yet */
3369 case 'y': /* we don't support mmx registers yet */
3370 case 'Z': /* not available in 32 bit mode */
3371 case 'e': /* not available in 32 bit mode */
3372 panic("unsupported asm constraint '%c' found in (%+F)",
3373 *c, current_ir_graph);
3376 panic("unknown asm constraint '%c' found in (%+F)", *c,
3384 const arch_register_req_t *other_constr;
3386 assert(cls == NULL && "same as and register constraint not supported");
3387 assert(!immediate_possible && "same as and immediate constraint not "
3389 assert(same_as < constraint->n_outs && "wrong constraint number in "
3390 "same_as constraint");
3392 other_constr = constraint->out_reqs[same_as];
3394 req = obstack_alloc(obst, sizeof(req[0]));
3395 req->cls = other_constr->cls;
3396 req->type = arch_register_req_type_should_be_same;
3397 req->limited = NULL;
3398 req->other_same = 1U << pos;
3399 req->other_different = 0;
3401 /* switch constraints. This is because in firm we have same_as
3402 * constraints on the output constraints while in the gcc asm syntax
3403 * they are specified on the input constraints */
3404 constraint->req = other_constr;
3405 constraint->out_reqs[same_as] = req;
3406 constraint->immediate_possible = 0;
3410 if(immediate_possible && cls == NULL) {
3411 cls = &ia32_reg_classes[CLASS_ia32_gp];
3413 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3414 assert(cls != NULL);
3416 if(immediate_possible) {
3417 assert(constraint->is_in
3418 && "immediate make no sense for output constraints");
3420 /* todo: check types (no float input on 'r' constrained in and such... */
3423 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3424 limited_ptr = (unsigned*) (req+1);
3426 req = obstack_alloc(obst, sizeof(req[0]));
3428 memset(req, 0, sizeof(req[0]));
3431 req->type = arch_register_req_type_limited;
3432 *limited_ptr = limited;
3433 req->limited = limited_ptr;
3435 req->type = arch_register_req_type_normal;
3439 constraint->req = req;
3440 constraint->immediate_possible = immediate_possible;
3441 constraint->immediate_type = immediate_type;
3444 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3451 panic("Clobbers not supported yet");
3454 static int is_memory_op(const ir_asm_constraint *constraint)
3456 ident *id = constraint->constraint;
3457 const char *str = get_id_str(id);
3460 for(c = str; *c != '\0'; ++c) {
3469 * generates code for a ASM node
3471 static ir_node *gen_ASM(ir_node *node)
3474 ir_graph *irg = current_ir_graph;
3475 ir_node *block = get_nodes_block(node);
3476 ir_node *new_block = be_transform_node(block);
3477 dbg_info *dbgi = get_irn_dbg_info(node);
3481 int n_out_constraints;
3483 const arch_register_req_t **out_reg_reqs;
3484 const arch_register_req_t **in_reg_reqs;
3485 ia32_asm_reg_t *register_map;
3486 unsigned reg_map_size = 0;
3487 struct obstack *obst;
3488 const ir_asm_constraint *in_constraints;
3489 const ir_asm_constraint *out_constraints;
3491 constraint_t parsed_constraint;
3493 arity = get_irn_arity(node);
3494 in = alloca(arity * sizeof(in[0]));
3495 memset(in, 0, arity * sizeof(in[0]));
3497 n_out_constraints = get_ASM_n_output_constraints(node);
3498 n_clobbers = get_ASM_n_clobbers(node);
3499 out_arity = n_out_constraints + n_clobbers;
3501 in_constraints = get_ASM_input_constraints(node);
3502 out_constraints = get_ASM_output_constraints(node);
3503 clobbers = get_ASM_clobbers(node);
3505 /* construct output constraints */
3506 obst = get_irg_obstack(irg);
3507 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3508 parsed_constraint.out_reqs = out_reg_reqs;
3509 parsed_constraint.n_outs = n_out_constraints;
3510 parsed_constraint.is_in = 0;
3512 for(i = 0; i < out_arity; ++i) {
3515 if(i < n_out_constraints) {
3516 const ir_asm_constraint *constraint = &out_constraints[i];
3517 c = get_id_str(constraint->constraint);
3518 parse_asm_constraint(i, &parsed_constraint, c);
3520 if(constraint->pos > reg_map_size)
3521 reg_map_size = constraint->pos;
3523 ident *glob_id = clobbers [i - n_out_constraints];
3524 c = get_id_str(glob_id);
3525 parse_clobber(node, i, &parsed_constraint, c);
3528 out_reg_reqs[i] = parsed_constraint.req;
3531 /* construct input constraints */
3532 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3533 parsed_constraint.is_in = 1;
3534 for(i = 0; i < arity; ++i) {
3535 const ir_asm_constraint *constraint = &in_constraints[i];
3536 ident *constr_id = constraint->constraint;
3537 const char *c = get_id_str(constr_id);
3539 parse_asm_constraint(i, &parsed_constraint, c);
3540 in_reg_reqs[i] = parsed_constraint.req;
3542 if(constraint->pos > reg_map_size)
3543 reg_map_size = constraint->pos;
3545 if(parsed_constraint.immediate_possible) {
3546 ir_node *pred = get_irn_n(node, i);
3547 char imm_type = parsed_constraint.immediate_type;
3548 ir_node *immediate = try_create_Immediate(pred, imm_type);
3550 if(immediate != NULL) {
3557 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3558 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3560 for(i = 0; i < n_out_constraints; ++i) {
3561 const ir_asm_constraint *constraint = &out_constraints[i];
3562 unsigned pos = constraint->pos;
3564 assert(pos < reg_map_size);
3565 register_map[pos].use_input = 0;
3566 register_map[pos].valid = 1;
3567 register_map[pos].memory = is_memory_op(constraint);
3568 register_map[pos].inout_pos = i;
3569 register_map[pos].mode = constraint->mode;
3572 /* transform inputs */
3573 for(i = 0; i < arity; ++i) {
3574 const ir_asm_constraint *constraint = &in_constraints[i];
3575 unsigned pos = constraint->pos;
3576 ir_node *pred = get_irn_n(node, i);
3577 ir_node *transformed;
3579 assert(pos < reg_map_size);
3580 register_map[pos].use_input = 1;
3581 register_map[pos].valid = 1;
3582 register_map[pos].memory = is_memory_op(constraint);
3583 register_map[pos].inout_pos = i;
3584 register_map[pos].mode = constraint->mode;
3589 transformed = be_transform_node(pred);
3590 in[i] = transformed;
3593 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3594 get_ASM_text(node), register_map);
3596 set_ia32_out_req_all(new_node, out_reg_reqs);
3597 set_ia32_in_req_all(new_node, in_reg_reqs);
3599 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3604 /********************************************
3607 * | |__ ___ _ __ ___ __| | ___ ___
3608 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3609 * | |_) | __/ | | | (_) | (_| | __/\__ \
3610 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3612 ********************************************/
3615 * Transforms a FrameAddr into an ia32 Add.
3617 static ir_node *gen_be_FrameAddr(ir_node *node) {
3618 ir_node *block = be_transform_node(get_nodes_block(node));
3619 ir_node *op = be_get_FrameAddr_frame(node);
3620 ir_node *new_op = be_transform_node(op);
3621 ir_graph *irg = current_ir_graph;
3622 dbg_info *dbgi = get_irn_dbg_info(node);
3623 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3626 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3627 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3628 set_ia32_use_frame(new_node);
3630 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3636 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3638 static ir_node *gen_be_Return(ir_node *node) {
3639 ir_graph *irg = current_ir_graph;
3640 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3641 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3642 ir_entity *ent = get_irg_entity(irg);
3643 ir_type *tp = get_entity_type(ent);
3648 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3649 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3652 int pn_ret_val, pn_ret_mem, arity, i;
3654 assert(ret_val != NULL);
3655 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3656 return be_duplicate_node(node);
3659 res_type = get_method_res_type(tp, 0);
3661 if (! is_Primitive_type(res_type)) {
3662 return be_duplicate_node(node);
3665 mode = get_type_mode(res_type);
3666 if (! mode_is_float(mode)) {
3667 return be_duplicate_node(node);
3670 assert(get_method_n_ress(tp) == 1);
3672 pn_ret_val = get_Proj_proj(ret_val);
3673 pn_ret_mem = get_Proj_proj(ret_mem);
3675 /* get the Barrier */
3676 barrier = get_Proj_pred(ret_val);
3678 /* get result input of the Barrier */
3679 ret_val = get_irn_n(barrier, pn_ret_val);
3680 new_ret_val = be_transform_node(ret_val);
3682 /* get memory input of the Barrier */
3683 ret_mem = get_irn_n(barrier, pn_ret_mem);
3684 new_ret_mem = be_transform_node(ret_mem);
3686 frame = get_irg_frame(irg);
3688 dbgi = get_irn_dbg_info(barrier);
3689 block = be_transform_node(get_nodes_block(barrier));
3691 noreg = ia32_new_NoReg_gp(env_cg);
3693 /* store xmm0 onto stack */
3694 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3695 new_ret_mem, new_ret_val);
3696 set_ia32_ls_mode(sse_store, mode);
3697 set_ia32_op_type(sse_store, ia32_AddrModeD);
3698 set_ia32_use_frame(sse_store);
3700 /* load into x87 register */
3701 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3702 set_ia32_op_type(fld, ia32_AddrModeS);
3703 set_ia32_use_frame(fld);
3705 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3706 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3708 /* create a new barrier */
3709 arity = get_irn_arity(barrier);
3710 in = alloca(arity * sizeof(in[0]));
3711 for (i = 0; i < arity; ++i) {
3714 if (i == pn_ret_val) {
3716 } else if (i == pn_ret_mem) {
3719 ir_node *in = get_irn_n(barrier, i);
3720 new_in = be_transform_node(in);
3725 new_barrier = new_ir_node(dbgi, irg, block,
3726 get_irn_op(barrier), get_irn_mode(barrier),
3728 copy_node_attr(barrier, new_barrier);
3729 be_duplicate_deps(barrier, new_barrier);
3730 be_set_transformed_node(barrier, new_barrier);
3731 mark_irn_visited(barrier);
3733 /* transform normally */
3734 return be_duplicate_node(node);
3738 * Transform a be_AddSP into an ia32_SubSP.
3740 static ir_node *gen_be_AddSP(ir_node *node)
3742 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3743 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3745 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3749 * Transform a be_SubSP into an ia32_AddSP
3751 static ir_node *gen_be_SubSP(ir_node *node)
3753 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3754 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3756 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3760 * This function just sets the register for the Unknown node
3761 * as this is not done during register allocation because Unknown
3762 * is an "ignore" node.
3764 static ir_node *gen_Unknown(ir_node *node) {
3765 ir_mode *mode = get_irn_mode(node);
3767 if (mode_is_float(mode)) {
3768 if (USE_SSE2(env_cg)) {
3769 return ia32_new_Unknown_xmm(env_cg);
3771 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3772 ir_graph *irg = current_ir_graph;
3773 dbg_info *dbgi = get_irn_dbg_info(node);
3774 ir_node *block = get_irg_start_block(irg);
3775 return new_rd_ia32_vfldz(dbgi, irg, block);
3777 } else if (mode_needs_gp_reg(mode)) {
3778 return ia32_new_Unknown_gp(env_cg);
3780 panic("unsupported Unknown-Mode");
3786 * Change some phi modes
3788 static ir_node *gen_Phi(ir_node *node) {
3789 ir_node *block = be_transform_node(get_nodes_block(node));
3790 ir_graph *irg = current_ir_graph;
3791 dbg_info *dbgi = get_irn_dbg_info(node);
3792 ir_mode *mode = get_irn_mode(node);
3795 if(mode_needs_gp_reg(mode)) {
3796 /* we shouldn't have any 64bit stuff around anymore */
3797 assert(get_mode_size_bits(mode) <= 32);
3798 /* all integer operations are on 32bit registers now */
3800 } else if(mode_is_float(mode)) {
3801 if (USE_SSE2(env_cg)) {
3808 /* phi nodes allow loops, so we use the old arguments for now
3809 * and fix this later */
3810 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3811 get_irn_in(node) + 1);
3812 copy_node_attr(node, phi);
3813 be_duplicate_deps(node, phi);
3815 be_set_transformed_node(node, phi);
3816 be_enqueue_preds(node);
3824 static ir_node *gen_IJmp(ir_node *node)
3826 ir_node *block = get_nodes_block(node);
3827 ir_node *new_block = be_transform_node(block);
3828 ir_graph *irg = current_ir_graph;
3829 dbg_info *dbgi = get_irn_dbg_info(node);
3830 ir_node *op = get_IJmp_target(node);
3832 ia32_address_mode_t am;
3833 ia32_address_t *addr = &am.addr;
3835 assert(get_irn_mode(op) == mode_P);
3837 match_arguments(&am, block, NULL, op,
3838 match_am | match_8bit_am | match_16bit_am |
3839 match_immediate | match_8bit | match_16bit);
3841 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3842 addr->mem, am.new_op2);
3843 set_am_attributes(new_node, &am);
3844 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3846 new_node = fix_mem_proj(new_node, &am);
3852 /**********************************************************************
3855 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3856 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3857 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3858 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3860 **********************************************************************/
3862 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3864 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3867 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3868 ir_node *val, ir_node *mem);
3871 * Transforms a lowered Load into a "real" one.
3873 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3875 ir_node *block = be_transform_node(get_nodes_block(node));
3876 ir_node *ptr = get_irn_n(node, 0);
3877 ir_node *new_ptr = be_transform_node(ptr);
3878 ir_node *mem = get_irn_n(node, 1);
3879 ir_node *new_mem = be_transform_node(mem);
3880 ir_graph *irg = current_ir_graph;
3881 dbg_info *dbgi = get_irn_dbg_info(node);
3882 ir_mode *mode = get_ia32_ls_mode(node);
3883 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3886 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3888 set_ia32_op_type(new_op, ia32_AddrModeS);
3889 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3890 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3891 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3892 if (is_ia32_am_sc_sign(node))
3893 set_ia32_am_sc_sign(new_op);
3894 set_ia32_ls_mode(new_op, mode);
3895 if (is_ia32_use_frame(node)) {
3896 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3897 set_ia32_use_frame(new_op);
3900 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3906 * Transforms a lowered Store into a "real" one.
3908 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3910 ir_node *block = be_transform_node(get_nodes_block(node));
3911 ir_node *ptr = get_irn_n(node, 0);
3912 ir_node *new_ptr = be_transform_node(ptr);
3913 ir_node *val = get_irn_n(node, 1);
3914 ir_node *new_val = be_transform_node(val);
3915 ir_node *mem = get_irn_n(node, 2);
3916 ir_node *new_mem = be_transform_node(mem);
3917 ir_graph *irg = current_ir_graph;
3918 dbg_info *dbgi = get_irn_dbg_info(node);
3919 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3920 ir_mode *mode = get_ia32_ls_mode(node);
3924 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3926 am_offs = get_ia32_am_offs_int(node);
3927 add_ia32_am_offs_int(new_op, am_offs);
3929 set_ia32_op_type(new_op, ia32_AddrModeD);
3930 set_ia32_ls_mode(new_op, mode);
3931 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3932 set_ia32_use_frame(new_op);
3934 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3939 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3941 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3942 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3944 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3945 match_immediate | match_mode_neutral);
3948 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3950 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3951 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3952 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3956 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3958 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3959 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3960 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3964 static ir_node *gen_ia32_l_Add(ir_node *node) {
3965 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3966 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3967 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3968 match_commutative | match_am | match_immediate |
3969 match_mode_neutral);
3971 if(is_Proj(lowered)) {
3972 lowered = get_Proj_pred(lowered);
3974 assert(is_ia32_Add(lowered));
3975 set_irn_mode(lowered, mode_T);
3981 static ir_node *gen_ia32_l_Adc(ir_node *node)
3983 return gen_binop_flags(node, new_rd_ia32_Adc,
3984 match_commutative | match_am | match_immediate |
3985 match_mode_neutral);
3989 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3991 * @param node The node to transform
3992 * @return the created ia32 vfild node
3994 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3995 return gen_lowered_Load(node, new_rd_ia32_vfild);
3999 * Transforms an ia32_l_Load into a "real" ia32_Load node
4001 * @param node The node to transform
4002 * @return the created ia32 Load node
4004 static ir_node *gen_ia32_l_Load(ir_node *node) {
4005 return gen_lowered_Load(node, new_rd_ia32_Load);
4009 * Transforms an ia32_l_Store into a "real" ia32_Store node
4011 * @param node The node to transform
4012 * @return the created ia32 Store node
4014 static ir_node *gen_ia32_l_Store(ir_node *node) {
4015 return gen_lowered_Store(node, new_rd_ia32_Store);
4019 * Transforms a l_vfist into a "real" vfist node.
4021 * @param node The node to transform
4022 * @return the created ia32 vfist node
4024 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4025 ir_node *block = be_transform_node(get_nodes_block(node));
4026 ir_node *ptr = get_irn_n(node, 0);
4027 ir_node *new_ptr = be_transform_node(ptr);
4028 ir_node *val = get_irn_n(node, 1);
4029 ir_node *new_val = be_transform_node(val);
4030 ir_node *mem = get_irn_n(node, 2);
4031 ir_node *new_mem = be_transform_node(mem);
4032 ir_graph *irg = current_ir_graph;
4033 dbg_info *dbgi = get_irn_dbg_info(node);
4034 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4035 ir_mode *mode = get_ia32_ls_mode(node);
4036 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4040 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4041 new_val, trunc_mode);
4043 am_offs = get_ia32_am_offs_int(node);
4044 add_ia32_am_offs_int(new_op, am_offs);
4046 set_ia32_op_type(new_op, ia32_AddrModeD);
4047 set_ia32_ls_mode(new_op, mode);
4048 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4049 set_ia32_use_frame(new_op);
4051 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4057 * Transforms a l_MulS into a "real" MulS node.
4059 * @return the created ia32 Mul node
4061 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4062 ir_node *left = get_binop_left(node);
4063 ir_node *right = get_binop_right(node);
4065 return gen_binop(node, left, right, new_rd_ia32_Mul,
4066 match_commutative | match_am | match_mode_neutral);
4070 * Transforms a l_IMulS into a "real" IMul1OPS node.
4072 * @return the created ia32 IMul1OP node
4074 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4075 ir_node *left = get_binop_left(node);
4076 ir_node *right = get_binop_right(node);
4078 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4079 match_commutative | match_am | match_mode_neutral);
4082 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4083 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4084 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4085 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4086 match_am | match_immediate | match_mode_neutral);
4088 if(is_Proj(lowered)) {
4089 lowered = get_Proj_pred(lowered);
4091 assert(is_ia32_Sub(lowered));
4092 set_irn_mode(lowered, mode_T);
4098 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4099 return gen_binop_flags(node, new_rd_ia32_Sbb,
4100 match_am | match_immediate | match_mode_neutral);
4104 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4105 * op1 - target to be shifted
4106 * op2 - contains bits to be shifted into target
4108 * Only op3 can be an immediate.
4110 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4111 ir_node *low, ir_node *count)
4113 ir_node *block = get_nodes_block(node);
4114 ir_node *new_block = be_transform_node(block);
4115 ir_graph *irg = current_ir_graph;
4116 dbg_info *dbgi = get_irn_dbg_info(node);
4117 ir_node *new_high = be_transform_node(high);
4118 ir_node *new_low = be_transform_node(low);
4122 /* the shift amount can be any mode that is bigger than 5 bits, since all
4123 * other bits are ignored anyway */
4124 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4125 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4126 count = get_Conv_op(count);
4128 new_count = create_immediate_or_transform(count, 0);
4130 if (is_ia32_l_ShlD(node)) {
4131 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4134 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4137 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4142 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4144 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4145 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4146 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4147 return gen_lowered_64bit_shifts(node, high, low, count);
4150 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4152 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4153 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4154 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4155 return gen_lowered_64bit_shifts(node, high, low, count);
4159 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4161 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4162 ir_node *block = be_transform_node(get_nodes_block(node));
4163 ir_node *val = get_irn_n(node, 1);
4164 ir_node *new_val = be_transform_node(val);
4165 ia32_code_gen_t *cg = env_cg;
4166 ir_node *res = NULL;
4167 ir_graph *irg = current_ir_graph;
4169 ir_node *noreg, *new_ptr, *new_mem;
4176 mem = get_irn_n(node, 2);
4177 new_mem = be_transform_node(mem);
4178 ptr = get_irn_n(node, 0);
4179 new_ptr = be_transform_node(ptr);
4180 noreg = ia32_new_NoReg_gp(cg);
4181 dbgi = get_irn_dbg_info(node);
4183 /* Store x87 -> MEM */
4184 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4185 get_ia32_ls_mode(node));
4186 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4187 set_ia32_use_frame(res);
4188 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4189 set_ia32_op_type(res, ia32_AddrModeD);
4191 /* Load MEM -> SSE */
4192 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4193 get_ia32_ls_mode(node));
4194 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4195 set_ia32_use_frame(res);
4196 set_ia32_op_type(res, ia32_AddrModeS);
4197 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4203 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4205 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4206 ir_node *block = be_transform_node(get_nodes_block(node));
4207 ir_node *val = get_irn_n(node, 1);
4208 ir_node *new_val = be_transform_node(val);
4209 ia32_code_gen_t *cg = env_cg;
4210 ir_graph *irg = current_ir_graph;
4211 ir_node *res = NULL;
4212 ir_entity *fent = get_ia32_frame_ent(node);
4213 ir_mode *lsmode = get_ia32_ls_mode(node);
4215 ir_node *noreg, *new_ptr, *new_mem;
4219 if (! USE_SSE2(cg)) {
4220 /* SSE unit is not used -> skip this node. */
4224 ptr = get_irn_n(node, 0);
4225 new_ptr = be_transform_node(ptr);
4226 mem = get_irn_n(node, 2);
4227 new_mem = be_transform_node(mem);
4228 noreg = ia32_new_NoReg_gp(cg);
4229 dbgi = get_irn_dbg_info(node);
4231 /* Store SSE -> MEM */
4232 if (is_ia32_xLoad(skip_Proj(new_val))) {
4233 ir_node *ld = skip_Proj(new_val);
4235 /* we can vfld the value directly into the fpu */
4236 fent = get_ia32_frame_ent(ld);
4237 ptr = get_irn_n(ld, 0);
4238 offs = get_ia32_am_offs_int(ld);
4240 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4242 set_ia32_frame_ent(res, fent);
4243 set_ia32_use_frame(res);
4244 set_ia32_ls_mode(res, lsmode);
4245 set_ia32_op_type(res, ia32_AddrModeD);
4249 /* Load MEM -> x87 */
4250 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4251 set_ia32_frame_ent(res, fent);
4252 set_ia32_use_frame(res);
4253 add_ia32_am_offs_int(res, offs);
4254 set_ia32_op_type(res, ia32_AddrModeS);
4255 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4260 /*********************************************************
4263 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4264 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4265 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4266 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4268 *********************************************************/
4271 * the BAD transformer.
4273 static ir_node *bad_transform(ir_node *node) {
4274 panic("No transform function for %+F available.\n", node);
4279 * Transform the Projs of an AddSP.
4281 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4282 ir_node *block = be_transform_node(get_nodes_block(node));
4283 ir_node *pred = get_Proj_pred(node);
4284 ir_node *new_pred = be_transform_node(pred);
4285 ir_graph *irg = current_ir_graph;
4286 dbg_info *dbgi = get_irn_dbg_info(node);
4287 long proj = get_Proj_proj(node);
4289 if (proj == pn_be_AddSP_sp) {
4290 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4291 pn_ia32_SubSP_stack);
4292 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4294 } else if(proj == pn_be_AddSP_res) {
4295 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4296 pn_ia32_SubSP_addr);
4297 } else if (proj == pn_be_AddSP_M) {
4298 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4302 return new_rd_Unknown(irg, get_irn_mode(node));
4306 * Transform the Projs of a SubSP.
4308 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4309 ir_node *block = be_transform_node(get_nodes_block(node));
4310 ir_node *pred = get_Proj_pred(node);
4311 ir_node *new_pred = be_transform_node(pred);
4312 ir_graph *irg = current_ir_graph;
4313 dbg_info *dbgi = get_irn_dbg_info(node);
4314 long proj = get_Proj_proj(node);
4316 if (proj == pn_be_SubSP_sp) {
4317 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4318 pn_ia32_AddSP_stack);
4319 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4321 } else if (proj == pn_be_SubSP_M) {
4322 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4326 return new_rd_Unknown(irg, get_irn_mode(node));
4330 * Transform and renumber the Projs from a Load.
4332 static ir_node *gen_Proj_Load(ir_node *node) {
4334 ir_node *block = be_transform_node(get_nodes_block(node));
4335 ir_node *pred = get_Proj_pred(node);
4336 ir_graph *irg = current_ir_graph;
4337 dbg_info *dbgi = get_irn_dbg_info(node);
4338 long proj = get_Proj_proj(node);
4341 /* loads might be part of source address mode matches, so we don't
4342 transform the ProjMs yet (with the exception of loads whose result is
4345 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4348 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4350 /* this is needed, because sometimes we have loops that are only
4351 reachable through the ProjM */
4352 be_enqueue_preds(node);
4353 /* do it in 2 steps, to silence firm verifier */
4354 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4355 set_Proj_proj(res, pn_ia32_Load_M);
4359 /* renumber the proj */
4360 new_pred = be_transform_node(pred);
4361 if (is_ia32_Load(new_pred)) {
4362 if (proj == pn_Load_res) {
4363 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4365 } else if (proj == pn_Load_M) {
4366 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4369 } else if(is_ia32_Conv_I2I(new_pred)
4370 || is_ia32_Conv_I2I8Bit(new_pred)) {
4371 set_irn_mode(new_pred, mode_T);
4372 if (proj == pn_Load_res) {
4373 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4374 } else if (proj == pn_Load_M) {
4375 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4377 } else if (is_ia32_xLoad(new_pred)) {
4378 if (proj == pn_Load_res) {
4379 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4381 } else if (proj == pn_Load_M) {
4382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4385 } else if (is_ia32_vfld(new_pred)) {
4386 if (proj == pn_Load_res) {
4387 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4389 } else if (proj == pn_Load_M) {
4390 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4394 /* can happen for ProJMs when source address mode happened for the
4397 /* however it should not be the result proj, as that would mean the
4398 load had multiple users and should not have been used for
4400 if(proj != pn_Load_M) {
4401 panic("internal error: transformed node not a Load");
4403 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4407 return new_rd_Unknown(irg, get_irn_mode(node));
4411 * Transform and renumber the Projs from a DivMod like instruction.
4413 static ir_node *gen_Proj_DivMod(ir_node *node) {
4414 ir_node *block = be_transform_node(get_nodes_block(node));
4415 ir_node *pred = get_Proj_pred(node);
4416 ir_node *new_pred = be_transform_node(pred);
4417 ir_graph *irg = current_ir_graph;
4418 dbg_info *dbgi = get_irn_dbg_info(node);
4419 ir_mode *mode = get_irn_mode(node);
4420 long proj = get_Proj_proj(node);
4422 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4424 switch (get_irn_opcode(pred)) {
4428 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4430 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4438 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4440 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4448 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4449 case pn_DivMod_res_div:
4450 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4451 case pn_DivMod_res_mod:
4452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4462 return new_rd_Unknown(irg, mode);
4466 * Transform and renumber the Projs from a CopyB.
4468 static ir_node *gen_Proj_CopyB(ir_node *node) {
4469 ir_node *block = be_transform_node(get_nodes_block(node));
4470 ir_node *pred = get_Proj_pred(node);
4471 ir_node *new_pred = be_transform_node(pred);
4472 ir_graph *irg = current_ir_graph;
4473 dbg_info *dbgi = get_irn_dbg_info(node);
4474 ir_mode *mode = get_irn_mode(node);
4475 long proj = get_Proj_proj(node);
4478 case pn_CopyB_M_regular:
4479 if (is_ia32_CopyB_i(new_pred)) {
4480 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4481 } else if (is_ia32_CopyB(new_pred)) {
4482 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4490 return new_rd_Unknown(irg, mode);
4494 * Transform and renumber the Projs from a Quot.
4496 static ir_node *gen_Proj_Quot(ir_node *node) {
4497 ir_node *block = be_transform_node(get_nodes_block(node));
4498 ir_node *pred = get_Proj_pred(node);
4499 ir_node *new_pred = be_transform_node(pred);
4500 ir_graph *irg = current_ir_graph;
4501 dbg_info *dbgi = get_irn_dbg_info(node);
4502 ir_mode *mode = get_irn_mode(node);
4503 long proj = get_Proj_proj(node);
4507 if (is_ia32_xDiv(new_pred)) {
4508 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4509 } else if (is_ia32_vfdiv(new_pred)) {
4510 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4514 if (is_ia32_xDiv(new_pred)) {
4515 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4516 } else if (is_ia32_vfdiv(new_pred)) {
4517 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4525 return new_rd_Unknown(irg, mode);
4529 * Transform the Thread Local Storage Proj.
4531 static ir_node *gen_Proj_tls(ir_node *node) {
4532 ir_node *block = be_transform_node(get_nodes_block(node));
4533 ir_graph *irg = current_ir_graph;
4534 dbg_info *dbgi = NULL;
4535 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4540 static ir_node *gen_be_Call(ir_node *node) {
4541 ir_node *res = be_duplicate_node(node);
4542 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4547 static ir_node *gen_be_IncSP(ir_node *node) {
4548 ir_node *res = be_duplicate_node(node);
4549 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4555 * Transform the Projs from a be_Call.
4557 static ir_node *gen_Proj_be_Call(ir_node *node) {
4558 ir_node *block = be_transform_node(get_nodes_block(node));
4559 ir_node *call = get_Proj_pred(node);
4560 ir_node *new_call = be_transform_node(call);
4561 ir_graph *irg = current_ir_graph;
4562 dbg_info *dbgi = get_irn_dbg_info(node);
4563 ir_type *method_type = be_Call_get_type(call);
4564 int n_res = get_method_n_ress(method_type);
4565 long proj = get_Proj_proj(node);
4566 ir_mode *mode = get_irn_mode(node);
4568 const arch_register_class_t *cls;
4570 /* The following is kinda tricky: If we're using SSE, then we have to
4571 * move the result value of the call in floating point registers to an
4572 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4573 * after the call, we have to make sure to correctly make the
4574 * MemProj and the result Proj use these 2 nodes
4576 if (proj == pn_be_Call_M_regular) {
4577 // get new node for result, are we doing the sse load/store hack?
4578 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4579 ir_node *call_res_new;
4580 ir_node *call_res_pred = NULL;
4582 if (call_res != NULL) {
4583 call_res_new = be_transform_node(call_res);
4584 call_res_pred = get_Proj_pred(call_res_new);
4587 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4588 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4589 pn_be_Call_M_regular);
4591 assert(is_ia32_xLoad(call_res_pred));
4592 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4596 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4597 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4598 && USE_SSE2(env_cg)) {
4600 ir_node *frame = get_irg_frame(irg);
4601 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4603 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4606 /* in case there is no memory output: create one to serialize the copy
4608 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4609 pn_be_Call_M_regular);
4610 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4611 pn_be_Call_first_res);
4613 /* store st(0) onto stack */
4614 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4616 set_ia32_op_type(fstp, ia32_AddrModeD);
4617 set_ia32_use_frame(fstp);
4619 /* load into SSE register */
4620 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4622 set_ia32_op_type(sse_load, ia32_AddrModeS);
4623 set_ia32_use_frame(sse_load);
4625 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4631 /* transform call modes */
4632 if (mode_is_data(mode)) {
4633 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4637 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4641 * Transform the Projs from a Cmp.
4643 static ir_node *gen_Proj_Cmp(ir_node *node)
4646 panic("not all mode_b nodes are lowered");
4649 /* normally Cmps are processed when looking at Cond nodes, but this case
4650 * can happen in complicated Psi conditions */
4651 dbg_info *dbgi = get_irn_dbg_info(node);
4652 ir_node *block = get_nodes_block(node);
4653 ir_node *new_block = be_transform_node(block);
4654 ir_node *cmp = get_Proj_pred(node);
4655 ir_node *new_cmp = be_transform_node(cmp);
4656 long pnc = get_Proj_proj(node);
4659 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4666 * Transform and potentially renumber Proj nodes.
4668 static ir_node *gen_Proj(ir_node *node) {
4669 ir_graph *irg = current_ir_graph;
4670 dbg_info *dbgi = get_irn_dbg_info(node);
4671 ir_node *pred = get_Proj_pred(node);
4672 long proj = get_Proj_proj(node);
4674 if (is_Store(pred)) {
4675 if (proj == pn_Store_M) {
4676 return be_transform_node(pred);
4679 return new_r_Bad(irg);
4681 } else if (is_Load(pred)) {
4682 return gen_Proj_Load(node);
4683 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4684 return gen_Proj_DivMod(node);
4685 } else if (is_CopyB(pred)) {
4686 return gen_Proj_CopyB(node);
4687 } else if (is_Quot(pred)) {
4688 return gen_Proj_Quot(node);
4689 } else if (be_is_SubSP(pred)) {
4690 return gen_Proj_be_SubSP(node);
4691 } else if (be_is_AddSP(pred)) {
4692 return gen_Proj_be_AddSP(node);
4693 } else if (be_is_Call(pred)) {
4694 return gen_Proj_be_Call(node);
4695 } else if (is_Cmp(pred)) {
4696 return gen_Proj_Cmp(node);
4697 } else if (get_irn_op(pred) == op_Start) {
4698 if (proj == pn_Start_X_initial_exec) {
4699 ir_node *block = get_nodes_block(pred);
4702 /* we exchange the ProjX with a jump */
4703 block = be_transform_node(block);
4704 jump = new_rd_Jmp(dbgi, irg, block);
4707 if (node == be_get_old_anchor(anchor_tls)) {
4708 return gen_Proj_tls(node);
4711 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4715 ir_node *new_pred = be_transform_node(pred);
4716 ir_node *block = be_transform_node(get_nodes_block(node));
4717 ir_mode *mode = get_irn_mode(node);
4718 if (mode_needs_gp_reg(mode)) {
4719 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4720 get_Proj_proj(node));
4721 #ifdef DEBUG_libfirm
4722 new_proj->node_nr = node->node_nr;
4728 return be_duplicate_node(node);
4732 * Enters all transform functions into the generic pointer
4734 static void register_transformers(void)
4738 /* first clear the generic function pointer for all ops */
4739 clear_irp_opcodes_generic_func();
4741 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4742 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4780 /* transform ops from intrinsic lowering */
4796 GEN(ia32_l_X87toSSE);
4797 GEN(ia32_l_SSEtoX87);
4803 /* we should never see these nodes */
4818 /* handle generic backend nodes */
4827 op_Mulh = get_op_Mulh();
4836 * Pre-transform all unknown and noreg nodes.
4838 static void ia32_pretransform_node(void *arch_cg) {
4839 ia32_code_gen_t *cg = arch_cg;
4841 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4842 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4843 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4844 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4845 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4846 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4851 * Walker, checks if all ia32 nodes producing more than one result have
4852 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4854 static void add_missing_keep_walker(ir_node *node, void *data)
4857 unsigned found_projs = 0;
4858 const ir_edge_t *edge;
4859 ir_mode *mode = get_irn_mode(node);
4864 if(!is_ia32_irn(node))
4867 n_outs = get_ia32_n_res(node);
4870 if(is_ia32_SwitchJmp(node))
4873 assert(n_outs < (int) sizeof(unsigned) * 8);
4874 foreach_out_edge(node, edge) {
4875 ir_node *proj = get_edge_src_irn(edge);
4876 int pn = get_Proj_proj(proj);
4878 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4879 found_projs |= 1 << pn;
4883 /* are keeps missing? */
4885 for(i = 0; i < n_outs; ++i) {
4888 const arch_register_req_t *req;
4889 const arch_register_class_t *class;
4891 if(found_projs & (1 << i)) {
4895 req = get_ia32_out_req(node, i);
4900 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4904 block = get_nodes_block(node);
4905 in[0] = new_r_Proj(current_ir_graph, block, node,
4906 arch_register_class_mode(class), i);
4907 if(last_keep != NULL) {
4908 be_Keep_add_node(last_keep, class, in[0]);
4910 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4911 if(sched_is_scheduled(node)) {
4912 sched_add_after(node, last_keep);
4919 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4922 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4924 ir_graph *irg = be_get_birg_irg(cg->birg);
4925 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4928 /* do the transformation */
4929 void ia32_transform_graph(ia32_code_gen_t *cg) {
4931 ir_graph *irg = cg->irg;
4932 int opt_arch = cg->isa->opt_arch;
4933 int arch = cg->isa->arch;
4935 /* TODO: look at cpu and fill transform config in with that... */
4936 transform_config.use_incdec = 1;
4937 transform_config.use_sse2 = 0;
4938 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4939 transform_config.use_ftst = 0;
4940 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4941 transform_config.use_fucomi = 1;
4942 transform_config.use_cmov = IS_P6_ARCH(arch);
4944 register_transformers();
4946 initial_fpcw = NULL;
4948 heights = heights_new(irg);
4949 ia32_calculate_non_address_mode_nodes(cg->birg);
4951 /* the transform phase is not safe for CSE (yet) because several nodes get
4952 * attributes set after their creation */
4953 cse_last = get_opt_cse();
4956 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4958 set_opt_cse(cse_last);
4960 ia32_free_non_address_mode_nodes();
4961 heights_free(heights);
4965 void ia32_init_transform(void)
4967 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");