2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
29 #include "../benode_t.h"
30 #include "../besched.h"
32 #include "bearch_ia32_t.h"
34 #include "ia32_nodes_attr.h"
35 #include "../arch/archop.h" /* we need this for Min and Max nodes */
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
40 #include "gen_ia32_regalloc_if.h"
42 #define SFP_SIGN "0x80000000"
43 #define DFP_SIGN "0x8000000000000000"
44 #define SFP_ABS "0x7FFFFFFF"
45 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
47 #define TP_SFP_SIGN "ia32_sfp_sign"
48 #define TP_DFP_SIGN "ia32_dfp_sign"
49 #define TP_SFP_ABS "ia32_sfp_abs"
50 #define TP_DFP_ABS "ia32_dfp_abs"
52 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
53 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
54 #define ENT_SFP_ABS "IA32_SFP_ABS"
55 #define ENT_DFP_ABS "IA32_DFP_ABS"
57 extern ir_op *get_op_Mulh(void);
59 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
60 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
62 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
63 ir_node *op, ir_node *mem, ir_mode *mode);
66 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
69 /****************************************************************************************************
71 * | | | | / _| | | (_)
72 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
73 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
74 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
75 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
77 ****************************************************************************************************/
80 * Gets the Proj with number pn from irn.
82 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
83 const ir_edge_t *edge;
85 assert(get_irn_mode(irn) == mode_T && "need mode_T");
87 foreach_out_edge(irn, edge) {
88 proj = get_edge_src_irn(edge);
90 if (get_Proj_proj(proj) == pn)
97 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
98 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
101 const char *ent_name;
102 const char *cnst_str;
103 } names [ia32_known_const_max] = {
104 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
105 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
106 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
107 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
109 static struct entity *ent_cache[ia32_known_const_max];
111 const char *tp_name, *ent_name, *cnst_str;
118 ent_name = names[kct].ent_name;
119 if (! ent_cache[kct]) {
120 tp_name = names[kct].tp_name;
121 cnst_str = names[kct].cnst_str;
123 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
124 tp = new_type_primitive(new_id_from_str(tp_name), mode);
125 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
127 set_entity_ld_ident(ent, get_entity_ident(ent));
128 set_entity_visibility(ent, visibility_local);
129 set_entity_variability(ent, variability_constant);
130 set_entity_allocation(ent, allocation_static);
132 /* we create a new entity here: It's initialization must resist on the
134 rem = current_ir_graph;
135 current_ir_graph = get_const_code_irg();
136 cnst = new_Const(mode, tv);
137 current_ir_graph = rem;
139 set_atomic_ent_value(ent, cnst);
141 /* cache the entry */
142 ent_cache[kct] = ent;
145 return get_entity_ident(ent_cache[kct]);
150 * Prints the old node name on cg obst and returns a pointer to it.
152 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
153 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
155 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
156 obstack_1grow(isa->name_obst, 0);
157 isa->name_obst_size += obstack_object_size(isa->name_obst);
158 return obstack_finish(isa->name_obst);
162 /* determine if one operator is an Imm */
163 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
165 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
166 else return is_ia32_Cnst(op2) ? op2 : NULL;
169 /* determine if one operator is not an Imm */
170 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
171 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
176 * Construct a standard binary operation, set AM and immediate if required.
178 * @param env The transformation environment
179 * @param op1 The first operand
180 * @param op2 The second operand
181 * @param func The node constructor function
182 * @return The constructed ia32 node.
184 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
185 ir_node *new_op = NULL;
186 ir_mode *mode = env->mode;
187 dbg_info *dbg = env->dbg;
188 ir_graph *irg = env->irg;
189 ir_node *block = env->block;
190 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
191 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
192 ir_node *nomem = new_NoMem();
193 ir_node *expr_op, *imm_op;
194 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
196 /* Check if immediate optimization is on and */
197 /* if it's an operation with immediate. */
198 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
202 else if (is_op_commutative(get_irn_op(env->irn))) {
203 imm_op = get_immediate_op(op1, op2);
204 expr_op = get_expr_op(op1, op2);
207 imm_op = get_immediate_op(NULL, op2);
208 expr_op = get_expr_op(op1, op2);
211 assert((expr_op || imm_op) && "invalid operands");
214 /* We have two consts here: not yet supported */
218 if (mode_is_float(mode)) {
219 /* floating point operations */
221 DB((mod, LEVEL_1, "FP with immediate ..."));
222 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
223 set_ia32_Immop_attr(new_op, imm_op);
224 set_ia32_am_support(new_op, ia32_am_None);
227 DB((mod, LEVEL_1, "FP binop ..."));
228 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
229 set_ia32_am_support(new_op, ia32_am_Source);
233 /* integer operations */
235 /* This is expr + const */
236 DB((mod, LEVEL_1, "INT with immediate ..."));
237 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
238 set_ia32_Immop_attr(new_op, imm_op);
241 set_ia32_am_support(new_op, ia32_am_Dest);
244 DB((mod, LEVEL_1, "INT binop ..."));
245 /* This is a normal operation */
246 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
249 set_ia32_am_support(new_op, ia32_am_Full);
253 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
255 set_ia32_res_mode(new_op, mode);
257 if (is_op_commutative(get_irn_op(env->irn))) {
258 set_ia32_commutative(new_op);
261 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
267 * Construct a shift/rotate binary operation, sets AM and immediate if required.
269 * @param env The transformation environment
270 * @param op1 The first operand
271 * @param op2 The second operand
272 * @param func The node constructor function
273 * @return The constructed ia32 node.
275 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
276 ir_node *new_op = NULL;
277 ir_mode *mode = env->mode;
278 dbg_info *dbg = env->dbg;
279 ir_graph *irg = env->irg;
280 ir_node *block = env->block;
281 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
282 ir_node *nomem = new_NoMem();
283 ir_node *expr_op, *imm_op;
285 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
287 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
289 /* Check if immediate optimization is on and */
290 /* if it's an operation with immediate. */
291 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
292 expr_op = get_expr_op(op1, op2);
294 assert((expr_op || imm_op) && "invalid operands");
297 /* We have two consts here: not yet supported */
301 /* Limit imm_op within range imm8 */
303 tv = get_ia32_Immop_tarval(imm_op);
306 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
313 /* integer operations */
315 /* This is shift/rot with const */
316 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
318 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
319 set_ia32_Immop_attr(new_op, imm_op);
322 /* This is a normal shift/rot */
323 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
324 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
328 set_ia32_am_support(new_op, ia32_am_Dest);
330 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
332 set_ia32_res_mode(new_op, mode);
333 set_ia32_emit_cl(new_op);
335 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
340 * Construct a standard unary operation, set AM and immediate if required.
342 * @param env The transformation environment
343 * @param op The operand
344 * @param func The node constructor function
345 * @return The constructed ia32 node.
347 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
348 ir_node *new_op = NULL;
349 ir_mode *mode = env->mode;
350 dbg_info *dbg = env->dbg;
351 ir_graph *irg = env->irg;
352 ir_node *block = env->block;
353 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
354 ir_node *nomem = new_NoMem();
355 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
357 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
359 if (mode_is_float(mode)) {
360 DB((mod, LEVEL_1, "FP unop ..."));
361 /* floating point operations don't support implicit store */
362 set_ia32_am_support(new_op, ia32_am_None);
365 DB((mod, LEVEL_1, "INT unop ..."));
366 set_ia32_am_support(new_op, ia32_am_Dest);
369 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
371 set_ia32_res_mode(new_op, mode);
373 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
379 * Creates an ia32 Add with immediate.
381 * @param env The transformation environment
382 * @param expr_op The expression operator
383 * @param const_op The constant
384 * @return the created ia32 Add node
386 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
387 ir_node *new_op = NULL;
388 tarval *tv = get_ia32_Immop_tarval(const_op);
389 dbg_info *dbg = env->dbg;
390 ir_graph *irg = env->irg;
391 ir_node *block = env->block;
392 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
393 ir_node *nomem = new_NoMem();
395 tarval_classification_t class_tv, class_negtv;
396 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
398 /* try to optimize to inc/dec */
399 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
400 /* optimize tarvals */
401 class_tv = classify_tarval(tv);
402 class_negtv = classify_tarval(tarval_neg(tv));
404 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
405 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
406 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
409 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
410 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
411 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
417 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
418 set_ia32_Immop_attr(new_op, const_op);
425 * Creates an ia32 Add.
427 * @param env The transformation environment
428 * @return the created ia32 Add node
430 static ir_node *gen_Add(ia32_transform_env_t *env) {
431 ir_node *new_op = NULL;
432 dbg_info *dbg = env->dbg;
433 ir_mode *mode = env->mode;
434 ir_graph *irg = env->irg;
435 ir_node *block = env->block;
436 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
437 ir_node *nomem = new_NoMem();
438 ir_node *expr_op, *imm_op;
439 ir_node *op1 = get_Add_left(env->irn);
440 ir_node *op2 = get_Add_right(env->irn);
442 /* Check if immediate optimization is on and */
443 /* if it's an operation with immediate. */
444 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
445 expr_op = get_expr_op(op1, op2);
447 assert((expr_op || imm_op) && "invalid operands");
449 if (mode_is_float(mode)) {
451 if (USE_SSE2(env->cg))
452 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
454 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
459 /* No expr_op means, that we have two const - one symconst and */
460 /* one tarval or another symconst - because this case is not */
461 /* covered by constant folding */
462 /* We need to check for: */
463 /* 1) symconst + const -> becomes a LEA */
464 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
465 /* linker doesn't support two symconsts */
467 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
468 /* this is the 2nd case */
469 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
470 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
471 set_ia32_am_flavour(new_op, ia32_am_OB);
474 /* this is the 1st case */
475 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
477 if (get_ia32_op_type(op1) == ia32_SymConst) {
478 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
479 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
482 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
483 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
485 set_ia32_am_flavour(new_op, ia32_am_O);
489 set_ia32_am_support(new_op, ia32_am_Source);
490 set_ia32_op_type(new_op, ia32_AddrModeS);
492 /* Lea doesn't need a Proj */
496 /* This is expr + const */
497 new_op = gen_imm_Add(env, expr_op, imm_op);
500 set_ia32_am_support(new_op, ia32_am_Dest);
503 /* This is a normal add */
504 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
507 set_ia32_am_support(new_op, ia32_am_Full);
508 set_ia32_commutative(new_op);
512 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
514 set_ia32_res_mode(new_op, mode);
516 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
522 * Creates an ia32 Mul.
524 * @param env The transformation environment
525 * @return the created ia32 Mul node
527 static ir_node *gen_Mul(ia32_transform_env_t *env) {
528 ir_node *op1 = get_Mul_left(env->irn);
529 ir_node *op2 = get_Mul_right(env->irn);
532 if (mode_is_float(env->mode)) {
534 if (USE_SSE2(env->cg))
535 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
537 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
540 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
549 * Creates an ia32 Mulh.
550 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
551 * this result while Mul returns the lower 32 bit.
553 * @param env The transformation environment
554 * @return the created ia32 Mulh node
556 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
557 ir_node *op1 = get_irn_n(env->irn, 0);
558 ir_node *op2 = get_irn_n(env->irn, 1);
559 ir_node *proj_EAX, *proj_EDX, *mulh;
562 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
563 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
564 mulh = get_Proj_pred(proj_EAX);
565 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
567 /* to be on the save side */
568 set_Proj_proj(proj_EAX, pn_EAX);
570 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
571 /* Mulh with const cannot have AM */
572 set_ia32_am_support(mulh, ia32_am_None);
575 /* Mulh cannot have AM for destination */
576 set_ia32_am_support(mulh, ia32_am_Source);
582 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
590 * Creates an ia32 And.
592 * @param env The transformation environment
593 * @return The created ia32 And node
595 static ir_node *gen_And(ia32_transform_env_t *env) {
596 ir_node *op1 = get_And_left(env->irn);
597 ir_node *op2 = get_And_right(env->irn);
599 assert (! mode_is_float(env->mode));
600 return gen_binop(env, op1, op2, new_rd_ia32_And);
606 * Creates an ia32 Or.
608 * @param env The transformation environment
609 * @return The created ia32 Or node
611 static ir_node *gen_Or(ia32_transform_env_t *env) {
612 ir_node *op1 = get_Or_left(env->irn);
613 ir_node *op2 = get_Or_right(env->irn);
615 assert (! mode_is_float(env->mode));
616 return gen_binop(env, op1, op2, new_rd_ia32_Or);
622 * Creates an ia32 Eor.
624 * @param env The transformation environment
625 * @return The created ia32 Eor node
627 static ir_node *gen_Eor(ia32_transform_env_t *env) {
628 ir_node *op1 = get_Eor_left(env->irn);
629 ir_node *op2 = get_Eor_right(env->irn);
631 assert(! mode_is_float(env->mode));
632 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
638 * Creates an ia32 Max.
640 * @param env The transformation environment
641 * @return the created ia32 Max node
643 static ir_node *gen_Max(ia32_transform_env_t *env) {
644 ir_node *op1 = get_irn_n(env->irn, 0);
645 ir_node *op2 = get_irn_n(env->irn, 1);
648 if (mode_is_float(env->mode)) {
650 if (USE_SSE2(env->cg))
651 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
657 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
658 set_ia32_am_support(new_op, ia32_am_None);
659 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
668 * Creates an ia32 Min.
670 * @param env The transformation environment
671 * @return the created ia32 Min node
673 static ir_node *gen_Min(ia32_transform_env_t *env) {
674 ir_node *op1 = get_irn_n(env->irn, 0);
675 ir_node *op2 = get_irn_n(env->irn, 1);
678 if (mode_is_float(env->mode)) {
680 if (USE_SSE2(env->cg))
681 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
687 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
688 set_ia32_am_support(new_op, ia32_am_None);
689 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
698 * Creates an ia32 Sub with immediate.
700 * @param env The transformation environment
701 * @param expr_op The first operator
702 * @param const_op The constant operator
703 * @return The created ia32 Sub node
705 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
706 ir_node *new_op = NULL;
707 tarval *tv = get_ia32_Immop_tarval(const_op);
708 dbg_info *dbg = env->dbg;
709 ir_graph *irg = env->irg;
710 ir_node *block = env->block;
711 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
712 ir_node *nomem = new_NoMem();
714 tarval_classification_t class_tv, class_negtv;
715 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
717 /* try to optimize to inc/dec */
718 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
719 /* optimize tarvals */
720 class_tv = classify_tarval(tv);
721 class_negtv = classify_tarval(tarval_neg(tv));
723 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
724 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
725 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
728 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
729 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
730 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
736 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
737 set_ia32_Immop_attr(new_op, const_op);
744 * Creates an ia32 Sub.
746 * @param env The transformation environment
747 * @return The created ia32 Sub node
749 static ir_node *gen_Sub(ia32_transform_env_t *env) {
750 ir_node *new_op = NULL;
751 dbg_info *dbg = env->dbg;
752 ir_mode *mode = env->mode;
753 ir_graph *irg = env->irg;
754 ir_node *block = env->block;
755 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
756 ir_node *nomem = new_NoMem();
757 ir_node *op1 = get_Sub_left(env->irn);
758 ir_node *op2 = get_Sub_right(env->irn);
759 ir_node *expr_op, *imm_op;
761 /* Check if immediate optimization is on and */
762 /* if it's an operation with immediate. */
763 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
764 expr_op = get_expr_op(op1, op2);
766 assert((expr_op || imm_op) && "invalid operands");
768 if (mode_is_float(mode)) {
770 if (USE_SSE2(env->cg))
771 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
773 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
778 /* No expr_op means, that we have two const - one symconst and */
779 /* one tarval or another symconst - because this case is not */
780 /* covered by constant folding */
781 /* We need to check for: */
782 /* 1) symconst + const -> becomes a LEA */
783 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
784 /* linker doesn't support two symconsts */
786 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
787 /* this is the 2nd case */
788 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
789 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
790 set_ia32_am_sc_sign(new_op);
791 set_ia32_am_flavour(new_op, ia32_am_OB);
794 /* this is the 1st case */
795 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
797 if (get_ia32_op_type(op1) == ia32_SymConst) {
798 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
799 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
802 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
803 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
804 set_ia32_am_sc_sign(new_op);
806 set_ia32_am_flavour(new_op, ia32_am_O);
810 set_ia32_am_support(new_op, ia32_am_Source);
811 set_ia32_op_type(new_op, ia32_AddrModeS);
813 /* Lea doesn't need a Proj */
817 /* This is expr - const */
818 new_op = gen_imm_Sub(env, expr_op, imm_op);
821 set_ia32_am_support(new_op, ia32_am_Dest);
824 /* This is a normal sub */
825 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
828 set_ia32_am_support(new_op, ia32_am_Full);
832 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
834 set_ia32_res_mode(new_op, mode);
836 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
842 * Generates an ia32 DivMod with additional infrastructure for the
843 * register allocator if needed.
845 * @param env The transformation environment
846 * @param dividend -no comment- :)
847 * @param divisor -no comment- :)
848 * @param dm_flav flavour_Div/Mod/DivMod
849 * @return The created ia32 DivMod node
851 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
853 ir_node *edx_node, *cltd;
855 dbg_info *dbg = env->dbg;
856 ir_graph *irg = env->irg;
857 ir_node *block = env->block;
858 ir_mode *mode = env->mode;
859 ir_node *irn = env->irn;
864 mem = get_Div_mem(irn);
865 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
868 mem = get_Mod_mem(irn);
869 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
872 mem = get_DivMod_mem(irn);
873 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
879 if (mode_is_signed(mode)) {
880 /* in signed mode, we need to sign extend the dividend */
881 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
882 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
883 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
886 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
887 set_ia32_Const_type(edx_node, ia32_Const);
888 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
891 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T, dm_flav);
893 set_ia32_n_res(res, 2);
895 /* Only one proj is used -> We must add a second proj and */
896 /* connect this one to a Keep node to eat up the second */
897 /* destroyed register. */
898 if (get_irn_n_edges(irn) == 1) {
899 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
900 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
902 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
903 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
906 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
912 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
914 set_ia32_res_mode(res, mode_Is);
921 * Wrapper for generate_DivMod. Sets flavour_Mod.
923 * @param env The transformation environment
925 static ir_node *gen_Mod(ia32_transform_env_t *env) {
926 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
930 * Wrapper for generate_DivMod. Sets flavour_Div.
932 * @param env The transformation environment
934 static ir_node *gen_Div(ia32_transform_env_t *env) {
935 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
939 * Wrapper for generate_DivMod. Sets flavour_DivMod.
941 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
942 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
948 * Creates an ia32 floating Div.
950 * @param env The transformation environment
951 * @return The created ia32 fDiv node
953 static ir_node *gen_Quot(ia32_transform_env_t *env) {
954 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
956 ir_node *nomem = new_rd_NoMem(env->irg);
957 ir_node *op1 = get_Quot_left(env->irn);
958 ir_node *op2 = get_Quot_right(env->irn);
961 if (USE_SSE2(env->cg)) {
962 if (is_ia32_fConst(op2)) {
963 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
964 set_ia32_am_support(new_op, ia32_am_None);
965 set_ia32_Immop_attr(new_op, op2);
968 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
969 set_ia32_am_support(new_op, ia32_am_Source);
973 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
974 set_ia32_am_support(new_op, ia32_am_Source);
976 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
977 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
985 * Creates an ia32 Shl.
987 * @param env The transformation environment
988 * @return The created ia32 Shl node
990 static ir_node *gen_Shl(ia32_transform_env_t *env) {
991 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
997 * Creates an ia32 Shr.
999 * @param env The transformation environment
1000 * @return The created ia32 Shr node
1002 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1003 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1009 * Creates an ia32 Shrs.
1011 * @param env The transformation environment
1012 * @return The created ia32 Shrs node
1014 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1015 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1021 * Creates an ia32 RotL.
1023 * @param env The transformation environment
1024 * @param op1 The first operator
1025 * @param op2 The second operator
1026 * @return The created ia32 RotL node
1028 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1029 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1035 * Creates an ia32 RotR.
1036 * NOTE: There is no RotR with immediate because this would always be a RotL
1037 * "imm-mode_size_bits" which can be pre-calculated.
1039 * @param env The transformation environment
1040 * @param op1 The first operator
1041 * @param op2 The second operator
1042 * @return The created ia32 RotR node
1044 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1045 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1051 * Creates an ia32 RotR or RotL (depending on the found pattern).
1053 * @param env The transformation environment
1054 * @return The created ia32 RotL or RotR node
1056 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1057 ir_node *rotate = NULL;
1058 ir_node *op1 = get_Rot_left(env->irn);
1059 ir_node *op2 = get_Rot_right(env->irn);
1061 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1062 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1063 that means we can create a RotR instead of an Add and a RotL */
1066 ir_node *pred = get_Proj_pred(op2);
1068 if (is_ia32_Add(pred)) {
1069 ir_node *pred_pred = get_irn_n(pred, 2);
1070 tarval *tv = get_ia32_Immop_tarval(pred);
1071 long bits = get_mode_size_bits(env->mode);
1073 if (is_Proj(pred_pred)) {
1074 pred_pred = get_Proj_pred(pred_pred);
1077 if (is_ia32_Minus(pred_pred) &&
1078 tarval_is_long(tv) &&
1079 get_tarval_long(tv) == bits)
1081 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1082 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1089 rotate = gen_RotL(env, op1, op2);
1098 * Transforms a Minus node.
1100 * @param env The transformation environment
1101 * @param op The Minus operand
1102 * @return The created ia32 Minus node
1104 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1109 if (mode_is_float(env->mode)) {
1111 if (USE_SSE2(env->cg)) {
1112 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1113 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1114 ir_node *nomem = new_rd_NoMem(env->irg);
1116 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1118 size = get_mode_size_bits(env->mode);
1119 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1121 set_ia32_sc(new_op, name);
1123 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1125 set_ia32_res_mode(new_op, env->mode);
1126 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1128 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1131 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1132 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1136 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1143 * Transforms a Minus node.
1145 * @param env The transformation environment
1146 * @return The created ia32 Minus node
1148 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1149 return gen_Minus_ex(env, get_Minus_op(env->irn));
1154 * Transforms a Not node.
1156 * @param env The transformation environment
1157 * @return The created ia32 Not node
1159 static ir_node *gen_Not(ia32_transform_env_t *env) {
1160 assert (! mode_is_float(env->mode));
1161 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1167 * Transforms an Abs node.
1169 * @param env The transformation environment
1170 * @return The created ia32 Abs node
1172 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1173 ir_node *res, *p_eax, *p_edx;
1174 dbg_info *dbg = env->dbg;
1175 ir_mode *mode = env->mode;
1176 ir_graph *irg = env->irg;
1177 ir_node *block = env->block;
1178 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1179 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1180 ir_node *nomem = new_NoMem();
1181 ir_node *op = get_Abs_op(env->irn);
1185 if (mode_is_float(mode)) {
1187 if (USE_SSE2(env->cg)) {
1188 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1190 size = get_mode_size_bits(mode);
1191 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1193 set_ia32_sc(res, name);
1195 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1197 set_ia32_res_mode(res, mode);
1198 set_ia32_immop_type(res, ia32_ImmSymConst);
1200 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1203 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1204 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1208 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1209 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1210 set_ia32_res_mode(res, mode);
1212 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1213 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1215 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1216 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1217 set_ia32_res_mode(res, mode);
1219 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1221 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1222 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1223 set_ia32_res_mode(res, mode);
1225 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1234 * Transforms a Load.
1236 * @param env The transformation environment
1237 * @return the created ia32 Load node
1239 static ir_node *gen_Load(ia32_transform_env_t *env) {
1240 ir_node *node = env->irn;
1241 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1242 ir_node *ptr = get_Load_ptr(node);
1243 ir_node *lptr = ptr;
1244 ir_mode *mode = get_Load_mode(node);
1247 ia32_am_flavour_t am_flav = ia32_B;
1249 /* address might be a constant (symconst or absolute address) */
1250 if (is_ia32_Const(ptr)) {
1255 if (mode_is_float(mode)) {
1257 if (USE_SSE2(env->cg))
1258 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1260 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1263 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1266 /* base is an constant address */
1268 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1269 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1272 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1278 set_ia32_am_support(new_op, ia32_am_Source);
1279 set_ia32_op_type(new_op, ia32_AddrModeS);
1280 set_ia32_am_flavour(new_op, am_flav);
1281 set_ia32_ls_mode(new_op, mode);
1283 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1291 * Transforms a Store.
1293 * @param env The transformation environment
1294 * @return the created ia32 Store node
1296 static ir_node *gen_Store(ia32_transform_env_t *env) {
1297 ir_node *node = env->irn;
1298 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1299 ir_node *val = get_Store_value(node);
1300 ir_node *ptr = get_Store_ptr(node);
1301 ir_node *sptr = ptr;
1302 ir_node *mem = get_Store_mem(node);
1303 ir_mode *mode = get_irn_mode(val);
1304 ir_node *sval = val;
1307 ia32_am_flavour_t am_flav = ia32_B;
1308 ia32_immop_type_t immop = ia32_ImmNone;
1310 if (! mode_is_float(mode)) {
1311 /* in case of storing a const (but not a symconst) -> make it an attribute */
1312 if (is_ia32_Cnst(val)) {
1313 switch (get_ia32_op_type(val)) {
1315 immop = ia32_ImmConst;
1318 immop = ia32_ImmSymConst;
1321 assert(0 && "unsupported Const type");
1327 /* address might be a constant (symconst or absolute address) */
1328 if (is_ia32_Const(ptr)) {
1333 if (mode_is_float(mode)) {
1335 if (USE_SSE2(env->cg))
1336 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1338 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1340 else if (get_mode_size_bits(mode) == 8) {
1341 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1344 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1347 /* stored const is an attribute (saves a register) */
1348 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1349 set_ia32_Immop_attr(new_op, val);
1352 /* base is an constant address */
1354 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1355 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1358 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1364 set_ia32_am_support(new_op, ia32_am_Dest);
1365 set_ia32_op_type(new_op, ia32_AddrModeD);
1366 set_ia32_am_flavour(new_op, am_flav);
1367 set_ia32_ls_mode(new_op, get_irn_mode(val));
1368 set_ia32_immop_type(new_op, immop);
1370 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1378 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1380 * @param env The transformation environment
1381 * @return The transformed node.
1383 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1384 dbg_info *dbg = env->dbg;
1385 ir_graph *irg = env->irg;
1386 ir_node *block = env->block;
1387 ir_node *node = env->irn;
1388 ir_node *sel = get_Cond_selector(node);
1389 ir_mode *sel_mode = get_irn_mode(sel);
1390 ir_node *res = NULL;
1391 ir_node *pred = NULL;
1392 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1393 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1395 if (is_Proj(sel) && sel_mode == mode_b) {
1396 ir_node *nomem = new_NoMem();
1398 pred = get_Proj_pred(sel);
1400 /* get both compare operators */
1401 cmp_a = get_Cmp_left(pred);
1402 cmp_b = get_Cmp_right(pred);
1404 /* check if we can use a CondJmp with immediate */
1405 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1406 expr = get_expr_op(cmp_a, cmp_b);
1409 pn_Cmp pnc = get_Proj_proj(sel);
1411 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1412 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1413 /* a Cmp A =/!= 0 */
1414 ir_node *op1 = expr;
1415 ir_node *op2 = expr;
1416 ir_node *and = skip_Proj(expr);
1417 const char *cnst = NULL;
1419 /* check, if expr is an only once used And operation */
1420 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1421 op1 = get_irn_n(and, 2);
1422 op2 = get_irn_n(and, 3);
1424 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1426 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1427 set_ia32_pncode(res, get_Proj_proj(sel));
1428 set_ia32_res_mode(res, get_irn_mode(op1));
1431 copy_ia32_Immop_attr(res, and);
1434 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1439 if (mode_is_float(get_irn_mode(expr))) {
1441 if (USE_SSE2(env->cg))
1442 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1448 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1450 set_ia32_Immop_attr(res, cnst);
1451 set_ia32_res_mode(res, get_irn_mode(expr));
1454 if (mode_is_float(get_irn_mode(cmp_a))) {
1456 if (USE_SSE2(env->cg))
1457 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1463 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1465 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1468 set_ia32_pncode(res, get_Proj_proj(sel));
1469 set_ia32_am_support(res, ia32_am_Source);
1472 /* determine the smallest switch case value */
1473 int switch_min = INT_MAX;
1474 const ir_edge_t *edge;
1477 foreach_out_edge(node, edge) {
1478 int pn = get_Proj_proj(get_edge_src_irn(edge));
1479 switch_min = pn < switch_min ? pn : switch_min;
1483 /* if smallest switch case is not 0 we need an additional sub */
1484 snprintf(buf, sizeof(buf), "%d", switch_min);
1485 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1486 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1487 sub_ia32_am_offs(res, buf);
1488 set_ia32_am_flavour(res, ia32_am_OB);
1489 set_ia32_am_support(res, ia32_am_Source);
1490 set_ia32_op_type(res, ia32_AddrModeS);
1493 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1494 set_ia32_pncode(res, get_Cond_defaultProj(node));
1495 set_ia32_res_mode(res, get_irn_mode(sel));
1498 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1505 * Transforms a CopyB node.
1507 * @param env The transformation environment
1508 * @return The transformed node.
1510 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1511 ir_node *res = NULL;
1512 dbg_info *dbg = env->dbg;
1513 ir_graph *irg = env->irg;
1514 ir_mode *mode = env->mode;
1515 ir_node *block = env->block;
1516 ir_node *node = env->irn;
1517 ir_node *src = get_CopyB_src(node);
1518 ir_node *dst = get_CopyB_dst(node);
1519 ir_node *mem = get_CopyB_mem(node);
1520 int size = get_type_size_bytes(get_CopyB_type(node));
1523 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1524 /* then we need the size explicitly in ECX. */
1525 if (size >= 16 * 4) {
1526 rem = size & 0x3; /* size % 4 */
1529 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1530 set_ia32_op_type(res, ia32_Const);
1531 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1533 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1534 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1537 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1538 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1539 set_ia32_immop_type(res, ia32_ImmConst);
1542 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1550 * Transforms a Mux node into CMov.
1552 * @param env The transformation environment
1553 * @return The transformed node.
1555 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1556 ir_node *node = env->irn;
1557 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1558 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1560 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1567 * Following conversion rules apply:
1571 * 1) n bit -> m bit n > m (downscale)
1572 * a) target is signed: movsx
1573 * b) target is unsigned: and with lower bits sets
1574 * 2) n bit -> m bit n == m (sign change)
1576 * 3) n bit -> m bit n < m (upscale)
1577 * a) source is signed: movsx
1578 * b) source is unsigned: and with lower bits sets
1582 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1586 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1587 * if target mode < 32bit: additional INT -> INT conversion (see above)
1591 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1592 * x87 is mode_E internally, conversions happen only at load and store
1593 * in non-strict semantic
1597 * Create a conversion from x87 state register to general purpose.
1599 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1600 ia32_code_gen_t *cg = env->cg;
1601 entity *ent = cg->fp_to_gp;
1602 ir_graph *irg = env->irg;
1603 ir_node *block = env->block;
1604 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1605 ir_node *op = get_Conv_op(env->irn);
1606 ir_node *fist, *mem, *load;
1609 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1610 ent = cg->fp_to_gp =
1611 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1615 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg), mode_T);
1617 set_ia32_frame_ent(fist, ent);
1618 set_ia32_use_frame(fist);
1619 set_ia32_am_support(fist, ia32_am_Dest);
1620 set_ia32_op_type(fist, ia32_AddrModeD);
1621 set_ia32_am_flavour(fist, ia32_B);
1622 set_ia32_ls_mode(fist, mode_E);
1624 mem = new_r_Proj(irg, block, fist, mode_M, 0);
1627 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
1629 set_ia32_frame_ent(load, ent);
1630 set_ia32_use_frame(load);
1631 set_ia32_am_support(load, ia32_am_Source);
1632 set_ia32_op_type(load, ia32_AddrModeS);
1633 set_ia32_am_flavour(load, ia32_B);
1634 set_ia32_ls_mode(load, tgt_mode);
1636 return new_r_Proj(irg, block, load, tgt_mode, 0);
1640 * Create a conversion from x87 state register to general purpose.
1642 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1643 ia32_code_gen_t *cg = env->cg;
1644 entity *ent = cg->gp_to_fp;
1645 ir_graph *irg = env->irg;
1646 ir_node *block = env->block;
1647 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1648 ir_node *nomem = get_irg_no_mem(irg);
1649 ir_node *op = get_Conv_op(env->irn);
1650 ir_node *fild, *store, *mem;
1654 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1655 ent = cg->gp_to_fp =
1656 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1659 /* first convert to 32 bit */
1660 src_bits = get_mode_size_bits(src_mode);
1661 if (src_bits == 8) {
1662 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1663 op = new_r_Proj(irg, block, op, mode_Is, 0);
1665 else if (src_bits < 32) {
1666 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1667 op = new_r_Proj(irg, block, op, mode_Is, 0);
1671 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem, mode_T);
1673 set_ia32_frame_ent(store, ent);
1674 set_ia32_use_frame(store);
1676 set_ia32_am_support(store, ia32_am_Dest);
1677 set_ia32_op_type(store, ia32_AddrModeD);
1678 set_ia32_am_flavour(store, ia32_B);
1679 set_ia32_ls_mode(store, mode_Is);
1681 mem = new_r_Proj(irg, block, store, mode_M, 0);
1684 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
1686 set_ia32_frame_ent(fild, ent);
1687 set_ia32_use_frame(fild);
1688 set_ia32_am_support(fild, ia32_am_Source);
1689 set_ia32_op_type(fild, ia32_AddrModeS);
1690 set_ia32_am_flavour(fild, ia32_B);
1691 set_ia32_ls_mode(fild, mode_E);
1693 return new_r_Proj(irg, block, fild, mode_E, 0);
1697 * Transforms a Conv node.
1699 * @param env The transformation environment
1700 * @return The created ia32 Conv node
1702 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1703 dbg_info *dbg = env->dbg;
1704 ir_graph *irg = env->irg;
1705 ir_node *op = get_Conv_op(env->irn);
1706 ir_mode *src_mode = get_irn_mode(op);
1707 ir_mode *tgt_mode = env->mode;
1708 int src_bits = get_mode_size_bits(src_mode);
1709 int tgt_bits = get_mode_size_bits(tgt_mode);
1710 ir_node *block = env->block;
1711 ir_node *new_op = NULL;
1712 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1713 ir_node *nomem = new_rd_NoMem(irg);
1715 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1717 if (src_mode == tgt_mode) {
1718 /* this can happen when changing mode_P to mode_Is */
1719 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1720 edges_reroute(env->irn, op, irg);
1722 else if (mode_is_float(src_mode)) {
1723 /* we convert from float ... */
1724 if (mode_is_float(tgt_mode)) {
1726 if (USE_SSE2(env->cg)) {
1727 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1728 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1731 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1732 edges_reroute(env->irn, op, irg);
1737 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1738 if (USE_SSE2(env->cg))
1739 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1741 return gen_x87_fp_to_gp(env, tgt_mode);
1743 /* if target mode is not int: add an additional downscale convert */
1744 if (tgt_bits < 32) {
1745 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1746 set_ia32_am_support(new_op, ia32_am_Source);
1747 set_ia32_tgt_mode(new_op, tgt_mode);
1748 set_ia32_src_mode(new_op, src_mode);
1750 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1752 if (tgt_bits == 8 || src_bits == 8) {
1753 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1756 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1762 /* we convert from int ... */
1763 if (mode_is_float(tgt_mode)) {
1766 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1767 if (USE_SSE2(env->cg))
1768 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1770 return gen_x87_gp_to_fp(env, src_mode);
1774 if (get_mode_size_bits(src_mode) == tgt_bits) {
1775 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1776 edges_reroute(env->irn, op, irg);
1779 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1780 if (tgt_bits == 8 || src_bits == 8) {
1781 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1784 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1792 set_ia32_tgt_mode(new_op, tgt_mode);
1793 set_ia32_src_mode(new_op, src_mode);
1795 set_ia32_am_support(new_op, ia32_am_Source);
1797 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1805 /********************************************
1808 * | |__ ___ _ __ ___ __| | ___ ___
1809 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1810 * | |_) | __/ | | | (_) | (_| | __/\__ \
1811 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1813 ********************************************/
1815 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
1816 ir_node *new_op = NULL;
1817 ir_node *node = env->irn;
1818 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1819 ir_node *mem = new_rd_NoMem(env->irg);
1820 ir_node *ptr = get_irn_n(node, 0);
1821 entity *ent = be_get_frame_entity(node);
1822 ir_mode *mode = env->mode;
1824 // /* If the StackParam has only one user -> */
1825 // /* put it in the Block where the user resides */
1826 // if (get_irn_n_edges(node) == 1) {
1827 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1830 if (mode_is_float(mode)) {
1832 if (USE_SSE2(env->cg))
1833 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1835 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1838 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1841 set_ia32_frame_ent(new_op, ent);
1842 set_ia32_use_frame(new_op);
1844 set_ia32_am_support(new_op, ia32_am_Source);
1845 set_ia32_op_type(new_op, ia32_AddrModeS);
1846 set_ia32_am_flavour(new_op, ia32_B);
1847 set_ia32_ls_mode(new_op, mode);
1849 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1851 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1855 * Transforms a FrameAddr into an ia32 Add.
1857 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
1858 ir_node *new_op = NULL;
1859 ir_node *node = env->irn;
1860 ir_node *op = get_irn_n(node, 0);
1861 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1862 ir_node *nomem = new_rd_NoMem(env->irg);
1864 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1865 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1866 set_ia32_am_support(new_op, ia32_am_Full);
1867 set_ia32_use_frame(new_op);
1868 set_ia32_immop_type(new_op, ia32_ImmConst);
1869 set_ia32_commutative(new_op);
1871 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1873 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1877 * Transforms a FrameLoad into an ia32 Load.
1879 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
1880 ir_node *new_op = NULL;
1881 ir_node *node = env->irn;
1882 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1883 ir_node *mem = get_irn_n(node, 0);
1884 ir_node *ptr = get_irn_n(node, 1);
1885 entity *ent = be_get_frame_entity(node);
1886 ir_mode *mode = get_type_mode(get_entity_type(ent));
1888 if (mode_is_float(mode)) {
1890 if (USE_SSE2(env->cg))
1891 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1893 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1896 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1898 set_ia32_frame_ent(new_op, ent);
1899 set_ia32_use_frame(new_op);
1901 set_ia32_am_support(new_op, ia32_am_Source);
1902 set_ia32_op_type(new_op, ia32_AddrModeS);
1903 set_ia32_am_flavour(new_op, ia32_B);
1904 set_ia32_ls_mode(new_op, mode);
1906 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1913 * Transforms a FrameStore into an ia32 Store.
1915 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
1916 ir_node *new_op = NULL;
1917 ir_node *node = env->irn;
1918 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1919 ir_node *mem = get_irn_n(node, 0);
1920 ir_node *ptr = get_irn_n(node, 1);
1921 ir_node *val = get_irn_n(node, 2);
1922 entity *ent = be_get_frame_entity(node);
1923 ir_mode *mode = get_irn_mode(val);
1925 if (mode_is_float(mode)) {
1927 if (USE_SSE2(env->cg))
1928 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1930 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1932 else if (get_mode_size_bits(mode) == 8) {
1933 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1936 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1939 set_ia32_frame_ent(new_op, ent);
1940 set_ia32_use_frame(new_op);
1942 set_ia32_am_support(new_op, ia32_am_Dest);
1943 set_ia32_op_type(new_op, ia32_AddrModeD);
1944 set_ia32_am_flavour(new_op, ia32_B);
1945 set_ia32_ls_mode(new_op, mode);
1947 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1954 /*********************************************************
1957 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1958 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1959 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1960 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1962 *********************************************************/
1965 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1966 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1968 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1969 ia32_transform_env_t tenv;
1970 ir_node *in1, *in2, *noreg, *nomem, *res;
1971 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1973 /* Return if AM node or not a Sub or fSub */
1974 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1977 noreg = ia32_new_NoReg_gp(cg);
1978 nomem = new_rd_NoMem(cg->irg);
1979 in1 = get_irn_n(irn, 2);
1980 in2 = get_irn_n(irn, 3);
1981 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1982 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1983 out_reg = get_ia32_out_reg(irn, 0);
1985 tenv.block = get_nodes_block(irn);
1986 tenv.dbg = get_irn_dbg_info(irn);
1989 tenv.mode = get_ia32_res_mode(irn);
1991 DEBUG_ONLY(tenv.mod = cg->mod;)
1993 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1994 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1995 /* generate the neg src2 */
1996 res = gen_Minus_ex(&tenv, in2);
1997 arch_set_irn_register(cg->arch_env, res, in2_reg);
1999 /* add to schedule */
2000 sched_add_before(irn, res);
2002 /* generate the add */
2003 if (mode_is_float(tenv.mode)) {
2004 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
2005 set_ia32_am_support(res, ia32_am_Source);
2008 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
2009 set_ia32_am_support(res, ia32_am_Full);
2010 set_ia32_commutative(res);
2013 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2015 slots = get_ia32_slots(res);
2018 /* add to schedule */
2019 sched_add_before(irn, res);
2021 /* remove the old sub */
2024 /* exchange the add and the sub */
2030 * Transforms a LEA into an Add if possible
2031 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2033 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2034 ia32_am_flavour_t am_flav;
2036 ir_node *res = NULL;
2037 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2039 ia32_transform_env_t tenv;
2040 const arch_register_t *out_reg, *base_reg, *index_reg;
2043 if (! is_ia32_Lea(irn))
2046 am_flav = get_ia32_am_flavour(irn);
2048 /* only some LEAs can be transformed to an Add */
2049 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2052 noreg = ia32_new_NoReg_gp(cg);
2053 nomem = new_rd_NoMem(cg->irg);
2056 base = get_irn_n(irn, 0);
2057 index = get_irn_n(irn,1);
2059 offs = get_ia32_am_offs(irn);
2061 /* offset has a explicit sign -> we need to skip + */
2062 if (offs && offs[0] == '+')
2065 out_reg = arch_get_irn_register(cg->arch_env, irn);
2066 base_reg = arch_get_irn_register(cg->arch_env, base);
2067 index_reg = arch_get_irn_register(cg->arch_env, index);
2069 tenv.block = get_nodes_block(irn);
2070 tenv.dbg = get_irn_dbg_info(irn);
2073 DEBUG_ONLY(tenv.mod = cg->mod;)
2074 tenv.mode = get_irn_mode(irn);
2077 switch(get_ia32_am_flavour(irn)) {
2079 /* out register must be same as base register */
2080 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2086 /* out register must be same as base register */
2087 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2094 /* out register must be same as index register */
2095 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2102 /* out register must be same as one in register */
2103 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2107 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2112 /* in registers a different from out -> no Add possible */
2119 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
2120 arch_set_irn_register(cg->arch_env, res, out_reg);
2121 set_ia32_op_type(res, ia32_Normal);
2122 set_ia32_commutative(res);
2125 set_ia32_cnst(res, offs);
2126 set_ia32_immop_type(res, ia32_ImmConst);
2129 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2131 /* add Add to schedule */
2132 sched_add_before(irn, res);
2134 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2136 /* add result Proj to schedule */
2137 sched_add_before(irn, res);
2139 /* remove the old LEA */
2142 /* exchange the Add and the LEA */
2147 * the BAD transformer.
2149 static ir_node *bad_transform(ia32_transform_env_t *env) {
2150 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2156 * Enters all transform functions into the generic pointer
2158 void ia32_register_transformers(void) {
2159 ir_op *op_Max, *op_Min, *op_Mulh;
2161 /* first clear the generic function pointer for all ops */
2162 clear_irp_opcodes_generic_func();
2164 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2165 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2212 /* constant transformation happens earlier */
2236 op_Max = get_op_Max();
2239 op_Min = get_op_Min();
2242 op_Mulh = get_op_Mulh();
2251 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2254 * Transforms the given firm node (and maybe some other related nodes)
2255 * into one or more assembler nodes.
2257 * @param node the firm node
2258 * @param env the debug module
2260 void ia32_transform_node(ir_node *node, void *env) {
2261 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2262 ir_op *op = get_irn_op(node);
2263 ir_node *asm_node = NULL;
2268 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2269 if (op->ops.generic) {
2270 ia32_transform_env_t tenv;
2271 transform_func *transform = (transform_func *)op->ops.generic;
2273 tenv.block = get_nodes_block(node);
2274 tenv.dbg = get_irn_dbg_info(node);
2275 tenv.irg = current_ir_graph;
2277 tenv.mode = get_irn_mode(node);
2279 DEBUG_ONLY(tenv.mod = cg->mod;)
2281 asm_node = (*transform)(&tenv);
2284 /* exchange nodes if a new one was generated */
2286 exchange(node, asm_node);
2287 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2290 DB((cg->mod, LEVEL_1, "ignored\n"));