2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 typedef struct ia32_transform_env_t {
69 ir_graph *irg; /**< The irg, the node should be created in */
70 ia32_code_gen_t *cg; /**< The code generator */
71 int visited; /**< visited count that indicates whether a
72 node is already transformed */
73 pdeq *worklist; /**< worklist of nodes that still need to be
75 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
76 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
77 } ia32_transform_env_t;
79 extern ir_op *get_op_Mulh(void);
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
82 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
83 ir_node *op2, ir_node *mem);
85 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
86 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
89 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
91 /****************************************************************************************************
93 * | | | | / _| | | (_)
94 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
95 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
96 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
97 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
99 ****************************************************************************************************/
101 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
102 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
103 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
106 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
108 set_irn_link(old_node, new_node);
111 static INLINE ir_node *get_new_node(ir_node *old_node)
113 assert(irn_visited(old_node));
114 return (ir_node*) get_irn_link(old_node);
118 * Returns 1 if irn is a Const representing 0, 0 otherwise
120 static INLINE int is_ia32_Const_0(ir_node *irn) {
121 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
122 && tarval_is_null(get_ia32_Immop_tarval(irn));
126 * Returns 1 if irn is a Const representing 1, 0 otherwise
128 static INLINE int is_ia32_Const_1(ir_node *irn) {
129 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
130 && tarval_is_one(get_ia32_Immop_tarval(irn));
134 * Collects all Projs of a node into the node array. Index is the projnum.
135 * BEWARE: The caller has to assure the appropriate array size!
137 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
138 const ir_edge_t *edge;
139 assert(get_irn_mode(irn) == mode_T && "need mode_T");
141 memset(projs, 0, size * sizeof(projs[0]));
143 foreach_out_edge(irn, edge) {
144 ir_node *proj = get_edge_src_irn(edge);
145 int proj_proj = get_Proj_proj(proj);
146 assert(proj_proj < size);
147 projs[proj_proj] = proj;
152 * Renumbers the proj having pn_old in the array tp pn_new
153 * and removes the proj from the array.
155 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
156 fprintf(stderr, "Warning: renumber_Proj used!\n");
158 set_Proj_proj(projs[pn_old], pn_new);
159 projs[pn_old] = NULL;
164 * creates a unique ident by adding a number to a tag
166 * @param tag the tag string, must contain a %d if a number
169 static ident *unique_id(const char *tag)
171 static unsigned id = 0;
174 snprintf(str, sizeof(str), tag, ++id);
175 return new_id_from_str(str);
179 * Get a primitive type for a mode.
181 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
183 pmap_entry *e = pmap_find(types, mode);
188 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
189 res = new_type_primitive(new_id_from_str(buf), mode);
190 pmap_insert(types, mode, res);
198 * Get an entity that is initialized with a tarval
200 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
202 tarval *tv = get_Const_tarval(cnst);
203 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
208 ir_mode *mode = get_irn_mode(cnst);
209 ir_type *tp = get_Const_type(cnst);
210 if (tp == firm_unknown_type)
211 tp = get_prim_type(cg->isa->types, mode);
213 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
215 set_entity_ld_ident(res, get_entity_ident(res));
216 set_entity_visibility(res, visibility_local);
217 set_entity_variability(res, variability_constant);
218 set_entity_allocation(res, allocation_static);
220 /* we create a new entity here: It's initialization must resist on the
222 rem = current_ir_graph;
223 current_ir_graph = get_const_code_irg();
224 set_atomic_ent_value(res, new_Const_type(tv, tp));
225 current_ir_graph = rem;
227 pmap_insert(cg->isa->tv_ent, tv, res);
235 * Transforms a Const.
237 * @param mod the debug module
238 * @param block the block the new node should belong to
239 * @param node the ir Const node
240 * @param mode mode of the Const
241 * @return the created ia32 Const node
243 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
244 ir_graph *irg = env->irg;
245 dbg_info *dbg = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
247 ir_node *block = transform_node(env, get_nodes_block(node));
249 if (mode_is_float(mode)) {
252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
253 ir_node *nomem = new_NoMem();
257 if (! USE_SSE2(env->cg)) {
258 cnst_classify_t clss = classify_Const(node);
260 if (clss == CNST_NULL) {
261 load = new_rd_ia32_vfldz(dbg, irg, block);
263 } else if (clss == CNST_ONE) {
264 load = new_rd_ia32_vfld1(dbg, irg, block);
267 floatent = get_entity_for_tv(env->cg, node);
269 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
270 set_ia32_am_support(load, ia32_am_Source);
271 set_ia32_op_type(load, ia32_AddrModeS);
272 set_ia32_am_flavour(load, ia32_am_N);
273 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
274 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
277 floatent = get_entity_for_tv(env->cg, node);
279 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
280 set_ia32_am_support(load, ia32_am_Source);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_flavour(load, ia32_am_N);
283 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
284 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
287 set_ia32_ls_mode(load, mode);
288 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
290 /* Const Nodes before the initial IncSP are a bad idea, because
291 * they could be spilled and we have no SP ready at that point yet
293 if (get_irg_start_block(irg) == block) {
294 add_irn_dep(load, get_irg_frame(irg));
297 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(cnst, get_irg_frame(irg));
307 set_ia32_Const_attr(cnst, node);
308 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
313 return new_r_Bad(irg);
317 * Transforms a SymConst.
319 * @param mod the debug module
320 * @param block the block the new node should belong to
321 * @param node the ir SymConst node
322 * @param mode mode of the SymConst
323 * @return the created ia32 Const node
325 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
326 ir_graph *irg = env->irg;
327 dbg_info *dbg = get_irn_dbg_info(node);
328 ir_mode *mode = get_irn_mode(node);
329 ir_node *block = transform_node(env, get_nodes_block(node));
332 if (mode_is_float(mode)) {
334 if (USE_SSE2(env->cg))
335 cnst = new_rd_ia32_xConst(dbg, irg, block);
337 cnst = new_rd_ia32_vfConst(dbg, irg, block);
338 set_ia32_ls_mode(cnst, mode);
340 cnst = new_rd_ia32_Const(dbg, irg, block);
343 /* Const Nodes before the initial IncSP are a bad idea, because
344 * they could be spilled and we have no SP ready at that point yet
346 if (get_irg_start_block(irg) == block) {
347 add_irn_dep(cnst, get_irg_frame(irg));
350 set_ia32_Const_attr(cnst, node);
351 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
357 * SSE convert of an integer node into a floating point node.
359 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
360 ir_graph *irg, ir_node *block,
361 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
364 ir_node *nomem = new_rd_NoMem(irg);
365 ir_node *old_pred = get_Cmp_left(old_node);
366 ir_mode *in_mode = get_irn_mode(old_pred);
367 int in_bits = get_mode_size_bits(in_mode);
369 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
370 set_ia32_ls_mode(conv, tgt_mode);
372 set_ia32_am_support(conv, ia32_am_Source);
374 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
380 * SSE convert of an float node into a double node.
382 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
390 set_ia32_am_support(conv, ia32_am_Source);
391 set_ia32_ls_mode(conv, mode_E);
392 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
398 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
399 static const struct {
401 const char *ent_name;
402 const char *cnst_str;
403 } names [ia32_known_const_max] = {
404 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
405 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
406 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
407 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
409 static ir_entity *ent_cache[ia32_known_const_max];
411 const char *tp_name, *ent_name, *cnst_str;
419 ent_name = names[kct].ent_name;
420 if (! ent_cache[kct]) {
421 tp_name = names[kct].tp_name;
422 cnst_str = names[kct].cnst_str;
424 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
429 set_entity_ld_ident(ent, get_entity_ident(ent));
430 set_entity_visibility(ent, visibility_local);
431 set_entity_variability(ent, variability_constant);
432 set_entity_allocation(ent, allocation_static);
434 /* we create a new entity here: It's initialization must resist on the
436 rem = current_ir_graph;
437 current_ir_graph = get_const_code_irg();
438 cnst = new_Const(mode, tv);
439 current_ir_graph = rem;
441 set_atomic_ent_value(ent, cnst);
443 /* cache the entry */
444 ent_cache[kct] = ent;
447 return get_entity_ident(ent_cache[kct]);
452 * Prints the old node name on cg obst and returns a pointer to it.
454 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
455 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
457 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
458 obstack_1grow(isa->name_obst, 0);
459 return obstack_finish(isa->name_obst);
463 /* determine if one operator is an Imm */
464 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
466 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
467 else return is_ia32_Cnst(op2) ? op2 : NULL;
470 /* determine if one operator is not an Imm */
471 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
472 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
475 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
479 if(! (env->cg->opt & IA32_OPT_IMMOPS))
482 left = get_irn_n(node, in1);
483 right = get_irn_n(node, in2);
484 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
485 /* we can only set right operand to immediate */
486 if(!is_ia32_commutative(node))
488 /* exchange left/right */
489 set_irn_n(node, in1, right);
490 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
491 copy_ia32_Immop_attr(node, left);
492 } else if(is_ia32_Cnst(right)) {
493 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
494 copy_ia32_Immop_attr(node, right);
499 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
503 * Construct a standard binary operation, set AM and immediate if required.
505 * @param env The transformation environment
506 * @param op1 The first operand
507 * @param op2 The second operand
508 * @param func The node constructor function
509 * @return The constructed ia32 node.
511 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
512 ir_node *op1, ir_node *op2,
513 construct_binop_func *func) {
514 ir_node *new_node = NULL;
515 ir_graph *irg = env->irg;
516 dbg_info *dbg = get_irn_dbg_info(node);
517 ir_node *block = transform_node(env, get_nodes_block(node));
518 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
519 ir_node *nomem = new_NoMem();
520 ir_node *new_op1 = transform_node(env, op1);
521 ir_node *new_op2 = transform_node(env, op2);
523 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
524 if(func == new_rd_ia32_IMul) {
525 set_ia32_am_support(new_node, ia32_am_Source);
527 set_ia32_am_support(new_node, ia32_am_Full);
530 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
531 if (is_op_commutative(get_irn_op(node))) {
532 set_ia32_commutative(new_node);
534 fold_immediate(env, new_node, 2, 3);
540 * Construct a standard binary operation, set AM and immediate if required.
542 * @param env The transformation environment
543 * @param op1 The first operand
544 * @param op2 The second operand
545 * @param func The node constructor function
546 * @return The constructed ia32 node.
548 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
549 ir_node *op1, ir_node *op2,
550 construct_binop_func *func)
552 ir_node *new_node = NULL;
553 dbg_info *dbg = get_irn_dbg_info(node);
554 ir_graph *irg = env->irg;
555 ir_mode *mode = get_irn_mode(node);
556 ir_node *block = transform_node(env, get_nodes_block(node));
557 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
558 ir_node *nomem = new_NoMem();
559 ir_node *new_op1 = transform_node(env, op1);
560 ir_node *new_op2 = transform_node(env, op2);
562 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
563 set_ia32_am_support(new_node, ia32_am_Source);
564 if (is_op_commutative(get_irn_op(node))) {
565 set_ia32_commutative(new_node);
567 if (USE_SSE2(env->cg)) {
568 set_ia32_ls_mode(new_node, mode);
571 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
578 * Construct a shift/rotate binary operation, sets AM and immediate if required.
580 * @param env The transformation environment
581 * @param op1 The first operand
582 * @param op2 The second operand
583 * @param func The node constructor function
584 * @return The constructed ia32 node.
586 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
587 ir_node *op1, ir_node *op2,
588 construct_binop_func *func) {
589 ir_node *new_op = NULL;
590 ir_mode *mode = get_irn_mode(node);
591 dbg_info *dbg = get_irn_dbg_info(node);
592 ir_graph *irg = env->irg;
593 ir_node *block = transform_node(env, get_nodes_block(node));
594 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
595 ir_node *nomem = new_NoMem();
598 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
599 ir_node *new_op1 = transform_node(env, op1);
600 ir_node *new_op2 = transform_node(env, op2);
603 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
605 /* Check if immediate optimization is on and */
606 /* if it's an operation with immediate. */
607 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
608 expr_op = get_expr_op(new_op1, new_op2);
610 assert((expr_op || imm_op) && "invalid operands");
613 /* We have two consts here: not yet supported */
617 /* Limit imm_op within range imm8 */
619 tv = get_ia32_Immop_tarval(imm_op);
622 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
623 set_ia32_Immop_tarval(imm_op, tv);
630 /* integer operations */
632 /* This is shift/rot with const */
633 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
635 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
636 copy_ia32_Immop_attr(new_op, imm_op);
638 /* This is a normal shift/rot */
639 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
640 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
644 set_ia32_am_support(new_op, ia32_am_Dest);
646 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
648 set_ia32_emit_cl(new_op);
655 * Construct a standard unary operation, set AM and immediate if required.
657 * @param env The transformation environment
658 * @param op The operand
659 * @param func The node constructor function
660 * @return The constructed ia32 node.
662 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
663 construct_unop_func *func) {
664 ir_node *new_node = NULL;
665 ir_graph *irg = env->irg;
666 dbg_info *dbg = get_irn_dbg_info(node);
667 ir_node *block = transform_node(env, get_nodes_block(node));
668 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
669 ir_node *nomem = new_NoMem();
670 ir_node *new_op = transform_node(env, op);
671 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
673 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
674 DB((mod, LEVEL_1, "INT unop ..."));
675 set_ia32_am_support(new_node, ia32_am_Dest);
677 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
684 * Creates an ia32 Add.
686 * @param env The transformation environment
687 * @return the created ia32 Add node
689 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
690 ir_node *new_op = NULL;
691 ir_graph *irg = env->irg;
692 dbg_info *dbg = get_irn_dbg_info(node);
693 ir_mode *mode = get_irn_mode(node);
694 ir_node *block = transform_node(env, get_nodes_block(node));
695 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
696 ir_node *nomem = new_NoMem();
697 ir_node *expr_op, *imm_op;
698 ir_node *op1 = get_Add_left(node);
699 ir_node *op2 = get_Add_right(node);
700 ir_node *new_op1 = transform_node(env, op1);
701 ir_node *new_op2 = transform_node(env, op2);
703 /* Check if immediate optimization is on and */
704 /* if it's an operation with immediate. */
705 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
706 expr_op = get_expr_op(new_op1, new_op2);
708 assert((expr_op || imm_op) && "invalid operands");
710 if (mode_is_float(mode)) {
712 if (USE_SSE2(env->cg))
713 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
715 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
720 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
721 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
723 /* No expr_op means, that we have two const - one symconst and */
724 /* one tarval or another symconst - because this case is not */
725 /* covered by constant folding */
726 /* We need to check for: */
727 /* 1) symconst + const -> becomes a LEA */
728 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
729 /* linker doesn't support two symconsts */
731 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
732 /* this is the 2nd case */
733 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
734 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
735 set_ia32_am_flavour(new_op, ia32_am_OB);
736 set_ia32_am_support(new_op, ia32_am_Source);
737 set_ia32_op_type(new_op, ia32_AddrModeS);
739 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
740 } else if (tp1 == ia32_ImmSymConst) {
741 tarval *tv = get_ia32_Immop_tarval(new_op2);
742 long offs = get_tarval_long(tv);
744 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
745 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
747 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
748 add_ia32_am_offs_int(new_op, offs);
749 set_ia32_am_flavour(new_op, ia32_am_O);
750 set_ia32_am_support(new_op, ia32_am_Source);
751 set_ia32_op_type(new_op, ia32_AddrModeS);
752 } else if (tp2 == ia32_ImmSymConst) {
753 tarval *tv = get_ia32_Immop_tarval(new_op1);
754 long offs = get_tarval_long(tv);
756 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
757 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
759 add_ia32_am_offs_int(new_op, offs);
760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
761 set_ia32_am_flavour(new_op, ia32_am_O);
762 set_ia32_am_support(new_op, ia32_am_Source);
763 set_ia32_op_type(new_op, ia32_AddrModeS);
765 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
766 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
767 tarval *restv = tarval_add(tv1, tv2);
769 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
771 new_op = new_rd_ia32_Const(dbg, irg, block);
772 set_ia32_Const_tarval(new_op, restv);
773 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
779 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
780 tarval_classification_t class_tv, class_negtv;
781 tarval *tv = get_ia32_Immop_tarval(imm_op);
783 /* optimize tarvals */
784 class_tv = classify_tarval(tv);
785 class_negtv = classify_tarval(tarval_neg(tv));
787 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
788 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
789 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
790 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
792 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
793 DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
794 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
801 /* This is a normal add */
802 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
805 set_ia32_am_support(new_op, ia32_am_Full);
806 set_ia32_commutative(new_op);
808 fold_immediate(env, new_op, 2, 3);
810 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
816 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
817 ir_graph *irg = env->irg;
818 dbg_info *dbg = get_irn_dbg_info(node);
819 ir_node *block = transform_node(env, get_nodes_block(node));
820 ir_node *op1 = get_Mul_left(node);
821 ir_node *op2 = get_Mul_right(node);
822 ir_node *new_op1 = transform_node(env, op1);
823 ir_node *new_op2 = transform_node(env, op2);
824 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
825 ir_node *proj_EAX, *proj_EDX, *res;
828 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
829 set_ia32_commutative(res);
830 set_ia32_am_support(res, ia32_am_Source);
832 /* imediates are not supported, so no fold_immediate */
833 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
834 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
838 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
846 * Creates an ia32 Mul.
848 * @param env The transformation environment
849 * @return the created ia32 Mul node
851 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
852 ir_node *op1 = get_Mul_left(node);
853 ir_node *op2 = get_Mul_right(node);
854 ir_mode *mode = get_irn_mode(node);
856 if (mode_is_float(mode)) {
858 if (USE_SSE2(env->cg))
859 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
861 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
864 // for the lower 32bit of the result it doesn't matter whether we use
865 // signed or unsigned multiplication so we use IMul as it has fewer
867 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
871 * Creates an ia32 Mulh.
872 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
873 * this result while Mul returns the lower 32 bit.
875 * @param env The transformation environment
876 * @return the created ia32 Mulh node
878 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
879 ir_graph *irg = env->irg;
880 dbg_info *dbg = get_irn_dbg_info(node);
881 ir_node *block = transform_node(env, get_nodes_block(node));
882 ir_node *op1 = get_irn_n(node, 0);
883 ir_node *op2 = get_irn_n(node, 1);
884 ir_node *new_op1 = transform_node(env, op1);
885 ir_node *new_op2 = transform_node(env, op2);
886 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
887 ir_node *proj_EAX, *proj_EDX, *res;
888 ir_mode *mode = get_irn_mode(node);
891 assert(!mode_is_float(mode) && "Mulh with float not supported");
892 if(mode_is_signed(mode)) {
893 res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
895 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
898 set_ia32_commutative(res);
899 set_ia32_am_support(res, ia32_am_Source);
901 set_ia32_am_support(res, ia32_am_Source);
903 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
904 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
908 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
916 * Creates an ia32 And.
918 * @param env The transformation environment
919 * @return The created ia32 And node
921 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
922 ir_node *op1 = get_And_left(node);
923 ir_node *op2 = get_And_right(node);
924 ir_mode *mode = get_irn_mode(node);
926 assert (! mode_is_float(mode));
927 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
933 * Creates an ia32 Or.
935 * @param env The transformation environment
936 * @return The created ia32 Or node
938 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
939 ir_node *op1 = get_Or_left(node);
940 ir_node *op2 = get_Or_right(node);
941 ir_mode *mode = get_irn_mode(node);
943 assert (! mode_is_float(mode));
944 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
950 * Creates an ia32 Eor.
952 * @param env The transformation environment
953 * @return The created ia32 Eor node
955 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
956 ir_node *op1 = get_Eor_left(node);
957 ir_node *op2 = get_Eor_right(node);
958 ir_mode *mode = get_irn_mode(node);
960 assert(! mode_is_float(mode));
961 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
967 * Creates an ia32 Max.
969 * @param env The transformation environment
970 * @return the created ia32 Max node
972 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
973 ir_graph *irg = env->irg;
975 ir_mode *mode = get_irn_mode(node);
976 dbg_info *dbg = get_irn_dbg_info(node);
977 ir_node *block = transform_node(env, get_nodes_block(node));
978 ir_node *op1 = get_irn_n(node, 0);
979 ir_node *op2 = get_irn_n(node, 1);
980 ir_node *new_op1 = transform_node(env, op1);
981 ir_node *new_op2 = transform_node(env, op2);
982 ir_mode *op_mode = get_irn_mode(op1);
984 assert(get_mode_size_bits(mode) == 32);
986 if (mode_is_float(mode)) {
988 if (USE_SSE2(env->cg))
989 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
995 long pnc = pn_Cmp_Gt;
996 if(!mode_is_signed(op_mode)) {
997 pnc |= ia32_pn_Cmp_Unsigned;
999 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1000 set_ia32_pncode(new_op, pnc);
1001 set_ia32_am_support(new_op, ia32_am_None);
1003 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1009 * Creates an ia32 Min.
1011 * @param env The transformation environment
1012 * @return the created ia32 Min node
1014 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1015 ir_graph *irg = env->irg;
1017 ir_mode *mode = get_irn_mode(node);
1018 dbg_info *dbg = get_irn_dbg_info(node);
1019 ir_node *block = transform_node(env, get_nodes_block(node));
1020 ir_node *op1 = get_irn_n(node, 0);
1021 ir_node *op2 = get_irn_n(node, 1);
1022 ir_node *new_op1 = transform_node(env, op1);
1023 ir_node *new_op2 = transform_node(env, op2);
1024 ir_mode *op_mode = get_irn_mode(op1);
1026 assert(get_mode_size_bits(mode) == 32);
1028 if (mode_is_float(mode)) {
1030 if (USE_SSE2(env->cg))
1031 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1037 long pnc = pn_Cmp_Lt;
1038 if(!mode_is_signed(op_mode)) {
1039 pnc |= ia32_pn_Cmp_Unsigned;
1041 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1042 set_ia32_pncode(new_op, pnc);
1043 set_ia32_am_support(new_op, ia32_am_None);
1045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1052 * Creates an ia32 Sub.
1054 * @param env The transformation environment
1055 * @return The created ia32 Sub node
1057 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1058 ir_node *new_op = NULL;
1059 ir_graph *irg = env->irg;
1060 dbg_info *dbg = get_irn_dbg_info(node);
1061 ir_mode *mode = get_irn_mode(node);
1062 ir_node *block = transform_node(env, get_nodes_block(node));
1063 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1064 ir_node *nomem = new_NoMem();
1065 ir_node *op1 = get_Sub_left(node);
1066 ir_node *op2 = get_Sub_right(node);
1067 ir_node *new_op1 = transform_node(env, op1);
1068 ir_node *new_op2 = transform_node(env, op2);
1069 ir_node *expr_op, *imm_op;
1071 /* Check if immediate optimization is on and */
1072 /* if it's an operation with immediate. */
1073 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1074 expr_op = get_expr_op(new_op1, new_op2);
1076 assert((expr_op || imm_op) && "invalid operands");
1078 if (mode_is_float(mode)) {
1080 if (USE_SSE2(env->cg))
1081 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1083 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1088 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1089 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1091 /* No expr_op means, that we have two const - one symconst and */
1092 /* one tarval or another symconst - because this case is not */
1093 /* covered by constant folding */
1094 /* We need to check for: */
1095 /* 1) symconst - const -> becomes a LEA */
1096 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1097 /* linker doesn't support two symconsts */
1098 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1099 /* this is the 2nd case */
1100 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1101 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1102 set_ia32_am_sc_sign(new_op);
1103 set_ia32_am_flavour(new_op, ia32_am_OB);
1105 DBG_OPT_LEA3(op1, op2, node, new_op);
1106 } else if (tp1 == ia32_ImmSymConst) {
1107 tarval *tv = get_ia32_Immop_tarval(new_op2);
1108 long offs = get_tarval_long(tv);
1110 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1111 DBG_OPT_LEA3(op1, op2, node, new_op);
1113 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1114 add_ia32_am_offs_int(new_op, -offs);
1115 set_ia32_am_flavour(new_op, ia32_am_O);
1116 set_ia32_am_support(new_op, ia32_am_Source);
1117 set_ia32_op_type(new_op, ia32_AddrModeS);
1118 } else if (tp2 == ia32_ImmSymConst) {
1119 tarval *tv = get_ia32_Immop_tarval(new_op1);
1120 long offs = get_tarval_long(tv);
1122 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1123 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 add_ia32_am_offs_int(new_op, offs);
1126 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1127 set_ia32_am_sc_sign(new_op);
1128 set_ia32_am_flavour(new_op, ia32_am_O);
1129 set_ia32_am_support(new_op, ia32_am_Source);
1130 set_ia32_op_type(new_op, ia32_AddrModeS);
1132 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1133 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1134 tarval *restv = tarval_sub(tv1, tv2);
1136 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1138 new_op = new_rd_ia32_Const(dbg, irg, block);
1139 set_ia32_Const_tarval(new_op, restv);
1140 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1143 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1145 } else if (imm_op) {
1146 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1147 tarval_classification_t class_tv, class_negtv;
1148 tarval *tv = get_ia32_Immop_tarval(imm_op);
1150 /* optimize tarvals */
1151 class_tv = classify_tarval(tv);
1152 class_negtv = classify_tarval(tarval_neg(tv));
1154 if (class_tv == TV_CLASSIFY_ONE) {
1155 DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
1156 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1157 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1159 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1160 DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
1161 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1168 /* This is a normal sub */
1169 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1171 /* set AM support */
1172 set_ia32_am_support(new_op, ia32_am_Full);
1174 fold_immediate(env, new_op, 2, 3);
1176 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1184 * Generates an ia32 DivMod with additional infrastructure for the
1185 * register allocator if needed.
1187 * @param env The transformation environment
1188 * @param dividend -no comment- :)
1189 * @param divisor -no comment- :)
1190 * @param dm_flav flavour_Div/Mod/DivMod
1191 * @return The created ia32 DivMod node
1193 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1194 ir_node *dividend, ir_node *divisor,
1195 ia32_op_flavour_t dm_flav) {
1196 ir_graph *irg = env->irg;
1197 dbg_info *dbg = get_irn_dbg_info(node);
1198 ir_mode *mode = get_irn_mode(node);
1199 ir_node *block = transform_node(env, get_nodes_block(node));
1200 ir_node *res, *proj_div, *proj_mod;
1201 ir_node *edx_node, *cltd;
1202 ir_node *in_keep[1];
1203 ir_node *mem, *new_mem;
1204 ir_node *projs[pn_DivMod_max];
1205 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1206 ir_node *new_dividend = transform_node(env, dividend);
1207 ir_node *new_divisor = transform_node(env, divisor);
1209 ia32_collect_Projs(node, projs, pn_DivMod_max);
1213 mem = get_Div_mem(node);
1214 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1217 mem = get_Mod_mem(node);
1218 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1220 case flavour_DivMod:
1221 mem = get_DivMod_mem(node);
1222 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1223 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1224 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1229 new_mem = transform_node(env, mem);
1231 if (mode_is_signed(mode)) {
1232 /* in signed mode, we need to sign extend the dividend */
1233 cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
1234 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1235 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1237 edx_node = new_rd_ia32_Const(dbg, irg, block);
1238 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1239 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1242 if(mode_is_signed(mode)) {
1243 res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1245 res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1248 /* Matze: code can't handle this at the moment... */
1250 /* set AM support */
1251 set_ia32_am_support(res, ia32_am_Source);
1254 set_ia32_n_res(res, 2);
1256 /* Only one proj is used -> We must add a second proj and */
1257 /* connect this one to a Keep node to eat up the second */
1258 /* destroyed register. */
1259 /* We also renumber the Firm projs into ia32 projs. */
1261 switch (get_irn_opcode(node)) {
1263 /* add Proj-Keep for mod res */
1264 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1265 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1268 /* add Proj-Keep for div res */
1269 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1270 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1273 /* check, which Proj-Keep, we need to add */
1274 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1275 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1277 if (proj_div && proj_mod) {
1278 /* nothing to be done */
1280 else if (! proj_div && ! proj_mod) {
1281 assert(0 && "Missing DivMod result proj");
1283 else if (! proj_div) {
1284 /* We have only mod result: add div res Proj-Keep */
1285 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1286 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1289 /* We have only div result: add mod res Proj-Keep */
1290 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1291 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1295 assert(0 && "Div, Mod, or DivMod expected.");
1299 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1306 * Wrapper for generate_DivMod. Sets flavour_Mod.
1308 * @param env The transformation environment
1310 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1311 return generate_DivMod(env, node, get_Mod_left(node),
1312 get_Mod_right(node), flavour_Mod);
1316 * Wrapper for generate_DivMod. Sets flavour_Div.
1318 * @param env The transformation environment
1320 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1321 return generate_DivMod(env, node, get_Div_left(node),
1322 get_Div_right(node), flavour_Div);
1326 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1328 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1329 return generate_DivMod(env, node, get_DivMod_left(node),
1330 get_DivMod_right(node), flavour_DivMod);
1336 * Creates an ia32 floating Div.
1338 * @param env The transformation environment
1339 * @return The created ia32 xDiv node
1341 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1342 ir_graph *irg = env->irg;
1343 dbg_info *dbg = get_irn_dbg_info(node);
1344 ir_node *block = transform_node(env, get_nodes_block(node));
1345 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1347 ir_node *nomem = new_rd_NoMem(env->irg);
1348 ir_node *op1 = get_Quot_left(node);
1349 ir_node *op2 = get_Quot_right(node);
1350 ir_node *new_op1 = transform_node(env, op1);
1351 ir_node *new_op2 = transform_node(env, op2);
1354 if (USE_SSE2(env->cg)) {
1355 ir_mode *mode = get_irn_mode(op1);
1356 if (is_ia32_xConst(new_op2)) {
1357 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1358 set_ia32_am_support(new_op, ia32_am_None);
1359 copy_ia32_Immop_attr(new_op, new_op2);
1361 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1362 // Matze: disabled for now, spillslot coalescer fails
1363 //set_ia32_am_support(new_op, ia32_am_Source);
1365 set_ia32_ls_mode(new_op, mode);
1367 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1368 // Matze: disabled for now (spillslot coalescer fails)
1369 //set_ia32_am_support(new_op, ia32_am_Source);
1371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1377 * Creates an ia32 Shl.
1379 * @param env The transformation environment
1380 * @return The created ia32 Shl node
1382 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1383 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1390 * Creates an ia32 Shr.
1392 * @param env The transformation environment
1393 * @return The created ia32 Shr node
1395 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1396 return gen_shift_binop(env, node, get_Shr_left(node),
1397 get_Shr_right(node), new_rd_ia32_Shr);
1403 * Creates an ia32 Sar.
1405 * @param env The transformation environment
1406 * @return The created ia32 Shrs node
1408 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1409 return gen_shift_binop(env, node, get_Shrs_left(node),
1410 get_Shrs_right(node), new_rd_ia32_Sar);
1416 * Creates an ia32 RotL.
1418 * @param env The transformation environment
1419 * @param op1 The first operator
1420 * @param op2 The second operator
1421 * @return The created ia32 RotL node
1423 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1424 ir_node *op1, ir_node *op2) {
1425 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1431 * Creates an ia32 RotR.
1432 * NOTE: There is no RotR with immediate because this would always be a RotL
1433 * "imm-mode_size_bits" which can be pre-calculated.
1435 * @param env The transformation environment
1436 * @param op1 The first operator
1437 * @param op2 The second operator
1438 * @return The created ia32 RotR node
1440 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1442 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1448 * Creates an ia32 RotR or RotL (depending on the found pattern).
1450 * @param env The transformation environment
1451 * @return The created ia32 RotL or RotR node
1453 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1454 ir_node *rotate = NULL;
1455 ir_node *op1 = get_Rot_left(node);
1456 ir_node *op2 = get_Rot_right(node);
1458 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1459 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1460 that means we can create a RotR instead of an Add and a RotL */
1462 if (get_irn_op(op2) == op_Add) {
1464 ir_node *left = get_Add_left(add);
1465 ir_node *right = get_Add_right(add);
1466 if (is_Const(right)) {
1467 tarval *tv = get_Const_tarval(right);
1468 ir_mode *mode = get_irn_mode(node);
1469 long bits = get_mode_size_bits(mode);
1471 if (get_irn_op(left) == op_Minus &&
1472 tarval_is_long(tv) &&
1473 get_tarval_long(tv) == bits)
1475 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1476 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1481 if (rotate == NULL) {
1482 rotate = gen_RotL(env, node, op1, op2);
1491 * Transforms a Minus node.
1493 * @param env The transformation environment
1494 * @param op The Minus operand
1495 * @return The created ia32 Minus node
1497 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1500 ir_graph *irg = env->irg;
1501 dbg_info *dbg = get_irn_dbg_info(node);
1502 ir_node *block = transform_node(env, get_nodes_block(node));
1503 ir_mode *mode = get_irn_mode(node);
1506 if (mode_is_float(mode)) {
1507 ir_node *new_op = transform_node(env, op);
1509 if (USE_SSE2(env->cg)) {
1510 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1511 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1512 ir_node *nomem = new_rd_NoMem(irg);
1514 res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1516 size = get_mode_size_bits(mode);
1517 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1519 set_ia32_am_sc(res, name);
1520 set_ia32_op_type(res, ia32_AddrModeS);
1521 set_ia32_ls_mode(res, mode);
1523 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1526 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1529 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1535 * Transforms a Minus node.
1537 * @param env The transformation environment
1538 * @return The created ia32 Minus node
1540 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1541 return gen_Minus_ex(env, node, get_Minus_op(node));
1546 * Transforms a Not node.
1548 * @param env The transformation environment
1549 * @return The created ia32 Not node
1551 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1552 ir_mode *mode = get_irn_mode(node);
1553 ir_node *op = get_Not_op(node);
1555 assert (! mode_is_float(mode));
1556 return gen_unop(env, node, op, new_rd_ia32_Not);
1562 * Transforms an Abs node.
1564 * @param env The transformation environment
1565 * @return The created ia32 Abs node
1567 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1568 ir_node *res, *p_eax, *p_edx;
1569 ir_graph *irg = env->irg;
1570 dbg_info *dbg = get_irn_dbg_info(node);
1571 ir_node *block = transform_node(env, get_nodes_block(node));
1572 ir_mode *mode = get_irn_mode(node);
1573 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1574 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1575 ir_node *nomem = new_NoMem();
1576 ir_node *op = get_Abs_op(node);
1577 ir_node *new_op = transform_node(env, op);
1581 if (mode_is_float(mode)) {
1583 if (USE_SSE2(env->cg)) {
1584 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1586 size = get_mode_size_bits(mode);
1587 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1589 set_ia32_am_sc(res, name);
1591 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1593 set_ia32_op_type(res, ia32_AddrModeS);
1594 set_ia32_ls_mode(res, mode);
1597 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1602 res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
1603 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1605 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1606 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1608 res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1609 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1611 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1612 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1621 * Transforms a Load.
1623 * @param env The transformation environment
1624 * @return the created ia32 Load node
1626 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1627 ir_graph *irg = env->irg;
1628 dbg_info *dbg = get_irn_dbg_info(node);
1629 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1630 ir_mode *mode = get_Load_mode(node);
1631 ir_node *block = transform_node(env, get_nodes_block(node));
1632 ir_node *ptr = get_Load_ptr(node);
1633 ir_node *new_ptr = transform_node(env, ptr);
1634 ir_node *lptr = new_ptr;
1635 ir_node *mem = get_Load_mem(node);
1636 ir_node *new_mem = transform_node(env, mem);
1639 ia32_am_flavour_t am_flav = ia32_am_B;
1640 ir_node *projs[pn_Load_max];
1642 ia32_collect_Projs(node, projs, pn_Load_max);
1645 check for special case: the loaded value might not be used (optimized, volatile, ...)
1646 we add a Proj + Keep for volatile loads and ignore all other cases
1648 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1649 /* add a result proj and a Keep to produce a pseudo use */
1650 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1651 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1654 /* address might be a constant (symconst or absolute address) */
1655 if (is_ia32_Const(new_ptr)) {
1660 if (mode_is_float(mode)) {
1662 if (USE_SSE2(env->cg)) {
1663 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1665 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1668 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1671 /* base is a constant address */
1673 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1674 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1675 am_flav = ia32_am_N;
1677 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1678 long offs = get_tarval_long(tv);
1680 add_ia32_am_offs_int(new_op, offs);
1681 am_flav = ia32_am_O;
1685 set_ia32_am_support(new_op, ia32_am_Source);
1686 set_ia32_op_type(new_op, ia32_AddrModeS);
1687 set_ia32_am_flavour(new_op, am_flav);
1688 set_ia32_ls_mode(new_op, mode);
1690 /* make sure we are scheduled behind the intial IncSP/Barrier
1691 * to avoid spills being placed before it
1693 if(block == get_irg_start_block(irg)) {
1694 add_irn_dep(new_op, get_irg_frame(irg));
1697 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1705 * Transforms a Store.
1707 * @param env The transformation environment
1708 * @return the created ia32 Store node
1710 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1711 ir_graph *irg = env->irg;
1712 dbg_info *dbg = get_irn_dbg_info(node);
1713 ir_node *block = transform_node(env, get_nodes_block(node));
1714 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1715 ir_node *ptr = get_Store_ptr(node);
1716 ir_node *new_ptr = transform_node(env, ptr);
1717 ir_node *sptr = new_ptr;
1718 ir_node *val = get_Store_value(node);
1719 ir_node *new_val = transform_node(env, val);
1720 ir_node *mem = get_Store_mem(node);
1721 ir_node *new_mem = transform_node(env, mem);
1722 ir_mode *mode = get_irn_mode(val);
1723 ir_node *sval = new_val;
1726 ia32_am_flavour_t am_flav = ia32_am_B;
1728 if (is_ia32_Const(new_val)) {
1729 assert(!mode_is_float(mode));
1733 /* address might be a constant (symconst or absolute address) */
1734 if (is_ia32_Const(new_ptr)) {
1739 if (mode_is_float(mode)) {
1741 if (USE_SSE2(env->cg)) {
1742 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1744 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1746 } else if (get_mode_size_bits(mode) == 8) {
1747 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1749 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1752 /* stored const is an immediate value */
1753 if (is_ia32_Const(new_val)) {
1754 assert(!mode_is_float(mode));
1755 copy_ia32_Immop_attr(new_op, new_val);
1758 /* base is an constant address */
1760 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1761 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1762 am_flav = ia32_am_N;
1764 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1765 long offs = get_tarval_long(tv);
1767 add_ia32_am_offs_int(new_op, offs);
1768 am_flav = ia32_am_O;
1772 set_ia32_am_support(new_op, ia32_am_Dest);
1773 set_ia32_op_type(new_op, ia32_AddrModeD);
1774 set_ia32_am_flavour(new_op, am_flav);
1775 set_ia32_ls_mode(new_op, mode);
1777 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1785 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1787 * @param env The transformation environment
1788 * @return The transformed node.
1790 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1791 ir_graph *irg = env->irg;
1792 dbg_info *dbg = get_irn_dbg_info(node);
1793 ir_node *block = transform_node(env, get_nodes_block(node));
1794 ir_node *sel = get_Cond_selector(node);
1795 ir_mode *sel_mode = get_irn_mode(sel);
1796 ir_node *res = NULL;
1797 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1798 ir_node *cnst, *expr;
1800 if (is_Proj(sel) && sel_mode == mode_b) {
1801 ir_node *nomem = new_NoMem();
1802 ir_node *pred = get_Proj_pred(sel);
1803 ir_node *cmp_a = get_Cmp_left(pred);
1804 ir_node *new_cmp_a = transform_node(env, cmp_a);
1805 ir_node *cmp_b = get_Cmp_right(pred);
1806 ir_node *new_cmp_b = transform_node(env, cmp_b);
1807 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1809 int pnc = get_Proj_proj(sel);
1810 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1811 pnc |= ia32_pn_Cmp_Unsigned;
1814 /* check if we can use a CondJmp with immediate */
1815 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1816 expr = get_expr_op(new_cmp_a, new_cmp_b);
1818 if (cnst != NULL && expr != NULL) {
1819 /* immop has to be the right operand, we might need to flip pnc */
1820 if(cnst != new_cmp_b) {
1821 pnc = get_inversed_pnc(pnc);
1824 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1825 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1826 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1828 /* a Cmp A =/!= 0 */
1829 ir_node *op1 = expr;
1830 ir_node *op2 = expr;
1833 /* check, if expr is an only once used And operation */
1834 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1835 op1 = get_irn_n(expr, 2);
1836 op2 = get_irn_n(expr, 3);
1838 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1840 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1841 set_ia32_pncode(res, pnc);
1844 copy_ia32_Immop_attr(res, expr);
1847 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1852 if (mode_is_float(cmp_mode)) {
1854 if (USE_SSE2(env->cg)) {
1855 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1856 set_ia32_ls_mode(res, cmp_mode);
1862 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1864 copy_ia32_Immop_attr(res, cnst);
1867 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1869 if (mode_is_float(cmp_mode)) {
1871 if (USE_SSE2(env->cg)) {
1872 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1873 set_ia32_ls_mode(res, cmp_mode);
1876 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1877 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1878 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1882 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1883 set_ia32_commutative(res);
1887 set_ia32_pncode(res, pnc);
1888 // Matze: disabled for now, because the default collect_spills_walker
1889 // is not able to detect the mode of the spilled value
1890 // moreover, the lea optimize phase freely exchanges left/right
1891 // without updating the pnc
1892 //set_ia32_am_support(res, ia32_am_Source);
1895 /* determine the smallest switch case value */
1896 int switch_min = INT_MAX;
1897 const ir_edge_t *edge;
1898 ir_node *new_sel = transform_node(env, sel);
1900 foreach_out_edge(node, edge) {
1901 int pn = get_Proj_proj(get_edge_src_irn(edge));
1902 switch_min = pn < switch_min ? pn : switch_min;
1906 /* if smallest switch case is not 0 we need an additional sub */
1907 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1908 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1909 add_ia32_am_offs_int(res, -switch_min);
1910 set_ia32_am_flavour(res, ia32_am_OB);
1911 set_ia32_am_support(res, ia32_am_Source);
1912 set_ia32_op_type(res, ia32_AddrModeS);
1915 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1916 set_ia32_pncode(res, get_Cond_defaultProj(node));
1919 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1926 * Transforms a CopyB node.
1928 * @param env The transformation environment
1929 * @return The transformed node.
1931 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1932 ir_node *res = NULL;
1933 ir_graph *irg = env->irg;
1934 dbg_info *dbg = get_irn_dbg_info(node);
1935 ir_node *block = transform_node(env, get_nodes_block(node));
1936 ir_node *src = get_CopyB_src(node);
1937 ir_node *new_src = transform_node(env, src);
1938 ir_node *dst = get_CopyB_dst(node);
1939 ir_node *new_dst = transform_node(env, dst);
1940 ir_node *mem = get_CopyB_mem(node);
1941 ir_node *new_mem = transform_node(env, mem);
1942 int size = get_type_size_bytes(get_CopyB_type(node));
1943 ir_mode *dst_mode = get_irn_mode(dst);
1944 ir_mode *src_mode = get_irn_mode(src);
1948 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1949 /* then we need the size explicitly in ECX. */
1950 if (size >= 32 * 4) {
1951 rem = size & 0x3; /* size % 4 */
1954 res = new_rd_ia32_Const(dbg, irg, block);
1955 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1956 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1958 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
1959 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1961 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1962 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1963 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1964 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1965 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1968 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
1969 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1971 /* ok: now attach Proj's because movsd will destroy esi and edi */
1972 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1973 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1974 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1977 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1985 * Transforms a Mux node into CMov.
1987 * @param env The transformation environment
1988 * @return The transformed node.
1990 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1991 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1992 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1994 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2000 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2001 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2002 ir_node *psi_default);
2005 * Transforms a Psi node into CMov.
2007 * @param env The transformation environment
2008 * @return The transformed node.
2010 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
2011 ia32_code_gen_t *cg = env->cg;
2012 ir_graph *irg = env->irg;
2013 dbg_info *dbg = get_irn_dbg_info(node);
2014 ir_mode *mode = get_irn_mode(node);
2015 ir_node *block = transform_node(env, get_nodes_block(node));
2016 ir_node *cmp_proj = get_Mux_sel(node);
2017 ir_node *psi_true = get_Psi_val(node, 0);
2018 ir_node *psi_default = get_Psi_default(node);
2019 ir_node *new_psi_true = transform_node(env, psi_true);
2020 ir_node *new_psi_default = transform_node(env, psi_default);
2021 ir_node *noreg = ia32_new_NoReg_gp(cg);
2022 ir_node *nomem = new_rd_NoMem(irg);
2023 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2024 ir_node *new_cmp_a, *new_cmp_b;
2028 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2030 cmp = get_Proj_pred(cmp_proj);
2031 cmp_a = get_Cmp_left(cmp);
2032 cmp_b = get_Cmp_right(cmp);
2033 cmp_mode = get_irn_mode(cmp_a);
2034 new_cmp_a = transform_node(env, cmp_a);
2035 new_cmp_b = transform_node(env, cmp_b);
2037 pnc = get_Proj_proj(cmp_proj);
2038 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2039 pnc |= ia32_pn_Cmp_Unsigned;
2042 if (mode_is_float(mode)) {
2043 /* floating point psi */
2046 /* 1st case: compare operands are float too */
2048 /* psi(cmp(a, b), t, f) can be done as: */
2049 /* tmp = cmp a, b */
2050 /* tmp2 = t and tmp */
2051 /* tmp3 = f and not tmp */
2052 /* res = tmp2 or tmp3 */
2054 /* in case the compare operands are int, we move them into xmm register */
2055 if (! mode_is_float(get_irn_mode(cmp_a))) {
2056 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
2057 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
2059 pnc |= 8; /* transform integer compare to fp compare */
2062 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2063 set_ia32_pncode(new_op, pnc);
2064 set_ia32_am_support(new_op, ia32_am_Source);
2065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2067 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2068 set_ia32_am_support(and1, ia32_am_None);
2069 set_ia32_commutative(and1);
2070 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2072 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2073 set_ia32_am_support(and2, ia32_am_None);
2074 set_ia32_commutative(and2);
2075 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2077 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2078 set_ia32_am_support(new_op, ia32_am_None);
2079 set_ia32_commutative(new_op);
2080 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2084 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2085 set_ia32_pncode(new_op, pnc);
2086 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2091 construct_binop_func *set_func = NULL;
2092 cmov_func_t *cmov_func = NULL;
2094 if (mode_is_float(get_irn_mode(cmp_a))) {
2095 /* 1st case: compare operands are floats */
2100 set_func = new_rd_ia32_xCmpSet;
2101 cmov_func = new_rd_ia32_xCmpCMov;
2105 set_func = new_rd_ia32_vfCmpSet;
2106 cmov_func = new_rd_ia32_vfCmpCMov;
2109 pnc &= ~0x8; /* fp compare -> int compare */
2112 /* 2nd case: compare operand are integer too */
2113 set_func = new_rd_ia32_CmpSet;
2114 cmov_func = new_rd_ia32_CmpCMov;
2117 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2118 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2119 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2120 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2121 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2122 set_ia32_pncode(new_op, pnc);
2124 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2125 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2126 /* we invert condition and set default to 0 */
2127 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2128 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2131 /* otherwise: use CMOVcc */
2132 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2133 set_ia32_pncode(new_op, pnc);
2136 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2139 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2140 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2141 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2142 set_ia32_pncode(new_op, pnc);
2143 set_ia32_am_support(new_op, ia32_am_Source);
2145 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2146 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2147 /* we invert condition and set default to 0 */
2148 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2149 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2150 set_ia32_am_support(new_op, ia32_am_Source);
2153 /* otherwise: use CMOVcc */
2154 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2155 set_ia32_pncode(new_op, pnc);
2156 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2166 * Following conversion rules apply:
2170 * 1) n bit -> m bit n > m (downscale)
2172 * 2) n bit -> m bit n == m (sign change)
2174 * 3) n bit -> m bit n < m (upscale)
2175 * a) source is signed: movsx
2176 * b) source is unsigned: and with lower bits sets
2180 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2184 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2188 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2189 * x87 is mode_E internally, conversions happen only at load and store
2190 * in non-strict semantic
2194 * Create a conversion from x87 state register to general purpose.
2196 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2197 ia32_code_gen_t *cg = env->cg;
2198 ir_graph *irg = env->irg;
2199 dbg_info *dbg = get_irn_dbg_info(node);
2200 ir_node *block = transform_node(env, get_nodes_block(node));
2201 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2202 ir_node *op = get_Conv_op(node);
2203 ir_node *new_op = transform_node(env, op);
2204 ir_node *fist, *load;
2207 fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem());
2209 set_ia32_use_frame(fist);
2210 set_ia32_am_support(fist, ia32_am_Dest);
2211 set_ia32_op_type(fist, ia32_AddrModeD);
2212 set_ia32_am_flavour(fist, ia32_am_B);
2213 set_ia32_ls_mode(fist, mode_Iu);
2214 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2217 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2219 set_ia32_use_frame(load);
2220 set_ia32_am_support(load, ia32_am_Source);
2221 set_ia32_op_type(load, ia32_AddrModeS);
2222 set_ia32_am_flavour(load, ia32_am_B);
2223 set_ia32_ls_mode(load, mode_Iu);
2224 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2226 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2230 * Create a conversion from general purpose to x87 register
2232 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2233 ia32_code_gen_t *cg = env->cg;
2234 ir_graph *irg = env->irg;
2235 dbg_info *dbg = get_irn_dbg_info(node);
2236 ir_mode *mode = get_irn_mode(node);
2237 ir_node *block = transform_node(env, get_nodes_block(node));
2238 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2239 ir_node *nomem = new_NoMem();
2240 ir_node *op = get_Conv_op(node);
2241 ir_node *new_op = transform_node(env, op);
2242 ir_node *fild, *store;
2245 /* first convert to 32 bit if necessary */
2246 src_bits = get_mode_size_bits(src_mode);
2247 if (src_bits == 8) {
2248 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2249 set_ia32_am_support(new_op, ia32_am_Source);
2250 set_ia32_ls_mode(new_op, src_mode);
2251 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2252 } else if (src_bits < 32) {
2253 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2254 set_ia32_am_support(new_op, ia32_am_Source);
2255 set_ia32_ls_mode(new_op, src_mode);
2256 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2260 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2262 set_ia32_use_frame(store);
2263 set_ia32_am_support(store, ia32_am_Dest);
2264 set_ia32_op_type(store, ia32_AddrModeD);
2265 set_ia32_am_flavour(store, ia32_am_OB);
2266 set_ia32_ls_mode(store, mode_Iu);
2269 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2271 set_ia32_use_frame(fild);
2272 set_ia32_am_support(fild, ia32_am_Source);
2273 set_ia32_op_type(fild, ia32_AddrModeS);
2274 set_ia32_am_flavour(fild, ia32_am_OB);
2275 set_ia32_ls_mode(fild, mode);
2277 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2281 * Transforms a Conv node.
2283 * @param env The transformation environment
2284 * @return The created ia32 Conv node
2286 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2287 ir_graph *irg = env->irg;
2288 dbg_info *dbg = get_irn_dbg_info(node);
2289 ir_node *op = get_Conv_op(node);
2290 ir_mode *src_mode = get_irn_mode(op);
2291 ir_mode *tgt_mode = get_irn_mode(node);
2292 int src_bits = get_mode_size_bits(src_mode);
2293 int tgt_bits = get_mode_size_bits(tgt_mode);
2294 ir_node *block = transform_node(env, get_nodes_block(node));
2296 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2297 ir_node *nomem = new_rd_NoMem(irg);
2298 ir_node *new_op = transform_node(env, op);
2299 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2301 if (src_mode == tgt_mode) {
2302 /* this should be optimized already, but who knows... */
2303 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2304 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2308 if (mode_is_float(src_mode)) {
2309 /* we convert from float ... */
2310 if (mode_is_float(tgt_mode)) {
2312 if (USE_SSE2(env->cg)) {
2313 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2314 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2315 set_ia32_ls_mode(res, tgt_mode);
2317 // Matze: TODO what about strict convs?
2318 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2323 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2324 if (USE_SSE2(env->cg)) {
2325 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2326 set_ia32_ls_mode(res, src_mode);
2328 return gen_x87_fp_to_gp(env, node);
2332 /* we convert from int ... */
2333 if (mode_is_float(tgt_mode)) {
2336 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2337 if (USE_SSE2(env->cg)) {
2338 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2339 set_ia32_ls_mode(res, tgt_mode);
2340 if(src_bits == 32) {
2341 set_ia32_am_support(res, ia32_am_Source);
2344 return gen_x87_gp_to_fp(env, node, src_mode);
2348 ir_mode *smaller_mode;
2351 if (src_bits == tgt_bits) {
2352 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2356 if(src_bits < tgt_bits) {
2357 smaller_mode = src_mode;
2358 smaller_bits = src_bits;
2360 smaller_mode = tgt_mode;
2361 smaller_bits = tgt_bits;
2364 // The following is not correct, we can't change the mode,
2365 // maybe others are using the load too
2366 // better move this to a separate phase!
2369 if(is_Proj(new_op)) {
2370 /* load operations do already sign/zero extend, so we have
2371 * nothing left to do */
2372 ir_node *pred = get_Proj_pred(new_op);
2373 if(is_ia32_Load(pred)) {
2374 set_ia32_ls_mode(pred, smaller_mode);
2380 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2381 if (smaller_bits == 8) {
2382 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2383 set_ia32_ls_mode(res, smaller_mode);
2385 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2386 set_ia32_ls_mode(res, smaller_mode);
2388 set_ia32_am_support(res, ia32_am_Source);
2392 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2399 /********************************************
2402 * | |__ ___ _ __ ___ __| | ___ ___
2403 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2404 * | |_) | __/ | | | (_) | (_| | __/\__ \
2405 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2407 ********************************************/
2409 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2410 ir_node *new_op = NULL;
2411 ir_graph *irg = env->irg;
2412 dbg_info *dbg = get_irn_dbg_info(node);
2413 ir_node *block = transform_node(env, get_nodes_block(node));
2414 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2415 ir_node *nomem = new_rd_NoMem(env->irg);
2416 ir_node *ptr = get_irn_n(node, 0);
2417 ir_node *new_ptr = transform_node(env, ptr);
2418 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2419 ir_mode *load_mode = get_irn_mode(node);
2423 if (mode_is_float(load_mode)) {
2425 if (USE_SSE2(env->cg)) {
2426 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2427 pn_res = pn_ia32_xLoad_res;
2429 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2430 pn_res = pn_ia32_vfld_res;
2435 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2436 proj_mode = mode_Iu;
2437 pn_res = pn_ia32_Load_res;
2440 set_ia32_frame_ent(new_op, ent);
2441 set_ia32_use_frame(new_op);
2443 set_ia32_am_support(new_op, ia32_am_Source);
2444 set_ia32_op_type(new_op, ia32_AddrModeS);
2445 set_ia32_am_flavour(new_op, ia32_am_B);
2446 set_ia32_ls_mode(new_op, load_mode);
2447 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2449 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2451 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2455 * Transforms a FrameAddr into an ia32 Add.
2457 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2458 ir_graph *irg = env->irg;
2459 dbg_info *dbg = get_irn_dbg_info(node);
2460 ir_node *block = transform_node(env, get_nodes_block(node));
2461 ir_node *op = get_irn_n(node, 0);
2462 ir_node *new_op = transform_node(env, op);
2464 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2466 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2467 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2468 set_ia32_am_support(res, ia32_am_Full);
2469 set_ia32_use_frame(res);
2470 set_ia32_am_flavour(res, ia32_am_OB);
2472 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2478 * Transforms a FrameLoad into an ia32 Load.
2480 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2481 ir_node *new_op = NULL;
2482 ir_graph *irg = env->irg;
2483 dbg_info *dbg = get_irn_dbg_info(node);
2484 ir_node *block = transform_node(env, get_nodes_block(node));
2485 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2486 ir_node *mem = get_irn_n(node, 0);
2487 ir_node *ptr = get_irn_n(node, 1);
2488 ir_node *new_mem = transform_node(env, mem);
2489 ir_node *new_ptr = transform_node(env, ptr);
2490 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2491 ir_mode *mode = get_type_mode(get_entity_type(ent));
2492 ir_node *projs[pn_Load_max];
2494 ia32_collect_Projs(node, projs, pn_Load_max);
2496 if (mode_is_float(mode)) {
2498 if (USE_SSE2(env->cg)) {
2499 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2502 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2506 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2509 set_ia32_frame_ent(new_op, ent);
2510 set_ia32_use_frame(new_op);
2512 set_ia32_am_support(new_op, ia32_am_Source);
2513 set_ia32_op_type(new_op, ia32_AddrModeS);
2514 set_ia32_am_flavour(new_op, ia32_am_B);
2515 set_ia32_ls_mode(new_op, mode);
2517 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2524 * Transforms a FrameStore into an ia32 Store.
2526 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2527 ir_node *new_op = NULL;
2528 ir_graph *irg = env->irg;
2529 dbg_info *dbg = get_irn_dbg_info(node);
2530 ir_node *block = transform_node(env, get_nodes_block(node));
2531 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2532 ir_node *mem = get_irn_n(node, 0);
2533 ir_node *ptr = get_irn_n(node, 1);
2534 ir_node *val = get_irn_n(node, 2);
2535 ir_node *new_mem = transform_node(env, mem);
2536 ir_node *new_ptr = transform_node(env, ptr);
2537 ir_node *new_val = transform_node(env, val);
2538 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2539 ir_mode *mode = get_irn_mode(val);
2541 if (mode_is_float(mode)) {
2543 if (USE_SSE2(env->cg)) {
2544 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2547 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2550 else if (get_mode_size_bits(mode) == 8) {
2551 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2554 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2557 set_ia32_frame_ent(new_op, ent);
2558 set_ia32_use_frame(new_op);
2560 set_ia32_am_support(new_op, ia32_am_Dest);
2561 set_ia32_op_type(new_op, ia32_AddrModeD);
2562 set_ia32_am_flavour(new_op, ia32_am_B);
2563 set_ia32_ls_mode(new_op, mode);
2565 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2571 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2573 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2574 ir_graph *irg = env->irg;
2577 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2578 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2579 ir_entity *ent = get_irg_entity(irg);
2580 ir_type *tp = get_entity_type(ent);
2583 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2584 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2586 int pn_ret_val, pn_ret_mem, arity, i;
2588 assert(ret_val != NULL);
2589 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2590 return duplicate_node(env, node);
2593 res_type = get_method_res_type(tp, 0);
2595 if (!is_Primitive_type(res_type)) {
2596 return duplicate_node(env, node);
2599 mode = get_type_mode(res_type);
2600 if (!mode_is_float(mode)) {
2601 return duplicate_node(env, node);
2604 assert(get_method_n_ress(tp) == 1);
2606 pn_ret_val = get_Proj_proj(ret_val);
2607 pn_ret_mem = get_Proj_proj(ret_mem);
2609 /* get the Barrier */
2610 barrier = get_Proj_pred(ret_val);
2612 /* get result input of the Barrier */
2613 ret_val = get_irn_n(barrier, pn_ret_val);
2614 new_ret_val = transform_node(env, ret_val);
2616 /* get memory input of the Barrier */
2617 ret_mem = get_irn_n(barrier, pn_ret_mem);
2618 new_ret_mem = transform_node(env, ret_mem);
2620 frame = get_irg_frame(irg);
2622 dbg = get_irn_dbg_info(barrier);
2623 block = transform_node(env, get_nodes_block(barrier));
2625 /* store xmm0 onto stack */
2626 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem);
2627 set_ia32_ls_mode(sse_store, mode);
2628 set_ia32_op_type(sse_store, ia32_AddrModeD);
2629 set_ia32_use_frame(sse_store);
2630 set_ia32_am_flavour(sse_store, ia32_am_B);
2631 set_ia32_am_support(sse_store, ia32_am_Dest);
2634 fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store);
2635 set_ia32_ls_mode(fld, mode);
2636 set_ia32_op_type(fld, ia32_AddrModeS);
2637 set_ia32_use_frame(fld);
2638 set_ia32_am_flavour(fld, ia32_am_B);
2639 set_ia32_am_support(fld, ia32_am_Source);
2641 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2642 fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
2643 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2645 /* create a new barrier */
2646 arity = get_irn_arity(barrier);
2647 in = alloca(arity * sizeof(in[0]));
2648 for(i = 0; i < arity; ++i) {
2650 if(i == pn_ret_val) {
2652 } else if(i == pn_ret_mem) {
2655 ir_node *in = get_irn_n(barrier, i);
2656 new_in = transform_node(env, in);
2661 new_barrier = new_ir_node(dbg, irg, block,
2662 get_irn_op(barrier), get_irn_mode(barrier),
2664 copy_node_attr(barrier, new_barrier);
2665 duplicate_deps(env, barrier, new_barrier);
2666 set_new_node(barrier, new_barrier);
2667 mark_irn_visited(barrier);
2669 /* transform normally */
2670 return duplicate_node(env, node);
2674 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2676 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2678 ir_graph *irg = env->irg;
2679 dbg_info *dbg = get_irn_dbg_info(node);
2680 ir_node *block = transform_node(env, get_nodes_block(node));
2681 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2682 ir_node *new_sz = transform_node(env, sz);
2683 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2684 ir_node *new_sp = transform_node(env, sp);
2685 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2686 ir_node *nomem = new_NoMem();
2688 /* ia32 stack grows in reverse direction, make a SubSP */
2689 new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2690 set_ia32_am_support(new_op, ia32_am_Source);
2691 fold_immediate(env, new_op, 2, 3);
2693 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2699 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2701 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2703 ir_graph *irg = env->irg;
2704 dbg_info *dbg = get_irn_dbg_info(node);
2705 ir_node *block = transform_node(env, get_nodes_block(node));
2706 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2707 ir_node *new_sz = transform_node(env, sz);
2708 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2709 ir_node *new_sp = transform_node(env, sp);
2710 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2711 ir_node *nomem = new_NoMem();
2713 /* ia32 stack grows in reverse direction, make an AddSP */
2714 new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2715 set_ia32_am_support(new_op, ia32_am_Source);
2716 fold_immediate(env, new_op, 2, 3);
2718 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2724 * This function just sets the register for the Unknown node
2725 * as this is not done during register allocation because Unknown
2726 * is an "ignore" node.
2728 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2729 ir_mode *mode = get_irn_mode(node);
2731 if (mode_is_float(mode)) {
2732 if (USE_SSE2(env->cg))
2733 return ia32_new_Unknown_xmm(env->cg);
2735 return ia32_new_Unknown_vfp(env->cg);
2736 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2737 return ia32_new_Unknown_gp(env->cg);
2739 assert(0 && "unsupported Unknown-Mode");
2746 * Change some phi modes
2748 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2749 ir_graph *irg = env->irg;
2750 dbg_info *dbg = get_irn_dbg_info(node);
2751 ir_mode *mode = get_irn_mode(node);
2752 ir_node *block = transform_node(env, get_nodes_block(node));
2756 if(mode_is_int(mode) || mode_is_reference(mode)) {
2757 // we shouldn't have any 64bit stuff around anymore
2758 assert(get_mode_size_bits(mode) <= 32);
2759 // all integer operations are on 32bit registers now
2761 } else if(mode_is_float(mode)) {
2762 assert(mode == mode_D || mode == mode_F);
2763 // all float operations are on mode_E registers
2767 /* phi nodes allow loops, so we use the old arguments for now
2768 * and fix this later */
2769 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2770 get_irn_in(node) + 1);
2771 copy_node_attr(node, phi);
2772 duplicate_deps(env, node, phi);
2774 set_new_node(node, phi);
2776 /* put the preds in the worklist */
2777 arity = get_irn_arity(node);
2778 for(i = 0; i < arity; ++i) {
2779 ir_node *pred = get_irn_n(node, i);
2780 pdeq_putr(env->worklist, pred);
2786 /**********************************************************************
2789 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2790 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2791 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2792 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2794 **********************************************************************/
2796 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2798 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2801 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2802 ir_node *val, ir_node *mem);
2805 * Transforms a lowered Load into a "real" one.
2807 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2808 ir_graph *irg = env->irg;
2809 dbg_info *dbg = get_irn_dbg_info(node);
2810 ir_node *block = transform_node(env, get_nodes_block(node));
2811 ir_mode *mode = get_ia32_ls_mode(node);
2813 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2814 ir_node *ptr = get_irn_n(node, 0);
2815 ir_node *mem = get_irn_n(node, 1);
2816 ir_node *new_ptr = transform_node(env, ptr);
2817 ir_node *new_mem = transform_node(env, mem);
2820 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2821 lowering we have x87 nodes, so we need to enforce simulation.
2823 if (mode_is_float(mode)) {
2825 if (fp_unit == fp_x87)
2829 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2831 set_ia32_am_support(new_op, ia32_am_Source);
2832 set_ia32_op_type(new_op, ia32_AddrModeS);
2833 set_ia32_am_flavour(new_op, ia32_am_OB);
2834 set_ia32_am_offs_int(new_op, 0);
2835 set_ia32_am_scale(new_op, 1);
2836 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2837 if(is_ia32_am_sc_sign(node))
2838 set_ia32_am_sc_sign(new_op);
2839 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2840 if(is_ia32_use_frame(node)) {
2841 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2842 set_ia32_use_frame(new_op);
2845 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2851 * Transforms a lowered Store into a "real" one.
2853 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2854 ir_graph *irg = env->irg;
2855 dbg_info *dbg = get_irn_dbg_info(node);
2856 ir_node *block = transform_node(env, get_nodes_block(node));
2857 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2858 ir_mode *mode = get_ia32_ls_mode(node);
2861 ia32_am_flavour_t am_flav = ia32_B;
2862 ir_node *ptr = get_irn_n(node, 0);
2863 ir_node *val = get_irn_n(node, 1);
2864 ir_node *mem = get_irn_n(node, 2);
2865 ir_node *new_ptr = transform_node(env, ptr);
2866 ir_node *new_val = transform_node(env, val);
2867 ir_node *new_mem = transform_node(env, mem);
2870 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2871 lowering we have x87 nodes, so we need to enforce simulation.
2873 if (mode_is_float(mode)) {
2875 if (fp_unit == fp_x87)
2879 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2881 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2883 add_ia32_am_offs_int(new_op, am_offs);
2886 set_ia32_am_support(new_op, ia32_am_Dest);
2887 set_ia32_op_type(new_op, ia32_AddrModeD);
2888 set_ia32_am_flavour(new_op, am_flav);
2889 set_ia32_ls_mode(new_op, mode);
2890 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2891 set_ia32_use_frame(new_op);
2893 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2900 * Transforms an ia32_l_XXX into a "real" XXX node
2902 * @param env The transformation environment
2903 * @return the created ia32 XXX node
2905 #define GEN_LOWERED_OP(op) \
2906 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2907 ir_mode *mode = get_irn_mode(node); \
2908 if (mode_is_float(mode)) \
2910 return gen_binop(env, node, get_binop_left(node), \
2911 get_binop_right(node), new_rd_ia32_##op); \
2914 #define GEN_LOWERED_x87_OP(op) \
2915 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2917 FORCE_x87(env->cg); \
2918 new_op = gen_binop_float(env, node, get_binop_left(node), \
2919 get_binop_right(node), new_rd_ia32_##op); \
2923 #define GEN_LOWERED_UNOP(op) \
2924 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2925 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
2928 #define GEN_LOWERED_SHIFT_OP(op) \
2929 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2930 return gen_shift_binop(env, node, get_binop_left(node), \
2931 get_binop_right(node), new_rd_ia32_##op); \
2934 #define GEN_LOWERED_LOAD(op, fp_unit) \
2935 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2936 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
2939 #define GEN_LOWERED_STORE(op, fp_unit) \
2940 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2941 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
2948 GEN_LOWERED_OP(IMul)
2950 GEN_LOWERED_x87_OP(vfprem)
2951 GEN_LOWERED_x87_OP(vfmul)
2952 GEN_LOWERED_x87_OP(vfsub)
2954 GEN_LOWERED_UNOP(Neg)
2956 GEN_LOWERED_LOAD(vfild, fp_x87)
2957 GEN_LOWERED_LOAD(Load, fp_none)
2958 GEN_LOWERED_STORE(vfist, fp_x87)
2959 GEN_LOWERED_STORE(Store, fp_none)
2961 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
2962 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2963 ir_graph *irg = env->irg;
2964 dbg_info *dbg = get_irn_dbg_info(node);
2965 ir_node *block = transform_node(env, get_nodes_block(node));
2966 ir_node *left = get_binop_left(node);
2967 ir_node *right = get_binop_right(node);
2968 ir_node *new_left = transform_node(env, left);
2969 ir_node *new_right = transform_node(env, right);
2972 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
2973 clear_ia32_commutative(vfdiv);
2974 set_ia32_am_support(vfdiv, ia32_am_Source);
2975 fold_immediate(env, vfdiv, 2, 3);
2977 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
2985 * Transforms a l_MulS into a "real" MulS node.
2987 * @param env The transformation environment
2988 * @return the created ia32 Mul node
2990 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
2991 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2992 ir_graph *irg = env->irg;
2993 dbg_info *dbg = get_irn_dbg_info(node);
2994 ir_node *block = transform_node(env, get_nodes_block(node));
2995 ir_node *left = get_binop_left(node);
2996 ir_node *right = get_binop_right(node);
2997 ir_node *new_left = transform_node(env, left);
2998 ir_node *new_right = transform_node(env, right);
3001 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3002 /* and then skip the result Proj, because all needed Projs are already there. */
3003 ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3004 clear_ia32_commutative(muls);
3005 set_ia32_am_support(muls, ia32_am_Source);
3006 fold_immediate(env, muls, 2, 3);
3008 /* check if EAX and EDX proj exist, add missing one */
3009 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3010 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3011 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3013 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3018 GEN_LOWERED_SHIFT_OP(Shl)
3019 GEN_LOWERED_SHIFT_OP(Shr)
3020 GEN_LOWERED_SHIFT_OP(Sar)
3023 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3024 * op1 - target to be shifted
3025 * op2 - contains bits to be shifted into target
3027 * Only op3 can be an immediate.
3029 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3030 ir_node *op1, ir_node *op2,
3032 ir_node *new_op = NULL;
3033 ir_graph *irg = env->irg;
3034 ir_mode *mode = get_irn_mode(node);
3035 dbg_info *dbg = get_irn_dbg_info(node);
3036 ir_node *block = transform_node(env, get_nodes_block(node));
3037 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3038 ir_node *nomem = new_NoMem();
3040 ir_node *new_op1 = transform_node(env, op1);
3041 ir_node *new_op2 = transform_node(env, op2);
3042 ir_node *new_count = transform_node(env, count);
3044 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3046 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
3048 /* Check if immediate optimization is on and */
3049 /* if it's an operation with immediate. */
3050 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3052 /* Limit imm_op within range imm8 */
3054 tv = get_ia32_Immop_tarval(imm_op);
3057 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3058 set_ia32_Immop_tarval(imm_op, tv);
3065 /* integer operations */
3067 /* This is ShiftD with const */
3068 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3070 if (is_ia32_l_ShlD(node))
3071 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3072 new_op1, new_op2, noreg, nomem);
3074 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3075 new_op1, new_op2, noreg, nomem);
3076 copy_ia32_Immop_attr(new_op, imm_op);
3079 /* This is a normal ShiftD */
3080 DB((mod, LEVEL_1, "ShiftD binop ..."));
3081 if (is_ia32_l_ShlD(node))
3082 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3083 new_op1, new_op2, new_count, nomem);
3085 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3086 new_op1, new_op2, new_count, nomem);
3089 /* set AM support */
3090 // Matze: node has unsupported format (6inputs)
3091 //set_ia32_am_support(new_op, ia32_am_Dest);
3093 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3095 set_ia32_emit_cl(new_op);
3100 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3101 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3102 get_irn_n(node, 1), get_irn_n(node, 2));
3105 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3106 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3107 get_irn_n(node, 1), get_irn_n(node, 2));
3111 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3113 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3114 ia32_code_gen_t *cg = env->cg;
3115 ir_node *res = NULL;
3116 ir_graph *irg = env->irg;
3117 dbg_info *dbg = get_irn_dbg_info(node);
3118 ir_node *block = transform_node(env, get_nodes_block(node));
3119 ir_node *ptr = get_irn_n(node, 0);
3120 ir_node *val = get_irn_n(node, 1);
3121 ir_node *new_val = transform_node(env, val);
3122 ir_node *mem = get_irn_n(node, 2);
3123 ir_node *noreg, *new_ptr, *new_mem;
3129 noreg = ia32_new_NoReg_gp(cg);
3130 new_mem = transform_node(env, mem);
3131 new_ptr = transform_node(env, ptr);
3133 /* Store x87 -> MEM */
3134 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3135 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3136 set_ia32_use_frame(res);
3137 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3138 set_ia32_am_support(res, ia32_am_Dest);
3139 set_ia32_am_flavour(res, ia32_B);
3140 set_ia32_op_type(res, ia32_AddrModeD);
3142 /* Load MEM -> SSE */
3143 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3144 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3145 set_ia32_use_frame(res);
3146 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3147 set_ia32_am_support(res, ia32_am_Source);
3148 set_ia32_am_flavour(res, ia32_B);
3149 set_ia32_op_type(res, ia32_AddrModeS);
3150 res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
3156 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3158 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3159 ia32_code_gen_t *cg = env->cg;
3160 ir_graph *irg = env->irg;
3161 dbg_info *dbg = get_irn_dbg_info(node);
3162 ir_node *block = transform_node(env, get_nodes_block(node));
3163 ir_node *res = NULL;
3164 ir_node *ptr = get_irn_n(node, 0);
3165 ir_node *val = get_irn_n(node, 1);
3166 ir_node *mem = get_irn_n(node, 2);
3167 ir_entity *fent = get_ia32_frame_ent(node);
3168 ir_mode *lsmode = get_ia32_ls_mode(node);
3169 ir_node *new_val = transform_node(env, val);
3170 ir_node *noreg, *new_ptr, *new_mem;
3173 if (!USE_SSE2(cg)) {
3174 /* SSE unit is not used -> skip this node. */
3178 noreg = ia32_new_NoReg_gp(cg);
3179 new_val = transform_node(env, val);
3180 new_ptr = transform_node(env, ptr);
3181 new_mem = transform_node(env, mem);
3183 /* Store SSE -> MEM */
3184 if (is_ia32_xLoad(skip_Proj(new_val))) {
3185 ir_node *ld = skip_Proj(new_val);
3187 /* we can vfld the value directly into the fpu */
3188 fent = get_ia32_frame_ent(ld);
3189 ptr = get_irn_n(ld, 0);
3190 offs = get_ia32_am_offs_int(ld);
3192 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3193 set_ia32_frame_ent(res, fent);
3194 set_ia32_use_frame(res);
3195 set_ia32_ls_mode(res, lsmode);
3196 set_ia32_am_support(res, ia32_am_Dest);
3197 set_ia32_am_flavour(res, ia32_B);
3198 set_ia32_op_type(res, ia32_AddrModeD);
3202 /* Load MEM -> x87 */
3203 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3204 set_ia32_frame_ent(res, fent);
3205 set_ia32_use_frame(res);
3206 set_ia32_ls_mode(res, lsmode);
3207 add_ia32_am_offs_int(res, offs);
3208 set_ia32_am_support(res, ia32_am_Source);
3209 set_ia32_am_flavour(res, ia32_B);
3210 set_ia32_op_type(res, ia32_AddrModeS);
3211 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3216 /*********************************************************
3219 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3220 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3221 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3222 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3224 *********************************************************/
3227 * the BAD transformer.
3229 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3230 panic("No transform function for %+F available.\n", node);
3234 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3235 /* end has to be duplicated manually because we need a dynamic in array */
3236 ir_graph *irg = env->irg;
3237 dbg_info *dbg = get_irn_dbg_info(node);
3238 ir_node *block = transform_node(env, get_nodes_block(node));
3242 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3243 copy_node_attr(node, new_end);
3244 duplicate_deps(env, node, new_end);
3246 set_irg_end(irg, new_end);
3247 set_new_node(new_end, new_end);
3249 /* transform preds */
3250 arity = get_irn_arity(node);
3251 for(i = 0; i < arity; ++i) {
3252 ir_node *in = get_irn_n(node, i);
3253 ir_node *new_in = transform_node(env, in);
3255 add_End_keepalive(new_end, new_in);
3261 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3262 ir_graph *irg = env->irg;
3263 dbg_info *dbg = get_irn_dbg_info(node);
3264 ir_node *start_block = env->old_anchors[anchor_start_block];
3269 * We replace the ProjX from the start node with a jump,
3270 * so the startblock has no preds anymore now
3272 if(node == start_block) {
3273 return new_rd_Block(dbg, irg, 0, NULL);
3276 /* we use the old blocks for now, because jumps allow cycles in the graph
3277 * we have to fix this later */
3278 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3279 get_irn_arity(node), get_irn_in(node) + 1);
3280 copy_node_attr(node, block);
3282 #ifdef DEBUG_libfirm
3283 block->node_nr = node->node_nr;
3285 set_new_node(node, block);
3287 /* put the preds in the worklist */
3288 arity = get_irn_arity(node);
3289 for(i = 0; i < arity; ++i) {
3290 ir_node *in = get_irn_n(node, i);
3291 pdeq_putr(env->worklist, in);
3297 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3298 ir_graph *irg = env->irg;
3299 ir_node *block = transform_node(env, get_nodes_block(node));
3300 dbg_info *dbg = get_irn_dbg_info(node);
3301 ir_node *pred = get_Proj_pred(node);
3302 ir_node *new_pred = transform_node(env, pred);
3303 long proj = get_Proj_proj(node);
3305 if(proj == pn_be_AddSP_res) {
3306 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3307 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3309 } else if(proj == pn_be_AddSP_M) {
3310 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3314 return new_rd_Unknown(irg, get_irn_mode(node));
3317 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3318 ir_graph *irg = env->irg;
3319 ir_node *block = transform_node(env, get_nodes_block(node));
3320 dbg_info *dbg = get_irn_dbg_info(node);
3321 ir_node *pred = get_Proj_pred(node);
3322 ir_node *new_pred = transform_node(env, pred);
3323 long proj = get_Proj_proj(node);
3325 if(proj == pn_be_SubSP_res) {
3326 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3327 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3329 } else if(proj == pn_be_SubSP_M) {
3330 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3334 return new_rd_Unknown(irg, get_irn_mode(node));
3337 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3338 ir_graph *irg = env->irg;
3339 ir_node *block = transform_node(env, get_nodes_block(node));
3340 dbg_info *dbg = get_irn_dbg_info(node);
3341 ir_node *pred = get_Proj_pred(node);
3342 ir_node *new_pred = transform_node(env, pred);
3343 long proj = get_Proj_proj(node);
3345 /* renumber the proj */
3346 if(is_ia32_Load(new_pred)) {
3347 if(proj == pn_Load_res) {
3348 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3349 } else if(proj == pn_Load_M) {
3350 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3352 } else if(is_ia32_xLoad(new_pred)) {
3353 if(proj == pn_Load_res) {
3354 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
3355 } else if(proj == pn_Load_M) {
3356 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3358 } else if(is_ia32_vfld(new_pred)) {
3359 if(proj == pn_Load_res) {
3360 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
3361 } else if(proj == pn_Load_M) {
3362 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3367 return new_rd_Unknown(irg, get_irn_mode(node));
3370 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3371 ir_graph *irg = env->irg;
3372 dbg_info *dbg = get_irn_dbg_info(node);
3373 ir_node *block = transform_node(env, get_nodes_block(node));
3374 ir_mode *mode = get_irn_mode(node);
3376 ir_node *pred = get_Proj_pred(node);
3377 ir_node *new_pred = transform_node(env, pred);
3378 long proj = get_Proj_proj(node);
3380 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3382 switch(get_irn_opcode(pred)) {
3386 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3388 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3396 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3398 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3406 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3407 case pn_DivMod_res_div:
3408 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3409 case pn_DivMod_res_mod:
3410 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3420 return new_rd_Unknown(irg, mode);
3423 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3425 ir_graph *irg = env->irg;
3426 dbg_info *dbg = get_irn_dbg_info(node);
3427 ir_node *block = transform_node(env, get_nodes_block(node));
3428 ir_mode *mode = get_irn_mode(node);
3430 ir_node *pred = get_Proj_pred(node);
3431 ir_node *new_pred = transform_node(env, pred);
3432 long proj = get_Proj_proj(node);
3435 case pn_CopyB_M_regular:
3436 if(is_ia32_CopyB_i(new_pred)) {
3437 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3439 } else if(is_ia32_CopyB(new_pred)) {
3440 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3449 return new_rd_Unknown(irg, mode);
3452 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3454 ir_graph *irg = env->irg;
3455 dbg_info *dbg = get_irn_dbg_info(node);
3456 ir_node *block = transform_node(env, get_nodes_block(node));
3457 ir_mode *mode = get_irn_mode(node);
3459 ir_node *pred = get_Proj_pred(node);
3460 ir_node *new_pred = transform_node(env, pred);
3461 long proj = get_Proj_proj(node);
3464 case pn_ia32_l_vfdiv_M:
3465 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3466 case pn_ia32_l_vfdiv_res:
3467 return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
3472 return new_rd_Unknown(irg, mode);
3475 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3477 ir_graph *irg = env->irg;
3478 dbg_info *dbg = get_irn_dbg_info(node);
3479 ir_node *block = transform_node(env, get_nodes_block(node));
3480 ir_mode *mode = get_irn_mode(node);
3482 ir_node *pred = get_Proj_pred(node);
3483 ir_node *new_pred = transform_node(env, pred);
3484 long proj = get_Proj_proj(node);
3488 if(is_ia32_xDiv(new_pred)) {
3489 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3491 } else if(is_ia32_vfdiv(new_pred)) {
3492 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3497 if(is_ia32_xDiv(new_pred)) {
3498 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3500 } else if(is_ia32_vfdiv(new_pred)) {
3501 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3510 return new_rd_Unknown(irg, mode);
3513 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3514 ir_graph *irg = env->irg;
3515 //dbg_info *dbg = get_irn_dbg_info(node);
3516 dbg_info *dbg = NULL;
3517 ir_node *block = transform_node(env, get_nodes_block(node));
3519 ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
3524 static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
3525 ir_graph *irg = env->irg;
3526 dbg_info *dbg = get_irn_dbg_info(node);
3527 long proj = get_Proj_proj(node);
3528 ir_mode *mode = get_irn_mode(node);
3529 ir_node *block = transform_node(env, get_nodes_block(node));
3531 ir_node *call = get_Proj_pred(node);
3532 ir_node *new_call = transform_node(env, call);
3534 /* The following is kinda tricky: If we're using SSE, then we have to
3535 * move the result value of the call in floating point registers to an
3536 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3537 * after the call, we have to make sure to correctly make the
3538 * MemProj and the result Proj use these 2 nodes
3540 if(proj == pn_be_Call_M_regular) {
3541 // get new node for result, are we doing the sse load/store hack?
3542 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3543 ir_node *call_res_new;
3544 ir_node *call_res_pred = NULL;
3546 if(call_res != NULL) {
3547 call_res_new = transform_node(env, call_res);
3548 call_res_pred = get_Proj_pred(call_res_new);
3551 if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
3552 return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3554 assert(is_ia32_xLoad(call_res_pred));
3555 return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3558 if(proj == pn_be_Call_first_res && mode_is_float(mode)
3559 && USE_SSE2(env->cg)) {
3561 ir_node *frame = get_irg_frame(irg);
3562 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3564 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3566 const arch_register_class_t *cls;
3568 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3569 call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3571 /* store st(0) onto stack */
3572 fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem);
3574 set_ia32_ls_mode(fstp, mode);
3575 set_ia32_op_type(fstp, ia32_AddrModeD);
3576 set_ia32_use_frame(fstp);
3577 set_ia32_am_flavour(fstp, ia32_am_B);
3578 set_ia32_am_support(fstp, ia32_am_Dest);
3580 /* load into SSE register */
3581 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp);
3582 set_ia32_ls_mode(sse_load, mode);
3583 set_ia32_op_type(sse_load, ia32_AddrModeS);
3584 set_ia32_use_frame(sse_load);
3585 set_ia32_am_flavour(sse_load, ia32_am_B);
3586 set_ia32_am_support(sse_load, ia32_am_Source);
3588 //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
3589 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
3591 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3593 /* get a Proj representing a caller save register */
3594 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3595 assert(is_Proj(p) && "Proj expected.");
3597 /* user of the the proj is the Keep */
3598 p = get_edge_src_irn(get_irn_out_edge_first(p));
3599 assert(be_is_Keep(p) && "Keep expected.");
3601 /* keep the result */
3602 cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
3603 keepin[0] = sse_load;
3604 be_new_Keep(cls, irg, block, 1, keepin);
3609 /* transform call modes to the mode_Iu or mode_E */
3610 if(mode_is_float(mode)) {
3612 } else if(mode != mode_M) {
3616 return new_rd_Proj(dbg, irg, block, new_call, mode, proj);
3619 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3620 ir_graph *irg = env->irg;
3621 dbg_info *dbg = get_irn_dbg_info(node);
3622 ir_node *pred = get_Proj_pred(node);
3623 long proj = get_Proj_proj(node);
3625 if(is_Store(pred) || be_is_FrameStore(pred)) {
3626 if(proj == pn_Store_M) {
3627 return transform_node(env, pred);
3630 return new_r_Bad(irg);
3632 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3633 return gen_Proj_Load(env, node);
3634 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3635 return gen_Proj_DivMod(env, node);
3636 } else if(is_CopyB(pred)) {
3637 return gen_Proj_CopyB(env, node);
3638 } else if(is_Quot(pred)) {
3639 return gen_Proj_Quot(env, node);
3640 } else if(is_ia32_l_vfdiv(pred)) {
3641 return gen_Proj_l_vfdiv(env, node);
3642 } else if(be_is_SubSP(pred)) {
3643 return gen_Proj_be_SubSP(env, node);
3644 } else if(be_is_AddSP(pred)) {
3645 return gen_Proj_be_AddSP(env, node);
3646 } else if(be_is_Call(pred)) {
3647 return gen_Proj_be_Call(env, node);
3648 } else if(get_irn_op(pred) == op_Start) {
3649 if(proj == pn_Start_X_initial_exec) {
3650 ir_node *block = get_nodes_block(pred);
3653 block = transform_node(env, block);
3654 // we exchange the ProjX with a jump
3655 jump = new_rd_Jmp(dbg, irg, block);
3656 ir_fprintf(stderr, "created jump: %+F\n", jump);
3659 if(node == env->old_anchors[anchor_tls]) {
3660 return gen_Proj_tls(env, node);
3664 return duplicate_node(env, node);
3668 * Enters all transform functions into the generic pointer
3670 static void register_transformers(void) {
3671 ir_op *op_Max, *op_Min, *op_Mulh;
3673 /* first clear the generic function pointer for all ops */
3674 clear_irp_opcodes_generic_func();
3676 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3677 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3716 /* transform ops from intrinsic lowering */
3738 GEN(ia32_l_X87toSSE);
3739 GEN(ia32_l_SSEtoX87);
3744 /* we should never see these nodes */
3759 /* handle generic backend nodes */
3769 /* set the register for all Unknown nodes */
3772 op_Max = get_op_Max();
3775 op_Min = get_op_Min();
3778 op_Mulh = get_op_Mulh();
3786 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3790 int deps = get_irn_deps(old_node);
3792 for(i = 0; i < deps; ++i) {
3793 ir_node *dep = get_irn_dep(old_node, i);
3794 ir_node *new_dep = transform_node(env, dep);
3796 add_irn_dep(new_node, new_dep);
3800 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3802 ir_graph *irg = env->irg;
3803 dbg_info *dbg = get_irn_dbg_info(node);
3804 ir_mode *mode = get_irn_mode(node);
3805 ir_op *op = get_irn_op(node);
3810 block = transform_node(env, get_nodes_block(node));
3812 arity = get_irn_arity(node);
3813 if(op->opar == oparity_dynamic) {
3814 new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL);
3815 for(i = 0; i < arity; ++i) {
3816 ir_node *in = get_irn_n(node, i);
3817 in = transform_node(env, in);
3818 add_irn_n(new_node, in);
3821 ir_node **ins = alloca(arity * sizeof(ins[0]));
3822 for(i = 0; i < arity; ++i) {
3823 ir_node *in = get_irn_n(node, i);
3824 ins[i] = transform_node(env, in);
3827 new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins);
3830 copy_node_attr(node, new_node);
3831 duplicate_deps(env, node, new_node);
3836 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3839 ir_op *op = get_irn_op(node);
3841 if(irn_visited(node)) {
3842 assert(get_new_node(node) != NULL);
3843 return get_new_node(node);
3846 mark_irn_visited(node);
3847 DEBUG_ONLY(set_new_node(node, NULL));
3849 if (op->ops.generic) {
3850 transform_func *transform = (transform_func *)op->ops.generic;
3852 new_node = (*transform)(env, node);
3853 assert(new_node != NULL);
3855 new_node = duplicate_node(env, node);
3857 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3859 set_new_node(node, new_node);
3860 mark_irn_visited(new_node);
3861 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3865 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3869 if(irn_visited(node))
3871 mark_irn_visited(node);
3873 assert(node_is_in_irgs_storage(env->irg, node));
3875 if(!is_Block(node)) {
3876 ir_node *block = get_nodes_block(node);
3877 ir_node *new_block = (ir_node*) get_irn_link(block);
3879 if(new_block != NULL) {
3880 set_nodes_block(node, new_block);
3884 fix_loops(env, block);
3887 arity = get_irn_arity(node);
3888 for(i = 0; i < arity; ++i) {
3889 ir_node *in = get_irn_n(node, i);
3890 ir_node *new = (ir_node*) get_irn_link(in);
3892 if(new != NULL && new != in) {
3893 set_irn_n(node, i, new);
3900 arity = get_irn_deps(node);
3901 for(i = 0; i < arity; ++i) {
3902 ir_node *in = get_irn_dep(node, i);
3903 ir_node *new = (ir_node*) get_irn_link(in);
3905 if(new != NULL && new != in) {
3906 set_irn_dep(node, i, new);
3914 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3919 *place = transform_node(env, *place);
3922 static void transform_nodes(ia32_code_gen_t *cg)
3925 ir_graph *irg = cg->irg;
3927 ia32_transform_env_t env;
3929 hook_dead_node_elim(irg, 1);
3931 inc_irg_visited(irg);
3935 env.visited = get_irg_visited(irg);
3936 env.worklist = new_pdeq();
3937 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3938 DEBUG_ONLY(env.mod = cg->mod);
3940 old_end = get_irg_end(irg);
3942 /* put all anchor nodes in the worklist */
3943 for(i = 0; i < anchor_max; ++i) {
3944 ir_node *anchor = irg->anchors[i];
3947 pdeq_putr(env.worklist, anchor);
3950 env.old_anchors[i] = anchor;
3951 // and set it to NULL to make sure we don't accidently use it
3952 irg->anchors[i] = NULL;
3955 // pre transform some anchors (so they are available in the other transform
3957 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3958 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3959 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3960 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3961 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3963 pre_transform_node(&cg->unknown_gp, &env);
3964 pre_transform_node(&cg->unknown_vfp, &env);
3965 pre_transform_node(&cg->unknown_xmm, &env);
3966 pre_transform_node(&cg->noreg_gp, &env);
3967 pre_transform_node(&cg->noreg_vfp, &env);
3968 pre_transform_node(&cg->noreg_xmm, &env);
3970 /* process worklist (this should transform all nodes in the graph) */
3971 while(!pdeq_empty(env.worklist)) {
3972 ir_node *node = pdeq_getl(env.worklist);
3973 transform_node(&env, node);
3976 /* fix loops and set new anchors*/
3977 inc_irg_visited(irg);
3978 for(i = 0; i < anchor_max; ++i) {
3979 ir_node *anchor = env.old_anchors[i];
3983 anchor = get_irn_link(anchor);
3984 fix_loops(&env, anchor);
3985 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3986 irg->anchors[i] = anchor;
3989 del_pdeq(env.worklist);
3991 hook_dead_node_elim(irg, 0);
3994 void ia32_transform_graph(ia32_code_gen_t *cg)
3996 ir_graph *irg = cg->irg;
3997 be_irg_t *birg = cg->birg;
3998 ir_graph *old_current_ir_graph = current_ir_graph;
3999 int old_interprocedural_view = get_interprocedural_view();
4000 struct obstack *old_obst = NULL;
4001 struct obstack *new_obst = NULL;
4003 current_ir_graph = irg;
4004 set_interprocedural_view(0);
4005 register_transformers();
4007 /* most analysis info is wrong after transformation */
4008 free_callee_info(irg);
4010 irg->outs_state = outs_none;
4012 free_loop_information(irg);
4013 set_irg_doms_inconsistent(irg);
4014 be_invalidate_liveness(birg);
4015 be_invalidate_dom_front(birg);
4017 /* create a new obstack */
4018 old_obst = irg->obst;
4019 new_obst = xmalloc(sizeof(*new_obst));
4020 obstack_init(new_obst);
4021 irg->obst = new_obst;
4022 irg->last_node_idx = 0;
4024 /* create new value table for CSE */
4025 del_identities(irg->value_table);
4026 irg->value_table = new_identities();
4028 /* do the main transformation */
4029 transform_nodes(cg);
4031 /* we don't want the globals anchor anymore */
4032 set_irg_globals(irg, new_r_Bad(irg));
4034 /* free the old obstack */
4035 obstack_free(old_obst, 0);
4039 current_ir_graph = old_current_ir_graph;
4040 set_interprocedural_view(old_interprocedural_view);
4042 /* recalculate edges */
4043 edges_deactivate(irg);
4044 edges_activate(irg);
4048 * Transforms a psi condition.
4050 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4053 /* if the mode is target mode, we have already seen this part of the tree */
4054 if (get_irn_mode(cond) == mode)
4057 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4059 set_irn_mode(cond, mode);
4061 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4062 ir_node *in = get_irn_n(cond, i);
4064 /* if in is a compare: transform into Set/xCmp */
4066 ir_node *new_op = NULL;
4067 ir_node *cmp = get_Proj_pred(in);
4068 ir_node *cmp_a = get_Cmp_left(cmp);
4069 ir_node *cmp_b = get_Cmp_right(cmp);
4070 dbg_info *dbg = get_irn_dbg_info(cmp);
4071 ir_graph *irg = get_irn_irg(cmp);
4072 ir_node *block = get_nodes_block(cmp);
4073 ir_node *noreg = ia32_new_NoReg_gp(cg);
4074 ir_node *nomem = new_rd_NoMem(irg);
4075 int pnc = get_Proj_proj(in);
4077 /* this is a compare */
4078 if (mode_is_float(mode)) {
4079 /* Psi is float, we need a floating point compare */
4082 ir_mode *m = get_irn_mode(cmp_a);
4084 if (! mode_is_float(m)) {
4085 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4086 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4088 else if (m == mode_F) {
4089 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4090 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4091 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4094 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4095 set_ia32_pncode(new_op, pnc);
4096 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4105 construct_binop_func *set_func = NULL;
4107 if (mode_is_float(get_irn_mode(cmp_a))) {
4108 /* 1st case: compare operands are floats */
4113 set_func = new_rd_ia32_xCmpSet;
4117 set_func = new_rd_ia32_vfCmpSet;
4120 pnc &= 7; /* fp compare -> int compare */
4123 /* 2nd case: compare operand are integer too */
4124 set_func = new_rd_ia32_CmpSet;
4127 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4128 if(!mode_is_signed(mode))
4129 pnc |= ia32_pn_Cmp_Unsigned;
4131 set_ia32_pncode(new_op, pnc);
4132 set_ia32_am_support(new_op, ia32_am_Source);
4135 /* the the new compare as in */
4136 set_irn_n(cond, i, new_op);
4139 /* another complex condition */
4140 transform_psi_cond(in, mode, cg);
4146 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4147 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4148 * compare, which causes the compare result to be stores in a register. The
4149 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4151 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4152 ia32_code_gen_t *cg = env;
4153 ir_node *psi_sel, *new_cmp, *block;
4158 if (get_irn_opcode(node) != iro_Psi)
4161 psi_sel = get_Psi_cond(node, 0);
4163 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4164 if (is_Proj(psi_sel))
4167 //mode = get_irn_mode(node);
4168 // TODO this is probably wrong...
4171 transform_psi_cond(psi_sel, mode, cg);
4173 irg = get_irn_irg(node);
4174 block = get_nodes_block(node);
4176 /* we need to compare the evaluated condition tree with 0 */
4177 mode = get_irn_mode(node);
4178 if (mode_is_float(mode)) {
4179 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4180 /* BEWARE: new_r_Const_long works for floating point as well */
4181 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4182 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4185 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4186 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4189 set_Psi_cond(node, 0, new_cmp);