2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
102 /****************************************************************************************************
104 * | | | | / _| | | (_)
105 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
106 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
107 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
108 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
110 ****************************************************************************************************/
112 static ir_node *try_create_Immediate(ir_node *node,
113 char immediate_constraint_type);
116 * Return true if a mode can be stored in the GP register set
118 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
119 if(mode == mode_fpcw)
121 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
125 * Returns 1 if irn is a Const representing 0, 0 otherwise
127 static INLINE int is_ia32_Const_0(ir_node *irn) {
128 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
129 && tarval_is_null(get_ia32_Immop_tarval(irn));
133 * Returns 1 if irn is a Const representing 1, 0 otherwise
135 static INLINE int is_ia32_Const_1(ir_node *irn) {
136 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
137 && tarval_is_one(get_ia32_Immop_tarval(irn));
141 * Collects all Projs of a node into the node array. Index is the projnum.
142 * BEWARE: The caller has to assure the appropriate array size!
144 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
145 const ir_edge_t *edge;
146 assert(get_irn_mode(irn) == mode_T && "need mode_T");
148 memset(projs, 0, size * sizeof(projs[0]));
150 foreach_out_edge(irn, edge) {
151 ir_node *proj = get_edge_src_irn(edge);
152 int proj_proj = get_Proj_proj(proj);
153 assert(proj_proj < size);
154 projs[proj_proj] = proj;
159 * Renumbers the proj having pn_old in the array tp pn_new
160 * and removes the proj from the array.
162 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
163 fprintf(stderr, "Warning: renumber_Proj used!\n");
165 set_Proj_proj(projs[pn_old], pn_new);
166 projs[pn_old] = NULL;
171 * creates a unique ident by adding a number to a tag
173 * @param tag the tag string, must contain a %d if a number
176 static ident *unique_id(const char *tag)
178 static unsigned id = 0;
181 snprintf(str, sizeof(str), tag, ++id);
182 return new_id_from_str(str);
186 * Get a primitive type for a mode.
188 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
190 pmap_entry *e = pmap_find(types, mode);
195 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
196 res = new_type_primitive(new_id_from_str(buf), mode);
197 pmap_insert(types, mode, res);
205 * Get an entity that is initialized with a tarval
207 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
209 tarval *tv = get_Const_tarval(cnst);
210 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
215 ir_mode *mode = get_irn_mode(cnst);
216 ir_type *tp = get_Const_type(cnst);
217 if (tp == firm_unknown_type)
218 tp = get_prim_type(cg->isa->types, mode);
220 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
222 set_entity_ld_ident(res, get_entity_ident(res));
223 set_entity_visibility(res, visibility_local);
224 set_entity_variability(res, variability_constant);
225 set_entity_allocation(res, allocation_static);
227 /* we create a new entity here: It's initialization must resist on the
229 rem = current_ir_graph;
230 current_ir_graph = get_const_code_irg();
231 set_atomic_ent_value(res, new_Const_type(tv, tp));
232 current_ir_graph = rem;
234 pmap_insert(cg->isa->tv_ent, tv, res);
242 static int is_Const_0(ir_node *node) {
246 return classify_Const(node) == CNST_NULL;
249 static int is_Const_1(ir_node *node) {
253 return classify_Const(node) == CNST_ONE;
257 * Transforms a Const.
259 static ir_node *gen_Const(ir_node *node) {
260 ir_graph *irg = current_ir_graph;
261 ir_node *block = be_transform_node(get_nodes_block(node));
262 dbg_info *dbgi = get_irn_dbg_info(node);
263 ir_mode *mode = get_irn_mode(node);
265 if (mode_is_float(mode)) {
267 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
268 ir_node *nomem = new_NoMem();
273 if (! USE_SSE2(env_cg)) {
274 cnst_classify_t clss = classify_Const(node);
276 if (clss == CNST_NULL) {
277 load = new_rd_ia32_vfldz(dbgi, irg, block);
279 } else if (clss == CNST_ONE) {
280 load = new_rd_ia32_vfld1(dbgi, irg, block);
283 floatent = get_entity_for_tv(env_cg, node);
285 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
286 set_ia32_am_support(load, ia32_am_Source);
287 set_ia32_op_type(load, ia32_AddrModeS);
288 set_ia32_am_flavour(load, ia32_am_N);
289 set_ia32_am_sc(load, floatent);
290 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
292 set_ia32_ls_mode(load, mode);
294 floatent = get_entity_for_tv(env_cg, node);
296 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
297 set_ia32_am_support(load, ia32_am_Source);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 set_ia32_ls_mode(load, mode);
303 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
306 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
308 /* Const Nodes before the initial IncSP are a bad idea, because
309 * they could be spilled and we have no SP ready at that point yet.
310 * So add a dependency to the initial frame pointer calculation to
311 * avoid that situation.
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(load, get_irg_frame(irg));
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
327 set_ia32_Const_attr(cnst, node);
328 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
333 return new_r_Bad(irg);
337 * Transforms a SymConst.
339 static ir_node *gen_SymConst(ir_node *node) {
340 ir_graph *irg = current_ir_graph;
341 ir_node *block = be_transform_node(get_nodes_block(node));
342 dbg_info *dbgi = get_irn_dbg_info(node);
343 ir_mode *mode = get_irn_mode(node);
346 if (mode_is_float(mode)) {
348 if (USE_SSE2(env_cg))
349 cnst = new_rd_ia32_xConst(dbgi, irg, block);
351 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
352 set_ia32_ls_mode(cnst, mode);
354 cnst = new_rd_ia32_Const(dbgi, irg, block);
357 /* Const Nodes before the initial IncSP are a bad idea, because
358 * they could be spilled and we have no SP ready at that point yet
360 if (get_irg_start_block(irg) == block) {
361 add_irn_dep(cnst, get_irg_frame(irg));
364 set_ia32_Const_attr(cnst, node);
365 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
372 * SSE convert of an integer node into a floating point node.
374 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
375 ir_graph *irg, ir_node *block,
376 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
378 ir_node *noreg = ia32_new_NoReg_gp(cg);
379 ir_node *nomem = new_rd_NoMem(irg);
380 ir_node *old_pred = get_Cmp_left(old_node);
381 ir_mode *in_mode = get_irn_mode(old_pred);
382 int in_bits = get_mode_size_bits(in_mode);
383 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
385 set_ia32_ls_mode(conv, tgt_mode);
387 set_ia32_am_support(conv, ia32_am_Source);
389 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
395 * SSE convert of an float node into a double node.
397 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
398 ir_graph *irg, ir_node *block,
399 ir_node *in, ir_node *old_node)
401 ir_node *noreg = ia32_new_NoReg_gp(cg);
402 ir_node *nomem = new_rd_NoMem(irg);
403 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
405 set_ia32_am_support(conv, ia32_am_Source);
406 set_ia32_ls_mode(conv, mode_xmm);
407 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
413 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
414 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
415 static const struct {
417 const char *ent_name;
418 const char *cnst_str;
419 } names [ia32_known_const_max] = {
420 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
421 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
422 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
423 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
425 static ir_entity *ent_cache[ia32_known_const_max];
427 const char *tp_name, *ent_name, *cnst_str;
435 ent_name = names[kct].ent_name;
436 if (! ent_cache[kct]) {
437 tp_name = names[kct].tp_name;
438 cnst_str = names[kct].cnst_str;
440 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
442 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
443 tp = new_type_primitive(new_id_from_str(tp_name), mode);
444 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
446 set_entity_ld_ident(ent, get_entity_ident(ent));
447 set_entity_visibility(ent, visibility_local);
448 set_entity_variability(ent, variability_constant);
449 set_entity_allocation(ent, allocation_static);
451 /* we create a new entity here: It's initialization must resist on the
453 rem = current_ir_graph;
454 current_ir_graph = get_const_code_irg();
455 cnst = new_Const(mode, tv);
456 current_ir_graph = rem;
458 set_atomic_ent_value(ent, cnst);
460 /* cache the entry */
461 ent_cache[kct] = ent;
464 return ent_cache[kct];
469 * Prints the old node name on cg obst and returns a pointer to it.
471 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
472 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
474 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
475 obstack_1grow(isa->name_obst, 0);
476 return obstack_finish(isa->name_obst);
480 /* determine if one operator is an Imm */
481 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
483 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
485 return is_ia32_Cnst(op2) ? op2 : NULL;
489 /* determine if one operator is not an Imm */
490 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
491 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
494 static void fold_immediate(ir_node *node, int in1, int in2) {
498 if (!(env_cg->opt & IA32_OPT_IMMOPS))
501 left = get_irn_n(node, in1);
502 right = get_irn_n(node, in2);
503 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
504 /* we can only set right operand to immediate */
505 if(!is_ia32_commutative(node))
507 /* exchange left/right */
508 set_irn_n(node, in1, right);
509 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
510 copy_ia32_Immop_attr(node, left);
511 } else if(is_ia32_Cnst(right)) {
512 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
513 copy_ia32_Immop_attr(node, right);
518 clear_ia32_commutative(node);
519 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
523 * Construct a standard binary operation, set AM and immediate if required.
525 * @param op1 The first operand
526 * @param op2 The second operand
527 * @param func The node constructor function
528 * @return The constructed ia32 node.
530 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
531 construct_binop_func *func, int commutative)
533 ir_node *block = be_transform_node(get_nodes_block(node));
534 ir_node *new_op1 = NULL;
535 ir_node *new_op2 = NULL;
536 ir_node *new_node = NULL;
537 ir_graph *irg = current_ir_graph;
538 dbg_info *dbgi = get_irn_dbg_info(node);
539 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
540 ir_node *nomem = new_NoMem();
543 new_op2 = try_create_Immediate(op1, 0);
544 if(new_op2 != NULL) {
545 new_op1 = be_transform_node(op2);
550 if(new_op2 == NULL) {
551 new_op2 = try_create_Immediate(op2, 0);
552 if(new_op2 != NULL) {
553 new_op1 = be_transform_node(op1);
558 if(new_op2 == NULL) {
559 new_op1 = be_transform_node(op1);
560 new_op2 = be_transform_node(op2);
563 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
564 if (func == new_rd_ia32_IMul) {
565 set_ia32_am_support(new_node, ia32_am_Source);
567 set_ia32_am_support(new_node, ia32_am_Full);
570 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
572 set_ia32_commutative(new_node);
579 * Construct a standard binary operation, set AM and immediate if required.
581 * @param op1 The first operand
582 * @param op2 The second operand
583 * @param func The node constructor function
584 * @return The constructed ia32 node.
586 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
587 construct_binop_func *func)
589 ir_node *block = be_transform_node(get_nodes_block(node));
590 ir_node *new_op1 = be_transform_node(op1);
591 ir_node *new_op2 = be_transform_node(op2);
592 ir_node *new_node = NULL;
593 dbg_info *dbgi = get_irn_dbg_info(node);
594 ir_graph *irg = current_ir_graph;
595 ir_mode *mode = get_irn_mode(node);
596 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_node *nomem = new_NoMem();
599 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
600 set_ia32_am_support(new_node, ia32_am_Source);
601 if (is_op_commutative(get_irn_op(node))) {
602 set_ia32_commutative(new_node);
604 if (USE_SSE2(env_cg)) {
605 set_ia32_ls_mode(new_node, mode);
608 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
615 * Construct a shift/rotate binary operation, sets AM and immediate if required.
617 * @param op1 The first operand
618 * @param op2 The second operand
619 * @param func The node constructor function
620 * @return The constructed ia32 node.
622 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
623 construct_binop_func *func)
625 ir_node *block = be_transform_node(get_nodes_block(node));
626 ir_node *new_op1 = be_transform_node(op1);
627 ir_node *new_op2 = be_transform_node(op2);
628 ir_node *new_op = NULL;
629 dbg_info *dbgi = get_irn_dbg_info(node);
630 ir_graph *irg = current_ir_graph;
631 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
632 ir_node *nomem = new_NoMem();
637 assert(! mode_is_float(get_irn_mode(node))
638 && "Shift/Rotate with float not supported");
640 /* Check if immediate optimization is on and */
641 /* if it's an operation with immediate. */
642 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
643 expr_op = get_expr_op(new_op1, new_op2);
645 assert((expr_op || imm_op) && "invalid operands");
648 /* We have two consts here: not yet supported */
652 /* Limit imm_op within range imm8 */
654 tv = get_ia32_Immop_tarval(imm_op);
657 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
658 set_ia32_Immop_tarval(imm_op, tv);
665 /* integer operations */
667 /* This is shift/rot with const */
668 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
670 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
671 copy_ia32_Immop_attr(new_op, imm_op);
673 /* This is a normal shift/rot */
674 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
675 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
679 set_ia32_am_support(new_op, ia32_am_Dest);
681 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
683 set_ia32_emit_cl(new_op);
690 * Construct a standard unary operation, set AM and immediate if required.
692 * @param op The operand
693 * @param func The node constructor function
694 * @return The constructed ia32 node.
696 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
698 ir_node *block = be_transform_node(get_nodes_block(node));
699 ir_node *new_op = be_transform_node(op);
700 ir_node *new_node = NULL;
701 ir_graph *irg = current_ir_graph;
702 dbg_info *dbgi = get_irn_dbg_info(node);
703 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
704 ir_node *nomem = new_NoMem();
706 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
707 DB((dbg, LEVEL_1, "INT unop ..."));
708 set_ia32_am_support(new_node, ia32_am_Dest);
710 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
716 * Creates an ia32 Add.
718 * @return the created ia32 Add node
720 static ir_node *gen_Add(ir_node *node) {
721 ir_node *block = be_transform_node(get_nodes_block(node));
722 ir_node *op1 = get_Add_left(node);
723 ir_node *new_op1 = be_transform_node(op1);
724 ir_node *op2 = get_Add_right(node);
725 ir_node *new_op2 = be_transform_node(op2);
726 ir_node *new_op = NULL;
727 ir_graph *irg = current_ir_graph;
728 dbg_info *dbgi = get_irn_dbg_info(node);
729 ir_mode *mode = get_irn_mode(node);
730 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
731 ir_node *nomem = new_NoMem();
732 ir_node *expr_op, *imm_op;
734 /* Check if immediate optimization is on and */
735 /* if it's an operation with immediate. */
736 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
737 expr_op = get_expr_op(new_op1, new_op2);
739 assert((expr_op || imm_op) && "invalid operands");
741 if (mode_is_float(mode)) {
743 if (USE_SSE2(env_cg))
744 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
746 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
751 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
752 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
754 /* No expr_op means, that we have two const - one symconst and */
755 /* one tarval or another symconst - because this case is not */
756 /* covered by constant folding */
757 /* We need to check for: */
758 /* 1) symconst + const -> becomes a LEA */
759 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
760 /* linker doesn't support two symconsts */
762 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
763 /* this is the 2nd case */
764 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
765 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
766 set_ia32_am_flavour(new_op, ia32_am_B);
767 set_ia32_am_support(new_op, ia32_am_Source);
768 set_ia32_op_type(new_op, ia32_AddrModeS);
770 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
771 } else if (tp1 == ia32_ImmSymConst) {
772 tarval *tv = get_ia32_Immop_tarval(new_op2);
773 long offs = get_tarval_long(tv);
775 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
776 add_irn_dep(new_op, get_irg_frame(irg));
777 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
779 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
780 add_ia32_am_offs_int(new_op, offs);
781 set_ia32_am_flavour(new_op, ia32_am_OB);
782 set_ia32_am_support(new_op, ia32_am_Source);
783 set_ia32_op_type(new_op, ia32_AddrModeS);
784 } else if (tp2 == ia32_ImmSymConst) {
785 tarval *tv = get_ia32_Immop_tarval(new_op1);
786 long offs = get_tarval_long(tv);
788 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
789 add_irn_dep(new_op, get_irg_frame(irg));
790 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
792 add_ia32_am_offs_int(new_op, offs);
793 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
794 set_ia32_am_flavour(new_op, ia32_am_OB);
795 set_ia32_am_support(new_op, ia32_am_Source);
796 set_ia32_op_type(new_op, ia32_AddrModeS);
798 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
799 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
800 tarval *restv = tarval_add(tv1, tv2);
802 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
804 new_op = new_rd_ia32_Const(dbgi, irg, block);
805 set_ia32_Const_tarval(new_op, restv);
806 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
809 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
812 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
813 tarval_classification_t class_tv, class_negtv;
814 tarval *tv = get_ia32_Immop_tarval(imm_op);
816 /* optimize tarvals */
817 class_tv = classify_tarval(tv);
818 class_negtv = classify_tarval(tarval_neg(tv));
820 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
821 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
822 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
823 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
825 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
826 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
827 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
828 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
834 /* This is a normal add */
835 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
838 set_ia32_am_support(new_op, ia32_am_Full);
839 set_ia32_commutative(new_op);
841 fold_immediate(new_op, 2, 3);
843 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
849 static ir_node *create_ia32_Mul(ir_node *node) {
850 ir_graph *irg = current_ir_graph;
851 dbg_info *dbgi = get_irn_dbg_info(node);
852 ir_node *block = be_transform_node(get_nodes_block(node));
853 ir_node *op1 = get_Mul_left(node);
854 ir_node *op2 = get_Mul_right(node);
855 ir_node *new_op1 = be_transform_node(op1);
856 ir_node *new_op2 = be_transform_node(op2);
857 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
858 ir_node *proj_EAX, *proj_EDX, *res;
861 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
862 set_ia32_commutative(res);
863 set_ia32_am_support(res, ia32_am_Source);
865 /* imediates are not supported, so no fold_immediate */
866 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
867 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
871 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
879 * Creates an ia32 Mul.
881 * @return the created ia32 Mul node
883 static ir_node *gen_Mul(ir_node *node) {
884 ir_node *op1 = get_Mul_left(node);
885 ir_node *op2 = get_Mul_right(node);
886 ir_mode *mode = get_irn_mode(node);
888 if (mode_is_float(mode)) {
890 if (USE_SSE2(env_cg))
891 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
893 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
897 for the lower 32bit of the result it doesn't matter whether we use
898 signed or unsigned multiplication so we use IMul as it has fewer
901 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
905 * Creates an ia32 Mulh.
906 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
907 * this result while Mul returns the lower 32 bit.
909 * @return the created ia32 Mulh node
911 static ir_node *gen_Mulh(ir_node *node) {
912 ir_node *block = be_transform_node(get_nodes_block(node));
913 ir_node *op1 = get_irn_n(node, 0);
914 ir_node *new_op1 = be_transform_node(op1);
915 ir_node *op2 = get_irn_n(node, 1);
916 ir_node *new_op2 = be_transform_node(op2);
917 ir_graph *irg = current_ir_graph;
918 dbg_info *dbgi = get_irn_dbg_info(node);
919 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
920 ir_mode *mode = get_irn_mode(node);
921 ir_node *proj_EAX, *proj_EDX, *res;
924 assert(!mode_is_float(mode) && "Mulh with float not supported");
925 if (mode_is_signed(mode)) {
926 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
928 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
931 set_ia32_commutative(res);
932 set_ia32_am_support(res, ia32_am_Source);
934 set_ia32_am_support(res, ia32_am_Source);
936 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
937 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
941 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
949 * Creates an ia32 And.
951 * @return The created ia32 And node
953 static ir_node *gen_And(ir_node *node) {
954 ir_node *op1 = get_And_left(node);
955 ir_node *op2 = get_And_right(node);
957 assert (! mode_is_float(get_irn_mode(node)));
958 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
964 * Creates an ia32 Or.
966 * @return The created ia32 Or node
968 static ir_node *gen_Or(ir_node *node) {
969 ir_node *op1 = get_Or_left(node);
970 ir_node *op2 = get_Or_right(node);
972 assert (! mode_is_float(get_irn_mode(node)));
973 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
979 * Creates an ia32 Eor.
981 * @return The created ia32 Eor node
983 static ir_node *gen_Eor(ir_node *node) {
984 ir_node *op1 = get_Eor_left(node);
985 ir_node *op2 = get_Eor_right(node);
987 assert(! mode_is_float(get_irn_mode(node)));
988 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
994 * Creates an ia32 Max.
996 * @return the created ia32 Max node
998 static ir_node *gen_Max(ir_node *node) {
999 ir_node *block = be_transform_node(get_nodes_block(node));
1000 ir_node *op1 = get_irn_n(node, 0);
1001 ir_node *new_op1 = be_transform_node(op1);
1002 ir_node *op2 = get_irn_n(node, 1);
1003 ir_node *new_op2 = be_transform_node(op2);
1004 ir_graph *irg = current_ir_graph;
1005 ir_mode *mode = get_irn_mode(node);
1006 dbg_info *dbgi = get_irn_dbg_info(node);
1007 ir_mode *op_mode = get_irn_mode(op1);
1010 assert(get_mode_size_bits(mode) == 32);
1012 if (mode_is_float(mode)) {
1014 if (USE_SSE2(env_cg)) {
1015 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1017 panic("Can't create Max node");
1020 long pnc = pn_Cmp_Gt;
1021 if (! mode_is_signed(op_mode)) {
1022 pnc |= ia32_pn_Cmp_Unsigned;
1024 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1025 new_op1, new_op2, pnc);
1027 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1033 * Creates an ia32 Min.
1035 * @return the created ia32 Min node
1037 static ir_node *gen_Min(ir_node *node) {
1038 ir_node *block = be_transform_node(get_nodes_block(node));
1039 ir_node *op1 = get_irn_n(node, 0);
1040 ir_node *new_op1 = be_transform_node(op1);
1041 ir_node *op2 = get_irn_n(node, 1);
1042 ir_node *new_op2 = be_transform_node(op2);
1043 ir_graph *irg = current_ir_graph;
1044 ir_mode *mode = get_irn_mode(node);
1045 dbg_info *dbgi = get_irn_dbg_info(node);
1046 ir_mode *op_mode = get_irn_mode(op1);
1049 assert(get_mode_size_bits(mode) == 32);
1051 if (mode_is_float(mode)) {
1053 if (USE_SSE2(env_cg)) {
1054 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1056 panic("can't create Min node");
1059 long pnc = pn_Cmp_Lt;
1060 if (! mode_is_signed(op_mode)) {
1061 pnc |= ia32_pn_Cmp_Unsigned;
1063 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1064 new_op1, new_op2, pnc);
1066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1073 * Creates an ia32 Sub.
1075 * @return The created ia32 Sub node
1077 static ir_node *gen_Sub(ir_node *node) {
1078 ir_node *block = be_transform_node(get_nodes_block(node));
1079 ir_node *op1 = get_Sub_left(node);
1080 ir_node *new_op1 = be_transform_node(op1);
1081 ir_node *op2 = get_Sub_right(node);
1082 ir_node *new_op2 = be_transform_node(op2);
1083 ir_node *new_op = NULL;
1084 ir_graph *irg = current_ir_graph;
1085 dbg_info *dbgi = get_irn_dbg_info(node);
1086 ir_mode *mode = get_irn_mode(node);
1087 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1088 ir_node *nomem = new_NoMem();
1089 ir_node *expr_op, *imm_op;
1091 /* Check if immediate optimization is on and */
1092 /* if it's an operation with immediate. */
1093 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1094 expr_op = get_expr_op(new_op1, new_op2);
1096 assert((expr_op || imm_op) && "invalid operands");
1098 if (mode_is_float(mode)) {
1100 if (USE_SSE2(env_cg))
1101 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1103 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1108 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1109 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1111 /* No expr_op means, that we have two const - one symconst and */
1112 /* one tarval or another symconst - because this case is not */
1113 /* covered by constant folding */
1114 /* We need to check for: */
1115 /* 1) symconst - const -> becomes a LEA */
1116 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1117 /* linker doesn't support two symconsts */
1118 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1119 /* this is the 2nd case */
1120 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1121 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1122 set_ia32_am_sc_sign(new_op);
1123 set_ia32_am_flavour(new_op, ia32_am_B);
1125 DBG_OPT_LEA3(op1, op2, node, new_op);
1126 } else if (tp1 == ia32_ImmSymConst) {
1127 tarval *tv = get_ia32_Immop_tarval(new_op2);
1128 long offs = get_tarval_long(tv);
1130 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1131 add_irn_dep(new_op, get_irg_frame(irg));
1132 DBG_OPT_LEA3(op1, op2, node, new_op);
1134 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1135 add_ia32_am_offs_int(new_op, -offs);
1136 set_ia32_am_flavour(new_op, ia32_am_OB);
1137 set_ia32_am_support(new_op, ia32_am_Source);
1138 set_ia32_op_type(new_op, ia32_AddrModeS);
1139 } else if (tp2 == ia32_ImmSymConst) {
1140 tarval *tv = get_ia32_Immop_tarval(new_op1);
1141 long offs = get_tarval_long(tv);
1143 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1144 add_irn_dep(new_op, get_irg_frame(irg));
1145 DBG_OPT_LEA3(op1, op2, node, new_op);
1147 add_ia32_am_offs_int(new_op, offs);
1148 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1149 set_ia32_am_sc_sign(new_op);
1150 set_ia32_am_flavour(new_op, ia32_am_OB);
1151 set_ia32_am_support(new_op, ia32_am_Source);
1152 set_ia32_op_type(new_op, ia32_AddrModeS);
1154 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1155 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1156 tarval *restv = tarval_sub(tv1, tv2);
1158 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1160 new_op = new_rd_ia32_Const(dbgi, irg, block);
1161 set_ia32_Const_tarval(new_op, restv);
1162 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1165 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1167 } else if (imm_op) {
1168 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1169 tarval_classification_t class_tv, class_negtv;
1170 tarval *tv = get_ia32_Immop_tarval(imm_op);
1172 /* optimize tarvals */
1173 class_tv = classify_tarval(tv);
1174 class_negtv = classify_tarval(tarval_neg(tv));
1176 if (class_tv == TV_CLASSIFY_ONE) {
1177 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1178 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1179 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1181 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1182 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1183 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1184 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1190 /* This is a normal sub */
1191 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1193 /* set AM support */
1194 set_ia32_am_support(new_op, ia32_am_Full);
1196 fold_immediate(new_op, 2, 3);
1198 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1206 * Generates an ia32 DivMod with additional infrastructure for the
1207 * register allocator if needed.
1209 * @param dividend -no comment- :)
1210 * @param divisor -no comment- :)
1211 * @param dm_flav flavour_Div/Mod/DivMod
1212 * @return The created ia32 DivMod node
1214 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1215 ir_node *divisor, ia32_op_flavour_t dm_flav)
1217 ir_node *block = be_transform_node(get_nodes_block(node));
1218 ir_node *new_dividend = be_transform_node(dividend);
1219 ir_node *new_divisor = be_transform_node(divisor);
1220 ir_graph *irg = current_ir_graph;
1221 dbg_info *dbgi = get_irn_dbg_info(node);
1222 ir_mode *mode = get_irn_mode(node);
1223 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1224 ir_node *res, *proj_div, *proj_mod;
1225 ir_node *edx_node, *cltd;
1226 ir_node *in_keep[2];
1227 ir_node *mem, *new_mem;
1228 ir_node *projs[pn_DivMod_max];
1231 ia32_collect_Projs(node, projs, pn_DivMod_max);
1233 proj_div = proj_mod = NULL;
1237 mem = get_Div_mem(node);
1238 mode = get_Div_resmode(node);
1239 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1240 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1243 mem = get_Mod_mem(node);
1244 mode = get_Mod_resmode(node);
1245 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1246 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1248 case flavour_DivMod:
1249 mem = get_DivMod_mem(node);
1250 mode = get_DivMod_resmode(node);
1251 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1252 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1253 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1256 panic("invalid divmod flavour!");
1258 new_mem = be_transform_node(mem);
1260 if (mode_is_signed(mode)) {
1261 /* in signed mode, we need to sign extend the dividend */
1262 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1263 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1264 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1266 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1267 add_irn_dep(edx_node, be_abi_get_start_barrier(env_cg->birg->abi));
1268 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1271 if (mode_is_signed(mode)) {
1272 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1274 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1277 set_ia32_exc_label(res, has_exc);
1279 /* Matze: code can't handle this at the moment... */
1281 /* set AM support */
1282 set_ia32_am_support(res, ia32_am_Source);
1285 /* check, which Proj-Keep, we need to add */
1287 if (proj_div == NULL) {
1288 /* We have only mod result: add div res Proj-Keep */
1289 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1292 if (proj_mod == NULL) {
1293 /* We have only div result: add mod res Proj-Keep */
1294 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1298 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1300 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1307 * Wrapper for generate_DivMod. Sets flavour_Mod.
1310 static ir_node *gen_Mod(ir_node *node) {
1311 return generate_DivMod(node, get_Mod_left(node),
1312 get_Mod_right(node), flavour_Mod);
1316 * Wrapper for generate_DivMod. Sets flavour_Div.
1319 static ir_node *gen_Div(ir_node *node) {
1320 return generate_DivMod(node, get_Div_left(node),
1321 get_Div_right(node), flavour_Div);
1325 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1327 static ir_node *gen_DivMod(ir_node *node) {
1328 return generate_DivMod(node, get_DivMod_left(node),
1329 get_DivMod_right(node), flavour_DivMod);
1335 * Creates an ia32 floating Div.
1337 * @return The created ia32 xDiv node
1339 static ir_node *gen_Quot(ir_node *node) {
1340 ir_node *block = be_transform_node(get_nodes_block(node));
1341 ir_node *op1 = get_Quot_left(node);
1342 ir_node *new_op1 = be_transform_node(op1);
1343 ir_node *op2 = get_Quot_right(node);
1344 ir_node *new_op2 = be_transform_node(op2);
1345 ir_graph *irg = current_ir_graph;
1346 dbg_info *dbgi = get_irn_dbg_info(node);
1347 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1348 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1352 if (USE_SSE2(env_cg)) {
1353 ir_mode *mode = get_irn_mode(op1);
1354 if (is_ia32_xConst(new_op2)) {
1355 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1356 set_ia32_am_support(new_op, ia32_am_None);
1357 copy_ia32_Immop_attr(new_op, new_op2);
1359 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1360 // Matze: disabled for now, spillslot coalescer fails
1361 //set_ia32_am_support(new_op, ia32_am_Source);
1363 set_ia32_ls_mode(new_op, mode);
1365 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1366 // Matze: disabled for now (spillslot coalescer fails)
1367 //set_ia32_am_support(new_op, ia32_am_Source);
1369 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1375 * Creates an ia32 Shl.
1377 * @return The created ia32 Shl node
1379 static ir_node *gen_Shl(ir_node *node) {
1380 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1387 * Creates an ia32 Shr.
1389 * @return The created ia32 Shr node
1391 static ir_node *gen_Shr(ir_node *node) {
1392 return gen_shift_binop(node, get_Shr_left(node),
1393 get_Shr_right(node), new_rd_ia32_Shr);
1399 * Creates an ia32 Sar.
1401 * @return The created ia32 Shrs node
1403 static ir_node *gen_Shrs(ir_node *node) {
1404 return gen_shift_binop(node, get_Shrs_left(node),
1405 get_Shrs_right(node), new_rd_ia32_Sar);
1411 * Creates an ia32 RotL.
1413 * @param op1 The first operator
1414 * @param op2 The second operator
1415 * @return The created ia32 RotL node
1417 static ir_node *gen_RotL(ir_node *node,
1418 ir_node *op1, ir_node *op2) {
1419 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1425 * Creates an ia32 RotR.
1426 * NOTE: There is no RotR with immediate because this would always be a RotL
1427 * "imm-mode_size_bits" which can be pre-calculated.
1429 * @param op1 The first operator
1430 * @param op2 The second operator
1431 * @return The created ia32 RotR node
1433 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1435 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1441 * Creates an ia32 RotR or RotL (depending on the found pattern).
1443 * @return The created ia32 RotL or RotR node
1445 static ir_node *gen_Rot(ir_node *node) {
1446 ir_node *rotate = NULL;
1447 ir_node *op1 = get_Rot_left(node);
1448 ir_node *op2 = get_Rot_right(node);
1450 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1451 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1452 that means we can create a RotR instead of an Add and a RotL */
1454 if (get_irn_op(op2) == op_Add) {
1456 ir_node *left = get_Add_left(add);
1457 ir_node *right = get_Add_right(add);
1458 if (is_Const(right)) {
1459 tarval *tv = get_Const_tarval(right);
1460 ir_mode *mode = get_irn_mode(node);
1461 long bits = get_mode_size_bits(mode);
1463 if (get_irn_op(left) == op_Minus &&
1464 tarval_is_long(tv) &&
1465 get_tarval_long(tv) == bits)
1467 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1468 rotate = gen_RotR(node, op1, get_Minus_op(left));
1473 if (rotate == NULL) {
1474 rotate = gen_RotL(node, op1, op2);
1483 * Transforms a Minus node.
1485 * @param op The Minus operand
1486 * @return The created ia32 Minus node
1488 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1489 ir_node *block = be_transform_node(get_nodes_block(node));
1490 ir_graph *irg = current_ir_graph;
1491 dbg_info *dbgi = get_irn_dbg_info(node);
1492 ir_mode *mode = get_irn_mode(node);
1497 if (mode_is_float(mode)) {
1498 ir_node *new_op = be_transform_node(op);
1500 if (USE_SSE2(env_cg)) {
1501 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1502 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1503 ir_node *nomem = new_rd_NoMem(irg);
1505 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1507 size = get_mode_size_bits(mode);
1508 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1510 set_ia32_am_sc(res, ent);
1511 set_ia32_op_type(res, ia32_AddrModeS);
1512 set_ia32_ls_mode(res, mode);
1514 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1517 res = gen_unop(node, op, new_rd_ia32_Neg);
1520 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1526 * Transforms a Minus node.
1528 * @return The created ia32 Minus node
1530 static ir_node *gen_Minus(ir_node *node) {
1531 return gen_Minus_ex(node, get_Minus_op(node));
1536 * Transforms a Not node.
1538 * @return The created ia32 Not node
1540 static ir_node *gen_Not(ir_node *node) {
1541 ir_node *op = get_Not_op(node);
1543 assert (! mode_is_float(get_irn_mode(node)));
1544 return gen_unop(node, op, new_rd_ia32_Not);
1550 * Transforms an Abs node.
1552 * @return The created ia32 Abs node
1554 static ir_node *gen_Abs(ir_node *node) {
1555 ir_node *block = be_transform_node(get_nodes_block(node));
1556 ir_node *op = get_Abs_op(node);
1557 ir_node *new_op = be_transform_node(op);
1558 ir_graph *irg = current_ir_graph;
1559 dbg_info *dbgi = get_irn_dbg_info(node);
1560 ir_mode *mode = get_irn_mode(node);
1561 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1562 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1563 ir_node *nomem = new_NoMem();
1564 ir_node *res, *p_eax, *p_edx;
1568 if (mode_is_float(mode)) {
1570 if (USE_SSE2(env_cg)) {
1571 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1573 size = get_mode_size_bits(mode);
1574 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1576 set_ia32_am_sc(res, ent);
1578 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1580 set_ia32_op_type(res, ia32_AddrModeS);
1581 set_ia32_ls_mode(res, mode);
1584 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1585 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1589 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1592 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1593 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1595 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1596 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1598 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1599 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1608 * Transforms a Load.
1610 * @return the created ia32 Load node
1612 static ir_node *gen_Load(ir_node *node) {
1613 ir_node *block = be_transform_node(get_nodes_block(node));
1614 ir_node *ptr = get_Load_ptr(node);
1615 ir_node *new_ptr = be_transform_node(ptr);
1616 ir_node *mem = get_Load_mem(node);
1617 ir_node *new_mem = be_transform_node(mem);
1618 ir_graph *irg = current_ir_graph;
1619 dbg_info *dbgi = get_irn_dbg_info(node);
1620 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1621 ir_mode *mode = get_Load_mode(node);
1623 ir_node *lptr = new_ptr;
1626 ir_node *projs[pn_Load_max];
1627 ia32_am_flavour_t am_flav = ia32_am_B;
1629 ia32_collect_Projs(node, projs, pn_Load_max);
1631 /* address might be a constant (symconst or absolute address) */
1632 if (is_ia32_Const(new_ptr)) {
1637 if (mode_is_float(mode)) {
1639 if (USE_SSE2(env_cg)) {
1640 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1641 res_mode = mode_xmm;
1643 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1644 res_mode = mode_vfp;
1647 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1652 check for special case: the loaded value might not be used
1654 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1655 /* add a result proj and a Keep to produce a pseudo use */
1656 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1658 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1661 /* base is a constant address */
1663 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1664 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1665 am_flav = ia32_am_N;
1667 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1668 long offs = get_tarval_long(tv);
1670 add_ia32_am_offs_int(new_op, offs);
1671 am_flav = ia32_am_O;
1675 set_irn_pinned(new_op, get_irn_pinned(node));
1676 set_ia32_am_support(new_op, ia32_am_Source);
1677 set_ia32_op_type(new_op, ia32_AddrModeS);
1678 set_ia32_am_flavour(new_op, am_flav);
1679 set_ia32_ls_mode(new_op, mode);
1681 /* make sure we are scheduled behind the initial IncSP/Barrier
1682 * to avoid spills being placed before it
1684 if (block == get_irg_start_block(irg)) {
1685 add_irn_dep(new_op, get_irg_frame(irg));
1688 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1689 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1697 * Transforms a Store.
1699 * @return the created ia32 Store node
1701 static ir_node *gen_Store(ir_node *node) {
1702 ir_node *block = be_transform_node(get_nodes_block(node));
1703 ir_node *ptr = get_Store_ptr(node);
1704 ir_node *new_ptr = be_transform_node(ptr);
1705 ir_node *val = get_Store_value(node);
1706 ir_node *new_val = be_transform_node(val);
1707 ir_node *mem = get_Store_mem(node);
1708 ir_node *new_mem = be_transform_node(mem);
1709 ir_graph *irg = current_ir_graph;
1710 dbg_info *dbgi = get_irn_dbg_info(node);
1711 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1712 ir_node *sptr = new_ptr;
1713 ir_mode *mode = get_irn_mode(val);
1714 ir_node *sval = new_val;
1717 ia32_am_flavour_t am_flav = ia32_am_B;
1719 if (is_ia32_Const(new_val)) {
1720 assert(!mode_is_float(mode));
1724 /* address might be a constant (symconst or absolute address) */
1725 if (is_ia32_Const(new_ptr)) {
1730 if (mode_is_float(mode)) {
1732 if (USE_SSE2(env_cg)) {
1733 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1735 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1737 } else if (get_mode_size_bits(mode) == 8) {
1738 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1740 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1743 /* stored const is an immediate value */
1744 if (is_ia32_Const(new_val)) {
1745 assert(!mode_is_float(mode));
1746 copy_ia32_Immop_attr(new_op, new_val);
1749 /* base is an constant address */
1751 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1752 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1753 am_flav = ia32_am_N;
1755 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1756 long offs = get_tarval_long(tv);
1758 add_ia32_am_offs_int(new_op, offs);
1759 am_flav = ia32_am_O;
1763 set_irn_pinned(new_op, get_irn_pinned(node));
1764 set_ia32_am_support(new_op, ia32_am_Dest);
1765 set_ia32_op_type(new_op, ia32_AddrModeD);
1766 set_ia32_am_flavour(new_op, am_flav);
1767 set_ia32_ls_mode(new_op, mode);
1769 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1770 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1778 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1780 * @return The transformed node.
1782 static ir_node *gen_Cond(ir_node *node) {
1783 ir_node *block = be_transform_node(get_nodes_block(node));
1784 ir_graph *irg = current_ir_graph;
1785 dbg_info *dbgi = get_irn_dbg_info(node);
1786 ir_node *sel = get_Cond_selector(node);
1787 ir_mode *sel_mode = get_irn_mode(sel);
1788 ir_node *res = NULL;
1789 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1790 ir_node *cnst, *expr;
1792 if (is_Proj(sel) && sel_mode == mode_b) {
1793 ir_node *pred = get_Proj_pred(sel);
1794 ir_node *cmp_a = get_Cmp_left(pred);
1795 ir_node *new_cmp_a = be_transform_node(cmp_a);
1796 ir_node *cmp_b = get_Cmp_right(pred);
1797 ir_node *new_cmp_b = be_transform_node(cmp_b);
1798 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1799 ir_node *nomem = new_NoMem();
1801 int pnc = get_Proj_proj(sel);
1802 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1803 pnc |= ia32_pn_Cmp_Unsigned;
1806 /* check if we can use a CondJmp with immediate */
1807 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1808 expr = get_expr_op(new_cmp_a, new_cmp_b);
1810 if (cnst != NULL && expr != NULL) {
1811 /* immop has to be the right operand, we might need to flip pnc */
1812 if(cnst != new_cmp_b) {
1813 pnc = get_inversed_pnc(pnc);
1816 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1817 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1818 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1820 /* a Cmp A =/!= 0 */
1821 ir_node *op1 = expr;
1822 ir_node *op2 = expr;
1825 /* check, if expr is an only once used And operation */
1826 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1827 op1 = get_irn_n(expr, 2);
1828 op2 = get_irn_n(expr, 3);
1830 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1832 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1833 set_ia32_pncode(res, pnc);
1836 copy_ia32_Immop_attr(res, expr);
1839 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1844 if (mode_is_float(cmp_mode)) {
1846 if (USE_SSE2(env_cg)) {
1847 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1848 set_ia32_ls_mode(res, cmp_mode);
1854 assert(get_mode_size_bits(cmp_mode) == 32);
1855 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1857 copy_ia32_Immop_attr(res, cnst);
1860 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1862 if (mode_is_float(cmp_mode)) {
1864 if (USE_SSE2(env_cg)) {
1865 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1866 set_ia32_ls_mode(res, cmp_mode);
1869 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1870 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1871 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1875 assert(get_mode_size_bits(cmp_mode) == 32);
1876 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1877 set_ia32_commutative(res);
1881 set_ia32_pncode(res, pnc);
1882 // Matze: disabled for now, because the default collect_spills_walker
1883 // is not able to detect the mode of the spilled value
1884 // moreover, the lea optimize phase freely exchanges left/right
1885 // without updating the pnc
1886 //set_ia32_am_support(res, ia32_am_Source);
1889 /* determine the smallest switch case value */
1890 ir_node *new_sel = be_transform_node(sel);
1891 int switch_min = INT_MAX;
1892 const ir_edge_t *edge;
1894 foreach_out_edge(node, edge) {
1895 int pn = get_Proj_proj(get_edge_src_irn(edge));
1896 switch_min = pn < switch_min ? pn : switch_min;
1900 /* if smallest switch case is not 0 we need an additional sub */
1901 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1902 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1903 add_ia32_am_offs_int(res, -switch_min);
1904 set_ia32_am_flavour(res, ia32_am_OB);
1905 set_ia32_am_support(res, ia32_am_Source);
1906 set_ia32_op_type(res, ia32_AddrModeS);
1909 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1910 set_ia32_pncode(res, get_Cond_defaultProj(node));
1913 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1920 * Transforms a CopyB node.
1922 * @return The transformed node.
1924 static ir_node *gen_CopyB(ir_node *node) {
1925 ir_node *block = be_transform_node(get_nodes_block(node));
1926 ir_node *src = get_CopyB_src(node);
1927 ir_node *new_src = be_transform_node(src);
1928 ir_node *dst = get_CopyB_dst(node);
1929 ir_node *new_dst = be_transform_node(dst);
1930 ir_node *mem = get_CopyB_mem(node);
1931 ir_node *new_mem = be_transform_node(mem);
1932 ir_node *res = NULL;
1933 ir_graph *irg = current_ir_graph;
1934 dbg_info *dbgi = get_irn_dbg_info(node);
1935 int size = get_type_size_bytes(get_CopyB_type(node));
1936 ir_mode *dst_mode = get_irn_mode(dst);
1937 ir_mode *src_mode = get_irn_mode(src);
1941 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1942 /* then we need the size explicitly in ECX. */
1943 if (size >= 32 * 4) {
1944 rem = size & 0x3; /* size % 4 */
1947 res = new_rd_ia32_Const(dbgi, irg, block);
1948 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1949 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1951 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1952 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1954 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1955 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1956 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1957 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1958 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1961 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1962 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1964 /* ok: now attach Proj's because movsd will destroy esi and edi */
1965 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1966 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1967 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1970 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1976 ir_node *gen_be_Copy(ir_node *node)
1978 ir_node *result = be_duplicate_node(node);
1979 ir_mode *mode = get_irn_mode(result);
1981 if (mode_needs_gp_reg(mode)) {
1982 set_irn_mode(result, mode_Iu);
1991 * Transforms a Mux node into CMov.
1993 * @return The transformed node.
1995 static ir_node *gen_Mux(ir_node *node) {
1996 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1997 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1999 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2005 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2006 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2007 ir_node *psi_default);
2010 * Transforms a Psi node into CMov.
2012 * @return The transformed node.
2014 static ir_node *gen_Psi(ir_node *node) {
2015 ir_node *block = be_transform_node(get_nodes_block(node));
2016 ir_node *psi_true = get_Psi_val(node, 0);
2017 ir_node *psi_default = get_Psi_default(node);
2018 ia32_code_gen_t *cg = env_cg;
2019 ir_graph *irg = current_ir_graph;
2020 dbg_info *dbgi = get_irn_dbg_info(node);
2021 ir_node *cond = get_Psi_cond(node, 0);
2022 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2023 ir_node *nomem = new_NoMem();
2025 ir_node *cmp, *cmp_a, *cmp_b;
2026 ir_node *new_cmp_a, *new_cmp_b;
2030 assert(get_Psi_n_conds(node) == 1);
2031 assert(get_irn_mode(cond) == mode_b);
2033 if(is_And(cond) || is_Or(cond)) {
2034 ir_node *new_cond = be_transform_node(cond);
2035 tarval *tv_zero = new_tarval_from_long(0, mode_Iu);
2036 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0,
2038 arch_set_irn_register(env_cg->arch_env, zero,
2039 &ia32_gp_regs[REG_GP_NOREG]);
2041 /* we have to compare the result against zero */
2042 new_cmp_a = new_cond;
2047 cmp = get_Proj_pred(cond);
2048 cmp_a = get_Cmp_left(cmp);
2049 cmp_b = get_Cmp_right(cmp);
2050 cmp_mode = get_irn_mode(cmp_a);
2051 pnc = get_Proj_proj(cond);
2053 new_cmp_b = try_create_Immediate(cmp_b, 0);
2054 if(new_cmp_b == NULL) {
2055 new_cmp_b = try_create_Immediate(cmp_a, 0);
2056 if(new_cmp_b != NULL) {
2057 pnc = get_inversed_pnc(pnc);
2058 new_cmp_a = be_transform_node(cmp_b);
2061 new_cmp_a = be_transform_node(cmp_a);
2063 if(new_cmp_b == NULL) {
2064 new_cmp_a = be_transform_node(cmp_a);
2065 new_cmp_b = be_transform_node(cmp_b);
2068 if (!mode_is_signed(cmp_mode)) {
2069 pnc |= ia32_pn_Cmp_Unsigned;
2073 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2074 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2075 new_cmp_a, new_cmp_b, nomem, pnc);
2076 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2077 pnc = get_negated_pnc(pnc, cmp_mode);
2078 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2079 new_cmp_a, new_cmp_b, nomem, pnc);
2081 ir_node *new_psi_true = be_transform_node(psi_true);
2082 ir_node *new_psi_default = be_transform_node(psi_default);
2083 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2084 new_psi_true, new_psi_default, pnc);
2086 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2090 if (mode_is_float(mode)) {
2091 if(mode_is_float(cmp_mode)) {
2092 pnc |= ia32_pn_Cmp_Unsigned;
2095 /* floating point psi */
2098 /* 1st case: compare operands are float too */
2100 /* psi(cmp(a, b), t, f) can be done as: */
2101 /* tmp = cmp a, b */
2102 /* tmp2 = t and tmp */
2103 /* tmp3 = f and not tmp */
2104 /* res = tmp2 or tmp3 */
2106 /* in case the compare operands are int, we move them into xmm register */
2107 if (! mode_is_float(get_irn_mode(cmp_a))) {
2108 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2109 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2111 pnc |= 8; /* transform integer compare to fp compare */
2114 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2115 set_ia32_pncode(new_op, pnc);
2116 set_ia32_am_support(new_op, ia32_am_Source);
2117 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2119 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2120 set_ia32_am_support(and1, ia32_am_None);
2121 set_ia32_commutative(and1);
2122 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2124 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2125 set_ia32_am_support(and2, ia32_am_None);
2126 set_ia32_commutative(and2);
2127 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2129 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2130 set_ia32_am_support(new_op, ia32_am_None);
2131 set_ia32_commutative(new_op);
2132 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2136 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2137 set_ia32_pncode(new_op, pnc);
2138 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2143 construct_binop_func *set_func = NULL;
2144 cmov_func_t *cmov_func = NULL;
2146 if (mode_is_float(get_irn_mode(cmp_a))) {
2147 /* 1st case: compare operands are floats */
2152 set_func = new_rd_ia32_xCmpSet;
2153 cmov_func = new_rd_ia32_xCmpCMov;
2157 set_func = new_rd_ia32_vfCmpSet;
2158 cmov_func = new_rd_ia32_vfCmpCMov;
2161 pnc &= ~0x8; /* fp compare -> int compare */
2164 /* 2nd case: compare operand are integer too */
2165 set_func = new_rd_ia32_CmpSet;
2166 cmov_func = new_rd_ia32_CmpCMov;
2169 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2170 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2171 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2172 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2173 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2174 set_ia32_pncode(new_op, pnc);
2176 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2177 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2178 /* we invert condition and set default to 0 */
2179 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2180 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2183 /* otherwise: use CMOVcc */
2184 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2185 set_ia32_pncode(new_op, pnc);
2188 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2191 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2192 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2193 new_op = gen_binop(node, cmp_a, cmp_b, set_func, 0);
2194 set_ia32_pncode(new_op, pnc);
2195 set_ia32_am_support(new_op, ia32_am_Source);
2197 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2198 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2199 /* we invert condition and set default to 0 */
2200 new_op = gen_binop(node, cmp_a, cmp_b, set_func, 0);
2201 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2202 set_ia32_am_support(new_op, ia32_am_Source);
2205 /* otherwise: use CMOVcc */
2206 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2207 set_ia32_pncode(new_op, pnc);
2208 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2219 * Following conversion rules apply:
2223 * 1) n bit -> m bit n > m (downscale)
2225 * 2) n bit -> m bit n == m (sign change)
2227 * 3) n bit -> m bit n < m (upscale)
2228 * a) source is signed: movsx
2229 * b) source is unsigned: and with lower bits sets
2233 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2237 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2241 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2242 * x87 is mode_E internally, conversions happen only at load and store
2243 * in non-strict semantic
2247 * Create a conversion from x87 state register to general purpose.
2249 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2250 ir_node *block = be_transform_node(get_nodes_block(node));
2251 ir_node *op = get_Conv_op(node);
2252 ir_node *new_op = be_transform_node(op);
2253 ia32_code_gen_t *cg = env_cg;
2254 ir_graph *irg = current_ir_graph;
2255 dbg_info *dbgi = get_irn_dbg_info(node);
2256 ir_node *noreg = ia32_new_NoReg_gp(cg);
2257 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2258 ir_node *fist, *load;
2261 fist = new_rd_ia32_vfist(dbgi, irg, block,
2262 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2264 set_irn_pinned(fist, op_pin_state_floats);
2265 set_ia32_use_frame(fist);
2266 set_ia32_am_support(fist, ia32_am_Dest);
2267 set_ia32_op_type(fist, ia32_AddrModeD);
2268 set_ia32_am_flavour(fist, ia32_am_B);
2269 set_ia32_ls_mode(fist, mode_Iu);
2270 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2273 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2275 set_irn_pinned(load, op_pin_state_floats);
2276 set_ia32_use_frame(load);
2277 set_ia32_am_support(load, ia32_am_Source);
2278 set_ia32_op_type(load, ia32_AddrModeS);
2279 set_ia32_am_flavour(load, ia32_am_B);
2280 set_ia32_ls_mode(load, mode_Iu);
2281 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2283 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2287 * Create a conversion from general purpose to x87 register
2289 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2290 ir_node *block = be_transform_node(get_nodes_block(node));
2291 ir_node *op = get_Conv_op(node);
2292 ir_node *new_op = be_transform_node(op);
2293 ir_graph *irg = current_ir_graph;
2294 dbg_info *dbgi = get_irn_dbg_info(node);
2295 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2296 ir_node *nomem = new_NoMem();
2297 ir_node *fild, *store;
2300 /* first convert to 32 bit if necessary */
2301 src_bits = get_mode_size_bits(src_mode);
2302 if (src_bits == 8) {
2303 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2304 set_ia32_am_support(new_op, ia32_am_Source);
2305 set_ia32_ls_mode(new_op, src_mode);
2306 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2307 } else if (src_bits < 32) {
2308 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2309 set_ia32_am_support(new_op, ia32_am_Source);
2310 set_ia32_ls_mode(new_op, src_mode);
2311 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2315 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2317 set_ia32_use_frame(store);
2318 set_ia32_am_support(store, ia32_am_Dest);
2319 set_ia32_op_type(store, ia32_AddrModeD);
2320 set_ia32_am_flavour(store, ia32_am_OB);
2321 set_ia32_ls_mode(store, mode_Iu);
2324 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2326 set_ia32_use_frame(fild);
2327 set_ia32_am_support(fild, ia32_am_Source);
2328 set_ia32_op_type(fild, ia32_AddrModeS);
2329 set_ia32_am_flavour(fild, ia32_am_OB);
2330 set_ia32_ls_mode(fild, mode_Iu);
2332 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2336 * Transforms a Conv node.
2338 * @return The created ia32 Conv node
2340 static ir_node *gen_Conv(ir_node *node) {
2341 ir_node *block = be_transform_node(get_nodes_block(node));
2342 ir_node *op = get_Conv_op(node);
2343 ir_node *new_op = be_transform_node(op);
2344 ir_graph *irg = current_ir_graph;
2345 dbg_info *dbgi = get_irn_dbg_info(node);
2346 ir_mode *src_mode = get_irn_mode(op);
2347 ir_mode *tgt_mode = get_irn_mode(node);
2348 int src_bits = get_mode_size_bits(src_mode);
2349 int tgt_bits = get_mode_size_bits(tgt_mode);
2350 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2351 ir_node *nomem = new_rd_NoMem(irg);
2354 if (src_mode == tgt_mode) {
2355 if (get_Conv_strict(node)) {
2356 if (USE_SSE2(env_cg)) {
2357 /* when we are in SSE mode, we can kill all strict no-op conversion */
2361 /* this should be optimized already, but who knows... */
2362 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2363 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2368 if (mode_is_float(src_mode)) {
2369 /* we convert from float ... */
2370 if (mode_is_float(tgt_mode)) {
2371 if(src_mode == mode_E && tgt_mode == mode_D
2372 && !get_Conv_strict(node)) {
2373 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2378 if (USE_SSE2(env_cg)) {
2379 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2380 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2381 set_ia32_ls_mode(res, tgt_mode);
2383 // Matze: TODO what about strict convs?
2384 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2385 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2390 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2391 if (USE_SSE2(env_cg)) {
2392 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2393 set_ia32_ls_mode(res, src_mode);
2395 return gen_x87_fp_to_gp(node);
2399 /* we convert from int ... */
2400 if (mode_is_float(tgt_mode)) {
2403 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2404 if (USE_SSE2(env_cg)) {
2405 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2406 set_ia32_ls_mode(res, tgt_mode);
2407 if(src_bits == 32) {
2408 set_ia32_am_support(res, ia32_am_Source);
2411 return gen_x87_gp_to_fp(node, src_mode);
2415 ir_mode *smaller_mode;
2418 if (src_bits == tgt_bits) {
2419 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2423 if (src_bits < tgt_bits) {
2424 smaller_mode = src_mode;
2425 smaller_bits = src_bits;
2427 smaller_mode = tgt_mode;
2428 smaller_bits = tgt_bits;
2431 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2432 if (smaller_bits == 8) {
2433 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2434 set_ia32_ls_mode(res, smaller_mode);
2436 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2437 set_ia32_ls_mode(res, smaller_mode);
2439 set_ia32_am_support(res, ia32_am_Source);
2443 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2449 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2453 assert(tarval_is_long(tv));
2454 val = get_tarval_long(tv);
2456 switch (immediate_constraint_type) {
2460 return val >= 0 && val <= 32;
2462 return val >= 0 && val <= 63;
2464 return val >= -128 && val <= 127;
2466 return val == 0xff || val == 0xffff;
2468 return val >= 0 && val <= 3;
2470 return val >= 0 && val <= 255;
2472 return val >= 0 && val <= 127;
2476 panic("Invalid immediate constraint found");
2481 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2484 tarval *offset = NULL;
2485 int offset_sign = 0;
2486 ir_entity *symconst_ent = NULL;
2487 int symconst_sign = 0;
2489 ir_node *cnst = NULL;
2490 ir_node *symconst = NULL;
2496 mode = get_irn_mode(node);
2497 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2498 !mode_is_reference(mode)) {
2502 if(is_Minus(node)) {
2504 node = get_Minus_op(node);
2507 if(is_Const(node)) {
2510 offset_sign = minus;
2511 } else if(is_SymConst(node)) {
2514 symconst_sign = minus;
2515 } else if(is_Add(node)) {
2516 ir_node *left = get_Add_left(node);
2517 ir_node *right = get_Add_right(node);
2518 if(is_Const(left) && is_SymConst(right)) {
2521 symconst_sign = minus;
2522 offset_sign = minus;
2523 } else if(is_SymConst(left) && is_Const(right)) {
2526 symconst_sign = minus;
2527 offset_sign = minus;
2529 } else if(is_Sub(node)) {
2530 ir_node *left = get_Sub_left(node);
2531 ir_node *right = get_Sub_right(node);
2532 if(is_Const(left) && is_SymConst(right)) {
2535 symconst_sign = !minus;
2536 offset_sign = minus;
2537 } else if(is_SymConst(left) && is_Const(right)) {
2540 symconst_sign = minus;
2541 offset_sign = !minus;
2548 offset = get_Const_tarval(cnst);
2549 if(!tarval_is_long(offset)) {
2550 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2555 if(!check_immediate_constraint(offset, immediate_constraint_type))
2558 if(symconst != NULL) {
2559 if(immediate_constraint_type != 0) {
2560 /* we need full 32bits for symconsts */
2564 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2566 symconst_ent = get_SymConst_entity(symconst);
2568 if(cnst == NULL && symconst == NULL)
2571 if(offset_sign && offset != NULL) {
2572 offset = tarval_neg(offset);
2575 irg = current_ir_graph;
2576 dbgi = get_irn_dbg_info(node);
2577 block = get_irg_start_block(irg);
2578 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2580 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2582 /* make sure we don't schedule stuff before the barrier */
2583 add_irn_dep(res, get_irg_frame(irg));
2588 typedef struct constraint_t constraint_t;
2589 struct constraint_t {
2592 const arch_register_req_t **out_reqs;
2594 const arch_register_req_t *req;
2595 unsigned immediate_possible;
2596 char immediate_type;
2599 void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint,
2602 int immediate_possible = 0;
2603 char immediate_type = 0;
2604 unsigned limited = 0;
2605 const arch_register_class_t *cls = NULL;
2607 struct obstack *obst;
2608 arch_register_req_t *req;
2609 unsigned *limited_ptr;
2613 /* TODO: replace all the asserts with nice error messages */
2615 printf("Constraint: %s\n", c);
2625 assert(cls == NULL ||
2626 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2627 cls = &ia32_reg_classes[CLASS_ia32_gp];
2628 limited |= 1 << REG_EAX;
2631 assert(cls == NULL ||
2632 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2633 cls = &ia32_reg_classes[CLASS_ia32_gp];
2634 limited |= 1 << REG_EBX;
2637 assert(cls == NULL ||
2638 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2639 cls = &ia32_reg_classes[CLASS_ia32_gp];
2640 limited |= 1 << REG_ECX;
2643 assert(cls == NULL ||
2644 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2645 cls = &ia32_reg_classes[CLASS_ia32_gp];
2646 limited |= 1 << REG_EDX;
2649 assert(cls == NULL ||
2650 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2651 cls = &ia32_reg_classes[CLASS_ia32_gp];
2652 limited |= 1 << REG_EDI;
2655 assert(cls == NULL ||
2656 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2657 cls = &ia32_reg_classes[CLASS_ia32_gp];
2658 limited |= 1 << REG_ESI;
2661 case 'q': /* q means lower part of the regs only, this makes no
2662 * difference to Q for us (we only assigne whole registers) */
2663 assert(cls == NULL ||
2664 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2665 cls = &ia32_reg_classes[CLASS_ia32_gp];
2666 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2670 assert(cls == NULL ||
2671 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2672 cls = &ia32_reg_classes[CLASS_ia32_gp];
2673 limited |= 1 << REG_EAX | 1 << REG_EDX;
2676 assert(cls == NULL ||
2677 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2678 cls = &ia32_reg_classes[CLASS_ia32_gp];
2679 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2680 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2687 assert(cls == NULL);
2688 cls = &ia32_reg_classes[CLASS_ia32_gp];
2694 /* TODO: mark values so the x87 simulator knows about t and u */
2695 assert(cls == NULL);
2696 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2701 assert(cls == NULL);
2702 /* TODO: check that sse2 is supported */
2703 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2713 assert(!immediate_possible);
2714 immediate_possible = 1;
2715 immediate_type = *c;
2719 assert(!immediate_possible);
2720 immediate_possible = 1;
2724 assert(!immediate_possible && cls == NULL);
2725 immediate_possible = 1;
2726 cls = &ia32_reg_classes[CLASS_ia32_gp];
2739 assert(constraint->is_in && "can only specify same constraint "
2742 sscanf(c, "%d%n", &same_as, &p);
2749 case 'E': /* no float consts yet */
2750 case 'F': /* no float consts yet */
2751 case 's': /* makes no sense on x86 */
2752 case 'X': /* we can't support that in firm */
2756 case '<': /* no autodecrement on x86 */
2757 case '>': /* no autoincrement on x86 */
2758 case 'C': /* sse constant not supported yet */
2759 case 'G': /* 80387 constant not supported yet */
2760 case 'y': /* we don't support mmx registers yet */
2761 case 'Z': /* not available in 32 bit mode */
2762 case 'e': /* not available in 32 bit mode */
2763 assert(0 && "asm constraint not supported");
2766 assert(0 && "unknown asm constraint found");
2773 const arch_register_req_t *other_constr;
2775 assert(cls == NULL && "same as and register constraint not supported");
2776 assert(!immediate_possible && "same as and immediate constraint not "
2778 assert(same_as < constraint->n_outs && "wrong constraint number in "
2779 "same_as constraint");
2781 other_constr = constraint->out_reqs[same_as];
2783 req = obstack_alloc(obst, sizeof(req[0]));
2784 req->cls = other_constr->cls;
2785 req->type = arch_register_req_type_should_be_same;
2786 req->limited = NULL;
2787 req->other_same = pos;
2788 req->other_different = -1;
2790 /* switch constraints. This is because in firm we have same_as
2791 * constraints on the output constraints while in the gcc asm syntax
2792 * they are specified on the input constraints */
2793 constraint->req = other_constr;
2794 constraint->out_reqs[same_as] = req;
2795 constraint->immediate_possible = 0;
2799 if(immediate_possible && cls == NULL) {
2800 cls = &ia32_reg_classes[CLASS_ia32_gp];
2802 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2803 assert(cls != NULL);
2805 if(immediate_possible) {
2806 assert(constraint->is_in
2807 && "imeediates make no sense for output constraints");
2809 /* todo: check types (no float input on 'r' constrainted in and such... */
2811 irg = current_ir_graph;
2812 obst = get_irg_obstack(irg);
2815 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2816 limited_ptr = (unsigned*) (req+1);
2818 req = obstack_alloc(obst, sizeof(req[0]));
2820 memset(req, 0, sizeof(req[0]));
2823 req->type = arch_register_req_type_limited;
2824 *limited_ptr = limited;
2825 req->limited = limited_ptr;
2827 req->type = arch_register_req_type_normal;
2831 constraint->req = req;
2832 constraint->immediate_possible = immediate_possible;
2833 constraint->immediate_type = immediate_type;
2837 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2840 panic("Clobbers not supported yet");
2843 ir_node *gen_ASM(ir_node *node)
2846 ir_graph *irg = current_ir_graph;
2847 ir_node *block = be_transform_node(get_nodes_block(node));
2848 dbg_info *dbgi = get_irn_dbg_info(node);
2855 ia32_asm_attr_t *attr;
2856 const arch_register_req_t **out_reqs;
2857 const arch_register_req_t **in_reqs;
2858 struct obstack *obst;
2859 constraint_t parsed_constraint;
2861 /* assembler could contain float statements */
2864 /* transform inputs */
2865 arity = get_irn_arity(node);
2866 in = alloca(arity * sizeof(in[0]));
2867 memset(in, 0, arity * sizeof(in[0]));
2869 n_outs = get_ASM_n_output_constraints(node);
2870 n_clobbers = get_ASM_n_clobbers(node);
2871 out_arity = n_outs + n_clobbers;
2873 /* construct register constraints */
2874 obst = get_irg_obstack(irg);
2875 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2876 parsed_constraint.out_reqs = out_reqs;
2877 parsed_constraint.n_outs = n_outs;
2878 parsed_constraint.is_in = 0;
2879 for(i = 0; i < out_arity; ++i) {
2883 const ir_asm_constraint *constraint;
2884 constraint = & get_ASM_output_constraints(node) [i];
2885 c = get_id_str(constraint->constraint);
2886 parse_asm_constraint(node, i, &parsed_constraint, c);
2888 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2889 c = get_id_str(glob_id);
2890 parse_clobber(node, i, &parsed_constraint, c);
2892 out_reqs[i] = parsed_constraint.req;
2895 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2896 parsed_constraint.is_in = 1;
2897 for(i = 0; i < arity; ++i) {
2898 const ir_asm_constraint *constraint;
2902 constraint = & get_ASM_input_constraints(node) [i];
2903 constr_id = constraint->constraint;
2904 c = get_id_str(constr_id);
2905 parse_asm_constraint(node, i, &parsed_constraint, c);
2906 in_reqs[i] = parsed_constraint.req;
2908 if(parsed_constraint.immediate_possible) {
2909 ir_node *pred = get_irn_n(node, i);
2910 char imm_type = parsed_constraint.immediate_type;
2911 ir_node *immediate = try_create_Immediate(pred, imm_type);
2913 if(immediate != NULL) {
2919 /* transform inputs */
2920 for(i = 0; i < arity; ++i) {
2922 ir_node *transformed;
2927 pred = get_irn_n(node, i);
2928 transformed = be_transform_node(pred);
2929 in[i] = transformed;
2932 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2934 generic_attr = get_irn_generic_attr(res);
2935 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2936 attr->asm_text = get_ASM_text(node);
2937 set_ia32_out_req_all(res, out_reqs);
2938 set_ia32_in_req_all(res, in_reqs);
2940 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2945 /********************************************
2948 * | |__ ___ _ __ ___ __| | ___ ___
2949 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2950 * | |_) | __/ | | | (_) | (_| | __/\__ \
2951 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2953 ********************************************/
2955 static ir_node *gen_be_StackParam(ir_node *node) {
2956 ir_node *block = be_transform_node(get_nodes_block(node));
2957 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2958 ir_node *new_ptr = be_transform_node(ptr);
2959 ir_node *new_op = NULL;
2960 ir_graph *irg = current_ir_graph;
2961 dbg_info *dbgi = get_irn_dbg_info(node);
2962 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2963 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2964 ir_mode *load_mode = get_irn_mode(node);
2965 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2969 if (mode_is_float(load_mode)) {
2971 if (USE_SSE2(env_cg)) {
2972 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2973 pn_res = pn_ia32_xLoad_res;
2974 proj_mode = mode_xmm;
2976 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2977 pn_res = pn_ia32_vfld_res;
2978 proj_mode = mode_vfp;
2981 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2982 proj_mode = mode_Iu;
2983 pn_res = pn_ia32_Load_res;
2986 set_irn_pinned(new_op, op_pin_state_floats);
2987 set_ia32_frame_ent(new_op, ent);
2988 set_ia32_use_frame(new_op);
2990 set_ia32_am_support(new_op, ia32_am_Source);
2991 set_ia32_op_type(new_op, ia32_AddrModeS);
2992 set_ia32_am_flavour(new_op, ia32_am_B);
2993 set_ia32_ls_mode(new_op, load_mode);
2994 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2996 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2998 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
3002 * Transforms a FrameAddr into an ia32 Add.
3004 static ir_node *gen_be_FrameAddr(ir_node *node) {
3005 ir_node *block = be_transform_node(get_nodes_block(node));
3006 ir_node *op = be_get_FrameAddr_frame(node);
3007 ir_node *new_op = be_transform_node(op);
3008 ir_graph *irg = current_ir_graph;
3009 dbg_info *dbgi = get_irn_dbg_info(node);
3010 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3013 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3014 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3015 set_ia32_am_support(res, ia32_am_Full);
3016 set_ia32_use_frame(res);
3017 set_ia32_am_flavour(res, ia32_am_OB);
3019 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3025 * Transforms a FrameLoad into an ia32 Load.
3027 static ir_node *gen_be_FrameLoad(ir_node *node) {
3028 ir_node *block = be_transform_node(get_nodes_block(node));
3029 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
3030 ir_node *new_mem = be_transform_node(mem);
3031 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
3032 ir_node *new_ptr = be_transform_node(ptr);
3033 ir_node *new_op = NULL;
3034 ir_graph *irg = current_ir_graph;
3035 dbg_info *dbgi = get_irn_dbg_info(node);
3036 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3037 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3038 ir_mode *mode = get_type_mode(get_entity_type(ent));
3039 ir_node *projs[pn_Load_max];
3041 ia32_collect_Projs(node, projs, pn_Load_max);
3043 if (mode_is_float(mode)) {
3045 if (USE_SSE2(env_cg)) {
3046 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
3049 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3053 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
3056 set_irn_pinned(new_op, op_pin_state_floats);
3057 set_ia32_frame_ent(new_op, ent);
3058 set_ia32_use_frame(new_op);
3060 set_ia32_am_support(new_op, ia32_am_Source);
3061 set_ia32_op_type(new_op, ia32_AddrModeS);
3062 set_ia32_am_flavour(new_op, ia32_am_B);
3063 set_ia32_ls_mode(new_op, mode);
3065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3072 * Transforms a FrameStore into an ia32 Store.
3074 static ir_node *gen_be_FrameStore(ir_node *node) {
3075 ir_node *block = be_transform_node(get_nodes_block(node));
3076 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
3077 ir_node *new_mem = be_transform_node(mem);
3078 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
3079 ir_node *new_ptr = be_transform_node(ptr);
3080 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3081 ir_node *new_val = be_transform_node(val);
3082 ir_node *new_op = NULL;
3083 ir_graph *irg = current_ir_graph;
3084 dbg_info *dbgi = get_irn_dbg_info(node);
3085 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3086 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3087 ir_mode *mode = get_irn_mode(val);
3089 if (mode_is_float(mode)) {
3091 if (USE_SSE2(env_cg)) {
3092 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3094 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3096 } else if (get_mode_size_bits(mode) == 8) {
3097 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3099 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3102 set_ia32_frame_ent(new_op, ent);
3103 set_ia32_use_frame(new_op);
3105 set_ia32_am_support(new_op, ia32_am_Dest);
3106 set_ia32_op_type(new_op, ia32_AddrModeD);
3107 set_ia32_am_flavour(new_op, ia32_am_B);
3108 set_ia32_ls_mode(new_op, mode);
3110 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3116 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3118 static ir_node *gen_be_Return(ir_node *node) {
3119 ir_graph *irg = current_ir_graph;
3120 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3121 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3122 ir_entity *ent = get_irg_entity(irg);
3123 ir_type *tp = get_entity_type(ent);
3128 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3129 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3132 int pn_ret_val, pn_ret_mem, arity, i;
3134 assert(ret_val != NULL);
3135 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3136 return be_duplicate_node(node);
3139 res_type = get_method_res_type(tp, 0);
3141 if (! is_Primitive_type(res_type)) {
3142 return be_duplicate_node(node);
3145 mode = get_type_mode(res_type);
3146 if (! mode_is_float(mode)) {
3147 return be_duplicate_node(node);
3150 assert(get_method_n_ress(tp) == 1);
3152 pn_ret_val = get_Proj_proj(ret_val);
3153 pn_ret_mem = get_Proj_proj(ret_mem);
3155 /* get the Barrier */
3156 barrier = get_Proj_pred(ret_val);
3158 /* get result input of the Barrier */
3159 ret_val = get_irn_n(barrier, pn_ret_val);
3160 new_ret_val = be_transform_node(ret_val);
3162 /* get memory input of the Barrier */
3163 ret_mem = get_irn_n(barrier, pn_ret_mem);
3164 new_ret_mem = be_transform_node(ret_mem);
3166 frame = get_irg_frame(irg);
3168 dbgi = get_irn_dbg_info(barrier);
3169 block = be_transform_node(get_nodes_block(barrier));
3171 noreg = ia32_new_NoReg_gp(env_cg);
3173 /* store xmm0 onto stack */
3174 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3175 set_ia32_ls_mode(sse_store, mode);
3176 set_ia32_op_type(sse_store, ia32_AddrModeD);
3177 set_ia32_use_frame(sse_store);
3178 set_ia32_am_flavour(sse_store, ia32_am_B);
3179 set_ia32_am_support(sse_store, ia32_am_Dest);
3182 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3183 set_ia32_ls_mode(fld, mode);
3184 set_ia32_op_type(fld, ia32_AddrModeS);
3185 set_ia32_use_frame(fld);
3186 set_ia32_am_flavour(fld, ia32_am_B);
3187 set_ia32_am_support(fld, ia32_am_Source);
3189 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3190 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3191 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3193 /* create a new barrier */
3194 arity = get_irn_arity(barrier);
3195 in = alloca(arity * sizeof(in[0]));
3196 for (i = 0; i < arity; ++i) {
3199 if (i == pn_ret_val) {
3201 } else if (i == pn_ret_mem) {
3204 ir_node *in = get_irn_n(barrier, i);
3205 new_in = be_transform_node(in);
3210 new_barrier = new_ir_node(dbgi, irg, block,
3211 get_irn_op(barrier), get_irn_mode(barrier),
3213 copy_node_attr(barrier, new_barrier);
3214 be_duplicate_deps(barrier, new_barrier);
3215 be_set_transformed_node(barrier, new_barrier);
3216 mark_irn_visited(barrier);
3218 /* transform normally */
3219 return be_duplicate_node(node);
3223 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3225 static ir_node *gen_be_AddSP(ir_node *node) {
3226 ir_node *block = be_transform_node(get_nodes_block(node));
3227 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3228 ir_node *new_sz = be_transform_node(sz);
3229 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3230 ir_node *new_sp = be_transform_node(sp);
3231 ir_graph *irg = current_ir_graph;
3232 dbg_info *dbgi = get_irn_dbg_info(node);
3233 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3234 ir_node *nomem = new_NoMem();
3237 /* ia32 stack grows in reverse direction, make a SubSP */
3238 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3239 set_ia32_am_support(new_op, ia32_am_Source);
3240 fold_immediate(new_op, 2, 3);
3242 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3248 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3250 static ir_node *gen_be_SubSP(ir_node *node) {
3251 ir_node *block = be_transform_node(get_nodes_block(node));
3252 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3253 ir_node *new_sz = be_transform_node(sz);
3254 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3255 ir_node *new_sp = be_transform_node(sp);
3256 ir_graph *irg = current_ir_graph;
3257 dbg_info *dbgi = get_irn_dbg_info(node);
3258 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3259 ir_node *nomem = new_NoMem();
3262 /* ia32 stack grows in reverse direction, make an AddSP */
3263 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3264 set_ia32_am_support(new_op, ia32_am_Source);
3265 fold_immediate(new_op, 2, 3);
3267 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3273 * This function just sets the register for the Unknown node
3274 * as this is not done during register allocation because Unknown
3275 * is an "ignore" node.
3277 static ir_node *gen_Unknown(ir_node *node) {
3278 ir_mode *mode = get_irn_mode(node);
3280 if (mode_is_float(mode)) {
3281 if (USE_SSE2(env_cg))
3282 return ia32_new_Unknown_xmm(env_cg);
3284 return ia32_new_Unknown_vfp(env_cg);
3285 } else if (mode_needs_gp_reg(mode)) {
3286 return ia32_new_Unknown_gp(env_cg);
3288 assert(0 && "unsupported Unknown-Mode");
3295 * Change some phi modes
3297 static ir_node *gen_Phi(ir_node *node) {
3298 ir_node *block = be_transform_node(get_nodes_block(node));
3299 ir_graph *irg = current_ir_graph;
3300 dbg_info *dbgi = get_irn_dbg_info(node);
3301 ir_mode *mode = get_irn_mode(node);
3304 if(mode_needs_gp_reg(mode)) {
3305 /* we shouldn't have any 64bit stuff around anymore */
3306 assert(get_mode_size_bits(mode) <= 32);
3307 /* all integer operations are on 32bit registers now */
3309 } else if(mode_is_float(mode)) {
3310 assert(mode == mode_D || mode == mode_F);
3311 if (USE_SSE2(env_cg)) {
3318 /* phi nodes allow loops, so we use the old arguments for now
3319 * and fix this later */
3320 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3321 copy_node_attr(node, phi);
3322 be_duplicate_deps(node, phi);
3324 be_set_transformed_node(node, phi);
3325 be_enqueue_preds(node);
3330 /**********************************************************************
3333 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3334 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3335 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3336 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3338 **********************************************************************/
3340 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3342 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3345 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3346 ir_node *val, ir_node *mem);
3349 * Transforms a lowered Load into a "real" one.
3351 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3352 ir_node *block = be_transform_node(get_nodes_block(node));
3353 ir_node *ptr = get_irn_n(node, 0);
3354 ir_node *new_ptr = be_transform_node(ptr);
3355 ir_node *mem = get_irn_n(node, 1);
3356 ir_node *new_mem = be_transform_node(mem);
3357 ir_graph *irg = current_ir_graph;
3358 dbg_info *dbgi = get_irn_dbg_info(node);
3359 ir_mode *mode = get_ia32_ls_mode(node);
3360 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3364 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3365 lowering we have x87 nodes, so we need to enforce simulation.
3367 if (mode_is_float(mode)) {
3369 if (fp_unit == fp_x87)
3373 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3375 set_ia32_am_support(new_op, ia32_am_Source);
3376 set_ia32_op_type(new_op, ia32_AddrModeS);
3377 set_ia32_am_flavour(new_op, ia32_am_OB);
3378 set_ia32_am_offs_int(new_op, 0);
3379 set_ia32_am_scale(new_op, 1);
3380 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3381 if (is_ia32_am_sc_sign(node))
3382 set_ia32_am_sc_sign(new_op);
3383 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3384 if (is_ia32_use_frame(node)) {
3385 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3386 set_ia32_use_frame(new_op);
3389 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3395 * Transforms a lowered Store into a "real" one.
3397 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3398 ir_node *block = be_transform_node(get_nodes_block(node));
3399 ir_node *ptr = get_irn_n(node, 0);
3400 ir_node *new_ptr = be_transform_node(ptr);
3401 ir_node *val = get_irn_n(node, 1);
3402 ir_node *new_val = be_transform_node(val);
3403 ir_node *mem = get_irn_n(node, 2);
3404 ir_node *new_mem = be_transform_node(mem);
3405 ir_graph *irg = current_ir_graph;
3406 dbg_info *dbgi = get_irn_dbg_info(node);
3407 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3408 ir_mode *mode = get_ia32_ls_mode(node);
3411 ia32_am_flavour_t am_flav = ia32_B;
3414 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3415 lowering we have x87 nodes, so we need to enforce simulation.
3417 if (mode_is_float(mode)) {
3419 if (fp_unit == fp_x87)
3423 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3425 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3427 add_ia32_am_offs_int(new_op, am_offs);
3430 set_ia32_am_support(new_op, ia32_am_Dest);
3431 set_ia32_op_type(new_op, ia32_AddrModeD);
3432 set_ia32_am_flavour(new_op, am_flav);
3433 set_ia32_ls_mode(new_op, mode);
3434 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3435 set_ia32_use_frame(new_op);
3437 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3444 * Transforms an ia32_l_XXX into a "real" XXX node
3446 * @param env The transformation environment
3447 * @return the created ia32 XXX node
3449 #define GEN_LOWERED_OP(op) \
3450 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3451 ir_mode *mode = get_irn_mode(node); \
3452 if (mode_is_float(mode)) \
3454 return gen_binop(node, get_binop_left(node), \
3455 get_binop_right(node), new_rd_ia32_##op,0); \
3458 #define GEN_LOWERED_x87_OP(op) \
3459 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3461 FORCE_x87(env_cg); \
3462 new_op = gen_binop_float(node, get_binop_left(node), \
3463 get_binop_right(node), new_rd_ia32_##op); \
3467 #define GEN_LOWERED_UNOP(op) \
3468 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3469 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3472 #define GEN_LOWERED_SHIFT_OP(op) \
3473 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3474 return gen_shift_binop(node, get_binop_left(node), \
3475 get_binop_right(node), new_rd_ia32_##op); \
3478 #define GEN_LOWERED_LOAD(op, fp_unit) \
3479 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3480 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3483 #define GEN_LOWERED_STORE(op, fp_unit) \
3484 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3485 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3492 GEN_LOWERED_OP(IMul)
3494 GEN_LOWERED_x87_OP(vfprem)
3495 GEN_LOWERED_x87_OP(vfmul)
3496 GEN_LOWERED_x87_OP(vfsub)
3498 GEN_LOWERED_UNOP(Neg)
3500 GEN_LOWERED_LOAD(vfild, fp_x87)
3501 GEN_LOWERED_LOAD(Load, fp_none)
3502 /*GEN_LOWERED_STORE(vfist, fp_x87)
3505 GEN_LOWERED_STORE(Store, fp_none)
3507 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3508 ir_node *block = be_transform_node(get_nodes_block(node));
3509 ir_node *left = get_binop_left(node);
3510 ir_node *new_left = be_transform_node(left);
3511 ir_node *right = get_binop_right(node);
3512 ir_node *new_right = be_transform_node(right);
3513 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3514 ir_graph *irg = current_ir_graph;
3515 dbg_info *dbgi = get_irn_dbg_info(node);
3518 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3519 clear_ia32_commutative(vfdiv);
3520 set_ia32_am_support(vfdiv, ia32_am_Source);
3521 fold_immediate(vfdiv, 2, 3);
3523 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3531 * Transforms a l_MulS into a "real" MulS node.
3533 * @param env The transformation environment
3534 * @return the created ia32 Mul node
3536 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3537 ir_node *block = be_transform_node(get_nodes_block(node));
3538 ir_node *left = get_binop_left(node);
3539 ir_node *new_left = be_transform_node(left);
3540 ir_node *right = get_binop_right(node);
3541 ir_node *new_right = be_transform_node(right);
3542 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3543 ir_graph *irg = current_ir_graph;
3544 dbg_info *dbgi = get_irn_dbg_info(node);
3547 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3548 /* and then skip the result Proj, because all needed Projs are already there. */
3549 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3550 clear_ia32_commutative(muls);
3551 set_ia32_am_support(muls, ia32_am_Source);
3552 fold_immediate(muls, 2, 3);
3554 /* check if EAX and EDX proj exist, add missing one */
3555 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3556 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3557 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3559 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3564 GEN_LOWERED_SHIFT_OP(Shl)
3565 GEN_LOWERED_SHIFT_OP(Shr)
3566 GEN_LOWERED_SHIFT_OP(Sar)
3569 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3570 * op1 - target to be shifted
3571 * op2 - contains bits to be shifted into target
3573 * Only op3 can be an immediate.
3575 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3576 ir_node *op2, ir_node *count)
3578 ir_node *block = be_transform_node(get_nodes_block(node));
3579 ir_node *new_op1 = be_transform_node(op1);
3580 ir_node *new_op2 = be_transform_node(op2);
3581 ir_node *new_count = be_transform_node(count);
3582 ir_node *new_op = NULL;
3583 ir_graph *irg = current_ir_graph;
3584 dbg_info *dbgi = get_irn_dbg_info(node);
3585 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3586 ir_node *nomem = new_NoMem();
3590 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3592 /* Check if immediate optimization is on and */
3593 /* if it's an operation with immediate. */
3594 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3596 /* Limit imm_op within range imm8 */
3598 tv = get_ia32_Immop_tarval(imm_op);
3601 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3602 set_ia32_Immop_tarval(imm_op, tv);
3609 /* integer operations */
3611 /* This is ShiftD with const */
3612 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3614 if (is_ia32_l_ShlD(node))
3615 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3616 new_op1, new_op2, noreg, nomem);
3618 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3619 new_op1, new_op2, noreg, nomem);
3620 copy_ia32_Immop_attr(new_op, imm_op);
3623 /* This is a normal ShiftD */
3624 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3625 if (is_ia32_l_ShlD(node))
3626 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3627 new_op1, new_op2, new_count, nomem);
3629 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3630 new_op1, new_op2, new_count, nomem);
3633 /* set AM support */
3634 // Matze: node has unsupported format (6inputs)
3635 //set_ia32_am_support(new_op, ia32_am_Dest);
3637 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3639 set_ia32_emit_cl(new_op);
3644 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3645 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3646 get_irn_n(node, 1), get_irn_n(node, 2));
3649 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3650 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3651 get_irn_n(node, 1), get_irn_n(node, 2));
3655 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3657 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3658 ir_node *block = be_transform_node(get_nodes_block(node));
3659 ir_node *val = get_irn_n(node, 1);
3660 ir_node *new_val = be_transform_node(val);
3661 ia32_code_gen_t *cg = env_cg;
3662 ir_node *res = NULL;
3663 ir_graph *irg = current_ir_graph;
3665 ir_node *noreg, *new_ptr, *new_mem;
3672 mem = get_irn_n(node, 2);
3673 new_mem = be_transform_node(mem);
3674 ptr = get_irn_n(node, 0);
3675 new_ptr = be_transform_node(ptr);
3676 noreg = ia32_new_NoReg_gp(cg);
3677 dbgi = get_irn_dbg_info(node);
3679 /* Store x87 -> MEM */
3680 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3681 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3682 set_ia32_use_frame(res);
3683 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3684 set_ia32_am_support(res, ia32_am_Dest);
3685 set_ia32_am_flavour(res, ia32_B);
3686 set_ia32_op_type(res, ia32_AddrModeD);
3688 /* Load MEM -> SSE */
3689 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3690 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3691 set_ia32_use_frame(res);
3692 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3693 set_ia32_am_support(res, ia32_am_Source);
3694 set_ia32_am_flavour(res, ia32_B);
3695 set_ia32_op_type(res, ia32_AddrModeS);
3696 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3702 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3704 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3705 ir_node *block = be_transform_node(get_nodes_block(node));
3706 ir_node *val = get_irn_n(node, 1);
3707 ir_node *new_val = be_transform_node(val);
3708 ia32_code_gen_t *cg = env_cg;
3709 ir_graph *irg = current_ir_graph;
3710 ir_node *res = NULL;
3711 ir_entity *fent = get_ia32_frame_ent(node);
3712 ir_mode *lsmode = get_ia32_ls_mode(node);
3714 ir_node *noreg, *new_ptr, *new_mem;
3718 if (! USE_SSE2(cg)) {
3719 /* SSE unit is not used -> skip this node. */
3723 ptr = get_irn_n(node, 0);
3724 new_ptr = be_transform_node(ptr);
3725 mem = get_irn_n(node, 2);
3726 new_mem = be_transform_node(mem);
3727 noreg = ia32_new_NoReg_gp(cg);
3728 dbgi = get_irn_dbg_info(node);
3730 /* Store SSE -> MEM */
3731 if (is_ia32_xLoad(skip_Proj(new_val))) {
3732 ir_node *ld = skip_Proj(new_val);
3734 /* we can vfld the value directly into the fpu */
3735 fent = get_ia32_frame_ent(ld);
3736 ptr = get_irn_n(ld, 0);
3737 offs = get_ia32_am_offs_int(ld);
3739 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3740 set_ia32_frame_ent(res, fent);
3741 set_ia32_use_frame(res);
3742 set_ia32_ls_mode(res, lsmode);
3743 set_ia32_am_support(res, ia32_am_Dest);
3744 set_ia32_am_flavour(res, ia32_B);
3745 set_ia32_op_type(res, ia32_AddrModeD);
3749 /* Load MEM -> x87 */
3750 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3751 set_ia32_frame_ent(res, fent);
3752 set_ia32_use_frame(res);
3753 set_ia32_ls_mode(res, lsmode);
3754 add_ia32_am_offs_int(res, offs);
3755 set_ia32_am_support(res, ia32_am_Source);
3756 set_ia32_am_flavour(res, ia32_B);
3757 set_ia32_op_type(res, ia32_AddrModeS);
3758 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3763 /*********************************************************
3766 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3767 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3768 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3769 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3771 *********************************************************/
3774 * the BAD transformer.
3776 static ir_node *bad_transform(ir_node *node) {
3777 panic("No transform function for %+F available.\n", node);
3782 * Transform the Projs of an AddSP.
3784 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3785 ir_node *block = be_transform_node(get_nodes_block(node));
3786 ir_node *pred = get_Proj_pred(node);
3787 ir_node *new_pred = be_transform_node(pred);
3788 ir_graph *irg = current_ir_graph;
3789 dbg_info *dbgi = get_irn_dbg_info(node);
3790 long proj = get_Proj_proj(node);
3792 if (proj == pn_be_AddSP_res) {
3793 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3794 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3796 } else if (proj == pn_be_AddSP_M) {
3797 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3801 return new_rd_Unknown(irg, get_irn_mode(node));
3805 * Transform the Projs of a SubSP.
3807 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3808 ir_node *block = be_transform_node(get_nodes_block(node));
3809 ir_node *pred = get_Proj_pred(node);
3810 ir_node *new_pred = be_transform_node(pred);
3811 ir_graph *irg = current_ir_graph;
3812 dbg_info *dbgi = get_irn_dbg_info(node);
3813 long proj = get_Proj_proj(node);
3815 if (proj == pn_be_SubSP_res) {
3816 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3817 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3819 } else if (proj == pn_be_SubSP_M) {
3820 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3824 return new_rd_Unknown(irg, get_irn_mode(node));
3828 * Transform and renumber the Projs from a Load.
3830 static ir_node *gen_Proj_Load(ir_node *node) {
3831 ir_node *block = be_transform_node(get_nodes_block(node));
3832 ir_node *pred = get_Proj_pred(node);
3833 ir_node *new_pred = be_transform_node(pred);
3834 ir_graph *irg = current_ir_graph;
3835 dbg_info *dbgi = get_irn_dbg_info(node);
3836 long proj = get_Proj_proj(node);
3838 /* renumber the proj */
3839 if (is_ia32_Load(new_pred)) {
3840 if (proj == pn_Load_res) {
3841 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3842 } else if (proj == pn_Load_M) {
3843 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3845 } else if (is_ia32_xLoad(new_pred)) {
3846 if (proj == pn_Load_res) {
3847 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3848 } else if (proj == pn_Load_M) {
3849 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3851 } else if (is_ia32_vfld(new_pred)) {
3852 if (proj == pn_Load_res) {
3853 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3854 } else if (proj == pn_Load_M) {
3855 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3860 return new_rd_Unknown(irg, get_irn_mode(node));
3864 * Transform and renumber the Projs from a DivMod like instruction.
3866 static ir_node *gen_Proj_DivMod(ir_node *node) {
3867 ir_node *block = be_transform_node(get_nodes_block(node));
3868 ir_node *pred = get_Proj_pred(node);
3869 ir_node *new_pred = be_transform_node(pred);
3870 ir_graph *irg = current_ir_graph;
3871 dbg_info *dbgi = get_irn_dbg_info(node);
3872 ir_mode *mode = get_irn_mode(node);
3873 long proj = get_Proj_proj(node);
3875 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3877 switch (get_irn_opcode(pred)) {
3881 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3883 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3891 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3893 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3901 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3902 case pn_DivMod_res_div:
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3904 case pn_DivMod_res_mod:
3905 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3915 return new_rd_Unknown(irg, mode);
3919 * Transform and renumber the Projs from a CopyB.
3921 static ir_node *gen_Proj_CopyB(ir_node *node) {
3922 ir_node *block = be_transform_node(get_nodes_block(node));
3923 ir_node *pred = get_Proj_pred(node);
3924 ir_node *new_pred = be_transform_node(pred);
3925 ir_graph *irg = current_ir_graph;
3926 dbg_info *dbgi = get_irn_dbg_info(node);
3927 ir_mode *mode = get_irn_mode(node);
3928 long proj = get_Proj_proj(node);
3931 case pn_CopyB_M_regular:
3932 if (is_ia32_CopyB_i(new_pred)) {
3933 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3934 } else if (is_ia32_CopyB(new_pred)) {
3935 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3943 return new_rd_Unknown(irg, mode);
3947 * Transform and renumber the Projs from a vfdiv.
3949 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3950 ir_node *block = be_transform_node(get_nodes_block(node));
3951 ir_node *pred = get_Proj_pred(node);
3952 ir_node *new_pred = be_transform_node(pred);
3953 ir_graph *irg = current_ir_graph;
3954 dbg_info *dbgi = get_irn_dbg_info(node);
3955 ir_mode *mode = get_irn_mode(node);
3956 long proj = get_Proj_proj(node);
3959 case pn_ia32_l_vfdiv_M:
3960 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3961 case pn_ia32_l_vfdiv_res:
3962 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3967 return new_rd_Unknown(irg, mode);
3971 * Transform and renumber the Projs from a Quot.
3973 static ir_node *gen_Proj_Quot(ir_node *node) {
3974 ir_node *block = be_transform_node(get_nodes_block(node));
3975 ir_node *pred = get_Proj_pred(node);
3976 ir_node *new_pred = be_transform_node(pred);
3977 ir_graph *irg = current_ir_graph;
3978 dbg_info *dbgi = get_irn_dbg_info(node);
3979 ir_mode *mode = get_irn_mode(node);
3980 long proj = get_Proj_proj(node);
3984 if (is_ia32_xDiv(new_pred)) {
3985 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3986 } else if (is_ia32_vfdiv(new_pred)) {
3987 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3991 if (is_ia32_xDiv(new_pred)) {
3992 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3993 } else if (is_ia32_vfdiv(new_pred)) {
3994 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4002 return new_rd_Unknown(irg, mode);
4006 * Transform the Thread Local Storage Proj.
4008 static ir_node *gen_Proj_tls(ir_node *node) {
4009 ir_node *block = be_transform_node(get_nodes_block(node));
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = NULL;
4012 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4018 * Transform the Projs from a be_Call.
4020 static ir_node *gen_Proj_be_Call(ir_node *node) {
4021 ir_node *block = be_transform_node(get_nodes_block(node));
4022 ir_node *call = get_Proj_pred(node);
4023 ir_node *new_call = be_transform_node(call);
4024 ir_graph *irg = current_ir_graph;
4025 dbg_info *dbgi = get_irn_dbg_info(node);
4026 long proj = get_Proj_proj(node);
4027 ir_mode *mode = get_irn_mode(node);
4029 const arch_register_class_t *cls;
4031 /* The following is kinda tricky: If we're using SSE, then we have to
4032 * move the result value of the call in floating point registers to an
4033 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4034 * after the call, we have to make sure to correctly make the
4035 * MemProj and the result Proj use these 2 nodes
4037 if (proj == pn_be_Call_M_regular) {
4038 // get new node for result, are we doing the sse load/store hack?
4039 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4040 ir_node *call_res_new;
4041 ir_node *call_res_pred = NULL;
4043 if (call_res != NULL) {
4044 call_res_new = be_transform_node(call_res);
4045 call_res_pred = get_Proj_pred(call_res_new);
4048 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4049 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4051 assert(is_ia32_xLoad(call_res_pred));
4052 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
4055 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
4057 ir_node *frame = get_irg_frame(irg);
4058 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4060 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4062 const arch_register_class_t *cls;
4064 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
4065 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4067 /* store st(0) onto stack */
4068 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
4070 set_ia32_ls_mode(fstp, mode);
4071 set_ia32_op_type(fstp, ia32_AddrModeD);
4072 set_ia32_use_frame(fstp);
4073 set_ia32_am_flavour(fstp, ia32_am_B);
4074 set_ia32_am_support(fstp, ia32_am_Dest);
4076 /* load into SSE register */
4077 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4078 set_ia32_ls_mode(sse_load, mode);
4079 set_ia32_op_type(sse_load, ia32_AddrModeS);
4080 set_ia32_use_frame(sse_load);
4081 set_ia32_am_flavour(sse_load, ia32_am_B);
4082 set_ia32_am_support(sse_load, ia32_am_Source);
4084 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
4086 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4088 /* get a Proj representing a caller save register */
4089 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4090 assert(is_Proj(p) && "Proj expected.");
4092 /* user of the the proj is the Keep */
4093 p = get_edge_src_irn(get_irn_out_edge_first(p));
4094 assert(be_is_Keep(p) && "Keep expected.");
4096 /* keep the result */
4097 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
4098 keepin[0] = sse_load;
4099 be_new_Keep(cls, irg, block, 1, keepin);
4104 /* transform call modes */
4105 if (mode_is_data(mode)) {
4106 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4110 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4114 * Transform the Projs from a Cmp.
4116 static ir_node *gen_Proj_Cmp(ir_node *node)
4118 /* normally Cmps are processed when looking at Cond nodes, but this case
4119 * can happen in complicated Psi conditions */
4121 ir_graph *irg = current_ir_graph;
4122 dbg_info *dbgi = get_irn_dbg_info(node);
4123 ir_node *block = be_transform_node(get_nodes_block(node));
4124 ir_node *cmp = get_Proj_pred(node);
4125 long pnc = get_Proj_proj(node);
4126 ir_node *cmp_left = get_Cmp_left(cmp);
4127 ir_node *cmp_right = get_Cmp_right(cmp);
4128 ir_node *new_cmp_left;
4129 ir_node *new_cmp_right;
4130 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4131 ir_node *nomem = new_rd_NoMem(irg);
4132 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4135 assert(!mode_is_float(cmp_mode));
4137 /* (a != b) -> (a ^ b) */
4138 if(pnc == pn_Cmp_Lg) {
4139 if(is_Const_0(cmp_left)) {
4140 new_op = be_transform_node(cmp_right);
4141 } else if(is_Const_0(cmp_right)) {
4142 new_op = be_transform_node(cmp_left);
4144 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4150 * (a == b) -> !(a ^ b)
4151 * (a < 0) -> (a & 0x80000000)
4152 * (a <= 0) -> !(a & 0x7fffffff)
4153 * (a > 0) -> (a & 0x7fffffff)
4154 * (a >= 0) -> !(a & 0x80000000)
4157 if(!mode_is_signed(cmp_mode)) {
4158 pnc |= ia32_pn_Cmp_Unsigned;
4161 new_cmp_right = try_create_Immediate(cmp_right, 0);
4162 if(new_cmp_right == NULL) {
4163 new_cmp_right = try_create_Immediate(cmp_left, 0);
4164 if(new_cmp_right != NULL) {
4165 pnc = get_inversed_pnc(pnc);
4166 new_cmp_left = be_transform_node(cmp_right);
4169 new_cmp_left = be_transform_node(cmp_left);
4171 if(new_cmp_right == NULL) {
4172 new_cmp_left = be_transform_node(cmp_left);
4173 new_cmp_right = be_transform_node(cmp_right);
4176 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4177 new_cmp_right, nomem, pnc);
4178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4184 * Transform and potentially renumber Proj nodes.
4186 static ir_node *gen_Proj(ir_node *node) {
4187 ir_graph *irg = current_ir_graph;
4188 dbg_info *dbgi = get_irn_dbg_info(node);
4189 ir_node *pred = get_Proj_pred(node);
4190 long proj = get_Proj_proj(node);
4192 if (is_Store(pred) || be_is_FrameStore(pred)) {
4193 if (proj == pn_Store_M) {
4194 return be_transform_node(pred);
4197 return new_r_Bad(irg);
4199 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4200 return gen_Proj_Load(node);
4201 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4202 return gen_Proj_DivMod(node);
4203 } else if (is_CopyB(pred)) {
4204 return gen_Proj_CopyB(node);
4205 } else if (is_Quot(pred)) {
4206 return gen_Proj_Quot(node);
4207 } else if (is_ia32_l_vfdiv(pred)) {
4208 return gen_Proj_l_vfdiv(node);
4209 } else if (be_is_SubSP(pred)) {
4210 return gen_Proj_be_SubSP(node);
4211 } else if (be_is_AddSP(pred)) {
4212 return gen_Proj_be_AddSP(node);
4213 } else if (be_is_Call(pred)) {
4214 return gen_Proj_be_Call(node);
4215 } else if (is_Cmp(pred)) {
4216 return gen_Proj_Cmp(node);
4217 } else if (get_irn_op(pred) == op_Start) {
4218 if (proj == pn_Start_X_initial_exec) {
4219 ir_node *block = get_nodes_block(pred);
4222 /* we exchange the ProjX with a jump */
4223 block = be_transform_node(block);
4224 jump = new_rd_Jmp(dbgi, irg, block);
4225 ir_fprintf(stderr, "created jump: %+F\n", jump);
4228 if (node == be_get_old_anchor(anchor_tls)) {
4229 return gen_Proj_tls(node);
4232 ir_node *new_pred = be_transform_node(pred);
4233 ir_node *block = be_transform_node(get_nodes_block(node));
4234 ir_mode *mode = get_irn_mode(node);
4235 if (mode_needs_gp_reg(mode)) {
4236 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4237 get_Proj_proj(node));
4238 #ifdef DEBUG_libfirm
4239 new_proj->node_nr = node->node_nr;
4245 return be_duplicate_node(node);
4249 * Enters all transform functions into the generic pointer
4251 static void register_transformers(void) {
4252 ir_op *op_Max, *op_Min, *op_Mulh;
4254 /* first clear the generic function pointer for all ops */
4255 clear_irp_opcodes_generic_func();
4257 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4258 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4295 /* transform ops from intrinsic lowering */
4315 /* GEN(ia32_l_vfist); TODO */
4317 GEN(ia32_l_X87toSSE);
4318 GEN(ia32_l_SSEtoX87);
4323 /* we should never see these nodes */
4338 /* handle generic backend nodes */
4349 /* set the register for all Unknown nodes */
4352 op_Max = get_op_Max();
4355 op_Min = get_op_Min();
4358 op_Mulh = get_op_Mulh();
4367 * Pre-transform all unknown and noreg nodes.
4369 static void ia32_pretransform_node(void *arch_cg) {
4370 ia32_code_gen_t *cg = arch_cg;
4372 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4373 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4374 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4375 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4376 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4377 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4380 /* do the transformation */
4381 void ia32_transform_graph(ia32_code_gen_t *cg) {
4382 register_transformers();
4384 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4387 void ia32_init_transform(void)
4389 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");