2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode.h"
51 #include "../besched.h"
53 #include "../beutil.h"
55 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_common_transform.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
66 #include "ia32_address_mode.h"
67 #include "ia32_architecture.h"
69 #include "gen_ia32_regalloc_if.h"
71 /* define this to construct SSE constants instead of load them */
72 #undef CONSTRUCT_SSE_CONST
75 #define SFP_SIGN "0x80000000"
76 #define DFP_SIGN "0x8000000000000000"
77 #define SFP_ABS "0x7FFFFFFF"
78 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
79 #define DFP_INTMAX "9223372036854775807"
80 #define ULL_BIAS "18446744073709551616"
82 #define ENT_SFP_SIGN "C_ia32_sfp_sign"
83 #define ENT_DFP_SIGN "C_ia32_dfp_sign"
84 #define ENT_SFP_ABS "C_ia32_sfp_abs"
85 #define ENT_DFP_ABS "C_ia32_dfp_abs"
86 #define ENT_ULL_BIAS "C_ia32_ull_bias"
88 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
89 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
91 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
93 static ir_node *initial_fpcw = NULL;
94 int ia32_no_pic_adjust;
96 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
97 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
100 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
101 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
104 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
105 ir_node *op1, ir_node *op2);
107 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
108 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
110 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
111 ir_node *base, ir_node *index, ir_node *mem);
113 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
114 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
117 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
122 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
123 dbg_info *dbgi, ir_node *block,
124 ir_node *op, ir_node *orig_node);
126 /* its enough to have those once */
127 static ir_node *nomem, *noreg_GP;
129 /** a list to postprocess all calls */
130 static ir_node **call_list;
131 static ir_type **call_types;
133 /** Return non-zero is a node represents the 0 constant. */
134 static bool is_Const_0(ir_node *node)
136 return is_Const(node) && is_Const_null(node);
139 /** Return non-zero is a node represents the 1 constant. */
140 static bool is_Const_1(ir_node *node)
142 return is_Const(node) && is_Const_one(node);
145 /** Return non-zero is a node represents the -1 constant. */
146 static bool is_Const_Minus_1(ir_node *node)
148 return is_Const(node) && is_Const_all_one(node);
152 * returns true if constant can be created with a simple float command
154 static bool is_simple_x87_Const(ir_node *node)
156 ir_tarval *tv = get_Const_tarval(node);
157 if (tarval_is_null(tv) || tarval_is_one(tv))
160 /* TODO: match all the other float constants */
165 * returns true if constant can be created with a simple float command
167 static bool is_simple_sse_Const(ir_node *node)
169 ir_tarval *tv = get_Const_tarval(node);
170 ir_mode *mode = get_tarval_mode(tv);
175 if (tarval_is_null(tv)
176 #ifdef CONSTRUCT_SSE_CONST
181 #ifdef CONSTRUCT_SSE_CONST
182 if (mode == mode_D) {
183 unsigned val = get_tarval_sub_bits(tv, 0) |
184 (get_tarval_sub_bits(tv, 1) << 8) |
185 (get_tarval_sub_bits(tv, 2) << 16) |
186 (get_tarval_sub_bits(tv, 3) << 24);
188 /* lower 32bit are zero, really a 32bit constant */
191 #endif /* CONSTRUCT_SSE_CONST */
192 /* TODO: match all the other float constants */
197 * return NoREG or pic_base in case of PIC.
198 * This is necessary as base address for newly created symbols
200 static ir_node *get_symconst_base(void)
202 ir_graph *irg = current_ir_graph;
204 if (be_get_irg_options(irg)->pic) {
205 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
206 return arch_env->impl->get_pic_base(irg);
213 * Transforms a Const.
215 static ir_node *gen_Const(ir_node *node)
217 ir_node *old_block = get_nodes_block(node);
218 ir_node *block = be_transform_node(old_block);
219 dbg_info *dbgi = get_irn_dbg_info(node);
220 ir_mode *mode = get_irn_mode(node);
222 assert(is_Const(node));
224 if (mode_is_float(mode)) {
230 if (ia32_cg_config.use_sse2) {
231 ir_tarval *tv = get_Const_tarval(node);
232 if (tarval_is_null(tv)) {
233 load = new_bd_ia32_xZero(dbgi, block);
234 set_ia32_ls_mode(load, mode);
236 #ifdef CONSTRUCT_SSE_CONST
237 } else if (tarval_is_one(tv)) {
238 int cnst = mode == mode_F ? 26 : 55;
239 ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
240 ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
241 ir_node *pslld, *psrld;
243 load = new_bd_ia32_xAllOnes(dbgi, block);
244 set_ia32_ls_mode(load, mode);
245 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
246 set_ia32_ls_mode(pslld, mode);
247 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
248 set_ia32_ls_mode(psrld, mode);
250 #endif /* CONSTRUCT_SSE_CONST */
251 } else if (mode == mode_F) {
252 /* we can place any 32bit constant by using a movd gp, sse */
253 unsigned val = get_tarval_sub_bits(tv, 0) |
254 (get_tarval_sub_bits(tv, 1) << 8) |
255 (get_tarval_sub_bits(tv, 2) << 16) |
256 (get_tarval_sub_bits(tv, 3) << 24);
257 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
258 load = new_bd_ia32_xMovd(dbgi, block, cnst);
259 set_ia32_ls_mode(load, mode);
262 #ifdef CONSTRUCT_SSE_CONST
263 if (mode == mode_D) {
264 unsigned val = get_tarval_sub_bits(tv, 0) |
265 (get_tarval_sub_bits(tv, 1) << 8) |
266 (get_tarval_sub_bits(tv, 2) << 16) |
267 (get_tarval_sub_bits(tv, 3) << 24);
269 ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
270 ir_node *cnst, *psllq;
272 /* fine, lower 32bit are zero, produce 32bit value */
273 val = get_tarval_sub_bits(tv, 4) |
274 (get_tarval_sub_bits(tv, 5) << 8) |
275 (get_tarval_sub_bits(tv, 6) << 16) |
276 (get_tarval_sub_bits(tv, 7) << 24);
277 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
278 load = new_bd_ia32_xMovd(dbgi, block, cnst);
279 set_ia32_ls_mode(load, mode);
280 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
281 set_ia32_ls_mode(psllq, mode);
286 #endif /* CONSTRUCT_SSE_CONST */
287 floatent = ia32_create_float_const_entity(node);
289 base = get_symconst_base();
290 load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
292 set_ia32_op_type(load, ia32_AddrModeS);
293 set_ia32_am_sc(load, floatent);
294 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
295 res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
298 if (is_Const_null(node)) {
299 load = new_bd_ia32_vfldz(dbgi, block);
301 set_ia32_ls_mode(load, mode);
302 } else if (is_Const_one(node)) {
303 load = new_bd_ia32_vfld1(dbgi, block);
305 set_ia32_ls_mode(load, mode);
310 floatent = ia32_create_float_const_entity(node);
311 /* create_float_const_ent is smart and sometimes creates
313 ls_mode = get_type_mode(get_entity_type(floatent));
314 base = get_symconst_base();
315 load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
317 set_ia32_op_type(load, ia32_AddrModeS);
318 set_ia32_am_sc(load, floatent);
319 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
320 res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
323 #ifdef CONSTRUCT_SSE_CONST
325 #endif /* CONSTRUCT_SSE_CONST */
326 SET_IA32_ORIG_NODE(load, node);
328 be_dep_on_frame(load);
330 } else { /* non-float mode */
332 ir_tarval *tv = get_Const_tarval(node);
335 tv = tarval_convert_to(tv, mode_Iu);
337 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
339 panic("couldn't convert constant tarval (%+F)", node);
341 val = get_tarval_long(tv);
343 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
344 SET_IA32_ORIG_NODE(cnst, node);
346 be_dep_on_frame(cnst);
352 * Transforms a SymConst.
354 static ir_node *gen_SymConst(ir_node *node)
356 ir_node *old_block = get_nodes_block(node);
357 ir_node *block = be_transform_node(old_block);
358 dbg_info *dbgi = get_irn_dbg_info(node);
359 ir_mode *mode = get_irn_mode(node);
362 if (mode_is_float(mode)) {
363 if (ia32_cg_config.use_sse2)
364 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
366 cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
367 set_ia32_am_sc(cnst, get_SymConst_entity(node));
368 set_ia32_use_frame(cnst);
372 if (get_SymConst_kind(node) != symconst_addr_ent) {
373 panic("backend only support symconst_addr_ent (at %+F)", node);
375 entity = get_SymConst_entity(node);
376 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
379 SET_IA32_ORIG_NODE(cnst, node);
381 be_dep_on_frame(cnst);
386 * Create a float type for the given mode and cache it.
388 * @param mode the mode for the float type (might be integer mode for SSE2 types)
389 * @param align alignment
391 static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
397 if (mode == mode_Iu) {
398 static ir_type *int_Iu[16] = {NULL, };
400 if (int_Iu[align] == NULL) {
401 int_Iu[align] = tp = new_type_primitive(mode);
402 /* set the specified alignment */
403 set_type_alignment_bytes(tp, align);
405 return int_Iu[align];
406 } else if (mode == mode_Lu) {
407 static ir_type *int_Lu[16] = {NULL, };
409 if (int_Lu[align] == NULL) {
410 int_Lu[align] = tp = new_type_primitive(mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, align);
414 return int_Lu[align];
415 } else if (mode == mode_F) {
416 static ir_type *float_F[16] = {NULL, };
418 if (float_F[align] == NULL) {
419 float_F[align] = tp = new_type_primitive(mode);
420 /* set the specified alignment */
421 set_type_alignment_bytes(tp, align);
423 return float_F[align];
424 } else if (mode == mode_D) {
425 static ir_type *float_D[16] = {NULL, };
427 if (float_D[align] == NULL) {
428 float_D[align] = tp = new_type_primitive(mode);
429 /* set the specified alignment */
430 set_type_alignment_bytes(tp, align);
432 return float_D[align];
434 static ir_type *float_E[16] = {NULL, };
436 if (float_E[align] == NULL) {
437 float_E[align] = tp = new_type_primitive(mode);
438 /* set the specified alignment */
439 set_type_alignment_bytes(tp, align);
441 return float_E[align];
446 * Create a float[2] array type for the given atomic type.
448 * @param tp the atomic type
450 static ir_type *ia32_create_float_array(ir_type *tp)
452 ir_mode *mode = get_type_mode(tp);
453 unsigned align = get_type_alignment_bytes(tp);
458 if (mode == mode_F) {
459 static ir_type *float_F[16] = {NULL, };
461 if (float_F[align] != NULL)
462 return float_F[align];
463 arr = float_F[align] = new_type_array(1, tp);
464 } else if (mode == mode_D) {
465 static ir_type *float_D[16] = {NULL, };
467 if (float_D[align] != NULL)
468 return float_D[align];
469 arr = float_D[align] = new_type_array(1, tp);
471 static ir_type *float_E[16] = {NULL, };
473 if (float_E[align] != NULL)
474 return float_E[align];
475 arr = float_E[align] = new_type_array(1, tp);
477 set_type_alignment_bytes(arr, align);
478 set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
479 set_type_state(arr, layout_fixed);
483 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
484 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
486 static const struct {
487 const char *ent_name;
488 const char *cnst_str;
491 } names [ia32_known_const_max] = {
492 { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
493 { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
494 { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
495 { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
496 { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
498 static ir_entity *ent_cache[ia32_known_const_max];
500 const char *ent_name, *cnst_str;
506 ent_name = names[kct].ent_name;
507 if (! ent_cache[kct]) {
508 cnst_str = names[kct].cnst_str;
510 switch (names[kct].mode) {
511 case 0: mode = mode_Iu; break;
512 case 1: mode = mode_Lu; break;
513 default: mode = mode_F; break;
515 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
516 tp = ia32_create_float_type(mode, names[kct].align);
518 if (kct == ia32_ULLBIAS)
519 tp = ia32_create_float_array(tp);
520 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
522 set_entity_ld_ident(ent, get_entity_ident(ent));
523 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
524 set_entity_visibility(ent, ir_visibility_private);
526 if (kct == ia32_ULLBIAS) {
527 ir_initializer_t *initializer = create_initializer_compound(2);
529 set_initializer_compound_value(initializer, 0,
530 create_initializer_tarval(get_mode_null(mode)));
531 set_initializer_compound_value(initializer, 1,
532 create_initializer_tarval(tv));
534 set_entity_initializer(ent, initializer);
536 set_entity_initializer(ent, create_initializer_tarval(tv));
539 /* cache the entry */
540 ent_cache[kct] = ent;
543 return ent_cache[kct];
547 * return true if the node is a Proj(Load) and could be used in source address
548 * mode for another node. Will return only true if the @p other node is not
549 * dependent on the memory of the Load (for binary operations use the other
550 * input here, for unary operations use NULL).
552 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
553 ir_node *other, ir_node *other2, match_flags_t flags)
558 /* float constants are always available */
559 if (is_Const(node)) {
560 ir_mode *mode = get_irn_mode(node);
561 if (mode_is_float(mode)) {
562 if (ia32_cg_config.use_sse2) {
563 if (is_simple_sse_Const(node))
566 if (is_simple_x87_Const(node))
569 if (get_irn_n_edges(node) > 1)
577 load = get_Proj_pred(node);
578 pn = get_Proj_proj(node);
579 if (!is_Load(load) || pn != pn_Load_res)
581 if (get_nodes_block(load) != block)
583 /* we only use address mode if we're the only user of the load */
584 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
586 /* in some edge cases with address mode we might reach the load normally
587 * and through some AM sequence, if it is already materialized then we
588 * can't create an AM node from it */
589 if (be_is_transformed(node))
592 /* don't do AM if other node inputs depend on the load (via mem-proj) */
593 if (other != NULL && ia32_prevents_AM(block, load, other))
596 if (other2 != NULL && ia32_prevents_AM(block, load, other2))
602 typedef struct ia32_address_mode_t ia32_address_mode_t;
603 struct ia32_address_mode_t {
608 ia32_op_type_t op_type;
612 unsigned commutative : 1;
613 unsigned ins_permuted : 1;
616 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
618 /* construct load address */
619 memset(addr, 0, sizeof(addr[0]));
620 ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
622 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
623 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
624 addr->mem = be_transform_node(mem);
627 static void build_address(ia32_address_mode_t *am, ir_node *node,
628 ia32_create_am_flags_t flags)
630 ia32_address_t *addr = &am->addr;
636 /* floating point immediates */
637 if (is_Const(node)) {
638 ir_entity *entity = ia32_create_float_const_entity(node);
639 addr->base = get_symconst_base();
640 addr->index = noreg_GP;
642 addr->symconst_ent = entity;
644 am->ls_mode = get_type_mode(get_entity_type(entity));
645 am->pinned = op_pin_state_floats;
649 load = get_Proj_pred(node);
650 ptr = get_Load_ptr(load);
651 mem = get_Load_mem(load);
652 new_mem = be_transform_node(mem);
653 am->pinned = get_irn_pinned(load);
654 am->ls_mode = get_Load_mode(load);
655 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
658 /* construct load address */
659 ia32_create_address_mode(addr, ptr, flags);
661 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
662 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
666 static void set_address(ir_node *node, const ia32_address_t *addr)
668 set_ia32_am_scale(node, addr->scale);
669 set_ia32_am_sc(node, addr->symconst_ent);
670 set_ia32_am_offs_int(node, addr->offset);
671 if (addr->symconst_sign)
672 set_ia32_am_sc_sign(node);
674 set_ia32_use_frame(node);
675 set_ia32_frame_ent(node, addr->frame_entity);
679 * Apply attributes of a given address mode to a node.
681 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
683 set_address(node, &am->addr);
685 set_ia32_op_type(node, am->op_type);
686 set_ia32_ls_mode(node, am->ls_mode);
687 if (am->pinned == op_pin_state_pinned) {
688 /* beware: some nodes are already pinned and did not allow to change the state */
689 if (get_irn_pinned(node) != op_pin_state_pinned)
690 set_irn_pinned(node, op_pin_state_pinned);
693 set_ia32_commutative(node);
697 * Check, if a given node is a Down-Conv, ie. a integer Conv
698 * from a mode with a mode with more bits to a mode with lesser bits.
699 * Moreover, we return only true if the node has not more than 1 user.
701 * @param node the node
702 * @return non-zero if node is a Down-Conv
704 static int is_downconv(const ir_node *node)
712 /* we only want to skip the conv when we're the only user
713 * (because this test is used in the context of address-mode selection
714 * and we don't want to use address mode for multiple users) */
715 if (get_irn_n_edges(node) > 1)
718 src_mode = get_irn_mode(get_Conv_op(node));
719 dest_mode = get_irn_mode(node);
721 ia32_mode_needs_gp_reg(src_mode) &&
722 ia32_mode_needs_gp_reg(dest_mode) &&
723 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
726 /** Skip all Down-Conv's on a given node and return the resulting node. */
727 ir_node *ia32_skip_downconv(ir_node *node)
729 while (is_downconv(node))
730 node = get_Conv_op(node);
735 static bool is_sameconv(ir_node *node)
743 /* we only want to skip the conv when we're the only user
744 * (because this test is used in the context of address-mode selection
745 * and we don't want to use address mode for multiple users) */
746 if (get_irn_n_edges(node) > 1)
749 src_mode = get_irn_mode(get_Conv_op(node));
750 dest_mode = get_irn_mode(node);
752 ia32_mode_needs_gp_reg(src_mode) &&
753 ia32_mode_needs_gp_reg(dest_mode) &&
754 get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
757 /** Skip all signedness convs */
758 static ir_node *ia32_skip_sameconv(ir_node *node)
760 while (is_sameconv(node))
761 node = get_Conv_op(node);
766 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
768 ir_mode *mode = get_irn_mode(node);
773 if (mode_is_signed(mode)) {
778 block = get_nodes_block(node);
779 dbgi = get_irn_dbg_info(node);
781 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
785 * matches operands of a node into ia32 addressing/operand modes. This covers
786 * usage of source address mode, immediates, operations with non 32-bit modes,
788 * The resulting data is filled into the @p am struct. block is the block
789 * of the node whose arguments are matched. op1, op2 are the first and second
790 * input that are matched (op1 may be NULL). other_op is another unrelated
791 * input that is not matched! but which is needed sometimes to check if AM
792 * for op1/op2 is legal.
793 * @p flags describes the supported modes of the operation in detail.
795 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
796 ir_node *op1, ir_node *op2, ir_node *other_op,
799 ia32_address_t *addr = &am->addr;
800 ir_mode *mode = get_irn_mode(op2);
801 int mode_bits = get_mode_size_bits(mode);
802 ir_node *new_op1, *new_op2;
804 unsigned commutative;
805 int use_am_and_immediates;
808 memset(am, 0, sizeof(am[0]));
810 commutative = (flags & match_commutative) != 0;
811 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
812 use_am = (flags & match_am) != 0;
813 use_immediate = (flags & match_immediate) != 0;
814 assert(!use_am_and_immediates || use_immediate);
817 assert(!commutative || op1 != NULL);
818 assert(use_am || !(flags & match_8bit_am));
819 assert(use_am || !(flags & match_16bit_am));
821 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
822 (mode_bits == 16 && !(flags & match_16bit_am))) {
826 /* we can simply skip downconvs for mode neutral nodes: the upper bits
827 * can be random for these operations */
828 if (flags & match_mode_neutral) {
829 op2 = ia32_skip_downconv(op2);
831 op1 = ia32_skip_downconv(op1);
834 op2 = ia32_skip_sameconv(op2);
836 op1 = ia32_skip_sameconv(op1);
840 /* match immediates. firm nodes are normalized: constants are always on the
843 if (!(flags & match_try_am) && use_immediate) {
844 new_op2 = ia32_try_create_Immediate(op2, 0);
847 if (new_op2 == NULL &&
848 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
849 build_address(am, op2, ia32_create_am_normal);
850 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
851 if (mode_is_float(mode)) {
852 new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
856 am->op_type = ia32_AddrModeS;
857 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
859 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
861 build_address(am, op1, ia32_create_am_normal);
863 if (mode_is_float(mode)) {
864 noreg = ia32_new_NoReg_vfp(current_ir_graph);
869 if (new_op2 != NULL) {
872 new_op1 = be_transform_node(op2);
874 am->ins_permuted = true;
876 am->op_type = ia32_AddrModeS;
879 am->op_type = ia32_Normal;
881 if (flags & match_try_am) {
887 mode = get_irn_mode(op2);
888 if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
889 new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
891 new_op2 = create_upconv(op2, NULL);
892 am->ls_mode = mode_Iu;
894 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
896 new_op2 = be_transform_node(op2);
897 am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
900 if (addr->base == NULL)
901 addr->base = noreg_GP;
902 if (addr->index == NULL)
903 addr->index = noreg_GP;
904 if (addr->mem == NULL)
907 am->new_op1 = new_op1;
908 am->new_op2 = new_op2;
909 am->commutative = commutative;
913 * "Fixes" a node that uses address mode by turning it into mode_T
914 * and returning a pn_ia32_res Proj.
916 * @param node the node
917 * @param am its address mode
919 * @return a Proj(pn_ia32_res) if a memory address mode is used,
922 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
927 if (am->mem_proj == NULL)
930 /* we have to create a mode_T so the old MemProj can attach to us */
931 mode = get_irn_mode(node);
932 load = get_Proj_pred(am->mem_proj);
934 be_set_transformed_node(load, node);
936 if (mode != mode_T) {
937 set_irn_mode(node, mode_T);
938 return new_rd_Proj(NULL, node, mode, pn_ia32_res);
945 * Construct a standard binary operation, set AM and immediate if required.
947 * @param node The original node for which the binop is created
948 * @param op1 The first operand
949 * @param op2 The second operand
950 * @param func The node constructor function
951 * @return The constructed ia32 node.
953 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
954 construct_binop_func *func, match_flags_t flags)
957 ir_node *block, *new_block, *new_node;
958 ia32_address_mode_t am;
959 ia32_address_t *addr = &am.addr;
961 block = get_nodes_block(node);
962 match_arguments(&am, block, op1, op2, NULL, flags);
964 dbgi = get_irn_dbg_info(node);
965 new_block = be_transform_node(block);
966 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
967 am.new_op1, am.new_op2);
968 set_am_attributes(new_node, &am);
969 /* we can't use source address mode anymore when using immediates */
970 if (!(flags & match_am_and_immediates) &&
971 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
972 set_ia32_am_support(new_node, ia32_am_none);
973 SET_IA32_ORIG_NODE(new_node, node);
975 new_node = fix_mem_proj(new_node, &am);
981 * Generic names for the inputs of an ia32 binary op.
984 n_ia32_l_binop_left, /**< ia32 left input */
985 n_ia32_l_binop_right, /**< ia32 right input */
986 n_ia32_l_binop_eflags /**< ia32 eflags input */
988 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
989 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
990 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
991 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
992 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
993 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
996 * Construct a binary operation which also consumes the eflags.
998 * @param node The node to transform
999 * @param func The node constructor function
1000 * @param flags The match flags
1001 * @return The constructor ia32 node
1003 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
1004 match_flags_t flags)
1006 ir_node *src_block = get_nodes_block(node);
1007 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
1008 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
1009 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
1011 ir_node *block, *new_node, *new_eflags;
1012 ia32_address_mode_t am;
1013 ia32_address_t *addr = &am.addr;
1015 match_arguments(&am, src_block, op1, op2, eflags, flags);
1017 dbgi = get_irn_dbg_info(node);
1018 block = be_transform_node(src_block);
1019 new_eflags = be_transform_node(eflags);
1020 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
1021 am.new_op1, am.new_op2, new_eflags);
1022 set_am_attributes(new_node, &am);
1023 /* we can't use source address mode anymore when using immediates */
1024 if (!(flags & match_am_and_immediates) &&
1025 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
1026 set_ia32_am_support(new_node, ia32_am_none);
1027 SET_IA32_ORIG_NODE(new_node, node);
1029 new_node = fix_mem_proj(new_node, &am);
1034 static ir_node *get_fpcw(void)
1037 if (initial_fpcw != NULL)
1038 return initial_fpcw;
1040 fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph),
1041 &ia32_registers[REG_FPCW]);
1042 initial_fpcw = be_transform_node(fpcw);
1044 return initial_fpcw;
1048 * Construct a standard binary operation, set AM and immediate if required.
1050 * @param op1 The first operand
1051 * @param op2 The second operand
1052 * @param func The node constructor function
1053 * @return The constructed ia32 node.
1055 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1056 construct_binop_float_func *func)
1058 ir_mode *mode = get_irn_mode(node);
1060 ir_node *block, *new_block, *new_node;
1061 ia32_address_mode_t am;
1062 ia32_address_t *addr = &am.addr;
1063 ia32_x87_attr_t *attr;
1064 /* All operations are considered commutative, because there are reverse
1066 match_flags_t flags = match_commutative;
1068 /* happens for div nodes... */
1069 if (mode == mode_T) {
1071 mode = get_Div_resmode(node);
1073 panic("can't determine mode");
1076 /* cannot use address mode with long double on x87 */
1077 if (get_mode_size_bits(mode) <= 64)
1080 block = get_nodes_block(node);
1081 match_arguments(&am, block, op1, op2, NULL, flags);
1083 dbgi = get_irn_dbg_info(node);
1084 new_block = be_transform_node(block);
1085 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1086 am.new_op1, am.new_op2, get_fpcw());
1087 set_am_attributes(new_node, &am);
1089 attr = get_ia32_x87_attr(new_node);
1090 attr->attr.data.ins_permuted = am.ins_permuted;
1092 SET_IA32_ORIG_NODE(new_node, node);
1094 new_node = fix_mem_proj(new_node, &am);
1100 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1102 * @param op1 The first operand
1103 * @param op2 The second operand
1104 * @param func The node constructor function
1105 * @return The constructed ia32 node.
1107 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1108 construct_shift_func *func,
1109 match_flags_t flags)
1112 ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
1114 assert(! mode_is_float(get_irn_mode(node)));
1115 assert(flags & match_immediate);
1116 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
1118 if (flags & match_mode_neutral) {
1119 op1 = ia32_skip_downconv(op1);
1120 new_op1 = be_transform_node(op1);
1121 } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
1122 new_op1 = create_upconv(op1, node);
1124 new_op1 = be_transform_node(op1);
1127 /* the shift amount can be any mode that is bigger than 5 bits, since all
1128 * other bits are ignored anyway */
1129 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1130 ir_node *const op = get_Conv_op(op2);
1131 if (mode_is_float(get_irn_mode(op)))
1134 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1136 new_op2 = create_immediate_or_transform(op2, 0);
1138 dbgi = get_irn_dbg_info(node);
1139 block = get_nodes_block(node);
1140 new_block = be_transform_node(block);
1141 new_node = func(dbgi, new_block, new_op1, new_op2);
1142 SET_IA32_ORIG_NODE(new_node, node);
1144 /* lowered shift instruction may have a dependency operand, handle it here */
1145 if (get_irn_arity(node) == 3) {
1146 /* we have a dependency */
1147 ir_node* dep = get_irn_n(node, 2);
1148 if (get_irn_n_edges(dep) > 1) {
1149 /* ... which has at least one user other than 'node' */
1150 ir_node *new_dep = be_transform_node(dep);
1151 add_irn_dep(new_node, new_dep);
1160 * Construct a standard unary operation, set AM and immediate if required.
1162 * @param op The operand
1163 * @param func The node constructor function
1164 * @return The constructed ia32 node.
1166 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1167 match_flags_t flags)
1170 ir_node *block, *new_block, *new_op, *new_node;
1172 assert(flags == 0 || flags == match_mode_neutral);
1173 if (flags & match_mode_neutral) {
1174 op = ia32_skip_downconv(op);
1177 new_op = be_transform_node(op);
1178 dbgi = get_irn_dbg_info(node);
1179 block = get_nodes_block(node);
1180 new_block = be_transform_node(block);
1181 new_node = func(dbgi, new_block, new_op);
1183 SET_IA32_ORIG_NODE(new_node, node);
1188 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1189 ia32_address_t *addr)
1191 ir_node *base, *index, *res;
1197 base = be_transform_node(base);
1200 index = addr->index;
1201 if (index == NULL) {
1204 index = be_transform_node(index);
1207 res = new_bd_ia32_Lea(dbgi, block, base, index);
1208 set_address(res, addr);
1214 * Returns non-zero if a given address mode has a symbolic or
1215 * numerical offset != 0.
1217 static int am_has_immediates(const ia32_address_t *addr)
1219 return addr->offset != 0 || addr->symconst_ent != NULL
1220 || addr->frame_entity || addr->use_frame;
1224 * Creates an ia32 Add.
1226 * @return the created ia32 Add node
1228 static ir_node *gen_Add(ir_node *node)
1230 ir_mode *mode = get_irn_mode(node);
1231 ir_node *op1 = get_Add_left(node);
1232 ir_node *op2 = get_Add_right(node);
1234 ir_node *block, *new_block, *new_node, *add_immediate_op;
1235 ia32_address_t addr;
1236 ia32_address_mode_t am;
1238 if (mode_is_float(mode)) {
1239 if (ia32_cg_config.use_sse2)
1240 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1241 match_commutative | match_am);
1243 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
1246 ia32_mark_non_am(node);
1248 op2 = ia32_skip_downconv(op2);
1249 op1 = ia32_skip_downconv(op1);
1253 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1254 * 1. Add with immediate -> Lea
1255 * 2. Add with possible source address mode -> Add
1256 * 3. Otherwise -> Lea
1258 memset(&addr, 0, sizeof(addr));
1259 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1260 add_immediate_op = NULL;
1262 dbgi = get_irn_dbg_info(node);
1263 block = get_nodes_block(node);
1264 new_block = be_transform_node(block);
1267 if (addr.base == NULL && addr.index == NULL) {
1268 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1269 addr.symconst_sign, 0, addr.offset);
1270 be_dep_on_frame(new_node);
1271 SET_IA32_ORIG_NODE(new_node, node);
1274 /* add with immediate? */
1275 if (addr.index == NULL) {
1276 add_immediate_op = addr.base;
1277 } else if (addr.base == NULL && addr.scale == 0) {
1278 add_immediate_op = addr.index;
1281 if (add_immediate_op != NULL) {
1282 if (!am_has_immediates(&addr)) {
1283 #ifdef DEBUG_libfirm
1284 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1287 return be_transform_node(add_immediate_op);
1290 new_node = create_lea_from_address(dbgi, new_block, &addr);
1291 SET_IA32_ORIG_NODE(new_node, node);
1295 /* test if we can use source address mode */
1296 match_arguments(&am, block, op1, op2, NULL, match_commutative
1297 | match_mode_neutral | match_am | match_immediate | match_try_am);
1299 /* construct an Add with source address mode */
1300 if (am.op_type == ia32_AddrModeS) {
1301 ia32_address_t *am_addr = &am.addr;
1302 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1303 am_addr->index, am_addr->mem, am.new_op1,
1305 set_am_attributes(new_node, &am);
1306 SET_IA32_ORIG_NODE(new_node, node);
1308 new_node = fix_mem_proj(new_node, &am);
1313 /* otherwise construct a lea */
1314 new_node = create_lea_from_address(dbgi, new_block, &addr);
1315 SET_IA32_ORIG_NODE(new_node, node);
1320 * Creates an ia32 Mul.
1322 * @return the created ia32 Mul node
1324 static ir_node *gen_Mul(ir_node *node)
1326 ir_node *op1 = get_Mul_left(node);
1327 ir_node *op2 = get_Mul_right(node);
1328 ir_mode *mode = get_irn_mode(node);
1330 if (mode_is_float(mode)) {
1331 if (ia32_cg_config.use_sse2)
1332 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1333 match_commutative | match_am);
1335 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
1337 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1338 match_commutative | match_am | match_mode_neutral |
1339 match_immediate | match_am_and_immediates);
1343 * Creates an ia32 Mulh.
1344 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1345 * this result while Mul returns the lower 32 bit.
1347 * @return the created ia32 Mulh node
1349 static ir_node *gen_Mulh(ir_node *node)
1351 dbg_info *dbgi = get_irn_dbg_info(node);
1352 ir_node *op1 = get_Mulh_left(node);
1353 ir_node *op2 = get_Mulh_right(node);
1354 ir_mode *mode = get_irn_mode(node);
1356 ir_node *proj_res_high;
1358 if (get_mode_size_bits(mode) != 32) {
1359 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1362 if (mode_is_signed(mode)) {
1363 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1364 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1366 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1367 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_Mul_res_high);
1369 return proj_res_high;
1373 * Creates an ia32 And.
1375 * @return The created ia32 And node
1377 static ir_node *gen_And(ir_node *node)
1379 ir_node *op1 = get_And_left(node);
1380 ir_node *op2 = get_And_right(node);
1381 assert(! mode_is_float(get_irn_mode(node)));
1383 /* is it a zero extension? */
1384 if (is_Const(op2)) {
1385 ir_tarval *tv = get_Const_tarval(op2);
1386 long v = get_tarval_long(tv);
1388 if (v == 0xFF || v == 0xFFFF) {
1389 dbg_info *dbgi = get_irn_dbg_info(node);
1390 ir_node *block = get_nodes_block(node);
1397 assert(v == 0xFFFF);
1400 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1405 return gen_binop(node, op1, op2, new_bd_ia32_And,
1406 match_commutative | match_mode_neutral | match_am | match_immediate);
1412 * Creates an ia32 Or.
1414 * @return The created ia32 Or node
1416 static ir_node *gen_Or(ir_node *node)
1418 ir_node *op1 = get_Or_left(node);
1419 ir_node *op2 = get_Or_right(node);
1421 assert (! mode_is_float(get_irn_mode(node)));
1422 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1423 | match_mode_neutral | match_am | match_immediate);
1429 * Creates an ia32 Eor.
1431 * @return The created ia32 Eor node
1433 static ir_node *gen_Eor(ir_node *node)
1435 ir_node *op1 = get_Eor_left(node);
1436 ir_node *op2 = get_Eor_right(node);
1438 assert(! mode_is_float(get_irn_mode(node)));
1439 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1440 | match_mode_neutral | match_am | match_immediate);
1445 * Creates an ia32 Sub.
1447 * @return The created ia32 Sub node
1449 static ir_node *gen_Sub(ir_node *node)
1451 ir_node *op1 = get_Sub_left(node);
1452 ir_node *op2 = get_Sub_right(node);
1453 ir_mode *mode = get_irn_mode(node);
1455 if (mode_is_float(mode)) {
1456 if (ia32_cg_config.use_sse2)
1457 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1459 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
1462 if (is_Const(op2)) {
1463 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1467 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1468 | match_am | match_immediate);
1471 static ir_node *transform_AM_mem(ir_node *const block,
1472 ir_node *const src_val,
1473 ir_node *const src_mem,
1474 ir_node *const am_mem)
1476 if (is_NoMem(am_mem)) {
1477 return be_transform_node(src_mem);
1478 } else if (is_Proj(src_val) &&
1480 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1481 /* avoid memory loop */
1483 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1484 ir_node *const ptr_pred = get_Proj_pred(src_val);
1485 int const arity = get_Sync_n_preds(src_mem);
1490 NEW_ARR_A(ir_node*, ins, arity + 1);
1492 /* NOTE: This sometimes produces dead-code because the old sync in
1493 * src_mem might not be used anymore, we should detect this case
1494 * and kill the sync... */
1495 for (i = arity - 1; i >= 0; --i) {
1496 ir_node *const pred = get_Sync_pred(src_mem, i);
1498 /* avoid memory loop */
1499 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1502 ins[n++] = be_transform_node(pred);
1505 if (n==1 && ins[0] == am_mem) {
1507 /* creating a new Sync and relying on CSE may fail,
1508 * if am_mem is a ProjM, which does not yet verify. */
1512 return new_r_Sync(block, n, ins);
1516 ins[0] = be_transform_node(src_mem);
1518 return new_r_Sync(block, 2, ins);
1523 * Create a 32bit to 64bit signed extension.
1525 * @param dbgi debug info
1526 * @param block the block where node nodes should be placed
1527 * @param val the value to extend
1528 * @param orig the original node
1530 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1531 ir_node *val, const ir_node *orig)
1536 if (ia32_cg_config.use_short_sex_eax) {
1537 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1538 be_dep_on_frame(pval);
1539 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1541 ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
1542 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1544 SET_IA32_ORIG_NODE(res, orig);
1549 * Generates an ia32 Div with additional infrastructure for the
1550 * register allocator if needed.
1552 static ir_node *create_Div(ir_node *node)
1554 dbg_info *dbgi = get_irn_dbg_info(node);
1555 ir_node *block = get_nodes_block(node);
1556 ir_node *new_block = be_transform_node(block);
1563 ir_node *sign_extension;
1564 ia32_address_mode_t am;
1565 ia32_address_t *addr = &am.addr;
1567 /* the upper bits have random contents for smaller modes */
1568 switch (get_irn_opcode(node)) {
1570 op1 = get_Div_left(node);
1571 op2 = get_Div_right(node);
1572 mem = get_Div_mem(node);
1573 mode = get_Div_resmode(node);
1576 op1 = get_Mod_left(node);
1577 op2 = get_Mod_right(node);
1578 mem = get_Mod_mem(node);
1579 mode = get_Mod_resmode(node);
1582 panic("invalid divmod node %+F", node);
1585 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
1587 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1588 is the memory of the consumed address. We can have only the second op as address
1589 in Div nodes, so check only op2. */
1590 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1592 if (mode_is_signed(mode)) {
1593 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1594 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1595 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1597 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1598 be_dep_on_frame(sign_extension);
1600 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1601 addr->index, new_mem, am.new_op2,
1602 am.new_op1, sign_extension);
1605 set_irn_pinned(new_node, get_irn_pinned(node));
1607 set_am_attributes(new_node, &am);
1608 SET_IA32_ORIG_NODE(new_node, node);
1610 new_node = fix_mem_proj(new_node, &am);
1616 * Generates an ia32 Mod.
1618 static ir_node *gen_Mod(ir_node *node)
1620 return create_Div(node);
1624 * Generates an ia32 Div.
1626 static ir_node *gen_Div(ir_node *node)
1628 ir_mode *mode = get_Div_resmode(node);
1629 if (mode_is_float(mode)) {
1630 ir_node *op1 = get_Div_left(node);
1631 ir_node *op2 = get_Div_right(node);
1633 if (ia32_cg_config.use_sse2) {
1634 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1636 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
1640 return create_Div(node);
1644 * Creates an ia32 Shl.
1646 * @return The created ia32 Shl node
1648 static ir_node *gen_Shl(ir_node *node)
1650 ir_node *left = get_Shl_left(node);
1651 ir_node *right = get_Shl_right(node);
1653 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1654 match_mode_neutral | match_immediate);
1658 * Creates an ia32 Shr.
1660 * @return The created ia32 Shr node
1662 static ir_node *gen_Shr(ir_node *node)
1664 ir_node *left = get_Shr_left(node);
1665 ir_node *right = get_Shr_right(node);
1667 return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
1673 * Creates an ia32 Sar.
1675 * @return The created ia32 Shrs node
1677 static ir_node *gen_Shrs(ir_node *node)
1679 ir_node *left = get_Shrs_left(node);
1680 ir_node *right = get_Shrs_right(node);
1682 if (is_Const(right)) {
1683 ir_tarval *tv = get_Const_tarval(right);
1684 long val = get_tarval_long(tv);
1686 /* this is a sign extension */
1687 dbg_info *dbgi = get_irn_dbg_info(node);
1688 ir_node *block = be_transform_node(get_nodes_block(node));
1689 ir_node *new_op = be_transform_node(left);
1691 return create_sex_32_64(dbgi, block, new_op, node);
1695 /* 8 or 16 bit sign extension? */
1696 if (is_Const(right) && is_Shl(left)) {
1697 ir_node *shl_left = get_Shl_left(left);
1698 ir_node *shl_right = get_Shl_right(left);
1699 if (is_Const(shl_right)) {
1700 ir_tarval *tv1 = get_Const_tarval(right);
1701 ir_tarval *tv2 = get_Const_tarval(shl_right);
1702 if (tv1 == tv2 && tarval_is_long(tv1)) {
1703 long val = get_tarval_long(tv1);
1704 if (val == 16 || val == 24) {
1705 dbg_info *dbgi = get_irn_dbg_info(node);
1706 ir_node *block = get_nodes_block(node);
1716 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1725 return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
1731 * Creates an ia32 Rol.
1733 * @param op1 The first operator
1734 * @param op2 The second operator
1735 * @return The created ia32 RotL node
1737 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1739 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1745 * Creates an ia32 Ror.
1746 * NOTE: There is no RotR with immediate because this would always be a RotL
1747 * "imm-mode_size_bits" which can be pre-calculated.
1749 * @param op1 The first operator
1750 * @param op2 The second operator
1751 * @return The created ia32 RotR node
1753 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1755 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1761 * Creates an ia32 RotR or RotL (depending on the found pattern).
1763 * @return The created ia32 RotL or RotR node
1765 static ir_node *gen_Rotl(ir_node *node)
1767 ir_node *op1 = get_Rotl_left(node);
1768 ir_node *op2 = get_Rotl_right(node);
1770 if (is_Minus(op2)) {
1771 return gen_Ror(node, op1, get_Minus_op(op2));
1774 return gen_Rol(node, op1, op2);
1780 * Transforms a Minus node.
1782 * @return The created ia32 Minus node
1784 static ir_node *gen_Minus(ir_node *node)
1786 ir_node *op = get_Minus_op(node);
1787 ir_node *block = be_transform_node(get_nodes_block(node));
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_mode *mode = get_irn_mode(node);
1794 if (mode_is_float(mode)) {
1795 ir_node *new_op = be_transform_node(op);
1796 if (ia32_cg_config.use_sse2) {
1797 /* TODO: non-optimal... if we have many xXors, then we should
1798 * rather create a load for the const and use that instead of
1799 * several AM nodes... */
1800 ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
1802 new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
1803 noreg_GP, nomem, new_op, noreg_xmm);
1805 size = get_mode_size_bits(mode);
1806 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1808 set_ia32_am_sc(new_node, ent);
1809 set_ia32_op_type(new_node, ia32_AddrModeS);
1810 set_ia32_ls_mode(new_node, mode);
1812 new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
1815 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1818 SET_IA32_ORIG_NODE(new_node, node);
1824 * Transforms a Not node.
1826 * @return The created ia32 Not node
1828 static ir_node *gen_Not(ir_node *node)
1830 ir_node *op = get_Not_op(node);
1832 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1833 assert (! mode_is_float(get_irn_mode(node)));
1835 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
1838 static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
1839 bool negate, ir_node *node)
1841 ir_node *new_block = be_transform_node(block);
1842 ir_mode *mode = get_irn_mode(op);
1848 if (mode_is_float(mode)) {
1849 new_op = be_transform_node(op);
1851 if (ia32_cg_config.use_sse2) {
1852 ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
1853 new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
1854 noreg_GP, nomem, new_op, noreg_fp);
1856 size = get_mode_size_bits(mode);
1857 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1859 set_ia32_am_sc(new_node, ent);
1861 SET_IA32_ORIG_NODE(new_node, node);
1863 set_ia32_op_type(new_node, ia32_AddrModeS);
1864 set_ia32_ls_mode(new_node, mode);
1866 /* TODO, implement -Abs case */
1869 new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
1870 SET_IA32_ORIG_NODE(new_node, node);
1872 new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
1873 SET_IA32_ORIG_NODE(new_node, node);
1878 ir_node *sign_extension;
1880 if (get_mode_size_bits(mode) == 32) {
1881 new_op = be_transform_node(op);
1883 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1886 sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
1888 xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
1889 nomem, new_op, sign_extension);
1890 SET_IA32_ORIG_NODE(xorn, node);
1893 new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
1894 nomem, sign_extension, xorn);
1896 new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
1897 nomem, xorn, sign_extension);
1899 SET_IA32_ORIG_NODE(new_node, node);
1906 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
1908 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
1910 dbg_info *dbgi = get_irn_dbg_info(cmp);
1911 ir_node *block = get_nodes_block(cmp);
1912 ir_node *new_block = be_transform_node(block);
1913 ir_node *op1 = be_transform_node(x);
1914 ir_node *op2 = be_transform_node(n);
1916 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
1919 static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
1922 if (mode_is_float(mode)) {
1924 case ir_relation_equal: return ia32_cc_float_equal;
1925 case ir_relation_less: return ia32_cc_float_below;
1926 case ir_relation_less_equal: return ia32_cc_float_below_equal;
1927 case ir_relation_greater: return ia32_cc_float_above;
1928 case ir_relation_greater_equal: return ia32_cc_float_above_equal;
1929 case ir_relation_less_greater: return ia32_cc_not_equal;
1930 case ir_relation_less_equal_greater: return ia32_cc_not_parity;
1931 case ir_relation_unordered: return ia32_cc_parity;
1932 case ir_relation_unordered_equal: return ia32_cc_equal;
1933 case ir_relation_unordered_less: return ia32_cc_float_unordered_below;
1934 case ir_relation_unordered_less_equal:
1935 return ia32_cc_float_unordered_below_equal;
1936 case ir_relation_unordered_greater:
1937 return ia32_cc_float_unordered_above;
1938 case ir_relation_unordered_greater_equal:
1939 return ia32_cc_float_unordered_above_equal;
1940 case ir_relation_unordered_less_greater:
1941 return ia32_cc_float_not_equal;
1942 case ir_relation_false:
1943 case ir_relation_true:
1944 /* should we introduce a jump always/jump never? */
1947 panic("Unexpected float pnc");
1948 } else if (mode_is_signed(mode)) {
1950 case ir_relation_unordered_equal:
1951 case ir_relation_equal: return ia32_cc_equal;
1952 case ir_relation_unordered_less:
1953 case ir_relation_less: return ia32_cc_less;
1954 case ir_relation_unordered_less_equal:
1955 case ir_relation_less_equal: return ia32_cc_less_equal;
1956 case ir_relation_unordered_greater:
1957 case ir_relation_greater: return ia32_cc_greater;
1958 case ir_relation_unordered_greater_equal:
1959 case ir_relation_greater_equal: return ia32_cc_greater_equal;
1960 case ir_relation_unordered_less_greater:
1961 case ir_relation_less_greater: return ia32_cc_not_equal;
1962 case ir_relation_less_equal_greater:
1963 case ir_relation_unordered:
1964 case ir_relation_false:
1965 case ir_relation_true:
1966 /* introduce jump always/jump never? */
1969 panic("Unexpected pnc");
1972 case ir_relation_unordered_equal:
1973 case ir_relation_equal: return ia32_cc_equal;
1974 case ir_relation_unordered_less:
1975 case ir_relation_less: return ia32_cc_below;
1976 case ir_relation_unordered_less_equal:
1977 case ir_relation_less_equal: return ia32_cc_below_equal;
1978 case ir_relation_unordered_greater:
1979 case ir_relation_greater: return ia32_cc_above;
1980 case ir_relation_unordered_greater_equal:
1981 case ir_relation_greater_equal: return ia32_cc_above_equal;
1982 case ir_relation_unordered_less_greater:
1983 case ir_relation_less_greater: return ia32_cc_not_equal;
1984 case ir_relation_less_equal_greater:
1985 case ir_relation_unordered:
1986 case ir_relation_false:
1987 case ir_relation_true:
1988 /* introduce jump always/jump never? */
1991 panic("Unexpected pnc");
1995 static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out)
1997 /* a mode_b value, we have to compare it against 0 */
1998 dbg_info *dbgi = get_irn_dbg_info(node);
1999 ir_node *new_block = be_transform_node(get_nodes_block(node));
2000 ir_node *new_op = be_transform_node(node);
2001 ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false);
2002 *cc_out = ia32_cc_not_equal;
2006 static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out)
2008 /* must have a Cmp as input */
2009 ir_relation relation = get_Cmp_relation(cmp);
2010 ir_node *l = get_Cmp_left(cmp);
2011 ir_mode *mode = get_irn_mode(l);
2014 /* check for bit-test */
2015 if (ia32_cg_config.use_bt && (relation == ir_relation_equal
2016 || (mode_is_signed(mode) && relation == ir_relation_less_greater)
2017 || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))) {
2018 ir_node *l = get_Cmp_left(cmp);
2019 ir_node *r = get_Cmp_right(cmp);
2021 ir_node *la = get_And_left(l);
2022 ir_node *ra = get_And_right(l);
2029 ir_node *c = get_Shl_left(la);
2030 if (is_Const_1(c) && is_Const_0(r)) {
2031 /* (1 << n) & ra) */
2032 ir_node *n = get_Shl_right(la);
2033 flags = gen_bt(cmp, ra, n);
2034 /* the bit is copied into the CF flag */
2035 if (relation & ir_relation_equal)
2036 *cc_out = ia32_cc_above_equal; /* test for CF=0 */
2038 *cc_out = ia32_cc_below; /* test for CF=1 */
2045 /* just do a normal transformation of the Cmp */
2046 *cc_out = relation_to_condition_code(relation, mode);
2047 flags = be_transform_node(cmp);
2052 * Transform a node returning a "flag" result.
2054 * @param node the node to transform
2055 * @param cc_out the compare mode to use
2057 static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out)
2060 return get_flags_node_cmp(node, cc_out);
2061 assert(get_irn_mode(node) == mode_b);
2062 return get_flags_mode_b(node, cc_out);
2066 * Transforms a Load.
2068 * @return the created ia32 Load node
2070 static ir_node *gen_Load(ir_node *node)
2072 ir_node *old_block = get_nodes_block(node);
2073 ir_node *block = be_transform_node(old_block);
2074 ir_node *ptr = get_Load_ptr(node);
2075 ir_node *mem = get_Load_mem(node);
2076 ir_node *new_mem = be_transform_node(mem);
2077 dbg_info *dbgi = get_irn_dbg_info(node);
2078 ir_mode *mode = get_Load_mode(node);
2082 ia32_address_t addr;
2084 /* construct load address */
2085 memset(&addr, 0, sizeof(addr));
2086 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2093 base = be_transform_node(base);
2096 if (index == NULL) {
2099 index = be_transform_node(index);
2102 if (mode_is_float(mode)) {
2103 if (ia32_cg_config.use_sse2) {
2104 new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
2107 new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
2111 assert(mode != mode_b);
2113 /* create a conv node with address mode for smaller modes */
2114 if (get_mode_size_bits(mode) < 32) {
2115 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
2116 new_mem, noreg_GP, mode);
2118 new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
2122 set_irn_pinned(new_node, get_irn_pinned(node));
2123 set_ia32_op_type(new_node, ia32_AddrModeS);
2124 set_ia32_ls_mode(new_node, mode);
2125 set_address(new_node, &addr);
2127 if (get_irn_pinned(node) == op_pin_state_floats) {
2128 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
2129 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
2130 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
2131 arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
2134 SET_IA32_ORIG_NODE(new_node, node);
2136 be_dep_on_frame(new_node);
2140 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2141 ir_node *ptr, ir_node *other)
2148 /* we only use address mode if we're the only user of the load */
2149 if (get_irn_n_edges(node) > 1)
2152 load = get_Proj_pred(node);
2155 if (get_nodes_block(load) != block)
2158 /* store should have the same pointer as the load */
2159 if (get_Load_ptr(load) != ptr)
2162 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2163 if (other != NULL &&
2164 get_nodes_block(other) == block &&
2165 heights_reachable_in_block(ia32_heights, other, load)) {
2169 if (ia32_prevents_AM(block, load, mem))
2171 /* Store should be attached to the load via mem */
2172 assert(heights_reachable_in_block(ia32_heights, mem, load));
2177 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2178 ir_node *mem, ir_node *ptr, ir_mode *mode,
2179 construct_binop_dest_func *func,
2180 construct_binop_dest_func *func8bit,
2181 match_flags_t flags)
2183 ir_node *src_block = get_nodes_block(node);
2191 ia32_address_mode_t am;
2192 ia32_address_t *addr = &am.addr;
2193 memset(&am, 0, sizeof(am));
2195 assert(flags & match_immediate); /* there is no destam node without... */
2196 commutative = (flags & match_commutative) != 0;
2198 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2199 build_address(&am, op1, ia32_create_am_double_use);
2200 new_op = create_immediate_or_transform(op2, 0);
2201 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2202 build_address(&am, op2, ia32_create_am_double_use);
2203 new_op = create_immediate_or_transform(op1, 0);
2208 if (addr->base == NULL)
2209 addr->base = noreg_GP;
2210 if (addr->index == NULL)
2211 addr->index = noreg_GP;
2212 if (addr->mem == NULL)
2215 dbgi = get_irn_dbg_info(node);
2216 block = be_transform_node(src_block);
2217 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2219 if (get_mode_size_bits(mode) == 8) {
2220 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2222 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2224 set_address(new_node, addr);
2225 set_ia32_op_type(new_node, ia32_AddrModeD);
2226 set_ia32_ls_mode(new_node, mode);
2227 SET_IA32_ORIG_NODE(new_node, node);
2229 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2230 mem_proj = be_transform_node(am.mem_proj);
2231 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2236 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2237 ir_node *ptr, ir_mode *mode,
2238 construct_unop_dest_func *func)
2240 ir_node *src_block = get_nodes_block(node);
2246 ia32_address_mode_t am;
2247 ia32_address_t *addr = &am.addr;
2249 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2252 memset(&am, 0, sizeof(am));
2253 build_address(&am, op, ia32_create_am_double_use);
2255 dbgi = get_irn_dbg_info(node);
2256 block = be_transform_node(src_block);
2257 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2258 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2259 set_address(new_node, addr);
2260 set_ia32_op_type(new_node, ia32_AddrModeD);
2261 set_ia32_ls_mode(new_node, mode);
2262 SET_IA32_ORIG_NODE(new_node, node);
2264 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2265 mem_proj = be_transform_node(am.mem_proj);
2266 be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
2271 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2273 ir_mode *mode = get_irn_mode(node);
2274 ir_node *mux_true = get_Mux_true(node);
2275 ir_node *mux_false = get_Mux_false(node);
2283 ia32_condition_code_t cc;
2284 ia32_address_t addr;
2286 if (get_mode_size_bits(mode) != 8)
2289 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2291 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2297 cond = get_Mux_sel(node);
2298 flags = get_flags_node(cond, &cc);
2299 /* we can't handle the float special cases with SetM */
2300 if (cc & ia32_cc_additional_float_cases)
2303 cc = ia32_negate_condition_code(cc);
2305 build_address_ptr(&addr, ptr, mem);
2307 dbgi = get_irn_dbg_info(node);
2308 block = get_nodes_block(node);
2309 new_block = be_transform_node(block);
2310 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2311 addr.index, addr.mem, flags, cc);
2312 set_address(new_node, &addr);
2313 set_ia32_op_type(new_node, ia32_AddrModeD);
2314 set_ia32_ls_mode(new_node, mode);
2315 SET_IA32_ORIG_NODE(new_node, node);
2320 static ir_node *try_create_dest_am(ir_node *node)
2322 ir_node *val = get_Store_value(node);
2323 ir_node *mem = get_Store_mem(node);
2324 ir_node *ptr = get_Store_ptr(node);
2325 ir_mode *mode = get_irn_mode(val);
2326 unsigned bits = get_mode_size_bits(mode);
2331 /* handle only GP modes for now... */
2332 if (!ia32_mode_needs_gp_reg(mode))
2336 /* store must be the only user of the val node */
2337 if (get_irn_n_edges(val) > 1)
2339 /* skip pointless convs */
2341 ir_node *conv_op = get_Conv_op(val);
2342 ir_mode *pred_mode = get_irn_mode(conv_op);
2343 if (!ia32_mode_needs_gp_reg(pred_mode))
2345 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2353 /* value must be in the same block */
2354 if (get_nodes_block(node) != get_nodes_block(val))
2357 switch (get_irn_opcode(val)) {
2359 op1 = get_Add_left(val);
2360 op2 = get_Add_right(val);
2361 if (ia32_cg_config.use_incdec) {
2362 if (is_Const_1(op2)) {
2363 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2365 } else if (is_Const_Minus_1(op2)) {
2366 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2370 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2371 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2372 match_commutative | match_immediate);
2375 op1 = get_Sub_left(val);
2376 op2 = get_Sub_right(val);
2377 if (is_Const(op2)) {
2378 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2380 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2381 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2385 op1 = get_And_left(val);
2386 op2 = get_And_right(val);
2387 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2388 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2389 match_commutative | match_immediate);
2392 op1 = get_Or_left(val);
2393 op2 = get_Or_right(val);
2394 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2395 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2396 match_commutative | match_immediate);
2399 op1 = get_Eor_left(val);
2400 op2 = get_Eor_right(val);
2401 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2402 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2403 match_commutative | match_immediate);
2406 op1 = get_Shl_left(val);
2407 op2 = get_Shl_right(val);
2408 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2409 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2413 op1 = get_Shr_left(val);
2414 op2 = get_Shr_right(val);
2415 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2416 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2420 op1 = get_Shrs_left(val);
2421 op2 = get_Shrs_right(val);
2422 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2423 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2427 op1 = get_Rotl_left(val);
2428 op2 = get_Rotl_right(val);
2429 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2430 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2433 /* TODO: match ROR patterns... */
2435 new_node = try_create_SetMem(val, ptr, mem);
2439 op1 = get_Minus_op(val);
2440 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2443 /* should be lowered already */
2444 assert(mode != mode_b);
2445 op1 = get_Not_op(val);
2446 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2452 if (new_node != NULL) {
2453 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2454 get_irn_pinned(node) == op_pin_state_pinned) {
2455 set_irn_pinned(new_node, op_pin_state_pinned);
2462 static bool possible_int_mode_for_fp(ir_mode *mode)
2466 if (!mode_is_signed(mode))
2468 size = get_mode_size_bits(mode);
2469 if (size != 16 && size != 32)
2474 static int is_float_to_int_conv(const ir_node *node)
2476 ir_mode *mode = get_irn_mode(node);
2480 if (!possible_int_mode_for_fp(mode))
2485 conv_op = get_Conv_op(node);
2486 conv_mode = get_irn_mode(conv_op);
2488 if (!mode_is_float(conv_mode))
2495 * Transform a Store(floatConst) into a sequence of
2498 * @return the created ia32 Store node
2500 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2502 ir_mode *mode = get_irn_mode(cns);
2503 unsigned size = get_mode_size_bytes(mode);
2504 ir_tarval *tv = get_Const_tarval(cns);
2505 ir_node *block = get_nodes_block(node);
2506 ir_node *new_block = be_transform_node(block);
2507 ir_node *ptr = get_Store_ptr(node);
2508 ir_node *mem = get_Store_mem(node);
2509 dbg_info *dbgi = get_irn_dbg_info(node);
2513 ia32_address_t addr;
2515 assert(size % 4 == 0);
2518 build_address_ptr(&addr, ptr, mem);
2522 get_tarval_sub_bits(tv, ofs) |
2523 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2524 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2525 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2526 ir_node *imm = ia32_create_Immediate(NULL, 0, val);
2528 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2529 addr.index, addr.mem, imm);
2531 set_irn_pinned(new_node, get_irn_pinned(node));
2532 set_ia32_op_type(new_node, ia32_AddrModeD);
2533 set_ia32_ls_mode(new_node, mode_Iu);
2534 set_address(new_node, &addr);
2535 SET_IA32_ORIG_NODE(new_node, node);
2538 ins[i++] = new_node;
2543 } while (size != 0);
2546 return new_rd_Sync(dbgi, new_block, i, ins);
2553 * Generate a vfist or vfisttp instruction.
2555 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index,
2556 ir_node *mem, ir_node *val, ir_node **fist)
2560 if (ia32_cg_config.use_fisttp) {
2561 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2562 if other users exists */
2563 ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
2564 ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res);
2565 be_new_Keep(block, 1, &value);
2567 new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M);
2570 ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
2573 new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
2579 * Transforms a general (no special case) Store.
2581 * @return the created ia32 Store node
2583 static ir_node *gen_general_Store(ir_node *node)
2585 ir_node *val = get_Store_value(node);
2586 ir_mode *mode = get_irn_mode(val);
2587 ir_node *block = get_nodes_block(node);
2588 ir_node *new_block = be_transform_node(block);
2589 ir_node *ptr = get_Store_ptr(node);
2590 ir_node *mem = get_Store_mem(node);
2591 dbg_info *dbgi = get_irn_dbg_info(node);
2592 ir_node *new_val, *new_node, *store;
2593 ia32_address_t addr;
2595 /* check for destination address mode */
2596 new_node = try_create_dest_am(node);
2597 if (new_node != NULL)
2600 /* construct store address */
2601 memset(&addr, 0, sizeof(addr));
2602 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2604 if (addr.base == NULL) {
2605 addr.base = noreg_GP;
2607 addr.base = be_transform_node(addr.base);
2610 if (addr.index == NULL) {
2611 addr.index = noreg_GP;
2613 addr.index = be_transform_node(addr.index);
2615 addr.mem = be_transform_node(mem);
2617 if (mode_is_float(mode)) {
2618 /* Convs (and strict-Convs) before stores are unnecessary if the mode
2620 while (is_Conv(val) && mode == get_irn_mode(val)) {
2621 ir_node *op = get_Conv_op(val);
2622 if (!mode_is_float(get_irn_mode(op)))
2626 new_val = be_transform_node(val);
2627 if (ia32_cg_config.use_sse2) {
2628 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2629 addr.index, addr.mem, new_val);
2631 new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
2632 addr.index, addr.mem, new_val, mode);
2635 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2636 val = get_Conv_op(val);
2638 /* TODO: is this optimisation still necessary at all (middleend)? */
2639 /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
2640 while (is_Conv(val)) {
2641 ir_node *op = get_Conv_op(val);
2642 if (!mode_is_float(get_irn_mode(op)))
2644 if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
2648 new_val = be_transform_node(val);
2649 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store);
2651 new_val = create_immediate_or_transform(val, 0);
2652 assert(mode != mode_b);
2654 if (get_mode_size_bits(mode) == 8) {
2655 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2656 addr.index, addr.mem, new_val);
2658 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2659 addr.index, addr.mem, new_val);
2664 set_irn_pinned(store, get_irn_pinned(node));
2665 set_ia32_op_type(store, ia32_AddrModeD);
2666 set_ia32_ls_mode(store, mode);
2668 set_address(store, &addr);
2669 SET_IA32_ORIG_NODE(store, node);
2675 * Transforms a Store.
2677 * @return the created ia32 Store node
2679 static ir_node *gen_Store(ir_node *node)
2681 ir_node *val = get_Store_value(node);
2682 ir_mode *mode = get_irn_mode(val);
2684 if (mode_is_float(mode) && is_Const(val)) {
2685 /* We can transform every floating const store
2686 into a sequence of integer stores.
2687 If the constant is already in a register,
2688 it would be better to use it, but we don't
2689 have this information here. */
2690 return gen_float_const_Store(node, val);
2692 return gen_general_Store(node);
2696 * Transforms a Switch.
2698 * @return the created ia32 SwitchJmp node
2700 static ir_node *create_Switch(ir_node *node)
2702 dbg_info *dbgi = get_irn_dbg_info(node);
2703 ir_node *block = be_transform_node(get_nodes_block(node));
2704 ir_node *sel = get_Cond_selector(node);
2705 ir_node *new_sel = be_transform_node(sel);
2706 long switch_min = LONG_MAX;
2707 long switch_max = LONG_MIN;
2708 long default_pn = get_Cond_default_proj(node);
2710 const ir_edge_t *edge;
2712 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2714 /* determine the smallest switch case value */
2715 foreach_out_edge(node, edge) {
2716 ir_node *proj = get_edge_src_irn(edge);
2717 long pn = get_Proj_proj(proj);
2718 if (pn == default_pn)
2721 if (pn < switch_min)
2723 if (pn > switch_max)
2727 if ((unsigned long) (switch_max - switch_min) > 128000) {
2728 panic("Size of switch %+F bigger than 128000", node);
2731 if (switch_min != 0) {
2732 /* if smallest switch case is not 0 we need an additional sub */
2733 new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP);
2734 add_ia32_am_offs_int(new_sel, -switch_min);
2735 set_ia32_op_type(new_sel, ia32_AddrModeS);
2737 SET_IA32_ORIG_NODE(new_sel, node);
2740 new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
2741 SET_IA32_ORIG_NODE(new_node, node);
2747 * Transform a Cond node.
2749 static ir_node *gen_Cond(ir_node *node)
2751 ir_node *block = get_nodes_block(node);
2752 ir_node *new_block = be_transform_node(block);
2753 dbg_info *dbgi = get_irn_dbg_info(node);
2754 ir_node *sel = get_Cond_selector(node);
2755 ir_mode *sel_mode = get_irn_mode(sel);
2756 ir_node *flags = NULL;
2758 ia32_condition_code_t cc;
2760 if (sel_mode != mode_b) {
2761 return create_Switch(node);
2764 /* we get flags from a Cmp */
2765 flags = get_flags_node(sel, &cc);
2767 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc);
2768 SET_IA32_ORIG_NODE(new_node, node);
2774 * Transform a be_Copy.
2776 static ir_node *gen_be_Copy(ir_node *node)
2778 ir_node *new_node = be_duplicate_node(node);
2779 ir_mode *mode = get_irn_mode(new_node);
2781 if (ia32_mode_needs_gp_reg(mode)) {
2782 set_irn_mode(new_node, mode_Iu);
2788 static ir_node *create_Fucom(ir_node *node)
2790 dbg_info *dbgi = get_irn_dbg_info(node);
2791 ir_node *block = get_nodes_block(node);
2792 ir_node *new_block = be_transform_node(block);
2793 ir_node *left = get_Cmp_left(node);
2794 ir_node *new_left = be_transform_node(left);
2795 ir_node *right = get_Cmp_right(node);
2799 if (ia32_cg_config.use_fucomi) {
2800 new_right = be_transform_node(right);
2801 new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
2803 set_ia32_commutative(new_node);
2804 SET_IA32_ORIG_NODE(new_node, node);
2806 if (ia32_cg_config.use_ftst && is_Const_0(right)) {
2807 new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
2809 new_right = be_transform_node(right);
2810 new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2813 set_ia32_commutative(new_node);
2815 SET_IA32_ORIG_NODE(new_node, node);
2817 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2818 SET_IA32_ORIG_NODE(new_node, node);
2824 static ir_node *create_Ucomi(ir_node *node)
2826 dbg_info *dbgi = get_irn_dbg_info(node);
2827 ir_node *src_block = get_nodes_block(node);
2828 ir_node *new_block = be_transform_node(src_block);
2829 ir_node *left = get_Cmp_left(node);
2830 ir_node *right = get_Cmp_right(node);
2832 ia32_address_mode_t am;
2833 ia32_address_t *addr = &am.addr;
2835 match_arguments(&am, src_block, left, right, NULL,
2836 match_commutative | match_am);
2838 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2839 addr->mem, am.new_op1, am.new_op2,
2841 set_am_attributes(new_node, &am);
2843 SET_IA32_ORIG_NODE(new_node, node);
2845 new_node = fix_mem_proj(new_node, &am);
2851 * returns true if it is assured, that the upper bits of a node are "clean"
2852 * which means for a 16 or 8 bit value, that the upper bits in the register
2853 * are 0 for unsigned and a copy of the last significant bit for signed
2856 static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
2858 assert(ia32_mode_needs_gp_reg(mode));
2859 if (get_mode_size_bits(mode) >= 32)
2862 if (is_Proj(transformed_node))
2863 return upper_bits_clean(get_Proj_pred(transformed_node), mode);
2865 switch (get_ia32_irn_opcode(transformed_node)) {
2866 case iro_ia32_Conv_I2I:
2867 case iro_ia32_Conv_I2I8Bit: {
2868 ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
2869 if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
2871 if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
2878 if (mode_is_signed(mode)) {
2879 return false; /* TODO handle signed modes */
2881 ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
2882 if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
2883 const ia32_immediate_attr_t *attr
2884 = get_ia32_immediate_attr_const(right);
2885 if (attr->symconst == 0 &&
2886 (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
2890 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
2894 /* TODO too conservative if shift amount is constant */
2895 return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
2898 if (!mode_is_signed(mode)) {
2900 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
2901 upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
2903 /* TODO if one is known to be zero extended, then || is sufficient */
2908 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
2909 upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
2911 case iro_ia32_Const:
2912 case iro_ia32_Immediate: {
2913 const ia32_immediate_attr_t *attr =
2914 get_ia32_immediate_attr_const(transformed_node);
2915 if (mode_is_signed(mode)) {
2916 long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
2917 return shifted == 0 || shifted == -1;
2919 unsigned long shifted = (unsigned long)attr->offset;
2920 shifted >>= get_mode_size_bits(mode);
2921 return shifted == 0;
2931 * Generate code for a Cmp.
2933 static ir_node *gen_Cmp(ir_node *node)
2935 dbg_info *dbgi = get_irn_dbg_info(node);
2936 ir_node *block = get_nodes_block(node);
2937 ir_node *new_block = be_transform_node(block);
2938 ir_node *left = get_Cmp_left(node);
2939 ir_node *right = get_Cmp_right(node);
2940 ir_mode *cmp_mode = get_irn_mode(left);
2942 ia32_address_mode_t am;
2943 ia32_address_t *addr = &am.addr;
2945 if (mode_is_float(cmp_mode)) {
2946 if (ia32_cg_config.use_sse2) {
2947 return create_Ucomi(node);
2949 return create_Fucom(node);
2953 assert(ia32_mode_needs_gp_reg(cmp_mode));
2955 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
2956 if (is_Const_0(right) &&
2958 get_irn_n_edges(left) == 1) {
2959 /* Test(and_left, and_right) */
2960 ir_node *and_left = get_And_left(left);
2961 ir_node *and_right = get_And_right(left);
2963 /* matze: code here used mode instead of cmd_mode, I think it is always
2964 * the same as cmp_mode, but I leave this here to see if this is really
2967 assert(get_irn_mode(and_left) == cmp_mode);
2969 match_arguments(&am, block, and_left, and_right, NULL,
2971 match_am | match_8bit_am | match_16bit_am |
2972 match_am_and_immediates | match_immediate);
2974 /* use 32bit compare mode if possible since the opcode is smaller */
2975 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2976 upper_bits_clean(am.new_op2, cmp_mode)) {
2977 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2980 if (get_mode_size_bits(cmp_mode) == 8) {
2981 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
2982 addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
2984 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
2985 addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
2988 /* Cmp(left, right) */
2989 match_arguments(&am, block, left, right, NULL,
2990 match_commutative | match_am | match_8bit_am |
2991 match_16bit_am | match_am_and_immediates |
2993 /* use 32bit compare mode if possible since the opcode is smaller */
2994 if (upper_bits_clean(am.new_op1, cmp_mode) &&
2995 upper_bits_clean(am.new_op2, cmp_mode)) {
2996 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
2999 if (get_mode_size_bits(cmp_mode) == 8) {
3000 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
3001 addr->index, addr->mem, am.new_op1,
3002 am.new_op2, am.ins_permuted);
3004 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
3005 addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
3008 set_am_attributes(new_node, &am);
3009 set_ia32_ls_mode(new_node, cmp_mode);
3011 SET_IA32_ORIG_NODE(new_node, node);
3013 new_node = fix_mem_proj(new_node, &am);
3018 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
3019 ia32_condition_code_t cc)
3021 dbg_info *dbgi = get_irn_dbg_info(node);
3022 ir_node *block = get_nodes_block(node);
3023 ir_node *new_block = be_transform_node(block);
3024 ir_node *val_true = get_Mux_true(node);
3025 ir_node *val_false = get_Mux_false(node);
3027 ia32_address_mode_t am;
3028 ia32_address_t *addr;
3030 assert(ia32_cg_config.use_cmov);
3031 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
3035 match_arguments(&am, block, val_false, val_true, flags,
3036 match_commutative | match_am | match_16bit_am | match_mode_neutral);
3038 if (am.ins_permuted)
3039 cc = ia32_invert_condition_code(cc);
3041 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
3042 addr->mem, am.new_op1, am.new_op2, new_flags,
3044 set_am_attributes(new_node, &am);
3046 SET_IA32_ORIG_NODE(new_node, node);
3048 new_node = fix_mem_proj(new_node, &am);
3054 * Creates a ia32 Setcc instruction.
3056 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
3057 ir_node *flags, ia32_condition_code_t cc,
3060 ir_mode *mode = get_irn_mode(orig_node);
3063 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc);
3064 SET_IA32_ORIG_NODE(new_node, orig_node);
3066 /* we might need to conv the result up */
3067 if (get_mode_size_bits(mode) > 8) {
3068 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3069 nomem, new_node, mode_Bu);
3070 SET_IA32_ORIG_NODE(new_node, orig_node);
3077 * Create instruction for an unsigned Difference or Zero.
3079 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3081 ir_mode *mode = get_irn_mode(psi);
3091 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3092 match_mode_neutral | match_am | match_immediate | match_two_users);
3094 block = get_nodes_block(new_node);
3096 if (is_Proj(new_node)) {
3097 sub = get_Proj_pred(new_node);
3100 set_irn_mode(sub, mode_T);
3101 new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
3103 assert(is_ia32_Sub(sub));
3104 eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
3106 dbgi = get_irn_dbg_info(psi);
3107 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3108 notn = new_bd_ia32_Not(dbgi, block, sbb);
3110 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
3111 set_ia32_commutative(new_node);
3116 * Create an const array of two float consts.
3118 * @param c0 the first constant
3119 * @param c1 the second constant
3120 * @param new_mode IN/OUT for the mode of the constants, if NULL
3121 * smallest possible mode will be used
3123 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
3126 ir_mode *mode = *new_mode;
3128 ir_initializer_t *initializer;
3129 ir_tarval *tv0 = get_Const_tarval(c0);
3130 ir_tarval *tv1 = get_Const_tarval(c1);
3133 /* detect the best mode for the constants */
3134 mode = get_tarval_mode(tv0);
3136 if (mode != mode_F) {
3137 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3138 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3140 tv0 = tarval_convert_to(tv0, mode);
3141 tv1 = tarval_convert_to(tv1, mode);
3142 } else if (mode != mode_D) {
3143 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3144 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3146 tv0 = tarval_convert_to(tv0, mode);
3147 tv1 = tarval_convert_to(tv1, mode);
3154 tp = ia32_create_float_type(mode, 4);
3155 tp = ia32_create_float_array(tp);
3157 ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
3159 set_entity_ld_ident(ent, get_entity_ident(ent));
3160 set_entity_visibility(ent, ir_visibility_private);
3161 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
3163 initializer = create_initializer_compound(2);
3165 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3166 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3168 set_entity_initializer(ent, initializer);
3175 * Possible transformations for creating a Setcc.
3177 enum setcc_transform_insn {
3190 typedef struct setcc_transform {
3192 ia32_condition_code_t cc;
3194 enum setcc_transform_insn transform;
3198 } setcc_transform_t;
3201 * Setcc can only handle 0 and 1 result.
3202 * Find a transformation that creates 0 and 1 from
3205 static void find_const_transform(ia32_condition_code_t cc,
3206 ir_tarval *t, ir_tarval *f,
3207 setcc_transform_t *res)
3213 if (tarval_is_null(t)) {
3217 cc = ia32_negate_condition_code(cc);
3218 } else if (tarval_cmp(t, f) == ir_relation_less) {
3219 // now, t is the bigger one
3223 cc = ia32_negate_condition_code(cc);
3227 if (! tarval_is_null(f)) {
3228 ir_tarval *t_sub = tarval_sub(t, f, NULL);
3231 res->steps[step].transform = SETCC_TR_ADD;
3233 if (t == tarval_bad)
3234 panic("constant subtract failed");
3235 if (! tarval_is_long(f))
3236 panic("tarval is not long");
3238 res->steps[step].val = get_tarval_long(f);
3240 f = tarval_sub(f, f, NULL);
3241 assert(tarval_is_null(f));
3244 if (tarval_is_one(t)) {
3245 res->steps[step].transform = SETCC_TR_SET;
3246 res->num_steps = ++step;
3250 if (tarval_is_minus_one(t)) {
3251 res->steps[step].transform = SETCC_TR_NEG;
3253 res->steps[step].transform = SETCC_TR_SET;
3254 res->num_steps = ++step;
3257 if (tarval_is_long(t)) {
3258 long v = get_tarval_long(t);
3260 res->steps[step].val = 0;
3263 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3265 res->steps[step].transform = SETCC_TR_LEAxx;
3266 res->steps[step].scale = 3; /* (a << 3) + a */
3269 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3271 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3272 res->steps[step].scale = 3; /* (a << 3) */
3275 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3277 res->steps[step].transform = SETCC_TR_LEAxx;
3278 res->steps[step].scale = 2; /* (a << 2) + a */
3281 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3283 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3284 res->steps[step].scale = 2; /* (a << 2) */
3287 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3289 res->steps[step].transform = SETCC_TR_LEAxx;
3290 res->steps[step].scale = 1; /* (a << 1) + a */
3293 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3295 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3296 res->steps[step].scale = 1; /* (a << 1) */
3299 res->num_steps = step;
3302 if (! tarval_is_single_bit(t)) {
3303 res->steps[step].transform = SETCC_TR_AND;
3304 res->steps[step].val = v;
3306 res->steps[step].transform = SETCC_TR_NEG;
3308 int v = get_tarval_lowest_bit(t);
3311 res->steps[step].transform = SETCC_TR_SHL;
3312 res->steps[step].scale = v;
3316 res->steps[step].transform = SETCC_TR_SET;
3317 res->num_steps = ++step;
3320 panic("tarval is not long");
3324 * Transforms a Mux node into some code sequence.
3326 * @return The transformed node.
3328 static ir_node *gen_Mux(ir_node *node)
3330 dbg_info *dbgi = get_irn_dbg_info(node);
3331 ir_node *block = get_nodes_block(node);
3332 ir_node *new_block = be_transform_node(block);
3333 ir_node *mux_true = get_Mux_true(node);
3334 ir_node *mux_false = get_Mux_false(node);
3335 ir_node *sel = get_Mux_sel(node);
3336 ir_mode *mode = get_irn_mode(node);
3340 ia32_condition_code_t cc;
3342 assert(get_irn_mode(sel) == mode_b);
3344 is_abs = be_mux_is_abs(sel, mux_true, mux_false);
3346 return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node);
3349 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3350 if (mode_is_float(mode)) {
3351 ir_node *cmp_left = get_Cmp_left(sel);
3352 ir_node *cmp_right = get_Cmp_right(sel);
3353 ir_relation relation = get_Cmp_relation(sel);
3355 if (ia32_cg_config.use_sse2) {
3356 if (relation == ir_relation_less || relation == ir_relation_less_equal) {
3357 if (cmp_left == mux_true && cmp_right == mux_false) {
3358 /* Mux(a <= b, a, b) => MIN */
3359 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3360 match_commutative | match_am | match_two_users);
3361 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3362 /* Mux(a <= b, b, a) => MAX */
3363 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3364 match_commutative | match_am | match_two_users);
3366 } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
3367 if (cmp_left == mux_true && cmp_right == mux_false) {
3368 /* Mux(a >= b, a, b) => MAX */
3369 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3370 match_commutative | match_am | match_two_users);
3371 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3372 /* Mux(a >= b, b, a) => MIN */
3373 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3374 match_commutative | match_am | match_two_users);
3379 if (is_Const(mux_true) && is_Const(mux_false)) {
3380 ia32_address_mode_t am;
3385 flags = get_flags_node(sel, &cc);
3386 new_node = create_set_32bit(dbgi, new_block, flags, cc, node);
3388 if (ia32_cg_config.use_sse2) {
3389 /* cannot load from different mode on SSE */
3392 /* x87 can load any mode */
3396 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3398 switch (get_mode_size_bytes(new_mode)) {
3408 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3409 set_ia32_am_scale(new_node, 2);
3414 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3415 set_ia32_am_scale(new_node, 1);
3418 /* arg, shift 16 NOT supported */
3420 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3423 panic("Unsupported constant size");
3426 am.ls_mode = new_mode;
3427 am.addr.base = get_symconst_base();
3428 am.addr.index = new_node;
3429 am.addr.mem = nomem;
3431 am.addr.scale = scale;
3432 am.addr.use_frame = 0;
3433 am.addr.frame_entity = NULL;
3434 am.addr.symconst_sign = 0;
3435 am.mem_proj = am.addr.mem;
3436 am.op_type = ia32_AddrModeS;
3439 am.pinned = op_pin_state_floats;
3441 am.ins_permuted = false;
3443 if (ia32_cg_config.use_sse2)
3444 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3446 load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3447 set_am_attributes(load, &am);
3449 return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
3451 panic("cannot transform floating point Mux");
3454 assert(ia32_mode_needs_gp_reg(mode));
3457 ir_node *cmp_left = get_Cmp_left(sel);
3458 ir_node *cmp_right = get_Cmp_right(sel);
3459 ir_relation relation = get_Cmp_relation(sel);
3460 ir_node *val_true = mux_true;
3461 ir_node *val_false = mux_false;
3463 if (is_Const(val_true) && is_Const_null(val_true)) {
3464 ir_node *tmp = val_false;
3465 val_false = val_true;
3467 relation = get_negated_relation(relation);
3469 if (is_Const_0(val_false) && is_Sub(val_true)) {
3470 if ((relation & ir_relation_greater)
3471 && get_Sub_left(val_true) == cmp_left
3472 && get_Sub_right(val_true) == cmp_right) {
3473 return create_doz(node, cmp_left, cmp_right);
3475 if ((relation & ir_relation_less)
3476 && get_Sub_left(val_true) == cmp_right
3477 && get_Sub_right(val_true) == cmp_left) {
3478 return create_doz(node, cmp_right, cmp_left);
3483 flags = get_flags_node(sel, &cc);
3485 if (is_Const(mux_true) && is_Const(mux_false)) {
3486 /* both are const, good */
3487 ir_tarval *tv_true = get_Const_tarval(mux_true);
3488 ir_tarval *tv_false = get_Const_tarval(mux_false);
3489 setcc_transform_t res;
3492 find_const_transform(cc, tv_true, tv_false, &res);
3494 for (step = (int)res.num_steps - 1; step >= 0; --step) {
3497 switch (res.steps[step].transform) {
3499 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP);
3500 add_ia32_am_offs_int(new_node, res.steps[step].val);
3502 case SETCC_TR_ADDxx:
3503 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3506 new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
3507 set_ia32_am_scale(new_node, res.steps[step].scale);
3508 set_ia32_am_offs_int(new_node, res.steps[step].val);
3510 case SETCC_TR_LEAxx:
3511 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3512 set_ia32_am_scale(new_node, res.steps[step].scale);
3513 set_ia32_am_offs_int(new_node, res.steps[step].val);
3516 imm = ia32_immediate_from_long(res.steps[step].scale);
3517 new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
3520 new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
3523 new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
3526 imm = ia32_immediate_from_long(res.steps[step].val);
3527 new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3530 new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
3533 new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
3536 panic("unknown setcc transform");
3540 new_node = create_CMov(node, sel, flags, cc);
3548 * Create a conversion from x87 state register to general purpose.
3550 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3552 ir_node *block = be_transform_node(get_nodes_block(node));
3553 ir_node *op = get_Conv_op(node);
3554 ir_node *new_op = be_transform_node(op);
3555 ir_graph *irg = current_ir_graph;
3556 dbg_info *dbgi = get_irn_dbg_info(node);
3557 ir_mode *mode = get_irn_mode(node);
3558 ir_node *fist, *load, *mem;
3560 mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist);
3561 set_irn_pinned(fist, op_pin_state_floats);
3562 set_ia32_use_frame(fist);
3563 set_ia32_op_type(fist, ia32_AddrModeD);
3565 assert(get_mode_size_bits(mode) <= 32);
3566 /* exception we can only store signed 32 bit integers, so for unsigned
3567 we store a 64bit (signed) integer and load the lower bits */
3568 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3569 set_ia32_ls_mode(fist, mode_Ls);
3571 set_ia32_ls_mode(fist, mode_Is);
3573 SET_IA32_ORIG_NODE(fist, node);
3576 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3578 set_irn_pinned(load, op_pin_state_floats);
3579 set_ia32_use_frame(load);
3580 set_ia32_op_type(load, ia32_AddrModeS);
3581 set_ia32_ls_mode(load, mode_Is);
3582 if (get_ia32_ls_mode(fist) == mode_Ls) {
3583 ia32_attr_t *attr = get_ia32_attr(load);
3584 attr->data.need_64bit_stackent = 1;
3586 ia32_attr_t *attr = get_ia32_attr(load);
3587 attr->data.need_32bit_stackent = 1;
3589 SET_IA32_ORIG_NODE(load, node);
3591 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
3595 * Creates a x87 strict Conv by placing a Store and a Load
3597 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
3599 ir_node *block = get_nodes_block(node);
3600 ir_graph *irg = get_Block_irg(block);
3601 dbg_info *dbgi = get_irn_dbg_info(node);
3602 ir_node *frame = get_irg_frame(irg);
3603 ir_node *store, *load;
3606 store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3607 set_ia32_use_frame(store);
3608 set_ia32_op_type(store, ia32_AddrModeD);
3609 SET_IA32_ORIG_NODE(store, node);
3611 load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode);
3612 set_ia32_use_frame(load);
3613 set_ia32_op_type(load, ia32_AddrModeS);
3614 SET_IA32_ORIG_NODE(load, node);
3616 new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res);
3620 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3621 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3623 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3625 func = get_mode_size_bits(mode) == 8 ?
3626 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3627 return func(dbgi, block, base, index, mem, val, mode);
3631 * Create a conversion from general purpose to x87 register
3633 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3635 ir_node *src_block = get_nodes_block(node);
3636 ir_node *block = be_transform_node(src_block);
3637 ir_graph *irg = get_Block_irg(block);
3638 dbg_info *dbgi = get_irn_dbg_info(node);
3639 ir_node *op = get_Conv_op(node);
3640 ir_node *new_op = NULL;
3642 ir_mode *store_mode;
3647 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3648 if (possible_int_mode_for_fp(src_mode)) {
3649 ia32_address_mode_t am;
3651 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
3652 if (am.op_type == ia32_AddrModeS) {
3653 ia32_address_t *addr = &am.addr;
3655 fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
3656 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3658 set_am_attributes(fild, &am);
3659 SET_IA32_ORIG_NODE(fild, node);
3661 fix_mem_proj(fild, &am);
3666 if (new_op == NULL) {
3667 new_op = be_transform_node(op);
3670 mode = get_irn_mode(op);
3672 /* first convert to 32 bit signed if necessary */
3673 if (get_mode_size_bits(src_mode) < 32) {
3674 if (!upper_bits_clean(new_op, src_mode)) {
3675 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3676 SET_IA32_ORIG_NODE(new_op, node);
3681 assert(get_mode_size_bits(mode) == 32);
3684 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3686 set_ia32_use_frame(store);
3687 set_ia32_op_type(store, ia32_AddrModeD);
3688 set_ia32_ls_mode(store, mode_Iu);
3690 /* exception for 32bit unsigned, do a 64bit spill+load */
3691 if (!mode_is_signed(mode)) {
3694 ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
3696 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3697 noreg_GP, nomem, zero_const);
3699 set_ia32_use_frame(zero_store);
3700 set_ia32_op_type(zero_store, ia32_AddrModeD);
3701 add_ia32_am_offs_int(zero_store, 4);
3702 set_ia32_ls_mode(zero_store, mode_Iu);
3707 store = new_rd_Sync(dbgi, block, 2, in);
3708 store_mode = mode_Ls;
3710 store_mode = mode_Is;
3714 fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store);
3716 set_ia32_use_frame(fild);
3717 set_ia32_op_type(fild, ia32_AddrModeS);
3718 set_ia32_ls_mode(fild, store_mode);
3720 new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
3726 * Create a conversion from one integer mode into another one
3728 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3729 dbg_info *dbgi, ir_node *block, ir_node *op,
3732 ir_node *new_block = be_transform_node(block);
3734 ir_mode *smaller_mode;
3735 ia32_address_mode_t am;
3736 ia32_address_t *addr = &am.addr;
3739 if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
3740 smaller_mode = src_mode;
3742 smaller_mode = tgt_mode;
3745 #ifdef DEBUG_libfirm
3747 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3752 match_arguments(&am, block, NULL, op, NULL,
3753 match_am | match_8bit_am | match_16bit_am);
3755 if (upper_bits_clean(am.new_op2, smaller_mode)) {
3756 /* unnecessary conv. in theory it shouldn't have been AM */
3757 assert(is_ia32_NoReg_GP(addr->base));
3758 assert(is_ia32_NoReg_GP(addr->index));
3759 assert(is_NoMem(addr->mem));
3760 assert(am.addr.offset == 0);
3761 assert(am.addr.symconst_ent == NULL);
3765 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3766 addr->mem, am.new_op2, smaller_mode);
3767 set_am_attributes(new_node, &am);
3768 /* match_arguments assume that out-mode = in-mode, this isn't true here
3770 set_ia32_ls_mode(new_node, smaller_mode);
3771 SET_IA32_ORIG_NODE(new_node, node);
3772 new_node = fix_mem_proj(new_node, &am);
3777 * Transforms a Conv node.
3779 * @return The created ia32 Conv node
3781 static ir_node *gen_Conv(ir_node *node)
3783 ir_node *block = get_nodes_block(node);
3784 ir_node *new_block = be_transform_node(block);
3785 ir_node *op = get_Conv_op(node);
3786 ir_node *new_op = NULL;
3787 dbg_info *dbgi = get_irn_dbg_info(node);
3788 ir_mode *src_mode = get_irn_mode(op);
3789 ir_mode *tgt_mode = get_irn_mode(node);
3790 int src_bits = get_mode_size_bits(src_mode);
3791 int tgt_bits = get_mode_size_bits(tgt_mode);
3792 ir_node *res = NULL;
3794 assert(!mode_is_int(src_mode) || src_bits <= 32);
3795 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3797 /* modeB -> X should already be lowered by the lower_mode_b pass */
3798 if (src_mode == mode_b) {
3799 panic("ConvB not lowered %+F", node);
3802 if (src_mode == tgt_mode) {
3803 if (get_Conv_strict(node)) {
3804 if (ia32_cg_config.use_sse2) {
3805 /* when we are in SSE mode, we can kill all strict no-op conversion */
3806 return be_transform_node(op);
3809 /* this should be optimized already, but who knows... */
3810 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
3811 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3812 return be_transform_node(op);
3816 if (mode_is_float(src_mode)) {
3817 new_op = be_transform_node(op);
3818 /* we convert from float ... */
3819 if (mode_is_float(tgt_mode)) {
3821 if (ia32_cg_config.use_sse2) {
3822 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3823 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3825 set_ia32_ls_mode(res, tgt_mode);
3827 if (get_Conv_strict(node)) {
3828 /* if fp_no_float_fold is not set then we assume that we
3829 * don't have any float operations in a non
3830 * mode_float_arithmetic mode and can skip strict upconvs */
3831 if (src_bits < tgt_bits) {
3832 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3835 res = gen_x87_strict_conv(tgt_mode, new_op);
3836 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3840 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3845 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3846 if (ia32_cg_config.use_sse2) {
3847 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3849 set_ia32_ls_mode(res, src_mode);
3851 return gen_x87_fp_to_gp(node);
3855 /* we convert from int ... */
3856 if (mode_is_float(tgt_mode)) {
3858 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3859 if (ia32_cg_config.use_sse2) {
3860 new_op = be_transform_node(op);
3861 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3863 set_ia32_ls_mode(res, tgt_mode);
3865 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3866 unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode);
3867 res = gen_x87_gp_to_fp(node, src_mode);
3869 /* we need a strict-Conv, if the int mode has more bits than the
3871 if (float_mantissa < int_mantissa) {
3872 res = gen_x87_strict_conv(tgt_mode, res);
3873 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3877 } else if (tgt_mode == mode_b) {
3878 /* mode_b lowering already took care that we only have 0/1 values */
3879 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3880 src_mode, tgt_mode));
3881 return be_transform_node(op);
3884 if (src_bits == tgt_bits) {
3885 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3886 src_mode, tgt_mode));
3887 return be_transform_node(op);
3890 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3898 static ir_node *create_immediate_or_transform(ir_node *node,
3899 char immediate_constraint_type)
3901 ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
3902 if (new_node == NULL) {
3903 new_node = be_transform_node(node);
3909 * Transforms a FrameAddr into an ia32 Add.
3911 static ir_node *gen_be_FrameAddr(ir_node *node)
3913 ir_node *block = be_transform_node(get_nodes_block(node));
3914 ir_node *op = be_get_FrameAddr_frame(node);
3915 ir_node *new_op = be_transform_node(op);
3916 dbg_info *dbgi = get_irn_dbg_info(node);
3919 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
3920 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3921 set_ia32_use_frame(new_node);
3923 SET_IA32_ORIG_NODE(new_node, node);
3929 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3931 static ir_node *gen_be_Return(ir_node *node)
3933 ir_graph *irg = current_ir_graph;
3934 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3935 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3936 ir_entity *ent = get_irg_entity(irg);
3937 ir_type *tp = get_entity_type(ent);
3942 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3943 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3945 int pn_ret_val, pn_ret_mem, arity, i;
3947 assert(ret_val != NULL);
3948 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3949 return be_duplicate_node(node);
3952 res_type = get_method_res_type(tp, 0);
3954 if (! is_Primitive_type(res_type)) {
3955 return be_duplicate_node(node);
3958 mode = get_type_mode(res_type);
3959 if (! mode_is_float(mode)) {
3960 return be_duplicate_node(node);
3963 assert(get_method_n_ress(tp) == 1);
3965 pn_ret_val = get_Proj_proj(ret_val);
3966 pn_ret_mem = get_Proj_proj(ret_mem);
3968 /* get the Barrier */
3969 barrier = get_Proj_pred(ret_val);
3971 /* get result input of the Barrier */
3972 ret_val = get_irn_n(barrier, pn_ret_val);
3973 new_ret_val = be_transform_node(ret_val);
3975 /* get memory input of the Barrier */
3976 ret_mem = get_irn_n(barrier, pn_ret_mem);
3977 new_ret_mem = be_transform_node(ret_mem);
3979 frame = get_irg_frame(irg);
3981 dbgi = get_irn_dbg_info(barrier);
3982 block = be_transform_node(get_nodes_block(barrier));
3984 /* store xmm0 onto stack */
3985 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
3986 new_ret_mem, new_ret_val);
3987 set_ia32_ls_mode(sse_store, mode);
3988 set_ia32_op_type(sse_store, ia32_AddrModeD);
3989 set_ia32_use_frame(sse_store);
3991 /* load into x87 register */
3992 fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode);
3993 set_ia32_op_type(fld, ia32_AddrModeS);
3994 set_ia32_use_frame(fld);
3996 mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
3997 fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
3999 /* create a new barrier */
4000 arity = get_irn_arity(barrier);
4001 in = ALLOCAN(ir_node*, arity);
4002 for (i = 0; i < arity; ++i) {
4005 if (i == pn_ret_val) {
4007 } else if (i == pn_ret_mem) {
4010 ir_node *in = get_irn_n(barrier, i);
4011 new_in = be_transform_node(in);
4016 new_barrier = new_ir_node(dbgi, irg, block,
4017 get_irn_op(barrier), get_irn_mode(barrier),
4019 copy_node_attr(irg, barrier, new_barrier);
4020 be_duplicate_deps(barrier, new_barrier);
4021 be_set_transformed_node(barrier, new_barrier);
4023 /* transform normally */
4024 return be_duplicate_node(node);
4028 * Transform a be_AddSP into an ia32_SubSP.
4030 static ir_node *gen_be_AddSP(ir_node *node)
4032 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
4033 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
4035 return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
4036 match_am | match_immediate);
4040 * Transform a be_SubSP into an ia32_AddSP
4042 static ir_node *gen_be_SubSP(ir_node *node)
4044 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
4045 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
4047 return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
4048 match_am | match_immediate);
4052 * Change some phi modes
4054 static ir_node *gen_Phi(ir_node *node)
4056 const arch_register_req_t *req;
4057 ir_node *block = be_transform_node(get_nodes_block(node));
4058 ir_graph *irg = current_ir_graph;
4059 dbg_info *dbgi = get_irn_dbg_info(node);
4060 ir_mode *mode = get_irn_mode(node);
4063 if (ia32_mode_needs_gp_reg(mode)) {
4064 /* we shouldn't have any 64bit stuff around anymore */
4065 assert(get_mode_size_bits(mode) <= 32);
4066 /* all integer operations are on 32bit registers now */
4068 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
4069 } else if (mode_is_float(mode)) {
4070 if (ia32_cg_config.use_sse2) {
4072 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
4075 req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
4078 req = arch_no_register_req;
4081 /* phi nodes allow loops, so we use the old arguments for now
4082 * and fix this later */
4083 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
4084 get_irn_in(node) + 1);
4085 copy_node_attr(irg, node, phi);
4086 be_duplicate_deps(node, phi);
4088 arch_set_out_register_req(phi, 0, req);
4090 be_enqueue_preds(node);
4095 static ir_node *gen_Jmp(ir_node *node)
4097 ir_node *block = get_nodes_block(node);
4098 ir_node *new_block = be_transform_node(block);
4099 dbg_info *dbgi = get_irn_dbg_info(node);
4102 new_node = new_bd_ia32_Jmp(dbgi, new_block);
4103 SET_IA32_ORIG_NODE(new_node, node);
4111 static ir_node *gen_IJmp(ir_node *node)
4113 ir_node *block = get_nodes_block(node);
4114 ir_node *new_block = be_transform_node(block);
4115 dbg_info *dbgi = get_irn_dbg_info(node);
4116 ir_node *op = get_IJmp_target(node);
4118 ia32_address_mode_t am;
4119 ia32_address_t *addr = &am.addr;
4121 assert(get_irn_mode(op) == mode_P);
4123 match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
4125 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
4126 addr->mem, am.new_op2);
4127 set_am_attributes(new_node, &am);
4128 SET_IA32_ORIG_NODE(new_node, node);
4130 new_node = fix_mem_proj(new_node, &am);
4135 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
4137 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
4138 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
4140 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
4141 match_immediate | match_mode_neutral);
4144 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
4146 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
4147 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
4148 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
4152 static ir_node *gen_ia32_l_SarDep(ir_node *node)
4154 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
4155 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
4156 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
4160 static ir_node *gen_ia32_l_Add(ir_node *node)
4162 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4163 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4164 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
4165 match_commutative | match_am | match_immediate |
4166 match_mode_neutral);
4168 if (is_Proj(lowered)) {
4169 lowered = get_Proj_pred(lowered);
4171 assert(is_ia32_Add(lowered));
4172 set_irn_mode(lowered, mode_T);
4178 static ir_node *gen_ia32_l_Adc(ir_node *node)
4180 return gen_binop_flags(node, new_bd_ia32_Adc,
4181 match_commutative | match_am | match_immediate |
4182 match_mode_neutral);
4186 * Transforms a l_MulS into a "real" MulS node.
4188 * @return the created ia32 Mul node
4190 static ir_node *gen_ia32_l_Mul(ir_node *node)
4192 ir_node *left = get_binop_left(node);
4193 ir_node *right = get_binop_right(node);
4195 return gen_binop(node, left, right, new_bd_ia32_Mul,
4196 match_commutative | match_am | match_mode_neutral);
4200 * Transforms a l_IMulS into a "real" IMul1OPS node.
4202 * @return the created ia32 IMul1OP node
4204 static ir_node *gen_ia32_l_IMul(ir_node *node)
4206 ir_node *left = get_binop_left(node);
4207 ir_node *right = get_binop_right(node);
4209 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
4210 match_commutative | match_am | match_mode_neutral);
4213 static ir_node *gen_ia32_l_Sub(ir_node *node)
4215 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4216 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4217 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
4218 match_am | match_immediate | match_mode_neutral);
4220 if (is_Proj(lowered)) {
4221 lowered = get_Proj_pred(lowered);
4223 assert(is_ia32_Sub(lowered));
4224 set_irn_mode(lowered, mode_T);
4230 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4232 return gen_binop_flags(node, new_bd_ia32_Sbb,
4233 match_am | match_immediate | match_mode_neutral);
4237 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4238 * op1 - target to be shifted
4239 * op2 - contains bits to be shifted into target
4241 * Only op3 can be an immediate.
4243 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4244 ir_node *low, ir_node *count)
4246 ir_node *block = get_nodes_block(node);
4247 ir_node *new_block = be_transform_node(block);
4248 dbg_info *dbgi = get_irn_dbg_info(node);
4249 ir_node *new_high = be_transform_node(high);
4250 ir_node *new_low = be_transform_node(low);
4254 /* the shift amount can be any mode that is bigger than 5 bits, since all
4255 * other bits are ignored anyway */
4256 while (is_Conv(count) &&
4257 get_irn_n_edges(count) == 1 &&
4258 mode_is_int(get_irn_mode(count))) {
4259 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4260 count = get_Conv_op(count);
4262 new_count = create_immediate_or_transform(count, 0);
4264 if (is_ia32_l_ShlD(node)) {
4265 new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
4268 new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
4271 SET_IA32_ORIG_NODE(new_node, node);
4276 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4278 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4279 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4280 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4281 return gen_lowered_64bit_shifts(node, high, low, count);
4284 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4286 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4287 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4288 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4289 return gen_lowered_64bit_shifts(node, high, low, count);
4292 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4294 ir_node *src_block = get_nodes_block(node);
4295 ir_node *block = be_transform_node(src_block);
4296 ir_graph *irg = current_ir_graph;
4297 dbg_info *dbgi = get_irn_dbg_info(node);
4298 ir_node *frame = get_irg_frame(irg);
4299 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4300 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4301 ir_node *new_val_low = be_transform_node(val_low);
4302 ir_node *new_val_high = be_transform_node(val_high);
4304 ir_node *sync, *fild, *res;
4305 ir_node *store_low, *store_high;
4307 if (ia32_cg_config.use_sse2) {
4308 panic("ia32_l_LLtoFloat not implemented for SSE2");
4312 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4314 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4316 SET_IA32_ORIG_NODE(store_low, node);
4317 SET_IA32_ORIG_NODE(store_high, node);
4319 set_ia32_use_frame(store_low);
4320 set_ia32_use_frame(store_high);
4321 set_ia32_op_type(store_low, ia32_AddrModeD);
4322 set_ia32_op_type(store_high, ia32_AddrModeD);
4323 set_ia32_ls_mode(store_low, mode_Iu);
4324 set_ia32_ls_mode(store_high, mode_Is);
4325 add_ia32_am_offs_int(store_high, 4);
4329 sync = new_rd_Sync(dbgi, block, 2, in);
4332 fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
4334 set_ia32_use_frame(fild);
4335 set_ia32_op_type(fild, ia32_AddrModeS);
4336 set_ia32_ls_mode(fild, mode_Ls);
4338 SET_IA32_ORIG_NODE(fild, node);
4340 res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
4342 if (! mode_is_signed(get_irn_mode(val_high))) {
4343 ia32_address_mode_t am;
4345 ir_node *count = ia32_create_Immediate(NULL, 0, 31);
4348 am.addr.base = get_symconst_base();
4349 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4350 am.addr.mem = nomem;
4353 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4354 am.addr.use_frame = 0;
4355 am.addr.frame_entity = NULL;
4356 am.addr.symconst_sign = 0;
4357 am.ls_mode = mode_F;
4358 am.mem_proj = nomem;
4359 am.op_type = ia32_AddrModeS;
4361 am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
4362 am.pinned = op_pin_state_floats;
4364 am.ins_permuted = false;
4366 fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4367 am.new_op1, am.new_op2, get_fpcw());
4368 set_am_attributes(fadd, &am);
4370 set_irn_mode(fadd, mode_T);
4371 res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
4376 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4378 ir_node *src_block = get_nodes_block(node);
4379 ir_node *block = be_transform_node(src_block);
4380 ir_graph *irg = get_Block_irg(block);
4381 dbg_info *dbgi = get_irn_dbg_info(node);
4382 ir_node *frame = get_irg_frame(irg);
4383 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4384 ir_node *new_val = be_transform_node(val);
4385 ir_node *fist, *mem;
4387 mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist);
4388 SET_IA32_ORIG_NODE(fist, node);
4389 set_ia32_use_frame(fist);
4390 set_ia32_op_type(fist, ia32_AddrModeD);
4391 set_ia32_ls_mode(fist, mode_Ls);
4396 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4398 ir_node *block = be_transform_node(get_nodes_block(node));
4399 ir_graph *irg = get_Block_irg(block);
4400 ir_node *pred = get_Proj_pred(node);
4401 ir_node *new_pred = be_transform_node(pred);
4402 ir_node *frame = get_irg_frame(irg);
4403 dbg_info *dbgi = get_irn_dbg_info(node);
4404 long pn = get_Proj_proj(node);
4409 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4410 SET_IA32_ORIG_NODE(load, node);
4411 set_ia32_use_frame(load);
4412 set_ia32_op_type(load, ia32_AddrModeS);
4413 set_ia32_ls_mode(load, mode_Iu);
4414 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4415 * 32 bit from it with this particular load */
4416 attr = get_ia32_attr(load);
4417 attr->data.need_64bit_stackent = 1;
4419 if (pn == pn_ia32_l_FloattoLL_res_high) {
4420 add_ia32_am_offs_int(load, 4);
4422 assert(pn == pn_ia32_l_FloattoLL_res_low);
4425 proj = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4431 * Transform the Projs of an AddSP.
4433 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4435 ir_node *pred = get_Proj_pred(node);
4436 ir_node *new_pred = be_transform_node(pred);
4437 dbg_info *dbgi = get_irn_dbg_info(node);
4438 long proj = get_Proj_proj(node);
4440 if (proj == pn_be_AddSP_sp) {
4441 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4442 pn_ia32_SubSP_stack);
4443 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4445 } else if (proj == pn_be_AddSP_res) {
4446 return new_rd_Proj(dbgi, new_pred, mode_Iu,
4447 pn_ia32_SubSP_addr);
4448 } else if (proj == pn_be_AddSP_M) {
4449 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_SubSP_M);
4452 panic("No idea how to transform proj->AddSP");
4456 * Transform the Projs of a SubSP.
4458 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4460 ir_node *pred = get_Proj_pred(node);
4461 ir_node *new_pred = be_transform_node(pred);
4462 dbg_info *dbgi = get_irn_dbg_info(node);
4463 long proj = get_Proj_proj(node);
4465 if (proj == pn_be_SubSP_sp) {
4466 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4467 pn_ia32_AddSP_stack);
4468 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4470 } else if (proj == pn_be_SubSP_M) {
4471 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
4474 panic("No idea how to transform proj->SubSP");
4478 * Transform and renumber the Projs from a Load.
4480 static ir_node *gen_Proj_Load(ir_node *node)
4483 ir_node *block = be_transform_node(get_nodes_block(node));
4484 ir_node *pred = get_Proj_pred(node);
4485 dbg_info *dbgi = get_irn_dbg_info(node);
4486 long proj = get_Proj_proj(node);
4488 /* loads might be part of source address mode matches, so we don't
4489 * transform the ProjMs yet (with the exception of loads whose result is
4492 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4495 /* this is needed, because sometimes we have loops that are only
4496 reachable through the ProjM */
4497 be_enqueue_preds(node);
4498 /* do it in 2 steps, to silence firm verifier */
4499 res = new_rd_Proj(dbgi, pred, mode_M, pn_Load_M);
4500 set_Proj_proj(res, pn_ia32_mem);
4504 /* renumber the proj */
4505 new_pred = be_transform_node(pred);
4506 if (is_ia32_Load(new_pred)) {
4509 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
4511 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
4512 case pn_Load_X_regular:
4513 return new_rd_Jmp(dbgi, block);
4514 case pn_Load_X_except:
4515 /* This Load might raise an exception. Mark it. */
4516 set_ia32_exc_label(new_pred, 1);
4517 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc);
4521 } else if (is_ia32_Conv_I2I(new_pred) ||
4522 is_ia32_Conv_I2I8Bit(new_pred)) {
4523 set_irn_mode(new_pred, mode_T);
4524 if (proj == pn_Load_res) {
4525 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
4526 } else if (proj == pn_Load_M) {
4527 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
4529 } else if (is_ia32_xLoad(new_pred)) {
4532 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
4534 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
4535 case pn_Load_X_regular:
4536 return new_rd_Jmp(dbgi, block);
4537 case pn_Load_X_except:
4538 /* This Load might raise an exception. Mark it. */
4539 set_ia32_exc_label(new_pred, 1);
4540 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc);
4544 } else if (is_ia32_vfld(new_pred)) {
4547 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
4549 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
4550 case pn_Load_X_regular:
4551 return new_rd_Jmp(dbgi, block);
4552 case pn_Load_X_except:
4553 /* This Load might raise an exception. Mark it. */
4554 set_ia32_exc_label(new_pred, 1);
4555 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc);
4560 /* can happen for ProJMs when source address mode happened for the
4563 /* however it should not be the result proj, as that would mean the
4564 load had multiple users and should not have been used for
4566 if (proj != pn_Load_M) {
4567 panic("internal error: transformed node not a Load");
4569 return new_rd_Proj(dbgi, new_pred, mode_M, 1);
4572 panic("No idea how to transform proj");
4576 * Transform and renumber the Projs from a Div or Mod instruction.
4578 static ir_node *gen_Proj_Div(ir_node *node)
4580 ir_node *block = be_transform_node(get_nodes_block(node));
4581 ir_node *pred = get_Proj_pred(node);
4582 ir_node *new_pred = be_transform_node(pred);
4583 dbg_info *dbgi = get_irn_dbg_info(node);
4584 long proj = get_Proj_proj(node);
4586 assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
4587 assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res);
4591 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4592 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4593 } else if (is_ia32_xDiv(new_pred)) {
4594 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
4595 } else if (is_ia32_vfdiv(new_pred)) {
4596 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
4598 panic("Div transformed to unexpected thing %+F", new_pred);
4601 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4602 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
4603 } else if (is_ia32_xDiv(new_pred)) {
4604 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
4605 } else if (is_ia32_vfdiv(new_pred)) {
4606 return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4608 panic("Div transformed to unexpected thing %+F", new_pred);
4610 case pn_Div_X_regular:
4611 return new_rd_Jmp(dbgi, block);
4612 case pn_Div_X_except:
4613 set_ia32_exc_label(new_pred, 1);
4614 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
4619 panic("No idea how to transform proj->Div");
4623 * Transform and renumber the Projs from a Div or Mod instruction.
4625 static ir_node *gen_Proj_Mod(ir_node *node)
4627 ir_node *pred = get_Proj_pred(node);
4628 ir_node *new_pred = be_transform_node(pred);
4629 dbg_info *dbgi = get_irn_dbg_info(node);
4630 long proj = get_Proj_proj(node);
4632 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4633 assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
4634 assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res);
4638 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4640 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4641 case pn_Mod_X_except:
4642 set_ia32_exc_label(new_pred, 1);
4643 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
4647 panic("No idea how to transform proj->Mod");
4651 * Transform and renumber the Projs from a CopyB.
4653 static ir_node *gen_Proj_CopyB(ir_node *node)
4655 ir_node *pred = get_Proj_pred(node);
4656 ir_node *new_pred = be_transform_node(pred);
4657 dbg_info *dbgi = get_irn_dbg_info(node);
4658 long proj = get_Proj_proj(node);
4662 if (is_ia32_CopyB_i(new_pred)) {
4663 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
4664 } else if (is_ia32_CopyB(new_pred)) {
4665 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
4672 panic("No idea how to transform proj->CopyB");
4675 static ir_node *gen_be_Call(ir_node *node)
4677 dbg_info *const dbgi = get_irn_dbg_info(node);
4678 ir_node *const src_block = get_nodes_block(node);
4679 ir_node *const block = be_transform_node(src_block);
4680 ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
4681 ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
4682 ir_node *const sp = be_transform_node(src_sp);
4683 ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
4684 ia32_address_mode_t am;
4685 ia32_address_t *const addr = &am.addr;
4690 ir_node * eax = noreg_GP;
4691 ir_node * ecx = noreg_GP;
4692 ir_node * edx = noreg_GP;
4693 unsigned const pop = be_Call_get_pop(node);
4694 ir_type *const call_tp = be_Call_get_type(node);
4695 int old_no_pic_adjust;
4697 /* Run the x87 simulator if the call returns a float value */
4698 if (get_method_n_ress(call_tp) > 0) {
4699 ir_type *const res_type = get_method_res_type(call_tp, 0);
4700 ir_mode *const res_mode = get_type_mode(res_type);
4702 if (res_mode != NULL && mode_is_float(res_mode)) {
4703 ir_graph *irg = current_ir_graph;
4704 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4705 irg_data->do_x87_sim = 1;
4709 /* We do not want be_Call direct calls */
4710 assert(be_Call_get_entity(node) == NULL);
4712 /* special case for PIC trampoline calls */
4713 old_no_pic_adjust = ia32_no_pic_adjust;
4714 ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
4716 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4717 match_am | match_immediate);
4719 ia32_no_pic_adjust = old_no_pic_adjust;
4721 i = get_irn_arity(node) - 1;
4722 fpcw = be_transform_node(get_irn_n(node, i--));
4723 for (; i >= be_pos_Call_first_arg; --i) {
4724 arch_register_req_t const *const req = arch_get_register_req(node, i);
4725 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4727 assert(req->type == arch_register_req_type_limited);
4728 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4730 switch (*req->limited) {
4731 case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4732 case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4733 case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4734 default: panic("Invalid GP register for register parameter");
4738 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4739 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4740 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4741 set_am_attributes(call, &am);
4742 call = fix_mem_proj(call, &am);
4744 if (get_irn_pinned(node) == op_pin_state_pinned)
4745 set_irn_pinned(call, op_pin_state_pinned);
4747 SET_IA32_ORIG_NODE(call, node);
4749 if (ia32_cg_config.use_sse2) {
4750 /* remember this call for post-processing */
4751 ARR_APP1(ir_node *, call_list, call);
4752 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4759 * Transform Builtin trap
4761 static ir_node *gen_trap(ir_node *node)
4763 dbg_info *dbgi = get_irn_dbg_info(node);
4764 ir_node *block = be_transform_node(get_nodes_block(node));
4765 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4767 return new_bd_ia32_UD2(dbgi, block, mem);
4771 * Transform Builtin debugbreak
4773 static ir_node *gen_debugbreak(ir_node *node)
4775 dbg_info *dbgi = get_irn_dbg_info(node);
4776 ir_node *block = be_transform_node(get_nodes_block(node));
4777 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4779 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4783 * Transform Builtin return_address
4785 static ir_node *gen_return_address(ir_node *node)
4787 ir_node *param = get_Builtin_param(node, 0);
4788 ir_node *frame = get_Builtin_param(node, 1);
4789 dbg_info *dbgi = get_irn_dbg_info(node);
4790 ir_tarval *tv = get_Const_tarval(param);
4791 unsigned long value = get_tarval_long(tv);
4793 ir_node *block = be_transform_node(get_nodes_block(node));
4794 ir_node *ptr = be_transform_node(frame);
4798 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4799 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4800 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4803 /* load the return address from this frame */
4804 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4806 set_irn_pinned(load, get_irn_pinned(node));
4807 set_ia32_op_type(load, ia32_AddrModeS);
4808 set_ia32_ls_mode(load, mode_Iu);
4810 set_ia32_am_offs_int(load, 0);
4811 set_ia32_use_frame(load);
4812 set_ia32_frame_ent(load, ia32_get_return_address_entity());
4814 if (get_irn_pinned(node) == op_pin_state_floats) {
4815 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4816 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4817 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4818 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4821 SET_IA32_ORIG_NODE(load, node);
4822 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4826 * Transform Builtin frame_address
4828 static ir_node *gen_frame_address(ir_node *node)
4830 ir_node *param = get_Builtin_param(node, 0);
4831 ir_node *frame = get_Builtin_param(node, 1);
4832 dbg_info *dbgi = get_irn_dbg_info(node);
4833 ir_tarval *tv = get_Const_tarval(param);
4834 unsigned long value = get_tarval_long(tv);
4836 ir_node *block = be_transform_node(get_nodes_block(node));
4837 ir_node *ptr = be_transform_node(frame);
4842 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4843 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4844 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4847 /* load the frame address from this frame */
4848 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4850 set_irn_pinned(load, get_irn_pinned(node));
4851 set_ia32_op_type(load, ia32_AddrModeS);
4852 set_ia32_ls_mode(load, mode_Iu);
4854 ent = ia32_get_frame_address_entity();
4856 set_ia32_am_offs_int(load, 0);
4857 set_ia32_use_frame(load);
4858 set_ia32_frame_ent(load, ent);
4860 /* will fail anyway, but gcc does this: */
4861 set_ia32_am_offs_int(load, 0);
4864 if (get_irn_pinned(node) == op_pin_state_floats) {
4865 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
4866 && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
4867 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4868 arch_irn_add_flags(load, arch_irn_flags_rematerializable);
4871 SET_IA32_ORIG_NODE(load, node);
4872 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4876 * Transform Builtin frame_address
4878 static ir_node *gen_prefetch(ir_node *node)
4881 ir_node *ptr, *block, *mem, *base, *index;
4882 ir_node *param, *new_node;
4885 ia32_address_t addr;
4887 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
4888 /* no prefetch at all, route memory */
4889 return be_transform_node(get_Builtin_mem(node));
4892 param = get_Builtin_param(node, 1);
4893 tv = get_Const_tarval(param);
4894 rw = get_tarval_long(tv);
4896 /* construct load address */
4897 memset(&addr, 0, sizeof(addr));
4898 ptr = get_Builtin_param(node, 0);
4899 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
4906 base = be_transform_node(base);
4909 if (index == NULL) {
4912 index = be_transform_node(index);
4915 dbgi = get_irn_dbg_info(node);
4916 block = be_transform_node(get_nodes_block(node));
4917 mem = be_transform_node(get_Builtin_mem(node));
4919 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
4920 /* we have 3DNow!, this was already checked above */
4921 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem);
4922 } else if (ia32_cg_config.use_sse_prefetch) {
4923 /* note: rw == 1 is IGNORED in that case */
4924 param = get_Builtin_param(node, 2);
4925 tv = get_Const_tarval(param);
4926 locality = get_tarval_long(tv);
4928 /* SSE style prefetch */
4931 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem);
4934 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem);
4937 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem);
4940 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem);
4944 assert(ia32_cg_config.use_3dnow_prefetch);
4945 /* 3DNow! style prefetch */
4946 new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem);
4949 set_irn_pinned(new_node, get_irn_pinned(node));
4950 set_ia32_op_type(new_node, ia32_AddrModeS);
4951 set_ia32_ls_mode(new_node, mode_Bu);
4952 set_address(new_node, &addr);
4954 SET_IA32_ORIG_NODE(new_node, node);
4956 be_dep_on_frame(new_node);
4957 return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
4961 * Transform bsf like node
4963 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
4965 ir_node *param = get_Builtin_param(node, 0);
4966 dbg_info *dbgi = get_irn_dbg_info(node);
4968 ir_node *block = get_nodes_block(node);
4969 ir_node *new_block = be_transform_node(block);
4971 ia32_address_mode_t am;
4972 ia32_address_t *addr = &am.addr;
4975 match_arguments(&am, block, NULL, param, NULL, match_am);
4977 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
4978 set_am_attributes(cnt, &am);
4979 set_ia32_ls_mode(cnt, get_irn_mode(param));
4981 SET_IA32_ORIG_NODE(cnt, node);
4982 return fix_mem_proj(cnt, &am);
4986 * Transform builtin ffs.
4988 static ir_node *gen_ffs(ir_node *node)
4990 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
4991 ir_node *real = skip_Proj(bsf);
4992 dbg_info *dbgi = get_irn_dbg_info(real);
4993 ir_node *block = get_nodes_block(real);
4994 ir_node *flag, *set, *conv, *neg, *orn, *add;
4997 if (get_irn_mode(real) != mode_T) {
4998 set_irn_mode(real, mode_T);
4999 bsf = new_r_Proj(real, mode_Iu, pn_ia32_res);
5002 flag = new_r_Proj(real, mode_b, pn_ia32_flags);
5005 set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal);
5006 SET_IA32_ORIG_NODE(set, node);
5009 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
5010 SET_IA32_ORIG_NODE(conv, node);
5013 neg = new_bd_ia32_Neg(dbgi, block, conv);
5016 orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
5017 set_ia32_commutative(orn);
5020 add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP);
5021 add_ia32_am_offs_int(add, 1);
5026 * Transform builtin clz.
5028 static ir_node *gen_clz(ir_node *node)
5030 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
5031 ir_node *real = skip_Proj(bsr);
5032 dbg_info *dbgi = get_irn_dbg_info(real);
5033 ir_node *block = get_nodes_block(real);
5034 ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
5036 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
5040 * Transform builtin ctz.
5042 static ir_node *gen_ctz(ir_node *node)
5044 return gen_unop_AM(node, new_bd_ia32_Bsf);
5048 * Transform builtin parity.
5050 static ir_node *gen_parity(ir_node *node)
5052 dbg_info *dbgi = get_irn_dbg_info(node);
5053 ir_node *block = get_nodes_block(node);
5054 ir_node *new_block = be_transform_node(block);
5055 ir_node *param = get_Builtin_param(node, 0);
5056 ir_node *new_param = be_transform_node(param);
5059 /* the x86 parity bit is stupid: it only looks at the lowest byte,
5060 * so we have to do complicated xoring first.
5061 * (we should also better lower this before the backend so we still have a
5062 * chance for CSE, constant folding and other goodies for some of these
5065 ir_node *count = ia32_create_Immediate(NULL, 0, 16);
5066 ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
5067 ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
5069 ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor);
5072 set_irn_mode(xor2, mode_T);
5073 flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
5076 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity);
5077 SET_IA32_ORIG_NODE(new_node, node);
5080 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
5081 nomem, new_node, mode_Bu);
5082 SET_IA32_ORIG_NODE(new_node, node);
5087 * Transform builtin popcount
5089 static ir_node *gen_popcount(ir_node *node)
5091 ir_node *param = get_Builtin_param(node, 0);
5092 dbg_info *dbgi = get_irn_dbg_info(node);
5094 ir_node *block = get_nodes_block(node);
5095 ir_node *new_block = be_transform_node(block);
5098 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
5100 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
5101 if (ia32_cg_config.use_popcnt) {
5102 ia32_address_mode_t am;
5103 ia32_address_t *addr = &am.addr;
5106 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
5108 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5109 set_am_attributes(cnt, &am);
5110 set_ia32_ls_mode(cnt, get_irn_mode(param));
5112 SET_IA32_ORIG_NODE(cnt, node);
5113 return fix_mem_proj(cnt, &am);
5116 new_param = be_transform_node(param);
5118 /* do the standard popcount algo */
5119 /* TODO: This is stupid, we should transform this before the backend,
5120 * to get CSE, localopts, etc. for the operations
5121 * TODO: This is also not the optimal algorithm (it is just the starting
5122 * example in hackers delight, they optimize it more on the following page)
5123 * But I'm too lazy to fix this now, as the code should get lowered before
5124 * the backend anyway.
5127 /* m1 = x & 0x55555555 */
5128 imm = ia32_create_Immediate(NULL, 0, 0x55555555);
5129 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
5132 simm = ia32_create_Immediate(NULL, 0, 1);
5133 s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
5135 /* m2 = s1 & 0x55555555 */
5136 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
5139 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
5141 /* m4 = m3 & 0x33333333 */
5142 imm = ia32_create_Immediate(NULL, 0, 0x33333333);
5143 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
5146 simm = ia32_create_Immediate(NULL, 0, 2);
5147 s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
5149 /* m5 = s2 & 0x33333333 */
5150 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
5153 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
5155 /* m7 = m6 & 0x0F0F0F0F */
5156 imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
5157 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
5160 simm = ia32_create_Immediate(NULL, 0, 4);
5161 s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
5163 /* m8 = s3 & 0x0F0F0F0F */
5164 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
5167 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
5169 /* m10 = m9 & 0x00FF00FF */
5170 imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
5171 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
5174 simm = ia32_create_Immediate(NULL, 0, 8);
5175 s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
5177 /* m11 = s4 & 0x00FF00FF */
5178 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
5180 /* m12 = m10 + m11 */
5181 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
5183 /* m13 = m12 & 0x0000FFFF */
5184 imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
5185 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
5187 /* s5 = m12 >> 16 */
5188 simm = ia32_create_Immediate(NULL, 0, 16);
5189 s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
5191 /* res = m13 + s5 */
5192 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
5196 * Transform builtin byte swap.
5198 static ir_node *gen_bswap(ir_node *node)
5200 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
5201 dbg_info *dbgi = get_irn_dbg_info(node);
5203 ir_node *block = get_nodes_block(node);
5204 ir_node *new_block = be_transform_node(block);
5205 ir_mode *mode = get_irn_mode(param);
5206 unsigned size = get_mode_size_bits(mode);
5207 ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4;
5211 if (ia32_cg_config.use_i486) {
5212 /* swap available */
5213 return new_bd_ia32_Bswap(dbgi, new_block, param);
5215 s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5216 s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5218 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00));
5219 m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1);
5221 s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
5223 m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000));
5224 m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3);
5226 s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
5227 return new_bd_ia32_Lea(dbgi, new_block, m4, s4);
5230 /* swap16 always available */
5231 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5234 panic("Invalid bswap size (%d)", size);
5239 * Transform builtin outport.
5241 static ir_node *gen_outport(ir_node *node)
5243 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5244 ir_node *oldv = get_Builtin_param(node, 1);
5245 ir_mode *mode = get_irn_mode(oldv);
5246 ir_node *value = be_transform_node(oldv);
5247 ir_node *block = be_transform_node(get_nodes_block(node));
5248 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5249 dbg_info *dbgi = get_irn_dbg_info(node);
5251 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5252 set_ia32_ls_mode(res, mode);
5257 * Transform builtin inport.
5259 static ir_node *gen_inport(ir_node *node)
5261 ir_type *tp = get_Builtin_type(node);
5262 ir_type *rstp = get_method_res_type(tp, 0);
5263 ir_mode *mode = get_type_mode(rstp);
5264 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
5265 ir_node *block = be_transform_node(get_nodes_block(node));
5266 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5267 dbg_info *dbgi = get_irn_dbg_info(node);
5269 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5270 set_ia32_ls_mode(res, mode);
5272 /* check for missing Result Proj */
5277 * Transform a builtin inner trampoline
5279 static ir_node *gen_inner_trampoline(ir_node *node)
5281 ir_node *ptr = get_Builtin_param(node, 0);
5282 ir_node *callee = get_Builtin_param(node, 1);
5283 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5284 ir_node *mem = get_Builtin_mem(node);
5285 ir_node *block = get_nodes_block(node);
5286 ir_node *new_block = be_transform_node(block);
5290 ir_node *trampoline;
5292 dbg_info *dbgi = get_irn_dbg_info(node);
5293 ia32_address_t addr;
5295 /* construct store address */
5296 memset(&addr, 0, sizeof(addr));
5297 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
5299 if (addr.base == NULL) {
5300 addr.base = noreg_GP;
5302 addr.base = be_transform_node(addr.base);
5305 if (addr.index == NULL) {
5306 addr.index = noreg_GP;
5308 addr.index = be_transform_node(addr.index);
5310 addr.mem = be_transform_node(mem);
5312 /* mov ecx, <env> */
5313 val = ia32_create_Immediate(NULL, 0, 0xB9);
5314 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5315 addr.index, addr.mem, val);
5316 set_irn_pinned(store, get_irn_pinned(node));
5317 set_ia32_op_type(store, ia32_AddrModeD);
5318 set_ia32_ls_mode(store, mode_Bu);
5319 set_address(store, &addr);
5323 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5324 addr.index, addr.mem, env);
5325 set_irn_pinned(store, get_irn_pinned(node));
5326 set_ia32_op_type(store, ia32_AddrModeD);
5327 set_ia32_ls_mode(store, mode_Iu);
5328 set_address(store, &addr);
5332 /* jmp rel <callee> */
5333 val = ia32_create_Immediate(NULL, 0, 0xE9);
5334 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5335 addr.index, addr.mem, val);
5336 set_irn_pinned(store, get_irn_pinned(node));
5337 set_ia32_op_type(store, ia32_AddrModeD);
5338 set_ia32_ls_mode(store, mode_Bu);
5339 set_address(store, &addr);
5343 trampoline = be_transform_node(ptr);
5345 /* the callee is typically an immediate */
5346 if (is_SymConst(callee)) {
5347 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5349 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP);
5350 add_ia32_am_offs_int(rel, -10);
5352 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5354 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5355 addr.index, addr.mem, rel);
5356 set_irn_pinned(store, get_irn_pinned(node));
5357 set_ia32_op_type(store, ia32_AddrModeD);
5358 set_ia32_ls_mode(store, mode_Iu);
5359 set_address(store, &addr);
5364 return new_r_Tuple(new_block, 2, in);
5368 * Transform Builtin node.
5370 static ir_node *gen_Builtin(ir_node *node)
5372 ir_builtin_kind kind = get_Builtin_kind(node);
5376 return gen_trap(node);
5377 case ir_bk_debugbreak:
5378 return gen_debugbreak(node);
5379 case ir_bk_return_address:
5380 return gen_return_address(node);
5381 case ir_bk_frame_address:
5382 return gen_frame_address(node);
5383 case ir_bk_prefetch:
5384 return gen_prefetch(node);
5386 return gen_ffs(node);
5388 return gen_clz(node);
5390 return gen_ctz(node);
5392 return gen_parity(node);
5393 case ir_bk_popcount:
5394 return gen_popcount(node);
5396 return gen_bswap(node);
5398 return gen_outport(node);
5400 return gen_inport(node);
5401 case ir_bk_inner_trampoline:
5402 return gen_inner_trampoline(node);
5404 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5408 * Transform Proj(Builtin) node.
5410 static ir_node *gen_Proj_Builtin(ir_node *proj)
5412 ir_node *node = get_Proj_pred(proj);
5413 ir_node *new_node = be_transform_node(node);
5414 ir_builtin_kind kind = get_Builtin_kind(node);
5417 case ir_bk_return_address:
5418 case ir_bk_frame_address:
5423 case ir_bk_popcount:
5425 assert(get_Proj_proj(proj) == pn_Builtin_1_result);
5428 case ir_bk_debugbreak:
5429 case ir_bk_prefetch:
5431 assert(get_Proj_proj(proj) == pn_Builtin_M);
5434 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5435 return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5437 assert(get_Proj_proj(proj) == pn_Builtin_M);
5438 return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
5440 case ir_bk_inner_trampoline:
5441 if (get_Proj_proj(proj) == pn_Builtin_1_result) {
5442 return get_Tuple_pred(new_node, 1);
5444 assert(get_Proj_proj(proj) == pn_Builtin_M);
5445 return get_Tuple_pred(new_node, 0);
5448 panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
5451 static ir_node *gen_be_IncSP(ir_node *node)
5453 ir_node *res = be_duplicate_node(node);
5454 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
5460 * Transform the Projs from a be_Call.
5462 static ir_node *gen_Proj_be_Call(ir_node *node)
5464 ir_node *call = get_Proj_pred(node);
5465 ir_node *new_call = be_transform_node(call);
5466 dbg_info *dbgi = get_irn_dbg_info(node);
5467 long proj = get_Proj_proj(node);
5468 ir_mode *mode = get_irn_mode(node);
5471 if (proj == pn_be_Call_M_regular) {
5472 return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
5474 /* transform call modes */
5475 if (mode_is_data(mode)) {
5476 const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
5480 /* Map from be_Call to ia32_Call proj number */
5481 if (proj == pn_be_Call_sp) {
5482 proj = pn_ia32_Call_stack;
5483 } else if (proj == pn_be_Call_M_regular) {
5484 proj = pn_ia32_Call_M;
5486 arch_register_req_t const *const req = arch_get_register_req_out(node);
5487 int const n_outs = arch_irn_get_n_outs(new_call);
5490 assert(proj >= pn_be_Call_first_res);
5491 assert(req->type & arch_register_req_type_limited);
5493 for (i = 0; i < n_outs; ++i) {
5494 arch_register_req_t const *const new_req
5495 = arch_get_out_register_req(new_call, i);
5497 if (!(new_req->type & arch_register_req_type_limited) ||
5498 new_req->cls != req->cls ||
5499 *new_req->limited != *req->limited)
5508 res = new_rd_Proj(dbgi, new_call, mode, proj);
5510 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5512 case pn_ia32_Call_stack:
5513 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
5516 case pn_ia32_Call_fpcw:
5517 arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
5525 * Transform the Projs from a Cmp.
5527 static ir_node *gen_Proj_Cmp(ir_node *node)
5529 /* this probably means not all mode_b nodes were lowered... */
5530 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
5534 static ir_node *gen_Proj_ASM(ir_node *node)
5536 ir_mode *mode = get_irn_mode(node);
5537 ir_node *pred = get_Proj_pred(node);
5538 ir_node *new_pred = be_transform_node(pred);
5539 long pos = get_Proj_proj(node);
5541 if (mode == mode_M) {
5542 pos = arch_irn_get_n_outs(new_pred)-1;
5543 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5545 } else if (mode_is_float(mode)) {
5548 panic("unexpected proj mode at ASM");
5551 return new_r_Proj(new_pred, mode, pos);
5555 * Transform and potentially renumber Proj nodes.
5557 static ir_node *gen_Proj(ir_node *node)
5559 ir_node *pred = get_Proj_pred(node);
5562 switch (get_irn_opcode(pred)) {
5564 proj = get_Proj_proj(node);
5565 if (proj == pn_Store_M) {
5566 return be_transform_node(pred);
5568 panic("No idea how to transform proj->Store");
5571 return gen_Proj_Load(node);
5573 return gen_Proj_ASM(node);
5575 return gen_Proj_Builtin(node);
5577 return gen_Proj_Div(node);
5579 return gen_Proj_Mod(node);
5581 return gen_Proj_CopyB(node);
5583 return gen_Proj_be_SubSP(node);
5585 return gen_Proj_be_AddSP(node);
5587 return gen_Proj_be_Call(node);
5589 return gen_Proj_Cmp(node);
5591 proj = get_Proj_proj(node);
5593 case pn_Start_X_initial_exec: {
5594 ir_node *block = get_nodes_block(pred);
5595 ir_node *new_block = be_transform_node(block);
5596 dbg_info *dbgi = get_irn_dbg_info(node);
5597 /* we exchange the ProjX with a jump */
5598 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5603 case pn_Start_P_tls:
5604 return ia32_gen_Proj_tls(node);
5609 if (is_ia32_l_FloattoLL(pred)) {
5610 return gen_Proj_l_FloattoLL(node);
5612 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5616 ir_mode *mode = get_irn_mode(node);
5617 if (ia32_mode_needs_gp_reg(mode)) {
5618 ir_node *new_pred = be_transform_node(pred);
5619 ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
5620 get_Proj_proj(node));
5621 new_proj->node_nr = node->node_nr;
5626 return be_duplicate_node(node);
5630 * Enters all transform functions into the generic pointer
5632 static void register_transformers(void)
5634 /* first clear the generic function pointer for all ops */
5635 be_start_transform_setup();
5637 be_set_transform_function(op_Add, gen_Add);
5638 be_set_transform_function(op_And, gen_And);
5639 be_set_transform_function(op_ASM, ia32_gen_ASM);
5640 be_set_transform_function(op_be_AddSP, gen_be_AddSP);
5641 be_set_transform_function(op_be_Call, gen_be_Call);
5642 be_set_transform_function(op_be_Copy, gen_be_Copy);
5643 be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
5644 be_set_transform_function(op_be_IncSP, gen_be_IncSP);
5645 be_set_transform_function(op_be_Return, gen_be_Return);
5646 be_set_transform_function(op_be_SubSP, gen_be_SubSP);
5647 be_set_transform_function(op_Builtin, gen_Builtin);
5648 be_set_transform_function(op_Cmp, gen_Cmp);
5649 be_set_transform_function(op_Cond, gen_Cond);
5650 be_set_transform_function(op_Const, gen_Const);
5651 be_set_transform_function(op_Conv, gen_Conv);
5652 be_set_transform_function(op_CopyB, ia32_gen_CopyB);
5653 be_set_transform_function(op_Div, gen_Div);
5654 be_set_transform_function(op_Eor, gen_Eor);
5655 be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc);
5656 be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add);
5657 be_set_transform_function(op_ia32_Leave, be_duplicate_node);
5658 be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL);
5659 be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
5660 be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
5661 be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
5662 be_set_transform_function(op_ia32_l_SarDep, gen_ia32_l_SarDep);
5663 be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
5664 be_set_transform_function(op_ia32_l_ShlDep, gen_ia32_l_ShlDep);
5665 be_set_transform_function(op_ia32_l_ShlD, gen_ia32_l_ShlD);
5666 be_set_transform_function(op_ia32_l_ShrDep, gen_ia32_l_ShrDep);
5667 be_set_transform_function(op_ia32_l_ShrD, gen_ia32_l_ShrD);
5668 be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
5669 be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
5670 be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
5671 be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
5672 be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
5673 be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
5674 be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
5675 be_set_transform_function(op_ia32_Push, be_duplicate_node);
5676 be_set_transform_function(op_IJmp, gen_IJmp);
5677 be_set_transform_function(op_Jmp, gen_Jmp);
5678 be_set_transform_function(op_Load, gen_Load);
5679 be_set_transform_function(op_Minus, gen_Minus);
5680 be_set_transform_function(op_Mod, gen_Mod);
5681 be_set_transform_function(op_Mul, gen_Mul);
5682 be_set_transform_function(op_Mulh, gen_Mulh);
5683 be_set_transform_function(op_Mux, gen_Mux);
5684 be_set_transform_function(op_Not, gen_Not);
5685 be_set_transform_function(op_Or, gen_Or);
5686 be_set_transform_function(op_Phi, gen_Phi);
5687 be_set_transform_function(op_Proj, gen_Proj);
5688 be_set_transform_function(op_Rotl, gen_Rotl);
5689 be_set_transform_function(op_Shl, gen_Shl);
5690 be_set_transform_function(op_Shr, gen_Shr);
5691 be_set_transform_function(op_Shrs, gen_Shrs);
5692 be_set_transform_function(op_Store, gen_Store);
5693 be_set_transform_function(op_Sub, gen_Sub);
5694 be_set_transform_function(op_SymConst, gen_SymConst);
5695 be_set_transform_function(op_Unknown, ia32_gen_Unknown);
5699 * Pre-transform all unknown and noreg nodes.
5701 static void ia32_pretransform_node(void)
5703 ir_graph *irg = current_ir_graph;
5704 ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
5706 irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
5707 irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
5708 irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
5710 nomem = get_irg_no_mem(irg);
5711 noreg_GP = ia32_new_NoReg_gp(irg);
5717 * Post-process all calls if we are in SSE mode.
5718 * The ABI requires that the results are in st0, copy them
5719 * to a xmm register.
5721 static void postprocess_fp_call_results(void)
5725 for (i = 0, n = ARR_LEN(call_list); i < n; ++i) {
5726 ir_node *call = call_list[i];
5727 ir_type *mtp = call_types[i];
5730 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5731 ir_type *res_tp = get_method_res_type(mtp, j);
5732 ir_node *res, *new_res;
5733 const ir_edge_t *edge, *next;
5736 if (! is_atomic_type(res_tp)) {
5737 /* no floating point return */
5740 mode = get_type_mode(res_tp);
5741 if (! mode_is_float(mode)) {
5742 /* no floating point return */
5746 res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
5749 /* now patch the users */
5750 foreach_out_edge_safe(res, edge, next) {
5751 ir_node *succ = get_edge_src_irn(edge);
5754 if (be_is_Keep(succ))
5757 if (is_ia32_xStore(succ)) {
5758 /* an xStore can be patched into an vfst */
5759 dbg_info *db = get_irn_dbg_info(succ);
5760 ir_node *block = get_nodes_block(succ);
5761 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5762 ir_node *index = get_irn_n(succ, n_ia32_xStore_index);
5763 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5764 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5765 ir_mode *mode = get_ia32_ls_mode(succ);
5767 ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode);
5768 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5769 if (is_ia32_use_frame(succ))
5770 set_ia32_use_frame(st);
5771 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5772 set_irn_pinned(st, get_irn_pinned(succ));
5773 set_ia32_op_type(st, ia32_AddrModeD);
5777 if (new_res == NULL) {
5778 dbg_info *db = get_irn_dbg_info(call);
5779 ir_node *block = get_nodes_block(call);
5780 ir_node *frame = get_irg_frame(current_ir_graph);
5781 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5782 ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
5783 ir_node *vfst, *xld, *new_mem;
5785 /* store st(0) on stack */
5786 vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode);
5787 set_ia32_op_type(vfst, ia32_AddrModeD);
5788 set_ia32_use_frame(vfst);
5790 /* load into SSE register */
5791 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode);
5792 set_ia32_op_type(xld, ia32_AddrModeS);
5793 set_ia32_use_frame(xld);
5795 new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res);
5796 new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
5798 if (old_mem != NULL) {
5799 edges_reroute(old_mem, new_mem, current_ir_graph);
5803 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5810 /* do the transformation */
5811 void ia32_transform_graph(ir_graph *irg)
5815 register_transformers();
5816 initial_fpcw = NULL;
5817 ia32_no_pic_adjust = 0;
5819 be_timer_push(T_HEIGHTS);
5820 ia32_heights = heights_new(irg);
5821 be_timer_pop(T_HEIGHTS);
5822 ia32_calculate_non_address_mode_nodes(irg);
5824 /* the transform phase is not safe for CSE (yet) because several nodes get
5825 * attributes set after their creation */
5826 cse_last = get_opt_cse();
5829 call_list = NEW_ARR_F(ir_node *, 0);
5830 call_types = NEW_ARR_F(ir_type *, 0);
5831 be_transform_graph(irg, ia32_pretransform_node);
5833 if (ia32_cg_config.use_sse2)
5834 postprocess_fp_call_results();
5835 DEL_ARR_F(call_types);
5836 DEL_ARR_F(call_list);
5838 set_opt_cse(cse_last);
5840 ia32_free_non_address_mode_nodes();
5841 heights_free(ia32_heights);
5842 ia32_heights = NULL;
5845 void ia32_init_transform(void)
5847 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");