2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define TP_SFP_SIGN "ia32_sfp_sign"
77 #define TP_DFP_SIGN "ia32_dfp_sign"
78 #define TP_SFP_ABS "ia32_sfp_abs"
79 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
82 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
83 #define ENT_SFP_ABS "IA32_SFP_ABS"
84 #define ENT_DFP_ABS "IA32_DFP_ABS"
86 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
87 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
89 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
91 /** hold the current code generator during transformation */
92 static ia32_code_gen_t *env_cg = NULL;
93 static ir_node *initial_fpcw = NULL;
94 static heights_t *heights = NULL;
96 extern ir_op *get_op_Mulh(void);
98 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem);
102 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
109 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
112 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
114 ir_node *op2, ir_node *mem, ir_node *fpcw);
116 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *op);
119 /****************************************************************************************************
121 * | | | | / _| | | (_)
122 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
123 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
124 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
125 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
127 ****************************************************************************************************/
129 static ir_node *try_create_Immediate(ir_node *node,
130 char immediate_constraint_type);
132 static ir_node *create_immediate_or_transform(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
136 dbg_info *dbgi, ir_node *new_block,
140 * Return true if a mode can be stored in the GP register set
142 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
143 if(mode == mode_fpcw)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an entity that is initialized with a tarval
186 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
188 tarval *tv = get_Const_tarval(cnst);
189 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
194 ir_mode *mode = get_irn_mode(cnst);
195 ir_type *tp = get_Const_type(cnst);
196 if (tp == firm_unknown_type)
197 tp = get_prim_type(cg->isa->types, mode);
199 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
201 set_entity_ld_ident(res, get_entity_ident(res));
202 set_entity_visibility(res, visibility_local);
203 set_entity_variability(res, variability_constant);
204 set_entity_allocation(res, allocation_static);
206 /* we create a new entity here: It's initialization must resist on the
208 rem = current_ir_graph;
209 current_ir_graph = get_const_code_irg();
210 set_atomic_ent_value(res, new_Const_type(tv, tp));
211 current_ir_graph = rem;
213 pmap_insert(cg->isa->tv_ent, tv, res);
221 static int is_Const_0(ir_node *node) {
225 return classify_Const(node) == CNST_NULL;
228 static int is_Const_1(ir_node *node) {
232 return classify_Const(node) == CNST_ONE;
235 static int is_Const_Minus_1(ir_node *node) {
240 tv = get_Const_tarval(node);
243 return classify_tarval(tv) == CNST_ONE;
247 * Transforms a Const.
249 static ir_node *gen_Const(ir_node *node) {
250 ir_graph *irg = current_ir_graph;
251 ir_node *old_block = get_nodes_block(node);
252 ir_node *block = be_transform_node(old_block);
253 dbg_info *dbgi = get_irn_dbg_info(node);
254 ir_mode *mode = get_irn_mode(node);
256 if (mode_is_float(mode)) {
258 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
259 ir_node *nomem = new_NoMem();
263 if (! USE_SSE2(env_cg)) {
264 cnst_classify_t clss = classify_Const(node);
266 if (clss == CNST_NULL) {
267 load = new_rd_ia32_vfldz(dbgi, irg, block);
269 } else if (clss == CNST_ONE) {
270 load = new_rd_ia32_vfld1(dbgi, irg, block);
273 floatent = get_entity_for_tv(env_cg, node);
275 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
276 set_ia32_op_type(load, ia32_AddrModeS);
277 set_ia32_am_sc(load, floatent);
278 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
279 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
281 set_ia32_ls_mode(load, mode);
283 floatent = get_entity_for_tv(env_cg, node);
285 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
287 set_ia32_op_type(load, ia32_AddrModeS);
288 set_ia32_am_sc(load, floatent);
289 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
291 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
294 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
296 /* Const Nodes before the initial IncSP are a bad idea, because
297 * they could be spilled and we have no SP ready at that point yet.
298 * So add a dependency to the initial frame pointer calculation to
299 * avoid that situation.
301 if (get_irg_start_block(irg) == block) {
302 add_irn_dep(load, get_irg_frame(irg));
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
309 tarval *tv = get_Const_tarval(node);
312 tv = tarval_convert_to(tv, mode_Iu);
314 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
316 panic("couldn't convert constant tarval (%+F)", node);
318 val = get_tarval_long(tv);
320 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
321 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
324 if (get_irg_start_block(irg) == block) {
325 add_irn_dep(cnst, get_irg_frame(irg));
333 * Transforms a SymConst.
335 static ir_node *gen_SymConst(ir_node *node) {
336 ir_graph *irg = current_ir_graph;
337 ir_node *old_block = get_nodes_block(node);
338 ir_node *block = be_transform_node(old_block);
339 dbg_info *dbgi = get_irn_dbg_info(node);
340 ir_mode *mode = get_irn_mode(node);
343 if (mode_is_float(mode)) {
344 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
345 ir_node *nomem = new_NoMem();
347 if (USE_SSE2(env_cg))
348 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
351 set_ia32_am_sc(cnst, get_SymConst_entity(node));
353 if(get_SymConst_kind(node) != symconst_addr_ent) {
354 panic("backend only support symconst_addr_ent (at %+F)", node);
356 ir_entity *entity = get_SymConst_entity(node);
357 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
360 /* Const Nodes before the initial IncSP are a bad idea, because
361 * they could be spilled and we have no SP ready at that point yet
363 if (get_irg_start_block(irg) == block) {
364 add_irn_dep(cnst, get_irg_frame(irg));
367 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
372 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
373 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
374 static const struct {
376 const char *ent_name;
377 const char *cnst_str;
378 } names [ia32_known_const_max] = {
379 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
380 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
381 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
382 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
384 static ir_entity *ent_cache[ia32_known_const_max];
386 const char *tp_name, *ent_name, *cnst_str;
394 ent_name = names[kct].ent_name;
395 if (! ent_cache[kct]) {
396 tp_name = names[kct].tp_name;
397 cnst_str = names[kct].cnst_str;
399 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
401 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
402 tp = new_type_primitive(new_id_from_str(tp_name), mode);
403 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
405 set_entity_ld_ident(ent, get_entity_ident(ent));
406 set_entity_visibility(ent, visibility_local);
407 set_entity_variability(ent, variability_constant);
408 set_entity_allocation(ent, allocation_static);
410 /* we create a new entity here: It's initialization must resist on the
412 rem = current_ir_graph;
413 current_ir_graph = get_const_code_irg();
414 cnst = new_Const(mode, tv);
415 current_ir_graph = rem;
417 set_atomic_ent_value(ent, cnst);
419 /* cache the entry */
420 ent_cache[kct] = ent;
423 return ent_cache[kct];
428 * Prints the old node name on cg obst and returns a pointer to it.
430 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
431 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
433 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
434 obstack_1grow(isa->name_obst, 0);
435 return obstack_finish(isa->name_obst);
439 static int use_source_address_mode(ir_node *block, ir_node *node,
448 load = get_Proj_pred(node);
449 pn = get_Proj_proj(node);
450 if(!is_Load(load) || pn != pn_Load_res)
452 if(get_nodes_block(load) != block)
454 /* we only use address mode if we're the only user of the load */
455 if(get_irn_n_edges(node) > 1)
458 mode = get_irn_mode(node);
459 if(!mode_needs_gp_reg(mode))
461 if(get_mode_size_bits(mode) != 32)
464 /* don't do AM if other node inputs depend on the load (via mem-proj) */
465 if(other != NULL && get_nodes_block(other) == block
466 && heights_reachable_in_block(heights, other, load))
472 typedef struct ia32_address_mode_t ia32_address_mode_t;
473 struct ia32_address_mode_t {
477 ia32_op_type_t op_type;
484 static void build_address(ia32_address_mode_t *am, ir_node *node)
486 ia32_address_t *addr = &am->addr;
487 ir_node *load = get_Proj_pred(node);
488 ir_node *ptr = get_Load_ptr(load);
489 ir_node *mem = get_Load_mem(load);
490 ir_node *new_mem = be_transform_node(mem);
494 am->ls_mode = get_Load_mode(load);
495 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
497 /* construct load address */
498 ia32_create_address_mode(addr, ptr, 0);
503 base = ia32_new_NoReg_gp(env_cg);
505 base = be_transform_node(base);
509 index = ia32_new_NoReg_gp(env_cg);
511 index = be_transform_node(index);
519 static void set_address(ir_node *node, ia32_address_t *addr)
521 set_ia32_am_scale(node, addr->scale);
522 set_ia32_am_sc(node, addr->symconst_ent);
523 set_ia32_am_offs_int(node, addr->offset);
524 if(addr->symconst_sign)
525 set_ia32_am_sc_sign(node);
527 set_ia32_use_frame(node);
528 set_ia32_frame_ent(node, addr->frame_entity);
531 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
533 set_address(node, &am->addr);
535 set_ia32_op_type(node, am->op_type);
536 set_ia32_ls_mode(node, am->ls_mode);
538 set_ia32_commutative(node);
541 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
542 ir_node *op1, ir_node *op2, int commutative,
543 int use_am_and_immediates)
545 ia32_address_t *addr = &am->addr;
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
550 memset(am, 0, sizeof(am[0]));
552 new_op2 = try_create_Immediate(op2, 0);
553 if(new_op2 == NULL && use_source_address_mode(block, op2, op1)) {
554 build_address(am, op2);
555 new_op1 = be_transform_node(op1);
557 am->op_type = ia32_AddrModeS;
558 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
559 use_source_address_mode(block, op1, op2)) {
560 build_address(am, op1);
561 if(new_op2 != NULL) {
564 new_op1 = be_transform_node(op2);
568 am->op_type = ia32_AddrModeS;
570 new_op1 = be_transform_node(op1);
572 new_op2 = be_transform_node(op2);
573 am->op_type = ia32_Normal;
575 if(addr->base == NULL)
576 addr->base = noreg_gp;
577 if(addr->index == NULL)
578 addr->index = noreg_gp;
579 if(addr->mem == NULL)
580 addr->mem = new_NoMem();
582 am->new_op1 = new_op1;
583 am->new_op2 = new_op2;
584 am->commutative = commutative;
587 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
589 ir_graph *irg = current_ir_graph;
593 if(am->mem_proj == NULL)
596 /* we have to create a mode_T so the old MemProj can attach to us */
597 mode = get_irn_mode(node);
598 load = get_Proj_pred(am->mem_proj);
600 mark_irn_visited(load);
601 be_set_transformed_node(load, node);
604 set_irn_mode(node, mode_T);
605 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
612 * Construct a standard binary operation, set AM and immediate if required.
614 * @param op1 The first operand
615 * @param op2 The second operand
616 * @param func The node constructor function
617 * @return The constructed ia32 node.
619 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
620 construct_binop_func *func, int commutative)
622 ir_node *src_block = get_nodes_block(node);
623 ir_node *block = be_transform_node(src_block);
624 ir_graph *irg = current_ir_graph;
625 dbg_info *dbgi = get_irn_dbg_info(node);
627 ia32_address_mode_t am;
628 ia32_address_t *addr = &am.addr;
630 match_arguments(&am, src_block, op1, op2, commutative, 0);
632 new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
633 am.new_op2, addr->mem);
634 set_am_attributes(new_node, &am);
635 /* we can't use source address mode anymore when using immediates */
636 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
637 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
638 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
640 new_node = fix_mem_proj(new_node, &am);
646 * Construct a standard binary operation, set AM and immediate if required.
648 * @param op1 The first operand
649 * @param op2 The second operand
650 * @param func The node constructor function
651 * @return The constructed ia32 node.
653 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
654 construct_binop_func *func)
656 ir_node *block = be_transform_node(get_nodes_block(node));
657 ir_node *new_op1 = be_transform_node(op1);
658 ir_node *new_op2 = be_transform_node(op2);
659 ir_node *new_node = NULL;
660 dbg_info *dbgi = get_irn_dbg_info(node);
661 ir_graph *irg = current_ir_graph;
662 ir_mode *mode = get_irn_mode(node);
663 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
664 ir_node *nomem = new_NoMem();
666 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
668 if (is_op_commutative(get_irn_op(node))) {
669 set_ia32_commutative(new_node);
671 set_ia32_ls_mode(new_node, mode);
673 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
678 static ir_node *get_fpcw(void)
681 if(initial_fpcw != NULL)
684 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
685 &ia32_fp_cw_regs[REG_FPCW]);
686 initial_fpcw = be_transform_node(fpcw);
692 * Construct a standard binary operation, set AM and immediate if required.
694 * @param op1 The first operand
695 * @param op2 The second operand
696 * @param func The node constructor function
697 * @return The constructed ia32 node.
699 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
700 construct_binop_float_func *func)
702 ir_node *block = be_transform_node(get_nodes_block(node));
703 ir_node *new_op1 = be_transform_node(op1);
704 ir_node *new_op2 = be_transform_node(op2);
705 ir_node *new_node = NULL;
706 dbg_info *dbgi = get_irn_dbg_info(node);
707 ir_graph *irg = current_ir_graph;
708 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
709 ir_node *nomem = new_NoMem();
711 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
713 if (is_op_commutative(get_irn_op(node))) {
714 set_ia32_commutative(new_node);
717 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
723 * Construct a shift/rotate binary operation, sets AM and immediate if required.
725 * @param op1 The first operand
726 * @param op2 The second operand
727 * @param func The node constructor function
728 * @return The constructed ia32 node.
730 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
731 construct_shift_func *func)
733 dbg_info *dbgi = get_irn_dbg_info(node);
734 ir_graph *irg = current_ir_graph;
735 ir_node *block = get_nodes_block(node);
736 ir_node *new_block = be_transform_node(block);
737 ir_node *new_op1 = be_transform_node(op1);
738 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
741 assert(! mode_is_float(get_irn_mode(node))
742 && "Shift/Rotate with float not supported");
744 res = func(dbgi, irg, new_block, new_op1, new_op2);
745 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
747 /* lowered shift instruction may have a dependency operand, handle it here */
748 if (get_irn_arity(node) == 3) {
749 /* we have a dependency */
750 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
751 add_irn_dep(res, new_dep);
759 * Construct a standard unary operation, set AM and immediate if required.
761 * @param op The operand
762 * @param func The node constructor function
763 * @return The constructed ia32 node.
765 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
767 ir_node *block = be_transform_node(get_nodes_block(node));
768 ir_node *new_op = be_transform_node(op);
769 ir_node *new_node = NULL;
770 ir_graph *irg = current_ir_graph;
771 dbg_info *dbgi = get_irn_dbg_info(node);
773 new_node = func(dbgi, irg, block, new_op);
775 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
780 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
781 ia32_address_t *addr)
783 ir_graph *irg = current_ir_graph;
784 ir_node *base = addr->base;
785 ir_node *index = addr->index;
789 base = ia32_new_NoReg_gp(env_cg);
791 base = be_transform_node(base);
795 index = ia32_new_NoReg_gp(env_cg);
797 index = be_transform_node(index);
800 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
801 set_address(res, addr);
806 static int am_has_immediates(const ia32_address_t *addr)
808 return addr->offset != 0 || addr->symconst_ent != NULL
809 || addr->frame_entity || addr->use_frame;
813 * Creates an ia32 Add.
815 * @return the created ia32 Add node
817 static ir_node *gen_Add(ir_node *node) {
818 ir_node *block = be_transform_node(get_nodes_block(node));
819 ir_node *op1 = get_Add_left(node);
820 ir_node *op2 = get_Add_right(node);
823 ir_graph *irg = current_ir_graph;
824 dbg_info *dbgi = get_irn_dbg_info(node);
825 ir_mode *mode = get_irn_mode(node);
826 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
827 ir_node *src_block = get_nodes_block(node);
828 ir_node *add_immediate_op;
830 ia32_address_mode_t am;
832 if (mode_is_float(mode)) {
833 if (USE_SSE2(env_cg))
834 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
836 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
841 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
842 * 1. Add with immediate -> Lea
843 * 2. Add with possible source address mode -> Add
844 * 3. Otherwise -> Lea
846 memset(&addr, 0, sizeof(addr));
847 ia32_create_address_mode(&addr, node, 1);
848 add_immediate_op = NULL;
850 if(addr.base == NULL && addr.index == NULL) {
851 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
852 addr.symconst_sign, addr.offset);
853 add_irn_dep(new_op, get_irg_frame(irg));
854 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
857 /* add with immediate? */
858 if(addr.index == NULL) {
859 add_immediate_op = addr.base;
860 } else if(addr.base == NULL && addr.scale == 0) {
861 add_immediate_op = addr.index;
864 if(add_immediate_op != NULL) {
865 if(!am_has_immediates(&addr)) {
867 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
870 return be_transform_node(add_immediate_op);
872 if(env_cg->isa->opt & IA32_OPT_INCDEC
873 && addr.symconst_ent == NULL) {
874 if(addr.offset == 1) {
875 ir_node *new_op = be_transform_node(add_immediate_op);
876 new_op = new_rd_ia32_Inc(dbgi, irg, block, new_op);
877 SET_IA32_ORIG_NODE(new_op,
878 ia32_get_old_node_name(env_cg, node));
880 } else if(addr.offset == -1) {
881 ir_node *new_op = be_transform_node(add_immediate_op);
882 new_op = new_rd_ia32_Dec(dbgi, irg, block, new_op);
883 SET_IA32_ORIG_NODE(new_op,
884 ia32_get_old_node_name(env_cg, node));
889 new_op = create_lea_from_address(dbgi, block, &addr);
890 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
894 /* test if we can use source address mode */
895 memset(&am, 0, sizeof(am));
897 if(use_source_address_mode(src_block, op2, op1)) {
898 build_address(&am, op2);
899 new_op1 = be_transform_node(op1);
900 } else if(use_source_address_mode(src_block, op1, op2)) {
901 build_address(&am, op1);
902 new_op1 = be_transform_node(op2);
904 /* construct an Add with source address mode */
905 if(new_op1 != NULL) {
906 ia32_address_t *am_addr = &am.addr;
907 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
908 am_addr->index, new_op1, noreg, am_addr->mem);
909 set_address(new_op, am_addr);
910 set_ia32_op_type(new_op, ia32_AddrModeS);
911 set_ia32_ls_mode(new_op, am.ls_mode);
912 set_ia32_commutative(new_op);
913 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
915 new_op = fix_mem_proj(new_op, &am);
920 /* otherwise construct a lea */
921 new_op = create_lea_from_address(dbgi, block, &addr);
922 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
927 * Creates an ia32 Mul.
929 * @return the created ia32 Mul node
931 static ir_node *gen_Mul(ir_node *node) {
932 ir_node *op1 = get_Mul_left(node);
933 ir_node *op2 = get_Mul_right(node);
934 ir_mode *mode = get_irn_mode(node);
936 if (mode_is_float(mode)) {
937 if (USE_SSE2(env_cg))
938 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
940 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
944 for the lower 32bit of the result it doesn't matter whether we use
945 signed or unsigned multiplication so we use IMul as it has fewer
948 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
952 * Creates an ia32 Mulh.
953 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
954 * this result while Mul returns the lower 32 bit.
956 * @return the created ia32 Mulh node
958 static ir_node *gen_Mulh(ir_node *node) {
959 ir_node *block = be_transform_node(get_nodes_block(node));
960 ir_node *op1 = get_irn_n(node, 0);
961 ir_node *new_op1 = be_transform_node(op1);
962 ir_node *op2 = get_irn_n(node, 1);
963 ir_node *new_op2 = be_transform_node(op2);
964 ir_graph *irg = current_ir_graph;
965 dbg_info *dbgi = get_irn_dbg_info(node);
966 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
967 ir_mode *mode = get_irn_mode(node);
968 ir_node *proj_EDX, *res;
970 assert(!mode_is_float(mode) && "Mulh with float not supported");
971 if (mode_is_signed(mode)) {
972 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
973 new_op2, new_NoMem());
975 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
979 set_ia32_commutative(res);
981 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
989 * Creates an ia32 And.
991 * @return The created ia32 And node
993 static ir_node *gen_And(ir_node *node) {
994 ir_node *op1 = get_And_left(node);
995 ir_node *op2 = get_And_right(node);
996 assert(! mode_is_float(get_irn_mode(node)));
998 /* is it a zero extension? */
1000 tarval *tv = get_Const_tarval(op2);
1001 long v = get_tarval_long(tv);
1003 if (v == 0xFF || v == 0xFFFF) {
1004 dbg_info *dbgi = get_irn_dbg_info(node);
1005 ir_node *block = be_transform_node(get_nodes_block(node));
1006 ir_node *new_op = be_transform_node(op1);
1013 assert(v == 0xFFFF);
1016 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
1017 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1023 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1029 * Creates an ia32 Or.
1031 * @return The created ia32 Or node
1033 static ir_node *gen_Or(ir_node *node) {
1034 ir_node *op1 = get_Or_left(node);
1035 ir_node *op2 = get_Or_right(node);
1037 assert (! mode_is_float(get_irn_mode(node)));
1038 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1044 * Creates an ia32 Eor.
1046 * @return The created ia32 Eor node
1048 static ir_node *gen_Eor(ir_node *node) {
1049 ir_node *op1 = get_Eor_left(node);
1050 ir_node *op2 = get_Eor_right(node);
1052 assert(! mode_is_float(get_irn_mode(node)));
1053 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1058 * Creates an ia32 Sub.
1060 * @return The created ia32 Sub node
1062 static ir_node *gen_Sub(ir_node *node) {
1063 ir_node *op1 = get_Sub_left(node);
1064 ir_node *op2 = get_Sub_right(node);
1065 ir_mode *mode = get_irn_mode(node);
1067 if (mode_is_float(mode)) {
1068 if (USE_SSE2(env_cg))
1069 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1071 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1074 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1080 * Generates an ia32 DivMod with additional infrastructure for the
1081 * register allocator if needed.
1083 * @param dividend -no comment- :)
1084 * @param divisor -no comment- :)
1085 * @param dm_flav flavour_Div/Mod/DivMod
1086 * @return The created ia32 DivMod node
1088 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1089 ir_node *divisor, ia32_op_flavour_t dm_flav)
1091 ir_node *block = be_transform_node(get_nodes_block(node));
1092 ir_node *new_dividend = be_transform_node(dividend);
1093 ir_node *new_divisor = be_transform_node(divisor);
1094 ir_graph *irg = current_ir_graph;
1095 dbg_info *dbgi = get_irn_dbg_info(node);
1096 ir_mode *mode = get_irn_mode(node);
1097 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1098 ir_node *res, *proj_div, *proj_mod;
1099 ir_node *sign_extension;
1100 ir_node *mem, *new_mem;
1103 proj_div = proj_mod = NULL;
1107 mem = get_Div_mem(node);
1108 mode = get_Div_resmode(node);
1109 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1110 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1113 mem = get_Mod_mem(node);
1114 mode = get_Mod_resmode(node);
1115 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1116 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1118 case flavour_DivMod:
1119 mem = get_DivMod_mem(node);
1120 mode = get_DivMod_resmode(node);
1121 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1122 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1123 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1126 panic("invalid divmod flavour!");
1128 new_mem = be_transform_node(mem);
1130 if (mode_is_signed(mode)) {
1131 /* in signed mode, we need to sign extend the dividend */
1132 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1133 add_irn_dep(produceval, get_irg_frame(irg));
1134 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1137 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1138 add_irn_dep(sign_extension, get_irg_frame(irg));
1141 if (mode_is_signed(mode)) {
1142 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1143 sign_extension, new_divisor, new_mem, dm_flav);
1145 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1146 sign_extension, new_divisor, new_mem, dm_flav);
1149 set_ia32_exc_label(res, has_exc);
1150 set_irn_pinned(res, get_irn_pinned(node));
1152 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1159 * Wrapper for generate_DivMod. Sets flavour_Mod.
1162 static ir_node *gen_Mod(ir_node *node) {
1163 return generate_DivMod(node, get_Mod_left(node),
1164 get_Mod_right(node), flavour_Mod);
1168 * Wrapper for generate_DivMod. Sets flavour_Div.
1171 static ir_node *gen_Div(ir_node *node) {
1172 return generate_DivMod(node, get_Div_left(node),
1173 get_Div_right(node), flavour_Div);
1177 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1179 static ir_node *gen_DivMod(ir_node *node) {
1180 return generate_DivMod(node, get_DivMod_left(node),
1181 get_DivMod_right(node), flavour_DivMod);
1187 * Creates an ia32 floating Div.
1189 * @return The created ia32 xDiv node
1191 static ir_node *gen_Quot(ir_node *node) {
1192 ir_node *block = be_transform_node(get_nodes_block(node));
1193 ir_node *op1 = get_Quot_left(node);
1194 ir_node *new_op1 = be_transform_node(op1);
1195 ir_node *op2 = get_Quot_right(node);
1196 ir_node *new_op2 = be_transform_node(op2);
1197 ir_graph *irg = current_ir_graph;
1198 dbg_info *dbgi = get_irn_dbg_info(node);
1199 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1200 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1203 if (USE_SSE2(env_cg)) {
1204 ir_mode *mode = get_irn_mode(op1);
1205 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
1207 set_ia32_ls_mode(new_op, mode);
1209 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1210 new_op2, nomem, get_fpcw());
1212 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1218 * Creates an ia32 Shl.
1220 * @return The created ia32 Shl node
1222 static ir_node *gen_Shl(ir_node *node) {
1223 ir_node *right = get_Shl_right(node);
1225 /* test wether we can build a lea */
1226 if(is_Const(right)) {
1227 tarval *tv = get_Const_tarval(right);
1228 if(tarval_is_long(tv)) {
1229 long val = get_tarval_long(tv);
1230 if(val >= 0 && val <= 3) {
1231 ir_graph *irg = current_ir_graph;
1232 dbg_info *dbgi = get_irn_dbg_info(node);
1233 ir_node *block = be_transform_node(get_nodes_block(node));
1234 ir_node *base = ia32_new_NoReg_gp(env_cg);
1235 ir_node *index = be_transform_node(get_Shl_left(node));
1238 = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1239 set_ia32_am_scale(res, val);
1240 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1246 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1253 * Creates an ia32 Shr.
1255 * @return The created ia32 Shr node
1257 static ir_node *gen_Shr(ir_node *node) {
1258 return gen_shift_binop(node, get_Shr_left(node),
1259 get_Shr_right(node), new_rd_ia32_Shr);
1265 * Creates an ia32 Sar.
1267 * @return The created ia32 Shrs node
1269 static ir_node *gen_Shrs(ir_node *node) {
1270 ir_node *left = get_Shrs_left(node);
1271 ir_node *right = get_Shrs_right(node);
1272 ir_mode *mode = get_irn_mode(node);
1273 if(is_Const(right) && mode == mode_Is) {
1274 tarval *tv = get_Const_tarval(right);
1275 long val = get_tarval_long(tv);
1277 /* this is a sign extension */
1278 ir_graph *irg = current_ir_graph;
1279 dbg_info *dbgi = get_irn_dbg_info(node);
1280 ir_node *block = be_transform_node(get_nodes_block(node));
1282 ir_node *new_op = be_transform_node(op);
1283 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1284 add_irn_dep(pval, get_irg_frame(irg));
1286 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1290 /* 8 or 16 bit sign extension? */
1291 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1292 ir_node *shl_left = get_Shl_left(left);
1293 ir_node *shl_right = get_Shl_right(left);
1294 if(is_Const(shl_right)) {
1295 tarval *tv1 = get_Const_tarval(right);
1296 tarval *tv2 = get_Const_tarval(shl_right);
1297 if(tv1 == tv2 && tarval_is_long(tv1)) {
1298 long val = get_tarval_long(tv1);
1299 if(val == 16 || val == 24) {
1300 dbg_info *dbgi = get_irn_dbg_info(node);
1301 ir_node *block = be_transform_node(get_nodes_block(node));
1302 ir_node *new_op = be_transform_node(shl_left);
1312 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1314 SET_IA32_ORIG_NODE(res,
1315 ia32_get_old_node_name(env_cg, node));
1323 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1329 * Creates an ia32 RotL.
1331 * @param op1 The first operator
1332 * @param op2 The second operator
1333 * @return The created ia32 RotL node
1335 static ir_node *gen_RotL(ir_node *node,
1336 ir_node *op1, ir_node *op2) {
1337 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1343 * Creates an ia32 RotR.
1344 * NOTE: There is no RotR with immediate because this would always be a RotL
1345 * "imm-mode_size_bits" which can be pre-calculated.
1347 * @param op1 The first operator
1348 * @param op2 The second operator
1349 * @return The created ia32 RotR node
1351 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1353 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1359 * Creates an ia32 RotR or RotL (depending on the found pattern).
1361 * @return The created ia32 RotL or RotR node
1363 static ir_node *gen_Rot(ir_node *node) {
1364 ir_node *rotate = NULL;
1365 ir_node *op1 = get_Rot_left(node);
1366 ir_node *op2 = get_Rot_right(node);
1368 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1369 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1370 that means we can create a RotR instead of an Add and a RotL */
1372 if (get_irn_op(op2) == op_Add) {
1374 ir_node *left = get_Add_left(add);
1375 ir_node *right = get_Add_right(add);
1376 if (is_Const(right)) {
1377 tarval *tv = get_Const_tarval(right);
1378 ir_mode *mode = get_irn_mode(node);
1379 long bits = get_mode_size_bits(mode);
1381 if (get_irn_op(left) == op_Minus &&
1382 tarval_is_long(tv) &&
1383 get_tarval_long(tv) == bits)
1385 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1386 rotate = gen_RotR(node, op1, get_Minus_op(left));
1391 if (rotate == NULL) {
1392 rotate = gen_RotL(node, op1, op2);
1401 * Transforms a Minus node.
1403 * @param op The Minus operand
1404 * @return The created ia32 Minus node
1406 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1407 ir_node *block = be_transform_node(get_nodes_block(node));
1408 ir_graph *irg = current_ir_graph;
1409 dbg_info *dbgi = get_irn_dbg_info(node);
1410 ir_mode *mode = get_irn_mode(node);
1415 if (mode_is_float(mode)) {
1416 ir_node *new_op = be_transform_node(op);
1417 if (USE_SSE2(env_cg)) {
1418 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1419 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1420 ir_node *nomem = new_rd_NoMem(irg);
1422 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1424 size = get_mode_size_bits(mode);
1425 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1427 set_ia32_am_sc(res, ent);
1428 set_ia32_op_type(res, ia32_AddrModeS);
1429 set_ia32_ls_mode(res, mode);
1431 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1434 res = gen_unop(node, op, new_rd_ia32_Neg);
1437 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1443 * Transforms a Minus node.
1445 * @return The created ia32 Minus node
1447 static ir_node *gen_Minus(ir_node *node) {
1448 return gen_Minus_ex(node, get_Minus_op(node));
1451 static ir_node *create_Immediate_from_int(int val)
1453 ir_graph *irg = current_ir_graph;
1454 ir_node *start_block = get_irg_start_block(irg);
1455 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1456 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1461 static ir_node *gen_bin_Not(ir_node *node)
1463 ir_graph *irg = current_ir_graph;
1464 dbg_info *dbgi = get_irn_dbg_info(node);
1465 ir_node *block = be_transform_node(get_nodes_block(node));
1466 ir_node *op = get_Not_op(node);
1467 ir_node *new_op = be_transform_node(op);
1468 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1469 ir_node *nomem = new_NoMem();
1470 ir_node *one = create_Immediate_from_int(1);
1472 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1476 * Transforms a Not node.
1478 * @return The created ia32 Not node
1480 static ir_node *gen_Not(ir_node *node) {
1481 ir_node *op = get_Not_op(node);
1482 ir_mode *mode = get_irn_mode(node);
1484 if(mode == mode_b) {
1485 return gen_bin_Not(node);
1488 assert (! mode_is_float(get_irn_mode(node)));
1489 return gen_unop(node, op, new_rd_ia32_Not);
1495 * Transforms an Abs node.
1497 * @return The created ia32 Abs node
1499 static ir_node *gen_Abs(ir_node *node) {
1500 ir_node *block = be_transform_node(get_nodes_block(node));
1501 ir_node *op = get_Abs_op(node);
1502 ir_node *new_op = be_transform_node(op);
1503 ir_graph *irg = current_ir_graph;
1504 dbg_info *dbgi = get_irn_dbg_info(node);
1505 ir_mode *mode = get_irn_mode(node);
1506 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1507 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1508 ir_node *nomem = new_NoMem();
1513 if (mode_is_float(mode)) {
1514 if (USE_SSE2(env_cg)) {
1515 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1517 size = get_mode_size_bits(mode);
1518 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1520 set_ia32_am_sc(res, ent);
1522 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1524 set_ia32_op_type(res, ia32_AddrModeS);
1525 set_ia32_ls_mode(res, mode);
1528 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1529 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1533 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1534 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1537 add_irn_dep(pval, get_irg_frame(irg));
1538 SET_IA32_ORIG_NODE(sign_extension,
1539 ia32_get_old_node_name(env_cg, node));
1541 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1542 sign_extension, nomem);
1543 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1545 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1546 sign_extension, nomem);
1547 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1554 * Transforms a Load.
1556 * @return the created ia32 Load node
1558 static ir_node *gen_Load(ir_node *node) {
1559 ir_node *old_block = get_nodes_block(node);
1560 ir_node *block = be_transform_node(old_block);
1561 ir_node *ptr = get_Load_ptr(node);
1562 ir_node *mem = get_Load_mem(node);
1563 ir_node *new_mem = be_transform_node(mem);
1566 ir_graph *irg = current_ir_graph;
1567 dbg_info *dbgi = get_irn_dbg_info(node);
1568 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1569 ir_mode *mode = get_Load_mode(node);
1572 ia32_address_t addr;
1574 /* construct load address */
1575 memset(&addr, 0, sizeof(addr));
1576 ia32_create_address_mode(&addr, ptr, 0);
1583 base = be_transform_node(base);
1589 index = be_transform_node(index);
1592 if (mode_is_float(mode)) {
1593 if (USE_SSE2(env_cg)) {
1594 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1596 res_mode = mode_xmm;
1598 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1600 res_mode = mode_vfp;
1606 /* create a conv node with address mode for smaller modes */
1607 if(get_mode_size_bits(mode) < 32) {
1608 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
1611 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1616 set_irn_pinned(new_op, get_irn_pinned(node));
1617 set_ia32_op_type(new_op, ia32_AddrModeS);
1618 set_ia32_ls_mode(new_op, mode);
1619 set_address(new_op, &addr);
1621 /* make sure we are scheduled behind the initial IncSP/Barrier
1622 * to avoid spills being placed before it
1624 if (block == get_irg_start_block(irg)) {
1625 add_irn_dep(new_op, get_irg_frame(irg));
1628 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1629 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1634 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1635 ir_node *ptr, ir_mode *mode, ir_node *other)
1642 /* we only use address mode if we're the only user of the load */
1643 if(get_irn_n_edges(node) > 1)
1646 load = get_Proj_pred(node);
1649 if(get_nodes_block(load) != block)
1652 /* Store should be attached to the load */
1653 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1655 /* store should have the same pointer as the load */
1656 if(get_Load_ptr(load) != ptr)
1659 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1660 if(other != NULL && get_nodes_block(other) == block
1661 && heights_reachable_in_block(heights, other, load))
1664 assert(get_Load_mode(load) == mode);
1669 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1670 ir_node *mem, ir_node *ptr, ir_mode *mode,
1671 construct_binop_dest_func *func, int commutative)
1673 ir_node *src_block = get_nodes_block(node);
1675 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1676 ir_graph *irg = current_ir_graph;
1680 ia32_address_mode_t am;
1681 ia32_address_t *addr = &am.addr;
1682 memset(&am, 0, sizeof(am));
1684 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1685 build_address(&am, op1);
1686 new_op = create_immediate_or_transform(op2, 0);
1687 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1688 build_address(&am, op2);
1689 new_op = create_immediate_or_transform(op1, 0);
1694 if(addr->base == NULL)
1695 addr->base = noreg_gp;
1696 if(addr->index == NULL)
1697 addr->index = noreg_gp;
1698 if(addr->mem == NULL)
1699 addr->mem = new_NoMem();
1701 dbgi = get_irn_dbg_info(node);
1702 block = be_transform_node(src_block);
1703 new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
1705 set_address(new_node, addr);
1706 set_ia32_op_type(new_node, ia32_AddrModeD);
1707 set_ia32_ls_mode(new_node, mode);
1708 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1713 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1714 ir_node *ptr, ir_mode *mode,
1715 construct_unop_dest_func *func)
1717 ir_node *src_block = get_nodes_block(node);
1719 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1720 ir_graph *irg = current_ir_graph;
1723 ia32_address_mode_t am;
1724 ia32_address_t *addr = &am.addr;
1725 memset(&am, 0, sizeof(am));
1727 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1730 build_address(&am, op);
1732 if(addr->base == NULL)
1733 addr->base = noreg_gp;
1734 if(addr->index == NULL)
1735 addr->index = noreg_gp;
1736 if(addr->mem == NULL)
1737 addr->mem = new_NoMem();
1739 dbgi = get_irn_dbg_info(node);
1740 block = be_transform_node(src_block);
1741 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1742 set_address(new_node, addr);
1743 set_ia32_op_type(new_node, ia32_AddrModeD);
1744 set_ia32_ls_mode(new_node, mode);
1745 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1750 static ir_node *try_create_dest_am(ir_node *node) {
1751 ir_node *val = get_Store_value(node);
1752 ir_node *mem = get_Store_mem(node);
1753 ir_node *ptr = get_Store_ptr(node);
1754 ir_mode *mode = get_irn_mode(val);
1759 /* handle only GP modes for now... */
1760 if(!mode_needs_gp_reg(mode))
1762 if(get_mode_size_bits(mode) != 32)
1765 /* store must be the only user of the val node */
1766 if(get_irn_n_edges(val) > 1)
1769 switch(get_irn_opcode(val)) {
1771 op1 = get_Add_left(val);
1772 op2 = get_Add_right(val);
1773 if(is_Const_1(op2)) {
1774 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1775 new_rd_ia32_IncMem);
1777 } else if(is_Const_Minus_1(op2)) {
1778 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1779 new_rd_ia32_DecMem);
1782 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1783 new_rd_ia32_AddMem, 1);
1786 op1 = get_Sub_left(val);
1787 op2 = get_Sub_right(val);
1788 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1789 new_rd_ia32_SubMem, 0);
1792 op1 = get_And_left(val);
1793 op2 = get_And_right(val);
1794 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1795 new_rd_ia32_AndMem, 1);
1798 op1 = get_Or_left(val);
1799 op2 = get_Or_right(val);
1800 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1801 new_rd_ia32_OrMem, 1);
1804 op1 = get_Eor_left(val);
1805 op2 = get_Eor_right(val);
1806 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1807 new_rd_ia32_XorMem, 1);
1810 op1 = get_Shl_left(val);
1811 op2 = get_Shl_right(val);
1812 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1813 new_rd_ia32_ShlMem, 0);
1816 op1 = get_Shr_left(val);
1817 op2 = get_Shr_right(val);
1818 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1819 new_rd_ia32_ShrMem, 0);
1822 op1 = get_Shrs_left(val);
1823 op2 = get_Shrs_right(val);
1824 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1825 new_rd_ia32_SarMem, 0);
1828 op1 = get_Rot_left(val);
1829 op2 = get_Rot_right(val);
1830 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1831 new_rd_ia32_RolMem, 0);
1833 /* TODO: match ROR patterns... */
1835 op1 = get_Minus_op(val);
1836 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1839 /* TODO this would be ^ 1 with DestAM */
1842 op1 = get_Not_op(val);
1843 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1853 * Transforms a Store.
1855 * @return the created ia32 Store node
1857 static ir_node *gen_Store(ir_node *node) {
1858 ir_node *block = be_transform_node(get_nodes_block(node));
1859 ir_node *ptr = get_Store_ptr(node);
1862 ir_node *val = get_Store_value(node);
1864 ir_node *mem = get_Store_mem(node);
1865 ir_node *new_mem = be_transform_node(mem);
1866 ir_graph *irg = current_ir_graph;
1867 dbg_info *dbgi = get_irn_dbg_info(node);
1868 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1869 ir_mode *mode = get_irn_mode(val);
1871 ia32_address_t addr;
1873 /* check for destination address mode */
1874 new_op = try_create_dest_am(node);
1878 /* construct load address */
1879 memset(&addr, 0, sizeof(addr));
1880 ia32_create_address_mode(&addr, ptr, 0);
1887 base = be_transform_node(base);
1893 index = be_transform_node(index);
1896 if (mode_is_float(mode)) {
1897 new_val = be_transform_node(val);
1898 if (USE_SSE2(env_cg)) {
1899 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
1902 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
1906 new_val = create_immediate_or_transform(val, 0);
1910 if (get_mode_size_bits(mode) == 8) {
1911 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
1914 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
1919 set_irn_pinned(new_op, get_irn_pinned(node));
1920 set_ia32_op_type(new_op, ia32_AddrModeD);
1921 set_ia32_ls_mode(new_op, mode);
1923 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1924 set_address(new_op, &addr);
1925 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1930 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1931 ir_node *cmp_left, ir_node *cmp_right)
1937 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1938 ia32_address_mode_t am;
1939 ia32_address_t *addr = &am.addr;
1941 if(cmp_right != NULL && !is_Const_0(cmp_right))
1944 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1945 mode = get_irn_mode(cmp_left);
1946 arg_left = get_And_left(cmp_left);
1947 arg_right = get_And_right(cmp_left);
1949 mode = get_irn_mode(cmp_left);
1950 arg_left = cmp_left;
1951 arg_right = cmp_left;
1957 assert(get_mode_size_bits(mode) <= 32);
1958 match_arguments(&am, block, arg_left, arg_right, 1, 1);
1960 pnc = get_inversed_pnc(pnc);
1962 if(get_mode_size_bits(mode) == 8) {
1963 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1964 addr->index, am.new_op1, am.new_op2,
1967 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1968 addr->index, am.new_op1, am.new_op2,
1971 set_am_attributes(res, &am);
1972 set_ia32_ls_mode(res, mode);
1974 res = fix_mem_proj(res, &am);
1979 static ir_node *create_Switch(ir_node *node)
1981 ir_graph *irg = current_ir_graph;
1982 dbg_info *dbgi = get_irn_dbg_info(node);
1983 ir_node *block = be_transform_node(get_nodes_block(node));
1984 ir_node *sel = get_Cond_selector(node);
1985 ir_node *new_sel = be_transform_node(sel);
1987 int switch_min = INT_MAX;
1988 const ir_edge_t *edge;
1990 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1992 /* determine the smallest switch case value */
1993 foreach_out_edge(node, edge) {
1994 ir_node *proj = get_edge_src_irn(edge);
1995 int pn = get_Proj_proj(proj);
2000 if (switch_min != 0) {
2001 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2003 /* if smallest switch case is not 0 we need an additional sub */
2004 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2005 add_ia32_am_offs_int(new_sel, -switch_min);
2006 set_ia32_op_type(new_sel, ia32_AddrModeS);
2008 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2011 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2012 set_ia32_pncode(res, get_Cond_defaultProj(node));
2014 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2020 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2022 * @return The transformed node.
2024 static ir_node *gen_Cond(ir_node *node) {
2025 ir_node *src_block = get_nodes_block(node);
2026 ir_node *block = be_transform_node(src_block);
2027 ir_graph *irg = current_ir_graph;
2028 dbg_info *dbgi = get_irn_dbg_info(node);
2029 ir_node *sel = get_Cond_selector(node);
2030 ir_mode *sel_mode = get_irn_mode(sel);
2031 ir_node *res = NULL;
2032 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2033 ir_node *nomem = new_NoMem();
2042 if (sel_mode != mode_b) {
2043 return create_Switch(node);
2046 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2047 /* it's some mode_b value but not a direct comparison -> create a
2049 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
2050 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2054 cmp = get_Proj_pred(sel);
2055 cmp_a = get_Cmp_left(cmp);
2056 cmp_b = get_Cmp_right(cmp);
2057 cmp_mode = get_irn_mode(cmp_a);
2058 pnc = get_Proj_proj(sel);
2059 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2060 pnc |= ia32_pn_Cmp_Unsigned;
2063 if(mode_needs_gp_reg(cmp_mode)) {
2064 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
2066 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2071 if (mode_is_float(cmp_mode)) {
2072 new_cmp_a = be_transform_node(cmp_a);
2073 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2074 if (USE_SSE2(env_cg)) {
2075 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
2077 set_ia32_commutative(res);
2078 set_ia32_ls_mode(res, cmp_mode);
2080 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2081 set_ia32_commutative(res);
2084 ia32_address_mode_t am;
2085 ia32_address_t *addr = &am.addr;
2086 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1);
2088 pnc = get_inversed_pnc(pnc);
2090 if(get_mode_size_bits(cmp_mode) == 8) {
2091 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
2092 addr->index, am.new_op1, am.new_op2,
2095 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2096 am.new_op1, am.new_op2, addr->mem, pnc);
2098 set_am_attributes(res, &am);
2099 assert(cmp_mode != NULL);
2100 set_ia32_ls_mode(res, cmp_mode);
2103 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2111 * Transforms a CopyB node.
2113 * @return The transformed node.
2115 static ir_node *gen_CopyB(ir_node *node) {
2116 ir_node *block = be_transform_node(get_nodes_block(node));
2117 ir_node *src = get_CopyB_src(node);
2118 ir_node *new_src = be_transform_node(src);
2119 ir_node *dst = get_CopyB_dst(node);
2120 ir_node *new_dst = be_transform_node(dst);
2121 ir_node *mem = get_CopyB_mem(node);
2122 ir_node *new_mem = be_transform_node(mem);
2123 ir_node *res = NULL;
2124 ir_graph *irg = current_ir_graph;
2125 dbg_info *dbgi = get_irn_dbg_info(node);
2126 int size = get_type_size_bytes(get_CopyB_type(node));
2129 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2130 /* then we need the size explicitly in ECX. */
2131 if (size >= 32 * 4) {
2132 rem = size & 0x3; /* size % 4 */
2135 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2136 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2138 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2139 /* we misuse the pncode field for the copyb size */
2140 set_ia32_pncode(res, rem);
2142 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2143 set_ia32_pncode(res, size);
2146 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2152 ir_node *gen_be_Copy(ir_node *node)
2154 ir_node *result = be_duplicate_node(node);
2155 ir_mode *mode = get_irn_mode(result);
2157 if (mode_needs_gp_reg(mode)) {
2158 set_irn_mode(result, mode_Iu);
2165 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2166 dbg_info *dbgi, ir_node *block)
2168 ir_graph *irg = current_ir_graph;
2169 ir_node *new_block = be_transform_node(block);
2170 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2171 ir_node *nomem = new_rd_NoMem(irg);
2176 ia32_address_mode_t am;
2177 ia32_address_t *addr = &am.addr;
2179 /* can we use a test instruction? */
2180 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2181 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2182 if(is_And(cmp_left) &&
2183 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2184 ir_node *and_left = get_And_left(cmp_left);
2185 ir_node *and_right = get_And_right(cmp_left);
2187 mode = get_irn_mode(and_left);
2188 arg_left = and_left;
2189 arg_right = and_right;
2191 mode = get_irn_mode(cmp_left);
2192 arg_left = cmp_left;
2193 arg_right = cmp_left;
2196 assert(get_mode_size_bits(mode) <= 32);
2198 match_arguments(&am, block, arg_left, arg_right, 1, 1);
2200 pnc = get_inversed_pnc(pnc);
2202 if(get_mode_size_bits(mode) == 8) {
2203 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2204 addr->index, am.new_op1, am.new_op2,
2207 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
2208 addr->index, am.new_op1, am.new_op2,
2211 set_am_attributes(res, &am);
2212 set_ia32_ls_mode(res, mode);
2214 res = fix_mem_proj(res, &am);
2216 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2222 mode = get_irn_mode(cmp_left);
2223 assert(get_mode_size_bits(mode) <= 32);
2225 match_arguments(&am, block, cmp_left, cmp_right, 1, 1);
2227 pnc = get_inversed_pnc(pnc);
2229 if(get_mode_size_bits(mode) == 8) {
2230 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
2231 addr->index, am.new_op1, am.new_op2,
2234 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2235 am.new_op1, am.new_op2, addr->mem, pnc);
2237 set_am_attributes(res, &am);
2238 set_ia32_ls_mode(res, mode);
2240 res = fix_mem_proj(res, &am);
2242 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
2248 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2249 ir_node *val_true, ir_node *val_false,
2250 dbg_info *dbgi, ir_node *block)
2252 ir_graph *irg = current_ir_graph;
2253 ir_node *new_block = be_transform_node(block);
2254 ir_node *new_val_true = be_transform_node(val_true);
2255 ir_node *new_val_false = be_transform_node(val_false);
2256 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2257 ir_node *nomem = new_NoMem();
2258 ir_node *new_cmp_left;
2259 ir_node *new_cmp_right;
2263 /* cmovs with unknowns are pointless... */
2264 if(is_Unknown(val_true)) {
2265 #ifdef DEBUG_libfirm
2266 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2268 return new_val_false;
2270 if(is_Unknown(val_false)) {
2271 #ifdef DEBUG_libfirm
2272 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2274 return new_val_true;
2277 /* can we use a test instruction? */
2278 if(is_Const_0(cmp_right)) {
2279 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2280 if(is_And(cmp_left) &&
2281 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2282 ir_node *and_left = get_And_left(cmp_left);
2283 ir_node *and_right = get_And_right(cmp_left);
2285 mode = get_irn_mode(and_left);
2286 new_cmp_left = be_transform_node(and_left);
2287 new_cmp_right = create_immediate_or_transform(and_right, 0);
2289 mode = get_irn_mode(cmp_left);
2290 new_cmp_left = be_transform_node(cmp_left);
2291 new_cmp_right = be_transform_node(cmp_left);
2294 assert(get_mode_size_bits(mode) <= 32);
2296 if(get_mode_size_bits(mode) == 8) {
2297 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
2298 noreg, noreg, new_cmp_left,
2299 new_cmp_right, nomem, new_val_true,
2300 new_val_false, pnc);
2302 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2303 noreg, new_cmp_left, new_cmp_right,
2304 nomem, new_val_true, new_val_false, pnc);
2306 set_ia32_ls_mode(res, mode);
2311 mode = get_irn_mode(cmp_left);
2312 new_cmp_left = be_transform_node(cmp_left);
2313 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2315 /* no support for 8,16 bit modes yet */
2316 assert(get_mode_size_bits(mode) <= 32);
2318 if(get_mode_size_bits(mode) == 8) {
2319 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
2320 new_cmp_left, new_cmp_right, nomem,
2321 new_val_true, new_val_false, pnc);
2323 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
2324 new_cmp_left, new_cmp_right, nomem,
2325 new_val_true, new_val_false, pnc);
2327 set_ia32_ls_mode(res, mode);
2334 * Transforms a Psi node into CMov.
2336 * @return The transformed node.
2338 static ir_node *gen_Psi(ir_node *node) {
2339 ir_node *psi_true = get_Psi_val(node, 0);
2340 ir_node *psi_default = get_Psi_default(node);
2341 ia32_code_gen_t *cg = env_cg;
2342 ir_node *cond = get_Psi_cond(node, 0);
2343 ir_node *block = get_nodes_block(node);
2344 dbg_info *dbgi = get_irn_dbg_info(node);
2351 assert(get_Psi_n_conds(node) == 1);
2352 assert(get_irn_mode(cond) == mode_b);
2353 assert(mode_needs_gp_reg(get_irn_mode(node)));
2355 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2356 /* a mode_b value, we have to compare it against 0 */
2358 cmp_right = new_Const_long(mode_Iu, 0);
2362 ir_node *cmp = get_Proj_pred(cond);
2364 cmp_left = get_Cmp_left(cmp);
2365 cmp_right = get_Cmp_right(cmp);
2366 cmp_mode = get_irn_mode(cmp_left);
2367 pnc = get_Proj_proj(cond);
2369 assert(!mode_is_float(cmp_mode));
2371 if (!mode_is_signed(cmp_mode)) {
2372 pnc |= ia32_pn_Cmp_Unsigned;
2376 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2377 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2378 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2379 pnc = get_negated_pnc(pnc, cmp_mode);
2380 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
2382 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2385 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2391 * Create a conversion from x87 state register to general purpose.
2393 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2394 ir_node *block = be_transform_node(get_nodes_block(node));
2395 ir_node *op = get_Conv_op(node);
2396 ir_node *new_op = be_transform_node(op);
2397 ia32_code_gen_t *cg = env_cg;
2398 ir_graph *irg = current_ir_graph;
2399 dbg_info *dbgi = get_irn_dbg_info(node);
2400 ir_node *noreg = ia32_new_NoReg_gp(cg);
2401 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2402 ir_mode *mode = get_irn_mode(node);
2403 ir_node *fist, *load;
2406 fist = new_rd_ia32_vfist(dbgi, irg, block,
2407 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2409 set_irn_pinned(fist, op_pin_state_floats);
2410 set_ia32_use_frame(fist);
2411 set_ia32_op_type(fist, ia32_AddrModeD);
2413 assert(get_mode_size_bits(mode) <= 32);
2414 /* exception we can only store signed 32 bit integers, so for unsigned
2415 we store a 64bit (signed) integer and load the lower bits */
2416 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2417 set_ia32_ls_mode(fist, mode_Ls);
2419 set_ia32_ls_mode(fist, mode_Is);
2421 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2424 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2426 set_irn_pinned(load, op_pin_state_floats);
2427 set_ia32_use_frame(load);
2428 set_ia32_op_type(load, ia32_AddrModeS);
2429 set_ia32_ls_mode(load, mode_Is);
2430 if(get_ia32_ls_mode(fist) == mode_Ls) {
2431 ia32_attr_t *attr = get_ia32_attr(load);
2432 attr->data.need_64bit_stackent = 1;
2434 ia32_attr_t *attr = get_ia32_attr(load);
2435 attr->data.need_32bit_stackent = 1;
2437 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2439 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2442 static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
2444 ir_node *block = get_nodes_block(node);
2445 ir_graph *irg = current_ir_graph;
2446 dbg_info *dbgi = get_irn_dbg_info(node);
2447 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2448 ir_node *nomem = new_NoMem();
2449 ir_node *frame = get_irg_frame(irg);
2450 ir_node *store, *load;
2453 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2455 set_ia32_use_frame(store);
2456 set_ia32_op_type(store, ia32_AddrModeD);
2457 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2459 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2461 set_ia32_use_frame(load);
2462 set_ia32_op_type(load, ia32_AddrModeS);
2463 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2465 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2470 * Create a conversion from general purpose to x87 register
2472 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2473 ir_node *block = be_transform_node(get_nodes_block(node));
2474 ir_node *op = get_Conv_op(node);
2475 ir_node *new_op = be_transform_node(op);
2476 ir_graph *irg = current_ir_graph;
2477 dbg_info *dbgi = get_irn_dbg_info(node);
2478 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2479 ir_node *nomem = new_NoMem();
2480 ir_mode *mode = get_irn_mode(op);
2481 ir_mode *store_mode;
2482 ir_node *fild, *store;
2486 /* first convert to 32 bit signed if necessary */
2487 src_bits = get_mode_size_bits(src_mode);
2488 if (src_bits == 8) {
2489 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
2491 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2493 } else if (src_bits < 32) {
2494 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
2495 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2499 assert(get_mode_size_bits(mode) == 32);
2502 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2504 set_ia32_use_frame(store);
2505 set_ia32_op_type(store, ia32_AddrModeD);
2506 set_ia32_ls_mode(store, mode_Iu);
2508 /* exception for 32bit unsigned, do a 64bit spill+load */
2509 if(!mode_is_signed(mode)) {
2512 ir_node *zero_const = create_Immediate_from_int(0);
2514 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
2517 set_ia32_use_frame(zero_store);
2518 set_ia32_op_type(zero_store, ia32_AddrModeD);
2519 add_ia32_am_offs_int(zero_store, 4);
2520 set_ia32_ls_mode(zero_store, mode_Iu);
2525 store = new_rd_Sync(dbgi, irg, block, 2, in);
2526 store_mode = mode_Ls;
2528 store_mode = mode_Is;
2532 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2534 set_ia32_use_frame(fild);
2535 set_ia32_op_type(fild, ia32_AddrModeS);
2536 set_ia32_ls_mode(fild, store_mode);
2538 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2544 * Crete a conversion from one integer mode into another one
2546 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2547 dbg_info *dbgi, ir_node *new_block,
2550 ir_graph *irg = current_ir_graph;
2551 int src_bits = get_mode_size_bits(src_mode);
2552 int tgt_bits = get_mode_size_bits(tgt_mode);
2553 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2554 ir_node *nomem = new_rd_NoMem(irg);
2556 ir_mode *smaller_mode;
2559 if (src_bits < tgt_bits) {
2560 smaller_mode = src_mode;
2561 smaller_bits = src_bits;
2563 smaller_mode = tgt_mode;
2564 smaller_bits = tgt_bits;
2567 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2568 if (smaller_bits == 8) {
2569 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2570 new_op, nomem, smaller_mode);
2572 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
2573 nomem, smaller_mode);
2580 * Transforms a Conv node.
2582 * @return The created ia32 Conv node
2584 static ir_node *gen_Conv(ir_node *node) {
2585 ir_node *block = be_transform_node(get_nodes_block(node));
2586 ir_node *op = get_Conv_op(node);
2587 ir_node *new_op = be_transform_node(op);
2588 ir_graph *irg = current_ir_graph;
2589 dbg_info *dbgi = get_irn_dbg_info(node);
2590 ir_mode *src_mode = get_irn_mode(op);
2591 ir_mode *tgt_mode = get_irn_mode(node);
2592 int src_bits = get_mode_size_bits(src_mode);
2593 int tgt_bits = get_mode_size_bits(tgt_mode);
2594 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2595 ir_node *nomem = new_rd_NoMem(irg);
2598 if (src_mode == mode_b) {
2599 assert(mode_is_int(tgt_mode));
2600 /* nothing to do, we already model bools as 0/1 ints */
2604 if (src_mode == tgt_mode) {
2605 if (get_Conv_strict(node)) {
2606 if (USE_SSE2(env_cg)) {
2607 /* when we are in SSE mode, we can kill all strict no-op conversion */
2611 /* this should be optimized already, but who knows... */
2612 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2613 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2618 if (mode_is_float(src_mode)) {
2619 /* we convert from float ... */
2620 if (mode_is_float(tgt_mode)) {
2621 if(src_mode == mode_E && tgt_mode == mode_D
2622 && !get_Conv_strict(node)) {
2623 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2628 if (USE_SSE2(env_cg)) {
2629 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2630 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2631 set_ia32_ls_mode(res, tgt_mode);
2633 if(get_Conv_strict(node)) {
2634 res = create_strict_conv(tgt_mode, new_op);
2635 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2638 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2643 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2644 if (USE_SSE2(env_cg)) {
2645 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2646 set_ia32_ls_mode(res, src_mode);
2648 return gen_x87_fp_to_gp(node);
2652 /* we convert from int ... */
2653 if (mode_is_float(tgt_mode)) {
2655 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2656 if (USE_SSE2(env_cg)) {
2657 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2658 set_ia32_ls_mode(res, tgt_mode);
2660 res = gen_x87_gp_to_fp(node, src_mode);
2661 if(get_Conv_strict(node)) {
2662 res = create_strict_conv(tgt_mode, res);
2663 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2664 ia32_get_old_node_name(env_cg, node));
2668 } else if(tgt_mode == mode_b) {
2669 /* mode_b lowering already took care that we only have 0/1 values */
2670 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2671 src_mode, tgt_mode));
2675 if (src_bits == tgt_bits) {
2676 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2677 src_mode, tgt_mode));
2681 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
2685 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2691 int check_immediate_constraint(long val, char immediate_constraint_type)
2693 switch (immediate_constraint_type) {
2697 return val >= 0 && val <= 32;
2699 return val >= 0 && val <= 63;
2701 return val >= -128 && val <= 127;
2703 return val == 0xff || val == 0xffff;
2705 return val >= 0 && val <= 3;
2707 return val >= 0 && val <= 255;
2709 return val >= 0 && val <= 127;
2713 panic("Invalid immediate constraint found");
2718 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2721 tarval *offset = NULL;
2722 int offset_sign = 0;
2724 ir_entity *symconst_ent = NULL;
2725 int symconst_sign = 0;
2727 ir_node *cnst = NULL;
2728 ir_node *symconst = NULL;
2734 mode = get_irn_mode(node);
2735 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2739 if(is_Minus(node)) {
2741 node = get_Minus_op(node);
2744 if(is_Const(node)) {
2747 offset_sign = minus;
2748 } else if(is_SymConst(node)) {
2751 symconst_sign = minus;
2752 } else if(is_Add(node)) {
2753 ir_node *left = get_Add_left(node);
2754 ir_node *right = get_Add_right(node);
2755 if(is_Const(left) && is_SymConst(right)) {
2758 symconst_sign = minus;
2759 offset_sign = minus;
2760 } else if(is_SymConst(left) && is_Const(right)) {
2763 symconst_sign = minus;
2764 offset_sign = minus;
2766 } else if(is_Sub(node)) {
2767 ir_node *left = get_Sub_left(node);
2768 ir_node *right = get_Sub_right(node);
2769 if(is_Const(left) && is_SymConst(right)) {
2772 symconst_sign = !minus;
2773 offset_sign = minus;
2774 } else if(is_SymConst(left) && is_Const(right)) {
2777 symconst_sign = minus;
2778 offset_sign = !minus;
2785 offset = get_Const_tarval(cnst);
2786 if(tarval_is_long(offset)) {
2787 val = get_tarval_long(offset);
2788 } else if(tarval_is_null(offset)) {
2791 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2796 if(!check_immediate_constraint(val, immediate_constraint_type))
2799 if(symconst != NULL) {
2800 if(immediate_constraint_type != 0) {
2801 /* we need full 32bits for symconsts */
2805 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2807 symconst_ent = get_SymConst_entity(symconst);
2809 if(cnst == NULL && symconst == NULL)
2812 if(offset_sign && offset != NULL) {
2813 offset = tarval_neg(offset);
2816 irg = current_ir_graph;
2817 dbgi = get_irn_dbg_info(node);
2818 block = get_irg_start_block(irg);
2819 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2820 symconst_sign, val);
2821 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2827 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2829 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2830 if (new_node == NULL) {
2831 new_node = be_transform_node(node);
2836 typedef struct constraint_t constraint_t;
2837 struct constraint_t {
2840 const arch_register_req_t **out_reqs;
2842 const arch_register_req_t *req;
2843 unsigned immediate_possible;
2844 char immediate_type;
2847 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2849 int immediate_possible = 0;
2850 char immediate_type = 0;
2851 unsigned limited = 0;
2852 const arch_register_class_t *cls = NULL;
2854 struct obstack *obst;
2855 arch_register_req_t *req;
2856 unsigned *limited_ptr;
2860 /* TODO: replace all the asserts with nice error messages */
2862 printf("Constraint: %s\n", c);
2872 assert(cls == NULL ||
2873 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2874 cls = &ia32_reg_classes[CLASS_ia32_gp];
2875 limited |= 1 << REG_EAX;
2878 assert(cls == NULL ||
2879 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2880 cls = &ia32_reg_classes[CLASS_ia32_gp];
2881 limited |= 1 << REG_EBX;
2884 assert(cls == NULL ||
2885 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2886 cls = &ia32_reg_classes[CLASS_ia32_gp];
2887 limited |= 1 << REG_ECX;
2890 assert(cls == NULL ||
2891 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2892 cls = &ia32_reg_classes[CLASS_ia32_gp];
2893 limited |= 1 << REG_EDX;
2896 assert(cls == NULL ||
2897 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2898 cls = &ia32_reg_classes[CLASS_ia32_gp];
2899 limited |= 1 << REG_EDI;
2902 assert(cls == NULL ||
2903 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2904 cls = &ia32_reg_classes[CLASS_ia32_gp];
2905 limited |= 1 << REG_ESI;
2908 case 'q': /* q means lower part of the regs only, this makes no
2909 * difference to Q for us (we only assigne whole registers) */
2910 assert(cls == NULL ||
2911 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2912 cls = &ia32_reg_classes[CLASS_ia32_gp];
2913 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2917 assert(cls == NULL ||
2918 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2919 cls = &ia32_reg_classes[CLASS_ia32_gp];
2920 limited |= 1 << REG_EAX | 1 << REG_EDX;
2923 assert(cls == NULL ||
2924 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2925 cls = &ia32_reg_classes[CLASS_ia32_gp];
2926 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2927 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2934 assert(cls == NULL);
2935 cls = &ia32_reg_classes[CLASS_ia32_gp];
2941 /* TODO: mark values so the x87 simulator knows about t and u */
2942 assert(cls == NULL);
2943 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2948 assert(cls == NULL);
2949 /* TODO: check that sse2 is supported */
2950 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2960 assert(!immediate_possible);
2961 immediate_possible = 1;
2962 immediate_type = *c;
2966 assert(!immediate_possible);
2967 immediate_possible = 1;
2971 assert(!immediate_possible && cls == NULL);
2972 immediate_possible = 1;
2973 cls = &ia32_reg_classes[CLASS_ia32_gp];
2986 assert(constraint->is_in && "can only specify same constraint "
2989 sscanf(c, "%d%n", &same_as, &p);
2996 case 'E': /* no float consts yet */
2997 case 'F': /* no float consts yet */
2998 case 's': /* makes no sense on x86 */
2999 case 'X': /* we can't support that in firm */
3003 case '<': /* no autodecrement on x86 */
3004 case '>': /* no autoincrement on x86 */
3005 case 'C': /* sse constant not supported yet */
3006 case 'G': /* 80387 constant not supported yet */
3007 case 'y': /* we don't support mmx registers yet */
3008 case 'Z': /* not available in 32 bit mode */
3009 case 'e': /* not available in 32 bit mode */
3010 assert(0 && "asm constraint not supported");
3013 assert(0 && "unknown asm constraint found");
3020 const arch_register_req_t *other_constr;
3022 assert(cls == NULL && "same as and register constraint not supported");
3023 assert(!immediate_possible && "same as and immediate constraint not "
3025 assert(same_as < constraint->n_outs && "wrong constraint number in "
3026 "same_as constraint");
3028 other_constr = constraint->out_reqs[same_as];
3030 req = obstack_alloc(obst, sizeof(req[0]));
3031 req->cls = other_constr->cls;
3032 req->type = arch_register_req_type_should_be_same;
3033 req->limited = NULL;
3034 req->other_same = pos;
3035 req->other_different = -1;
3037 /* switch constraints. This is because in firm we have same_as
3038 * constraints on the output constraints while in the gcc asm syntax
3039 * they are specified on the input constraints */
3040 constraint->req = other_constr;
3041 constraint->out_reqs[same_as] = req;
3042 constraint->immediate_possible = 0;
3046 if(immediate_possible && cls == NULL) {
3047 cls = &ia32_reg_classes[CLASS_ia32_gp];
3049 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3050 assert(cls != NULL);
3052 if(immediate_possible) {
3053 assert(constraint->is_in
3054 && "imeediates make no sense for output constraints");
3056 /* todo: check types (no float input on 'r' constrainted in and such... */
3058 irg = current_ir_graph;
3059 obst = get_irg_obstack(irg);
3062 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3063 limited_ptr = (unsigned*) (req+1);
3065 req = obstack_alloc(obst, sizeof(req[0]));
3067 memset(req, 0, sizeof(req[0]));
3070 req->type = arch_register_req_type_limited;
3071 *limited_ptr = limited;
3072 req->limited = limited_ptr;
3074 req->type = arch_register_req_type_normal;
3078 constraint->req = req;
3079 constraint->immediate_possible = immediate_possible;
3080 constraint->immediate_type = immediate_type;
3084 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3091 panic("Clobbers not supported yet");
3094 ir_node *gen_ASM(ir_node *node)
3097 ir_graph *irg = current_ir_graph;
3098 ir_node *block = be_transform_node(get_nodes_block(node));
3099 dbg_info *dbgi = get_irn_dbg_info(node);
3106 ia32_asm_attr_t *attr;
3107 const arch_register_req_t **out_reqs;
3108 const arch_register_req_t **in_reqs;
3109 struct obstack *obst;
3110 constraint_t parsed_constraint;
3112 /* transform inputs */
3113 arity = get_irn_arity(node);
3114 in = alloca(arity * sizeof(in[0]));
3115 memset(in, 0, arity * sizeof(in[0]));
3117 n_outs = get_ASM_n_output_constraints(node);
3118 n_clobbers = get_ASM_n_clobbers(node);
3119 out_arity = n_outs + n_clobbers;
3121 /* construct register constraints */
3122 obst = get_irg_obstack(irg);
3123 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3124 parsed_constraint.out_reqs = out_reqs;
3125 parsed_constraint.n_outs = n_outs;
3126 parsed_constraint.is_in = 0;
3127 for(i = 0; i < out_arity; ++i) {
3131 const ir_asm_constraint *constraint;
3132 constraint = & get_ASM_output_constraints(node) [i];
3133 c = get_id_str(constraint->constraint);
3134 parse_asm_constraint(i, &parsed_constraint, c);
3136 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3137 c = get_id_str(glob_id);
3138 parse_clobber(node, i, &parsed_constraint, c);
3140 out_reqs[i] = parsed_constraint.req;
3143 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3144 parsed_constraint.is_in = 1;
3145 for(i = 0; i < arity; ++i) {
3146 const ir_asm_constraint *constraint;
3150 constraint = & get_ASM_input_constraints(node) [i];
3151 constr_id = constraint->constraint;
3152 c = get_id_str(constr_id);
3153 parse_asm_constraint(i, &parsed_constraint, c);
3154 in_reqs[i] = parsed_constraint.req;
3156 if(parsed_constraint.immediate_possible) {
3157 ir_node *pred = get_irn_n(node, i);
3158 char imm_type = parsed_constraint.immediate_type;
3159 ir_node *immediate = try_create_Immediate(pred, imm_type);
3161 if(immediate != NULL) {
3167 /* transform inputs */
3168 for(i = 0; i < arity; ++i) {
3170 ir_node *transformed;
3175 pred = get_irn_n(node, i);
3176 transformed = be_transform_node(pred);
3177 in[i] = transformed;
3180 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3182 generic_attr = get_irn_generic_attr(res);
3183 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3184 attr->asm_text = get_ASM_text(node);
3185 set_ia32_out_req_all(res, out_reqs);
3186 set_ia32_in_req_all(res, in_reqs);
3188 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3193 /********************************************
3196 * | |__ ___ _ __ ___ __| | ___ ___
3197 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3198 * | |_) | __/ | | | (_) | (_| | __/\__ \
3199 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3201 ********************************************/
3204 * Transforms a FrameAddr into an ia32 Add.
3206 static ir_node *gen_be_FrameAddr(ir_node *node) {
3207 ir_node *block = be_transform_node(get_nodes_block(node));
3208 ir_node *op = be_get_FrameAddr_frame(node);
3209 ir_node *new_op = be_transform_node(op);
3210 ir_graph *irg = current_ir_graph;
3211 dbg_info *dbgi = get_irn_dbg_info(node);
3212 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3215 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3216 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3217 set_ia32_use_frame(res);
3219 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3225 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3227 static ir_node *gen_be_Return(ir_node *node) {
3228 ir_graph *irg = current_ir_graph;
3229 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3230 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3231 ir_entity *ent = get_irg_entity(irg);
3232 ir_type *tp = get_entity_type(ent);
3237 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3238 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3241 int pn_ret_val, pn_ret_mem, arity, i;
3243 assert(ret_val != NULL);
3244 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3245 return be_duplicate_node(node);
3248 res_type = get_method_res_type(tp, 0);
3250 if (! is_Primitive_type(res_type)) {
3251 return be_duplicate_node(node);
3254 mode = get_type_mode(res_type);
3255 if (! mode_is_float(mode)) {
3256 return be_duplicate_node(node);
3259 assert(get_method_n_ress(tp) == 1);
3261 pn_ret_val = get_Proj_proj(ret_val);
3262 pn_ret_mem = get_Proj_proj(ret_mem);
3264 /* get the Barrier */
3265 barrier = get_Proj_pred(ret_val);
3267 /* get result input of the Barrier */
3268 ret_val = get_irn_n(barrier, pn_ret_val);
3269 new_ret_val = be_transform_node(ret_val);
3271 /* get memory input of the Barrier */
3272 ret_mem = get_irn_n(barrier, pn_ret_mem);
3273 new_ret_mem = be_transform_node(ret_mem);
3275 frame = get_irg_frame(irg);
3277 dbgi = get_irn_dbg_info(barrier);
3278 block = be_transform_node(get_nodes_block(barrier));
3280 noreg = ia32_new_NoReg_gp(env_cg);
3282 /* store xmm0 onto stack */
3283 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3284 new_ret_val, new_ret_mem);
3285 set_ia32_ls_mode(sse_store, mode);
3286 set_ia32_op_type(sse_store, ia32_AddrModeD);
3287 set_ia32_use_frame(sse_store);
3289 /* load into x87 register */
3290 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3291 set_ia32_op_type(fld, ia32_AddrModeS);
3292 set_ia32_use_frame(fld);
3294 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3295 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3297 /* create a new barrier */
3298 arity = get_irn_arity(barrier);
3299 in = alloca(arity * sizeof(in[0]));
3300 for (i = 0; i < arity; ++i) {
3303 if (i == pn_ret_val) {
3305 } else if (i == pn_ret_mem) {
3308 ir_node *in = get_irn_n(barrier, i);
3309 new_in = be_transform_node(in);
3314 new_barrier = new_ir_node(dbgi, irg, block,
3315 get_irn_op(barrier), get_irn_mode(barrier),
3317 copy_node_attr(barrier, new_barrier);
3318 be_duplicate_deps(barrier, new_barrier);
3319 be_set_transformed_node(barrier, new_barrier);
3320 mark_irn_visited(barrier);
3322 /* transform normally */
3323 return be_duplicate_node(node);
3327 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3329 static ir_node *gen_be_AddSP(ir_node *node) {
3330 ir_node *block = be_transform_node(get_nodes_block(node));
3331 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3333 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3334 ir_node *new_sp = be_transform_node(sp);
3335 ir_graph *irg = current_ir_graph;
3336 dbg_info *dbgi = get_irn_dbg_info(node);
3337 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3338 ir_node *nomem = new_NoMem();
3341 new_sz = create_immediate_or_transform(sz, 0);
3343 /* ia32 stack grows in reverse direction, make a SubSP */
3344 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3346 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3352 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3354 static ir_node *gen_be_SubSP(ir_node *node) {
3355 ir_node *block = be_transform_node(get_nodes_block(node));
3356 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3358 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3359 ir_node *new_sp = be_transform_node(sp);
3360 ir_graph *irg = current_ir_graph;
3361 dbg_info *dbgi = get_irn_dbg_info(node);
3362 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3363 ir_node *nomem = new_NoMem();
3366 new_sz = create_immediate_or_transform(sz, 0);
3368 /* ia32 stack grows in reverse direction, make an AddSP */
3369 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3370 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3376 * This function just sets the register for the Unknown node
3377 * as this is not done during register allocation because Unknown
3378 * is an "ignore" node.
3380 static ir_node *gen_Unknown(ir_node *node) {
3381 ir_mode *mode = get_irn_mode(node);
3383 if (mode_is_float(mode)) {
3384 if (USE_SSE2(env_cg)) {
3385 return ia32_new_Unknown_xmm(env_cg);
3387 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3388 ir_graph *irg = current_ir_graph;
3389 dbg_info *dbgi = get_irn_dbg_info(node);
3390 ir_node *block = get_irg_start_block(irg);
3391 return new_rd_ia32_vfldz(dbgi, irg, block);
3393 } else if (mode_needs_gp_reg(mode)) {
3394 return ia32_new_Unknown_gp(env_cg);
3396 assert(0 && "unsupported Unknown-Mode");
3403 * Change some phi modes
3405 static ir_node *gen_Phi(ir_node *node) {
3406 ir_node *block = be_transform_node(get_nodes_block(node));
3407 ir_graph *irg = current_ir_graph;
3408 dbg_info *dbgi = get_irn_dbg_info(node);
3409 ir_mode *mode = get_irn_mode(node);
3412 if(mode_needs_gp_reg(mode)) {
3413 /* we shouldn't have any 64bit stuff around anymore */
3414 assert(get_mode_size_bits(mode) <= 32);
3415 /* all integer operations are on 32bit registers now */
3417 } else if(mode_is_float(mode)) {
3418 if (USE_SSE2(env_cg)) {
3425 /* phi nodes allow loops, so we use the old arguments for now
3426 * and fix this later */
3427 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3428 get_irn_in(node) + 1);
3429 copy_node_attr(node, phi);
3430 be_duplicate_deps(node, phi);
3432 be_set_transformed_node(node, phi);
3433 be_enqueue_preds(node);
3441 static ir_node *gen_IJmp(ir_node *node) {
3442 /* TODO: support AM */
3443 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3447 /**********************************************************************
3450 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3451 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3452 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3453 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3455 **********************************************************************/
3457 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3459 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3462 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3463 ir_node *val, ir_node *mem);
3466 * Transforms a lowered Load into a "real" one.
3468 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3470 ir_node *block = be_transform_node(get_nodes_block(node));
3471 ir_node *ptr = get_irn_n(node, 0);
3472 ir_node *new_ptr = be_transform_node(ptr);
3473 ir_node *mem = get_irn_n(node, 1);
3474 ir_node *new_mem = be_transform_node(mem);
3475 ir_graph *irg = current_ir_graph;
3476 dbg_info *dbgi = get_irn_dbg_info(node);
3477 ir_mode *mode = get_ia32_ls_mode(node);
3478 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3481 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3483 set_ia32_op_type(new_op, ia32_AddrModeS);
3484 set_ia32_am_offs_int(new_op, 0);
3485 set_ia32_am_scale(new_op, 1);
3486 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3487 if (is_ia32_am_sc_sign(node))
3488 set_ia32_am_sc_sign(new_op);
3489 set_ia32_ls_mode(new_op, mode);
3490 if (is_ia32_use_frame(node)) {
3491 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3492 set_ia32_use_frame(new_op);
3495 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3501 * Transforms a lowered Store into a "real" one.
3503 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3505 ir_node *block = be_transform_node(get_nodes_block(node));
3506 ir_node *ptr = get_irn_n(node, 0);
3507 ir_node *new_ptr = be_transform_node(ptr);
3508 ir_node *val = get_irn_n(node, 1);
3509 ir_node *new_val = be_transform_node(val);
3510 ir_node *mem = get_irn_n(node, 2);
3511 ir_node *new_mem = be_transform_node(mem);
3512 ir_graph *irg = current_ir_graph;
3513 dbg_info *dbgi = get_irn_dbg_info(node);
3514 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3515 ir_mode *mode = get_ia32_ls_mode(node);
3519 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3521 am_offs = get_ia32_am_offs_int(node);
3522 add_ia32_am_offs_int(new_op, am_offs);
3524 set_ia32_op_type(new_op, ia32_AddrModeD);
3525 set_ia32_ls_mode(new_op, mode);
3526 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3527 set_ia32_use_frame(new_op);
3529 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3536 * Transforms an ia32_l_XXX into a "real" XXX node
3538 * @param env The transformation environment
3539 * @return the created ia32 XXX node
3541 #define GEN_LOWERED_OP(op) \
3542 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3543 return gen_binop(node, get_binop_left(node), \
3544 get_binop_right(node), new_rd_ia32_##op,0); \
3547 #define GEN_LOWERED_x87_OP(op) \
3548 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3550 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3551 get_binop_right(node), new_rd_ia32_##op); \
3555 #define GEN_LOWERED_UNOP(op) \
3556 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3557 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3560 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3561 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3562 return gen_shift_binop(node, get_irn_n(node, 0), \
3563 get_irn_n(node, 1), new_rd_ia32_##op); \
3566 #define GEN_LOWERED_LOAD(op) \
3567 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3568 return gen_lowered_Load(node, new_rd_ia32_##op); \
3571 #define GEN_LOWERED_STORE(op) \
3572 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3573 return gen_lowered_Store(node, new_rd_ia32_##op); \
3581 GEN_LOWERED_x87_OP(vfprem)
3582 GEN_LOWERED_x87_OP(vfmul)
3583 GEN_LOWERED_x87_OP(vfsub)
3585 GEN_LOWERED_UNOP(Neg)
3587 GEN_LOWERED_LOAD(vfild)
3588 GEN_LOWERED_LOAD(Load)
3589 GEN_LOWERED_STORE(Store)
3592 * Transforms a l_vfist into a "real" vfist node.
3594 * @param env The transformation environment
3595 * @return the created ia32 vfist node
3597 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3598 ir_node *block = be_transform_node(get_nodes_block(node));
3599 ir_node *ptr = get_irn_n(node, 0);
3600 ir_node *new_ptr = be_transform_node(ptr);
3601 ir_node *val = get_irn_n(node, 1);
3602 ir_node *new_val = be_transform_node(val);
3603 ir_node *mem = get_irn_n(node, 2);
3604 ir_node *new_mem = be_transform_node(mem);
3605 ir_graph *irg = current_ir_graph;
3606 dbg_info *dbgi = get_irn_dbg_info(node);
3607 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3608 ir_mode *mode = get_ia32_ls_mode(node);
3609 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3613 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
3614 trunc_mode, new_mem);
3616 am_offs = get_ia32_am_offs_int(node);
3617 add_ia32_am_offs_int(new_op, am_offs);
3619 set_ia32_op_type(new_op, ia32_AddrModeD);
3620 set_ia32_ls_mode(new_op, mode);
3621 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3622 set_ia32_use_frame(new_op);
3624 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3630 * Transforms a l_vfdiv into a "real" vfdiv node.
3632 * @param env The transformation environment
3633 * @return the created ia32 vfdiv node
3635 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3636 ir_node *block = be_transform_node(get_nodes_block(node));
3637 ir_node *left = get_binop_left(node);
3638 ir_node *new_left = be_transform_node(left);
3639 ir_node *right = get_binop_right(node);
3640 ir_node *new_right = be_transform_node(right);
3641 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3642 ir_graph *irg = current_ir_graph;
3643 dbg_info *dbgi = get_irn_dbg_info(node);
3644 ir_node *fpcw = get_fpcw();
3647 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3648 new_right, new_NoMem(), fpcw);
3649 clear_ia32_commutative(vfdiv);
3651 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3657 * Transforms a l_MulS into a "real" MulS node.
3659 * @param env The transformation environment
3660 * @return the created ia32 Mul node
3662 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3663 ir_node *block = be_transform_node(get_nodes_block(node));
3664 ir_node *left = get_binop_left(node);
3665 ir_node *new_left = be_transform_node(left);
3666 ir_node *right = get_binop_right(node);
3667 ir_node *new_right = be_transform_node(right);
3668 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3669 ir_graph *irg = current_ir_graph;
3670 dbg_info *dbgi = get_irn_dbg_info(node);
3672 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3673 /* and then skip the result Proj, because all needed Projs are already there. */
3674 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3675 new_right, new_NoMem());
3676 clear_ia32_commutative(muls);
3678 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3684 * Transforms a l_IMulS into a "real" IMul1OPS node.
3686 * @param env The transformation environment
3687 * @return the created ia32 IMul1OP node
3689 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3690 ir_node *block = be_transform_node(get_nodes_block(node));
3691 ir_node *left = get_binop_left(node);
3692 ir_node *new_left = be_transform_node(left);
3693 ir_node *right = get_binop_right(node);
3694 ir_node *new_right = be_transform_node(right);
3695 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3696 ir_graph *irg = current_ir_graph;
3697 dbg_info *dbgi = get_irn_dbg_info(node);
3699 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3700 /* and then skip the result Proj, because all needed Projs are already there. */
3701 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
3702 new_right, new_NoMem());
3703 clear_ia32_commutative(muls);
3704 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3706 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3711 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3712 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3713 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3714 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3717 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3718 * op1 - target to be shifted
3719 * op2 - contains bits to be shifted into target
3721 * Only op3 can be an immediate.
3723 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3724 ir_node *op2, ir_node *count)
3726 ir_node *block = be_transform_node(get_nodes_block(node));
3727 ir_node *new_op = NULL;
3728 ir_graph *irg = current_ir_graph;
3729 dbg_info *dbgi = get_irn_dbg_info(node);
3730 ir_node *new_op1 = be_transform_node(op1);
3731 ir_node *new_op2 = create_immediate_or_transform(op2, 'I');
3732 ir_node *new_count = be_transform_node(count);
3734 /* TODO proper AM support */
3736 if (is_ia32_l_ShlD(node))
3737 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3739 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3741 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3746 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3747 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3748 get_irn_n(node, 1), get_irn_n(node, 2));
3751 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3752 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3753 get_irn_n(node, 1), get_irn_n(node, 2));
3757 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3759 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3760 ir_node *block = be_transform_node(get_nodes_block(node));
3761 ir_node *val = get_irn_n(node, 1);
3762 ir_node *new_val = be_transform_node(val);
3763 ia32_code_gen_t *cg = env_cg;
3764 ir_node *res = NULL;
3765 ir_graph *irg = current_ir_graph;
3767 ir_node *noreg, *new_ptr, *new_mem;
3774 mem = get_irn_n(node, 2);
3775 new_mem = be_transform_node(mem);
3776 ptr = get_irn_n(node, 0);
3777 new_ptr = be_transform_node(ptr);
3778 noreg = ia32_new_NoReg_gp(cg);
3779 dbgi = get_irn_dbg_info(node);
3781 /* Store x87 -> MEM */
3782 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3783 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3784 set_ia32_use_frame(res);
3785 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3786 set_ia32_op_type(res, ia32_AddrModeD);
3788 /* Load MEM -> SSE */
3789 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3790 get_ia32_ls_mode(node));
3791 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3792 set_ia32_use_frame(res);
3793 set_ia32_op_type(res, ia32_AddrModeS);
3794 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3800 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3802 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3803 ir_node *block = be_transform_node(get_nodes_block(node));
3804 ir_node *val = get_irn_n(node, 1);
3805 ir_node *new_val = be_transform_node(val);
3806 ia32_code_gen_t *cg = env_cg;
3807 ir_graph *irg = current_ir_graph;
3808 ir_node *res = NULL;
3809 ir_entity *fent = get_ia32_frame_ent(node);
3810 ir_mode *lsmode = get_ia32_ls_mode(node);
3812 ir_node *noreg, *new_ptr, *new_mem;
3816 if (! USE_SSE2(cg)) {
3817 /* SSE unit is not used -> skip this node. */
3821 ptr = get_irn_n(node, 0);
3822 new_ptr = be_transform_node(ptr);
3823 mem = get_irn_n(node, 2);
3824 new_mem = be_transform_node(mem);
3825 noreg = ia32_new_NoReg_gp(cg);
3826 dbgi = get_irn_dbg_info(node);
3828 /* Store SSE -> MEM */
3829 if (is_ia32_xLoad(skip_Proj(new_val))) {
3830 ir_node *ld = skip_Proj(new_val);
3832 /* we can vfld the value directly into the fpu */
3833 fent = get_ia32_frame_ent(ld);
3834 ptr = get_irn_n(ld, 0);
3835 offs = get_ia32_am_offs_int(ld);
3837 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3838 set_ia32_frame_ent(res, fent);
3839 set_ia32_use_frame(res);
3840 set_ia32_ls_mode(res, lsmode);
3841 set_ia32_op_type(res, ia32_AddrModeD);
3845 /* Load MEM -> x87 */
3846 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3847 set_ia32_frame_ent(res, fent);
3848 set_ia32_use_frame(res);
3849 add_ia32_am_offs_int(res, offs);
3850 set_ia32_op_type(res, ia32_AddrModeS);
3851 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3856 /*********************************************************
3859 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3860 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3861 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3862 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3864 *********************************************************/
3867 * the BAD transformer.
3869 static ir_node *bad_transform(ir_node *node) {
3870 panic("No transform function for %+F available.\n", node);
3875 * Transform the Projs of an AddSP.
3877 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3878 ir_node *block = be_transform_node(get_nodes_block(node));
3879 ir_node *pred = get_Proj_pred(node);
3880 ir_node *new_pred = be_transform_node(pred);
3881 ir_graph *irg = current_ir_graph;
3882 dbg_info *dbgi = get_irn_dbg_info(node);
3883 long proj = get_Proj_proj(node);
3885 if (proj == pn_be_AddSP_sp) {
3886 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3887 pn_ia32_SubSP_stack);
3888 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3890 } else if(proj == pn_be_AddSP_res) {
3891 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3892 pn_ia32_SubSP_addr);
3893 } else if (proj == pn_be_AddSP_M) {
3894 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3898 return new_rd_Unknown(irg, get_irn_mode(node));
3902 * Transform the Projs of a SubSP.
3904 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3905 ir_node *block = be_transform_node(get_nodes_block(node));
3906 ir_node *pred = get_Proj_pred(node);
3907 ir_node *new_pred = be_transform_node(pred);
3908 ir_graph *irg = current_ir_graph;
3909 dbg_info *dbgi = get_irn_dbg_info(node);
3910 long proj = get_Proj_proj(node);
3912 if (proj == pn_be_SubSP_sp) {
3913 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3914 pn_ia32_AddSP_stack);
3915 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3917 } else if (proj == pn_be_SubSP_M) {
3918 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3922 return new_rd_Unknown(irg, get_irn_mode(node));
3926 * Transform and renumber the Projs from a Load.
3928 static ir_node *gen_Proj_Load(ir_node *node) {
3930 ir_node *block = be_transform_node(get_nodes_block(node));
3931 ir_node *pred = get_Proj_pred(node);
3932 ir_graph *irg = current_ir_graph;
3933 dbg_info *dbgi = get_irn_dbg_info(node);
3934 long proj = get_Proj_proj(node);
3937 /* loads might be part of source address mode matches, so we don't
3938 transform the ProjMs yet (with the exception of loads whose result is
3941 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
3942 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
3944 /* this is needed, because sometimes we have loops that are only
3945 reachable through the ProjM */
3946 be_enqueue_preds(node);
3947 /* do it in 2 steps, to silence firm verifier */
3948 ir_node *res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
3949 set_Proj_proj(res, pn_ia32_Load_M);
3953 /* renumber the proj */
3954 new_pred = be_transform_node(pred);
3955 if (is_ia32_Load(new_pred)) {
3956 if (proj == pn_Load_res) {
3957 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3959 } else if (proj == pn_Load_M) {
3960 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3963 } else if(is_ia32_Conv_I2I(new_pred)) {
3964 set_irn_mode(new_pred, mode_T);
3965 if (proj == pn_Load_res) {
3966 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
3967 } else if (proj == pn_Load_M) {
3968 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
3970 } else if (is_ia32_xLoad(new_pred)) {
3971 if (proj == pn_Load_res) {
3972 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
3974 } else if (proj == pn_Load_M) {
3975 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3978 } else if (is_ia32_vfld(new_pred)) {
3979 if (proj == pn_Load_res) {
3980 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
3982 } else if (proj == pn_Load_M) {
3983 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
3987 /* can happen for ProJMs when source address mode happened for the
3990 /* however it should not be the result proj, as that would mean the
3991 load had multiple users and should not have been used for
3993 if(proj != pn_Load_M) {
3994 panic("internal error: transformed node not a Load");
3996 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4000 return new_rd_Unknown(irg, get_irn_mode(node));
4004 * Transform and renumber the Projs from a DivMod like instruction.
4006 static ir_node *gen_Proj_DivMod(ir_node *node) {
4007 ir_node *block = be_transform_node(get_nodes_block(node));
4008 ir_node *pred = get_Proj_pred(node);
4009 ir_node *new_pred = be_transform_node(pred);
4010 ir_graph *irg = current_ir_graph;
4011 dbg_info *dbgi = get_irn_dbg_info(node);
4012 ir_mode *mode = get_irn_mode(node);
4013 long proj = get_Proj_proj(node);
4015 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4017 switch (get_irn_opcode(pred)) {
4021 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4031 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4033 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4041 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4042 case pn_DivMod_res_div:
4043 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4044 case pn_DivMod_res_mod:
4045 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4055 return new_rd_Unknown(irg, mode);
4059 * Transform and renumber the Projs from a CopyB.
4061 static ir_node *gen_Proj_CopyB(ir_node *node) {
4062 ir_node *block = be_transform_node(get_nodes_block(node));
4063 ir_node *pred = get_Proj_pred(node);
4064 ir_node *new_pred = be_transform_node(pred);
4065 ir_graph *irg = current_ir_graph;
4066 dbg_info *dbgi = get_irn_dbg_info(node);
4067 ir_mode *mode = get_irn_mode(node);
4068 long proj = get_Proj_proj(node);
4071 case pn_CopyB_M_regular:
4072 if (is_ia32_CopyB_i(new_pred)) {
4073 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4074 } else if (is_ia32_CopyB(new_pred)) {
4075 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4083 return new_rd_Unknown(irg, mode);
4087 * Transform and renumber the Projs from a vfdiv.
4089 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4090 ir_node *block = be_transform_node(get_nodes_block(node));
4091 ir_node *pred = get_Proj_pred(node);
4092 ir_node *new_pred = be_transform_node(pred);
4093 ir_graph *irg = current_ir_graph;
4094 dbg_info *dbgi = get_irn_dbg_info(node);
4095 ir_mode *mode = get_irn_mode(node);
4096 long proj = get_Proj_proj(node);
4099 case pn_ia32_l_vfdiv_M:
4100 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4101 case pn_ia32_l_vfdiv_res:
4102 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4107 return new_rd_Unknown(irg, mode);
4111 * Transform and renumber the Projs from a Quot.
4113 static ir_node *gen_Proj_Quot(ir_node *node) {
4114 ir_node *block = be_transform_node(get_nodes_block(node));
4115 ir_node *pred = get_Proj_pred(node);
4116 ir_node *new_pred = be_transform_node(pred);
4117 ir_graph *irg = current_ir_graph;
4118 dbg_info *dbgi = get_irn_dbg_info(node);
4119 ir_mode *mode = get_irn_mode(node);
4120 long proj = get_Proj_proj(node);
4124 if (is_ia32_xDiv(new_pred)) {
4125 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4126 } else if (is_ia32_vfdiv(new_pred)) {
4127 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4131 if (is_ia32_xDiv(new_pred)) {
4132 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4133 } else if (is_ia32_vfdiv(new_pred)) {
4134 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4142 return new_rd_Unknown(irg, mode);
4146 * Transform the Thread Local Storage Proj.
4148 static ir_node *gen_Proj_tls(ir_node *node) {
4149 ir_node *block = be_transform_node(get_nodes_block(node));
4150 ir_graph *irg = current_ir_graph;
4151 dbg_info *dbgi = NULL;
4152 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4158 * Transform the Projs from a be_Call.
4160 static ir_node *gen_Proj_be_Call(ir_node *node) {
4161 ir_node *block = be_transform_node(get_nodes_block(node));
4162 ir_node *call = get_Proj_pred(node);
4163 ir_node *new_call = be_transform_node(call);
4164 ir_graph *irg = current_ir_graph;
4165 dbg_info *dbgi = get_irn_dbg_info(node);
4166 ir_type *method_type = be_Call_get_type(call);
4167 int n_res = get_method_n_ress(method_type);
4168 long proj = get_Proj_proj(node);
4169 ir_mode *mode = get_irn_mode(node);
4171 const arch_register_class_t *cls;
4173 /* The following is kinda tricky: If we're using SSE, then we have to
4174 * move the result value of the call in floating point registers to an
4175 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4176 * after the call, we have to make sure to correctly make the
4177 * MemProj and the result Proj use these 2 nodes
4179 if (proj == pn_be_Call_M_regular) {
4180 // get new node for result, are we doing the sse load/store hack?
4181 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4182 ir_node *call_res_new;
4183 ir_node *call_res_pred = NULL;
4185 if (call_res != NULL) {
4186 call_res_new = be_transform_node(call_res);
4187 call_res_pred = get_Proj_pred(call_res_new);
4190 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4191 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4192 pn_be_Call_M_regular);
4194 assert(is_ia32_xLoad(call_res_pred));
4195 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4199 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4200 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4201 && USE_SSE2(env_cg)) {
4203 ir_node *frame = get_irg_frame(irg);
4204 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4206 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4209 /* in case there is no memory output: create one to serialize the copy
4211 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4212 pn_be_Call_M_regular);
4213 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4214 pn_be_Call_first_res);
4216 /* store st(0) onto stack */
4217 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
4219 set_ia32_op_type(fstp, ia32_AddrModeD);
4220 set_ia32_use_frame(fstp);
4222 /* load into SSE register */
4223 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4225 set_ia32_op_type(sse_load, ia32_AddrModeS);
4226 set_ia32_use_frame(sse_load);
4228 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4234 /* transform call modes */
4235 if (mode_is_data(mode)) {
4236 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4240 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4244 * Transform the Projs from a Cmp.
4246 static ir_node *gen_Proj_Cmp(ir_node *node)
4248 /* normally Cmps are processed when looking at Cond nodes, but this case
4249 * can happen in complicated Psi conditions */
4251 ir_node *cmp = get_Proj_pred(node);
4252 long pnc = get_Proj_proj(node);
4253 ir_node *cmp_left = get_Cmp_left(cmp);
4254 ir_node *cmp_right = get_Cmp_right(cmp);
4255 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4256 dbg_info *dbgi = get_irn_dbg_info(cmp);
4257 ir_node *block = get_nodes_block(node);
4260 assert(!mode_is_float(cmp_mode));
4262 if(!mode_is_signed(cmp_mode)) {
4263 pnc |= ia32_pn_Cmp_Unsigned;
4266 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
4267 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4273 * Transform and potentially renumber Proj nodes.
4275 static ir_node *gen_Proj(ir_node *node) {
4276 ir_graph *irg = current_ir_graph;
4277 dbg_info *dbgi = get_irn_dbg_info(node);
4278 ir_node *pred = get_Proj_pred(node);
4279 long proj = get_Proj_proj(node);
4281 if (is_Store(pred)) {
4282 if (proj == pn_Store_M) {
4283 return be_transform_node(pred);
4286 return new_r_Bad(irg);
4288 } else if (is_Load(pred)) {
4289 return gen_Proj_Load(node);
4290 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4291 return gen_Proj_DivMod(node);
4292 } else if (is_CopyB(pred)) {
4293 return gen_Proj_CopyB(node);
4294 } else if (is_Quot(pred)) {
4295 return gen_Proj_Quot(node);
4296 } else if (is_ia32_l_vfdiv(pred)) {
4297 return gen_Proj_l_vfdiv(node);
4298 } else if (be_is_SubSP(pred)) {
4299 return gen_Proj_be_SubSP(node);
4300 } else if (be_is_AddSP(pred)) {
4301 return gen_Proj_be_AddSP(node);
4302 } else if (be_is_Call(pred)) {
4303 return gen_Proj_be_Call(node);
4304 } else if (is_Cmp(pred)) {
4305 return gen_Proj_Cmp(node);
4306 } else if (get_irn_op(pred) == op_Start) {
4307 if (proj == pn_Start_X_initial_exec) {
4308 ir_node *block = get_nodes_block(pred);
4311 /* we exchange the ProjX with a jump */
4312 block = be_transform_node(block);
4313 jump = new_rd_Jmp(dbgi, irg, block);
4316 if (node == be_get_old_anchor(anchor_tls)) {
4317 return gen_Proj_tls(node);
4320 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4324 ir_node *new_pred = be_transform_node(pred);
4325 ir_node *block = be_transform_node(get_nodes_block(node));
4326 ir_mode *mode = get_irn_mode(node);
4327 if (mode_needs_gp_reg(mode)) {
4328 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4329 get_Proj_proj(node));
4330 #ifdef DEBUG_libfirm
4331 new_proj->node_nr = node->node_nr;
4337 return be_duplicate_node(node);
4341 * Enters all transform functions into the generic pointer
4343 static void register_transformers(void)
4347 /* first clear the generic function pointer for all ops */
4348 clear_irp_opcodes_generic_func();
4350 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4351 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4388 /* transform ops from intrinsic lowering */
4411 GEN(ia32_l_X87toSSE);
4412 GEN(ia32_l_SSEtoX87);
4418 /* we should never see these nodes */
4433 /* handle generic backend nodes */
4441 op_Mulh = get_op_Mulh();
4450 * Pre-transform all unknown and noreg nodes.
4452 static void ia32_pretransform_node(void *arch_cg) {
4453 ia32_code_gen_t *cg = arch_cg;
4455 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4456 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4457 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4458 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4459 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4460 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4465 * Walker, checks if all ia32 nodes producing more than one result have
4466 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4469 void add_missing_keep_walker(ir_node *node, void *data)
4472 unsigned found_projs = 0;
4473 const ir_edge_t *edge;
4474 ir_mode *mode = get_irn_mode(node);
4479 if(!is_ia32_irn(node))
4482 n_outs = get_ia32_n_res(node);
4485 if(is_ia32_SwitchJmp(node))
4488 assert(n_outs < (int) sizeof(unsigned) * 8);
4489 foreach_out_edge(node, edge) {
4490 ir_node *proj = get_edge_src_irn(edge);
4491 int pn = get_Proj_proj(proj);
4493 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4494 found_projs |= 1 << pn;
4498 /* are keeps missing? */
4500 for(i = 0; i < n_outs; ++i) {
4503 const arch_register_req_t *req;
4504 const arch_register_class_t *class;
4506 if(found_projs & (1 << i)) {
4510 req = get_ia32_out_req(node, i);
4516 block = get_nodes_block(node);
4517 in[0] = new_r_Proj(current_ir_graph, block, node,
4518 arch_register_class_mode(class), i);
4519 if(last_keep != NULL) {
4520 be_Keep_add_node(last_keep, class, in[0]);
4522 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4528 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4532 void add_missing_keeps(ia32_code_gen_t *cg)
4534 ir_graph *irg = be_get_birg_irg(cg->birg);
4535 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4538 /* do the transformation */
4539 void ia32_transform_graph(ia32_code_gen_t *cg) {
4540 register_transformers();
4542 initial_fpcw = NULL;
4544 heights = heights_new(cg->irg);
4546 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4548 heights_free(heights);
4550 add_missing_keeps(cg);
4553 void ia32_init_transform(void)
4555 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");