2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
28 #include "archop.h" /* we need this for Min and Max nodes */
30 #include "../benode_t.h"
31 #include "../besched.h"
34 #include "bearch_ia32_t.h"
35 #include "ia32_nodes_attr.h"
36 #include "ia32_transform.h"
37 #include "ia32_new_nodes.h"
38 #include "ia32_map_regs.h"
39 #include "ia32_dbg_stat.h"
40 #include "ia32_optimize.h"
42 #include "gen_ia32_regalloc_if.h"
44 #define SFP_SIGN "0x80000000"
45 #define DFP_SIGN "0x8000000000000000"
46 #define SFP_ABS "0x7FFFFFFF"
47 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
49 #define TP_SFP_SIGN "ia32_sfp_sign"
50 #define TP_DFP_SIGN "ia32_dfp_sign"
51 #define TP_SFP_ABS "ia32_sfp_abs"
52 #define TP_DFP_ABS "ia32_dfp_abs"
54 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
55 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
56 #define ENT_SFP_ABS "IA32_SFP_ABS"
57 #define ENT_DFP_ABS "IA32_DFP_ABS"
59 extern ir_op *get_op_Mulh(void);
61 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op1, ir_node *op2, ir_node *mem);
64 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op, ir_node *mem);
68 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
71 /****************************************************************************************************
73 * | | | | / _| | | (_)
74 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
75 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
76 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
77 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
79 ****************************************************************************************************/
82 * Returns 1 if irn is a Const representing 0, 0 otherwise
84 static INLINE int is_ia32_Const_0(ir_node *irn) {
85 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
89 * Returns 1 if irn is a Const representing 1, 0 otherwise
91 static INLINE int is_ia32_Const_1(ir_node *irn) {
92 return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
96 * Returns the Proj representing the UNKNOWN register for given mode.
98 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
99 be_abi_irg_t *babi = cg->birg->abi;
100 const arch_register_t *unknwn_reg = NULL;
102 if (mode_is_float(mode)) {
103 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
106 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
109 return be_abi_get_callee_save_irn(babi, unknwn_reg);
113 * Gets the Proj with number pn from irn.
115 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
116 const ir_edge_t *edge;
118 assert(get_irn_mode(irn) == mode_T && "need mode_T");
120 foreach_out_edge(irn, edge) {
121 proj = get_edge_src_irn(edge);
123 if (get_Proj_proj(proj) == pn)
131 * SSE convert of an integer node into a floating point node.
133 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
134 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
136 ir_node *noreg = ia32_new_NoReg_gp(cg);
137 ir_node *nomem = new_rd_NoMem(irg);
139 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
140 set_ia32_src_mode(conv, get_irn_mode(in));
141 set_ia32_tgt_mode(conv, tgt_mode);
142 set_ia32_am_support(conv, ia32_am_Source);
143 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
145 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
148 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
149 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
150 static const struct {
152 const char *ent_name;
153 const char *cnst_str;
154 } names [ia32_known_const_max] = {
155 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
156 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
157 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
158 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
160 static struct entity *ent_cache[ia32_known_const_max];
162 const char *tp_name, *ent_name, *cnst_str;
169 ent_name = names[kct].ent_name;
170 if (! ent_cache[kct]) {
171 tp_name = names[kct].tp_name;
172 cnst_str = names[kct].cnst_str;
174 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
175 tp = new_type_primitive(new_id_from_str(tp_name), mode);
176 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
178 set_entity_ld_ident(ent, get_entity_ident(ent));
179 set_entity_visibility(ent, visibility_local);
180 set_entity_variability(ent, variability_constant);
181 set_entity_allocation(ent, allocation_static);
183 /* we create a new entity here: It's initialization must resist on the
185 rem = current_ir_graph;
186 current_ir_graph = get_const_code_irg();
187 cnst = new_Const(mode, tv);
188 current_ir_graph = rem;
190 set_atomic_ent_value(ent, cnst);
192 /* cache the entry */
193 ent_cache[kct] = ent;
196 return get_entity_ident(ent_cache[kct]);
201 * Prints the old node name on cg obst and returns a pointer to it.
203 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
204 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
206 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
207 obstack_1grow(isa->name_obst, 0);
208 isa->name_obst_size += obstack_object_size(isa->name_obst);
209 return obstack_finish(isa->name_obst);
213 /* determine if one operator is an Imm */
214 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
216 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
217 else return is_ia32_Cnst(op2) ? op2 : NULL;
220 /* determine if one operator is not an Imm */
221 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
222 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
227 * Construct a standard binary operation, set AM and immediate if required.
229 * @param env The transformation environment
230 * @param op1 The first operand
231 * @param op2 The second operand
232 * @param func The node constructor function
233 * @return The constructed ia32 node.
235 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
236 ir_node *new_op = NULL;
237 ir_mode *mode = env->mode;
238 dbg_info *dbg = env->dbg;
239 ir_graph *irg = env->irg;
240 ir_node *block = env->block;
241 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
242 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
243 ir_node *nomem = new_NoMem();
244 ir_node *expr_op, *imm_op;
245 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
247 /* Check if immediate optimization is on and */
248 /* if it's an operation with immediate. */
249 if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
253 else if (is_op_commutative(get_irn_op(env->irn))) {
254 imm_op = get_immediate_op(op1, op2);
255 expr_op = get_expr_op(op1, op2);
258 imm_op = get_immediate_op(NULL, op2);
259 expr_op = get_expr_op(op1, op2);
262 assert((expr_op || imm_op) && "invalid operands");
265 /* We have two consts here: not yet supported */
269 if (mode_is_float(mode)) {
270 /* floating point operations */
272 DB((mod, LEVEL_1, "FP with immediate ..."));
273 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
274 set_ia32_Immop_attr(new_op, imm_op);
275 set_ia32_am_support(new_op, ia32_am_None);
278 DB((mod, LEVEL_1, "FP binop ..."));
279 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
280 set_ia32_am_support(new_op, ia32_am_Source);
282 set_ia32_ls_mode(new_op, mode);
285 /* integer operations */
287 /* This is expr + const */
288 DB((mod, LEVEL_1, "INT with immediate ..."));
289 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
290 set_ia32_Immop_attr(new_op, imm_op);
293 set_ia32_am_support(new_op, ia32_am_Dest);
296 DB((mod, LEVEL_1, "INT binop ..."));
297 /* This is a normal operation */
298 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
301 set_ia32_am_support(new_op, ia32_am_Full);
305 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
307 set_ia32_res_mode(new_op, mode);
309 if (is_op_commutative(get_irn_op(env->irn))) {
310 set_ia32_commutative(new_op);
313 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
319 * Construct a shift/rotate binary operation, sets AM and immediate if required.
321 * @param env The transformation environment
322 * @param op1 The first operand
323 * @param op2 The second operand
324 * @param func The node constructor function
325 * @return The constructed ia32 node.
327 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
328 ir_node *new_op = NULL;
329 ir_mode *mode = env->mode;
330 dbg_info *dbg = env->dbg;
331 ir_graph *irg = env->irg;
332 ir_node *block = env->block;
333 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
334 ir_node *nomem = new_NoMem();
335 ir_node *expr_op, *imm_op;
337 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
339 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
341 /* Check if immediate optimization is on and */
342 /* if it's an operation with immediate. */
343 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
344 expr_op = get_expr_op(op1, op2);
346 assert((expr_op || imm_op) && "invalid operands");
349 /* We have two consts here: not yet supported */
353 /* Limit imm_op within range imm8 */
355 tv = get_ia32_Immop_tarval(imm_op);
358 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
359 set_ia32_Immop_tarval(imm_op, tv);
366 /* integer operations */
368 /* This is shift/rot with const */
369 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
371 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
372 set_ia32_Immop_attr(new_op, imm_op);
375 /* This is a normal shift/rot */
376 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
377 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
381 set_ia32_am_support(new_op, ia32_am_Dest);
383 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
385 set_ia32_res_mode(new_op, mode);
386 set_ia32_emit_cl(new_op);
388 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
393 * Construct a standard unary operation, set AM and immediate if required.
395 * @param env The transformation environment
396 * @param op The operand
397 * @param func The node constructor function
398 * @return The constructed ia32 node.
400 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
401 ir_node *new_op = NULL;
402 ir_mode *mode = env->mode;
403 dbg_info *dbg = env->dbg;
404 ir_graph *irg = env->irg;
405 ir_node *block = env->block;
406 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
407 ir_node *nomem = new_NoMem();
408 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
410 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
412 if (mode_is_float(mode)) {
413 DB((mod, LEVEL_1, "FP unop ..."));
414 /* floating point operations don't support implicit store */
415 set_ia32_am_support(new_op, ia32_am_None);
418 DB((mod, LEVEL_1, "INT unop ..."));
419 set_ia32_am_support(new_op, ia32_am_Dest);
422 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
424 set_ia32_res_mode(new_op, mode);
426 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
432 * Creates an ia32 Add with immediate.
434 * @param env The transformation environment
435 * @param expr_op The expression operator
436 * @param const_op The constant
437 * @return the created ia32 Add node
439 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
440 ir_node *new_op = NULL;
441 tarval *tv = get_ia32_Immop_tarval(const_op);
442 dbg_info *dbg = env->dbg;
443 ir_graph *irg = env->irg;
444 ir_node *block = env->block;
445 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
446 ir_node *nomem = new_NoMem();
448 tarval_classification_t class_tv, class_negtv;
449 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
451 /* try to optimize to inc/dec */
452 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
453 /* optimize tarvals */
454 class_tv = classify_tarval(tv);
455 class_negtv = classify_tarval(tarval_neg(tv));
457 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
458 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
459 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
462 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
463 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
464 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
470 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
471 set_ia32_Immop_attr(new_op, const_op);
472 set_ia32_commutative(new_op);
479 * Creates an ia32 Add.
481 * @param env The transformation environment
482 * @return the created ia32 Add node
484 static ir_node *gen_Add(ia32_transform_env_t *env) {
485 ir_node *new_op = NULL;
486 dbg_info *dbg = env->dbg;
487 ir_mode *mode = env->mode;
488 ir_graph *irg = env->irg;
489 ir_node *block = env->block;
490 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
491 ir_node *nomem = new_NoMem();
492 ir_node *expr_op, *imm_op;
493 ir_node *op1 = get_Add_left(env->irn);
494 ir_node *op2 = get_Add_right(env->irn);
496 /* Check if immediate optimization is on and */
497 /* if it's an operation with immediate. */
498 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
499 expr_op = get_expr_op(op1, op2);
501 assert((expr_op || imm_op) && "invalid operands");
503 if (mode_is_float(mode)) {
505 if (USE_SSE2(env->cg))
506 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
508 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
513 /* No expr_op means, that we have two const - one symconst and */
514 /* one tarval or another symconst - because this case is not */
515 /* covered by constant folding */
516 /* We need to check for: */
517 /* 1) symconst + const -> becomes a LEA */
518 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
519 /* linker doesn't support two symconsts */
521 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
522 /* this is the 2nd case */
523 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
524 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
525 set_ia32_am_flavour(new_op, ia32_am_OB);
527 DBG_OPT_LEA1(op2, new_op);
530 /* this is the 1st case */
531 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
533 DBG_OPT_LEA2(op1, op2, new_op);
535 if (get_ia32_op_type(op1) == ia32_SymConst) {
536 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
537 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
540 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
541 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
543 set_ia32_am_flavour(new_op, ia32_am_O);
547 set_ia32_am_support(new_op, ia32_am_Source);
548 set_ia32_op_type(new_op, ia32_AddrModeS);
550 /* Lea doesn't need a Proj */
554 /* This is expr + const */
555 new_op = gen_imm_Add(env, expr_op, imm_op);
558 set_ia32_am_support(new_op, ia32_am_Dest);
561 /* This is a normal add */
562 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
565 set_ia32_am_support(new_op, ia32_am_Full);
566 set_ia32_commutative(new_op);
570 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
572 set_ia32_res_mode(new_op, mode);
574 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
580 * Creates an ia32 Mul.
582 * @param env The transformation environment
583 * @return the created ia32 Mul node
585 static ir_node *gen_Mul(ia32_transform_env_t *env) {
586 ir_node *op1 = get_Mul_left(env->irn);
587 ir_node *op2 = get_Mul_right(env->irn);
590 if (mode_is_float(env->mode)) {
592 if (USE_SSE2(env->cg))
593 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
595 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
598 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
607 * Creates an ia32 Mulh.
608 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
609 * this result while Mul returns the lower 32 bit.
611 * @param env The transformation environment
612 * @return the created ia32 Mulh node
614 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
615 ir_node *op1 = get_irn_n(env->irn, 0);
616 ir_node *op2 = get_irn_n(env->irn, 1);
617 ir_node *proj_EAX, *proj_EDX, *mulh;
620 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
621 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
622 mulh = get_Proj_pred(proj_EAX);
623 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
625 /* to be on the save side */
626 set_Proj_proj(proj_EAX, pn_EAX);
628 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
629 /* Mulh with const cannot have AM */
630 set_ia32_am_support(mulh, ia32_am_None);
633 /* Mulh cannot have AM for destination */
634 set_ia32_am_support(mulh, ia32_am_Source);
640 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
648 * Creates an ia32 And.
650 * @param env The transformation environment
651 * @return The created ia32 And node
653 static ir_node *gen_And(ia32_transform_env_t *env) {
654 ir_node *op1 = get_And_left(env->irn);
655 ir_node *op2 = get_And_right(env->irn);
657 assert (! mode_is_float(env->mode));
658 return gen_binop(env, op1, op2, new_rd_ia32_And);
664 * Creates an ia32 Or.
666 * @param env The transformation environment
667 * @return The created ia32 Or node
669 static ir_node *gen_Or(ia32_transform_env_t *env) {
670 ir_node *op1 = get_Or_left(env->irn);
671 ir_node *op2 = get_Or_right(env->irn);
673 assert (! mode_is_float(env->mode));
674 return gen_binop(env, op1, op2, new_rd_ia32_Or);
680 * Creates an ia32 Eor.
682 * @param env The transformation environment
683 * @return The created ia32 Eor node
685 static ir_node *gen_Eor(ia32_transform_env_t *env) {
686 ir_node *op1 = get_Eor_left(env->irn);
687 ir_node *op2 = get_Eor_right(env->irn);
689 assert(! mode_is_float(env->mode));
690 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
696 * Creates an ia32 Max.
698 * @param env The transformation environment
699 * @return the created ia32 Max node
701 static ir_node *gen_Max(ia32_transform_env_t *env) {
702 ir_node *op1 = get_irn_n(env->irn, 0);
703 ir_node *op2 = get_irn_n(env->irn, 1);
706 if (mode_is_float(env->mode)) {
708 if (USE_SSE2(env->cg))
709 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
715 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
716 set_ia32_am_support(new_op, ia32_am_None);
717 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
726 * Creates an ia32 Min.
728 * @param env The transformation environment
729 * @return the created ia32 Min node
731 static ir_node *gen_Min(ia32_transform_env_t *env) {
732 ir_node *op1 = get_irn_n(env->irn, 0);
733 ir_node *op2 = get_irn_n(env->irn, 1);
736 if (mode_is_float(env->mode)) {
738 if (USE_SSE2(env->cg))
739 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
745 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
746 set_ia32_am_support(new_op, ia32_am_None);
747 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
756 * Creates an ia32 Sub with immediate.
758 * @param env The transformation environment
759 * @param expr_op The first operator
760 * @param const_op The constant operator
761 * @return The created ia32 Sub node
763 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
764 ir_node *new_op = NULL;
765 tarval *tv = get_ia32_Immop_tarval(const_op);
766 dbg_info *dbg = env->dbg;
767 ir_graph *irg = env->irg;
768 ir_node *block = env->block;
769 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
770 ir_node *nomem = new_NoMem();
772 tarval_classification_t class_tv, class_negtv;
773 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
775 /* try to optimize to inc/dec */
776 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
777 /* optimize tarvals */
778 class_tv = classify_tarval(tv);
779 class_negtv = classify_tarval(tarval_neg(tv));
781 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
782 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
783 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
786 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
787 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
788 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
794 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
795 set_ia32_Immop_attr(new_op, const_op);
802 * Creates an ia32 Sub.
804 * @param env The transformation environment
805 * @return The created ia32 Sub node
807 static ir_node *gen_Sub(ia32_transform_env_t *env) {
808 ir_node *new_op = NULL;
809 dbg_info *dbg = env->dbg;
810 ir_mode *mode = env->mode;
811 ir_graph *irg = env->irg;
812 ir_node *block = env->block;
813 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
814 ir_node *nomem = new_NoMem();
815 ir_node *op1 = get_Sub_left(env->irn);
816 ir_node *op2 = get_Sub_right(env->irn);
817 ir_node *expr_op, *imm_op;
819 /* Check if immediate optimization is on and */
820 /* if it's an operation with immediate. */
821 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
822 expr_op = get_expr_op(op1, op2);
824 assert((expr_op || imm_op) && "invalid operands");
826 if (mode_is_float(mode)) {
828 if (USE_SSE2(env->cg))
829 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
831 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
836 /* No expr_op means, that we have two const - one symconst and */
837 /* one tarval or another symconst - because this case is not */
838 /* covered by constant folding */
839 /* We need to check for: */
840 /* 1) symconst + const -> becomes a LEA */
841 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
842 /* linker doesn't support two symconsts */
844 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
845 /* this is the 2nd case */
846 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
847 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
848 set_ia32_am_sc_sign(new_op);
849 set_ia32_am_flavour(new_op, ia32_am_OB);
851 DBG_OPT_LEA1(op2, new_op);
854 /* this is the 1st case */
855 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
857 DBG_OPT_LEA2(op1, op2, new_op);
859 if (get_ia32_op_type(op1) == ia32_SymConst) {
860 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
861 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
864 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
865 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
866 set_ia32_am_sc_sign(new_op);
868 set_ia32_am_flavour(new_op, ia32_am_O);
872 set_ia32_am_support(new_op, ia32_am_Source);
873 set_ia32_op_type(new_op, ia32_AddrModeS);
875 /* Lea doesn't need a Proj */
879 /* This is expr - const */
880 new_op = gen_imm_Sub(env, expr_op, imm_op);
883 set_ia32_am_support(new_op, ia32_am_Dest);
886 /* This is a normal sub */
887 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
890 set_ia32_am_support(new_op, ia32_am_Full);
894 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
896 set_ia32_res_mode(new_op, mode);
898 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
904 * Generates an ia32 DivMod with additional infrastructure for the
905 * register allocator if needed.
907 * @param env The transformation environment
908 * @param dividend -no comment- :)
909 * @param divisor -no comment- :)
910 * @param dm_flav flavour_Div/Mod/DivMod
911 * @return The created ia32 DivMod node
913 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
915 ir_node *edx_node, *cltd;
917 dbg_info *dbg = env->dbg;
918 ir_graph *irg = env->irg;
919 ir_node *block = env->block;
920 ir_mode *mode = env->mode;
921 ir_node *irn = env->irn;
926 mem = get_Div_mem(irn);
927 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
930 mem = get_Mod_mem(irn);
931 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
934 mem = get_DivMod_mem(irn);
935 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
941 if (mode_is_signed(mode)) {
942 /* in signed mode, we need to sign extend the dividend */
943 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
944 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
945 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
948 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
949 set_ia32_Const_type(edx_node, ia32_Const);
950 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
953 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
955 set_ia32_n_res(res, 2);
957 /* Only one proj is used -> We must add a second proj and */
958 /* connect this one to a Keep node to eat up the second */
959 /* destroyed register. */
960 if (get_irn_n_edges(irn) == 1) {
961 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
962 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
964 if (get_irn_op(irn) == op_Div) {
965 set_Proj_proj(proj, pn_DivMod_res_div);
966 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
969 set_Proj_proj(proj, pn_DivMod_res_mod);
970 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
973 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
976 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
978 set_ia32_res_mode(res, mode_Is);
985 * Wrapper for generate_DivMod. Sets flavour_Mod.
987 * @param env The transformation environment
989 static ir_node *gen_Mod(ia32_transform_env_t *env) {
990 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
994 * Wrapper for generate_DivMod. Sets flavour_Div.
996 * @param env The transformation environment
998 static ir_node *gen_Div(ia32_transform_env_t *env) {
999 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1003 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1005 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1006 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1012 * Creates an ia32 floating Div.
1014 * @param env The transformation environment
1015 * @return The created ia32 xDiv node
1017 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1018 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1020 ir_node *nomem = new_rd_NoMem(env->irg);
1021 ir_node *op1 = get_Quot_left(env->irn);
1022 ir_node *op2 = get_Quot_right(env->irn);
1025 if (USE_SSE2(env->cg)) {
1026 if (is_ia32_xConst(op2)) {
1027 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1028 set_ia32_am_support(new_op, ia32_am_None);
1029 set_ia32_Immop_attr(new_op, op2);
1032 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1033 set_ia32_am_support(new_op, ia32_am_Source);
1037 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1038 set_ia32_am_support(new_op, ia32_am_Source);
1040 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1049 * Creates an ia32 Shl.
1051 * @param env The transformation environment
1052 * @return The created ia32 Shl node
1054 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1055 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1061 * Creates an ia32 Shr.
1063 * @param env The transformation environment
1064 * @return The created ia32 Shr node
1066 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1067 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1073 * Creates an ia32 Shrs.
1075 * @param env The transformation environment
1076 * @return The created ia32 Shrs node
1078 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1079 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1085 * Creates an ia32 RotL.
1087 * @param env The transformation environment
1088 * @param op1 The first operator
1089 * @param op2 The second operator
1090 * @return The created ia32 RotL node
1092 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1093 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1099 * Creates an ia32 RotR.
1100 * NOTE: There is no RotR with immediate because this would always be a RotL
1101 * "imm-mode_size_bits" which can be pre-calculated.
1103 * @param env The transformation environment
1104 * @param op1 The first operator
1105 * @param op2 The second operator
1106 * @return The created ia32 RotR node
1108 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1109 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1115 * Creates an ia32 RotR or RotL (depending on the found pattern).
1117 * @param env The transformation environment
1118 * @return The created ia32 RotL or RotR node
1120 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1121 ir_node *rotate = NULL;
1122 ir_node *op1 = get_Rot_left(env->irn);
1123 ir_node *op2 = get_Rot_right(env->irn);
1125 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1126 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1127 that means we can create a RotR instead of an Add and a RotL */
1130 ir_node *pred = get_Proj_pred(op2);
1132 if (is_ia32_Add(pred)) {
1133 ir_node *pred_pred = get_irn_n(pred, 2);
1134 tarval *tv = get_ia32_Immop_tarval(pred);
1135 long bits = get_mode_size_bits(env->mode);
1137 if (is_Proj(pred_pred)) {
1138 pred_pred = get_Proj_pred(pred_pred);
1141 if (is_ia32_Minus(pred_pred) &&
1142 tarval_is_long(tv) &&
1143 get_tarval_long(tv) == bits)
1145 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1146 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1153 rotate = gen_RotL(env, op1, op2);
1162 * Transforms a Minus node.
1164 * @param env The transformation environment
1165 * @param op The Minus operand
1166 * @return The created ia32 Minus node
1168 static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1173 if (mode_is_float(env->mode)) {
1175 if (USE_SSE2(env->cg)) {
1176 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1177 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1178 ir_node *nomem = new_rd_NoMem(env->irg);
1180 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1182 size = get_mode_size_bits(env->mode);
1183 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1185 set_ia32_sc(new_op, name);
1187 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1189 set_ia32_res_mode(new_op, env->mode);
1190 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1192 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1195 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1196 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1200 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1207 * Transforms a Minus node.
1209 * @param env The transformation environment
1210 * @return The created ia32 Minus node
1212 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1213 return gen_Minus_ex(env, get_Minus_op(env->irn));
1218 * Transforms a Not node.
1220 * @param env The transformation environment
1221 * @return The created ia32 Not node
1223 static ir_node *gen_Not(ia32_transform_env_t *env) {
1224 assert (! mode_is_float(env->mode));
1225 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1231 * Transforms an Abs node.
1233 * @param env The transformation environment
1234 * @return The created ia32 Abs node
1236 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1237 ir_node *res, *p_eax, *p_edx;
1238 dbg_info *dbg = env->dbg;
1239 ir_mode *mode = env->mode;
1240 ir_graph *irg = env->irg;
1241 ir_node *block = env->block;
1242 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1243 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1244 ir_node *nomem = new_NoMem();
1245 ir_node *op = get_Abs_op(env->irn);
1249 if (mode_is_float(mode)) {
1251 if (USE_SSE2(env->cg)) {
1252 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1254 size = get_mode_size_bits(mode);
1255 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1257 set_ia32_sc(res, name);
1259 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1261 set_ia32_res_mode(res, mode);
1262 set_ia32_immop_type(res, ia32_ImmSymConst);
1264 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1267 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1268 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1272 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1273 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1274 set_ia32_res_mode(res, mode);
1276 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1277 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1279 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1281 set_ia32_res_mode(res, mode);
1283 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1285 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1286 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1287 set_ia32_res_mode(res, mode);
1289 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1298 * Transforms a Load.
1300 * @param env The transformation environment
1301 * @return the created ia32 Load node
1303 static ir_node *gen_Load(ia32_transform_env_t *env) {
1304 ir_node *node = env->irn;
1305 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1306 ir_node *ptr = get_Load_ptr(node);
1307 ir_node *lptr = ptr;
1308 ir_mode *mode = get_Load_mode(node);
1311 ia32_am_flavour_t am_flav = ia32_B;
1313 /* address might be a constant (symconst or absolute address) */
1314 if (is_ia32_Const(ptr)) {
1319 if (mode_is_float(mode)) {
1321 if (USE_SSE2(env->cg))
1322 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1324 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1327 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1330 /* base is an constant address */
1332 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1333 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1336 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1342 set_ia32_am_support(new_op, ia32_am_Source);
1343 set_ia32_op_type(new_op, ia32_AddrModeS);
1344 set_ia32_am_flavour(new_op, am_flav);
1345 set_ia32_ls_mode(new_op, mode);
1347 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1355 * Transforms a Store.
1357 * @param env The transformation environment
1358 * @return the created ia32 Store node
1360 static ir_node *gen_Store(ia32_transform_env_t *env) {
1361 ir_node *node = env->irn;
1362 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1363 ir_node *val = get_Store_value(node);
1364 ir_node *ptr = get_Store_ptr(node);
1365 ir_node *sptr = ptr;
1366 ir_node *mem = get_Store_mem(node);
1367 ir_mode *mode = get_irn_mode(val);
1368 ir_node *sval = val;
1371 ia32_am_flavour_t am_flav = ia32_B;
1372 ia32_immop_type_t immop = ia32_ImmNone;
1374 if (! mode_is_float(mode)) {
1375 /* in case of storing a const (but not a symconst) -> make it an attribute */
1376 if (is_ia32_Cnst(val)) {
1377 switch (get_ia32_op_type(val)) {
1379 immop = ia32_ImmConst;
1382 immop = ia32_ImmSymConst;
1385 assert(0 && "unsupported Const type");
1391 /* address might be a constant (symconst or absolute address) */
1392 if (is_ia32_Const(ptr)) {
1397 if (mode_is_float(mode)) {
1399 if (USE_SSE2(env->cg))
1400 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1402 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1404 else if (get_mode_size_bits(mode) == 8) {
1405 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1408 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1411 /* stored const is an attribute (saves a register) */
1412 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1413 set_ia32_Immop_attr(new_op, val);
1416 /* base is an constant address */
1418 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1419 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1422 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1428 set_ia32_am_support(new_op, ia32_am_Dest);
1429 set_ia32_op_type(new_op, ia32_AddrModeD);
1430 set_ia32_am_flavour(new_op, am_flav);
1431 set_ia32_ls_mode(new_op, get_irn_mode(val));
1432 set_ia32_immop_type(new_op, immop);
1434 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1442 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1444 * @param env The transformation environment
1445 * @return The transformed node.
1447 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1448 dbg_info *dbg = env->dbg;
1449 ir_graph *irg = env->irg;
1450 ir_node *block = env->block;
1451 ir_node *node = env->irn;
1452 ir_node *sel = get_Cond_selector(node);
1453 ir_mode *sel_mode = get_irn_mode(sel);
1454 ir_node *res = NULL;
1455 ir_node *pred = NULL;
1456 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1457 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1459 if (is_Proj(sel) && sel_mode == mode_b) {
1460 ir_node *nomem = new_NoMem();
1462 pred = get_Proj_pred(sel);
1464 /* get both compare operators */
1465 cmp_a = get_Cmp_left(pred);
1466 cmp_b = get_Cmp_right(pred);
1468 /* check if we can use a CondJmp with immediate */
1469 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1470 expr = get_expr_op(cmp_a, cmp_b);
1473 pn_Cmp pnc = get_Proj_proj(sel);
1475 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1476 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1477 /* a Cmp A =/!= 0 */
1478 ir_node *op1 = expr;
1479 ir_node *op2 = expr;
1480 ir_node *and = skip_Proj(expr);
1481 const char *cnst = NULL;
1483 /* check, if expr is an only once used And operation */
1484 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1485 op1 = get_irn_n(and, 2);
1486 op2 = get_irn_n(and, 3);
1488 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1490 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1491 set_ia32_pncode(res, get_Proj_proj(sel));
1492 set_ia32_res_mode(res, get_irn_mode(op1));
1495 copy_ia32_Immop_attr(res, and);
1498 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1503 if (mode_is_float(get_irn_mode(expr))) {
1505 if (USE_SSE2(env->cg))
1506 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1512 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1514 set_ia32_Immop_attr(res, cnst);
1515 set_ia32_res_mode(res, get_irn_mode(expr));
1518 if (mode_is_float(get_irn_mode(cmp_a))) {
1520 if (USE_SSE2(env->cg))
1521 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1524 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1525 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1526 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1530 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1531 set_ia32_commutative(res);
1533 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1536 set_ia32_pncode(res, get_Proj_proj(sel));
1537 //set_ia32_am_support(res, ia32_am_Source);
1540 /* determine the smallest switch case value */
1541 int switch_min = INT_MAX;
1542 const ir_edge_t *edge;
1545 foreach_out_edge(node, edge) {
1546 int pn = get_Proj_proj(get_edge_src_irn(edge));
1547 switch_min = pn < switch_min ? pn : switch_min;
1551 /* if smallest switch case is not 0 we need an additional sub */
1552 snprintf(buf, sizeof(buf), "%d", switch_min);
1553 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1554 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1555 sub_ia32_am_offs(res, buf);
1556 set_ia32_am_flavour(res, ia32_am_OB);
1557 set_ia32_am_support(res, ia32_am_Source);
1558 set_ia32_op_type(res, ia32_AddrModeS);
1561 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1562 set_ia32_pncode(res, get_Cond_defaultProj(node));
1563 set_ia32_res_mode(res, get_irn_mode(sel));
1566 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1573 * Transforms a CopyB node.
1575 * @param env The transformation environment
1576 * @return The transformed node.
1578 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1579 ir_node *res = NULL;
1580 dbg_info *dbg = env->dbg;
1581 ir_graph *irg = env->irg;
1582 ir_mode *mode = env->mode;
1583 ir_node *block = env->block;
1584 ir_node *node = env->irn;
1585 ir_node *src = get_CopyB_src(node);
1586 ir_node *dst = get_CopyB_dst(node);
1587 ir_node *mem = get_CopyB_mem(node);
1588 int size = get_type_size_bytes(get_CopyB_type(node));
1591 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1592 /* then we need the size explicitly in ECX. */
1593 if (size >= 16 * 4) {
1594 rem = size & 0x3; /* size % 4 */
1597 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1598 set_ia32_op_type(res, ia32_Const);
1599 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1601 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1602 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1605 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1606 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1607 set_ia32_immop_type(res, ia32_ImmConst);
1610 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1618 * Transforms a Mux node into CMov.
1620 * @param env The transformation environment
1621 * @return The transformed node.
1623 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1625 ir_node *node = env->irn;
1626 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1627 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1629 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1636 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1637 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1640 * Transforms a Psi node into CMov.
1642 * @param env The transformation environment
1643 * @return The transformed node.
1645 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1646 ia32_code_gen_t *cg = env->cg;
1647 dbg_info *dbg = env->dbg;
1648 ir_graph *irg = env->irg;
1649 ir_mode *mode = env->mode;
1650 ir_node *block = env->block;
1651 ir_node *node = env->irn;
1652 ir_node *cmp_proj = get_Mux_sel(node);
1653 ir_node *psi_true = get_Psi_val(node, 0);
1654 ir_node *psi_default = get_Psi_default(node);
1655 ir_node *noreg = ia32_new_NoReg_gp(cg);
1656 ir_node *nomem = new_rd_NoMem(irg);
1657 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1660 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1662 cmp = get_Proj_pred(cmp_proj);
1663 cmp_a = get_Cmp_left(cmp);
1664 cmp_b = get_Cmp_right(cmp);
1665 pnc = get_Proj_proj(cmp_proj);
1667 if (mode_is_float(mode)) {
1668 /* floating point psi */
1671 /* 1st case: compare operands are float too */
1673 /* psi(cmp(a, b), t, f) can be done as: */
1674 /* tmp = cmp a, b */
1675 /* tmp2 = t and tmp */
1676 /* tmp3 = f and not tmp */
1677 /* res = tmp2 or tmp3 */
1679 /* in case the compare operands are int, we move them into xmm register */
1680 if (! mode_is_float(get_irn_mode(cmp_a))) {
1681 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1682 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1684 pnc |= 8; /* transform integer compare to fp compare */
1687 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1688 set_ia32_pncode(new_op, pnc);
1689 set_ia32_am_support(new_op, ia32_am_Source);
1690 set_ia32_res_mode(new_op, mode);
1691 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1692 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1694 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1695 set_ia32_am_support(and1, ia32_am_Source);
1696 set_ia32_res_mode(and1, mode);
1697 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1698 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1700 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1701 set_ia32_am_support(and2, ia32_am_Source);
1702 set_ia32_res_mode(and2, mode);
1703 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1704 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1706 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1707 set_ia32_am_support(new_op, ia32_am_Source);
1708 set_ia32_res_mode(new_op, mode);
1709 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1710 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1714 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1715 set_ia32_pncode(new_op, pnc);
1716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1721 construct_binop_func *set_func = NULL;
1722 cmov_func_t *cmov_func = NULL;
1724 if (mode_is_float(get_irn_mode(cmp_a))) {
1725 /* 1st case: compare operands are floats */
1730 set_func = new_rd_ia32_xCmpSet;
1731 cmov_func = new_rd_ia32_xCmpCMov;
1735 set_func = new_rd_ia32_vfCmpSet;
1736 cmov_func = new_rd_ia32_vfCmpCMov;
1739 pnc &= 7; /* fp compare -> int compare */
1742 /* 2nd case: compare operand are integer too */
1743 set_func = new_rd_ia32_CmpSet;
1744 cmov_func = new_rd_ia32_CmpCMov;
1747 /* create the nodes */
1749 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1750 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1751 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1752 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1753 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1754 set_ia32_pncode(new_op, pnc);
1756 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1757 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1758 /* we invert condition and set default to 0 */
1759 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1760 set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
1763 /* otherwise: use CMOVcc */
1764 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1765 set_ia32_pncode(new_op, pnc);
1768 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1772 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1773 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1774 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1775 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1776 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1778 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1779 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1780 /* we invert condition and set default to 0 */
1781 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1782 set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
1783 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1786 /* otherwise: use CMOVcc */
1787 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1788 set_ia32_pncode(new_op, pnc);
1789 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1799 * Following conversion rules apply:
1803 * 1) n bit -> m bit n > m (downscale)
1804 * a) target is signed: movsx
1805 * b) target is unsigned: and with lower bits sets
1806 * 2) n bit -> m bit n == m (sign change)
1808 * 3) n bit -> m bit n < m (upscale)
1809 * a) source is signed: movsx
1810 * b) source is unsigned: and with lower bits sets
1814 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1818 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1819 * if target mode < 32bit: additional INT -> INT conversion (see above)
1823 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1824 * x87 is mode_E internally, conversions happen only at load and store
1825 * in non-strict semantic
1829 * Create a conversion from x87 state register to general purpose.
1831 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1832 ia32_code_gen_t *cg = env->cg;
1833 entity *ent = cg->fp_to_gp;
1834 ir_graph *irg = env->irg;
1835 ir_node *block = env->block;
1836 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1837 ir_node *op = get_Conv_op(env->irn);
1838 ir_node *fist, *mem, *load;
1841 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1842 ent = cg->fp_to_gp =
1843 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1847 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1849 set_ia32_frame_ent(fist, ent);
1850 set_ia32_use_frame(fist);
1851 set_ia32_am_support(fist, ia32_am_Dest);
1852 set_ia32_op_type(fist, ia32_AddrModeD);
1853 set_ia32_am_flavour(fist, ia32_B);
1854 set_ia32_ls_mode(fist, mode_E);
1856 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1859 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1861 set_ia32_frame_ent(load, ent);
1862 set_ia32_use_frame(load);
1863 set_ia32_am_support(load, ia32_am_Source);
1864 set_ia32_op_type(load, ia32_AddrModeS);
1865 set_ia32_am_flavour(load, ia32_B);
1866 set_ia32_ls_mode(load, tgt_mode);
1868 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1872 * Create a conversion from x87 state register to general purpose.
1874 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1875 ia32_code_gen_t *cg = env->cg;
1876 entity *ent = cg->gp_to_fp;
1877 ir_graph *irg = env->irg;
1878 ir_node *block = env->block;
1879 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1880 ir_node *nomem = get_irg_no_mem(irg);
1881 ir_node *op = get_Conv_op(env->irn);
1882 ir_node *fild, *store, *mem;
1886 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1887 ent = cg->gp_to_fp =
1888 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1891 /* first convert to 32 bit */
1892 src_bits = get_mode_size_bits(src_mode);
1893 if (src_bits == 8) {
1894 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1895 op = new_r_Proj(irg, block, op, mode_Is, 0);
1897 else if (src_bits < 32) {
1898 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1899 op = new_r_Proj(irg, block, op, mode_Is, 0);
1903 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1905 set_ia32_frame_ent(store, ent);
1906 set_ia32_use_frame(store);
1908 set_ia32_am_support(store, ia32_am_Dest);
1909 set_ia32_op_type(store, ia32_AddrModeD);
1910 set_ia32_am_flavour(store, ia32_B);
1911 set_ia32_ls_mode(store, mode_Is);
1913 mem = new_r_Proj(irg, block, store, mode_M, 0);
1916 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1918 set_ia32_frame_ent(fild, ent);
1919 set_ia32_use_frame(fild);
1920 set_ia32_am_support(fild, ia32_am_Source);
1921 set_ia32_op_type(fild, ia32_AddrModeS);
1922 set_ia32_am_flavour(fild, ia32_B);
1923 set_ia32_ls_mode(fild, mode_E);
1925 return new_r_Proj(irg, block, fild, mode_E, 0);
1929 * Transforms a Conv node.
1931 * @param env The transformation environment
1932 * @return The created ia32 Conv node
1934 static ir_node *gen_Conv(ia32_transform_env_t *env) {
1935 dbg_info *dbg = env->dbg;
1936 ir_graph *irg = env->irg;
1937 ir_node *op = get_Conv_op(env->irn);
1938 ir_mode *src_mode = get_irn_mode(op);
1939 ir_mode *tgt_mode = env->mode;
1940 int src_bits = get_mode_size_bits(src_mode);
1941 int tgt_bits = get_mode_size_bits(tgt_mode);
1943 ir_node *block = env->block;
1944 ir_node *new_op = NULL;
1945 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1946 ir_node *nomem = new_rd_NoMem(irg);
1948 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1950 if (src_mode == tgt_mode) {
1951 /* this can happen when changing mode_P to mode_Is */
1952 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1953 edges_reroute(env->irn, op, irg);
1955 else if (mode_is_float(src_mode)) {
1956 /* we convert from float ... */
1957 if (mode_is_float(tgt_mode)) {
1959 if (USE_SSE2(env->cg)) {
1960 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1961 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
1962 pn = pn_ia32_Conv_FP2FP_res;
1965 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1966 edges_reroute(env->irn, op, irg);
1971 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1972 if (USE_SSE2(env->cg)) {
1973 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
1974 pn = pn_ia32_Conv_FP2I_res;
1977 return gen_x87_fp_to_gp(env, tgt_mode);
1979 /* if target mode is not int: add an additional downscale convert */
1980 if (tgt_bits < 32) {
1981 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1982 set_ia32_am_support(new_op, ia32_am_Source);
1983 set_ia32_tgt_mode(new_op, tgt_mode);
1984 set_ia32_src_mode(new_op, src_mode);
1986 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
1988 if (tgt_bits == 8 || src_bits == 8) {
1989 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
1990 pn = pn_ia32_Conv_I2I8Bit_res;
1993 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
1994 pn = pn_ia32_Conv_I2I_res;
2000 /* we convert from int ... */
2001 if (mode_is_float(tgt_mode)) {
2004 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2005 if (USE_SSE2(env->cg)) {
2006 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2007 pn = pn_ia32_Conv_I2FP_res;
2010 return gen_x87_gp_to_fp(env, src_mode);
2014 if (get_mode_size_bits(src_mode) == tgt_bits) {
2015 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2016 edges_reroute(env->irn, op, irg);
2019 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2020 if (tgt_bits == 8 || src_bits == 8) {
2021 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2022 pn = pn_ia32_Conv_I2I8Bit_res;
2025 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2026 pn = pn_ia32_Conv_I2I_res;
2033 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2034 set_ia32_tgt_mode(new_op, tgt_mode);
2035 set_ia32_src_mode(new_op, src_mode);
2037 set_ia32_am_support(new_op, ia32_am_Source);
2039 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2047 /********************************************
2050 * | |__ ___ _ __ ___ __| | ___ ___
2051 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2052 * | |_) | __/ | | | (_) | (_| | __/\__ \
2053 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2055 ********************************************/
2058 * Decides in which block the transformed StackParam should be placed.
2059 * If the StackParam has more than one user, the dominator block of
2060 * the users will be returned. In case of only one user, this is either
2061 * the user block or, in case of a Phi, the predecessor block of the Phi.
2063 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2064 ir_node *dom_bl = NULL;
2066 if (get_irn_n_edges(irn) == 1) {
2067 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2069 if (! is_Phi(src)) {
2070 dom_bl = get_nodes_block(src);
2073 /* Determine on which in position of the Phi the irn is */
2074 /* and get the corresponding cfg predecessor block. */
2076 int i = get_irn_pred_pos(src, irn);
2077 assert(i >= 0 && "kaputt");
2078 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2082 dom_bl = node_users_smallest_common_dominator(irn, 1);
2085 assert(dom_bl && "dominator block not found");
2090 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2091 ir_node *new_op = NULL;
2092 ir_node *node = env->irn;
2093 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2094 ir_node *mem = new_rd_NoMem(env->irg);
2095 ir_node *ptr = get_irn_n(node, 0);
2096 entity *ent = be_get_frame_entity(node);
2097 ir_mode *mode = env->mode;
2099 /* choose the block where to place the load */
2100 env->block = get_block_transformed_stack_param(node);
2102 if (mode_is_float(mode)) {
2104 if (USE_SSE2(env->cg))
2105 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2107 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2110 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2113 set_ia32_frame_ent(new_op, ent);
2114 set_ia32_use_frame(new_op);
2116 set_ia32_am_support(new_op, ia32_am_Source);
2117 set_ia32_op_type(new_op, ia32_AddrModeS);
2118 set_ia32_am_flavour(new_op, ia32_B);
2119 set_ia32_ls_mode(new_op, mode);
2121 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2123 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2127 * Transforms a FrameAddr into an ia32 Add.
2129 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2130 ir_node *new_op = NULL;
2131 ir_node *node = env->irn;
2132 ir_node *op = get_irn_n(node, 0);
2133 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2134 ir_node *nomem = new_rd_NoMem(env->irg);
2136 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2137 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
2138 set_ia32_am_support(new_op, ia32_am_Full);
2139 set_ia32_use_frame(new_op);
2140 set_ia32_immop_type(new_op, ia32_ImmConst);
2141 set_ia32_commutative(new_op);
2143 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2145 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2149 * Transforms a FrameLoad into an ia32 Load.
2151 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2152 ir_node *new_op = NULL;
2153 ir_node *node = env->irn;
2154 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2155 ir_node *mem = get_irn_n(node, 0);
2156 ir_node *ptr = get_irn_n(node, 1);
2157 entity *ent = be_get_frame_entity(node);
2158 ir_mode *mode = get_type_mode(get_entity_type(ent));
2160 if (mode_is_float(mode)) {
2162 if (USE_SSE2(env->cg))
2163 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2165 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2168 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2170 set_ia32_frame_ent(new_op, ent);
2171 set_ia32_use_frame(new_op);
2173 set_ia32_am_support(new_op, ia32_am_Source);
2174 set_ia32_op_type(new_op, ia32_AddrModeS);
2175 set_ia32_am_flavour(new_op, ia32_B);
2176 set_ia32_ls_mode(new_op, mode);
2178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2185 * Transforms a FrameStore into an ia32 Store.
2187 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2188 ir_node *new_op = NULL;
2189 ir_node *node = env->irn;
2190 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2191 ir_node *mem = get_irn_n(node, 0);
2192 ir_node *ptr = get_irn_n(node, 1);
2193 ir_node *val = get_irn_n(node, 2);
2194 entity *ent = be_get_frame_entity(node);
2195 ir_mode *mode = get_irn_mode(val);
2197 if (mode_is_float(mode)) {
2199 if (USE_SSE2(env->cg))
2200 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2202 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2204 else if (get_mode_size_bits(mode) == 8) {
2205 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2208 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2211 set_ia32_frame_ent(new_op, ent);
2212 set_ia32_use_frame(new_op);
2214 set_ia32_am_support(new_op, ia32_am_Dest);
2215 set_ia32_op_type(new_op, ia32_AddrModeD);
2216 set_ia32_am_flavour(new_op, ia32_B);
2217 set_ia32_ls_mode(new_op, mode);
2219 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2225 * This function just sets the register for the Unknown node
2226 * as this is not done during register allocation because Unknown
2227 * is an "ignore" node.
2229 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2230 ir_mode *mode = env->mode;
2231 ir_node *irn = env->irn;
2233 if (mode_is_float(mode)) {
2234 if (USE_SSE2(env->cg))
2235 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2237 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2239 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2240 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2243 assert(0 && "unsupported Unknown-Mode");
2249 /**********************************************************************
2252 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2253 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2254 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2255 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2257 **********************************************************************/
2259 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2262 * Transforms an ia32_l_XXX into a "real" XXX node
2264 * @param env The transformation environment
2265 * @return the created ia32 XXX node
2267 #define GEN_LOWERED_OP(op) \
2268 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2269 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2272 #define GEN_LOWERED_UNOP(op) \
2273 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2274 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2277 #define GEN_LOWERED_SHIFT_OP(op) \
2278 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2279 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2282 GEN_LOWERED_OP(AddC)
2284 GEN_LOWERED_OP(SubC)
2289 GEN_LOWERED_UNOP(Minus)
2292 * Transforms a l_MulS into a "real" MulS node.
2294 * @param env The transformation environment
2295 * @return the created ia32 MulS node
2297 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2299 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2300 /* and then skip the result Proj, because all needed Projs are already there. */
2302 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2303 return get_Proj_pred(new_op);
2306 GEN_LOWERED_SHIFT_OP(Shl)
2307 GEN_LOWERED_SHIFT_OP(Shr)
2308 GEN_LOWERED_SHIFT_OP(Shrs)
2311 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2312 * op1 - target to be shifted
2313 * op2 - contains bits to be shifted into target
2315 * Only op3 can be an immediate.
2317 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2318 ir_node *new_op = NULL;
2319 ir_mode *mode = env->mode;
2320 dbg_info *dbg = env->dbg;
2321 ir_graph *irg = env->irg;
2322 ir_node *block = env->block;
2323 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2324 ir_node *nomem = new_NoMem();
2327 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2329 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2331 /* Check if immediate optimization is on and */
2332 /* if it's an operation with immediate. */
2333 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2335 /* Limit imm_op within range imm8 */
2337 tv = get_ia32_Immop_tarval(imm_op);
2340 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2341 set_ia32_Immop_tarval(imm_op, tv);
2348 /* integer operations */
2350 /* This is ShiftD with const */
2351 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2353 if (is_ia32_l_ShlD(env->irn))
2354 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2356 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2357 set_ia32_Immop_attr(new_op, imm_op);
2360 /* This is a normal ShiftD */
2361 DB((mod, LEVEL_1, "ShiftD binop ..."));
2362 if (is_ia32_l_ShlD(env->irn))
2363 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2365 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2368 /* set AM support */
2369 set_ia32_am_support(new_op, ia32_am_Dest);
2371 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2373 set_ia32_res_mode(new_op, mode);
2374 set_ia32_emit_cl(new_op);
2376 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2379 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2380 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2383 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2384 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2389 /*********************************************************
2392 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2393 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2394 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2395 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2397 *********************************************************/
2400 * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
2401 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2403 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
2404 ia32_transform_env_t tenv;
2405 ir_node *in1, *in2, *noreg, *nomem, *res;
2406 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
2408 /* Return if AM node or not a Sub or xSub */
2409 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
2412 noreg = ia32_new_NoReg_gp(cg);
2413 nomem = new_rd_NoMem(cg->irg);
2414 in1 = get_irn_n(irn, 2);
2415 in2 = get_irn_n(irn, 3);
2416 in1_reg = arch_get_irn_register(cg->arch_env, in1);
2417 in2_reg = arch_get_irn_register(cg->arch_env, in2);
2418 out_reg = get_ia32_out_reg(irn, 0);
2420 tenv.block = get_nodes_block(irn);
2421 tenv.dbg = get_irn_dbg_info(irn);
2424 tenv.mode = get_ia32_res_mode(irn);
2426 DEBUG_ONLY(tenv.mod = cg->mod;)
2428 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
2429 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
2430 /* generate the neg src2 */
2431 res = gen_Minus_ex(&tenv, in2);
2432 arch_set_irn_register(cg->arch_env, res, in2_reg);
2434 /* add to schedule */
2435 sched_add_before(irn, res);
2437 /* generate the add */
2438 if (mode_is_float(tenv.mode)) {
2439 res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2440 set_ia32_am_support(res, ia32_am_Source);
2443 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
2444 set_ia32_am_support(res, ia32_am_Full);
2445 set_ia32_commutative(res);
2447 set_ia32_res_mode(res, tenv.mode);
2449 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
2451 slots = get_ia32_slots(res);
2454 /* add to schedule */
2455 sched_add_before(irn, res);
2457 /* remove the old sub */
2460 DBG_OPT_SUB2NEGADD(irn, res);
2462 /* exchange the add and the sub */
2468 * Transforms a LEA into an Add if possible
2469 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
2471 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
2472 ia32_am_flavour_t am_flav;
2474 ir_node *res = NULL;
2475 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
2478 ia32_transform_env_t tenv;
2479 const arch_register_t *out_reg, *base_reg, *index_reg;
2482 if (! is_ia32_Lea(irn))
2485 am_flav = get_ia32_am_flavour(irn);
2487 if (get_ia32_am_sc(irn))
2490 /* only some LEAs can be transformed to an Add */
2491 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
2494 noreg = ia32_new_NoReg_gp(cg);
2495 nomem = new_rd_NoMem(cg->irg);
2498 base = get_irn_n(irn, 0);
2499 index = get_irn_n(irn,1);
2501 offs = get_ia32_am_offs(irn);
2503 /* offset has a explicit sign -> we need to skip + */
2504 if (offs && offs[0] == '+')
2507 out_reg = arch_get_irn_register(cg->arch_env, irn);
2508 base_reg = arch_get_irn_register(cg->arch_env, base);
2509 index_reg = arch_get_irn_register(cg->arch_env, index);
2511 tenv.block = get_nodes_block(irn);
2512 tenv.dbg = get_irn_dbg_info(irn);
2515 DEBUG_ONLY(tenv.mod = cg->mod;)
2516 tenv.mode = get_irn_mode(irn);
2519 switch(get_ia32_am_flavour(irn)) {
2521 /* out register must be same as base register */
2522 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2528 /* out register must be same as base register */
2529 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2536 /* out register must be same as index register */
2537 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2544 /* out register must be same as one in register */
2545 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2549 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2554 /* in registers a different from out -> no Add possible */
2561 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
2562 arch_set_irn_register(cg->arch_env, res, out_reg);
2563 set_ia32_op_type(res, ia32_Normal);
2564 set_ia32_commutative(res);
2565 set_ia32_res_mode(res, tenv.mode);
2568 set_ia32_cnst(res, offs);
2569 set_ia32_immop_type(res, ia32_ImmConst);
2572 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2574 /* add Add to schedule */
2575 sched_add_before(irn, res);
2577 DBG_OPT_LEA2ADD(irn, res);
2579 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
2581 /* add result Proj to schedule */
2582 sched_add_before(irn, res);
2584 /* remove the old LEA */
2587 /* exchange the Add and the LEA */
2592 * the BAD transformer.
2594 static ir_node *bad_transform(ia32_transform_env_t *env) {
2595 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2601 * Enters all transform functions into the generic pointer
2603 void ia32_register_transformers(void) {
2604 ir_op *op_Max, *op_Min, *op_Mulh;
2606 /* first clear the generic function pointer for all ops */
2607 clear_irp_opcodes_generic_func();
2609 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2610 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2644 /* transform ops from intrinsic lowering */
2672 /* constant transformation happens earlier */
2696 /* set the register for all Unknown nodes */
2699 op_Max = get_op_Max();
2702 op_Min = get_op_Min();
2705 op_Mulh = get_op_Mulh();
2714 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2717 * Transforms the given firm node (and maybe some other related nodes)
2718 * into one or more assembler nodes.
2720 * @param node the firm node
2721 * @param env the debug module
2723 void ia32_transform_node(ir_node *node, void *env) {
2724 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2725 ir_op *op = get_irn_op(node);
2726 ir_node *asm_node = NULL;
2732 /* link arguments pointing to Unknown to the UNKNOWN Proj */
2733 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
2734 if (is_Unknown(get_irn_n(node, i)))
2735 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
2738 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
2739 if (op->ops.generic) {
2740 ia32_transform_env_t tenv;
2741 transform_func *transform = (transform_func *)op->ops.generic;
2743 tenv.block = get_nodes_block(node);
2744 tenv.dbg = get_irn_dbg_info(node);
2745 tenv.irg = current_ir_graph;
2747 tenv.mode = get_irn_mode(node);
2749 DEBUG_ONLY(tenv.mod = cg->mod;)
2751 asm_node = (*transform)(&tenv);
2754 /* exchange nodes if a new one was generated */
2756 exchange(node, asm_node);
2757 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2760 DB((cg->mod, LEVEL_1, "ignored\n"));
2765 * Transforms a psi condition.
2767 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
2770 /* if the mode is target mode, we have already seen this part of the tree */
2771 if (get_irn_mode(cond) == mode)
2774 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
2776 set_irn_mode(cond, mode);
2778 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
2779 ir_node *in = get_irn_n(cond, i);
2781 /* if in is a compare: transform into Set/xCmp */
2783 ir_node *new_op = NULL;
2784 ir_node *cmp = get_Proj_pred(in);
2785 ir_node *cmp_a = get_Cmp_left(cmp);
2786 ir_node *cmp_b = get_Cmp_right(cmp);
2787 dbg_info *dbg = get_irn_dbg_info(cmp);
2788 ir_graph *irg = get_irn_irg(cmp);
2789 ir_node *block = get_nodes_block(cmp);
2790 ir_node *noreg = ia32_new_NoReg_gp(cg);
2791 ir_node *nomem = new_rd_NoMem(irg);
2792 int pnc = get_Proj_proj(in);
2794 /* this is a compare */
2795 if (mode_is_float(mode)) {
2796 /* Psi is float, we need a floating point compare */
2800 if (! mode_is_float(get_irn_mode(cmp_a))) {
2801 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
2802 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
2806 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
2807 set_ia32_pncode(new_op, pnc);
2808 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
2817 ia32_transform_env_t tenv;
2818 construct_binop_func *set_func = NULL;
2820 if (mode_is_float(get_irn_mode(cmp_a))) {
2821 /* 1st case: compare operands are floats */
2826 set_func = new_rd_ia32_xCmpSet;
2830 set_func = new_rd_ia32_vfCmpSet;
2833 pnc &= 7; /* fp compare -> int compare */
2836 /* 2nd case: compare operand are integer too */
2837 set_func = new_rd_ia32_CmpSet;
2848 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
2849 set_ia32_pncode(get_Proj_pred(new_op), pnc);
2850 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
2853 /* the the new compare as in */
2854 set_irn_n(cond, i, new_op);
2857 /* another complex condition */
2858 transform_psi_cond(in, mode, cg);
2864 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
2865 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
2866 * compare, which causes the compare result to be stores in a register. The
2867 * "And"s and "Or"s are transformed later, we just have to set their mode right.
2869 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
2870 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
2871 ir_node *psi_sel, *new_cmp, *block;
2876 if (get_irn_opcode(node) != iro_Psi)
2879 psi_sel = get_Psi_cond(node, 0);
2881 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
2882 if (is_Proj(psi_sel))
2885 mode = get_irn_mode(node);
2887 transform_psi_cond(psi_sel, mode, cg);
2889 irg = get_irn_irg(node);
2890 block = get_nodes_block(node);
2892 /* we need to compare the evaluated condition tree with 0 */
2894 /* BEWARE: new_r_Const_long works for floating point as well */
2895 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
2896 /* transform the const */
2897 ia32_place_consts_set_modes(new_cmp, cg);
2898 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
2900 set_Psi_cond(node, 0, new_cmp);