2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 /****************************************************************************************************
129 * | | | | / _| | | (_)
130 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
131 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
132 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
133 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
135 ****************************************************************************************************/
137 static ir_node *try_create_Immediate(ir_node *node,
138 char immediate_constraint_type);
140 static ir_node *create_immediate_or_transform(ir_node *node,
141 char immediate_constraint_type);
143 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
144 dbg_info *dbgi, ir_node *block,
145 ir_node *op, ir_node *orig_node);
148 * Return true if a mode can be stored in the GP register set
150 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
151 if(mode == mode_fpcw)
153 if(get_mode_size_bits(mode) > 32)
155 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
159 * creates a unique ident by adding a number to a tag
161 * @param tag the tag string, must contain a %d if a number
164 static ident *unique_id(const char *tag)
166 static unsigned id = 0;
169 snprintf(str, sizeof(str), tag, ++id);
170 return new_id_from_str(str);
174 * Get a primitive type for a mode.
176 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
178 pmap_entry *e = pmap_find(types, mode);
183 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
184 res = new_type_primitive(new_id_from_str(buf), mode);
185 set_type_alignment_bytes(res, 16);
186 pmap_insert(types, mode, res);
194 * Get an atomic entity that is initialized with a tarval
196 static ir_entity *create_float_const_entity(ir_node *cnst)
198 ia32_isa_t *isa = env_cg->isa;
199 tarval *tv = get_Const_tarval(cnst);
200 pmap_entry *e = pmap_find(isa->tv_ent, tv);
205 ir_mode *mode = get_irn_mode(cnst);
206 ir_type *tp = get_Const_type(cnst);
207 if (tp == firm_unknown_type)
208 tp = get_prim_type(isa->types, mode);
210 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
212 set_entity_ld_ident(res, get_entity_ident(res));
213 set_entity_visibility(res, visibility_local);
214 set_entity_variability(res, variability_constant);
215 set_entity_allocation(res, allocation_static);
217 /* we create a new entity here: It's initialization must resist on the
219 rem = current_ir_graph;
220 current_ir_graph = get_const_code_irg();
221 set_atomic_ent_value(res, new_Const_type(tv, tp));
222 current_ir_graph = rem;
224 pmap_insert(isa->tv_ent, tv, res);
232 static int is_Const_0(ir_node *node) {
233 return is_Const(node) && is_Const_null(node);
236 static int is_Const_1(ir_node *node) {
237 return is_Const(node) && is_Const_one(node);
240 static int is_Const_Minus_1(ir_node *node) {
241 return is_Const(node) && is_Const_all_one(node);
245 * returns true if constant can be created with a simple float command
247 static int is_simple_x87_Const(ir_node *node)
249 tarval *tv = get_Const_tarval(node);
251 if(tarval_is_null(tv) || tarval_is_one(tv))
254 /* TODO: match all the other float constants */
259 * Transforms a Const.
261 static ir_node *gen_Const(ir_node *node) {
262 ir_graph *irg = current_ir_graph;
263 ir_node *old_block = get_nodes_block(node);
264 ir_node *block = be_transform_node(old_block);
265 dbg_info *dbgi = get_irn_dbg_info(node);
266 ir_mode *mode = get_irn_mode(node);
268 if (mode_is_float(mode)) {
270 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
271 ir_node *nomem = new_NoMem();
275 if (USE_SSE2(env_cg)) {
276 if (is_Const_null(node)) {
277 load = new_rd_ia32_xZero(dbgi, irg, block);
278 set_ia32_ls_mode(load, mode);
281 floatent = create_float_const_entity(node);
283 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
285 set_ia32_op_type(load, ia32_AddrModeS);
286 set_ia32_am_sc(load, floatent);
287 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
288 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
291 if (is_Const_null(node)) {
292 load = new_rd_ia32_vfldz(dbgi, irg, block);
294 } else if (is_Const_one(node)) {
295 load = new_rd_ia32_vfld1(dbgi, irg, block);
298 floatent = create_float_const_entity(node);
300 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
301 set_ia32_op_type(load, ia32_AddrModeS);
302 set_ia32_am_sc(load, floatent);
303 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
304 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
306 set_ia32_ls_mode(load, mode);
309 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
311 /* Const Nodes before the initial IncSP are a bad idea, because
312 * they could be spilled and we have no SP ready at that point yet.
313 * So add a dependency to the initial frame pointer calculation to
314 * avoid that situation.
316 if (get_irg_start_block(irg) == block) {
317 add_irn_dep(load, get_irg_frame(irg));
320 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
324 tarval *tv = get_Const_tarval(node);
327 tv = tarval_convert_to(tv, mode_Iu);
329 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
331 panic("couldn't convert constant tarval (%+F)", node);
333 val = get_tarval_long(tv);
335 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
339 if (get_irg_start_block(irg) == block) {
340 add_irn_dep(cnst, get_irg_frame(irg));
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = current_ir_graph;
352 ir_node *old_block = get_nodes_block(node);
353 ir_node *block = be_transform_node(old_block);
354 dbg_info *dbgi = get_irn_dbg_info(node);
355 ir_mode *mode = get_irn_mode(node);
358 if (mode_is_float(mode)) {
359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
360 ir_node *nomem = new_NoMem();
362 if (USE_SSE2(env_cg))
363 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
365 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
366 set_ia32_am_sc(cnst, get_SymConst_entity(node));
367 set_ia32_use_frame(cnst);
371 if(get_SymConst_kind(node) != symconst_addr_ent) {
372 panic("backend only support symconst_addr_ent (at %+F)", node);
374 entity = get_SymConst_entity(node);
375 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
378 /* Const Nodes before the initial IncSP are a bad idea, because
379 * they could be spilled and we have no SP ready at that point yet
381 if (get_irg_start_block(irg) == block) {
382 add_irn_dep(cnst, get_irg_frame(irg));
385 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
390 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
391 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
392 static const struct {
394 const char *ent_name;
395 const char *cnst_str;
398 } names [ia32_known_const_max] = {
399 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
400 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
401 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
402 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
403 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
405 static ir_entity *ent_cache[ia32_known_const_max];
407 const char *tp_name, *ent_name, *cnst_str;
415 ent_name = names[kct].ent_name;
416 if (! ent_cache[kct]) {
417 tp_name = names[kct].tp_name;
418 cnst_str = names[kct].cnst_str;
420 switch (names[kct].mode) {
421 case 0: mode = mode_Iu; break;
422 case 1: mode = mode_Lu; break;
423 default: mode = mode_F; break;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 /* set the specified alignment */
428 set_type_alignment_bytes(tp, names[kct].align);
430 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
432 set_entity_ld_ident(ent, get_entity_ident(ent));
433 set_entity_visibility(ent, visibility_local);
434 set_entity_variability(ent, variability_constant);
435 set_entity_allocation(ent, allocation_static);
437 /* we create a new entity here: It's initialization must resist on the
439 rem = current_ir_graph;
440 current_ir_graph = get_const_code_irg();
441 cnst = new_Const(mode, tv);
442 current_ir_graph = rem;
444 set_atomic_ent_value(ent, cnst);
446 /* cache the entry */
447 ent_cache[kct] = ent;
450 return ent_cache[kct];
455 * Prints the old node name on cg obst and returns a pointer to it.
457 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
458 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
460 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
461 obstack_1grow(isa->name_obst, 0);
462 return obstack_finish(isa->name_obst);
466 int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
468 ir_mode *mode = get_irn_mode(node);
472 /* float constants are always available */
473 if(is_Const(node) && mode_is_float(mode)) {
474 if(!is_simple_x87_Const(node))
476 if(get_irn_n_edges(node) > 1)
483 load = get_Proj_pred(node);
484 pn = get_Proj_proj(node);
485 if(!is_Load(load) || pn != pn_Load_res)
487 if(get_nodes_block(load) != block)
489 /* we only use address mode if we're the only user of the load */
490 if(get_irn_n_edges(node) > 1)
492 /* in some edge cases with address mode we might reach the load normally
493 * and through some AM sequence, if it is already materialized then we
494 * can't create an AM node from it */
495 if(be_is_transformed(node))
498 /* don't do AM if other node inputs depend on the load (via mem-proj) */
499 if(other != NULL && get_nodes_block(other) == block
500 && heights_reachable_in_block(heights, other, load))
506 typedef struct ia32_address_mode_t ia32_address_mode_t;
507 struct ia32_address_mode_t {
511 ia32_op_type_t op_type;
515 unsigned commutative : 1;
516 unsigned ins_permuted : 1;
519 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
523 /* construct load address */
524 memset(addr, 0, sizeof(addr[0]));
525 ia32_create_address_mode(addr, ptr, /*force=*/0);
527 if(addr->base == NULL) {
528 addr->base = noreg_gp;
530 addr->base = be_transform_node(addr->base);
533 if(addr->index == NULL) {
534 addr->index = noreg_gp;
536 addr->index = be_transform_node(addr->index);
538 addr->mem = be_transform_node(mem);
541 static void build_address(ia32_address_mode_t *am, ir_node *node)
543 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
544 ia32_address_t *addr = &am->addr;
553 ir_entity *entity = create_float_const_entity(node);
554 addr->base = noreg_gp;
555 addr->index = noreg_gp;
556 addr->mem = new_NoMem();
557 addr->symconst_ent = entity;
559 am->ls_mode = get_irn_mode(node);
560 am->pinned = op_pin_state_floats;
564 load = get_Proj_pred(node);
565 ptr = get_Load_ptr(load);
566 mem = get_Load_mem(load);
567 new_mem = be_transform_node(mem);
568 am->pinned = get_irn_pinned(load);
569 am->ls_mode = get_Load_mode(load);
570 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
572 /* construct load address */
573 ia32_create_address_mode(addr, ptr, /*force=*/0);
580 base = be_transform_node(base);
586 index = be_transform_node(index);
594 static void set_address(ir_node *node, const ia32_address_t *addr)
596 set_ia32_am_scale(node, addr->scale);
597 set_ia32_am_sc(node, addr->symconst_ent);
598 set_ia32_am_offs_int(node, addr->offset);
599 if(addr->symconst_sign)
600 set_ia32_am_sc_sign(node);
602 set_ia32_use_frame(node);
603 set_ia32_frame_ent(node, addr->frame_entity);
606 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
608 set_address(node, &am->addr);
610 set_ia32_op_type(node, am->op_type);
611 set_ia32_ls_mode(node, am->ls_mode);
612 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
613 set_irn_pinned(node, am->pinned);
616 set_ia32_commutative(node);
620 * Check, if a given node is a Down-Conv, ie. a integer Conv
621 * from a mode with a mode with more bits to a mode with lesser bits.
622 * Moreover, we return only true if the node has not more than 1 user.
624 * @param node the node
625 * @return non-zero if node is a Down-Conv
627 static int is_downconv(const ir_node *node)
635 /* we only want to skip the conv when we're the only user
636 * (not optimal but for now...)
638 if(get_irn_n_edges(node) > 1)
641 src_mode = get_irn_mode(get_Conv_op(node));
642 dest_mode = get_irn_mode(node);
643 return mode_needs_gp_reg(src_mode)
644 && mode_needs_gp_reg(dest_mode)
645 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
648 /* Skip all Down-Conv's on a given node and return the resulting node. */
649 ir_node *ia32_skip_downconv(ir_node *node) {
650 while (is_downconv(node))
651 node = get_Conv_op(node);
657 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
659 ir_mode *mode = get_irn_mode(node);
664 if(mode_is_signed(mode)) {
669 block = get_nodes_block(node);
670 dbgi = get_irn_dbg_info(node);
672 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
676 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
677 ir_node *op1, ir_node *op2, match_flags_t flags)
679 ia32_address_t *addr = &am->addr;
680 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
683 ir_mode *mode = get_irn_mode(op2);
685 unsigned commutative;
686 int use_am_and_immediates;
688 int mode_bits = get_mode_size_bits(mode);
690 memset(am, 0, sizeof(am[0]));
692 commutative = (flags & match_commutative) != 0;
693 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
694 use_am = (flags & match_am) != 0;
695 use_immediate = (flags & match_immediate) != 0;
696 assert(!use_am_and_immediates || use_immediate);
699 assert(!commutative || op1 != NULL);
700 assert(use_am || !(flags & match_8bit_am));
701 assert(use_am || !(flags & match_16bit_am));
704 if (! (flags & match_8bit_am))
706 assert((flags & match_mode_neutral) || (flags & match_8bit));
707 } else if(mode_bits == 16) {
708 if(! (flags & match_16bit_am))
710 assert((flags & match_mode_neutral) || (flags & match_16bit));
713 /* we can simply skip downconvs for mode neutral nodes: the upper bits
714 * can be random for these operations */
715 if(flags & match_mode_neutral) {
716 op2 = ia32_skip_downconv(op2);
718 op1 = ia32_skip_downconv(op1);
722 if(! (flags & match_try_am) && use_immediate)
723 new_op2 = try_create_Immediate(op2, 0);
727 if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
728 build_address(am, op2);
729 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
730 if(mode_is_float(mode)) {
731 new_op2 = ia32_new_NoReg_vfp(env_cg);
735 am->op_type = ia32_AddrModeS;
736 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
737 use_am && ia32_use_source_address_mode(block, op1, op2)) {
739 build_address(am, op1);
741 if(mode_is_float(mode)) {
742 noreg = ia32_new_NoReg_vfp(env_cg);
747 if(new_op2 != NULL) {
750 new_op1 = be_transform_node(op2);
752 am->ins_permuted = 1;
754 am->op_type = ia32_AddrModeS;
756 if(flags & match_try_am) {
759 am->op_type = ia32_Normal;
763 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
765 new_op2 = be_transform_node(op2);
766 am->op_type = ia32_Normal;
767 am->ls_mode = get_irn_mode(op2);
768 if(flags & match_mode_neutral)
769 am->ls_mode = mode_Iu;
771 if(addr->base == NULL)
772 addr->base = noreg_gp;
773 if(addr->index == NULL)
774 addr->index = noreg_gp;
775 if(addr->mem == NULL)
776 addr->mem = new_NoMem();
778 am->new_op1 = new_op1;
779 am->new_op2 = new_op2;
780 am->commutative = commutative;
783 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
785 ir_graph *irg = current_ir_graph;
789 if(am->mem_proj == NULL)
792 /* we have to create a mode_T so the old MemProj can attach to us */
793 mode = get_irn_mode(node);
794 load = get_Proj_pred(am->mem_proj);
796 mark_irn_visited(load);
797 be_set_transformed_node(load, node);
800 set_irn_mode(node, mode_T);
801 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
808 * Construct a standard binary operation, set AM and immediate if required.
810 * @param op1 The first operand
811 * @param op2 The second operand
812 * @param func The node constructor function
813 * @return The constructed ia32 node.
815 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
816 construct_binop_func *func, match_flags_t flags)
818 ir_node *block = get_nodes_block(node);
819 ir_node *new_block = be_transform_node(block);
820 ir_graph *irg = current_ir_graph;
821 dbg_info *dbgi = get_irn_dbg_info(node);
823 ia32_address_mode_t am;
824 ia32_address_t *addr = &am.addr;
826 match_arguments(&am, block, op1, op2, flags);
828 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
829 am.new_op1, am.new_op2);
830 set_am_attributes(new_node, &am);
831 /* we can't use source address mode anymore when using immediates */
832 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
833 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
834 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
836 new_node = fix_mem_proj(new_node, &am);
843 n_ia32_l_binop_right,
844 n_ia32_l_binop_eflags
846 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
847 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
848 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
849 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
850 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
851 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
854 * Construct a binary operation which also consumes the eflags.
856 * @param node The node to transform
857 * @param func The node constructor function
858 * @param flags The match flags
859 * @return The constructor ia32 node
861 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
864 ir_node *src_block = get_nodes_block(node);
865 ir_node *block = be_transform_node(src_block);
866 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
867 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
868 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
869 ir_node *new_eflags = be_transform_node(eflags);
870 ir_graph *irg = current_ir_graph;
871 dbg_info *dbgi = get_irn_dbg_info(node);
873 ia32_address_mode_t am;
874 ia32_address_t *addr = &am.addr;
876 match_arguments(&am, src_block, op1, op2, flags);
878 new_node = func(dbgi, irg, block, addr->base, addr->index,
879 addr->mem, am.new_op1, am.new_op2, new_eflags);
880 set_am_attributes(new_node, &am);
881 /* we can't use source address mode anymore when using immediates */
882 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
883 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
884 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
886 new_node = fix_mem_proj(new_node, &am);
891 static ir_node *get_fpcw(void)
894 if(initial_fpcw != NULL)
897 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
898 &ia32_fp_cw_regs[REG_FPCW]);
899 initial_fpcw = be_transform_node(fpcw);
905 * Construct a standard binary operation, set AM and immediate if required.
907 * @param op1 The first operand
908 * @param op2 The second operand
909 * @param func The node constructor function
910 * @return The constructed ia32 node.
912 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
913 construct_binop_float_func *func,
916 ir_graph *irg = current_ir_graph;
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_node *block = get_nodes_block(node);
919 ir_node *new_block = be_transform_node(block);
920 ir_mode *mode = get_irn_mode(node);
922 ia32_address_mode_t am;
923 ia32_address_t *addr = &am.addr;
925 /* cannot use addresmode with long double on x87 */
926 if (get_mode_size_bits(mode) > 64) flags &= ~match_am;
928 match_arguments(&am, block, op1, op2, flags);
930 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
931 am.new_op1, am.new_op2, get_fpcw());
932 set_am_attributes(new_node, &am);
934 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
936 new_node = fix_mem_proj(new_node, &am);
942 * Construct a shift/rotate binary operation, sets AM and immediate if required.
944 * @param op1 The first operand
945 * @param op2 The second operand
946 * @param func The node constructor function
947 * @return The constructed ia32 node.
949 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
950 construct_shift_func *func,
953 dbg_info *dbgi = get_irn_dbg_info(node);
954 ir_graph *irg = current_ir_graph;
955 ir_node *block = get_nodes_block(node);
956 ir_node *new_block = be_transform_node(block);
957 ir_mode *mode = get_irn_mode(node);
962 assert(! mode_is_float(mode));
963 assert(flags & match_immediate);
964 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
966 if(flags & match_mode_neutral) {
967 op1 = ia32_skip_downconv(op1);
969 new_op1 = be_transform_node(op1);
971 /* the shift amount can be any mode that is bigger than 5 bits, since all
972 * other bits are ignored anyway */
973 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
974 op2 = get_Conv_op(op2);
975 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
977 new_op2 = create_immediate_or_transform(op2, 0);
979 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
980 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
982 /* lowered shift instruction may have a dependency operand, handle it here */
983 if (get_irn_arity(node) == 3) {
984 /* we have a dependency */
985 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
986 add_irn_dep(new_node, new_dep);
994 * Construct a standard unary operation, set AM and immediate if required.
996 * @param op The operand
997 * @param func The node constructor function
998 * @return The constructed ia32 node.
1000 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1001 match_flags_t flags)
1003 ir_graph *irg = current_ir_graph;
1004 dbg_info *dbgi = get_irn_dbg_info(node);
1005 ir_node *block = get_nodes_block(node);
1006 ir_node *new_block = be_transform_node(block);
1010 assert(flags == 0 || flags == match_mode_neutral);
1011 if(flags & match_mode_neutral) {
1012 op = ia32_skip_downconv(op);
1015 new_op = be_transform_node(op);
1016 new_node = func(dbgi, irg, new_block, new_op);
1018 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1023 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1024 ia32_address_t *addr)
1026 ir_graph *irg = current_ir_graph;
1027 ir_node *base = addr->base;
1028 ir_node *index = addr->index;
1032 base = ia32_new_NoReg_gp(env_cg);
1034 base = be_transform_node(base);
1038 index = ia32_new_NoReg_gp(env_cg);
1040 index = be_transform_node(index);
1043 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1044 set_address(res, addr);
1049 static int am_has_immediates(const ia32_address_t *addr)
1051 return addr->offset != 0 || addr->symconst_ent != NULL
1052 || addr->frame_entity || addr->use_frame;
1056 * Creates an ia32 Add.
1058 * @return the created ia32 Add node
1060 static ir_node *gen_Add(ir_node *node) {
1061 ir_graph *irg = current_ir_graph;
1062 dbg_info *dbgi = get_irn_dbg_info(node);
1063 ir_node *block = get_nodes_block(node);
1064 ir_node *new_block = be_transform_node(block);
1065 ir_node *op1 = get_Add_left(node);
1066 ir_node *op2 = get_Add_right(node);
1067 ir_mode *mode = get_irn_mode(node);
1069 ir_node *add_immediate_op;
1070 ia32_address_t addr;
1071 ia32_address_mode_t am;
1073 if (mode_is_float(mode)) {
1074 if (USE_SSE2(env_cg))
1075 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1076 match_commutative | match_am);
1078 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1079 match_commutative | match_am);
1082 ia32_mark_non_am(node);
1084 op2 = ia32_skip_downconv(op2);
1085 op1 = ia32_skip_downconv(op1);
1089 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1090 * 1. Add with immediate -> Lea
1091 * 2. Add with possible source address mode -> Add
1092 * 3. Otherwise -> Lea
1094 memset(&addr, 0, sizeof(addr));
1095 ia32_create_address_mode(&addr, node, /*force=*/1);
1096 add_immediate_op = NULL;
1098 if(addr.base == NULL && addr.index == NULL) {
1099 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1100 addr.symconst_sign, addr.offset);
1101 add_irn_dep(new_node, get_irg_frame(irg));
1102 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1105 /* add with immediate? */
1106 if(addr.index == NULL) {
1107 add_immediate_op = addr.base;
1108 } else if(addr.base == NULL && addr.scale == 0) {
1109 add_immediate_op = addr.index;
1112 if(add_immediate_op != NULL) {
1113 if(!am_has_immediates(&addr)) {
1114 #ifdef DEBUG_libfirm
1115 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1118 return be_transform_node(add_immediate_op);
1121 new_node = create_lea_from_address(dbgi, new_block, &addr);
1122 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1126 /* test if we can use source address mode */
1127 match_arguments(&am, block, op1, op2, match_commutative
1128 | match_mode_neutral | match_am | match_immediate | match_try_am);
1130 /* construct an Add with source address mode */
1131 if (am.op_type == ia32_AddrModeS) {
1132 ia32_address_t *am_addr = &am.addr;
1133 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1134 am_addr->index, am_addr->mem, am.new_op1,
1136 set_am_attributes(new_node, &am);
1137 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1139 new_node = fix_mem_proj(new_node, &am);
1144 /* otherwise construct a lea */
1145 new_node = create_lea_from_address(dbgi, new_block, &addr);
1146 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1151 * Creates an ia32 Mul.
1153 * @return the created ia32 Mul node
1155 static ir_node *gen_Mul(ir_node *node) {
1156 ir_node *op1 = get_Mul_left(node);
1157 ir_node *op2 = get_Mul_right(node);
1158 ir_mode *mode = get_irn_mode(node);
1160 if (mode_is_float(mode)) {
1161 if (USE_SSE2(env_cg))
1162 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1163 match_commutative | match_am);
1165 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1166 match_commutative | match_am);
1170 for the lower 32bit of the result it doesn't matter whether we use
1171 signed or unsigned multiplication so we use IMul as it has fewer
1174 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1175 match_commutative | match_am | match_mode_neutral |
1176 match_immediate | match_am_and_immediates);
1180 * Creates an ia32 Mulh.
1181 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1182 * this result while Mul returns the lower 32 bit.
1184 * @return the created ia32 Mulh node
1186 static ir_node *gen_Mulh(ir_node *node)
1188 ir_node *block = get_nodes_block(node);
1189 ir_node *new_block = be_transform_node(block);
1190 ir_graph *irg = current_ir_graph;
1191 dbg_info *dbgi = get_irn_dbg_info(node);
1192 ir_mode *mode = get_irn_mode(node);
1193 ir_node *op1 = get_Mulh_left(node);
1194 ir_node *op2 = get_Mulh_right(node);
1197 match_flags_t flags;
1198 ia32_address_mode_t am;
1199 ia32_address_t *addr = &am.addr;
1201 flags = match_commutative | match_am;
1203 assert(!mode_is_float(mode) && "Mulh with float not supported");
1204 assert(get_mode_size_bits(mode) == 32);
1206 match_arguments(&am, block, op1, op2, flags);
1208 if (mode_is_signed(mode)) {
1209 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1210 addr->index, addr->mem, am.new_op1,
1213 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1214 addr->index, addr->mem, am.new_op1,
1218 set_am_attributes(new_node, &am);
1219 /* we can't use source address mode anymore when using immediates */
1220 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1221 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1222 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1224 assert(get_irn_mode(new_node) == mode_T);
1226 fix_mem_proj(new_node, &am);
1228 assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
1229 proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
1230 mode_Iu, pn_ia32_IMul1OP_EDX);
1238 * Creates an ia32 And.
1240 * @return The created ia32 And node
1242 static ir_node *gen_And(ir_node *node) {
1243 ir_node *op1 = get_And_left(node);
1244 ir_node *op2 = get_And_right(node);
1245 assert(! mode_is_float(get_irn_mode(node)));
1247 /* is it a zero extension? */
1248 if (is_Const(op2)) {
1249 tarval *tv = get_Const_tarval(op2);
1250 long v = get_tarval_long(tv);
1252 if (v == 0xFF || v == 0xFFFF) {
1253 dbg_info *dbgi = get_irn_dbg_info(node);
1254 ir_node *block = get_nodes_block(node);
1261 assert(v == 0xFFFF);
1264 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1270 return gen_binop(node, op1, op2, new_rd_ia32_And,
1271 match_commutative | match_mode_neutral | match_am
1278 * Creates an ia32 Or.
1280 * @return The created ia32 Or node
1282 static ir_node *gen_Or(ir_node *node) {
1283 ir_node *op1 = get_Or_left(node);
1284 ir_node *op2 = get_Or_right(node);
1286 assert (! mode_is_float(get_irn_mode(node)));
1287 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1288 | match_mode_neutral | match_am | match_immediate);
1294 * Creates an ia32 Eor.
1296 * @return The created ia32 Eor node
1298 static ir_node *gen_Eor(ir_node *node) {
1299 ir_node *op1 = get_Eor_left(node);
1300 ir_node *op2 = get_Eor_right(node);
1302 assert(! mode_is_float(get_irn_mode(node)));
1303 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1304 | match_mode_neutral | match_am | match_immediate);
1309 * Creates an ia32 Sub.
1311 * @return The created ia32 Sub node
1313 static ir_node *gen_Sub(ir_node *node) {
1314 ir_node *op1 = get_Sub_left(node);
1315 ir_node *op2 = get_Sub_right(node);
1316 ir_mode *mode = get_irn_mode(node);
1318 if (mode_is_float(mode)) {
1319 if (USE_SSE2(env_cg))
1320 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1322 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1327 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1331 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1332 | match_am | match_immediate);
1336 * Generates an ia32 DivMod with additional infrastructure for the
1337 * register allocator if needed.
1339 static ir_node *create_Div(ir_node *node)
1341 ir_graph *irg = current_ir_graph;
1342 dbg_info *dbgi = get_irn_dbg_info(node);
1343 ir_node *block = get_nodes_block(node);
1344 ir_node *new_block = be_transform_node(block);
1351 ir_node *sign_extension;
1353 ia32_address_mode_t am;
1354 ia32_address_t *addr = &am.addr;
1356 /* the upper bits have random contents for smaller modes */
1358 switch (get_irn_opcode(node)) {
1360 op1 = get_Div_left(node);
1361 op2 = get_Div_right(node);
1362 mem = get_Div_mem(node);
1363 mode = get_Div_resmode(node);
1364 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1367 op1 = get_Mod_left(node);
1368 op2 = get_Mod_right(node);
1369 mem = get_Mod_mem(node);
1370 mode = get_Mod_resmode(node);
1371 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1374 op1 = get_DivMod_left(node);
1375 op2 = get_DivMod_right(node);
1376 mem = get_DivMod_mem(node);
1377 mode = get_DivMod_resmode(node);
1378 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1381 panic("invalid divmod node %+F", node);
1384 match_arguments(&am, block, op1, op2, match_am);
1386 if(!is_NoMem(mem)) {
1387 new_mem = be_transform_node(mem);
1388 if(!is_NoMem(addr->mem)) {
1392 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1395 new_mem = addr->mem;
1398 if (mode_is_signed(mode)) {
1399 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1400 add_irn_dep(produceval, get_irg_frame(irg));
1401 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1404 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1405 addr->index, new_mem, am.new_op1,
1406 sign_extension, am.new_op2);
1408 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1409 add_irn_dep(sign_extension, get_irg_frame(irg));
1411 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1412 addr->index, new_mem, am.new_op1,
1413 sign_extension, am.new_op2);
1416 set_ia32_exc_label(new_node, has_exc);
1417 set_irn_pinned(new_node, get_irn_pinned(node));
1419 set_am_attributes(new_node, &am);
1420 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1422 new_node = fix_mem_proj(new_node, &am);
1428 static ir_node *gen_Mod(ir_node *node) {
1429 return create_Div(node);
1432 static ir_node *gen_Div(ir_node *node) {
1433 return create_Div(node);
1436 static ir_node *gen_DivMod(ir_node *node) {
1437 return create_Div(node);
1443 * Creates an ia32 floating Div.
1445 * @return The created ia32 xDiv node
1447 static ir_node *gen_Quot(ir_node *node)
1449 ir_node *op1 = get_Quot_left(node);
1450 ir_node *op2 = get_Quot_right(node);
1452 if (USE_SSE2(env_cg)) {
1453 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1455 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1461 * Creates an ia32 Shl.
1463 * @return The created ia32 Shl node
1465 static ir_node *gen_Shl(ir_node *node) {
1466 ir_node *left = get_Shl_left(node);
1467 ir_node *right = get_Shl_right(node);
1469 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1470 match_mode_neutral | match_immediate);
1474 * Creates an ia32 Shr.
1476 * @return The created ia32 Shr node
1478 static ir_node *gen_Shr(ir_node *node) {
1479 ir_node *left = get_Shr_left(node);
1480 ir_node *right = get_Shr_right(node);
1482 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1488 * Creates an ia32 Sar.
1490 * @return The created ia32 Shrs node
1492 static ir_node *gen_Shrs(ir_node *node) {
1493 ir_node *left = get_Shrs_left(node);
1494 ir_node *right = get_Shrs_right(node);
1495 ir_mode *mode = get_irn_mode(node);
1497 if(is_Const(right) && mode == mode_Is) {
1498 tarval *tv = get_Const_tarval(right);
1499 long val = get_tarval_long(tv);
1501 /* this is a sign extension */
1502 ir_graph *irg = current_ir_graph;
1503 dbg_info *dbgi = get_irn_dbg_info(node);
1504 ir_node *block = be_transform_node(get_nodes_block(node));
1506 ir_node *new_op = be_transform_node(op);
1507 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1508 add_irn_dep(pval, get_irg_frame(irg));
1510 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1514 /* 8 or 16 bit sign extension? */
1515 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1516 ir_node *shl_left = get_Shl_left(left);
1517 ir_node *shl_right = get_Shl_right(left);
1518 if(is_Const(shl_right)) {
1519 tarval *tv1 = get_Const_tarval(right);
1520 tarval *tv2 = get_Const_tarval(shl_right);
1521 if(tv1 == tv2 && tarval_is_long(tv1)) {
1522 long val = get_tarval_long(tv1);
1523 if(val == 16 || val == 24) {
1524 dbg_info *dbgi = get_irn_dbg_info(node);
1525 ir_node *block = get_nodes_block(node);
1535 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1544 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1550 * Creates an ia32 RotL.
1552 * @param op1 The first operator
1553 * @param op2 The second operator
1554 * @return The created ia32 RotL node
1556 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1557 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1563 * Creates an ia32 RotR.
1564 * NOTE: There is no RotR with immediate because this would always be a RotL
1565 * "imm-mode_size_bits" which can be pre-calculated.
1567 * @param op1 The first operator
1568 * @param op2 The second operator
1569 * @return The created ia32 RotR node
1571 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1572 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1578 * Creates an ia32 RotR or RotL (depending on the found pattern).
1580 * @return The created ia32 RotL or RotR node
1582 static ir_node *gen_Rot(ir_node *node) {
1583 ir_node *rotate = NULL;
1584 ir_node *op1 = get_Rot_left(node);
1585 ir_node *op2 = get_Rot_right(node);
1587 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1588 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1589 that means we can create a RotR instead of an Add and a RotL */
1591 if (get_irn_op(op2) == op_Add) {
1593 ir_node *left = get_Add_left(add);
1594 ir_node *right = get_Add_right(add);
1595 if (is_Const(right)) {
1596 tarval *tv = get_Const_tarval(right);
1597 ir_mode *mode = get_irn_mode(node);
1598 long bits = get_mode_size_bits(mode);
1600 if (get_irn_op(left) == op_Minus &&
1601 tarval_is_long(tv) &&
1602 get_tarval_long(tv) == bits &&
1605 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1606 rotate = gen_RotR(node, op1, get_Minus_op(left));
1611 if (rotate == NULL) {
1612 rotate = gen_RotL(node, op1, op2);
1621 * Transforms a Minus node.
1623 * @return The created ia32 Minus node
1625 static ir_node *gen_Minus(ir_node *node)
1627 ir_node *op = get_Minus_op(node);
1628 ir_node *block = be_transform_node(get_nodes_block(node));
1629 ir_graph *irg = current_ir_graph;
1630 dbg_info *dbgi = get_irn_dbg_info(node);
1631 ir_mode *mode = get_irn_mode(node);
1636 if (mode_is_float(mode)) {
1637 ir_node *new_op = be_transform_node(op);
1638 if (USE_SSE2(env_cg)) {
1639 /* TODO: non-optimal... if we have many xXors, then we should
1640 * rather create a load for the const and use that instead of
1641 * several AM nodes... */
1642 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1643 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1644 ir_node *nomem = new_rd_NoMem(irg);
1646 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1647 nomem, new_op, noreg_xmm);
1649 size = get_mode_size_bits(mode);
1650 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1652 set_ia32_am_sc(new_node, ent);
1653 set_ia32_op_type(new_node, ia32_AddrModeS);
1654 set_ia32_ls_mode(new_node, mode);
1656 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1659 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1662 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1668 * Transforms a Not node.
1670 * @return The created ia32 Not node
1672 static ir_node *gen_Not(ir_node *node) {
1673 ir_node *op = get_Not_op(node);
1675 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1676 assert (! mode_is_float(get_irn_mode(node)));
1678 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1684 * Transforms an Abs node.
1686 * @return The created ia32 Abs node
1688 static ir_node *gen_Abs(ir_node *node)
1690 ir_node *block = get_nodes_block(node);
1691 ir_node *new_block = be_transform_node(block);
1692 ir_node *op = get_Abs_op(node);
1693 ir_graph *irg = current_ir_graph;
1694 dbg_info *dbgi = get_irn_dbg_info(node);
1695 ir_mode *mode = get_irn_mode(node);
1696 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1697 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1698 ir_node *nomem = new_NoMem();
1704 if (mode_is_float(mode)) {
1705 new_op = be_transform_node(op);
1707 if (USE_SSE2(env_cg)) {
1708 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1709 nomem, new_op, noreg_fp);
1711 size = get_mode_size_bits(mode);
1712 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1714 set_ia32_am_sc(new_node, ent);
1716 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1718 set_ia32_op_type(new_node, ia32_AddrModeS);
1719 set_ia32_ls_mode(new_node, mode);
1721 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1722 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1725 if (get_mode_size_bits(mode) == 32) {
1726 new_op = be_transform_node(op);
1728 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1732 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1733 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1736 add_irn_dep(pval, get_irg_frame(irg));
1737 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1739 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1740 nomem, new_op, sign_extension);
1741 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1743 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1744 nomem, xor, sign_extension);
1745 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1751 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1753 ir_graph *irg = current_ir_graph;
1761 /* we have a Cmp as input */
1763 ir_node *pred = get_Proj_pred(node);
1765 flags = be_transform_node(pred);
1766 *pnc_out = get_Proj_proj(node);
1771 /* a mode_b value, we have to compare it against 0 */
1772 dbgi = get_irn_dbg_info(node);
1773 new_block = be_transform_node(get_nodes_block(node));
1774 new_op = be_transform_node(node);
1775 noreg = ia32_new_NoReg_gp(env_cg);
1776 nomem = new_NoMem();
1777 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1778 new_op, new_op, 0, 0);
1779 *pnc_out = pn_Cmp_Lg;
1784 * Transforms a Load.
1786 * @return the created ia32 Load node
1788 static ir_node *gen_Load(ir_node *node) {
1789 ir_node *old_block = get_nodes_block(node);
1790 ir_node *block = be_transform_node(old_block);
1791 ir_node *ptr = get_Load_ptr(node);
1792 ir_node *mem = get_Load_mem(node);
1793 ir_node *new_mem = be_transform_node(mem);
1796 ir_graph *irg = current_ir_graph;
1797 dbg_info *dbgi = get_irn_dbg_info(node);
1798 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1799 ir_mode *mode = get_Load_mode(node);
1802 ia32_address_t addr;
1804 /* construct load address */
1805 memset(&addr, 0, sizeof(addr));
1806 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1813 base = be_transform_node(base);
1819 index = be_transform_node(index);
1822 if (mode_is_float(mode)) {
1823 if (USE_SSE2(env_cg)) {
1824 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1826 res_mode = mode_xmm;
1828 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1830 res_mode = mode_vfp;
1833 assert(mode != mode_b);
1835 /* create a conv node with address mode for smaller modes */
1836 if(get_mode_size_bits(mode) < 32) {
1837 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1838 new_mem, noreg, mode);
1840 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1845 set_irn_pinned(new_node, get_irn_pinned(node));
1846 set_ia32_op_type(new_node, ia32_AddrModeS);
1847 set_ia32_ls_mode(new_node, mode);
1848 set_address(new_node, &addr);
1850 if(get_irn_pinned(node) == op_pin_state_floats) {
1851 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1854 /* make sure we are scheduled behind the initial IncSP/Barrier
1855 * to avoid spills being placed before it
1857 if (block == get_irg_start_block(irg)) {
1858 add_irn_dep(new_node, get_irg_frame(irg));
1861 set_ia32_exc_label(new_node,
1862 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1863 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1868 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1869 ir_node *ptr, ir_node *other)
1876 /* we only use address mode if we're the only user of the load */
1877 if(get_irn_n_edges(node) > 1)
1880 load = get_Proj_pred(node);
1883 if(get_nodes_block(load) != block)
1886 /* Store should be attached to the load */
1887 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1889 /* store should have the same pointer as the load */
1890 if(get_Load_ptr(load) != ptr)
1893 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1894 if(other != NULL && get_nodes_block(other) == block
1895 && heights_reachable_in_block(heights, other, load))
1901 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1902 ir_node *mem, ir_node *ptr, ir_mode *mode,
1903 construct_binop_dest_func *func,
1904 construct_binop_dest_func *func8bit,
1905 match_flags_t flags)
1907 ir_node *src_block = get_nodes_block(node);
1909 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1910 ir_graph *irg = current_ir_graph;
1915 ia32_address_mode_t am;
1916 ia32_address_t *addr = &am.addr;
1917 memset(&am, 0, sizeof(am));
1919 assert(flags & match_dest_am);
1920 assert(flags & match_immediate); /* there is no destam node without... */
1921 commutative = (flags & match_commutative) != 0;
1923 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1924 build_address(&am, op1);
1925 new_op = create_immediate_or_transform(op2, 0);
1926 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1927 build_address(&am, op2);
1928 new_op = create_immediate_or_transform(op1, 0);
1933 if(addr->base == NULL)
1934 addr->base = noreg_gp;
1935 if(addr->index == NULL)
1936 addr->index = noreg_gp;
1937 if(addr->mem == NULL)
1938 addr->mem = new_NoMem();
1940 dbgi = get_irn_dbg_info(node);
1941 block = be_transform_node(src_block);
1942 if(get_mode_size_bits(mode) == 8) {
1943 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1946 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1949 set_address(new_node, addr);
1950 set_ia32_op_type(new_node, ia32_AddrModeD);
1951 set_ia32_ls_mode(new_node, mode);
1952 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1957 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1958 ir_node *ptr, ir_mode *mode,
1959 construct_unop_dest_func *func)
1961 ir_graph *irg = current_ir_graph;
1962 ir_node *src_block = get_nodes_block(node);
1966 ia32_address_mode_t am;
1967 ia32_address_t *addr = &am.addr;
1968 memset(&am, 0, sizeof(am));
1970 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1973 build_address(&am, op);
1975 dbgi = get_irn_dbg_info(node);
1976 block = be_transform_node(src_block);
1977 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1978 set_address(new_node, addr);
1979 set_ia32_op_type(new_node, ia32_AddrModeD);
1980 set_ia32_ls_mode(new_node, mode);
1981 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1986 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1987 ir_mode *mode = get_irn_mode(node);
1988 ir_node *psi_true = get_Psi_val(node, 0);
1989 ir_node *psi_default = get_Psi_default(node);
2000 ia32_address_t addr;
2002 if(get_mode_size_bits(mode) != 8)
2005 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2007 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2013 build_address_ptr(&addr, ptr, mem);
2015 irg = current_ir_graph;
2016 dbgi = get_irn_dbg_info(node);
2017 block = get_nodes_block(node);
2018 new_block = be_transform_node(block);
2019 cond = get_Psi_cond(node, 0);
2020 flags = get_flags_node(cond, &pnc);
2021 new_mem = be_transform_node(mem);
2022 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2023 addr.index, addr.mem, flags, pnc, negated);
2024 set_address(new_node, &addr);
2025 set_ia32_op_type(new_node, ia32_AddrModeD);
2026 set_ia32_ls_mode(new_node, mode);
2027 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2032 static ir_node *try_create_dest_am(ir_node *node) {
2033 ir_node *val = get_Store_value(node);
2034 ir_node *mem = get_Store_mem(node);
2035 ir_node *ptr = get_Store_ptr(node);
2036 ir_mode *mode = get_irn_mode(val);
2037 int bits = get_mode_size_bits(mode);
2042 /* handle only GP modes for now... */
2043 if(!mode_needs_gp_reg(mode))
2047 /* store must be the only user of the val node */
2048 if(get_irn_n_edges(val) > 1)
2050 /* skip pointless convs */
2052 ir_node *conv_op = get_Conv_op(val);
2053 ir_mode *pred_mode = get_irn_mode(conv_op);
2054 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2062 /* value must be in the same block */
2063 if(get_nodes_block(node) != get_nodes_block(val))
2066 switch(get_irn_opcode(val)) {
2068 op1 = get_Add_left(val);
2069 op2 = get_Add_right(val);
2070 if(is_Const_1(op2)) {
2071 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2072 new_rd_ia32_IncMem);
2074 } else if(is_Const_Minus_1(op2)) {
2075 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2076 new_rd_ia32_DecMem);
2079 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2080 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2081 match_dest_am | match_commutative |
2085 op1 = get_Sub_left(val);
2086 op2 = get_Sub_right(val);
2088 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2091 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2092 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2093 match_dest_am | match_immediate |
2097 op1 = get_And_left(val);
2098 op2 = get_And_right(val);
2099 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2100 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2101 match_dest_am | match_commutative |
2105 op1 = get_Or_left(val);
2106 op2 = get_Or_right(val);
2107 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2108 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2109 match_dest_am | match_commutative |
2113 op1 = get_Eor_left(val);
2114 op2 = get_Eor_right(val);
2115 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2116 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2117 match_dest_am | match_commutative |
2121 op1 = get_Shl_left(val);
2122 op2 = get_Shl_right(val);
2123 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2124 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2125 match_dest_am | match_immediate);
2128 op1 = get_Shr_left(val);
2129 op2 = get_Shr_right(val);
2130 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2131 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2132 match_dest_am | match_immediate);
2135 op1 = get_Shrs_left(val);
2136 op2 = get_Shrs_right(val);
2137 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2138 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2139 match_dest_am | match_immediate);
2142 op1 = get_Rot_left(val);
2143 op2 = get_Rot_right(val);
2144 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2145 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2146 match_dest_am | match_immediate);
2148 /* TODO: match ROR patterns... */
2150 new_node = try_create_SetMem(val, ptr, mem);
2153 op1 = get_Minus_op(val);
2154 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2157 /* should be lowered already */
2158 assert(mode != mode_b);
2159 op1 = get_Not_op(val);
2160 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2166 if(new_node != NULL) {
2167 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2168 get_irn_pinned(node) == op_pin_state_pinned) {
2169 set_irn_pinned(new_node, op_pin_state_pinned);
2176 static int is_float_to_int32_conv(const ir_node *node)
2178 ir_mode *mode = get_irn_mode(node);
2182 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2187 conv_op = get_Conv_op(node);
2188 conv_mode = get_irn_mode(conv_op);
2190 if(!mode_is_float(conv_mode))
2197 * Transforms a Store.
2199 * @return the created ia32 Store node
2201 static ir_node *gen_Store(ir_node *node)
2203 ir_node *block = get_nodes_block(node);
2204 ir_node *new_block = be_transform_node(block);
2205 ir_node *ptr = get_Store_ptr(node);
2206 ir_node *val = get_Store_value(node);
2207 ir_node *mem = get_Store_mem(node);
2208 ir_graph *irg = current_ir_graph;
2209 dbg_info *dbgi = get_irn_dbg_info(node);
2210 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2211 ir_mode *mode = get_irn_mode(val);
2214 ia32_address_t addr;
2216 /* check for destination address mode */
2217 new_node = try_create_dest_am(node);
2218 if(new_node != NULL)
2221 /* construct store address */
2222 memset(&addr, 0, sizeof(addr));
2223 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2225 if(addr.base == NULL) {
2228 addr.base = be_transform_node(addr.base);
2231 if(addr.index == NULL) {
2234 addr.index = be_transform_node(addr.index);
2236 addr.mem = be_transform_node(mem);
2238 if (mode_is_float(mode)) {
2239 /* convs (and strict-convs) before stores are unnecessary if the mode
2241 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2242 val = get_Conv_op(val);
2244 new_val = be_transform_node(val);
2245 if (USE_SSE2(env_cg)) {
2246 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2247 addr.index, addr.mem, new_val);
2249 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2250 addr.index, addr.mem, new_val, mode);
2252 } else if(is_float_to_int32_conv(val)) {
2253 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2254 val = get_Conv_op(val);
2256 /* convs (and strict-convs) before stores are unnecessary if the mode
2258 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2259 val = get_Conv_op(val);
2261 new_val = be_transform_node(val);
2263 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2264 addr.index, addr.mem, new_val, trunc_mode);
2266 new_val = create_immediate_or_transform(val, 0);
2267 assert(mode != mode_b);
2269 if (get_mode_size_bits(mode) == 8) {
2270 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2271 addr.index, addr.mem, new_val);
2273 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2274 addr.index, addr.mem, new_val);
2278 set_irn_pinned(new_node, get_irn_pinned(node));
2279 set_ia32_op_type(new_node, ia32_AddrModeD);
2280 set_ia32_ls_mode(new_node, mode);
2282 set_ia32_exc_label(new_node,
2283 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2284 set_address(new_node, &addr);
2285 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2290 static ir_node *create_Switch(ir_node *node)
2292 ir_graph *irg = current_ir_graph;
2293 dbg_info *dbgi = get_irn_dbg_info(node);
2294 ir_node *block = be_transform_node(get_nodes_block(node));
2295 ir_node *sel = get_Cond_selector(node);
2296 ir_node *new_sel = be_transform_node(sel);
2297 int switch_min = INT_MAX;
2299 const ir_edge_t *edge;
2301 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2303 /* determine the smallest switch case value */
2304 foreach_out_edge(node, edge) {
2305 ir_node *proj = get_edge_src_irn(edge);
2306 int pn = get_Proj_proj(proj);
2311 if (switch_min != 0) {
2312 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2314 /* if smallest switch case is not 0 we need an additional sub */
2315 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2316 add_ia32_am_offs_int(new_sel, -switch_min);
2317 set_ia32_op_type(new_sel, ia32_AddrModeS);
2319 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2322 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
2323 get_Cond_defaultProj(node));
2324 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2329 static ir_node *gen_Cond(ir_node *node) {
2330 ir_node *block = get_nodes_block(node);
2331 ir_node *new_block = be_transform_node(block);
2332 ir_graph *irg = current_ir_graph;
2333 dbg_info *dbgi = get_irn_dbg_info(node);
2334 ir_node *sel = get_Cond_selector(node);
2335 ir_mode *sel_mode = get_irn_mode(sel);
2336 ir_node *flags = NULL;
2340 if (sel_mode != mode_b) {
2341 return create_Switch(node);
2344 /* we get flags from a cmp */
2345 flags = get_flags_node(sel, &pnc);
2347 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2348 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2356 * Transforms a CopyB node.
2358 * @return The transformed node.
2360 static ir_node *gen_CopyB(ir_node *node) {
2361 ir_node *block = be_transform_node(get_nodes_block(node));
2362 ir_node *src = get_CopyB_src(node);
2363 ir_node *new_src = be_transform_node(src);
2364 ir_node *dst = get_CopyB_dst(node);
2365 ir_node *new_dst = be_transform_node(dst);
2366 ir_node *mem = get_CopyB_mem(node);
2367 ir_node *new_mem = be_transform_node(mem);
2368 ir_node *res = NULL;
2369 ir_graph *irg = current_ir_graph;
2370 dbg_info *dbgi = get_irn_dbg_info(node);
2371 int size = get_type_size_bytes(get_CopyB_type(node));
2374 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2375 /* then we need the size explicitly in ECX. */
2376 if (size >= 32 * 4) {
2377 rem = size & 0x3; /* size % 4 */
2380 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2381 add_irn_dep(res, get_irg_frame(irg));
2383 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2386 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2389 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2392 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2397 static ir_node *gen_be_Copy(ir_node *node)
2399 ir_node *new_node = be_duplicate_node(node);
2400 ir_mode *mode = get_irn_mode(new_node);
2402 if (mode_needs_gp_reg(mode)) {
2403 set_irn_mode(new_node, mode_Iu);
2409 static ir_node *create_Fucom(ir_node *node)
2411 ir_graph *irg = current_ir_graph;
2412 dbg_info *dbgi = get_irn_dbg_info(node);
2413 ir_node *block = get_nodes_block(node);
2414 ir_node *new_block = be_transform_node(block);
2415 ir_node *left = get_Cmp_left(node);
2416 ir_node *new_left = be_transform_node(left);
2417 ir_node *right = get_Cmp_right(node);
2421 if(transform_config.use_fucomi) {
2422 new_right = be_transform_node(right);
2423 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2425 set_ia32_commutative(new_node);
2426 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2428 if(transform_config.use_ftst && is_Const_null(right)) {
2429 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2432 new_right = be_transform_node(right);
2433 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2437 set_ia32_commutative(new_node);
2439 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2441 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2442 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2448 static ir_node *create_Ucomi(ir_node *node)
2450 ir_graph *irg = current_ir_graph;
2451 dbg_info *dbgi = get_irn_dbg_info(node);
2452 ir_node *src_block = get_nodes_block(node);
2453 ir_node *new_block = be_transform_node(src_block);
2454 ir_node *left = get_Cmp_left(node);
2455 ir_node *right = get_Cmp_right(node);
2457 ia32_address_mode_t am;
2458 ia32_address_t *addr = &am.addr;
2460 match_arguments(&am, src_block, left, right, match_commutative | match_am);
2462 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2463 addr->mem, am.new_op1, am.new_op2,
2465 set_am_attributes(new_node, &am);
2467 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2469 new_node = fix_mem_proj(new_node, &am);
2475 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2476 * to fold an and into a test node
2478 static int can_fold_test_and(ir_node *node)
2480 const ir_edge_t *edge;
2482 /** we can only have eq and lg projs */
2483 foreach_out_edge(node, edge) {
2484 ir_node *proj = get_edge_src_irn(edge);
2485 pn_Cmp pnc = get_Proj_proj(proj);
2486 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2493 static ir_node *gen_Cmp(ir_node *node)
2495 ir_graph *irg = current_ir_graph;
2496 dbg_info *dbgi = get_irn_dbg_info(node);
2497 ir_node *block = get_nodes_block(node);
2498 ir_node *new_block = be_transform_node(block);
2499 ir_node *left = get_Cmp_left(node);
2500 ir_node *right = get_Cmp_right(node);
2501 ir_mode *cmp_mode = get_irn_mode(left);
2503 ia32_address_mode_t am;
2504 ia32_address_t *addr = &am.addr;
2507 if(mode_is_float(cmp_mode)) {
2508 if (USE_SSE2(env_cg)) {
2509 return create_Ucomi(node);
2511 return create_Fucom(node);
2515 assert(mode_needs_gp_reg(cmp_mode));
2517 /* we prefer the Test instruction where possible except cases where
2518 * we can use SourceAM */
2519 cmp_unsigned = !mode_is_signed(cmp_mode);
2520 if (is_Const_0(right)) {
2522 get_irn_n_edges(left) == 1 &&
2523 can_fold_test_and(node)) {
2524 /* Test(and_left, and_right) */
2525 ir_node *and_left = get_And_left(left);
2526 ir_node *and_right = get_And_right(left);
2527 ir_mode *mode = get_irn_mode(and_left);
2529 match_arguments(&am, block, and_left, and_right, match_commutative |
2530 match_am | match_8bit_am | match_16bit_am |
2531 match_am_and_immediates | match_immediate |
2532 match_8bit | match_16bit);
2533 if (get_mode_size_bits(mode) == 8) {
2534 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2535 addr->index, addr->mem, am.new_op1,
2536 am.new_op2, am.ins_permuted,
2539 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2540 addr->index, addr->mem, am.new_op1,
2541 am.new_op2, am.ins_permuted, cmp_unsigned);
2544 match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
2545 match_16bit_am | match_8bit | match_16bit);
2546 if (am.op_type == ia32_AddrModeS) {
2548 ir_node *imm_zero = try_create_Immediate(right, 0);
2549 if (get_mode_size_bits(cmp_mode) == 8) {
2550 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2551 addr->index, addr->mem, am.new_op2,
2552 imm_zero, am.ins_permuted,
2555 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2556 addr->index, addr->mem, am.new_op2,
2557 imm_zero, am.ins_permuted, cmp_unsigned);
2560 /* Test(left, left) */
2561 if (get_mode_size_bits(cmp_mode) == 8) {
2562 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2563 addr->index, addr->mem, am.new_op2,
2564 am.new_op2, am.ins_permuted,
2567 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2568 addr->index, addr->mem, am.new_op2,
2569 am.new_op2, am.ins_permuted,
2575 /* Cmp(left, right) */
2576 match_arguments(&am, block, left, right, match_commutative | match_am |
2577 match_8bit_am | match_16bit_am | match_am_and_immediates |
2578 match_immediate | match_8bit | match_16bit);
2579 if (get_mode_size_bits(cmp_mode) == 8) {
2580 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2581 addr->index, addr->mem, am.new_op1,
2582 am.new_op2, am.ins_permuted,
2585 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2586 addr->index, addr->mem, am.new_op1,
2587 am.new_op2, am.ins_permuted, cmp_unsigned);
2590 set_am_attributes(new_node, &am);
2591 assert(cmp_mode != NULL);
2592 set_ia32_ls_mode(new_node, cmp_mode);
2594 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2596 new_node = fix_mem_proj(new_node, &am);
2601 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2603 ir_graph *irg = current_ir_graph;
2604 dbg_info *dbgi = get_irn_dbg_info(node);
2605 ir_node *block = get_nodes_block(node);
2606 ir_node *new_block = be_transform_node(block);
2607 ir_node *val_true = get_Psi_val(node, 0);
2608 ir_node *val_false = get_Psi_default(node);
2610 match_flags_t match_flags;
2611 ia32_address_mode_t am;
2612 ia32_address_t *addr;
2614 assert(transform_config.use_cmov);
2615 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2619 match_flags = match_commutative | match_am | match_16bit_am |
2622 match_arguments(&am, block, val_false, val_true, match_flags);
2624 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2625 addr->mem, am.new_op1, am.new_op2, new_flags,
2626 am.ins_permuted, pnc);
2627 set_am_attributes(new_node, &am);
2629 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2631 new_node = fix_mem_proj(new_node, &am);
2638 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2639 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2642 ir_graph *irg = current_ir_graph;
2643 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2644 ir_node *nomem = new_NoMem();
2645 ir_mode *mode = get_irn_mode(orig_node);
2648 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2649 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2651 /* we might need to conv the result up */
2652 if(get_mode_size_bits(mode) > 8) {
2653 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2654 nomem, new_node, mode_Bu);
2655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2662 * Transforms a Psi node into CMov.
2664 * @return The transformed node.
2666 static ir_node *gen_Psi(ir_node *node)
2668 dbg_info *dbgi = get_irn_dbg_info(node);
2669 ir_node *block = get_nodes_block(node);
2670 ir_node *new_block = be_transform_node(block);
2671 ir_node *psi_true = get_Psi_val(node, 0);
2672 ir_node *psi_default = get_Psi_default(node);
2673 ir_node *cond = get_Psi_cond(node, 0);
2674 ir_node *flags = NULL;
2678 assert(get_Psi_n_conds(node) == 1);
2679 assert(get_irn_mode(cond) == mode_b);
2680 assert(mode_needs_gp_reg(get_irn_mode(node)));
2682 flags = get_flags_node(cond, &pnc);
2684 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2685 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2686 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2687 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2689 new_node = create_CMov(node, flags, pnc);
2696 * Create a conversion from x87 state register to general purpose.
2698 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2699 ir_node *block = be_transform_node(get_nodes_block(node));
2700 ir_node *op = get_Conv_op(node);
2701 ir_node *new_op = be_transform_node(op);
2702 ia32_code_gen_t *cg = env_cg;
2703 ir_graph *irg = current_ir_graph;
2704 dbg_info *dbgi = get_irn_dbg_info(node);
2705 ir_node *noreg = ia32_new_NoReg_gp(cg);
2706 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2707 ir_mode *mode = get_irn_mode(node);
2708 ir_node *fist, *load;
2711 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2712 new_NoMem(), new_op, trunc_mode);
2714 set_irn_pinned(fist, op_pin_state_floats);
2715 set_ia32_use_frame(fist);
2716 set_ia32_op_type(fist, ia32_AddrModeD);
2718 assert(get_mode_size_bits(mode) <= 32);
2719 /* exception we can only store signed 32 bit integers, so for unsigned
2720 we store a 64bit (signed) integer and load the lower bits */
2721 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2722 set_ia32_ls_mode(fist, mode_Ls);
2724 set_ia32_ls_mode(fist, mode_Is);
2726 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2729 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2731 set_irn_pinned(load, op_pin_state_floats);
2732 set_ia32_use_frame(load);
2733 set_ia32_op_type(load, ia32_AddrModeS);
2734 set_ia32_ls_mode(load, mode_Is);
2735 if(get_ia32_ls_mode(fist) == mode_Ls) {
2736 ia32_attr_t *attr = get_ia32_attr(load);
2737 attr->data.need_64bit_stackent = 1;
2739 ia32_attr_t *attr = get_ia32_attr(load);
2740 attr->data.need_32bit_stackent = 1;
2742 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2744 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2748 * Creates a x87 strict Conv by placing a Sore and a Load
2750 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2752 ir_node *block = get_nodes_block(node);
2753 ir_graph *irg = current_ir_graph;
2754 dbg_info *dbgi = get_irn_dbg_info(node);
2755 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2756 ir_node *nomem = new_NoMem();
2757 ir_node *frame = get_irg_frame(irg);
2758 ir_node *store, *load;
2761 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2763 set_ia32_use_frame(store);
2764 set_ia32_op_type(store, ia32_AddrModeD);
2765 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2767 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2769 set_ia32_use_frame(load);
2770 set_ia32_op_type(load, ia32_AddrModeS);
2771 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2773 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2777 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2779 ir_graph *irg = current_ir_graph;
2780 ir_node *start_block = get_irg_start_block(irg);
2781 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2782 symconst, symconst_sign, val);
2783 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2789 * Create a conversion from general purpose to x87 register
2791 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2792 ir_node *src_block = get_nodes_block(node);
2793 ir_node *block = be_transform_node(src_block);
2794 ir_graph *irg = current_ir_graph;
2795 dbg_info *dbgi = get_irn_dbg_info(node);
2796 ir_node *op = get_Conv_op(node);
2797 ir_node *new_op = NULL;
2801 ir_mode *store_mode;
2807 /* fild can use source AM if the operand is a signed 32bit integer */
2808 if (src_mode == mode_Is) {
2809 ia32_address_mode_t am;
2811 match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
2812 if (am.op_type == ia32_AddrModeS) {
2813 ia32_address_t *addr = &am.addr;
2815 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2816 addr->index, addr->mem);
2817 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2820 set_am_attributes(fild, &am);
2821 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2823 fix_mem_proj(fild, &am);
2828 if(new_op == NULL) {
2829 new_op = be_transform_node(op);
2832 noreg = ia32_new_NoReg_gp(env_cg);
2833 nomem = new_NoMem();
2834 mode = get_irn_mode(op);
2836 /* first convert to 32 bit signed if necessary */
2837 src_bits = get_mode_size_bits(src_mode);
2838 if (src_bits == 8) {
2839 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2841 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2843 } else if (src_bits < 32) {
2844 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2846 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2850 assert(get_mode_size_bits(mode) == 32);
2853 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2856 set_ia32_use_frame(store);
2857 set_ia32_op_type(store, ia32_AddrModeD);
2858 set_ia32_ls_mode(store, mode_Iu);
2860 /* exception for 32bit unsigned, do a 64bit spill+load */
2861 if(!mode_is_signed(mode)) {
2864 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2866 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2867 get_irg_frame(irg), noreg, nomem,
2870 set_ia32_use_frame(zero_store);
2871 set_ia32_op_type(zero_store, ia32_AddrModeD);
2872 add_ia32_am_offs_int(zero_store, 4);
2873 set_ia32_ls_mode(zero_store, mode_Iu);
2878 store = new_rd_Sync(dbgi, irg, block, 2, in);
2879 store_mode = mode_Ls;
2881 store_mode = mode_Is;
2885 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2887 set_ia32_use_frame(fild);
2888 set_ia32_op_type(fild, ia32_AddrModeS);
2889 set_ia32_ls_mode(fild, store_mode);
2891 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2897 * Create a conversion from one integer mode into another one
2899 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2900 dbg_info *dbgi, ir_node *block, ir_node *op,
2903 ir_graph *irg = current_ir_graph;
2904 int src_bits = get_mode_size_bits(src_mode);
2905 int tgt_bits = get_mode_size_bits(tgt_mode);
2906 ir_node *new_block = be_transform_node(block);
2908 ir_mode *smaller_mode;
2910 ia32_address_mode_t am;
2911 ia32_address_t *addr = &am.addr;
2913 if (src_bits < tgt_bits) {
2914 smaller_mode = src_mode;
2915 smaller_bits = src_bits;
2917 smaller_mode = tgt_mode;
2918 smaller_bits = tgt_bits;
2921 #ifdef DEBUG_libfirm
2923 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2928 match_arguments(&am, block, NULL, op, match_8bit | match_16bit | match_am |
2929 match_8bit_am | match_16bit_am);
2930 if (smaller_bits == 8) {
2931 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2932 addr->index, addr->mem, am.new_op2,
2935 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2936 addr->index, addr->mem, am.new_op2,
2939 set_am_attributes(new_node, &am);
2940 /* match_arguments assume that out-mode = in-mode, this isn't true here
2942 set_ia32_ls_mode(new_node, smaller_mode);
2943 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2944 new_node = fix_mem_proj(new_node, &am);
2949 * Transforms a Conv node.
2951 * @return The created ia32 Conv node
2953 static ir_node *gen_Conv(ir_node *node) {
2954 ir_node *block = get_nodes_block(node);
2955 ir_node *new_block = be_transform_node(block);
2956 ir_node *op = get_Conv_op(node);
2957 ir_node *new_op = NULL;
2958 ir_graph *irg = current_ir_graph;
2959 dbg_info *dbgi = get_irn_dbg_info(node);
2960 ir_mode *src_mode = get_irn_mode(op);
2961 ir_mode *tgt_mode = get_irn_mode(node);
2962 int src_bits = get_mode_size_bits(src_mode);
2963 int tgt_bits = get_mode_size_bits(tgt_mode);
2964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2965 ir_node *nomem = new_rd_NoMem(irg);
2966 ir_node *res = NULL;
2968 if (src_mode == mode_b) {
2969 assert(mode_is_int(tgt_mode));
2970 /* nothing to do, we already model bools as 0/1 ints */
2971 return be_transform_node(op);
2974 if (src_mode == tgt_mode) {
2975 if (get_Conv_strict(node)) {
2976 if (USE_SSE2(env_cg)) {
2977 /* when we are in SSE mode, we can kill all strict no-op conversion */
2978 return be_transform_node(op);
2981 /* this should be optimized already, but who knows... */
2982 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2983 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2984 return be_transform_node(op);
2988 if (mode_is_float(src_mode)) {
2989 new_op = be_transform_node(op);
2990 /* we convert from float ... */
2991 if (mode_is_float(tgt_mode)) {
2992 if(src_mode == mode_E && tgt_mode == mode_D
2993 && !get_Conv_strict(node)) {
2994 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2999 if (USE_SSE2(env_cg)) {
3000 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3001 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3003 set_ia32_ls_mode(res, tgt_mode);
3005 if(get_Conv_strict(node)) {
3006 res = gen_x87_strict_conv(tgt_mode, new_op);
3007 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3010 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3015 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3016 if (USE_SSE2(env_cg)) {
3017 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3019 set_ia32_ls_mode(res, src_mode);
3021 return gen_x87_fp_to_gp(node);
3025 /* we convert from int ... */
3026 if (mode_is_float(tgt_mode)) {
3028 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3029 if (USE_SSE2(env_cg)) {
3030 new_op = be_transform_node(op);
3031 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3033 set_ia32_ls_mode(res, tgt_mode);
3035 res = gen_x87_gp_to_fp(node, src_mode);
3036 if(get_Conv_strict(node)) {
3037 res = gen_x87_strict_conv(tgt_mode, res);
3038 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3039 ia32_get_old_node_name(env_cg, node));
3043 } else if(tgt_mode == mode_b) {
3044 /* mode_b lowering already took care that we only have 0/1 values */
3045 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3046 src_mode, tgt_mode));
3047 return be_transform_node(op);
3050 if (src_bits == tgt_bits) {
3051 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3052 src_mode, tgt_mode));
3053 return be_transform_node(op);
3056 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3064 static int check_immediate_constraint(long val, char immediate_constraint_type)
3066 switch (immediate_constraint_type) {
3070 return val >= 0 && val <= 32;
3072 return val >= 0 && val <= 63;
3074 return val >= -128 && val <= 127;
3076 return val == 0xff || val == 0xffff;
3078 return val >= 0 && val <= 3;
3080 return val >= 0 && val <= 255;
3082 return val >= 0 && val <= 127;
3086 panic("Invalid immediate constraint found");
3090 static ir_node *try_create_Immediate(ir_node *node,
3091 char immediate_constraint_type)
3094 tarval *offset = NULL;
3095 int offset_sign = 0;
3097 ir_entity *symconst_ent = NULL;
3098 int symconst_sign = 0;
3100 ir_node *cnst = NULL;
3101 ir_node *symconst = NULL;
3104 mode = get_irn_mode(node);
3105 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3109 if(is_Minus(node)) {
3111 node = get_Minus_op(node);
3114 if(is_Const(node)) {
3117 offset_sign = minus;
3118 } else if(is_SymConst(node)) {
3121 symconst_sign = minus;
3122 } else if(is_Add(node)) {
3123 ir_node *left = get_Add_left(node);
3124 ir_node *right = get_Add_right(node);
3125 if(is_Const(left) && is_SymConst(right)) {
3128 symconst_sign = minus;
3129 offset_sign = minus;
3130 } else if(is_SymConst(left) && is_Const(right)) {
3133 symconst_sign = minus;
3134 offset_sign = minus;
3136 } else if(is_Sub(node)) {
3137 ir_node *left = get_Sub_left(node);
3138 ir_node *right = get_Sub_right(node);
3139 if(is_Const(left) && is_SymConst(right)) {
3142 symconst_sign = !minus;
3143 offset_sign = minus;
3144 } else if(is_SymConst(left) && is_Const(right)) {
3147 symconst_sign = minus;
3148 offset_sign = !minus;
3155 offset = get_Const_tarval(cnst);
3156 if(tarval_is_long(offset)) {
3157 val = get_tarval_long(offset);
3159 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3164 if(!check_immediate_constraint(val, immediate_constraint_type))
3167 if(symconst != NULL) {
3168 if(immediate_constraint_type != 0) {
3169 /* we need full 32bits for symconsts */
3173 /* unfortunately the assembler/linker doesn't support -symconst */
3177 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3179 symconst_ent = get_SymConst_entity(symconst);
3181 if(cnst == NULL && symconst == NULL)
3184 if(offset_sign && offset != NULL) {
3185 offset = tarval_neg(offset);
3188 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3193 static ir_node *create_immediate_or_transform(ir_node *node,
3194 char immediate_constraint_type)
3196 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3197 if (new_node == NULL) {
3198 new_node = be_transform_node(node);
3203 static const arch_register_req_t no_register_req = {
3204 arch_register_req_type_none,
3205 NULL, /* regclass */
3206 NULL, /* limit bitset */
3208 0 /* different pos */
3212 * An assembler constraint.
3214 typedef struct constraint_t constraint_t;
3215 struct constraint_t {
3218 const arch_register_req_t **out_reqs;
3220 const arch_register_req_t *req;
3221 unsigned immediate_possible;
3222 char immediate_type;
3225 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3227 int immediate_possible = 0;
3228 char immediate_type = 0;
3229 unsigned limited = 0;
3230 const arch_register_class_t *cls = NULL;
3231 ir_graph *irg = current_ir_graph;
3232 struct obstack *obst = get_irg_obstack(irg);
3233 arch_register_req_t *req;
3234 unsigned *limited_ptr = NULL;
3238 /* TODO: replace all the asserts with nice error messages */
3241 /* a memory constraint: no need to do anything in backend about it
3242 * (the dependencies are already respected by the memory edge of
3244 constraint->req = &no_register_req;
3256 assert(cls == NULL ||
3257 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3258 cls = &ia32_reg_classes[CLASS_ia32_gp];
3259 limited |= 1 << REG_EAX;
3262 assert(cls == NULL ||
3263 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3264 cls = &ia32_reg_classes[CLASS_ia32_gp];
3265 limited |= 1 << REG_EBX;
3268 assert(cls == NULL ||
3269 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3270 cls = &ia32_reg_classes[CLASS_ia32_gp];
3271 limited |= 1 << REG_ECX;
3274 assert(cls == NULL ||
3275 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3276 cls = &ia32_reg_classes[CLASS_ia32_gp];
3277 limited |= 1 << REG_EDX;
3280 assert(cls == NULL ||
3281 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3282 cls = &ia32_reg_classes[CLASS_ia32_gp];
3283 limited |= 1 << REG_EDI;
3286 assert(cls == NULL ||
3287 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3288 cls = &ia32_reg_classes[CLASS_ia32_gp];
3289 limited |= 1 << REG_ESI;
3292 case 'q': /* q means lower part of the regs only, this makes no
3293 * difference to Q for us (we only assigne whole registers) */
3294 assert(cls == NULL ||
3295 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3296 cls = &ia32_reg_classes[CLASS_ia32_gp];
3297 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3301 assert(cls == NULL ||
3302 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3303 cls = &ia32_reg_classes[CLASS_ia32_gp];
3304 limited |= 1 << REG_EAX | 1 << REG_EDX;
3307 assert(cls == NULL ||
3308 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3309 cls = &ia32_reg_classes[CLASS_ia32_gp];
3310 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3311 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3318 assert(cls == NULL);
3319 cls = &ia32_reg_classes[CLASS_ia32_gp];
3325 /* TODO: mark values so the x87 simulator knows about t and u */
3326 assert(cls == NULL);
3327 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3332 assert(cls == NULL);
3333 /* TODO: check that sse2 is supported */
3334 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3344 assert(!immediate_possible);
3345 immediate_possible = 1;
3346 immediate_type = *c;
3350 assert(!immediate_possible);
3351 immediate_possible = 1;
3355 assert(!immediate_possible && cls == NULL);
3356 immediate_possible = 1;
3357 cls = &ia32_reg_classes[CLASS_ia32_gp];
3370 assert(constraint->is_in && "can only specify same constraint "
3373 sscanf(c, "%d%n", &same_as, &p);
3381 /* memory constraint no need to do anything in backend about it
3382 * (the dependencies are already respected by the memory edge of
3384 constraint->req = &no_register_req;
3387 case 'E': /* no float consts yet */
3388 case 'F': /* no float consts yet */
3389 case 's': /* makes no sense on x86 */
3390 case 'X': /* we can't support that in firm */
3393 case '<': /* no autodecrement on x86 */
3394 case '>': /* no autoincrement on x86 */
3395 case 'C': /* sse constant not supported yet */
3396 case 'G': /* 80387 constant not supported yet */
3397 case 'y': /* we don't support mmx registers yet */
3398 case 'Z': /* not available in 32 bit mode */
3399 case 'e': /* not available in 32 bit mode */
3400 panic("unsupported asm constraint '%c' found in (%+F)",
3401 *c, current_ir_graph);
3404 panic("unknown asm constraint '%c' found in (%+F)", *c,
3412 const arch_register_req_t *other_constr;
3414 assert(cls == NULL && "same as and register constraint not supported");
3415 assert(!immediate_possible && "same as and immediate constraint not "
3417 assert(same_as < constraint->n_outs && "wrong constraint number in "
3418 "same_as constraint");
3420 other_constr = constraint->out_reqs[same_as];
3422 req = obstack_alloc(obst, sizeof(req[0]));
3423 req->cls = other_constr->cls;
3424 req->type = arch_register_req_type_should_be_same;
3425 req->limited = NULL;
3426 req->other_same = 1U << pos;
3427 req->other_different = 0;
3429 /* switch constraints. This is because in firm we have same_as
3430 * constraints on the output constraints while in the gcc asm syntax
3431 * they are specified on the input constraints */
3432 constraint->req = other_constr;
3433 constraint->out_reqs[same_as] = req;
3434 constraint->immediate_possible = 0;
3438 if(immediate_possible && cls == NULL) {
3439 cls = &ia32_reg_classes[CLASS_ia32_gp];
3441 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3442 assert(cls != NULL);
3444 if(immediate_possible) {
3445 assert(constraint->is_in
3446 && "immediate make no sense for output constraints");
3448 /* todo: check types (no float input on 'r' constrained in and such... */
3451 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3452 limited_ptr = (unsigned*) (req+1);
3454 req = obstack_alloc(obst, sizeof(req[0]));
3456 memset(req, 0, sizeof(req[0]));
3459 req->type = arch_register_req_type_limited;
3460 *limited_ptr = limited;
3461 req->limited = limited_ptr;
3463 req->type = arch_register_req_type_normal;
3467 constraint->req = req;
3468 constraint->immediate_possible = immediate_possible;
3469 constraint->immediate_type = immediate_type;
3472 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3479 panic("Clobbers not supported yet");
3482 static int is_memory_op(const ir_asm_constraint *constraint)
3484 ident *id = constraint->constraint;
3485 const char *str = get_id_str(id);
3488 for(c = str; *c != '\0'; ++c) {
3497 * generates code for a ASM node
3499 static ir_node *gen_ASM(ir_node *node)
3502 ir_graph *irg = current_ir_graph;
3503 ir_node *block = get_nodes_block(node);
3504 ir_node *new_block = be_transform_node(block);
3505 dbg_info *dbgi = get_irn_dbg_info(node);
3509 int n_out_constraints;
3511 const arch_register_req_t **out_reg_reqs;
3512 const arch_register_req_t **in_reg_reqs;
3513 ia32_asm_reg_t *register_map;
3514 unsigned reg_map_size = 0;
3515 struct obstack *obst;
3516 const ir_asm_constraint *in_constraints;
3517 const ir_asm_constraint *out_constraints;
3519 constraint_t parsed_constraint;
3521 arity = get_irn_arity(node);
3522 in = alloca(arity * sizeof(in[0]));
3523 memset(in, 0, arity * sizeof(in[0]));
3525 n_out_constraints = get_ASM_n_output_constraints(node);
3526 n_clobbers = get_ASM_n_clobbers(node);
3527 out_arity = n_out_constraints + n_clobbers;
3529 in_constraints = get_ASM_input_constraints(node);
3530 out_constraints = get_ASM_output_constraints(node);
3531 clobbers = get_ASM_clobbers(node);
3533 /* construct output constraints */
3534 obst = get_irg_obstack(irg);
3535 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3536 parsed_constraint.out_reqs = out_reg_reqs;
3537 parsed_constraint.n_outs = n_out_constraints;
3538 parsed_constraint.is_in = 0;
3540 for(i = 0; i < out_arity; ++i) {
3543 if(i < n_out_constraints) {
3544 const ir_asm_constraint *constraint = &out_constraints[i];
3545 c = get_id_str(constraint->constraint);
3546 parse_asm_constraint(i, &parsed_constraint, c);
3548 if(constraint->pos > reg_map_size)
3549 reg_map_size = constraint->pos;
3551 ident *glob_id = clobbers [i - n_out_constraints];
3552 c = get_id_str(glob_id);
3553 parse_clobber(node, i, &parsed_constraint, c);
3556 out_reg_reqs[i] = parsed_constraint.req;
3559 /* construct input constraints */
3560 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3561 parsed_constraint.is_in = 1;
3562 for(i = 0; i < arity; ++i) {
3563 const ir_asm_constraint *constraint = &in_constraints[i];
3564 ident *constr_id = constraint->constraint;
3565 const char *c = get_id_str(constr_id);
3567 parse_asm_constraint(i, &parsed_constraint, c);
3568 in_reg_reqs[i] = parsed_constraint.req;
3570 if(constraint->pos > reg_map_size)
3571 reg_map_size = constraint->pos;
3573 if(parsed_constraint.immediate_possible) {
3574 ir_node *pred = get_irn_n(node, i);
3575 char imm_type = parsed_constraint.immediate_type;
3576 ir_node *immediate = try_create_Immediate(pred, imm_type);
3578 if(immediate != NULL) {
3585 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3586 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3588 for(i = 0; i < n_out_constraints; ++i) {
3589 const ir_asm_constraint *constraint = &out_constraints[i];
3590 unsigned pos = constraint->pos;
3592 assert(pos < reg_map_size);
3593 register_map[pos].use_input = 0;
3594 register_map[pos].valid = 1;
3595 register_map[pos].memory = is_memory_op(constraint);
3596 register_map[pos].inout_pos = i;
3597 register_map[pos].mode = constraint->mode;
3600 /* transform inputs */
3601 for(i = 0; i < arity; ++i) {
3602 const ir_asm_constraint *constraint = &in_constraints[i];
3603 unsigned pos = constraint->pos;
3604 ir_node *pred = get_irn_n(node, i);
3605 ir_node *transformed;
3607 assert(pos < reg_map_size);
3608 register_map[pos].use_input = 1;
3609 register_map[pos].valid = 1;
3610 register_map[pos].memory = is_memory_op(constraint);
3611 register_map[pos].inout_pos = i;
3612 register_map[pos].mode = constraint->mode;
3617 transformed = be_transform_node(pred);
3618 in[i] = transformed;
3621 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3622 get_ASM_text(node), register_map);
3624 set_ia32_out_req_all(new_node, out_reg_reqs);
3625 set_ia32_in_req_all(new_node, in_reg_reqs);
3627 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3632 /********************************************
3635 * | |__ ___ _ __ ___ __| | ___ ___
3636 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3637 * | |_) | __/ | | | (_) | (_| | __/\__ \
3638 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3640 ********************************************/
3643 * Transforms a FrameAddr into an ia32 Add.
3645 static ir_node *gen_be_FrameAddr(ir_node *node) {
3646 ir_node *block = be_transform_node(get_nodes_block(node));
3647 ir_node *op = be_get_FrameAddr_frame(node);
3648 ir_node *new_op = be_transform_node(op);
3649 ir_graph *irg = current_ir_graph;
3650 dbg_info *dbgi = get_irn_dbg_info(node);
3651 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3654 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3655 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3656 set_ia32_use_frame(new_node);
3658 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3664 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3666 static ir_node *gen_be_Return(ir_node *node) {
3667 ir_graph *irg = current_ir_graph;
3668 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3669 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3670 ir_entity *ent = get_irg_entity(irg);
3671 ir_type *tp = get_entity_type(ent);
3676 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3677 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3680 int pn_ret_val, pn_ret_mem, arity, i;
3682 assert(ret_val != NULL);
3683 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3684 return be_duplicate_node(node);
3687 res_type = get_method_res_type(tp, 0);
3689 if (! is_Primitive_type(res_type)) {
3690 return be_duplicate_node(node);
3693 mode = get_type_mode(res_type);
3694 if (! mode_is_float(mode)) {
3695 return be_duplicate_node(node);
3698 assert(get_method_n_ress(tp) == 1);
3700 pn_ret_val = get_Proj_proj(ret_val);
3701 pn_ret_mem = get_Proj_proj(ret_mem);
3703 /* get the Barrier */
3704 barrier = get_Proj_pred(ret_val);
3706 /* get result input of the Barrier */
3707 ret_val = get_irn_n(barrier, pn_ret_val);
3708 new_ret_val = be_transform_node(ret_val);
3710 /* get memory input of the Barrier */
3711 ret_mem = get_irn_n(barrier, pn_ret_mem);
3712 new_ret_mem = be_transform_node(ret_mem);
3714 frame = get_irg_frame(irg);
3716 dbgi = get_irn_dbg_info(barrier);
3717 block = be_transform_node(get_nodes_block(barrier));
3719 noreg = ia32_new_NoReg_gp(env_cg);
3721 /* store xmm0 onto stack */
3722 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3723 new_ret_mem, new_ret_val);
3724 set_ia32_ls_mode(sse_store, mode);
3725 set_ia32_op_type(sse_store, ia32_AddrModeD);
3726 set_ia32_use_frame(sse_store);
3728 /* load into x87 register */
3729 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3730 set_ia32_op_type(fld, ia32_AddrModeS);
3731 set_ia32_use_frame(fld);
3733 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3734 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3736 /* create a new barrier */
3737 arity = get_irn_arity(barrier);
3738 in = alloca(arity * sizeof(in[0]));
3739 for (i = 0; i < arity; ++i) {
3742 if (i == pn_ret_val) {
3744 } else if (i == pn_ret_mem) {
3747 ir_node *in = get_irn_n(barrier, i);
3748 new_in = be_transform_node(in);
3753 new_barrier = new_ir_node(dbgi, irg, block,
3754 get_irn_op(barrier), get_irn_mode(barrier),
3756 copy_node_attr(barrier, new_barrier);
3757 be_duplicate_deps(barrier, new_barrier);
3758 be_set_transformed_node(barrier, new_barrier);
3759 mark_irn_visited(barrier);
3761 /* transform normally */
3762 return be_duplicate_node(node);
3766 * Transform a be_AddSP into an ia32_SubSP.
3768 static ir_node *gen_be_AddSP(ir_node *node)
3770 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3771 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3773 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3777 * Transform a be_SubSP into an ia32_AddSP
3779 static ir_node *gen_be_SubSP(ir_node *node)
3781 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3782 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3784 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3788 * This function just sets the register for the Unknown node
3789 * as this is not done during register allocation because Unknown
3790 * is an "ignore" node.
3792 static ir_node *gen_Unknown(ir_node *node) {
3793 ir_mode *mode = get_irn_mode(node);
3795 if (mode_is_float(mode)) {
3796 if (USE_SSE2(env_cg)) {
3797 return ia32_new_Unknown_xmm(env_cg);
3799 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3800 ir_graph *irg = current_ir_graph;
3801 dbg_info *dbgi = get_irn_dbg_info(node);
3802 ir_node *block = get_irg_start_block(irg);
3803 return new_rd_ia32_vfldz(dbgi, irg, block);
3805 } else if (mode_needs_gp_reg(mode)) {
3806 return ia32_new_Unknown_gp(env_cg);
3808 panic("unsupported Unknown-Mode");
3814 * Change some phi modes
3816 static ir_node *gen_Phi(ir_node *node) {
3817 ir_node *block = be_transform_node(get_nodes_block(node));
3818 ir_graph *irg = current_ir_graph;
3819 dbg_info *dbgi = get_irn_dbg_info(node);
3820 ir_mode *mode = get_irn_mode(node);
3823 if(mode_needs_gp_reg(mode)) {
3824 /* we shouldn't have any 64bit stuff around anymore */
3825 assert(get_mode_size_bits(mode) <= 32);
3826 /* all integer operations are on 32bit registers now */
3828 } else if(mode_is_float(mode)) {
3829 if (USE_SSE2(env_cg)) {
3836 /* phi nodes allow loops, so we use the old arguments for now
3837 * and fix this later */
3838 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3839 get_irn_in(node) + 1);
3840 copy_node_attr(node, phi);
3841 be_duplicate_deps(node, phi);
3843 be_set_transformed_node(node, phi);
3844 be_enqueue_preds(node);
3852 static ir_node *gen_IJmp(ir_node *node)
3854 ir_node *block = get_nodes_block(node);
3855 ir_node *new_block = be_transform_node(block);
3856 ir_graph *irg = current_ir_graph;
3857 dbg_info *dbgi = get_irn_dbg_info(node);
3858 ir_node *op = get_IJmp_target(node);
3860 ia32_address_mode_t am;
3861 ia32_address_t *addr = &am.addr;
3863 assert(get_irn_mode(op) == mode_P);
3865 match_arguments(&am, block, NULL, op,
3866 match_am | match_8bit_am | match_16bit_am |
3867 match_immediate | match_8bit | match_16bit);
3869 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3870 addr->mem, am.new_op2);
3871 set_am_attributes(new_node, &am);
3872 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3874 new_node = fix_mem_proj(new_node, &am);
3880 /**********************************************************************
3883 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3884 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3885 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3886 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3888 **********************************************************************/
3890 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3892 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3895 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3896 ir_node *val, ir_node *mem);
3899 * Transforms a lowered Load into a "real" one.
3901 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3903 ir_node *block = be_transform_node(get_nodes_block(node));
3904 ir_node *ptr = get_irn_n(node, 0);
3905 ir_node *new_ptr = be_transform_node(ptr);
3906 ir_node *mem = get_irn_n(node, 1);
3907 ir_node *new_mem = be_transform_node(mem);
3908 ir_graph *irg = current_ir_graph;
3909 dbg_info *dbgi = get_irn_dbg_info(node);
3910 ir_mode *mode = get_ia32_ls_mode(node);
3911 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3914 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3916 set_ia32_op_type(new_op, ia32_AddrModeS);
3917 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3918 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3919 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3920 if (is_ia32_am_sc_sign(node))
3921 set_ia32_am_sc_sign(new_op);
3922 set_ia32_ls_mode(new_op, mode);
3923 if (is_ia32_use_frame(node)) {
3924 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3925 set_ia32_use_frame(new_op);
3928 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3934 * Transforms a lowered Store into a "real" one.
3936 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3938 ir_node *block = be_transform_node(get_nodes_block(node));
3939 ir_node *ptr = get_irn_n(node, 0);
3940 ir_node *new_ptr = be_transform_node(ptr);
3941 ir_node *val = get_irn_n(node, 1);
3942 ir_node *new_val = be_transform_node(val);
3943 ir_node *mem = get_irn_n(node, 2);
3944 ir_node *new_mem = be_transform_node(mem);
3945 ir_graph *irg = current_ir_graph;
3946 dbg_info *dbgi = get_irn_dbg_info(node);
3947 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3948 ir_mode *mode = get_ia32_ls_mode(node);
3952 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3954 am_offs = get_ia32_am_offs_int(node);
3955 add_ia32_am_offs_int(new_op, am_offs);
3957 set_ia32_op_type(new_op, ia32_AddrModeD);
3958 set_ia32_ls_mode(new_op, mode);
3959 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3960 set_ia32_use_frame(new_op);
3962 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3967 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3969 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
3970 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
3972 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3973 match_immediate | match_mode_neutral);
3976 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3978 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
3979 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
3980 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3984 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3986 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
3987 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
3988 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3992 static ir_node *gen_ia32_l_Add(ir_node *node) {
3993 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3994 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3995 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3996 match_commutative | match_am | match_immediate |
3997 match_mode_neutral);
3999 if(is_Proj(lowered)) {
4000 lowered = get_Proj_pred(lowered);
4002 assert(is_ia32_Add(lowered));
4003 set_irn_mode(lowered, mode_T);
4009 static ir_node *gen_ia32_l_Adc(ir_node *node)
4011 return gen_binop_flags(node, new_rd_ia32_Adc,
4012 match_commutative | match_am | match_immediate |
4013 match_mode_neutral);
4017 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4019 * @param node The node to transform
4020 * @return the created ia32 vfild node
4022 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4023 return gen_lowered_Load(node, new_rd_ia32_vfild);
4027 * Transforms an ia32_l_Load into a "real" ia32_Load node
4029 * @param node The node to transform
4030 * @return the created ia32 Load node
4032 static ir_node *gen_ia32_l_Load(ir_node *node) {
4033 return gen_lowered_Load(node, new_rd_ia32_Load);
4037 * Transforms an ia32_l_Store into a "real" ia32_Store node
4039 * @param node The node to transform
4040 * @return the created ia32 Store node
4042 static ir_node *gen_ia32_l_Store(ir_node *node) {
4043 return gen_lowered_Store(node, new_rd_ia32_Store);
4047 * Transforms a l_vfist into a "real" vfist node.
4049 * @param node The node to transform
4050 * @return the created ia32 vfist node
4052 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4053 ir_node *block = be_transform_node(get_nodes_block(node));
4054 ir_node *ptr = get_irn_n(node, 0);
4055 ir_node *new_ptr = be_transform_node(ptr);
4056 ir_node *val = get_irn_n(node, 1);
4057 ir_node *new_val = be_transform_node(val);
4058 ir_node *mem = get_irn_n(node, 2);
4059 ir_node *new_mem = be_transform_node(mem);
4060 ir_graph *irg = current_ir_graph;
4061 dbg_info *dbgi = get_irn_dbg_info(node);
4062 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4063 ir_mode *mode = get_ia32_ls_mode(node);
4064 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4068 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4069 new_val, trunc_mode);
4071 am_offs = get_ia32_am_offs_int(node);
4072 add_ia32_am_offs_int(new_op, am_offs);
4074 set_ia32_op_type(new_op, ia32_AddrModeD);
4075 set_ia32_ls_mode(new_op, mode);
4076 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4077 set_ia32_use_frame(new_op);
4079 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4085 * Transforms a l_MulS into a "real" MulS node.
4087 * @return the created ia32 Mul node
4089 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4090 ir_node *left = get_binop_left(node);
4091 ir_node *right = get_binop_right(node);
4093 return gen_binop(node, left, right, new_rd_ia32_Mul,
4094 match_commutative | match_am | match_mode_neutral);
4098 * Transforms a l_IMulS into a "real" IMul1OPS node.
4100 * @return the created ia32 IMul1OP node
4102 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4103 ir_node *left = get_binop_left(node);
4104 ir_node *right = get_binop_right(node);
4106 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4107 match_commutative | match_am | match_mode_neutral);
4110 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4111 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4112 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4113 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4114 match_am | match_immediate | match_mode_neutral);
4116 if(is_Proj(lowered)) {
4117 lowered = get_Proj_pred(lowered);
4119 assert(is_ia32_Sub(lowered));
4120 set_irn_mode(lowered, mode_T);
4126 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4127 return gen_binop_flags(node, new_rd_ia32_Sbb,
4128 match_am | match_immediate | match_mode_neutral);
4132 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4133 * op1 - target to be shifted
4134 * op2 - contains bits to be shifted into target
4136 * Only op3 can be an immediate.
4138 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4139 ir_node *low, ir_node *count)
4141 ir_node *block = get_nodes_block(node);
4142 ir_node *new_block = be_transform_node(block);
4143 ir_graph *irg = current_ir_graph;
4144 dbg_info *dbgi = get_irn_dbg_info(node);
4145 ir_node *new_high = be_transform_node(high);
4146 ir_node *new_low = be_transform_node(low);
4150 /* the shift amount can be any mode that is bigger than 5 bits, since all
4151 * other bits are ignored anyway */
4152 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4153 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4154 count = get_Conv_op(count);
4156 new_count = create_immediate_or_transform(count, 0);
4158 if (is_ia32_l_ShlD(node)) {
4159 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4162 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4165 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4170 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4172 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
4173 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
4174 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4175 return gen_lowered_64bit_shifts(node, high, low, count);
4178 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4180 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
4181 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
4182 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4183 return gen_lowered_64bit_shifts(node, high, low, count);
4187 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4189 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4190 ir_node *block = be_transform_node(get_nodes_block(node));
4191 ir_node *val = get_irn_n(node, 1);
4192 ir_node *new_val = be_transform_node(val);
4193 ia32_code_gen_t *cg = env_cg;
4194 ir_node *res = NULL;
4195 ir_graph *irg = current_ir_graph;
4197 ir_node *noreg, *new_ptr, *new_mem;
4204 mem = get_irn_n(node, 2);
4205 new_mem = be_transform_node(mem);
4206 ptr = get_irn_n(node, 0);
4207 new_ptr = be_transform_node(ptr);
4208 noreg = ia32_new_NoReg_gp(cg);
4209 dbgi = get_irn_dbg_info(node);
4211 /* Store x87 -> MEM */
4212 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4213 get_ia32_ls_mode(node));
4214 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4215 set_ia32_use_frame(res);
4216 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4217 set_ia32_op_type(res, ia32_AddrModeD);
4219 /* Load MEM -> SSE */
4220 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4221 get_ia32_ls_mode(node));
4222 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4223 set_ia32_use_frame(res);
4224 set_ia32_op_type(res, ia32_AddrModeS);
4225 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4231 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4233 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4234 ir_node *block = be_transform_node(get_nodes_block(node));
4235 ir_node *val = get_irn_n(node, 1);
4236 ir_node *new_val = be_transform_node(val);
4237 ia32_code_gen_t *cg = env_cg;
4238 ir_graph *irg = current_ir_graph;
4239 ir_node *res = NULL;
4240 ir_entity *fent = get_ia32_frame_ent(node);
4241 ir_mode *lsmode = get_ia32_ls_mode(node);
4243 ir_node *noreg, *new_ptr, *new_mem;
4247 if (! USE_SSE2(cg)) {
4248 /* SSE unit is not used -> skip this node. */
4252 ptr = get_irn_n(node, 0);
4253 new_ptr = be_transform_node(ptr);
4254 mem = get_irn_n(node, 2);
4255 new_mem = be_transform_node(mem);
4256 noreg = ia32_new_NoReg_gp(cg);
4257 dbgi = get_irn_dbg_info(node);
4259 /* Store SSE -> MEM */
4260 if (is_ia32_xLoad(skip_Proj(new_val))) {
4261 ir_node *ld = skip_Proj(new_val);
4263 /* we can vfld the value directly into the fpu */
4264 fent = get_ia32_frame_ent(ld);
4265 ptr = get_irn_n(ld, 0);
4266 offs = get_ia32_am_offs_int(ld);
4268 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4270 set_ia32_frame_ent(res, fent);
4271 set_ia32_use_frame(res);
4272 set_ia32_ls_mode(res, lsmode);
4273 set_ia32_op_type(res, ia32_AddrModeD);
4277 /* Load MEM -> x87 */
4278 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4279 set_ia32_frame_ent(res, fent);
4280 set_ia32_use_frame(res);
4281 add_ia32_am_offs_int(res, offs);
4282 set_ia32_op_type(res, ia32_AddrModeS);
4283 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4288 /*********************************************************
4291 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4292 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4293 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4294 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4296 *********************************************************/
4299 * the BAD transformer.
4301 static ir_node *bad_transform(ir_node *node) {
4302 panic("No transform function for %+F available.\n", node);
4307 * Transform the Projs of an AddSP.
4309 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4310 ir_node *block = be_transform_node(get_nodes_block(node));
4311 ir_node *pred = get_Proj_pred(node);
4312 ir_node *new_pred = be_transform_node(pred);
4313 ir_graph *irg = current_ir_graph;
4314 dbg_info *dbgi = get_irn_dbg_info(node);
4315 long proj = get_Proj_proj(node);
4317 if (proj == pn_be_AddSP_sp) {
4318 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4319 pn_ia32_SubSP_stack);
4320 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4322 } else if(proj == pn_be_AddSP_res) {
4323 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4324 pn_ia32_SubSP_addr);
4325 } else if (proj == pn_be_AddSP_M) {
4326 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4330 return new_rd_Unknown(irg, get_irn_mode(node));
4334 * Transform the Projs of a SubSP.
4336 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4337 ir_node *block = be_transform_node(get_nodes_block(node));
4338 ir_node *pred = get_Proj_pred(node);
4339 ir_node *new_pred = be_transform_node(pred);
4340 ir_graph *irg = current_ir_graph;
4341 dbg_info *dbgi = get_irn_dbg_info(node);
4342 long proj = get_Proj_proj(node);
4344 if (proj == pn_be_SubSP_sp) {
4345 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4346 pn_ia32_AddSP_stack);
4347 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4349 } else if (proj == pn_be_SubSP_M) {
4350 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4354 return new_rd_Unknown(irg, get_irn_mode(node));
4358 * Transform and renumber the Projs from a Load.
4360 static ir_node *gen_Proj_Load(ir_node *node) {
4362 ir_node *block = be_transform_node(get_nodes_block(node));
4363 ir_node *pred = get_Proj_pred(node);
4364 ir_graph *irg = current_ir_graph;
4365 dbg_info *dbgi = get_irn_dbg_info(node);
4366 long proj = get_Proj_proj(node);
4369 /* loads might be part of source address mode matches, so we don't
4370 transform the ProjMs yet (with the exception of loads whose result is
4373 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4376 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4378 /* this is needed, because sometimes we have loops that are only
4379 reachable through the ProjM */
4380 be_enqueue_preds(node);
4381 /* do it in 2 steps, to silence firm verifier */
4382 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4383 set_Proj_proj(res, pn_ia32_Load_M);
4387 /* renumber the proj */
4388 new_pred = be_transform_node(pred);
4389 if (is_ia32_Load(new_pred)) {
4390 if (proj == pn_Load_res) {
4391 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4393 } else if (proj == pn_Load_M) {
4394 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4397 } else if(is_ia32_Conv_I2I(new_pred)
4398 || is_ia32_Conv_I2I8Bit(new_pred)) {
4399 set_irn_mode(new_pred, mode_T);
4400 if (proj == pn_Load_res) {
4401 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4402 } else if (proj == pn_Load_M) {
4403 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4405 } else if (is_ia32_xLoad(new_pred)) {
4406 if (proj == pn_Load_res) {
4407 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4409 } else if (proj == pn_Load_M) {
4410 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4413 } else if (is_ia32_vfld(new_pred)) {
4414 if (proj == pn_Load_res) {
4415 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4417 } else if (proj == pn_Load_M) {
4418 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4422 /* can happen for ProJMs when source address mode happened for the
4425 /* however it should not be the result proj, as that would mean the
4426 load had multiple users and should not have been used for
4428 if(proj != pn_Load_M) {
4429 panic("internal error: transformed node not a Load");
4431 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4435 return new_rd_Unknown(irg, get_irn_mode(node));
4439 * Transform and renumber the Projs from a DivMod like instruction.
4441 static ir_node *gen_Proj_DivMod(ir_node *node) {
4442 ir_node *block = be_transform_node(get_nodes_block(node));
4443 ir_node *pred = get_Proj_pred(node);
4444 ir_node *new_pred = be_transform_node(pred);
4445 ir_graph *irg = current_ir_graph;
4446 dbg_info *dbgi = get_irn_dbg_info(node);
4447 ir_mode *mode = get_irn_mode(node);
4448 long proj = get_Proj_proj(node);
4450 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4452 switch (get_irn_opcode(pred)) {
4456 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4458 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4466 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4468 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4476 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4477 case pn_DivMod_res_div:
4478 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4479 case pn_DivMod_res_mod:
4480 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4490 return new_rd_Unknown(irg, mode);
4494 * Transform and renumber the Projs from a CopyB.
4496 static ir_node *gen_Proj_CopyB(ir_node *node) {
4497 ir_node *block = be_transform_node(get_nodes_block(node));
4498 ir_node *pred = get_Proj_pred(node);
4499 ir_node *new_pred = be_transform_node(pred);
4500 ir_graph *irg = current_ir_graph;
4501 dbg_info *dbgi = get_irn_dbg_info(node);
4502 ir_mode *mode = get_irn_mode(node);
4503 long proj = get_Proj_proj(node);
4506 case pn_CopyB_M_regular:
4507 if (is_ia32_CopyB_i(new_pred)) {
4508 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4509 } else if (is_ia32_CopyB(new_pred)) {
4510 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4518 return new_rd_Unknown(irg, mode);
4522 * Transform and renumber the Projs from a Quot.
4524 static ir_node *gen_Proj_Quot(ir_node *node) {
4525 ir_node *block = be_transform_node(get_nodes_block(node));
4526 ir_node *pred = get_Proj_pred(node);
4527 ir_node *new_pred = be_transform_node(pred);
4528 ir_graph *irg = current_ir_graph;
4529 dbg_info *dbgi = get_irn_dbg_info(node);
4530 ir_mode *mode = get_irn_mode(node);
4531 long proj = get_Proj_proj(node);
4535 if (is_ia32_xDiv(new_pred)) {
4536 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4537 } else if (is_ia32_vfdiv(new_pred)) {
4538 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4542 if (is_ia32_xDiv(new_pred)) {
4543 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4544 } else if (is_ia32_vfdiv(new_pred)) {
4545 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4553 return new_rd_Unknown(irg, mode);
4557 * Transform the Thread Local Storage Proj.
4559 static ir_node *gen_Proj_tls(ir_node *node) {
4560 ir_node *block = be_transform_node(get_nodes_block(node));
4561 ir_graph *irg = current_ir_graph;
4562 dbg_info *dbgi = NULL;
4563 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4568 static ir_node *gen_be_Call(ir_node *node) {
4569 ir_node *res = be_duplicate_node(node);
4570 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4575 static ir_node *gen_be_IncSP(ir_node *node) {
4576 ir_node *res = be_duplicate_node(node);
4577 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4583 * Transform the Projs from a be_Call.
4585 static ir_node *gen_Proj_be_Call(ir_node *node) {
4586 ir_node *block = be_transform_node(get_nodes_block(node));
4587 ir_node *call = get_Proj_pred(node);
4588 ir_node *new_call = be_transform_node(call);
4589 ir_graph *irg = current_ir_graph;
4590 dbg_info *dbgi = get_irn_dbg_info(node);
4591 ir_type *method_type = be_Call_get_type(call);
4592 int n_res = get_method_n_ress(method_type);
4593 long proj = get_Proj_proj(node);
4594 ir_mode *mode = get_irn_mode(node);
4596 const arch_register_class_t *cls;
4598 /* The following is kinda tricky: If we're using SSE, then we have to
4599 * move the result value of the call in floating point registers to an
4600 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4601 * after the call, we have to make sure to correctly make the
4602 * MemProj and the result Proj use these 2 nodes
4604 if (proj == pn_be_Call_M_regular) {
4605 // get new node for result, are we doing the sse load/store hack?
4606 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4607 ir_node *call_res_new;
4608 ir_node *call_res_pred = NULL;
4610 if (call_res != NULL) {
4611 call_res_new = be_transform_node(call_res);
4612 call_res_pred = get_Proj_pred(call_res_new);
4615 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4616 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4617 pn_be_Call_M_regular);
4619 assert(is_ia32_xLoad(call_res_pred));
4620 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4624 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4625 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4626 && USE_SSE2(env_cg)) {
4628 ir_node *frame = get_irg_frame(irg);
4629 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4631 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4634 /* in case there is no memory output: create one to serialize the copy
4636 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4637 pn_be_Call_M_regular);
4638 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4639 pn_be_Call_first_res);
4641 /* store st(0) onto stack */
4642 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4644 set_ia32_op_type(fstp, ia32_AddrModeD);
4645 set_ia32_use_frame(fstp);
4647 /* load into SSE register */
4648 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4650 set_ia32_op_type(sse_load, ia32_AddrModeS);
4651 set_ia32_use_frame(sse_load);
4653 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4659 /* transform call modes */
4660 if (mode_is_data(mode)) {
4661 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4665 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4669 * Transform the Projs from a Cmp.
4671 static ir_node *gen_Proj_Cmp(ir_node *node)
4674 panic("not all mode_b nodes are lowered");
4677 /* normally Cmps are processed when looking at Cond nodes, but this case
4678 * can happen in complicated Psi conditions */
4679 dbg_info *dbgi = get_irn_dbg_info(node);
4680 ir_node *block = get_nodes_block(node);
4681 ir_node *new_block = be_transform_node(block);
4682 ir_node *cmp = get_Proj_pred(node);
4683 ir_node *new_cmp = be_transform_node(cmp);
4684 long pnc = get_Proj_proj(node);
4687 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
4694 * Transform and potentially renumber Proj nodes.
4696 static ir_node *gen_Proj(ir_node *node) {
4697 ir_graph *irg = current_ir_graph;
4698 dbg_info *dbgi = get_irn_dbg_info(node);
4699 ir_node *pred = get_Proj_pred(node);
4700 long proj = get_Proj_proj(node);
4702 if (is_Store(pred)) {
4703 if (proj == pn_Store_M) {
4704 return be_transform_node(pred);
4707 return new_r_Bad(irg);
4709 } else if (is_Load(pred)) {
4710 return gen_Proj_Load(node);
4711 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4712 return gen_Proj_DivMod(node);
4713 } else if (is_CopyB(pred)) {
4714 return gen_Proj_CopyB(node);
4715 } else if (is_Quot(pred)) {
4716 return gen_Proj_Quot(node);
4717 } else if (be_is_SubSP(pred)) {
4718 return gen_Proj_be_SubSP(node);
4719 } else if (be_is_AddSP(pred)) {
4720 return gen_Proj_be_AddSP(node);
4721 } else if (be_is_Call(pred)) {
4722 return gen_Proj_be_Call(node);
4723 } else if (is_Cmp(pred)) {
4724 return gen_Proj_Cmp(node);
4725 } else if (get_irn_op(pred) == op_Start) {
4726 if (proj == pn_Start_X_initial_exec) {
4727 ir_node *block = get_nodes_block(pred);
4730 /* we exchange the ProjX with a jump */
4731 block = be_transform_node(block);
4732 jump = new_rd_Jmp(dbgi, irg, block);
4735 if (node == be_get_old_anchor(anchor_tls)) {
4736 return gen_Proj_tls(node);
4739 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4743 ir_node *new_pred = be_transform_node(pred);
4744 ir_node *block = be_transform_node(get_nodes_block(node));
4745 ir_mode *mode = get_irn_mode(node);
4746 if (mode_needs_gp_reg(mode)) {
4747 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4748 get_Proj_proj(node));
4749 #ifdef DEBUG_libfirm
4750 new_proj->node_nr = node->node_nr;
4756 return be_duplicate_node(node);
4760 * Enters all transform functions into the generic pointer
4762 static void register_transformers(void)
4766 /* first clear the generic function pointer for all ops */
4767 clear_irp_opcodes_generic_func();
4769 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4770 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4808 /* transform ops from intrinsic lowering */
4824 GEN(ia32_l_X87toSSE);
4825 GEN(ia32_l_SSEtoX87);
4831 /* we should never see these nodes */
4846 /* handle generic backend nodes */
4855 op_Mulh = get_op_Mulh();
4864 * Pre-transform all unknown and noreg nodes.
4866 static void ia32_pretransform_node(void *arch_cg) {
4867 ia32_code_gen_t *cg = arch_cg;
4869 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4870 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4871 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4872 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4873 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4874 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4879 * Walker, checks if all ia32 nodes producing more than one result have
4880 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4882 static void add_missing_keep_walker(ir_node *node, void *data)
4885 unsigned found_projs = 0;
4886 const ir_edge_t *edge;
4887 ir_mode *mode = get_irn_mode(node);
4892 if(!is_ia32_irn(node))
4895 n_outs = get_ia32_n_res(node);
4898 if(is_ia32_SwitchJmp(node))
4901 assert(n_outs < (int) sizeof(unsigned) * 8);
4902 foreach_out_edge(node, edge) {
4903 ir_node *proj = get_edge_src_irn(edge);
4904 int pn = get_Proj_proj(proj);
4906 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4907 found_projs |= 1 << pn;
4911 /* are keeps missing? */
4913 for(i = 0; i < n_outs; ++i) {
4916 const arch_register_req_t *req;
4917 const arch_register_class_t *class;
4919 if(found_projs & (1 << i)) {
4923 req = get_ia32_out_req(node, i);
4928 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4932 block = get_nodes_block(node);
4933 in[0] = new_r_Proj(current_ir_graph, block, node,
4934 arch_register_class_mode(class), i);
4935 if(last_keep != NULL) {
4936 be_Keep_add_node(last_keep, class, in[0]);
4938 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4939 if(sched_is_scheduled(node)) {
4940 sched_add_after(node, last_keep);
4947 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4950 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4952 ir_graph *irg = be_get_birg_irg(cg->birg);
4953 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4956 /* do the transformation */
4957 void ia32_transform_graph(ia32_code_gen_t *cg) {
4959 ir_graph *irg = cg->irg;
4960 int opt_arch = cg->isa->opt_arch;
4961 int arch = cg->isa->arch;
4963 /* TODO: look at cpu and fill transform config in with that... */
4964 transform_config.use_incdec = 1;
4965 transform_config.use_sse2 = 0;
4966 transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
4967 transform_config.use_ftst = 0;
4968 transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
4969 transform_config.use_fucomi = 1;
4970 transform_config.use_cmov = IS_P6_ARCH(arch);
4972 register_transformers();
4974 initial_fpcw = NULL;
4976 heights = heights_new(irg);
4977 ia32_calculate_non_address_mode_nodes(cg->birg);
4979 /* the transform phase is not safe for CSE (yet) because several nodes get
4980 * attributes set after their creation */
4981 cse_last = get_opt_cse();
4984 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4986 set_opt_cse(cse_last);
4988 ia32_free_non_address_mode_nodes();
4989 heights_free(heights);
4993 void ia32_init_transform(void)
4995 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");