2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
14 #include "irgraph_t.h"
19 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
37 #include "../benode_t.h"
38 #include "../besched.h"
40 #include "../beutil.h"
42 #include "bearch_ia32_t.h"
43 #include "ia32_nodes_attr.h"
44 #include "ia32_transform.h"
45 #include "ia32_new_nodes.h"
46 #include "ia32_map_regs.h"
47 #include "ia32_dbg_stat.h"
48 #include "ia32_optimize.h"
49 #include "ia32_util.h"
51 #include "gen_ia32_regalloc_if.h"
53 #define SFP_SIGN "0x80000000"
54 #define DFP_SIGN "0x8000000000000000"
55 #define SFP_ABS "0x7FFFFFFF"
56 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
58 #define TP_SFP_SIGN "ia32_sfp_sign"
59 #define TP_DFP_SIGN "ia32_dfp_sign"
60 #define TP_SFP_ABS "ia32_sfp_abs"
61 #define TP_DFP_ABS "ia32_dfp_abs"
63 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
64 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
65 #define ENT_SFP_ABS "IA32_SFP_ABS"
66 #define ENT_DFP_ABS "IA32_DFP_ABS"
68 typedef struct ia32_transform_env_t {
69 ir_graph *irg; /**< The irg, the node should be created in */
70 ia32_code_gen_t *cg; /**< The code generator */
71 int visited; /**< visited count that indicates whether a
72 node is already transformed */
73 pdeq *worklist; /**< worklist of nodes that still need to be
75 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
76 DEBUG_ONLY(firm_dbg_module_t *mod;) /**< The firm debugger */
77 } ia32_transform_env_t;
79 extern ir_op *get_op_Mulh(void);
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
82 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
83 ir_node *op2, ir_node *mem);
85 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
86 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
89 typedef ir_node *(transform_func)(ia32_transform_env_t *env, ir_node *node);
91 /****************************************************************************************************
93 * | | | | / _| | | (_)
94 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
95 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
96 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
97 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
99 ****************************************************************************************************/
101 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node);
102 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node);
103 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
106 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
108 set_irn_link(old_node, new_node);
111 static INLINE ir_node *get_new_node(ir_node *old_node)
113 assert(irn_visited(old_node));
114 return (ir_node*) get_irn_link(old_node);
118 * Returns 1 if irn is a Const representing 0, 0 otherwise
120 static INLINE int is_ia32_Const_0(ir_node *irn) {
121 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
122 && tarval_is_null(get_ia32_Immop_tarval(irn));
126 * Returns 1 if irn is a Const representing 1, 0 otherwise
128 static INLINE int is_ia32_Const_1(ir_node *irn) {
129 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
130 && tarval_is_one(get_ia32_Immop_tarval(irn));
134 * Collects all Projs of a node into the node array. Index is the projnum.
135 * BEWARE: The caller has to assure the appropriate array size!
137 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
138 const ir_edge_t *edge;
139 assert(get_irn_mode(irn) == mode_T && "need mode_T");
141 memset(projs, 0, size * sizeof(projs[0]));
143 foreach_out_edge(irn, edge) {
144 ir_node *proj = get_edge_src_irn(edge);
145 int proj_proj = get_Proj_proj(proj);
146 assert(proj_proj < size);
147 projs[proj_proj] = proj;
152 * Renumbers the proj having pn_old in the array tp pn_new
153 * and removes the proj from the array.
155 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
156 fprintf(stderr, "Warning: renumber_Proj used!\n");
158 set_Proj_proj(projs[pn_old], pn_new);
159 projs[pn_old] = NULL;
164 * creates a unique ident by adding a number to a tag
166 * @param tag the tag string, must contain a %d if a number
169 static ident *unique_id(const char *tag)
171 static unsigned id = 0;
174 snprintf(str, sizeof(str), tag, ++id);
175 return new_id_from_str(str);
179 * Get a primitive type for a mode.
181 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
183 pmap_entry *e = pmap_find(types, mode);
188 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
189 res = new_type_primitive(new_id_from_str(buf), mode);
190 pmap_insert(types, mode, res);
198 * Get an entity that is initialized with a tarval
200 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
202 tarval *tv = get_Const_tarval(cnst);
203 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
208 ir_mode *mode = get_irn_mode(cnst);
209 ir_type *tp = get_Const_type(cnst);
210 if (tp == firm_unknown_type)
211 tp = get_prim_type(cg->isa->types, mode);
213 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
215 set_entity_ld_ident(res, get_entity_ident(res));
216 set_entity_visibility(res, visibility_local);
217 set_entity_variability(res, variability_constant);
218 set_entity_allocation(res, allocation_static);
220 /* we create a new entity here: It's initialization must resist on the
222 rem = current_ir_graph;
223 current_ir_graph = get_const_code_irg();
224 set_atomic_ent_value(res, new_Const_type(tv, tp));
225 current_ir_graph = rem;
227 pmap_insert(cg->isa->tv_ent, tv, res);
235 * Transforms a Const.
237 * @param mod the debug module
238 * @param block the block the new node should belong to
239 * @param node the ir Const node
240 * @param mode mode of the Const
241 * @return the created ia32 Const node
243 static ir_node *gen_Const(ia32_transform_env_t *env, ir_node *node) {
244 ir_graph *irg = env->irg;
245 dbg_info *dbg = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
247 ir_node *block = transform_node(env, get_nodes_block(node));
249 if (mode_is_float(mode)) {
252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
253 ir_node *nomem = new_NoMem();
257 if (! USE_SSE2(env->cg)) {
258 cnst_classify_t clss = classify_Const(node);
260 if (clss == CNST_NULL) {
261 load = new_rd_ia32_vfldz(dbg, irg, block);
263 } else if (clss == CNST_ONE) {
264 load = new_rd_ia32_vfld1(dbg, irg, block);
267 floatent = get_entity_for_tv(env->cg, node);
269 load = new_rd_ia32_vfld(dbg, irg, block, noreg, noreg, nomem);
270 set_ia32_am_support(load, ia32_am_Source);
271 set_ia32_op_type(load, ia32_AddrModeS);
272 set_ia32_am_flavour(load, ia32_am_N);
273 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
274 res = new_r_Proj(irg, block, load, mode_D, pn_ia32_vfld_res);
277 floatent = get_entity_for_tv(env->cg, node);
279 load = new_rd_ia32_xLoad(dbg, irg, block, noreg, noreg, nomem);
280 set_ia32_am_support(load, ia32_am_Source);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_flavour(load, ia32_am_N);
283 set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
284 res = new_r_Proj(irg, block, load, mode_D, pn_ia32_xLoad_res);
287 set_ia32_ls_mode(load, mode);
288 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
290 /* Const Nodes before the initial IncSP are a bad idea, because
291 * they could be spilled and we have no SP ready at that point yet
293 if (get_irg_start_block(irg) == block) {
294 add_irn_dep(load, get_irg_frame(irg));
297 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env->cg, node));
300 ir_node *cnst = new_rd_ia32_Const(dbg, irg, block);
303 if (get_irg_start_block(irg) == block) {
304 add_irn_dep(cnst, get_irg_frame(irg));
307 set_ia32_Const_attr(cnst, node);
308 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
313 return new_r_Bad(irg);
317 * Transforms a SymConst.
319 * @param mod the debug module
320 * @param block the block the new node should belong to
321 * @param node the ir SymConst node
322 * @param mode mode of the SymConst
323 * @return the created ia32 Const node
325 static ir_node *gen_SymConst(ia32_transform_env_t *env, ir_node *node) {
326 ir_graph *irg = env->irg;
327 dbg_info *dbg = get_irn_dbg_info(node);
328 ir_mode *mode = get_irn_mode(node);
329 ir_node *block = transform_node(env, get_nodes_block(node));
332 if (mode_is_float(mode)) {
334 if (USE_SSE2(env->cg))
335 cnst = new_rd_ia32_xConst(dbg, irg, block);
337 cnst = new_rd_ia32_vfConst(dbg, irg, block);
338 set_ia32_ls_mode(cnst, mode);
340 cnst = new_rd_ia32_Const(dbg, irg, block);
343 /* Const Nodes before the initial IncSP are a bad idea, because
344 * they could be spilled and we have no SP ready at that point yet
346 if (get_irg_start_block(irg) == block) {
347 add_irn_dep(cnst, get_irg_frame(irg));
350 set_ia32_Const_attr(cnst, node);
351 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env->cg, node));
357 * SSE convert of an integer node into a floating point node.
359 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg,
360 ir_graph *irg, ir_node *block,
361 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
364 ir_node *nomem = new_rd_NoMem(irg);
365 ir_node *old_pred = get_Cmp_left(old_node);
366 ir_mode *in_mode = get_irn_mode(old_pred);
367 int in_bits = get_mode_size_bits(in_mode);
369 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
370 set_ia32_ls_mode(conv, tgt_mode);
372 set_ia32_am_support(conv, ia32_am_Source);
374 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
380 * SSE convert of an float node into a double node.
382 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg,
383 ir_graph *irg, ir_node *block,
384 ir_node *in, ir_node *old_node)
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
387 ir_node *nomem = new_rd_NoMem(irg);
389 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
390 set_ia32_am_support(conv, ia32_am_Source);
391 set_ia32_ls_mode(conv, mode_D);
392 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
397 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
398 ident *ia32_gen_fp_known_const(ia32_known_const_t kct) {
399 static const struct {
401 const char *ent_name;
402 const char *cnst_str;
403 } names [ia32_known_const_max] = {
404 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
405 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
406 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
407 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
409 static ir_entity *ent_cache[ia32_known_const_max];
411 const char *tp_name, *ent_name, *cnst_str;
419 ent_name = names[kct].ent_name;
420 if (! ent_cache[kct]) {
421 tp_name = names[kct].tp_name;
422 cnst_str = names[kct].cnst_str;
424 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
425 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
426 tp = new_type_primitive(new_id_from_str(tp_name), mode);
427 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
429 set_entity_ld_ident(ent, get_entity_ident(ent));
430 set_entity_visibility(ent, visibility_local);
431 set_entity_variability(ent, variability_constant);
432 set_entity_allocation(ent, allocation_static);
434 /* we create a new entity here: It's initialization must resist on the
436 rem = current_ir_graph;
437 current_ir_graph = get_const_code_irg();
438 cnst = new_Const(mode, tv);
439 current_ir_graph = rem;
441 set_atomic_ent_value(ent, cnst);
443 /* cache the entry */
444 ent_cache[kct] = ent;
447 return get_entity_ident(ent_cache[kct]);
452 * Prints the old node name on cg obst and returns a pointer to it.
454 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
455 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
457 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
458 obstack_1grow(isa->name_obst, 0);
459 return obstack_finish(isa->name_obst);
463 /* determine if one operator is an Imm */
464 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
466 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
467 else return is_ia32_Cnst(op2) ? op2 : NULL;
470 /* determine if one operator is not an Imm */
471 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
472 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
475 static void fold_immediate(ia32_transform_env_t *env, ir_node *node, int in1, int in2) {
479 if(! (env->cg->opt & IA32_OPT_IMMOPS))
482 left = get_irn_n(node, in1);
483 right = get_irn_n(node, in2);
484 if(!is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
485 /* we can only set right operand to immediate */
486 if(!is_ia32_commutative(node))
488 /* exchange left/right */
489 set_irn_n(node, in1, right);
490 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
491 copy_ia32_Immop_attr(node, left);
492 } else if(is_ia32_Cnst(right)) {
493 set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
494 copy_ia32_Immop_attr(node, right);
499 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
503 * Construct a standard binary operation, set AM and immediate if required.
505 * @param env The transformation environment
506 * @param op1 The first operand
507 * @param op2 The second operand
508 * @param func The node constructor function
509 * @return The constructed ia32 node.
511 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *node,
512 ir_node *op1, ir_node *op2,
513 construct_binop_func *func) {
514 ir_node *new_node = NULL;
515 ir_graph *irg = env->irg;
516 dbg_info *dbg = get_irn_dbg_info(node);
517 ir_node *block = transform_node(env, get_nodes_block(node));
518 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
519 ir_node *nomem = new_NoMem();
520 ir_node *new_op1 = transform_node(env, op1);
521 ir_node *new_op2 = transform_node(env, op2);
523 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
524 if(func == new_rd_ia32_Mul) {
525 set_ia32_am_support(new_node, ia32_am_Source);
527 set_ia32_am_support(new_node, ia32_am_Full);
530 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
531 if (is_op_commutative(get_irn_op(node))) {
532 set_ia32_commutative(new_node);
534 fold_immediate(env, new_node, 2, 3);
540 * Construct a standard binary operation, set AM and immediate if required.
542 * @param env The transformation environment
543 * @param op1 The first operand
544 * @param op2 The second operand
545 * @param func The node constructor function
546 * @return The constructed ia32 node.
548 static ir_node *gen_binop_float(ia32_transform_env_t *env, ir_node *node,
549 ir_node *op1, ir_node *op2,
550 construct_binop_func *func)
552 ir_node *new_node = NULL;
553 dbg_info *dbg = get_irn_dbg_info(node);
554 ir_graph *irg = env->irg;
555 ir_mode *mode = get_irn_mode(node);
556 ir_node *block = transform_node(env, get_nodes_block(node));
557 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
558 ir_node *nomem = new_NoMem();
559 ir_node *new_op1 = transform_node(env, op1);
560 ir_node *new_op2 = transform_node(env, op2);
562 new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
563 set_ia32_am_support(new_node, ia32_am_Source);
564 if (is_op_commutative(get_irn_op(node))) {
565 set_ia32_commutative(new_node);
567 if (USE_SSE2(env->cg)) {
568 set_ia32_ls_mode(new_node, mode);
571 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
578 * Construct a shift/rotate binary operation, sets AM and immediate if required.
580 * @param env The transformation environment
581 * @param op1 The first operand
582 * @param op2 The second operand
583 * @param func The node constructor function
584 * @return The constructed ia32 node.
586 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *node,
587 ir_node *op1, ir_node *op2,
588 construct_binop_func *func) {
589 ir_node *new_op = NULL;
590 ir_mode *mode = get_irn_mode(node);
591 dbg_info *dbg = get_irn_dbg_info(node);
592 ir_graph *irg = env->irg;
593 ir_node *block = transform_node(env, get_nodes_block(node));
594 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
595 ir_node *nomem = new_NoMem();
598 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
599 ir_node *new_op1 = transform_node(env, op1);
600 ir_node *new_op2 = transform_node(env, op2);
603 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
605 /* Check if immediate optimization is on and */
606 /* if it's an operation with immediate. */
607 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
608 expr_op = get_expr_op(new_op1, new_op2);
610 assert((expr_op || imm_op) && "invalid operands");
613 /* We have two consts here: not yet supported */
617 /* Limit imm_op within range imm8 */
619 tv = get_ia32_Immop_tarval(imm_op);
622 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
623 set_ia32_Immop_tarval(imm_op, tv);
630 /* integer operations */
632 /* This is shift/rot with const */
633 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
635 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
636 copy_ia32_Immop_attr(new_op, imm_op);
638 /* This is a normal shift/rot */
639 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
640 new_op = func(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
644 set_ia32_am_support(new_op, ia32_am_Dest);
646 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
648 set_ia32_emit_cl(new_op);
655 * Construct a standard unary operation, set AM and immediate if required.
657 * @param env The transformation environment
658 * @param op The operand
659 * @param func The node constructor function
660 * @return The constructed ia32 node.
662 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *node, ir_node *op,
663 construct_unop_func *func) {
664 ir_node *new_node = NULL;
665 ir_graph *irg = env->irg;
666 dbg_info *dbg = get_irn_dbg_info(node);
667 ir_node *block = transform_node(env, get_nodes_block(node));
668 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
669 ir_node *nomem = new_NoMem();
670 ir_node *new_op = transform_node(env, op);
671 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
673 new_node = func(dbg, irg, block, noreg, noreg, new_op, nomem);
674 DB((mod, LEVEL_1, "INT unop ..."));
675 set_ia32_am_support(new_node, ia32_am_Dest);
677 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env->cg, node));
684 * Creates an ia32 Add.
686 * @param env The transformation environment
687 * @return the created ia32 Add node
689 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *node) {
690 ir_node *new_op = NULL;
691 ir_graph *irg = env->irg;
692 dbg_info *dbg = get_irn_dbg_info(node);
693 ir_mode *mode = get_irn_mode(node);
694 ir_node *block = transform_node(env, get_nodes_block(node));
695 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
696 ir_node *nomem = new_NoMem();
697 ir_node *expr_op, *imm_op;
698 ir_node *op1 = get_Add_left(node);
699 ir_node *op2 = get_Add_right(node);
700 ir_node *new_op1 = transform_node(env, op1);
701 ir_node *new_op2 = transform_node(env, op2);
703 /* Check if immediate optimization is on and */
704 /* if it's an operation with immediate. */
705 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
706 expr_op = get_expr_op(new_op1, new_op2);
708 assert((expr_op || imm_op) && "invalid operands");
710 if (mode_is_float(mode)) {
712 if (USE_SSE2(env->cg))
713 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xAdd);
715 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
720 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
721 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
723 /* No expr_op means, that we have two const - one symconst and */
724 /* one tarval or another symconst - because this case is not */
725 /* covered by constant folding */
726 /* We need to check for: */
727 /* 1) symconst + const -> becomes a LEA */
728 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
729 /* linker doesn't support two symconsts */
731 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
732 /* this is the 2nd case */
733 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
734 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
735 set_ia32_am_flavour(new_op, ia32_am_OB);
736 set_ia32_am_support(new_op, ia32_am_Source);
737 set_ia32_op_type(new_op, ia32_AddrModeS);
739 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
740 } else if (tp1 == ia32_ImmSymConst) {
741 tarval *tv = get_ia32_Immop_tarval(new_op2);
742 long offs = get_tarval_long(tv);
744 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
745 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
747 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
748 add_ia32_am_offs_int(new_op, offs);
749 set_ia32_am_flavour(new_op, ia32_am_O);
750 set_ia32_am_support(new_op, ia32_am_Source);
751 set_ia32_op_type(new_op, ia32_AddrModeS);
752 } else if (tp2 == ia32_ImmSymConst) {
753 tarval *tv = get_ia32_Immop_tarval(new_op1);
754 long offs = get_tarval_long(tv);
756 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
757 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
759 add_ia32_am_offs_int(new_op, offs);
760 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
761 set_ia32_am_flavour(new_op, ia32_am_O);
762 set_ia32_am_support(new_op, ia32_am_Source);
763 set_ia32_op_type(new_op, ia32_AddrModeS);
765 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
766 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
767 tarval *restv = tarval_add(tv1, tv2);
769 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
771 new_op = new_rd_ia32_Const(dbg, irg, block);
772 set_ia32_Const_tarval(new_op, restv);
773 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
779 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
780 tarval_classification_t class_tv, class_negtv;
781 tarval *tv = get_ia32_Immop_tarval(imm_op);
783 /* optimize tarvals */
784 class_tv = classify_tarval(tv);
785 class_negtv = classify_tarval(tarval_neg(tv));
787 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
788 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
789 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
790 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
792 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
793 DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
794 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
801 /* This is a normal add */
802 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
805 set_ia32_am_support(new_op, ia32_am_Full);
806 set_ia32_commutative(new_op);
808 fold_immediate(env, new_op, 2, 3);
810 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
816 static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
817 ir_graph *irg = env->irg;
818 dbg_info *dbg = get_irn_dbg_info(node);
819 ir_node *block = transform_node(env, get_nodes_block(node));
820 ir_node *op1 = get_Mul_left(node);
821 ir_node *op2 = get_Mul_right(node);
822 ir_node *new_op1 = transform_node(env, op1);
823 ir_node *new_op2 = transform_node(env, op2);
824 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
825 ir_node *proj_EAX, *proj_EDX, *res;
828 res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
829 set_ia32_commutative(res);
830 set_ia32_am_support(res, ia32_am_Source);
832 /* imediates are not supported, so no fold_immediate */
833 proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
834 proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
838 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
846 * Creates an ia32 Mul.
848 * @param env The transformation environment
849 * @return the created ia32 Mul node
851 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
852 ir_node *op1 = get_Mul_left(node);
853 ir_node *op2 = get_Mul_right(node);
854 ir_mode *mode = get_irn_mode(node);
856 if (mode_is_float(mode)) {
858 if (USE_SSE2(env->cg))
859 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
861 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
864 // for the lower 32bit of the result it doesn't matter whether we use
865 // signed or unsigned multiplication so we use IMul as it has fewer
867 return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
871 * Creates an ia32 Mulh.
872 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
873 * this result while Mul returns the lower 32 bit.
875 * @param env The transformation environment
876 * @return the created ia32 Mulh node
878 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *node) {
879 ir_graph *irg = env->irg;
880 dbg_info *dbg = get_irn_dbg_info(node);
881 ir_node *block = transform_node(env, get_nodes_block(node));
882 ir_node *op1 = get_irn_n(node, 0);
883 ir_node *op2 = get_irn_n(node, 1);
884 ir_node *new_op1 = transform_node(env, op1);
885 ir_node *new_op2 = transform_node(env, op2);
886 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
887 ir_node *proj_EAX, *proj_EDX, *mulh;
888 ir_mode *mode = get_irn_mode(node);
891 assert(!mode_is_float(mode) && "Mulh with float not supported");
892 mulh = new_rd_ia32_Mulh(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
893 set_ia32_commutative(mulh);
894 set_ia32_am_support(mulh, ia32_am_Source);
896 /* imediates are not supported, so no fold_immediate */
897 proj_EAX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EAX);
898 proj_EDX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EDX);
902 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
910 * Creates an ia32 And.
912 * @param env The transformation environment
913 * @return The created ia32 And node
915 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *node) {
916 ir_node *op1 = get_And_left(node);
917 ir_node *op2 = get_And_right(node);
918 ir_mode *mode = get_irn_mode(node);
920 assert (! mode_is_float(mode));
921 return gen_binop(env, node, op1, op2, new_rd_ia32_And);
927 * Creates an ia32 Or.
929 * @param env The transformation environment
930 * @return The created ia32 Or node
932 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *node) {
933 ir_node *op1 = get_Or_left(node);
934 ir_node *op2 = get_Or_right(node);
935 ir_mode *mode = get_irn_mode(node);
937 assert (! mode_is_float(mode));
938 return gen_binop(env, node, op1, op2, new_rd_ia32_Or);
944 * Creates an ia32 Eor.
946 * @param env The transformation environment
947 * @return The created ia32 Eor node
949 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *node) {
950 ir_node *op1 = get_Eor_left(node);
951 ir_node *op2 = get_Eor_right(node);
952 ir_mode *mode = get_irn_mode(node);
954 assert(! mode_is_float(mode));
955 return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
961 * Creates an ia32 Max.
963 * @param env The transformation environment
964 * @return the created ia32 Max node
966 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *node) {
967 ir_graph *irg = env->irg;
969 ir_mode *mode = get_irn_mode(node);
970 dbg_info *dbg = get_irn_dbg_info(node);
971 ir_node *block = transform_node(env, get_nodes_block(node));
972 ir_node *op1 = get_irn_n(node, 0);
973 ir_node *op2 = get_irn_n(node, 1);
974 ir_node *new_op1 = transform_node(env, op1);
975 ir_node *new_op2 = transform_node(env, op2);
976 ir_mode *op_mode = get_irn_mode(op1);
978 assert(get_mode_size_bits(mode) == 32);
980 if (mode_is_float(mode)) {
982 if (USE_SSE2(env->cg))
983 new_op = gen_binop_float(env, node, new_op1, new_op2, new_rd_ia32_xMax);
989 long pnc = pn_Cmp_Gt;
990 if(!mode_is_signed(op_mode)) {
991 pnc |= ia32_pn_Cmp_Unsigned;
993 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
994 set_ia32_pncode(new_op, pnc);
995 set_ia32_am_support(new_op, ia32_am_None);
997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1003 * Creates an ia32 Min.
1005 * @param env The transformation environment
1006 * @return the created ia32 Min node
1008 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *node) {
1009 ir_graph *irg = env->irg;
1011 ir_mode *mode = get_irn_mode(node);
1012 dbg_info *dbg = get_irn_dbg_info(node);
1013 ir_node *block = transform_node(env, get_nodes_block(node));
1014 ir_node *op1 = get_irn_n(node, 0);
1015 ir_node *op2 = get_irn_n(node, 1);
1016 ir_node *new_op1 = transform_node(env, op1);
1017 ir_node *new_op2 = transform_node(env, op2);
1018 ir_mode *op_mode = get_irn_mode(op1);
1020 assert(get_mode_size_bits(mode) == 32);
1022 if (mode_is_float(mode)) {
1024 if (USE_SSE2(env->cg))
1025 new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMin);
1031 long pnc = pn_Cmp_Lt;
1032 if(!mode_is_signed(op_mode)) {
1033 pnc |= ia32_pn_Cmp_Unsigned;
1035 new_op = new_rd_ia32_CmpCMov(dbg, irg, block, new_op1, new_op2, new_op1, new_op2);
1036 set_ia32_pncode(new_op, pnc);
1037 set_ia32_am_support(new_op, ia32_am_None);
1039 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1046 * Creates an ia32 Sub.
1048 * @param env The transformation environment
1049 * @return The created ia32 Sub node
1051 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *node) {
1052 ir_node *new_op = NULL;
1053 ir_graph *irg = env->irg;
1054 dbg_info *dbg = get_irn_dbg_info(node);
1055 ir_mode *mode = get_irn_mode(node);
1056 ir_node *block = transform_node(env, get_nodes_block(node));
1057 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1058 ir_node *nomem = new_NoMem();
1059 ir_node *op1 = get_Sub_left(node);
1060 ir_node *op2 = get_Sub_right(node);
1061 ir_node *new_op1 = transform_node(env, op1);
1062 ir_node *new_op2 = transform_node(env, op2);
1063 ir_node *expr_op, *imm_op;
1065 /* Check if immediate optimization is on and */
1066 /* if it's an operation with immediate. */
1067 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1068 expr_op = get_expr_op(new_op1, new_op2);
1070 assert((expr_op || imm_op) && "invalid operands");
1072 if (mode_is_float(mode)) {
1074 if (USE_SSE2(env->cg))
1075 return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
1077 return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
1082 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1083 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1085 /* No expr_op means, that we have two const - one symconst and */
1086 /* one tarval or another symconst - because this case is not */
1087 /* covered by constant folding */
1088 /* We need to check for: */
1089 /* 1) symconst - const -> becomes a LEA */
1090 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1091 /* linker doesn't support two symconsts */
1092 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1093 /* this is the 2nd case */
1094 new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
1095 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1096 set_ia32_am_sc_sign(new_op);
1097 set_ia32_am_flavour(new_op, ia32_am_OB);
1099 DBG_OPT_LEA3(op1, op2, node, new_op);
1100 } else if (tp1 == ia32_ImmSymConst) {
1101 tarval *tv = get_ia32_Immop_tarval(new_op2);
1102 long offs = get_tarval_long(tv);
1104 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1105 DBG_OPT_LEA3(op1, op2, node, new_op);
1107 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1108 add_ia32_am_offs_int(new_op, -offs);
1109 set_ia32_am_flavour(new_op, ia32_am_O);
1110 set_ia32_am_support(new_op, ia32_am_Source);
1111 set_ia32_op_type(new_op, ia32_AddrModeS);
1112 } else if (tp2 == ia32_ImmSymConst) {
1113 tarval *tv = get_ia32_Immop_tarval(new_op1);
1114 long offs = get_tarval_long(tv);
1116 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
1117 DBG_OPT_LEA3(op1, op2, node, new_op);
1119 add_ia32_am_offs_int(new_op, offs);
1120 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1121 set_ia32_am_sc_sign(new_op);
1122 set_ia32_am_flavour(new_op, ia32_am_O);
1123 set_ia32_am_support(new_op, ia32_am_Source);
1124 set_ia32_op_type(new_op, ia32_AddrModeS);
1126 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1127 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1128 tarval *restv = tarval_sub(tv1, tv2);
1130 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1132 new_op = new_rd_ia32_Const(dbg, irg, block);
1133 set_ia32_Const_tarval(new_op, restv);
1134 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1137 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1139 } else if (imm_op) {
1140 if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1141 tarval_classification_t class_tv, class_negtv;
1142 tarval *tv = get_ia32_Immop_tarval(imm_op);
1144 /* optimize tarvals */
1145 class_tv = classify_tarval(tv);
1146 class_negtv = classify_tarval(tarval_neg(tv));
1148 if (class_tv == TV_CLASSIFY_ONE) {
1149 DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
1150 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
1151 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1153 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1154 DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
1155 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
1156 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1162 /* This is a normal sub */
1163 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1165 /* set AM support */
1166 set_ia32_am_support(new_op, ia32_am_Full);
1168 fold_immediate(env, new_op, 2, 3);
1170 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1178 * Generates an ia32 DivMod with additional infrastructure for the
1179 * register allocator if needed.
1181 * @param env The transformation environment
1182 * @param dividend -no comment- :)
1183 * @param divisor -no comment- :)
1184 * @param dm_flav flavour_Div/Mod/DivMod
1185 * @return The created ia32 DivMod node
1187 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *node,
1188 ir_node *dividend, ir_node *divisor,
1189 ia32_op_flavour_t dm_flav) {
1190 ir_graph *irg = env->irg;
1191 dbg_info *dbg = get_irn_dbg_info(node);
1192 ir_mode *mode = get_irn_mode(node);
1193 ir_node *block = transform_node(env, get_nodes_block(node));
1194 ir_node *res, *proj_div, *proj_mod;
1195 ir_node *edx_node, *cltd;
1196 ir_node *in_keep[1];
1197 ir_node *mem, *new_mem;
1198 ir_node *projs[pn_DivMod_max];
1199 ir_node *new_dividend = transform_node(env, dividend);
1200 ir_node *new_divisor = transform_node(env, divisor);
1202 ia32_collect_Projs(node, projs, pn_DivMod_max);
1206 mem = get_Div_mem(node);
1207 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
1210 mem = get_Mod_mem(node);
1211 mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
1213 case flavour_DivMod:
1214 mem = get_DivMod_mem(node);
1215 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1216 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1217 mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
1222 new_mem = transform_node(env, mem);
1224 if (mode_is_signed(mode)) {
1225 /* in signed mode, we need to sign extend the dividend */
1226 cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
1227 new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1228 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1230 edx_node = new_rd_ia32_Const(dbg, irg, block);
1231 add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
1232 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1235 if(mode_is_signed(mode)) {
1236 res = new_rd_ia32_IDiv(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
1238 res = new_rd_ia32_Div(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
1240 set_ia32_n_res(res, 2);
1242 /* Only one proj is used -> We must add a second proj and */
1243 /* connect this one to a Keep node to eat up the second */
1244 /* destroyed register. */
1245 /* We also renumber the Firm projs into ia32 projs. */
1247 switch (get_irn_opcode(node)) {
1249 /* add Proj-Keep for mod res */
1250 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1251 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1254 /* add Proj-Keep for div res */
1255 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1256 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1259 /* check, which Proj-Keep, we need to add */
1260 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1261 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1263 if (proj_div && proj_mod) {
1264 /* nothing to be done */
1266 else if (! proj_div && ! proj_mod) {
1267 assert(0 && "Missing DivMod result proj");
1269 else if (! proj_div) {
1270 /* We have only mod result: add div res Proj-Keep */
1271 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1272 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1275 /* We have only div result: add mod res Proj-Keep */
1276 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1277 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1281 assert(0 && "Div, Mod, or DivMod expected.");
1285 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1292 * Wrapper for generate_DivMod. Sets flavour_Mod.
1294 * @param env The transformation environment
1296 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *node) {
1297 return generate_DivMod(env, node, get_Mod_left(node),
1298 get_Mod_right(node), flavour_Mod);
1302 * Wrapper for generate_DivMod. Sets flavour_Div.
1304 * @param env The transformation environment
1306 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *node) {
1307 return generate_DivMod(env, node, get_Div_left(node),
1308 get_Div_right(node), flavour_Div);
1312 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1314 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *node) {
1315 return generate_DivMod(env, node, get_DivMod_left(node),
1316 get_DivMod_right(node), flavour_DivMod);
1322 * Creates an ia32 floating Div.
1324 * @param env The transformation environment
1325 * @return The created ia32 xDiv node
1327 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *node) {
1328 ir_graph *irg = env->irg;
1329 dbg_info *dbg = get_irn_dbg_info(node);
1330 ir_node *block = transform_node(env, get_nodes_block(node));
1331 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1333 ir_node *nomem = new_rd_NoMem(env->irg);
1334 ir_node *op1 = get_Quot_left(node);
1335 ir_node *op2 = get_Quot_right(node);
1336 ir_node *new_op1 = transform_node(env, op1);
1337 ir_node *new_op2 = transform_node(env, op2);
1340 if (USE_SSE2(env->cg)) {
1341 ir_mode *mode = get_irn_mode(op1);
1342 if (is_ia32_xConst(new_op2)) {
1343 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
1344 set_ia32_am_support(new_op, ia32_am_None);
1345 copy_ia32_Immop_attr(new_op, new_op2);
1347 new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1348 // Matze: disabled for now, spillslot coalescer fails
1349 //set_ia32_am_support(new_op, ia32_am_Source);
1351 set_ia32_ls_mode(new_op, mode);
1353 new_op = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1354 // Matze: disabled for now (spillslot coalescer fails)
1355 //set_ia32_am_support(new_op, ia32_am_Source);
1357 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1363 * Creates an ia32 Shl.
1365 * @param env The transformation environment
1366 * @return The created ia32 Shl node
1368 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *node) {
1369 return gen_shift_binop(env, node, get_Shl_left(node), get_Shl_right(node),
1376 * Creates an ia32 Shr.
1378 * @param env The transformation environment
1379 * @return The created ia32 Shr node
1381 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *node) {
1382 return gen_shift_binop(env, node, get_Shr_left(node),
1383 get_Shr_right(node), new_rd_ia32_Shr);
1389 * Creates an ia32 Sar.
1391 * @param env The transformation environment
1392 * @return The created ia32 Shrs node
1394 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
1395 return gen_shift_binop(env, node, get_Shrs_left(node),
1396 get_Shrs_right(node), new_rd_ia32_Sar);
1402 * Creates an ia32 RotL.
1404 * @param env The transformation environment
1405 * @param op1 The first operator
1406 * @param op2 The second operator
1407 * @return The created ia32 RotL node
1409 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
1410 ir_node *op1, ir_node *op2) {
1411 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
1417 * Creates an ia32 RotR.
1418 * NOTE: There is no RotR with immediate because this would always be a RotL
1419 * "imm-mode_size_bits" which can be pre-calculated.
1421 * @param env The transformation environment
1422 * @param op1 The first operator
1423 * @param op2 The second operator
1424 * @return The created ia32 RotR node
1426 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
1428 return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
1434 * Creates an ia32 RotR or RotL (depending on the found pattern).
1436 * @param env The transformation environment
1437 * @return The created ia32 RotL or RotR node
1439 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *node) {
1440 ir_node *rotate = NULL;
1441 ir_node *op1 = get_Rot_left(node);
1442 ir_node *op2 = get_Rot_right(node);
1444 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1445 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1446 that means we can create a RotR instead of an Add and a RotL */
1448 if (get_irn_op(op2) == op_Add) {
1450 ir_node *left = get_Add_left(add);
1451 ir_node *right = get_Add_right(add);
1452 if (is_Const(right)) {
1453 tarval *tv = get_Const_tarval(right);
1454 ir_mode *mode = get_irn_mode(node);
1455 long bits = get_mode_size_bits(mode);
1457 if (get_irn_op(left) == op_Minus &&
1458 tarval_is_long(tv) &&
1459 get_tarval_long(tv) == bits)
1461 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1462 rotate = gen_RotR(env, node, op1, get_Minus_op(left));
1467 if (rotate == NULL) {
1468 rotate = gen_RotL(env, node, op1, op2);
1477 * Transforms a Minus node.
1479 * @param env The transformation environment
1480 * @param op The Minus operand
1481 * @return The created ia32 Minus node
1483 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *node, ir_node *op) {
1486 ir_graph *irg = env->irg;
1487 dbg_info *dbg = get_irn_dbg_info(node);
1488 ir_node *block = transform_node(env, get_nodes_block(node));
1489 ir_mode *mode = get_irn_mode(node);
1492 if (mode_is_float(mode)) {
1493 ir_node *new_op = transform_node(env, op);
1495 if (USE_SSE2(env->cg)) {
1496 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1497 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1498 ir_node *nomem = new_rd_NoMem(irg);
1500 res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1502 size = get_mode_size_bits(mode);
1503 name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1505 set_ia32_am_sc(res, name);
1506 set_ia32_op_type(res, ia32_AddrModeS);
1507 set_ia32_ls_mode(res, mode);
1509 res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
1512 res = gen_unop(env, node, op, new_rd_ia32_Neg);
1515 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1521 * Transforms a Minus node.
1523 * @param env The transformation environment
1524 * @return The created ia32 Minus node
1526 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *node) {
1527 return gen_Minus_ex(env, node, get_Minus_op(node));
1532 * Transforms a Not node.
1534 * @param env The transformation environment
1535 * @return The created ia32 Not node
1537 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *node) {
1538 ir_mode *mode = get_irn_mode(node);
1539 ir_node *op = get_Not_op(node);
1541 assert (! mode_is_float(mode));
1542 return gen_unop(env, node, op, new_rd_ia32_Not);
1548 * Transforms an Abs node.
1550 * @param env The transformation environment
1551 * @return The created ia32 Abs node
1553 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *node) {
1554 ir_node *res, *p_eax, *p_edx;
1555 ir_graph *irg = env->irg;
1556 dbg_info *dbg = get_irn_dbg_info(node);
1557 ir_node *block = transform_node(env, get_nodes_block(node));
1558 ir_mode *mode = get_irn_mode(node);
1559 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1560 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1561 ir_node *nomem = new_NoMem();
1562 ir_node *op = get_Abs_op(node);
1563 ir_node *new_op = transform_node(env, op);
1567 if (mode_is_float(mode)) {
1569 if (USE_SSE2(env->cg)) {
1570 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1572 size = get_mode_size_bits(mode);
1573 name = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1575 set_ia32_am_sc(res, name);
1577 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1579 set_ia32_op_type(res, ia32_AddrModeS);
1580 set_ia32_ls_mode(res, mode);
1583 res = new_rd_ia32_vfabs(dbg, irg, block, new_op);
1584 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1588 res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
1589 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1591 p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
1592 p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
1594 res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1595 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1597 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1607 * Transforms a Load.
1609 * @param env The transformation environment
1610 * @return the created ia32 Load node
1612 static ir_node *gen_Load(ia32_transform_env_t *env, ir_node *node) {
1613 ir_graph *irg = env->irg;
1614 dbg_info *dbg = get_irn_dbg_info(node);
1615 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1616 ir_mode *mode = get_Load_mode(node);
1617 ir_node *block = transform_node(env, get_nodes_block(node));
1618 ir_node *ptr = get_Load_ptr(node);
1619 ir_node *new_ptr = transform_node(env, ptr);
1620 ir_node *lptr = new_ptr;
1621 ir_node *mem = get_Load_mem(node);
1622 ir_node *new_mem = transform_node(env, mem);
1625 ia32_am_flavour_t am_flav = ia32_am_B;
1626 ir_node *projs[pn_Load_max];
1628 ia32_collect_Projs(node, projs, pn_Load_max);
1631 check for special case: the loaded value might not be used (optimized, volatile, ...)
1632 we add a Proj + Keep for volatile loads and ignore all other cases
1634 if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1635 /* add a result proj and a Keep to produce a pseudo use */
1636 ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
1637 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
1640 /* address might be a constant (symconst or absolute address) */
1641 if (is_ia32_Const(new_ptr)) {
1646 if (mode_is_float(mode)) {
1648 if (USE_SSE2(env->cg)) {
1649 new_op = new_rd_ia32_xLoad(dbg, irg, block, lptr, noreg, new_mem);
1651 new_op = new_rd_ia32_vfld(dbg, irg, block, lptr, noreg, new_mem);
1654 new_op = new_rd_ia32_Load(dbg, irg, block, lptr, noreg, new_mem);
1657 /* base is a constant address */
1659 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1660 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1661 am_flav = ia32_am_N;
1663 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1664 long offs = get_tarval_long(tv);
1666 add_ia32_am_offs_int(new_op, offs);
1667 am_flav = ia32_am_O;
1671 set_ia32_am_support(new_op, ia32_am_Source);
1672 set_ia32_op_type(new_op, ia32_AddrModeS);
1673 set_ia32_am_flavour(new_op, am_flav);
1674 set_ia32_ls_mode(new_op, mode);
1676 /* make sure we are scheduled behind the intial IncSP/Barrier
1677 * to avoid spills being placed before it
1679 if(block == get_irg_start_block(irg)) {
1680 add_irn_dep(new_op, get_irg_frame(irg));
1683 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1691 * Transforms a Store.
1693 * @param env The transformation environment
1694 * @return the created ia32 Store node
1696 static ir_node *gen_Store(ia32_transform_env_t *env, ir_node *node) {
1697 ir_graph *irg = env->irg;
1698 dbg_info *dbg = get_irn_dbg_info(node);
1699 ir_node *block = transform_node(env, get_nodes_block(node));
1700 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1701 ir_node *ptr = get_Store_ptr(node);
1702 ir_node *new_ptr = transform_node(env, ptr);
1703 ir_node *sptr = new_ptr;
1704 ir_node *val = get_Store_value(node);
1705 ir_node *new_val = transform_node(env, val);
1706 ir_node *mem = get_Store_mem(node);
1707 ir_node *new_mem = transform_node(env, mem);
1708 ir_mode *mode = get_irn_mode(val);
1709 ir_node *sval = new_val;
1712 ia32_am_flavour_t am_flav = ia32_am_B;
1714 if (is_ia32_Const(new_val)) {
1715 assert(!mode_is_float(mode));
1719 /* address might be a constant (symconst or absolute address) */
1720 if (is_ia32_Const(new_ptr)) {
1725 if (mode_is_float(mode)) {
1727 if (USE_SSE2(env->cg)) {
1728 new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
1730 new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
1732 } else if (get_mode_size_bits(mode) == 8) {
1733 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
1735 new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
1738 /* stored const is an immediate value */
1739 if (is_ia32_Const(new_val)) {
1740 assert(!mode_is_float(mode));
1741 copy_ia32_Immop_attr(new_op, new_val);
1744 /* base is an constant address */
1746 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1747 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1748 am_flav = ia32_am_N;
1750 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1751 long offs = get_tarval_long(tv);
1753 add_ia32_am_offs_int(new_op, offs);
1754 am_flav = ia32_am_O;
1758 set_ia32_am_support(new_op, ia32_am_Dest);
1759 set_ia32_op_type(new_op, ia32_AddrModeD);
1760 set_ia32_am_flavour(new_op, am_flav);
1761 set_ia32_ls_mode(new_op, mode);
1763 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1771 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1773 * @param env The transformation environment
1774 * @return The transformed node.
1776 static ir_node *gen_Cond(ia32_transform_env_t *env, ir_node *node) {
1777 ir_graph *irg = env->irg;
1778 dbg_info *dbg = get_irn_dbg_info(node);
1779 ir_node *block = transform_node(env, get_nodes_block(node));
1780 ir_node *sel = get_Cond_selector(node);
1781 ir_mode *sel_mode = get_irn_mode(sel);
1782 ir_node *res = NULL;
1783 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1784 ir_node *cnst, *expr;
1786 if (is_Proj(sel) && sel_mode == mode_b) {
1787 ir_node *nomem = new_NoMem();
1788 ir_node *pred = get_Proj_pred(sel);
1789 ir_node *cmp_a = get_Cmp_left(pred);
1790 ir_node *new_cmp_a = transform_node(env, cmp_a);
1791 ir_node *cmp_b = get_Cmp_right(pred);
1792 ir_node *new_cmp_b = transform_node(env, cmp_b);
1793 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1795 int pnc = get_Proj_proj(sel);
1796 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1797 pnc |= ia32_pn_Cmp_Unsigned;
1800 /* check if we can use a CondJmp with immediate */
1801 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1802 expr = get_expr_op(new_cmp_a, new_cmp_b);
1804 if (cnst != NULL && expr != NULL) {
1805 /* immop has to be the right operand, we might need to flip pnc */
1806 if(cnst != new_cmp_b) {
1807 pnc = get_inversed_pnc(pnc);
1810 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1811 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1812 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1814 /* a Cmp A =/!= 0 */
1815 ir_node *op1 = expr;
1816 ir_node *op2 = expr;
1819 /* check, if expr is an only once used And operation */
1820 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1821 op1 = get_irn_n(expr, 2);
1822 op2 = get_irn_n(expr, 3);
1824 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1826 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1827 set_ia32_pncode(res, pnc);
1830 copy_ia32_Immop_attr(res, expr);
1833 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1838 if (mode_is_float(cmp_mode)) {
1840 if (USE_SSE2(env->cg)) {
1841 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1842 set_ia32_ls_mode(res, cmp_mode);
1848 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1850 copy_ia32_Immop_attr(res, cnst);
1853 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1855 if (mode_is_float(cmp_mode)) {
1857 if (USE_SSE2(env->cg)) {
1858 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1859 set_ia32_ls_mode(res, cmp_mode);
1862 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1863 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1864 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1868 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1869 set_ia32_commutative(res);
1873 set_ia32_pncode(res, pnc);
1874 // Matze: disabled for now, because the default collect_spills_walker
1875 // is not able to detect the mode of the spilled value
1876 // moreover, the lea optimize phase freely exchanges left/right
1877 // without updating the pnc
1878 //set_ia32_am_support(res, ia32_am_Source);
1881 /* determine the smallest switch case value */
1882 int switch_min = INT_MAX;
1883 const ir_edge_t *edge;
1884 ir_node *new_sel = transform_node(env, sel);
1886 foreach_out_edge(node, edge) {
1887 int pn = get_Proj_proj(get_edge_src_irn(edge));
1888 switch_min = pn < switch_min ? pn : switch_min;
1892 /* if smallest switch case is not 0 we need an additional sub */
1893 res = new_rd_ia32_Lea(dbg, irg, block, new_sel, noreg);
1894 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1895 add_ia32_am_offs_int(res, -switch_min);
1896 set_ia32_am_flavour(res, ia32_am_OB);
1897 set_ia32_am_support(res, ia32_am_Source);
1898 set_ia32_op_type(res, ia32_AddrModeS);
1901 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : new_sel, mode_T);
1902 set_ia32_pncode(res, get_Cond_defaultProj(node));
1905 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1912 * Transforms a CopyB node.
1914 * @param env The transformation environment
1915 * @return The transformed node.
1917 static ir_node *gen_CopyB(ia32_transform_env_t *env, ir_node *node) {
1918 ir_node *res = NULL;
1919 ir_graph *irg = env->irg;
1920 dbg_info *dbg = get_irn_dbg_info(node);
1921 ir_node *block = transform_node(env, get_nodes_block(node));
1922 ir_node *src = get_CopyB_src(node);
1923 ir_node *new_src = transform_node(env, src);
1924 ir_node *dst = get_CopyB_dst(node);
1925 ir_node *new_dst = transform_node(env, dst);
1926 ir_node *mem = get_CopyB_mem(node);
1927 ir_node *new_mem = transform_node(env, mem);
1928 int size = get_type_size_bytes(get_CopyB_type(node));
1929 ir_mode *dst_mode = get_irn_mode(dst);
1930 ir_mode *src_mode = get_irn_mode(src);
1934 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1935 /* then we need the size explicitly in ECX. */
1936 if (size >= 32 * 4) {
1937 rem = size & 0x3; /* size % 4 */
1940 res = new_rd_ia32_Const(dbg, irg, block);
1941 add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
1942 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1944 res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
1945 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1947 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1948 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1949 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1950 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1951 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1954 res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
1955 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1957 /* ok: now attach Proj's because movsd will destroy esi and edi */
1958 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1959 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1960 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1963 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
1971 * Transforms a Mux node into CMov.
1973 * @param env The transformation environment
1974 * @return The transformed node.
1976 static ir_node *gen_Mux(ia32_transform_env_t *env, ir_node *node) {
1977 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1978 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1980 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1986 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1987 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1988 ir_node *psi_default);
1991 * Transforms a Psi node into CMov.
1993 * @param env The transformation environment
1994 * @return The transformed node.
1996 static ir_node *gen_Psi(ia32_transform_env_t *env, ir_node *node) {
1997 ia32_code_gen_t *cg = env->cg;
1998 ir_graph *irg = env->irg;
1999 dbg_info *dbg = get_irn_dbg_info(node);
2000 ir_mode *mode = get_irn_mode(node);
2001 ir_node *block = transform_node(env, get_nodes_block(node));
2002 ir_node *cmp_proj = get_Mux_sel(node);
2003 ir_node *psi_true = get_Psi_val(node, 0);
2004 ir_node *psi_default = get_Psi_default(node);
2005 ir_node *new_psi_true = transform_node(env, psi_true);
2006 ir_node *new_psi_default = transform_node(env, psi_default);
2007 ir_node *noreg = ia32_new_NoReg_gp(cg);
2008 ir_node *nomem = new_rd_NoMem(irg);
2009 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2010 ir_node *new_cmp_a, *new_cmp_b;
2014 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2016 cmp = get_Proj_pred(cmp_proj);
2017 cmp_a = get_Cmp_left(cmp);
2018 cmp_b = get_Cmp_right(cmp);
2019 cmp_mode = get_irn_mode(cmp_a);
2020 new_cmp_a = transform_node(env, cmp_a);
2021 new_cmp_b = transform_node(env, cmp_b);
2023 pnc = get_Proj_proj(cmp_proj);
2024 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2025 pnc |= ia32_pn_Cmp_Unsigned;
2028 if (mode_is_float(mode)) {
2029 /* floating point psi */
2032 /* 1st case: compare operands are float too */
2034 /* psi(cmp(a, b), t, f) can be done as: */
2035 /* tmp = cmp a, b */
2036 /* tmp2 = t and tmp */
2037 /* tmp3 = f and not tmp */
2038 /* res = tmp2 or tmp3 */
2040 /* in case the compare operands are int, we move them into xmm register */
2041 if (! mode_is_float(get_irn_mode(cmp_a))) {
2042 new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_D);
2043 new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_D);
2045 pnc |= 8; /* transform integer compare to fp compare */
2048 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2049 set_ia32_pncode(new_op, pnc);
2050 set_ia32_am_support(new_op, ia32_am_Source);
2051 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2053 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2054 set_ia32_am_support(and1, ia32_am_None);
2055 set_ia32_commutative(and1);
2056 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2058 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2059 set_ia32_am_support(and2, ia32_am_None);
2060 set_ia32_commutative(and2);
2061 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2063 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
2064 set_ia32_am_support(new_op, ia32_am_None);
2065 set_ia32_commutative(new_op);
2066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2070 new_op = new_rd_ia32_vfCMov(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2071 set_ia32_pncode(new_op, pnc);
2072 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2077 construct_binop_func *set_func = NULL;
2078 cmov_func_t *cmov_func = NULL;
2080 if (mode_is_float(get_irn_mode(cmp_a))) {
2081 /* 1st case: compare operands are floats */
2086 set_func = new_rd_ia32_xCmpSet;
2087 cmov_func = new_rd_ia32_xCmpCMov;
2091 set_func = new_rd_ia32_vfCmpSet;
2092 cmov_func = new_rd_ia32_vfCmpCMov;
2095 pnc &= ~0x8; /* fp compare -> int compare */
2098 /* 2nd case: compare operand are integer too */
2099 set_func = new_rd_ia32_CmpSet;
2100 cmov_func = new_rd_ia32_CmpCMov;
2103 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2104 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2105 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2106 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2107 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2108 set_ia32_pncode(new_op, pnc);
2110 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2111 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2112 /* we invert condition and set default to 0 */
2113 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, new_cmp_a);
2114 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2117 /* otherwise: use CMOVcc */
2118 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2119 set_ia32_pncode(new_op, pnc);
2122 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2125 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2126 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2127 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2128 set_ia32_pncode(new_op, pnc);
2129 set_ia32_am_support(new_op, ia32_am_Source);
2131 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2132 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2133 /* we invert condition and set default to 0 */
2134 new_op = gen_binop(env, node, cmp_a, cmp_b, set_func);
2135 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2136 set_ia32_am_support(new_op, ia32_am_Source);
2139 /* otherwise: use CMOVcc */
2140 new_op = cmov_func(dbg, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2141 set_ia32_pncode(new_op, pnc);
2142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2152 * Following conversion rules apply:
2156 * 1) n bit -> m bit n > m (downscale)
2158 * 2) n bit -> m bit n == m (sign change)
2160 * 3) n bit -> m bit n < m (upscale)
2161 * a) source is signed: movsx
2162 * b) source is unsigned: and with lower bits sets
2166 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2170 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2174 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2175 * x87 is mode_E internally, conversions happen only at load and store
2176 * in non-strict semantic
2180 * Create a conversion from x87 state register to general purpose.
2182 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_node *node) {
2183 ia32_code_gen_t *cg = env->cg;
2184 ir_graph *irg = env->irg;
2185 dbg_info *dbg = get_irn_dbg_info(node);
2186 ir_node *block = transform_node(env, get_nodes_block(node));
2187 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2188 ir_node *op = get_Conv_op(node);
2189 ir_node *new_op = transform_node(env, op);
2190 ir_node *fist, *load;
2193 fist = new_rd_ia32_vfist(dbg, irg, block, get_irg_frame(irg), noreg, new_op, new_NoMem());
2195 set_ia32_use_frame(fist);
2196 set_ia32_am_support(fist, ia32_am_Dest);
2197 set_ia32_op_type(fist, ia32_AddrModeD);
2198 set_ia32_am_flavour(fist, ia32_am_B);
2199 set_ia32_ls_mode(fist, mode_Iu);
2200 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2203 load = new_rd_ia32_Load(dbg, irg, block, get_irg_frame(irg), noreg, fist);
2205 set_ia32_use_frame(load);
2206 set_ia32_am_support(load, ia32_am_Source);
2207 set_ia32_op_type(load, ia32_AddrModeS);
2208 set_ia32_am_flavour(load, ia32_am_B);
2209 set_ia32_ls_mode(load, mode_Iu);
2210 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2212 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2216 * Create a conversion from general purpose to x87 register
2218 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_node *node, ir_mode *src_mode) {
2219 ia32_code_gen_t *cg = env->cg;
2220 ir_graph *irg = env->irg;
2221 dbg_info *dbg = get_irn_dbg_info(node);
2222 ir_mode *mode = get_irn_mode(node);
2223 ir_node *block = transform_node(env, get_nodes_block(node));
2224 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2225 ir_node *nomem = new_NoMem();
2226 ir_node *op = get_Conv_op(node);
2227 ir_node *new_op = transform_node(env, op);
2228 ir_node *fild, *store;
2231 /* first convert to 32 bit if necessary */
2232 src_bits = get_mode_size_bits(src_mode);
2233 if (src_bits == 8) {
2234 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2235 set_ia32_am_support(new_op, ia32_am_Source);
2236 set_ia32_ls_mode(new_op, src_mode);
2237 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2238 } else if (src_bits < 32) {
2239 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2240 set_ia32_am_support(new_op, ia32_am_Source);
2241 set_ia32_ls_mode(new_op, src_mode);
2242 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2246 store = new_rd_ia32_Store(dbg, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2248 set_ia32_use_frame(store);
2249 set_ia32_am_support(store, ia32_am_Dest);
2250 set_ia32_op_type(store, ia32_AddrModeD);
2251 set_ia32_am_flavour(store, ia32_am_OB);
2252 set_ia32_ls_mode(store, mode_Iu);
2255 fild = new_rd_ia32_vfild(dbg, irg, block, get_irg_frame(irg), noreg, store);
2257 set_ia32_use_frame(fild);
2258 set_ia32_am_support(fild, ia32_am_Source);
2259 set_ia32_op_type(fild, ia32_AddrModeS);
2260 set_ia32_am_flavour(fild, ia32_am_OB);
2261 set_ia32_ls_mode(fild, mode);
2263 return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
2267 * Transforms a Conv node.
2269 * @param env The transformation environment
2270 * @return The created ia32 Conv node
2272 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *node) {
2273 ir_graph *irg = env->irg;
2274 dbg_info *dbg = get_irn_dbg_info(node);
2275 ir_node *op = get_Conv_op(node);
2276 ir_mode *src_mode = get_irn_mode(op);
2277 ir_mode *tgt_mode = get_irn_mode(node);
2278 int src_bits = get_mode_size_bits(src_mode);
2279 int tgt_bits = get_mode_size_bits(tgt_mode);
2280 ir_node *block = transform_node(env, get_nodes_block(node));
2282 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2283 ir_node *nomem = new_rd_NoMem(irg);
2284 ir_node *new_op = transform_node(env, op);
2285 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2287 if (src_mode == tgt_mode) {
2288 /* this should be optimized already, but who knows... */
2289 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2290 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2294 if (mode_is_float(src_mode)) {
2295 /* we convert from float ... */
2296 if (mode_is_float(tgt_mode)) {
2298 if (USE_SSE2(env->cg)) {
2299 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2300 res = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2301 set_ia32_ls_mode(res, tgt_mode);
2303 // Matze: TODO what about strict convs?
2304 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2309 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2310 if (USE_SSE2(env->cg)) {
2311 res = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2312 set_ia32_ls_mode(res, src_mode);
2314 return gen_x87_fp_to_gp(env, node);
2318 /* we convert from int ... */
2319 if (mode_is_float(tgt_mode)) {
2322 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2323 if (USE_SSE2(env->cg)) {
2324 res = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, new_op, nomem);
2325 set_ia32_ls_mode(res, tgt_mode);
2326 if(src_bits == 32) {
2327 set_ia32_am_support(res, ia32_am_Source);
2330 return gen_x87_gp_to_fp(env, node, src_mode);
2334 ir_mode *smaller_mode;
2337 if (src_bits == tgt_bits) {
2338 DB((mod, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2342 if(src_bits < tgt_bits) {
2343 smaller_mode = src_mode;
2344 smaller_bits = src_bits;
2346 smaller_mode = tgt_mode;
2347 smaller_bits = tgt_bits;
2350 // The following is not correct, we can't change the mode,
2351 // maybe others are using the load too
2352 // better move this to a separate phase!
2355 if(is_Proj(new_op)) {
2356 /* load operations do already sign/zero extend, so we have
2357 * nothing left to do */
2358 ir_node *pred = get_Proj_pred(new_op);
2359 if(is_ia32_Load(pred)) {
2360 set_ia32_ls_mode(pred, smaller_mode);
2366 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2367 if (smaller_bits == 8) {
2368 res = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, new_op, nomem);
2369 set_ia32_ls_mode(res, smaller_mode);
2371 res = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, new_op, nomem);
2372 set_ia32_ls_mode(res, smaller_mode);
2374 set_ia32_am_support(res, ia32_am_Source);
2378 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2385 /********************************************
2388 * | |__ ___ _ __ ___ __| | ___ ___
2389 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2390 * | |_) | __/ | | | (_) | (_| | __/\__ \
2391 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2393 ********************************************/
2395 static ir_node *gen_be_StackParam(ia32_transform_env_t *env, ir_node *node) {
2396 ir_node *new_op = NULL;
2397 ir_graph *irg = env->irg;
2398 dbg_info *dbg = get_irn_dbg_info(node);
2399 ir_node *block = transform_node(env, get_nodes_block(node));
2400 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2401 ir_node *nomem = new_rd_NoMem(env->irg);
2402 ir_node *ptr = get_irn_n(node, 0);
2403 ir_node *new_ptr = transform_node(env, ptr);
2404 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2405 ir_mode *load_mode = get_irn_mode(node);
2409 if (mode_is_float(load_mode)) {
2411 if (USE_SSE2(env->cg)) {
2412 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, nomem);
2413 pn_res = pn_ia32_xLoad_res;
2415 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, nomem);
2416 pn_res = pn_ia32_vfld_res;
2421 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
2422 proj_mode = mode_Iu;
2423 pn_res = pn_ia32_Load_res;
2426 set_ia32_frame_ent(new_op, ent);
2427 set_ia32_use_frame(new_op);
2429 set_ia32_am_support(new_op, ia32_am_Source);
2430 set_ia32_op_type(new_op, ia32_AddrModeS);
2431 set_ia32_am_flavour(new_op, ia32_am_B);
2432 set_ia32_ls_mode(new_op, load_mode);
2433 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2435 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2437 return new_rd_Proj(dbg, irg, block, new_op, proj_mode, pn_res);
2441 * Transforms a FrameAddr into an ia32 Add.
2443 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env, ir_node *node) {
2444 ir_graph *irg = env->irg;
2445 dbg_info *dbg = get_irn_dbg_info(node);
2446 ir_node *block = transform_node(env, get_nodes_block(node));
2447 ir_node *op = get_irn_n(node, 0);
2448 ir_node *new_op = transform_node(env, op);
2450 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2452 res = new_rd_ia32_Lea(dbg, irg, block, new_op, noreg);
2453 set_ia32_frame_ent(res, arch_get_frame_entity(env->cg->arch_env, node));
2454 set_ia32_am_support(res, ia32_am_Full);
2455 set_ia32_use_frame(res);
2456 set_ia32_am_flavour(res, ia32_am_OB);
2458 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
2464 * Transforms a FrameLoad into an ia32 Load.
2466 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env, ir_node *node) {
2467 ir_node *new_op = NULL;
2468 ir_graph *irg = env->irg;
2469 dbg_info *dbg = get_irn_dbg_info(node);
2470 ir_node *block = transform_node(env, get_nodes_block(node));
2471 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2472 ir_node *mem = get_irn_n(node, 0);
2473 ir_node *ptr = get_irn_n(node, 1);
2474 ir_node *new_mem = transform_node(env, mem);
2475 ir_node *new_ptr = transform_node(env, ptr);
2476 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2477 ir_mode *mode = get_type_mode(get_entity_type(ent));
2478 ir_node *projs[pn_Load_max];
2480 ia32_collect_Projs(node, projs, pn_Load_max);
2482 if (mode_is_float(mode)) {
2484 if (USE_SSE2(env->cg)) {
2485 new_op = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, new_mem);
2488 new_op = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
2492 new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, new_mem);
2495 set_ia32_frame_ent(new_op, ent);
2496 set_ia32_use_frame(new_op);
2498 set_ia32_am_support(new_op, ia32_am_Source);
2499 set_ia32_op_type(new_op, ia32_AddrModeS);
2500 set_ia32_am_flavour(new_op, ia32_am_B);
2501 set_ia32_ls_mode(new_op, mode);
2503 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2510 * Transforms a FrameStore into an ia32 Store.
2512 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env, ir_node *node) {
2513 ir_node *new_op = NULL;
2514 ir_graph *irg = env->irg;
2515 dbg_info *dbg = get_irn_dbg_info(node);
2516 ir_node *block = transform_node(env, get_nodes_block(node));
2517 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2518 ir_node *mem = get_irn_n(node, 0);
2519 ir_node *ptr = get_irn_n(node, 1);
2520 ir_node *val = get_irn_n(node, 2);
2521 ir_node *new_mem = transform_node(env, mem);
2522 ir_node *new_ptr = transform_node(env, ptr);
2523 ir_node *new_val = transform_node(env, val);
2524 ir_entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2525 ir_mode *mode = get_irn_mode(val);
2527 if (mode_is_float(mode)) {
2529 if (USE_SSE2(env->cg)) {
2530 new_op = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2533 new_op = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2536 else if (get_mode_size_bits(mode) == 8) {
2537 new_op = new_rd_ia32_Store8Bit(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2540 new_op = new_rd_ia32_Store(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2543 set_ia32_frame_ent(new_op, ent);
2544 set_ia32_use_frame(new_op);
2546 set_ia32_am_support(new_op, ia32_am_Dest);
2547 set_ia32_op_type(new_op, ia32_AddrModeD);
2548 set_ia32_am_flavour(new_op, ia32_am_B);
2549 set_ia32_ls_mode(new_op, mode);
2551 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2557 * In case SSE is used we need to copy the result from FPU TOS.
2559 static ir_node *gen_be_Call(ia32_transform_env_t *env, ir_node *node) {
2560 ir_graph *irg = env->irg;
2561 dbg_info *dbg = get_irn_dbg_info(node);
2562 ir_node *block = transform_node(env, get_nodes_block(node));
2563 ir_node *call_res = be_get_Proj_for_pn(node, pn_be_Call_first_res);
2564 ir_node *call_mem = be_get_Proj_for_pn(node, pn_be_Call_M_regular);
2566 ir_node *nomem = new_NoMem();
2567 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2569 if (! call_res || ! USE_SSE2(env->cg)) {
2570 return duplicate_node(env, node);
2573 mode = get_irn_mode(call_res);
2575 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2576 if (call_mem == NULL)
2577 call_mem = new_rd_Proj(dbg, irg, block, node, mode_M, pn_be_Call_M_regular);
2579 if (mode_is_float(mode)) {
2580 /* store st(0) onto stack */
2581 ir_node *frame = get_irg_frame(irg);
2582 ir_node *fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, nomem);
2583 ir_entity *ent = frame_alloc_area(get_irg_frame_type(irg), get_mode_size_bytes(mode), 16, 0);
2584 ir_node *sse_load, *p, *bad, *keep;
2589 // Matze: TODO, fix this for new transform code...
2592 set_ia32_ls_mode(fstp, mode);
2593 set_ia32_op_type(fstp, ia32_AddrModeD);
2594 set_ia32_use_frame(fstp);
2595 set_ia32_frame_ent(fstp, ent);
2596 set_ia32_am_flavour(fstp, ia32_am_B);
2597 set_ia32_am_support(fstp, ia32_am_Dest);
2599 /* load into SSE register */
2600 sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, ia32_new_NoReg_gp(env->cg), fstp);
2601 set_ia32_ls_mode(sse_load, mode);
2602 set_ia32_op_type(sse_load, ia32_AddrModeS);
2603 set_ia32_use_frame(sse_load);
2604 set_ia32_frame_ent(sse_load, ent);
2605 set_ia32_am_flavour(sse_load, ia32_am_B);
2606 set_ia32_am_support(sse_load, ia32_am_Source);
2607 mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
2608 sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode, pn_ia32_xLoad_res);
2610 /* reroute all users of the result proj to the sse load */
2611 edges_reroute(call_res, sse_load, irg);
2612 edges_reroute_kind(call_res, sse_load, EDGE_KIND_DEP, irg);
2614 /* reroute all users of the old call memory to the sse load memory */
2615 edges_reroute(call_mem, mproj, irg);
2616 edges_reroute_kind(call_mem, mproj, EDGE_KIND_DEP, irg);
2618 /* now, we can set the old call mem as input of GetST0 */
2619 set_irn_n(fstp, 1, call_mem);
2621 /* now: create new Keep whith all former ins and one additional in - the result Proj */
2623 /* get a Proj representing a caller save register */
2624 p = be_get_Proj_for_pn(node, pn_be_Call_first_res + 1);
2625 assert(is_Proj(p) && "Proj expected.");
2627 /* user of the the proj is the Keep */
2628 p = get_edge_src_irn(get_irn_out_edge_first(p));
2629 assert(be_is_Keep(p) && "Keep expected.");
2631 /* copy in array of the old keep and set the result proj as additional in */
2632 keep_arity = get_irn_arity(p) + 1;
2633 NEW_ARR_A(ir_node *, in_keep, keep_arity);
2634 in_keep[keep_arity - 1] = call_res;
2635 for (i = 0; i < keep_arity - 1; ++i)
2636 in_keep[i] = get_irn_n(p, i);
2638 /* create new keep and set the in class requirements properly */
2639 keep = be_new_Keep(NULL, irg, block, keep_arity, in_keep);
2640 for(i = 0; i < keep_arity; ++i) {
2641 const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
2642 be_node_set_reg_class(keep, i, cls);
2645 /* kill the old keep */
2646 bad = get_irg_bad(irg);
2647 for (i = 0; i < keep_arity - 1; i++)
2648 set_irn_n(p, i, bad);
2649 remove_End_keepalive(get_irg_end(irg), p);
2652 return duplicate_node(env, node);
2656 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2658 static ir_node *gen_be_Return(ia32_transform_env_t *env, ir_node *node) {
2659 ir_graph *irg = env->irg;
2662 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2663 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2664 ir_entity *ent = get_irg_entity(irg);
2665 ir_type *tp = get_entity_type(ent);
2668 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2669 ir_node *new_barrier, *new_frame, *new_ret_val, *new_ret_mem;
2671 int pn_ret_val, pn_ret_mem, arity, i;
2673 assert(ret_val != NULL);
2674 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env->cg)) {
2675 return duplicate_node(env, node);
2678 res_type = get_method_res_type(tp, 0);
2680 if (!is_Primitive_type(res_type)) {
2681 return duplicate_node(env, node);
2684 mode = get_type_mode(res_type);
2685 if (!mode_is_float(mode)) {
2686 return duplicate_node(env, node);
2689 assert(get_method_n_ress(tp) == 1);
2692 pn_ret_val = get_Proj_proj(ret_val);
2693 pn_ret_mem = get_Proj_proj(ret_mem);
2695 /* get the Barrier */
2696 barrier = get_Proj_pred(ret_val);
2698 /* get result input of the Barrier */
2699 ret_val = get_irn_n(barrier, pn_ret_val);
2700 new_ret_val = transform_node(env, ret_val);
2702 /* get memory input of the Barrier */
2703 ret_mem = get_irn_n(barrier, pn_ret_mem);
2704 new_ret_mem = transform_node(env, ret_mem);
2706 frame = get_irg_frame(irg);
2707 new_frame = transform_node(env, frame);
2709 dbg = get_irn_dbg_info(barrier);
2710 block = transform_node(env, get_nodes_block(barrier));
2712 /* store xmm0 onto stack */
2713 sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, new_frame, new_ret_val, new_ret_mem);
2714 set_ia32_ls_mode(sse_store, mode);
2715 set_ia32_op_type(sse_store, ia32_AddrModeD);
2716 set_ia32_use_frame(sse_store);
2717 set_ia32_am_flavour(sse_store, ia32_am_B);
2718 set_ia32_am_support(sse_store, ia32_am_Dest);
2721 fld = new_rd_ia32_SetST0(dbg, irg, block, new_frame, sse_store);
2722 set_ia32_ls_mode(fld, mode);
2723 set_ia32_op_type(fld, ia32_AddrModeS);
2724 set_ia32_use_frame(fld);
2725 set_ia32_am_flavour(fld, ia32_am_B);
2726 set_ia32_am_support(fld, ia32_am_Source);
2728 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2729 fld = new_r_Proj(irg, block, fld, mode_D, pn_ia32_SetST0_res);
2730 arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2732 /* create a new barrier */
2733 arity = get_irn_arity(barrier);
2734 in = alloca(arity * sizeof(in[0]));
2735 for(i = 0; i < arity; ++i) {
2737 if(i == pn_ret_val) {
2739 } else if(i == pn_ret_mem) {
2742 ir_node *in = get_irn_n(barrier, i);
2743 new_in = transform_node(env, in);
2748 new_barrier = new_ir_node(dbg, irg, block,
2749 get_irn_op(barrier), get_irn_mode(barrier),
2751 copy_node_attr(barrier, new_barrier);
2752 duplicate_deps(env, barrier, new_barrier);
2753 set_new_node(barrier, new_barrier);
2754 mark_irn_visited(barrier);
2756 /* transform normally */
2757 return duplicate_node(env, node);
2761 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2763 static ir_node *gen_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
2765 ir_graph *irg = env->irg;
2766 dbg_info *dbg = get_irn_dbg_info(node);
2767 ir_node *block = transform_node(env, get_nodes_block(node));
2768 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
2769 ir_node *new_sz = transform_node(env, sz);
2770 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
2771 ir_node *new_sp = transform_node(env, sp);
2772 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2773 ir_node *nomem = new_NoMem();
2775 /* ia32 stack grows in reverse direction, make a SubSP */
2776 new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2777 set_ia32_am_support(new_op, ia32_am_Source);
2778 fold_immediate(env, new_op, 2, 3);
2780 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2786 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
2788 static ir_node *gen_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
2790 ir_graph *irg = env->irg;
2791 dbg_info *dbg = get_irn_dbg_info(node);
2792 ir_node *block = transform_node(env, get_nodes_block(node));
2793 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
2794 ir_node *new_sz = transform_node(env, sz);
2795 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
2796 ir_node *new_sp = transform_node(env, sp);
2797 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2798 ir_node *nomem = new_NoMem();
2800 /* ia32 stack grows in reverse direction, make an AddSP */
2801 new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
2802 set_ia32_am_support(new_op, ia32_am_Source);
2803 fold_immediate(env, new_op, 2, 3);
2805 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2811 * This function just sets the register for the Unknown node
2812 * as this is not done during register allocation because Unknown
2813 * is an "ignore" node.
2815 static ir_node *gen_Unknown(ia32_transform_env_t *env, ir_node *node) {
2816 ir_mode *mode = get_irn_mode(node);
2818 if (mode_is_float(mode)) {
2819 if (USE_SSE2(env->cg))
2820 return ia32_new_Unknown_xmm(env->cg);
2822 return ia32_new_Unknown_vfp(env->cg);
2823 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
2824 return ia32_new_Unknown_gp(env->cg);
2826 assert(0 && "unsupported Unknown-Mode");
2833 * Change some phi modes
2835 static ir_node *gen_Phi(ia32_transform_env_t *env, ir_node *node) {
2836 ir_graph *irg = env->irg;
2837 dbg_info *dbg = get_irn_dbg_info(node);
2838 ir_mode *mode = get_irn_mode(node);
2839 ir_node *block = transform_node(env, get_nodes_block(node));
2843 if(mode_is_int(mode) || mode_is_reference(mode)) {
2844 // we shouldn't have any 64bit stuff around anymore
2845 assert(get_mode_size_bits(mode) <= 32);
2846 // all integer operations are on 32bit registers now
2848 } else if(mode_is_float(mode)) {
2849 assert(mode == mode_D || mode == mode_F);
2850 // all float operations are on mode_D registers
2854 /* phi nodes allow loops, so we use the old arguments for now
2855 * and fix this later */
2856 phi = new_ir_node(dbg, irg, block, op_Phi, mode, get_irn_arity(node),
2857 get_irn_in(node) + 1);
2858 copy_node_attr(node, phi);
2859 duplicate_deps(env, node, phi);
2861 set_new_node(node, phi);
2863 /* put the preds in the worklist */
2864 arity = get_irn_arity(node);
2865 for(i = 0; i < arity; ++i) {
2866 ir_node *pred = get_irn_n(node, i);
2867 pdeq_putr(env->worklist, pred);
2873 /**********************************************************************
2876 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2877 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2878 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2879 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2881 **********************************************************************/
2883 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2885 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2888 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2889 ir_node *val, ir_node *mem);
2892 * Transforms a lowered Load into a "real" one.
2894 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, ir_node *node, construct_load_func func, char fp_unit) {
2895 ir_graph *irg = env->irg;
2896 dbg_info *dbg = get_irn_dbg_info(node);
2897 ir_node *block = transform_node(env, get_nodes_block(node));
2898 ir_mode *mode = get_ia32_ls_mode(node);
2900 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2901 ir_node *ptr = get_irn_n(node, 0);
2902 ir_node *mem = get_irn_n(node, 1);
2903 ir_node *new_ptr = transform_node(env, ptr);
2904 ir_node *new_mem = transform_node(env, mem);
2907 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2908 lowering we have x87 nodes, so we need to enforce simulation.
2910 if (mode_is_float(mode)) {
2912 if (fp_unit == fp_x87)
2916 new_op = func(dbg, irg, block, new_ptr, noreg, new_mem);
2918 set_ia32_am_support(new_op, ia32_am_Source);
2919 set_ia32_op_type(new_op, ia32_AddrModeS);
2920 set_ia32_am_flavour(new_op, ia32_am_OB);
2921 set_ia32_am_offs_int(new_op, 0);
2922 set_ia32_am_scale(new_op, 1);
2923 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
2924 if(is_ia32_am_sc_sign(node))
2925 set_ia32_am_sc_sign(new_op);
2926 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
2927 if(is_ia32_use_frame(node)) {
2928 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2929 set_ia32_use_frame(new_op);
2932 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2938 * Transforms a lowered Store into a "real" one.
2940 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, ir_node *node, construct_store_func func, char fp_unit) {
2941 ir_graph *irg = env->irg;
2942 dbg_info *dbg = get_irn_dbg_info(node);
2943 ir_node *block = transform_node(env, get_nodes_block(node));
2944 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2945 ir_mode *mode = get_ia32_ls_mode(node);
2948 ia32_am_flavour_t am_flav = ia32_B;
2949 ir_node *ptr = get_irn_n(node, 0);
2950 ir_node *val = get_irn_n(node, 1);
2951 ir_node *mem = get_irn_n(node, 2);
2952 ir_node *new_ptr = transform_node(env, ptr);
2953 ir_node *new_val = transform_node(env, val);
2954 ir_node *new_mem = transform_node(env, mem);
2957 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2958 lowering we have x87 nodes, so we need to enforce simulation.
2960 if (mode_is_float(mode)) {
2962 if (fp_unit == fp_x87)
2966 new_op = func(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
2968 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
2970 add_ia32_am_offs_int(new_op, am_offs);
2973 set_ia32_am_support(new_op, ia32_am_Dest);
2974 set_ia32_op_type(new_op, ia32_AddrModeD);
2975 set_ia32_am_flavour(new_op, am_flav);
2976 set_ia32_ls_mode(new_op, mode);
2977 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2978 set_ia32_use_frame(new_op);
2980 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2987 * Transforms an ia32_l_XXX into a "real" XXX node
2989 * @param env The transformation environment
2990 * @return the created ia32 XXX node
2992 #define GEN_LOWERED_OP(op) \
2993 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
2994 ir_mode *mode = get_irn_mode(node); \
2995 if (mode_is_float(mode)) \
2997 return gen_binop(env, node, get_binop_left(node), \
2998 get_binop_right(node), new_rd_ia32_##op); \
3001 #define GEN_LOWERED_x87_OP(op) \
3002 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3004 FORCE_x87(env->cg); \
3005 new_op = gen_binop_float(env, node, get_binop_left(node), \
3006 get_binop_right(node), new_rd_ia32_##op); \
3010 #define GEN_LOWERED_UNOP(op) \
3011 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3012 return gen_unop(env, node, get_unop_op(node), new_rd_ia32_##op); \
3015 #define GEN_LOWERED_SHIFT_OP(op) \
3016 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3017 return gen_shift_binop(env, node, get_binop_left(node), \
3018 get_binop_right(node), new_rd_ia32_##op); \
3021 #define GEN_LOWERED_LOAD(op, fp_unit) \
3022 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3023 return gen_lowered_Load(env, node, new_rd_ia32_##op, fp_unit); \
3026 #define GEN_LOWERED_STORE(op, fp_unit) \
3027 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env, ir_node *node) {\
3028 return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
3035 GEN_LOWERED_OP(IMul)
3037 GEN_LOWERED_x87_OP(vfprem)
3038 GEN_LOWERED_x87_OP(vfmul)
3039 GEN_LOWERED_x87_OP(vfsub)
3041 GEN_LOWERED_UNOP(Neg)
3043 GEN_LOWERED_LOAD(vfild, fp_x87)
3044 GEN_LOWERED_LOAD(Load, fp_none)
3045 GEN_LOWERED_STORE(vfist, fp_x87)
3046 GEN_LOWERED_STORE(Store, fp_none)
3048 static ir_node *gen_ia32_l_vfdiv(ia32_transform_env_t *env, ir_node *node) {
3049 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3050 ir_graph *irg = env->irg;
3051 dbg_info *dbg = get_irn_dbg_info(node);
3052 ir_node *block = transform_node(env, get_nodes_block(node));
3053 ir_node *left = get_binop_left(node);
3054 ir_node *right = get_binop_right(node);
3055 ir_node *new_left = transform_node(env, left);
3056 ir_node *new_right = transform_node(env, right);
3059 vfdiv = new_rd_ia32_vfdiv(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3060 clear_ia32_commutative(vfdiv);
3061 set_ia32_am_support(vfdiv, ia32_am_Source);
3062 fold_immediate(env, vfdiv, 2, 3);
3064 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env->cg, node));
3072 * Transforms a l_MulS into a "real" MulS node.
3074 * @param env The transformation environment
3075 * @return the created ia32 Mul node
3077 static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
3078 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3079 ir_graph *irg = env->irg;
3080 dbg_info *dbg = get_irn_dbg_info(node);
3081 ir_node *block = transform_node(env, get_nodes_block(node));
3082 ir_node *left = get_binop_left(node);
3083 ir_node *right = get_binop_right(node);
3084 ir_node *new_left = transform_node(env, left);
3085 ir_node *new_right = transform_node(env, right);
3088 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3089 /* and then skip the result Proj, because all needed Projs are already there. */
3090 ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3091 clear_ia32_commutative(muls);
3092 set_ia32_am_support(muls, ia32_am_Source);
3093 fold_immediate(env, muls, 2, 3);
3095 /* check if EAX and EDX proj exist, add missing one */
3096 in[0] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EAX);
3097 in[1] = new_rd_Proj(dbg, irg, block, muls, mode_Iu, pn_EDX);
3098 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3100 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env->cg, node));
3105 GEN_LOWERED_SHIFT_OP(Shl)
3106 GEN_LOWERED_SHIFT_OP(Shr)
3107 GEN_LOWERED_SHIFT_OP(Sar)
3110 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3111 * op1 - target to be shifted
3112 * op2 - contains bits to be shifted into target
3114 * Only op3 can be an immediate.
3116 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *node,
3117 ir_node *op1, ir_node *op2,
3119 ir_node *new_op = NULL;
3120 ir_graph *irg = env->irg;
3121 ir_mode *mode = get_irn_mode(node);
3122 dbg_info *dbg = get_irn_dbg_info(node);
3123 ir_node *block = transform_node(env, get_nodes_block(node));
3124 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
3125 ir_node *nomem = new_NoMem();
3127 ir_node *new_op1 = transform_node(env, op1);
3128 ir_node *new_op2 = transform_node(env, op2);
3129 ir_node *new_count = transform_node(env, count);
3131 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
3133 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
3135 /* Check if immediate optimization is on and */
3136 /* if it's an operation with immediate. */
3137 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3139 /* Limit imm_op within range imm8 */
3141 tv = get_ia32_Immop_tarval(imm_op);
3144 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3145 set_ia32_Immop_tarval(imm_op, tv);
3152 /* integer operations */
3154 /* This is ShiftD with const */
3155 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
3157 if (is_ia32_l_ShlD(node))
3158 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3159 new_op1, new_op2, noreg, nomem);
3161 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3162 new_op1, new_op2, noreg, nomem);
3163 copy_ia32_Immop_attr(new_op, imm_op);
3166 /* This is a normal ShiftD */
3167 DB((mod, LEVEL_1, "ShiftD binop ..."));
3168 if (is_ia32_l_ShlD(node))
3169 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg,
3170 new_op1, new_op2, new_count, nomem);
3172 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
3173 new_op1, new_op2, new_count, nomem);
3176 /* set AM support */
3177 // Matze: node has unsupported format (6inputs)
3178 //set_ia32_am_support(new_op, ia32_am_Dest);
3180 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
3182 set_ia32_emit_cl(new_op);
3187 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env, ir_node *node) {
3188 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3189 get_irn_n(node, 1), get_irn_n(node, 2));
3192 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env, ir_node *node) {
3193 return gen_lowered_64bit_shifts(env, node, get_irn_n(node, 0),
3194 get_irn_n(node, 1), get_irn_n(node, 2));
3198 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3200 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env, ir_node *node) {
3201 ia32_code_gen_t *cg = env->cg;
3202 ir_node *res = NULL;
3203 ir_graph *irg = env->irg;
3204 dbg_info *dbg = get_irn_dbg_info(node);
3205 ir_node *block = transform_node(env, get_nodes_block(node));
3206 ir_node *ptr = get_irn_n(node, 0);
3207 ir_node *val = get_irn_n(node, 1);
3208 ir_node *new_val = transform_node(env, val);
3209 ir_node *mem = get_irn_n(node, 2);
3210 ir_node *noreg, *new_ptr, *new_mem;
3216 noreg = ia32_new_NoReg_gp(cg);
3217 new_mem = transform_node(env, mem);
3218 new_ptr = transform_node(env, ptr);
3220 /* Store x87 -> MEM */
3221 res = new_rd_ia32_vfst(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3222 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3223 set_ia32_use_frame(res);
3224 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3225 set_ia32_am_support(res, ia32_am_Dest);
3226 set_ia32_am_flavour(res, ia32_B);
3227 set_ia32_op_type(res, ia32_AddrModeD);
3229 /* Load MEM -> SSE */
3230 res = new_rd_ia32_xLoad(dbg, irg, block, new_ptr, noreg, res);
3231 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3232 set_ia32_use_frame(res);
3233 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3234 set_ia32_am_support(res, ia32_am_Source);
3235 set_ia32_am_flavour(res, ia32_B);
3236 set_ia32_op_type(res, ia32_AddrModeS);
3237 res = new_rd_Proj(dbg, irg, block, res, mode_D, pn_ia32_xLoad_res);
3243 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3245 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env, ir_node *node) {
3246 ia32_code_gen_t *cg = env->cg;
3247 ir_graph *irg = env->irg;
3248 dbg_info *dbg = get_irn_dbg_info(node);
3249 ir_node *block = transform_node(env, get_nodes_block(node));
3250 ir_node *res = NULL;
3251 ir_node *ptr = get_irn_n(node, 0);
3252 ir_node *val = get_irn_n(node, 1);
3253 ir_node *mem = get_irn_n(node, 2);
3254 ir_entity *fent = get_ia32_frame_ent(node);
3255 ir_mode *lsmode = get_ia32_ls_mode(node);
3256 ir_node *new_val = transform_node(env, val);
3257 ir_node *noreg, *new_ptr, *new_mem;
3260 if (!USE_SSE2(cg)) {
3261 /* SSE unit is not used -> skip this node. */
3265 noreg = ia32_new_NoReg_gp(cg);
3266 new_val = transform_node(env, val);
3267 new_ptr = transform_node(env, ptr);
3268 new_mem = transform_node(env, mem);
3270 /* Store SSE -> MEM */
3271 if (is_ia32_xLoad(skip_Proj(new_val))) {
3272 ir_node *ld = skip_Proj(new_val);
3274 /* we can vfld the value directly into the fpu */
3275 fent = get_ia32_frame_ent(ld);
3276 ptr = get_irn_n(ld, 0);
3277 offs = get_ia32_am_offs_int(ld);
3279 res = new_rd_ia32_xStore(dbg, irg, block, new_ptr, noreg, new_val, new_mem);
3280 set_ia32_frame_ent(res, fent);
3281 set_ia32_use_frame(res);
3282 set_ia32_ls_mode(res, lsmode);
3283 set_ia32_am_support(res, ia32_am_Dest);
3284 set_ia32_am_flavour(res, ia32_B);
3285 set_ia32_op_type(res, ia32_AddrModeD);
3289 /* Load MEM -> x87 */
3290 res = new_rd_ia32_vfld(dbg, irg, block, new_ptr, noreg, new_mem);
3291 set_ia32_frame_ent(res, fent);
3292 set_ia32_use_frame(res);
3293 set_ia32_ls_mode(res, lsmode);
3294 add_ia32_am_offs_int(res, offs);
3295 set_ia32_am_support(res, ia32_am_Source);
3296 set_ia32_am_flavour(res, ia32_B);
3297 set_ia32_op_type(res, ia32_AddrModeS);
3298 res = new_rd_Proj(dbg, irg, block, res, lsmode, pn_ia32_vfld_res);
3303 /*********************************************************
3306 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3307 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3308 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3309 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3311 *********************************************************/
3314 * the BAD transformer.
3316 static ir_node *bad_transform(ia32_transform_env_t *env, ir_node *node) {
3317 panic("No transform function for %+F available.\n", node);
3321 static ir_node *gen_End(ia32_transform_env_t *env, ir_node *node) {
3322 /* end has to be duplicated manually because we need a dynamic in array */
3323 ir_graph *irg = env->irg;
3324 dbg_info *dbg = get_irn_dbg_info(node);
3325 ir_node *block = transform_node(env, get_nodes_block(node));
3329 new_end = new_ir_node(dbg, irg, block, op_End, mode_X, -1, NULL);
3330 copy_node_attr(node, new_end);
3331 duplicate_deps(env, node, new_end);
3333 set_irg_end(irg, new_end);
3334 set_new_node(new_end, new_end);
3336 /* transform preds */
3337 arity = get_irn_arity(node);
3338 for(i = 0; i < arity; ++i) {
3339 ir_node *in = get_irn_n(node, i);
3340 ir_node *new_in = transform_node(env, in);
3342 add_End_keepalive(new_end, new_in);
3348 static ir_node *gen_Block(ia32_transform_env_t *env, ir_node *node) {
3349 ir_graph *irg = env->irg;
3350 dbg_info *dbg = get_irn_dbg_info(node);
3351 ir_node *start_block = env->old_anchors[anchor_start_block];
3356 * We replace the ProjX from the start node with a jump,
3357 * so the startblock has no preds anymore now
3359 if(node == start_block) {
3360 return new_rd_Block(dbg, irg, 0, NULL);
3363 /* we use the old blocks for now, because jumps allow cycles in the graph
3364 * we have to fix this later */
3365 block = new_ir_node(dbg, irg, NULL, get_irn_op(node), get_irn_mode(node),
3366 get_irn_arity(node), get_irn_in(node) + 1);
3367 copy_node_attr(node, block);
3369 #ifdef DEBUG_libfirm
3370 block->node_nr = node->node_nr;
3372 set_new_node(node, block);
3374 /* put the preds in the worklist */
3375 arity = get_irn_arity(node);
3376 for(i = 0; i < arity; ++i) {
3377 ir_node *in = get_irn_n(node, i);
3378 pdeq_putr(env->worklist, in);
3384 static ir_node *gen_Proj_be_AddSP(ia32_transform_env_t *env, ir_node *node) {
3385 ir_graph *irg = env->irg;
3386 ir_node *block = transform_node(env, get_nodes_block(node));
3387 dbg_info *dbg = get_irn_dbg_info(node);
3388 ir_node *pred = get_Proj_pred(node);
3389 ir_node *new_pred = transform_node(env, pred);
3390 int proj = get_Proj_proj(node);
3392 if(proj == pn_be_AddSP_res) {
3393 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3394 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3396 } else if(proj == pn_be_AddSP_M) {
3397 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3401 return new_rd_Unknown(irg, get_irn_mode(node));
3404 static ir_node *gen_Proj_be_SubSP(ia32_transform_env_t *env, ir_node *node) {
3405 ir_graph *irg = env->irg;
3406 ir_node *block = transform_node(env, get_nodes_block(node));
3407 dbg_info *dbg = get_irn_dbg_info(node);
3408 ir_node *pred = get_Proj_pred(node);
3409 ir_node *new_pred = transform_node(env, pred);
3410 int proj = get_Proj_proj(node);
3412 if(proj == pn_be_SubSP_res) {
3413 ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3414 arch_set_irn_register(env->cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3416 } else if(proj == pn_be_SubSP_M) {
3417 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3421 return new_rd_Unknown(irg, get_irn_mode(node));
3424 static ir_node *gen_Proj_Load(ia32_transform_env_t *env, ir_node *node) {
3425 ir_graph *irg = env->irg;
3426 ir_node *block = transform_node(env, get_nodes_block(node));
3427 dbg_info *dbg = get_irn_dbg_info(node);
3428 ir_node *pred = get_Proj_pred(node);
3429 ir_node *new_pred = transform_node(env, pred);
3430 int proj = get_Proj_proj(node);
3432 /* renumber the proj */
3433 if(is_ia32_Load(new_pred)) {
3434 if(proj == pn_Load_res) {
3435 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3436 } else if(proj == pn_Load_M) {
3437 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3439 } else if(is_ia32_xLoad(new_pred)) {
3440 if(proj == pn_Load_res) {
3441 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_xLoad_res);
3442 } else if(proj == pn_Load_M) {
3443 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3445 } else if(is_ia32_vfld(new_pred)) {
3446 if(proj == pn_Load_res) {
3447 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfld_res);
3448 } else if(proj == pn_Load_M) {
3449 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3454 return new_rd_Unknown(irg, get_irn_mode(node));
3457 static ir_node *gen_Proj_DivMod(ia32_transform_env_t *env, ir_node *node) {
3458 ir_graph *irg = env->irg;
3459 dbg_info *dbg = get_irn_dbg_info(node);
3460 ir_node *block = transform_node(env, get_nodes_block(node));
3461 ir_mode *mode = get_irn_mode(node);
3463 ir_node *pred = get_Proj_pred(node);
3464 ir_node *new_pred = transform_node(env, pred);
3465 int proj = get_Proj_proj(node);
3467 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3469 switch(get_irn_opcode(pred)) {
3473 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3475 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3483 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3485 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3493 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3494 case pn_DivMod_res_div:
3495 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3496 case pn_DivMod_res_mod:
3497 return new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3507 return new_rd_Unknown(irg, mode);
3510 static ir_node *gen_Proj_CopyB(ia32_transform_env_t *env, ir_node *node)
3512 ir_graph *irg = env->irg;
3513 dbg_info *dbg = get_irn_dbg_info(node);
3514 ir_node *block = transform_node(env, get_nodes_block(node));
3515 ir_mode *mode = get_irn_mode(node);
3517 ir_node *pred = get_Proj_pred(node);
3518 ir_node *new_pred = transform_node(env, pred);
3519 int proj = get_Proj_proj(node);
3522 case pn_CopyB_M_regular:
3523 if(is_ia32_CopyB_i(new_pred)) {
3524 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3526 } else if(is_ia32_CopyB(new_pred)) {
3527 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3536 return new_rd_Unknown(irg, mode);
3539 static ir_node *gen_Proj_l_vfdiv(ia32_transform_env_t *env, ir_node *node)
3541 ir_graph *irg = env->irg;
3542 dbg_info *dbg = get_irn_dbg_info(node);
3543 ir_node *block = transform_node(env, get_nodes_block(node));
3544 ir_mode *mode = get_irn_mode(node);
3546 ir_node *pred = get_Proj_pred(node);
3547 ir_node *new_pred = transform_node(env, pred);
3548 int proj = get_Proj_proj(node);
3551 case pn_ia32_l_vfdiv_M:
3552 return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3553 case pn_ia32_l_vfdiv_res:
3554 return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfdiv_res);
3559 return new_rd_Unknown(irg, mode);
3562 static ir_node *gen_Proj_Quot(ia32_transform_env_t *env, ir_node *node)
3564 ir_graph *irg = env->irg;
3565 dbg_info *dbg = get_irn_dbg_info(node);
3566 ir_node *block = transform_node(env, get_nodes_block(node));
3567 ir_mode *mode = get_irn_mode(node);
3569 ir_node *pred = get_Proj_pred(node);
3570 ir_node *new_pred = transform_node(env, pred);
3571 int proj = get_Proj_proj(node);
3575 if(is_ia32_xDiv(new_pred)) {
3576 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3578 } else if(is_ia32_vfdiv(new_pred)) {
3579 return new_rd_Proj(dbg, irg, block, new_pred, mode_M,
3584 if(is_ia32_xDiv(new_pred)) {
3585 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3587 } else if(is_ia32_vfdiv(new_pred)) {
3588 return new_rd_Proj(dbg, irg, block, new_pred, mode,
3597 return new_rd_Unknown(irg, mode);
3600 static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
3601 ir_graph *irg = env->irg;
3602 dbg_info *dbg = get_irn_dbg_info(node);
3603 ir_node *block = transform_node(env, get_nodes_block(node));
3605 ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
3610 static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
3611 ir_graph *irg = env->irg;
3612 dbg_info *dbg = get_irn_dbg_info(node);
3613 ir_node *pred = get_Proj_pred(node);
3614 int proj = get_Proj_proj(node);
3616 if(is_Store(pred) || be_is_FrameStore(pred)) {
3617 if(proj == pn_Store_M) {
3618 return transform_node(env, pred);
3621 return new_r_Bad(irg);
3623 } else if(is_Load(pred) || be_is_FrameLoad(pred)) {
3624 return gen_Proj_Load(env, node);
3625 } else if(is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3626 return gen_Proj_DivMod(env, node);
3627 } else if(is_CopyB(pred)) {
3628 return gen_Proj_CopyB(env, node);
3629 } else if(is_Quot(pred)) {
3630 return gen_Proj_Quot(env, node);
3631 } else if(is_ia32_l_vfdiv(pred)) {
3632 return gen_Proj_l_vfdiv(env, node);
3633 } else if(be_is_SubSP(pred)) {
3634 return gen_Proj_be_SubSP(env, node);
3635 } else if(be_is_AddSP(pred)) {
3636 return gen_Proj_be_AddSP(env, node);
3637 } else if(get_irn_op(pred) == op_Start) {
3638 if(proj == pn_Start_X_initial_exec) {
3639 ir_node *block = get_nodes_block(pred);
3642 block = transform_node(env, block);
3643 // we exchange the ProjX with a jump
3644 jump = new_rd_Jmp(dbg, irg, block);
3645 ir_fprintf(stderr, "created jump: %+F\n", jump);
3648 if(node == env->old_anchors[anchor_tls]) {
3649 return gen_Proj_tls(env, node);
3653 return duplicate_node(env, node);
3657 * Enters all transform functions into the generic pointer
3659 static void register_transformers(void) {
3660 ir_op *op_Max, *op_Min, *op_Mulh;
3662 /* first clear the generic function pointer for all ops */
3663 clear_irp_opcodes_generic_func();
3665 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3666 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3705 /* transform ops from intrinsic lowering */
3727 GEN(ia32_l_X87toSSE);
3728 GEN(ia32_l_SSEtoX87);
3733 /* we should never see these nodes */
3748 /* handle generic backend nodes */
3758 /* set the register for all Unknown nodes */
3761 op_Max = get_op_Max();
3764 op_Min = get_op_Min();
3767 op_Mulh = get_op_Mulh();
3775 static void duplicate_deps(ia32_transform_env_t *env, ir_node *old_node,
3779 int deps = get_irn_deps(old_node);
3781 for(i = 0; i < deps; ++i) {
3782 ir_node *dep = get_irn_dep(old_node, i);
3783 ir_node *new_dep = transform_node(env, dep);
3785 add_irn_dep(new_node, new_dep);
3789 static ir_node *duplicate_node(ia32_transform_env_t *env, ir_node *node)
3791 ir_graph *irg = env->irg;
3792 dbg_info *dbg = get_irn_dbg_info(node);
3793 ir_mode *mode = get_irn_mode(node);
3794 ir_op *op = get_irn_op(node);
3800 block = transform_node(env, get_nodes_block(node));
3802 arity = get_irn_arity(node);
3803 ins = alloca(arity * sizeof(ins[0]));
3804 for(i = 0; i < arity; ++i) {
3805 ir_node *in = get_irn_n(node, i);
3806 ins[i] = transform_node(env, in);
3809 new_node = new_ir_node(dbg, irg, block,
3810 op, mode, arity, ins);
3811 copy_node_attr(node, new_node);
3812 duplicate_deps(env, node, new_node);
3817 static ir_node *transform_node(ia32_transform_env_t *env, ir_node *node)
3820 ir_op *op = get_irn_op(node);
3822 if(irn_visited(node)) {
3823 assert(get_new_node(node) != NULL);
3824 return get_new_node(node);
3827 mark_irn_visited(node);
3828 DEBUG_ONLY(set_new_node(node, NULL));
3830 if (op->ops.generic) {
3831 transform_func *transform = (transform_func *)op->ops.generic;
3833 new_node = (*transform)(env, node);
3834 assert(new_node != NULL);
3836 new_node = duplicate_node(env, node);
3838 //ir_fprintf(stderr, "%+F -> %+F\n", node, new_node);
3840 set_new_node(node, new_node);
3841 mark_irn_visited(new_node);
3842 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
3846 static void fix_loops(ia32_transform_env_t *env, ir_node *node)
3850 if(irn_visited(node))
3852 mark_irn_visited(node);
3854 assert(node_is_in_irgs_storage(env->irg, node));
3856 if(!is_Block(node)) {
3857 ir_node *block = get_nodes_block(node);
3858 ir_node *new_block = (ir_node*) get_irn_link(block);
3860 if(new_block != NULL) {
3861 set_nodes_block(node, new_block);
3865 fix_loops(env, block);
3868 arity = get_irn_arity(node);
3869 for(i = 0; i < arity; ++i) {
3870 ir_node *in = get_irn_n(node, i);
3871 ir_node *new = (ir_node*) get_irn_link(in);
3873 if(new != NULL && new != in) {
3874 set_irn_n(node, i, new);
3881 arity = get_irn_deps(node);
3882 for(i = 0; i < arity; ++i) {
3883 ir_node *in = get_irn_dep(node, i);
3884 ir_node *new = (ir_node*) get_irn_link(in);
3886 if(new != NULL && new != in) {
3887 set_irn_dep(node, i, new);
3895 static void pre_transform_node(ir_node **place, ia32_transform_env_t *env)
3900 *place = transform_node(env, *place);
3903 static void transform_nodes(ia32_code_gen_t *cg)
3906 ir_graph *irg = cg->irg;
3908 ia32_transform_env_t env;
3910 hook_dead_node_elim(irg, 1);
3912 inc_irg_visited(irg);
3916 env.visited = get_irg_visited(irg);
3917 env.worklist = new_pdeq();
3918 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
3919 DEBUG_ONLY(env.mod = cg->mod);
3921 old_end = get_irg_end(irg);
3923 /* put all anchor nodes in the worklist */
3924 for(i = 0; i < anchor_max; ++i) {
3925 ir_node *anchor = irg->anchors[i];
3928 pdeq_putr(env.worklist, anchor);
3931 env.old_anchors[i] = anchor;
3932 // and set it to NULL to make sure we don't accidently use it
3933 irg->anchors[i] = NULL;
3936 // pre transform some anchors (so they are available in the other transform
3938 set_irg_bad(irg, transform_node(&env, env.old_anchors[anchor_bad]));
3939 set_irg_no_mem(irg, transform_node(&env, env.old_anchors[anchor_no_mem]));
3940 set_irg_start_block(irg, transform_node(&env, env.old_anchors[anchor_start_block]));
3941 set_irg_start(irg, transform_node(&env, env.old_anchors[anchor_start]));
3942 set_irg_frame(irg, transform_node(&env, env.old_anchors[anchor_frame]));
3944 pre_transform_node(&cg->unknown_gp, &env);
3945 pre_transform_node(&cg->unknown_vfp, &env);
3946 pre_transform_node(&cg->unknown_xmm, &env);
3947 pre_transform_node(&cg->noreg_gp, &env);
3948 pre_transform_node(&cg->noreg_vfp, &env);
3949 pre_transform_node(&cg->noreg_xmm, &env);
3951 /* process worklist (this should transform all nodes in the graph) */
3952 while(!pdeq_empty(env.worklist)) {
3953 ir_node *node = pdeq_getl(env.worklist);
3954 transform_node(&env, node);
3957 /* fix loops and set new anchors*/
3958 inc_irg_visited(irg);
3959 for(i = 0; i < anchor_max; ++i) {
3960 ir_node *anchor = env.old_anchors[i];
3964 anchor = get_irn_link(anchor);
3965 fix_loops(&env, anchor);
3966 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
3967 irg->anchors[i] = anchor;
3970 del_pdeq(env.worklist);
3972 hook_dead_node_elim(irg, 0);
3975 void ia32_transform_graph(ia32_code_gen_t *cg)
3977 ir_graph *irg = cg->irg;
3978 be_irg_t *birg = cg->birg;
3979 ir_graph *old_current_ir_graph = current_ir_graph;
3980 int old_interprocedural_view = get_interprocedural_view();
3981 struct obstack *old_obst = NULL;
3982 struct obstack *new_obst = NULL;
3984 current_ir_graph = irg;
3985 set_interprocedural_view(0);
3986 register_transformers();
3988 /* most analysis info is wrong after transformation */
3989 free_callee_info(irg);
3991 irg->outs_state = outs_none;
3993 free_loop_information(irg);
3994 set_irg_doms_inconsistent(irg);
3995 be_invalidate_liveness(birg);
3996 be_invalidate_dom_front(birg);
3998 /* create a new obstack */
3999 old_obst = irg->obst;
4000 new_obst = xmalloc(sizeof(*new_obst));
4001 obstack_init(new_obst);
4002 irg->obst = new_obst;
4003 irg->last_node_idx = 0;
4005 /* create new value table for CSE */
4006 del_identities(irg->value_table);
4007 irg->value_table = new_identities();
4009 /* do the main transformation */
4010 transform_nodes(cg);
4012 /* we don't want the globals anchor anymore */
4013 set_irg_globals(irg, new_r_Bad(irg));
4015 /* free the old obstack */
4016 obstack_free(old_obst, 0);
4020 current_ir_graph = old_current_ir_graph;
4021 set_interprocedural_view(old_interprocedural_view);
4023 /* recalculate edges */
4024 edges_deactivate(irg);
4025 edges_activate(irg);
4029 * Transforms a psi condition.
4031 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4034 /* if the mode is target mode, we have already seen this part of the tree */
4035 if (get_irn_mode(cond) == mode)
4038 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4040 set_irn_mode(cond, mode);
4042 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4043 ir_node *in = get_irn_n(cond, i);
4045 /* if in is a compare: transform into Set/xCmp */
4047 ir_node *new_op = NULL;
4048 ir_node *cmp = get_Proj_pred(in);
4049 ir_node *cmp_a = get_Cmp_left(cmp);
4050 ir_node *cmp_b = get_Cmp_right(cmp);
4051 dbg_info *dbg = get_irn_dbg_info(cmp);
4052 ir_graph *irg = get_irn_irg(cmp);
4053 ir_node *block = get_nodes_block(cmp);
4054 ir_node *noreg = ia32_new_NoReg_gp(cg);
4055 ir_node *nomem = new_rd_NoMem(irg);
4056 int pnc = get_Proj_proj(in);
4058 /* this is a compare */
4059 if (mode_is_float(mode)) {
4060 /* Psi is float, we need a floating point compare */
4063 ir_mode *m = get_irn_mode(cmp_a);
4065 if (! mode_is_float(m)) {
4066 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
4067 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
4069 else if (m == mode_F) {
4070 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4071 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
4072 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
4075 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4076 set_ia32_pncode(new_op, pnc);
4077 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4086 construct_binop_func *set_func = NULL;
4088 if (mode_is_float(get_irn_mode(cmp_a))) {
4089 /* 1st case: compare operands are floats */
4094 set_func = new_rd_ia32_xCmpSet;
4098 set_func = new_rd_ia32_vfCmpSet;
4101 pnc &= 7; /* fp compare -> int compare */
4104 /* 2nd case: compare operand are integer too */
4105 set_func = new_rd_ia32_CmpSet;
4108 new_op = set_func(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4109 if(!mode_is_signed(mode))
4110 pnc |= ia32_pn_Cmp_Unsigned;
4112 set_ia32_pncode(new_op, pnc);
4113 set_ia32_am_support(new_op, ia32_am_Source);
4116 /* the the new compare as in */
4117 set_irn_n(cond, i, new_op);
4120 /* another complex condition */
4121 transform_psi_cond(in, mode, cg);
4127 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4128 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
4129 * compare, which causes the compare result to be stores in a register. The
4130 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4132 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4133 ia32_code_gen_t *cg = env;
4134 ir_node *psi_sel, *new_cmp, *block;
4139 if (get_irn_opcode(node) != iro_Psi)
4142 psi_sel = get_Psi_cond(node, 0);
4144 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4145 if (is_Proj(psi_sel))
4148 //mode = get_irn_mode(node);
4149 // TODO this is probably wrong...
4152 transform_psi_cond(psi_sel, mode, cg);
4154 irg = get_irn_irg(node);
4155 block = get_nodes_block(node);
4157 /* we need to compare the evaluated condition tree with 0 */
4158 mode = get_irn_mode(node);
4159 if (mode_is_float(mode)) {
4160 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4161 /* BEWARE: new_r_Const_long works for floating point as well */
4162 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
4163 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4166 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
4167 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4170 set_Psi_cond(node, 0, new_cmp);