2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** holdd the current code generator during transformation */
90 static ia32_code_gen_t *env_cg;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
102 /****************************************************************************************************
104 * | | | | / _| | | (_)
105 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
106 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
107 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
108 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
110 ****************************************************************************************************/
112 static ir_node *try_create_Immediate(ir_node *node,
113 char immediate_constraint_type);
115 static INLINE int mode_needs_gp_reg(ir_mode *mode)
117 if(mode == mode_fpcw)
120 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
124 * Returns 1 if irn is a Const representing 0, 0 otherwise
126 static INLINE int is_ia32_Const_0(ir_node *irn) {
127 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
128 && tarval_is_null(get_ia32_Immop_tarval(irn));
132 * Returns 1 if irn is a Const representing 1, 0 otherwise
134 static INLINE int is_ia32_Const_1(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_one(get_ia32_Immop_tarval(irn));
140 * Collects all Projs of a node into the node array. Index is the projnum.
141 * BEWARE: The caller has to assure the appropriate array size!
143 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
144 const ir_edge_t *edge;
145 assert(get_irn_mode(irn) == mode_T && "need mode_T");
147 memset(projs, 0, size * sizeof(projs[0]));
149 foreach_out_edge(irn, edge) {
150 ir_node *proj = get_edge_src_irn(edge);
151 int proj_proj = get_Proj_proj(proj);
152 assert(proj_proj < size);
153 projs[proj_proj] = proj;
158 * Renumbers the proj having pn_old in the array tp pn_new
159 * and removes the proj from the array.
161 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
162 fprintf(stderr, "Warning: renumber_Proj used!\n");
164 set_Proj_proj(projs[pn_old], pn_new);
165 projs[pn_old] = NULL;
170 * creates a unique ident by adding a number to a tag
172 * @param tag the tag string, must contain a %d if a number
175 static ident *unique_id(const char *tag)
177 static unsigned id = 0;
180 snprintf(str, sizeof(str), tag, ++id);
181 return new_id_from_str(str);
185 * Get a primitive type for a mode.
187 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
189 pmap_entry *e = pmap_find(types, mode);
194 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
195 res = new_type_primitive(new_id_from_str(buf), mode);
196 pmap_insert(types, mode, res);
204 * Get an entity that is initialized with a tarval
206 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
208 tarval *tv = get_Const_tarval(cnst);
209 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
214 ir_mode *mode = get_irn_mode(cnst);
215 ir_type *tp = get_Const_type(cnst);
216 if (tp == firm_unknown_type)
217 tp = get_prim_type(cg->isa->types, mode);
219 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
221 set_entity_ld_ident(res, get_entity_ident(res));
222 set_entity_visibility(res, visibility_local);
223 set_entity_variability(res, variability_constant);
224 set_entity_allocation(res, allocation_static);
226 /* we create a new entity here: It's initialization must resist on the
228 rem = current_ir_graph;
229 current_ir_graph = get_const_code_irg();
230 set_atomic_ent_value(res, new_Const_type(tv, tp));
231 current_ir_graph = rem;
233 pmap_insert(cg->isa->tv_ent, tv, res);
241 static int is_Const_0(ir_node *node) {
245 return classify_Const(node) == CNST_NULL;
248 static int is_Const_1(ir_node *node) {
252 return classify_Const(node) == CNST_ONE;
256 * Transforms a Const.
258 static ir_node *gen_Const(ir_node *node) {
259 ir_graph *irg = current_ir_graph;
260 ir_node *block = be_transform_node(get_nodes_block(node));
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
272 if (! USE_SSE2(env_cg)) {
273 cnst_classify_t clss = classify_Const(node);
275 if (clss == CNST_NULL) {
276 load = new_rd_ia32_vfldz(dbgi, irg, block);
278 } else if (clss == CNST_ONE) {
279 load = new_rd_ia32_vfld1(dbgi, irg, block);
282 floatent = get_entity_for_tv(env_cg, node);
284 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
285 set_ia32_am_support(load, ia32_am_Source);
286 set_ia32_op_type(load, ia32_AddrModeS);
287 set_ia32_am_flavour(load, ia32_am_N);
288 set_ia32_am_sc(load, floatent);
289 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
291 set_ia32_ls_mode(load, mode);
293 floatent = get_entity_for_tv(env_cg, node);
295 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
296 set_ia32_am_support(load, ia32_am_Source);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_flavour(load, ia32_am_N);
299 set_ia32_am_sc(load, floatent);
300 set_ia32_ls_mode(load, mode);
302 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet.
309 * So add a dependency to the initial frame pointer calculation to
310 * avoid that situation.
312 if (get_irg_start_block(irg) == block) {
313 add_irn_dep(load, get_irg_frame(irg));
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
319 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
322 if (get_irg_start_block(irg) == block) {
323 add_irn_dep(cnst, get_irg_frame(irg));
326 set_ia32_Const_attr(cnst, node);
327 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
332 return new_r_Bad(irg);
336 * Transforms a SymConst.
338 static ir_node *gen_SymConst(ir_node *node) {
339 ir_graph *irg = current_ir_graph;
340 ir_node *block = be_transform_node(get_nodes_block(node));
341 dbg_info *dbgi = get_irn_dbg_info(node);
342 ir_mode *mode = get_irn_mode(node);
345 if (mode_is_float(mode)) {
347 if (USE_SSE2(env_cg))
348 cnst = new_rd_ia32_xConst(dbgi, irg, block);
350 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
351 set_ia32_ls_mode(cnst, mode);
353 cnst = new_rd_ia32_Const(dbgi, irg, block);
356 /* Const Nodes before the initial IncSP are a bad idea, because
357 * they could be spilled and we have no SP ready at that point yet
359 if (get_irg_start_block(irg) == block) {
360 add_irn_dep(cnst, get_irg_frame(irg));
363 set_ia32_Const_attr(cnst, node);
364 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
371 * SSE convert of an integer node into a floating point node.
373 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
374 ir_graph *irg, ir_node *block,
375 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
377 ir_node *noreg = ia32_new_NoReg_gp(cg);
378 ir_node *nomem = new_rd_NoMem(irg);
379 ir_node *old_pred = get_Cmp_left(old_node);
380 ir_mode *in_mode = get_irn_mode(old_pred);
381 int in_bits = get_mode_size_bits(in_mode);
382 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
384 set_ia32_ls_mode(conv, tgt_mode);
386 set_ia32_am_support(conv, ia32_am_Source);
388 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
394 * SSE convert of an float node into a double node.
396 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
397 ir_graph *irg, ir_node *block,
398 ir_node *in, ir_node *old_node)
400 ir_node *noreg = ia32_new_NoReg_gp(cg);
401 ir_node *nomem = new_rd_NoMem(irg);
402 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
404 set_ia32_am_support(conv, ia32_am_Source);
405 set_ia32_ls_mode(conv, mode_xmm);
406 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
412 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
413 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
414 static const struct {
416 const char *ent_name;
417 const char *cnst_str;
418 } names [ia32_known_const_max] = {
419 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
420 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
421 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
422 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
424 static ir_entity *ent_cache[ia32_known_const_max];
426 const char *tp_name, *ent_name, *cnst_str;
434 ent_name = names[kct].ent_name;
435 if (! ent_cache[kct]) {
436 tp_name = names[kct].tp_name;
437 cnst_str = names[kct].cnst_str;
439 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
441 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
442 tp = new_type_primitive(new_id_from_str(tp_name), mode);
443 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
445 set_entity_ld_ident(ent, get_entity_ident(ent));
446 set_entity_visibility(ent, visibility_local);
447 set_entity_variability(ent, variability_constant);
448 set_entity_allocation(ent, allocation_static);
450 /* we create a new entity here: It's initialization must resist on the
452 rem = current_ir_graph;
453 current_ir_graph = get_const_code_irg();
454 cnst = new_Const(mode, tv);
455 current_ir_graph = rem;
457 set_atomic_ent_value(ent, cnst);
459 /* cache the entry */
460 ent_cache[kct] = ent;
463 return ent_cache[kct];
468 * Prints the old node name on cg obst and returns a pointer to it.
470 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
471 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
473 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
474 obstack_1grow(isa->name_obst, 0);
475 return obstack_finish(isa->name_obst);
479 /* determine if one operator is an Imm */
480 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
482 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
484 return is_ia32_Cnst(op2) ? op2 : NULL;
488 /* determine if one operator is not an Imm */
489 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
490 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
493 static void fold_immediate(ir_node *node, int in1, int in2) {
497 if (!(env_cg->opt & IA32_OPT_IMMOPS))
500 left = get_irn_n(node, in1);
501 right = get_irn_n(node, in2);
502 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
503 /* we can only set right operand to immediate */
504 if(!is_ia32_commutative(node))
506 /* exchange left/right */
507 set_irn_n(node, in1, right);
508 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
509 copy_ia32_Immop_attr(node, left);
510 } else if(is_ia32_Cnst(right)) {
511 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
512 copy_ia32_Immop_attr(node, right);
517 clear_ia32_commutative(node);
518 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
522 * Construct a standard binary operation, set AM and immediate if required.
524 * @param op1 The first operand
525 * @param op2 The second operand
526 * @param func The node constructor function
527 * @return The constructed ia32 node.
529 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
530 construct_binop_func *func, int commutative)
532 ir_node *block = be_transform_node(get_nodes_block(node));
533 ir_node *new_op1 = NULL;
534 ir_node *new_op2 = NULL;
535 ir_node *new_node = NULL;
536 ir_graph *irg = current_ir_graph;
537 dbg_info *dbgi = get_irn_dbg_info(node);
538 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
539 ir_node *nomem = new_NoMem();
542 new_op2 = try_create_Immediate(op1, 0);
543 if(new_op2 != NULL) {
544 new_op1 = be_transform_node(op2);
549 if(new_op2 == NULL) {
550 new_op2 = try_create_Immediate(op2, 0);
551 if(new_op2 != NULL) {
552 new_op1 = be_transform_node(op1);
557 if(new_op2 == NULL) {
558 new_op1 = be_transform_node(op1);
559 new_op2 = be_transform_node(op2);
562 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
563 if (func == new_rd_ia32_IMul) {
564 set_ia32_am_support(new_node, ia32_am_Source);
566 set_ia32_am_support(new_node, ia32_am_Full);
569 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
571 set_ia32_commutative(new_node);
578 * Construct a standard binary operation, set AM and immediate if required.
580 * @param op1 The first operand
581 * @param op2 The second operand
582 * @param func The node constructor function
583 * @return The constructed ia32 node.
585 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
586 construct_binop_func *func)
588 ir_node *block = be_transform_node(get_nodes_block(node));
589 ir_node *new_op1 = be_transform_node(op1);
590 ir_node *new_op2 = be_transform_node(op2);
591 ir_node *new_node = NULL;
592 dbg_info *dbgi = get_irn_dbg_info(node);
593 ir_graph *irg = current_ir_graph;
594 ir_mode *mode = get_irn_mode(node);
595 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
596 ir_node *nomem = new_NoMem();
598 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
599 set_ia32_am_support(new_node, ia32_am_Source);
600 if (is_op_commutative(get_irn_op(node))) {
601 set_ia32_commutative(new_node);
603 if (USE_SSE2(env_cg)) {
604 set_ia32_ls_mode(new_node, mode);
607 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
614 * Construct a shift/rotate binary operation, sets AM and immediate if required.
616 * @param op1 The first operand
617 * @param op2 The second operand
618 * @param func The node constructor function
619 * @return The constructed ia32 node.
621 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
622 construct_binop_func *func)
624 ir_node *block = be_transform_node(get_nodes_block(node));
625 ir_node *new_op1 = be_transform_node(op1);
626 ir_node *new_op2 = be_transform_node(op2);
627 ir_node *new_op = NULL;
628 dbg_info *dbgi = get_irn_dbg_info(node);
629 ir_graph *irg = current_ir_graph;
630 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
631 ir_node *nomem = new_NoMem();
636 assert(! mode_is_float(get_irn_mode(node))
637 && "Shift/Rotate with float not supported");
639 /* Check if immediate optimization is on and */
640 /* if it's an operation with immediate. */
641 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
642 expr_op = get_expr_op(new_op1, new_op2);
644 assert((expr_op || imm_op) && "invalid operands");
647 /* We have two consts here: not yet supported */
651 /* Limit imm_op within range imm8 */
653 tv = get_ia32_Immop_tarval(imm_op);
656 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
657 set_ia32_Immop_tarval(imm_op, tv);
664 /* integer operations */
666 /* This is shift/rot with const */
667 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
669 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
670 copy_ia32_Immop_attr(new_op, imm_op);
672 /* This is a normal shift/rot */
673 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
674 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
678 set_ia32_am_support(new_op, ia32_am_Dest);
680 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
682 set_ia32_emit_cl(new_op);
689 * Construct a standard unary operation, set AM and immediate if required.
691 * @param op The operand
692 * @param func The node constructor function
693 * @return The constructed ia32 node.
695 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
697 ir_node *block = be_transform_node(get_nodes_block(node));
698 ir_node *new_op = be_transform_node(op);
699 ir_node *new_node = NULL;
700 ir_graph *irg = current_ir_graph;
701 dbg_info *dbgi = get_irn_dbg_info(node);
702 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
703 ir_node *nomem = new_NoMem();
705 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
706 DB((dbg, LEVEL_1, "INT unop ..."));
707 set_ia32_am_support(new_node, ia32_am_Dest);
709 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
715 * Creates an ia32 Add.
717 * @return the created ia32 Add node
719 static ir_node *gen_Add(ir_node *node) {
720 ir_node *block = be_transform_node(get_nodes_block(node));
721 ir_node *op1 = get_Add_left(node);
722 ir_node *new_op1 = be_transform_node(op1);
723 ir_node *op2 = get_Add_right(node);
724 ir_node *new_op2 = be_transform_node(op2);
725 ir_node *new_op = NULL;
726 ir_graph *irg = current_ir_graph;
727 dbg_info *dbgi = get_irn_dbg_info(node);
728 ir_mode *mode = get_irn_mode(node);
729 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
730 ir_node *nomem = new_NoMem();
731 ir_node *expr_op, *imm_op;
733 /* Check if immediate optimization is on and */
734 /* if it's an operation with immediate. */
735 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
736 expr_op = get_expr_op(new_op1, new_op2);
738 assert((expr_op || imm_op) && "invalid operands");
740 if (mode_is_float(mode)) {
742 if (USE_SSE2(env_cg))
743 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
745 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
750 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
751 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
753 /* No expr_op means, that we have two const - one symconst and */
754 /* one tarval or another symconst - because this case is not */
755 /* covered by constant folding */
756 /* We need to check for: */
757 /* 1) symconst + const -> becomes a LEA */
758 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
759 /* linker doesn't support two symconsts */
761 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
762 /* this is the 2nd case */
763 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
764 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
765 set_ia32_am_flavour(new_op, ia32_am_B);
766 set_ia32_am_support(new_op, ia32_am_Source);
767 set_ia32_op_type(new_op, ia32_AddrModeS);
769 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
770 } else if (tp1 == ia32_ImmSymConst) {
771 tarval *tv = get_ia32_Immop_tarval(new_op2);
772 long offs = get_tarval_long(tv);
774 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
775 add_irn_dep(new_op, get_irg_frame(irg));
776 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
778 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
779 add_ia32_am_offs_int(new_op, offs);
780 set_ia32_am_flavour(new_op, ia32_am_OB);
781 set_ia32_am_support(new_op, ia32_am_Source);
782 set_ia32_op_type(new_op, ia32_AddrModeS);
783 } else if (tp2 == ia32_ImmSymConst) {
784 tarval *tv = get_ia32_Immop_tarval(new_op1);
785 long offs = get_tarval_long(tv);
787 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
788 add_irn_dep(new_op, get_irg_frame(irg));
789 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
791 add_ia32_am_offs_int(new_op, offs);
792 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
793 set_ia32_am_flavour(new_op, ia32_am_OB);
794 set_ia32_am_support(new_op, ia32_am_Source);
795 set_ia32_op_type(new_op, ia32_AddrModeS);
797 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
798 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
799 tarval *restv = tarval_add(tv1, tv2);
801 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
803 new_op = new_rd_ia32_Const(dbgi, irg, block);
804 set_ia32_Const_tarval(new_op, restv);
805 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
808 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
811 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
812 tarval_classification_t class_tv, class_negtv;
813 tarval *tv = get_ia32_Immop_tarval(imm_op);
815 /* optimize tarvals */
816 class_tv = classify_tarval(tv);
817 class_negtv = classify_tarval(tarval_neg(tv));
819 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
820 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
821 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
822 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
824 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
825 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
826 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
827 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
833 /* This is a normal add */
834 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
837 set_ia32_am_support(new_op, ia32_am_Full);
838 set_ia32_commutative(new_op);
840 fold_immediate(new_op, 2, 3);
842 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
848 static ir_node *create_ia32_Mul(ir_node *node) {
849 ir_graph *irg = current_ir_graph;
850 dbg_info *dbgi = get_irn_dbg_info(node);
851 ir_node *block = be_transform_node(get_nodes_block(node));
852 ir_node *op1 = get_Mul_left(node);
853 ir_node *op2 = get_Mul_right(node);
854 ir_node *new_op1 = be_transform_node(op1);
855 ir_node *new_op2 = be_transform_node(op2);
856 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
857 ir_node *proj_EAX, *proj_EDX, *res;
860 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
861 set_ia32_commutative(res);
862 set_ia32_am_support(res, ia32_am_Source);
864 /* imediates are not supported, so no fold_immediate */
865 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
866 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
870 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
878 * Creates an ia32 Mul.
880 * @return the created ia32 Mul node
882 static ir_node *gen_Mul(ir_node *node) {
883 ir_node *op1 = get_Mul_left(node);
884 ir_node *op2 = get_Mul_right(node);
885 ir_mode *mode = get_irn_mode(node);
887 if (mode_is_float(mode)) {
889 if (USE_SSE2(env_cg))
890 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
892 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
896 for the lower 32bit of the result it doesn't matter whether we use
897 signed or unsigned multiplication so we use IMul as it has fewer
900 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
904 * Creates an ia32 Mulh.
905 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
906 * this result while Mul returns the lower 32 bit.
908 * @return the created ia32 Mulh node
910 static ir_node *gen_Mulh(ir_node *node) {
911 ir_node *block = be_transform_node(get_nodes_block(node));
912 ir_node *op1 = get_irn_n(node, 0);
913 ir_node *new_op1 = be_transform_node(op1);
914 ir_node *op2 = get_irn_n(node, 1);
915 ir_node *new_op2 = be_transform_node(op2);
916 ir_graph *irg = current_ir_graph;
917 dbg_info *dbgi = get_irn_dbg_info(node);
918 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
919 ir_mode *mode = get_irn_mode(node);
920 ir_node *proj_EAX, *proj_EDX, *res;
923 assert(!mode_is_float(mode) && "Mulh with float not supported");
924 if (mode_is_signed(mode)) {
925 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
927 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
930 set_ia32_commutative(res);
931 set_ia32_am_support(res, ia32_am_Source);
933 set_ia32_am_support(res, ia32_am_Source);
935 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
936 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
940 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
948 * Creates an ia32 And.
950 * @return The created ia32 And node
952 static ir_node *gen_And(ir_node *node) {
953 ir_node *op1 = get_And_left(node);
954 ir_node *op2 = get_And_right(node);
956 assert (! mode_is_float(get_irn_mode(node)));
957 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
963 * Creates an ia32 Or.
965 * @return The created ia32 Or node
967 static ir_node *gen_Or(ir_node *node) {
968 ir_node *op1 = get_Or_left(node);
969 ir_node *op2 = get_Or_right(node);
971 assert (! mode_is_float(get_irn_mode(node)));
972 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
978 * Creates an ia32 Eor.
980 * @return The created ia32 Eor node
982 static ir_node *gen_Eor(ir_node *node) {
983 ir_node *op1 = get_Eor_left(node);
984 ir_node *op2 = get_Eor_right(node);
986 assert(! mode_is_float(get_irn_mode(node)));
987 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
993 * Creates an ia32 Max.
995 * @return the created ia32 Max node
997 static ir_node *gen_Max(ir_node *node) {
998 ir_node *block = be_transform_node(get_nodes_block(node));
999 ir_node *op1 = get_irn_n(node, 0);
1000 ir_node *new_op1 = be_transform_node(op1);
1001 ir_node *op2 = get_irn_n(node, 1);
1002 ir_node *new_op2 = be_transform_node(op2);
1003 ir_graph *irg = current_ir_graph;
1004 ir_mode *mode = get_irn_mode(node);
1005 dbg_info *dbgi = get_irn_dbg_info(node);
1006 ir_mode *op_mode = get_irn_mode(op1);
1009 assert(get_mode_size_bits(mode) == 32);
1011 if (mode_is_float(mode)) {
1013 if (USE_SSE2(env_cg)) {
1014 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1016 panic("Can't create Max node");
1019 long pnc = pn_Cmp_Gt;
1020 if (! mode_is_signed(op_mode)) {
1021 pnc |= ia32_pn_Cmp_Unsigned;
1023 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1024 new_op1, new_op2, pnc);
1026 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1032 * Creates an ia32 Min.
1034 * @return the created ia32 Min node
1036 static ir_node *gen_Min(ir_node *node) {
1037 ir_node *block = be_transform_node(get_nodes_block(node));
1038 ir_node *op1 = get_irn_n(node, 0);
1039 ir_node *new_op1 = be_transform_node(op1);
1040 ir_node *op2 = get_irn_n(node, 1);
1041 ir_node *new_op2 = be_transform_node(op2);
1042 ir_graph *irg = current_ir_graph;
1043 ir_mode *mode = get_irn_mode(node);
1044 dbg_info *dbgi = get_irn_dbg_info(node);
1045 ir_mode *op_mode = get_irn_mode(op1);
1048 assert(get_mode_size_bits(mode) == 32);
1050 if (mode_is_float(mode)) {
1052 if (USE_SSE2(env_cg)) {
1053 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1055 panic("can't create Min node");
1058 long pnc = pn_Cmp_Lt;
1059 if (! mode_is_signed(op_mode)) {
1060 pnc |= ia32_pn_Cmp_Unsigned;
1062 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1063 new_op1, new_op2, pnc);
1065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1072 * Creates an ia32 Sub.
1074 * @return The created ia32 Sub node
1076 static ir_node *gen_Sub(ir_node *node) {
1077 ir_node *block = be_transform_node(get_nodes_block(node));
1078 ir_node *op1 = get_Sub_left(node);
1079 ir_node *new_op1 = be_transform_node(op1);
1080 ir_node *op2 = get_Sub_right(node);
1081 ir_node *new_op2 = be_transform_node(op2);
1082 ir_node *new_op = NULL;
1083 ir_graph *irg = current_ir_graph;
1084 dbg_info *dbgi = get_irn_dbg_info(node);
1085 ir_mode *mode = get_irn_mode(node);
1086 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1087 ir_node *nomem = new_NoMem();
1088 ir_node *expr_op, *imm_op;
1090 /* Check if immediate optimization is on and */
1091 /* if it's an operation with immediate. */
1092 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1093 expr_op = get_expr_op(new_op1, new_op2);
1095 assert((expr_op || imm_op) && "invalid operands");
1097 if (mode_is_float(mode)) {
1099 if (USE_SSE2(env_cg))
1100 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1102 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1107 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1108 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1110 /* No expr_op means, that we have two const - one symconst and */
1111 /* one tarval or another symconst - because this case is not */
1112 /* covered by constant folding */
1113 /* We need to check for: */
1114 /* 1) symconst - const -> becomes a LEA */
1115 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1116 /* linker doesn't support two symconsts */
1117 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1118 /* this is the 2nd case */
1119 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1120 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1121 set_ia32_am_sc_sign(new_op);
1122 set_ia32_am_flavour(new_op, ia32_am_B);
1124 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 } else if (tp1 == ia32_ImmSymConst) {
1126 tarval *tv = get_ia32_Immop_tarval(new_op2);
1127 long offs = get_tarval_long(tv);
1129 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1130 add_irn_dep(new_op, get_irg_frame(irg));
1131 DBG_OPT_LEA3(op1, op2, node, new_op);
1133 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1134 add_ia32_am_offs_int(new_op, -offs);
1135 set_ia32_am_flavour(new_op, ia32_am_OB);
1136 set_ia32_am_support(new_op, ia32_am_Source);
1137 set_ia32_op_type(new_op, ia32_AddrModeS);
1138 } else if (tp2 == ia32_ImmSymConst) {
1139 tarval *tv = get_ia32_Immop_tarval(new_op1);
1140 long offs = get_tarval_long(tv);
1142 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1143 add_irn_dep(new_op, get_irg_frame(irg));
1144 DBG_OPT_LEA3(op1, op2, node, new_op);
1146 add_ia32_am_offs_int(new_op, offs);
1147 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1148 set_ia32_am_sc_sign(new_op);
1149 set_ia32_am_flavour(new_op, ia32_am_OB);
1150 set_ia32_am_support(new_op, ia32_am_Source);
1151 set_ia32_op_type(new_op, ia32_AddrModeS);
1153 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1154 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1155 tarval *restv = tarval_sub(tv1, tv2);
1157 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1159 new_op = new_rd_ia32_Const(dbgi, irg, block);
1160 set_ia32_Const_tarval(new_op, restv);
1161 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1164 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1166 } else if (imm_op) {
1167 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1168 tarval_classification_t class_tv, class_negtv;
1169 tarval *tv = get_ia32_Immop_tarval(imm_op);
1171 /* optimize tarvals */
1172 class_tv = classify_tarval(tv);
1173 class_negtv = classify_tarval(tarval_neg(tv));
1175 if (class_tv == TV_CLASSIFY_ONE) {
1176 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1177 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1178 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1180 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1181 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1182 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1183 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1189 /* This is a normal sub */
1190 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1192 /* set AM support */
1193 set_ia32_am_support(new_op, ia32_am_Full);
1195 fold_immediate(new_op, 2, 3);
1197 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1205 * Generates an ia32 DivMod with additional infrastructure for the
1206 * register allocator if needed.
1208 * @param dividend -no comment- :)
1209 * @param divisor -no comment- :)
1210 * @param dm_flav flavour_Div/Mod/DivMod
1211 * @return The created ia32 DivMod node
1213 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1214 ir_node *divisor, ia32_op_flavour_t dm_flav)
1216 ir_node *block = be_transform_node(get_nodes_block(node));
1217 ir_node *new_dividend = be_transform_node(dividend);
1218 ir_node *new_divisor = be_transform_node(divisor);
1219 ir_graph *irg = current_ir_graph;
1220 dbg_info *dbgi = get_irn_dbg_info(node);
1221 ir_mode *mode = get_irn_mode(node);
1222 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1223 ir_node *res, *proj_div, *proj_mod;
1224 ir_node *edx_node, *cltd;
1225 ir_node *in_keep[2];
1226 ir_node *mem, *new_mem;
1227 ir_node *projs[pn_DivMod_max];
1230 ia32_collect_Projs(node, projs, pn_DivMod_max);
1232 proj_div = proj_mod = NULL;
1236 mem = get_Div_mem(node);
1237 mode = get_Div_resmode(node);
1238 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1239 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1242 mem = get_Mod_mem(node);
1243 mode = get_Mod_resmode(node);
1244 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1245 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1247 case flavour_DivMod:
1248 mem = get_DivMod_mem(node);
1249 mode = get_DivMod_resmode(node);
1250 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1251 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1252 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1255 panic("invalid divmod flavour!");
1257 new_mem = be_transform_node(mem);
1259 if (mode_is_signed(mode)) {
1260 /* in signed mode, we need to sign extend the dividend */
1261 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1262 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1263 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1265 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1266 add_irn_dep(edx_node, be_abi_get_start_barrier(env_cg->birg->abi));
1267 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1270 if (mode_is_signed(mode)) {
1271 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1273 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1276 set_ia32_exc_label(res, has_exc);
1278 /* Matze: code can't handle this at the moment... */
1280 /* set AM support */
1281 set_ia32_am_support(res, ia32_am_Source);
1284 /* check, which Proj-Keep, we need to add */
1286 if (proj_div == NULL) {
1287 /* We have only mod result: add div res Proj-Keep */
1288 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1291 if (proj_mod == NULL) {
1292 /* We have only div result: add mod res Proj-Keep */
1293 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1297 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1299 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1306 * Wrapper for generate_DivMod. Sets flavour_Mod.
1309 static ir_node *gen_Mod(ir_node *node) {
1310 return generate_DivMod(node, get_Mod_left(node),
1311 get_Mod_right(node), flavour_Mod);
1315 * Wrapper for generate_DivMod. Sets flavour_Div.
1318 static ir_node *gen_Div(ir_node *node) {
1319 return generate_DivMod(node, get_Div_left(node),
1320 get_Div_right(node), flavour_Div);
1324 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1326 static ir_node *gen_DivMod(ir_node *node) {
1327 return generate_DivMod(node, get_DivMod_left(node),
1328 get_DivMod_right(node), flavour_DivMod);
1334 * Creates an ia32 floating Div.
1336 * @return The created ia32 xDiv node
1338 static ir_node *gen_Quot(ir_node *node) {
1339 ir_node *block = be_transform_node(get_nodes_block(node));
1340 ir_node *op1 = get_Quot_left(node);
1341 ir_node *new_op1 = be_transform_node(op1);
1342 ir_node *op2 = get_Quot_right(node);
1343 ir_node *new_op2 = be_transform_node(op2);
1344 ir_graph *irg = current_ir_graph;
1345 dbg_info *dbgi = get_irn_dbg_info(node);
1346 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1347 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1351 if (USE_SSE2(env_cg)) {
1352 ir_mode *mode = get_irn_mode(op1);
1353 if (is_ia32_xConst(new_op2)) {
1354 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1355 set_ia32_am_support(new_op, ia32_am_None);
1356 copy_ia32_Immop_attr(new_op, new_op2);
1358 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1359 // Matze: disabled for now, spillslot coalescer fails
1360 //set_ia32_am_support(new_op, ia32_am_Source);
1362 set_ia32_ls_mode(new_op, mode);
1364 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1365 // Matze: disabled for now (spillslot coalescer fails)
1366 //set_ia32_am_support(new_op, ia32_am_Source);
1368 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1374 * Creates an ia32 Shl.
1376 * @return The created ia32 Shl node
1378 static ir_node *gen_Shl(ir_node *node) {
1379 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1386 * Creates an ia32 Shr.
1388 * @return The created ia32 Shr node
1390 static ir_node *gen_Shr(ir_node *node) {
1391 return gen_shift_binop(node, get_Shr_left(node),
1392 get_Shr_right(node), new_rd_ia32_Shr);
1398 * Creates an ia32 Sar.
1400 * @return The created ia32 Shrs node
1402 static ir_node *gen_Shrs(ir_node *node) {
1403 return gen_shift_binop(node, get_Shrs_left(node),
1404 get_Shrs_right(node), new_rd_ia32_Sar);
1410 * Creates an ia32 RotL.
1412 * @param op1 The first operator
1413 * @param op2 The second operator
1414 * @return The created ia32 RotL node
1416 static ir_node *gen_RotL(ir_node *node,
1417 ir_node *op1, ir_node *op2) {
1418 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1424 * Creates an ia32 RotR.
1425 * NOTE: There is no RotR with immediate because this would always be a RotL
1426 * "imm-mode_size_bits" which can be pre-calculated.
1428 * @param op1 The first operator
1429 * @param op2 The second operator
1430 * @return The created ia32 RotR node
1432 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1434 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1440 * Creates an ia32 RotR or RotL (depending on the found pattern).
1442 * @return The created ia32 RotL or RotR node
1444 static ir_node *gen_Rot(ir_node *node) {
1445 ir_node *rotate = NULL;
1446 ir_node *op1 = get_Rot_left(node);
1447 ir_node *op2 = get_Rot_right(node);
1449 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1450 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1451 that means we can create a RotR instead of an Add and a RotL */
1453 if (get_irn_op(op2) == op_Add) {
1455 ir_node *left = get_Add_left(add);
1456 ir_node *right = get_Add_right(add);
1457 if (is_Const(right)) {
1458 tarval *tv = get_Const_tarval(right);
1459 ir_mode *mode = get_irn_mode(node);
1460 long bits = get_mode_size_bits(mode);
1462 if (get_irn_op(left) == op_Minus &&
1463 tarval_is_long(tv) &&
1464 get_tarval_long(tv) == bits)
1466 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1467 rotate = gen_RotR(node, op1, get_Minus_op(left));
1472 if (rotate == NULL) {
1473 rotate = gen_RotL(node, op1, op2);
1482 * Transforms a Minus node.
1484 * @param op The Minus operand
1485 * @return The created ia32 Minus node
1487 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1488 ir_node *block = be_transform_node(get_nodes_block(node));
1489 ir_graph *irg = current_ir_graph;
1490 dbg_info *dbgi = get_irn_dbg_info(node);
1491 ir_mode *mode = get_irn_mode(node);
1496 if (mode_is_float(mode)) {
1497 ir_node *new_op = be_transform_node(op);
1499 if (USE_SSE2(env_cg)) {
1500 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1501 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1502 ir_node *nomem = new_rd_NoMem(irg);
1504 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1506 size = get_mode_size_bits(mode);
1507 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1509 set_ia32_am_sc(res, ent);
1510 set_ia32_op_type(res, ia32_AddrModeS);
1511 set_ia32_ls_mode(res, mode);
1513 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1516 res = gen_unop(node, op, new_rd_ia32_Neg);
1519 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1525 * Transforms a Minus node.
1527 * @return The created ia32 Minus node
1529 static ir_node *gen_Minus(ir_node *node) {
1530 return gen_Minus_ex(node, get_Minus_op(node));
1535 * Transforms a Not node.
1537 * @return The created ia32 Not node
1539 static ir_node *gen_Not(ir_node *node) {
1540 ir_node *op = get_Not_op(node);
1542 assert (! mode_is_float(get_irn_mode(node)));
1543 return gen_unop(node, op, new_rd_ia32_Not);
1549 * Transforms an Abs node.
1551 * @return The created ia32 Abs node
1553 static ir_node *gen_Abs(ir_node *node) {
1554 ir_node *block = be_transform_node(get_nodes_block(node));
1555 ir_node *op = get_Abs_op(node);
1556 ir_node *new_op = be_transform_node(op);
1557 ir_graph *irg = current_ir_graph;
1558 dbg_info *dbgi = get_irn_dbg_info(node);
1559 ir_mode *mode = get_irn_mode(node);
1560 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1561 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1562 ir_node *nomem = new_NoMem();
1563 ir_node *res, *p_eax, *p_edx;
1567 if (mode_is_float(mode)) {
1569 if (USE_SSE2(env_cg)) {
1570 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1572 size = get_mode_size_bits(mode);
1573 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1575 set_ia32_am_sc(res, ent);
1577 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1579 set_ia32_op_type(res, ia32_AddrModeS);
1580 set_ia32_ls_mode(res, mode);
1583 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1584 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1588 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1589 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1591 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1592 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1594 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1595 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1597 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1598 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1607 * Transforms a Load.
1609 * @return the created ia32 Load node
1611 static ir_node *gen_Load(ir_node *node) {
1612 ir_node *block = be_transform_node(get_nodes_block(node));
1613 ir_node *ptr = get_Load_ptr(node);
1614 ir_node *new_ptr = be_transform_node(ptr);
1615 ir_node *mem = get_Load_mem(node);
1616 ir_node *new_mem = be_transform_node(mem);
1617 ir_graph *irg = current_ir_graph;
1618 dbg_info *dbgi = get_irn_dbg_info(node);
1619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1620 ir_mode *mode = get_Load_mode(node);
1622 ir_node *lptr = new_ptr;
1625 ir_node *projs[pn_Load_max];
1626 ia32_am_flavour_t am_flav = ia32_am_B;
1628 ia32_collect_Projs(node, projs, pn_Load_max);
1630 /* address might be a constant (symconst or absolute address) */
1631 if (is_ia32_Const(new_ptr)) {
1636 if (mode_is_float(mode)) {
1638 if (USE_SSE2(env_cg)) {
1639 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1640 res_mode = mode_xmm;
1642 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1643 res_mode = mode_vfp;
1646 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1651 check for special case: the loaded value might not be used
1653 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1654 /* add a result proj and a Keep to produce a pseudo use */
1655 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1657 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1660 /* base is a constant address */
1662 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1663 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1664 am_flav = ia32_am_N;
1666 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1667 long offs = get_tarval_long(tv);
1669 add_ia32_am_offs_int(new_op, offs);
1670 am_flav = ia32_am_O;
1674 set_irn_pinned(new_op, get_irn_pinned(node));
1675 set_ia32_am_support(new_op, ia32_am_Source);
1676 set_ia32_op_type(new_op, ia32_AddrModeS);
1677 set_ia32_am_flavour(new_op, am_flav);
1678 set_ia32_ls_mode(new_op, mode);
1680 /* make sure we are scheduled behind the initial IncSP/Barrier
1681 * to avoid spills being placed before it
1683 if (block == get_irg_start_block(irg)) {
1684 add_irn_dep(new_op, get_irg_frame(irg));
1687 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1688 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1696 * Transforms a Store.
1698 * @return the created ia32 Store node
1700 static ir_node *gen_Store(ir_node *node) {
1701 ir_node *block = be_transform_node(get_nodes_block(node));
1702 ir_node *ptr = get_Store_ptr(node);
1703 ir_node *new_ptr = be_transform_node(ptr);
1704 ir_node *val = get_Store_value(node);
1705 ir_node *new_val = be_transform_node(val);
1706 ir_node *mem = get_Store_mem(node);
1707 ir_node *new_mem = be_transform_node(mem);
1708 ir_graph *irg = current_ir_graph;
1709 dbg_info *dbgi = get_irn_dbg_info(node);
1710 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1711 ir_node *sptr = new_ptr;
1712 ir_mode *mode = get_irn_mode(val);
1713 ir_node *sval = new_val;
1716 ia32_am_flavour_t am_flav = ia32_am_B;
1718 if (is_ia32_Const(new_val)) {
1719 assert(!mode_is_float(mode));
1723 /* address might be a constant (symconst or absolute address) */
1724 if (is_ia32_Const(new_ptr)) {
1729 if (mode_is_float(mode)) {
1731 if (USE_SSE2(env_cg)) {
1732 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1734 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1736 } else if (get_mode_size_bits(mode) == 8) {
1737 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1739 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1742 /* stored const is an immediate value */
1743 if (is_ia32_Const(new_val)) {
1744 assert(!mode_is_float(mode));
1745 copy_ia32_Immop_attr(new_op, new_val);
1748 /* base is an constant address */
1750 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1751 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1752 am_flav = ia32_am_N;
1754 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1755 long offs = get_tarval_long(tv);
1757 add_ia32_am_offs_int(new_op, offs);
1758 am_flav = ia32_am_O;
1762 set_irn_pinned(new_op, get_irn_pinned(node));
1763 set_ia32_am_support(new_op, ia32_am_Dest);
1764 set_ia32_op_type(new_op, ia32_AddrModeD);
1765 set_ia32_am_flavour(new_op, am_flav);
1766 set_ia32_ls_mode(new_op, mode);
1768 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1769 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1777 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1779 * @return The transformed node.
1781 static ir_node *gen_Cond(ir_node *node) {
1782 ir_node *block = be_transform_node(get_nodes_block(node));
1783 ir_graph *irg = current_ir_graph;
1784 dbg_info *dbgi = get_irn_dbg_info(node);
1785 ir_node *sel = get_Cond_selector(node);
1786 ir_mode *sel_mode = get_irn_mode(sel);
1787 ir_node *res = NULL;
1788 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1789 ir_node *cnst, *expr;
1791 if (is_Proj(sel) && sel_mode == mode_b) {
1792 ir_node *pred = get_Proj_pred(sel);
1793 ir_node *cmp_a = get_Cmp_left(pred);
1794 ir_node *new_cmp_a = be_transform_node(cmp_a);
1795 ir_node *cmp_b = get_Cmp_right(pred);
1796 ir_node *new_cmp_b = be_transform_node(cmp_b);
1797 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1798 ir_node *nomem = new_NoMem();
1800 int pnc = get_Proj_proj(sel);
1801 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1802 pnc |= ia32_pn_Cmp_Unsigned;
1805 /* check if we can use a CondJmp with immediate */
1806 cnst = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1807 expr = get_expr_op(new_cmp_a, new_cmp_b);
1809 if (cnst != NULL && expr != NULL) {
1810 /* immop has to be the right operand, we might need to flip pnc */
1811 if(cnst != new_cmp_b) {
1812 pnc = get_inversed_pnc(pnc);
1815 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1816 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1817 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1819 /* a Cmp A =/!= 0 */
1820 ir_node *op1 = expr;
1821 ir_node *op2 = expr;
1824 /* check, if expr is an only once used And operation */
1825 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1826 op1 = get_irn_n(expr, 2);
1827 op2 = get_irn_n(expr, 3);
1829 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1831 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1832 set_ia32_pncode(res, pnc);
1835 copy_ia32_Immop_attr(res, expr);
1838 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1843 if (mode_is_float(cmp_mode)) {
1845 if (USE_SSE2(env_cg)) {
1846 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1847 set_ia32_ls_mode(res, cmp_mode);
1853 assert(get_mode_size_bits(cmp_mode) == 32);
1854 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1856 copy_ia32_Immop_attr(res, cnst);
1859 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1861 if (mode_is_float(cmp_mode)) {
1863 if (USE_SSE2(env_cg)) {
1864 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1865 set_ia32_ls_mode(res, cmp_mode);
1868 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1869 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1870 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1874 assert(get_mode_size_bits(cmp_mode) == 32);
1875 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1876 set_ia32_commutative(res);
1880 set_ia32_pncode(res, pnc);
1881 // Matze: disabled for now, because the default collect_spills_walker
1882 // is not able to detect the mode of the spilled value
1883 // moreover, the lea optimize phase freely exchanges left/right
1884 // without updating the pnc
1885 //set_ia32_am_support(res, ia32_am_Source);
1888 /* determine the smallest switch case value */
1889 ir_node *new_sel = be_transform_node(sel);
1890 int switch_min = INT_MAX;
1891 const ir_edge_t *edge;
1893 foreach_out_edge(node, edge) {
1894 int pn = get_Proj_proj(get_edge_src_irn(edge));
1895 switch_min = pn < switch_min ? pn : switch_min;
1899 /* if smallest switch case is not 0 we need an additional sub */
1900 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1901 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1902 add_ia32_am_offs_int(res, -switch_min);
1903 set_ia32_am_flavour(res, ia32_am_OB);
1904 set_ia32_am_support(res, ia32_am_Source);
1905 set_ia32_op_type(res, ia32_AddrModeS);
1908 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1909 set_ia32_pncode(res, get_Cond_defaultProj(node));
1912 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1919 * Transforms a CopyB node.
1921 * @return The transformed node.
1923 static ir_node *gen_CopyB(ir_node *node) {
1924 ir_node *block = be_transform_node(get_nodes_block(node));
1925 ir_node *src = get_CopyB_src(node);
1926 ir_node *new_src = be_transform_node(src);
1927 ir_node *dst = get_CopyB_dst(node);
1928 ir_node *new_dst = be_transform_node(dst);
1929 ir_node *mem = get_CopyB_mem(node);
1930 ir_node *new_mem = be_transform_node(mem);
1931 ir_node *res = NULL;
1932 ir_graph *irg = current_ir_graph;
1933 dbg_info *dbgi = get_irn_dbg_info(node);
1934 int size = get_type_size_bytes(get_CopyB_type(node));
1935 ir_mode *dst_mode = get_irn_mode(dst);
1936 ir_mode *src_mode = get_irn_mode(src);
1940 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1941 /* then we need the size explicitly in ECX. */
1942 if (size >= 32 * 4) {
1943 rem = size & 0x3; /* size % 4 */
1946 res = new_rd_ia32_Const(dbgi, irg, block);
1947 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1948 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1950 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1953 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1954 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1955 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1956 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1957 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1960 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1961 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1963 /* ok: now attach Proj's because movsd will destroy esi and edi */
1964 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1965 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1966 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1969 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1975 ir_node *gen_be_Copy(ir_node *node)
1977 ir_node *result = be_duplicate_node(node);
1978 ir_mode *mode = get_irn_mode(result);
1980 if (mode_needs_gp_reg(mode)) {
1981 set_irn_mode(result, mode_Iu);
1990 * Transforms a Mux node into CMov.
1992 * @return The transformed node.
1994 static ir_node *gen_Mux(ir_node *node) {
1995 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1996 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1998 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2004 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
2005 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
2006 ir_node *psi_default);
2009 * Transforms a Psi node into CMov.
2011 * @return The transformed node.
2013 static ir_node *gen_Psi(ir_node *node) {
2014 ir_node *block = be_transform_node(get_nodes_block(node));
2015 ir_node *psi_true = get_Psi_val(node, 0);
2016 ir_node *psi_default = get_Psi_default(node);
2017 ia32_code_gen_t *cg = env_cg;
2018 ir_graph *irg = current_ir_graph;
2019 dbg_info *dbgi = get_irn_dbg_info(node);
2020 ir_node *cond = get_Psi_cond(node, 0);
2021 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2022 ir_node *nomem = new_NoMem();
2024 ir_node *cmp, *cmp_a, *cmp_b;
2025 ir_node *new_cmp_a, *new_cmp_b;
2029 assert(get_Psi_n_conds(node) == 1);
2030 assert(get_irn_mode(cond) == mode_b);
2032 if(is_And(cond) || is_Or(cond)) {
2033 ir_node *new_cond = be_transform_node(cond);
2034 tarval *tv_zero = new_tarval_from_long(0, mode_Iu);
2035 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0,
2037 arch_set_irn_register(env_cg->arch_env, zero,
2038 &ia32_gp_regs[REG_GP_NOREG]);
2040 /* we have to compare the result against zero */
2041 new_cmp_a = new_cond;
2045 cmp = get_Proj_pred(cond);
2046 cmp_a = get_Cmp_left(cmp);
2047 cmp_b = get_Cmp_right(cmp);
2048 cmp_mode = get_irn_mode(cmp_a);
2049 pnc = get_Proj_proj(cond);
2051 new_cmp_b = try_create_Immediate(cmp_b, 0);
2052 if(new_cmp_b == NULL) {
2053 new_cmp_b = try_create_Immediate(cmp_a, 0);
2054 if(new_cmp_b != NULL) {
2055 pnc = get_inversed_pnc(pnc);
2056 new_cmp_a = be_transform_node(cmp_b);
2059 new_cmp_a = be_transform_node(cmp_a);
2061 if(new_cmp_b == NULL) {
2062 new_cmp_a = be_transform_node(cmp_a);
2063 new_cmp_b = be_transform_node(cmp_b);
2066 if (!mode_is_signed(cmp_mode)) {
2067 pnc |= ia32_pn_Cmp_Unsigned;
2071 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2072 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2073 new_cmp_a, new_cmp_b, nomem, pnc);
2074 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2075 pnc = get_inversed_pnc(pnc);
2076 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2077 new_cmp_a, new_cmp_b, nomem, pnc);
2079 ir_node *new_psi_true = be_transform_node(psi_true);
2080 ir_node *new_psi_default = be_transform_node(psi_default);
2081 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2082 new_psi_true, new_psi_default, pnc);
2084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2088 if (mode_is_float(mode)) {
2089 if(mode_is_float(cmp_mode)) {
2090 pnc |= ia32_pn_Cmp_Unsigned;
2093 /* floating point psi */
2096 /* 1st case: compare operands are float too */
2098 /* psi(cmp(a, b), t, f) can be done as: */
2099 /* tmp = cmp a, b */
2100 /* tmp2 = t and tmp */
2101 /* tmp3 = f and not tmp */
2102 /* res = tmp2 or tmp3 */
2104 /* in case the compare operands are int, we move them into xmm register */
2105 if (! mode_is_float(get_irn_mode(cmp_a))) {
2106 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2107 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2109 pnc |= 8; /* transform integer compare to fp compare */
2112 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2113 set_ia32_pncode(new_op, pnc);
2114 set_ia32_am_support(new_op, ia32_am_Source);
2115 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2117 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2118 set_ia32_am_support(and1, ia32_am_None);
2119 set_ia32_commutative(and1);
2120 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2122 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2123 set_ia32_am_support(and2, ia32_am_None);
2124 set_ia32_commutative(and2);
2125 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2127 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2128 set_ia32_am_support(new_op, ia32_am_None);
2129 set_ia32_commutative(new_op);
2130 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2134 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2135 set_ia32_pncode(new_op, pnc);
2136 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2141 construct_binop_func *set_func = NULL;
2142 cmov_func_t *cmov_func = NULL;
2144 if (mode_is_float(get_irn_mode(cmp_a))) {
2145 /* 1st case: compare operands are floats */
2150 set_func = new_rd_ia32_xCmpSet;
2151 cmov_func = new_rd_ia32_xCmpCMov;
2155 set_func = new_rd_ia32_vfCmpSet;
2156 cmov_func = new_rd_ia32_vfCmpCMov;
2159 pnc &= ~0x8; /* fp compare -> int compare */
2162 /* 2nd case: compare operand are integer too */
2163 set_func = new_rd_ia32_CmpSet;
2164 cmov_func = new_rd_ia32_CmpCMov;
2167 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2168 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2169 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2170 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2171 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2172 set_ia32_pncode(new_op, pnc);
2174 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2175 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2176 /* we invert condition and set default to 0 */
2177 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2178 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2181 /* otherwise: use CMOVcc */
2182 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2183 set_ia32_pncode(new_op, pnc);
2186 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2189 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2190 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2191 new_op = gen_binop(node, cmp_a, cmp_b, set_func, 0);
2192 set_ia32_pncode(new_op, pnc);
2193 set_ia32_am_support(new_op, ia32_am_Source);
2195 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2196 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2197 /* we invert condition and set default to 0 */
2198 new_op = gen_binop(node, cmp_a, cmp_b, set_func, 0);
2199 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2200 set_ia32_am_support(new_op, ia32_am_Source);
2203 /* otherwise: use CMOVcc */
2204 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2205 set_ia32_pncode(new_op, pnc);
2206 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2217 * Following conversion rules apply:
2221 * 1) n bit -> m bit n > m (downscale)
2223 * 2) n bit -> m bit n == m (sign change)
2225 * 3) n bit -> m bit n < m (upscale)
2226 * a) source is signed: movsx
2227 * b) source is unsigned: and with lower bits sets
2231 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2235 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2239 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2240 * x87 is mode_E internally, conversions happen only at load and store
2241 * in non-strict semantic
2245 * Create a conversion from x87 state register to general purpose.
2247 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2248 ir_node *block = be_transform_node(get_nodes_block(node));
2249 ir_node *op = get_Conv_op(node);
2250 ir_node *new_op = be_transform_node(op);
2251 ia32_code_gen_t *cg = env_cg;
2252 ir_graph *irg = current_ir_graph;
2253 dbg_info *dbgi = get_irn_dbg_info(node);
2254 ir_node *noreg = ia32_new_NoReg_gp(cg);
2255 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2256 ir_node *fist, *load;
2259 fist = new_rd_ia32_vfist(dbgi, irg, block,
2260 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2262 set_irn_pinned(load, op_pin_state_floats);
2263 set_ia32_use_frame(fist);
2264 set_ia32_am_support(fist, ia32_am_Dest);
2265 set_ia32_op_type(fist, ia32_AddrModeD);
2266 set_ia32_am_flavour(fist, ia32_am_B);
2267 set_ia32_ls_mode(fist, mode_Iu);
2268 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2271 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2273 set_irn_pinned(load, op_pin_state_floats);
2274 set_ia32_use_frame(load);
2275 set_ia32_am_support(load, ia32_am_Source);
2276 set_ia32_op_type(load, ia32_AddrModeS);
2277 set_ia32_am_flavour(load, ia32_am_B);
2278 set_ia32_ls_mode(load, mode_Iu);
2279 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2281 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2285 * Create a conversion from general purpose to x87 register
2287 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2288 ir_node *block = be_transform_node(get_nodes_block(node));
2289 ir_node *op = get_Conv_op(node);
2290 ir_node *new_op = be_transform_node(op);
2291 ir_graph *irg = current_ir_graph;
2292 dbg_info *dbgi = get_irn_dbg_info(node);
2293 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2294 ir_node *nomem = new_NoMem();
2295 ir_node *fild, *store;
2298 /* first convert to 32 bit if necessary */
2299 src_bits = get_mode_size_bits(src_mode);
2300 if (src_bits == 8) {
2301 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2302 set_ia32_am_support(new_op, ia32_am_Source);
2303 set_ia32_ls_mode(new_op, src_mode);
2304 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2305 } else if (src_bits < 32) {
2306 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2307 set_ia32_am_support(new_op, ia32_am_Source);
2308 set_ia32_ls_mode(new_op, src_mode);
2309 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2313 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2315 set_ia32_use_frame(store);
2316 set_ia32_am_support(store, ia32_am_Dest);
2317 set_ia32_op_type(store, ia32_AddrModeD);
2318 set_ia32_am_flavour(store, ia32_am_OB);
2319 set_ia32_ls_mode(store, mode_Iu);
2322 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2324 set_ia32_use_frame(fild);
2325 set_ia32_am_support(fild, ia32_am_Source);
2326 set_ia32_op_type(fild, ia32_AddrModeS);
2327 set_ia32_am_flavour(fild, ia32_am_OB);
2328 set_ia32_ls_mode(fild, mode_Iu);
2330 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2334 * Transforms a Conv node.
2336 * @param env The transformation environment
2337 * @return The created ia32 Conv node
2339 static ir_node *gen_Conv(ir_node *node) {
2340 ir_node *block = be_transform_node(get_nodes_block(node));
2341 ir_node *op = get_Conv_op(node);
2342 ir_node *new_op = be_transform_node(op);
2343 ir_graph *irg = current_ir_graph;
2344 dbg_info *dbgi = get_irn_dbg_info(node);
2345 ir_mode *src_mode = get_irn_mode(op);
2346 ir_mode *tgt_mode = get_irn_mode(node);
2347 int src_bits = get_mode_size_bits(src_mode);
2348 int tgt_bits = get_mode_size_bits(tgt_mode);
2349 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2350 ir_node *nomem = new_rd_NoMem(irg);
2353 if (src_mode == tgt_mode) {
2354 if (get_Conv_strict(node)) {
2355 if (USE_SSE2(env_cg)) {
2356 /* when we are in SSE mode, we can kill all strict no-op conversion */
2360 /* this should be optimized already, but who knows... */
2361 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2362 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2367 if (mode_is_float(src_mode)) {
2368 /* we convert from float ... */
2369 if (mode_is_float(tgt_mode)) {
2370 if(src_mode == mode_E && tgt_mode == mode_D
2371 && !get_Conv_strict(node)) {
2372 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2377 if (USE_SSE2(env_cg)) {
2378 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2379 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2380 set_ia32_ls_mode(res, tgt_mode);
2382 // Matze: TODO what about strict convs?
2383 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2384 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2389 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2390 if (USE_SSE2(env_cg)) {
2391 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2392 set_ia32_ls_mode(res, src_mode);
2394 return gen_x87_fp_to_gp(node);
2398 /* we convert from int ... */
2399 if (mode_is_float(tgt_mode)) {
2402 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2403 if (USE_SSE2(env_cg)) {
2404 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2405 set_ia32_ls_mode(res, tgt_mode);
2406 if(src_bits == 32) {
2407 set_ia32_am_support(res, ia32_am_Source);
2410 return gen_x87_gp_to_fp(node, src_mode);
2414 ir_mode *smaller_mode;
2417 if (src_bits == tgt_bits) {
2418 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2422 if (src_bits < tgt_bits) {
2423 smaller_mode = src_mode;
2424 smaller_bits = src_bits;
2426 smaller_mode = tgt_mode;
2427 smaller_bits = tgt_bits;
2430 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2431 if (smaller_bits == 8) {
2432 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2433 set_ia32_ls_mode(res, smaller_mode);
2435 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2436 set_ia32_ls_mode(res, smaller_mode);
2438 set_ia32_am_support(res, ia32_am_Source);
2442 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2448 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2452 assert(tarval_is_long(tv));
2453 val = get_tarval_long(tv);
2455 switch (immediate_constraint_type) {
2459 return val >= 0 && val <= 32;
2461 return val >= 0 && val <= 63;
2463 return val >= -128 && val <= 127;
2465 return val == 0xff || val == 0xffff;
2467 return val >= 0 && val <= 3;
2469 return val >= 0 && val <= 255;
2471 return val >= 0 && val <= 127;
2475 panic("Invalid immediate constraint found");
2480 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2483 tarval *offset = NULL;
2484 int offset_sign = 0;
2485 ir_entity *symconst_ent = NULL;
2486 int symconst_sign = 0;
2488 ir_node *cnst = NULL;
2489 ir_node *symconst = NULL;
2495 mode = get_irn_mode(node);
2496 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2497 !mode_is_reference(mode)) {
2501 if(is_Minus(node)) {
2503 node = get_Minus_op(node);
2506 if(is_Const(node)) {
2509 offset_sign = minus;
2510 } else if(is_SymConst(node)) {
2513 symconst_sign = minus;
2514 } else if(is_Add(node)) {
2515 ir_node *left = get_Add_left(node);
2516 ir_node *right = get_Add_right(node);
2517 if(is_Const(left) && is_SymConst(right)) {
2520 symconst_sign = minus;
2521 offset_sign = minus;
2522 } else if(is_SymConst(left) && is_Const(right)) {
2525 symconst_sign = minus;
2526 offset_sign = minus;
2528 } else if(is_Sub(node)) {
2529 ir_node *left = get_Sub_left(node);
2530 ir_node *right = get_Sub_right(node);
2531 if(is_Const(left) && is_SymConst(right)) {
2534 symconst_sign = !minus;
2535 offset_sign = minus;
2536 } else if(is_SymConst(left) && is_Const(right)) {
2539 symconst_sign = minus;
2540 offset_sign = !minus;
2547 offset = get_Const_tarval(cnst);
2548 if(!tarval_is_long(offset)) {
2549 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2554 if(!check_immediate_constraint(offset, immediate_constraint_type))
2557 if(symconst != NULL) {
2558 if(immediate_constraint_type != 0) {
2559 /* we need full 32bits for symconsts */
2563 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2565 symconst_ent = get_SymConst_entity(symconst);
2567 if(cnst == NULL && symconst == NULL)
2570 if(offset_sign && offset != NULL) {
2571 offset = tarval_neg(offset);
2574 irg = current_ir_graph;
2575 dbgi = get_irn_dbg_info(node);
2576 block = get_irg_start_block(irg);
2577 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2579 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2581 /* make sure we don't schedule stuff before the barrier */
2582 add_irn_dep(res, get_irg_frame(irg));
2587 typedef struct constraint_t constraint_t;
2588 struct constraint_t {
2591 const arch_register_req_t **out_reqs;
2593 const arch_register_req_t *req;
2594 unsigned immediate_possible;
2595 char immediate_type;
2598 void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint,
2601 int immediate_possible = 0;
2602 char immediate_type = 0;
2603 unsigned limited = 0;
2604 const arch_register_class_t *cls = NULL;
2606 struct obstack *obst;
2607 arch_register_req_t *req;
2608 unsigned *limited_ptr;
2612 /* TODO: replace all the asserts with nice error messages */
2614 printf("Constraint: %s\n", c);
2624 assert(cls == NULL ||
2625 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2626 cls = &ia32_reg_classes[CLASS_ia32_gp];
2627 limited |= 1 << REG_EAX;
2630 assert(cls == NULL ||
2631 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2632 cls = &ia32_reg_classes[CLASS_ia32_gp];
2633 limited |= 1 << REG_EBX;
2636 assert(cls == NULL ||
2637 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2638 cls = &ia32_reg_classes[CLASS_ia32_gp];
2639 limited |= 1 << REG_ECX;
2642 assert(cls == NULL ||
2643 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2644 cls = &ia32_reg_classes[CLASS_ia32_gp];
2645 limited |= 1 << REG_EDX;
2648 assert(cls == NULL ||
2649 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2650 cls = &ia32_reg_classes[CLASS_ia32_gp];
2651 limited |= 1 << REG_EDI;
2654 assert(cls == NULL ||
2655 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2656 cls = &ia32_reg_classes[CLASS_ia32_gp];
2657 limited |= 1 << REG_ESI;
2660 case 'q': /* q means lower part of the regs only, this makes no
2661 * difference to Q for us (we only assigne whole registers) */
2662 assert(cls == NULL ||
2663 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2664 cls = &ia32_reg_classes[CLASS_ia32_gp];
2665 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2669 assert(cls == NULL ||
2670 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2671 cls = &ia32_reg_classes[CLASS_ia32_gp];
2672 limited |= 1 << REG_EAX | 1 << REG_EDX;
2675 assert(cls == NULL ||
2676 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2677 cls = &ia32_reg_classes[CLASS_ia32_gp];
2678 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2679 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2686 assert(cls == NULL);
2687 cls = &ia32_reg_classes[CLASS_ia32_gp];
2693 /* TODO: mark values so the x87 simulator knows about t and u */
2694 assert(cls == NULL);
2695 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2700 assert(cls == NULL);
2701 /* TODO: check that sse2 is supported */
2702 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2712 assert(!immediate_possible);
2713 immediate_possible = 1;
2714 immediate_type = *c;
2718 assert(!immediate_possible);
2719 immediate_possible = 1;
2723 assert(!immediate_possible && cls == NULL);
2724 immediate_possible = 1;
2725 cls = &ia32_reg_classes[CLASS_ia32_gp];
2738 assert(constraint->is_in && "can only specify same constraint "
2741 sscanf(c, "%d%n", &same_as, &p);
2748 case 'E': /* no float consts yet */
2749 case 'F': /* no float consts yet */
2750 case 's': /* makes no sense on x86 */
2751 case 'X': /* we can't support that in firm */
2755 case '<': /* no autodecrement on x86 */
2756 case '>': /* no autoincrement on x86 */
2757 case 'C': /* sse constant not supported yet */
2758 case 'G': /* 80387 constant not supported yet */
2759 case 'y': /* we don't support mmx registers yet */
2760 case 'Z': /* not available in 32 bit mode */
2761 case 'e': /* not available in 32 bit mode */
2762 assert(0 && "asm constraint not supported");
2765 assert(0 && "unknown asm constraint found");
2772 const arch_register_req_t *other_constr;
2774 assert(cls == NULL && "same as and register constraint not supported");
2775 assert(!immediate_possible && "same as and immediate constraint not "
2777 assert(same_as < constraint->n_outs && "wrong constraint number in "
2778 "same_as constraint");
2780 other_constr = constraint->out_reqs[same_as];
2782 req = obstack_alloc(obst, sizeof(req[0]));
2783 req->cls = other_constr->cls;
2784 req->type = arch_register_req_type_should_be_same;
2785 req->limited = NULL;
2786 req->other_same = pos;
2787 req->other_different = -1;
2789 /* switch constraints. This is because in firm we have same_as
2790 * constraints on the output constraints while in the gcc asm syntax
2791 * they are specified on the input constraints */
2792 constraint->req = other_constr;
2793 constraint->out_reqs[same_as] = req;
2794 constraint->immediate_possible = 0;
2798 if(immediate_possible && cls == NULL) {
2799 cls = &ia32_reg_classes[CLASS_ia32_gp];
2801 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2802 assert(cls != NULL);
2804 if(immediate_possible) {
2805 assert(constraint->is_in
2806 && "imeediates make no sense for output constraints");
2808 /* todo: check types (no float input on 'r' constrainted in and such... */
2810 irg = current_ir_graph;
2811 obst = get_irg_obstack(irg);
2814 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2815 limited_ptr = (unsigned*) (req+1);
2817 req = obstack_alloc(obst, sizeof(req[0]));
2819 memset(req, 0, sizeof(req[0]));
2822 req->type = arch_register_req_type_limited;
2823 *limited_ptr = limited;
2824 req->limited = limited_ptr;
2826 req->type = arch_register_req_type_normal;
2830 constraint->req = req;
2831 constraint->immediate_possible = immediate_possible;
2832 constraint->immediate_type = immediate_type;
2836 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2839 panic("Clobbers not supported yet");
2842 ir_node *gen_ASM(ir_node *node)
2845 ir_graph *irg = current_ir_graph;
2846 ir_node *block = be_transform_node(get_nodes_block(node));
2847 dbg_info *dbgi = get_irn_dbg_info(node);
2854 ia32_asm_attr_t *attr;
2855 const arch_register_req_t **out_reqs;
2856 const arch_register_req_t **in_reqs;
2857 struct obstack *obst;
2858 constraint_t parsed_constraint;
2860 /* assembler could contain float statements */
2863 /* transform inputs */
2864 arity = get_irn_arity(node);
2865 in = alloca(arity * sizeof(in[0]));
2866 memset(in, 0, arity * sizeof(in[0]));
2868 n_outs = get_ASM_n_output_constraints(node);
2869 n_clobbers = get_ASM_n_clobbers(node);
2870 out_arity = n_outs + n_clobbers;
2872 /* construct register constraints */
2873 obst = get_irg_obstack(irg);
2874 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2875 parsed_constraint.out_reqs = out_reqs;
2876 parsed_constraint.n_outs = n_outs;
2877 parsed_constraint.is_in = 0;
2878 for(i = 0; i < out_arity; ++i) {
2882 const ir_asm_constraint *constraint;
2883 constraint = & get_ASM_output_constraints(node) [i];
2884 c = get_id_str(constraint->constraint);
2885 parse_asm_constraint(node, i, &parsed_constraint, c);
2887 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2888 c = get_id_str(glob_id);
2889 parse_clobber(node, i, &parsed_constraint, c);
2891 out_reqs[i] = parsed_constraint.req;
2894 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2895 parsed_constraint.is_in = 1;
2896 for(i = 0; i < arity; ++i) {
2897 const ir_asm_constraint *constraint;
2901 constraint = & get_ASM_input_constraints(node) [i];
2902 constr_id = constraint->constraint;
2903 c = get_id_str(constr_id);
2904 parse_asm_constraint(node, i, &parsed_constraint, c);
2905 in_reqs[i] = parsed_constraint.req;
2907 if(parsed_constraint.immediate_possible) {
2908 ir_node *pred = get_irn_n(node, i);
2909 char imm_type = parsed_constraint.immediate_type;
2910 ir_node *immediate = try_create_Immediate(pred, imm_type);
2912 if(immediate != NULL) {
2918 /* transform inputs */
2919 for(i = 0; i < arity; ++i) {
2921 ir_node *transformed;
2926 pred = get_irn_n(node, i);
2927 transformed = be_transform_node(pred);
2928 in[i] = transformed;
2931 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2933 generic_attr = get_irn_generic_attr(res);
2934 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2935 attr->asm_text = get_ASM_text(node);
2936 set_ia32_out_req_all(res, out_reqs);
2937 set_ia32_in_req_all(res, in_reqs);
2939 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2944 /********************************************
2947 * | |__ ___ _ __ ___ __| | ___ ___
2948 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2949 * | |_) | __/ | | | (_) | (_| | __/\__ \
2950 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2952 ********************************************/
2954 static ir_node *gen_be_StackParam(ir_node *node) {
2955 ir_node *block = be_transform_node(get_nodes_block(node));
2956 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2957 ir_node *new_ptr = be_transform_node(ptr);
2958 ir_node *new_op = NULL;
2959 ir_graph *irg = current_ir_graph;
2960 dbg_info *dbgi = get_irn_dbg_info(node);
2961 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2962 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2963 ir_mode *load_mode = get_irn_mode(node);
2964 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2968 if (mode_is_float(load_mode)) {
2970 if (USE_SSE2(env_cg)) {
2971 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2972 pn_res = pn_ia32_xLoad_res;
2973 proj_mode = mode_xmm;
2975 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2976 pn_res = pn_ia32_vfld_res;
2977 proj_mode = mode_vfp;
2980 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2981 proj_mode = mode_Iu;
2982 pn_res = pn_ia32_Load_res;
2985 set_irn_pinned(new_op, op_pin_state_floats);
2986 set_ia32_frame_ent(new_op, ent);
2987 set_ia32_use_frame(new_op);
2989 set_ia32_am_support(new_op, ia32_am_Source);
2990 set_ia32_op_type(new_op, ia32_AddrModeS);
2991 set_ia32_am_flavour(new_op, ia32_am_B);
2992 set_ia32_ls_mode(new_op, load_mode);
2993 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2995 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2997 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
3001 * Transforms a FrameAddr into an ia32 Add.
3003 static ir_node *gen_be_FrameAddr(ir_node *node) {
3004 ir_node *block = be_transform_node(get_nodes_block(node));
3005 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
3006 ir_node *new_op = be_transform_node(op);
3007 ir_graph *irg = current_ir_graph;
3008 dbg_info *dbgi = get_irn_dbg_info(node);
3009 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3012 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3013 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3014 set_ia32_am_support(res, ia32_am_Full);
3015 set_ia32_use_frame(res);
3016 set_ia32_am_flavour(res, ia32_am_OB);
3018 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3024 * Transforms a FrameLoad into an ia32 Load.
3026 static ir_node *gen_be_FrameLoad(ir_node *node) {
3027 ir_node *block = be_transform_node(get_nodes_block(node));
3028 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
3029 ir_node *new_mem = be_transform_node(mem);
3030 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
3031 ir_node *new_ptr = be_transform_node(ptr);
3032 ir_node *new_op = NULL;
3033 ir_graph *irg = current_ir_graph;
3034 dbg_info *dbgi = get_irn_dbg_info(node);
3035 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3036 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3037 ir_mode *mode = get_type_mode(get_entity_type(ent));
3038 ir_node *projs[pn_Load_max];
3040 ia32_collect_Projs(node, projs, pn_Load_max);
3042 if (mode_is_float(mode)) {
3044 if (USE_SSE2(env_cg)) {
3045 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
3048 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3052 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
3055 set_irn_pinned(new_op, op_pin_state_floats);
3056 set_ia32_frame_ent(new_op, ent);
3057 set_ia32_use_frame(new_op);
3059 set_ia32_am_support(new_op, ia32_am_Source);
3060 set_ia32_op_type(new_op, ia32_AddrModeS);
3061 set_ia32_am_flavour(new_op, ia32_am_B);
3062 set_ia32_ls_mode(new_op, mode);
3064 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3071 * Transforms a FrameStore into an ia32 Store.
3073 static ir_node *gen_be_FrameStore(ir_node *node) {
3074 ir_node *block = be_transform_node(get_nodes_block(node));
3075 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
3076 ir_node *new_mem = be_transform_node(mem);
3077 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
3078 ir_node *new_ptr = be_transform_node(ptr);
3079 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3080 ir_node *new_val = be_transform_node(val);
3081 ir_node *new_op = NULL;
3082 ir_graph *irg = current_ir_graph;
3083 dbg_info *dbgi = get_irn_dbg_info(node);
3084 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3085 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
3086 ir_mode *mode = get_irn_mode(val);
3088 if (mode_is_float(mode)) {
3090 if (USE_SSE2(env_cg)) {
3091 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3093 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3095 } else if (get_mode_size_bits(mode) == 8) {
3096 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3098 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3101 set_ia32_frame_ent(new_op, ent);
3102 set_ia32_use_frame(new_op);
3104 set_ia32_am_support(new_op, ia32_am_Dest);
3105 set_ia32_op_type(new_op, ia32_AddrModeD);
3106 set_ia32_am_flavour(new_op, ia32_am_B);
3107 set_ia32_ls_mode(new_op, mode);
3109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3115 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3117 static ir_node *gen_be_Return(ir_node *node) {
3118 ir_graph *irg = current_ir_graph;
3119 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3120 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3121 ir_entity *ent = get_irg_entity(irg);
3122 ir_type *tp = get_entity_type(ent);
3127 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3128 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3131 int pn_ret_val, pn_ret_mem, arity, i;
3133 assert(ret_val != NULL);
3134 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3135 return be_duplicate_node(node);
3138 res_type = get_method_res_type(tp, 0);
3140 if (! is_Primitive_type(res_type)) {
3141 return be_duplicate_node(node);
3144 mode = get_type_mode(res_type);
3145 if (! mode_is_float(mode)) {
3146 return be_duplicate_node(node);
3149 assert(get_method_n_ress(tp) == 1);
3151 pn_ret_val = get_Proj_proj(ret_val);
3152 pn_ret_mem = get_Proj_proj(ret_mem);
3154 /* get the Barrier */
3155 barrier = get_Proj_pred(ret_val);
3157 /* get result input of the Barrier */
3158 ret_val = get_irn_n(barrier, pn_ret_val);
3159 new_ret_val = be_transform_node(ret_val);
3161 /* get memory input of the Barrier */
3162 ret_mem = get_irn_n(barrier, pn_ret_mem);
3163 new_ret_mem = be_transform_node(ret_mem);
3165 frame = get_irg_frame(irg);
3167 dbgi = get_irn_dbg_info(barrier);
3168 block = be_transform_node(get_nodes_block(barrier));
3170 noreg = ia32_new_NoReg_gp(env_cg);
3172 /* store xmm0 onto stack */
3173 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3174 set_ia32_ls_mode(sse_store, mode);
3175 set_ia32_op_type(sse_store, ia32_AddrModeD);
3176 set_ia32_use_frame(sse_store);
3177 set_ia32_am_flavour(sse_store, ia32_am_B);
3178 set_ia32_am_support(sse_store, ia32_am_Dest);
3181 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3182 set_ia32_ls_mode(fld, mode);
3183 set_ia32_op_type(fld, ia32_AddrModeS);
3184 set_ia32_use_frame(fld);
3185 set_ia32_am_flavour(fld, ia32_am_B);
3186 set_ia32_am_support(fld, ia32_am_Source);
3188 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3189 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3190 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3192 /* create a new barrier */
3193 arity = get_irn_arity(barrier);
3194 in = alloca(arity * sizeof(in[0]));
3195 for (i = 0; i < arity; ++i) {
3198 if (i == pn_ret_val) {
3200 } else if (i == pn_ret_mem) {
3203 ir_node *in = get_irn_n(barrier, i);
3204 new_in = be_transform_node(in);
3209 new_barrier = new_ir_node(dbgi, irg, block,
3210 get_irn_op(barrier), get_irn_mode(barrier),
3212 copy_node_attr(barrier, new_barrier);
3213 be_duplicate_deps(barrier, new_barrier);
3214 be_set_transformed_node(barrier, new_barrier);
3215 mark_irn_visited(barrier);
3217 /* transform normally */
3218 return be_duplicate_node(node);
3222 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3224 static ir_node *gen_be_AddSP(ir_node *node) {
3225 ir_node *block = be_transform_node(get_nodes_block(node));
3226 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3227 ir_node *new_sz = be_transform_node(sz);
3228 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3229 ir_node *new_sp = be_transform_node(sp);
3230 ir_graph *irg = current_ir_graph;
3231 dbg_info *dbgi = get_irn_dbg_info(node);
3232 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3233 ir_node *nomem = new_NoMem();
3236 /* ia32 stack grows in reverse direction, make a SubSP */
3237 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3238 set_ia32_am_support(new_op, ia32_am_Source);
3239 fold_immediate(new_op, 2, 3);
3241 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3247 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3249 static ir_node *gen_be_SubSP(ir_node *node) {
3250 ir_node *block = be_transform_node(get_nodes_block(node));
3251 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3252 ir_node *new_sz = be_transform_node(sz);
3253 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3254 ir_node *new_sp = be_transform_node(sp);
3255 ir_graph *irg = current_ir_graph;
3256 dbg_info *dbgi = get_irn_dbg_info(node);
3257 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3258 ir_node *nomem = new_NoMem();
3261 /* ia32 stack grows in reverse direction, make an AddSP */
3262 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3263 set_ia32_am_support(new_op, ia32_am_Source);
3264 fold_immediate(new_op, 2, 3);
3266 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3272 * This function just sets the register for the Unknown node
3273 * as this is not done during register allocation because Unknown
3274 * is an "ignore" node.
3276 static ir_node *gen_Unknown(ir_node *node) {
3277 ir_mode *mode = get_irn_mode(node);
3279 if (mode_is_float(mode)) {
3280 if (USE_SSE2(env_cg))
3281 return ia32_new_Unknown_xmm(env_cg);
3283 return ia32_new_Unknown_vfp(env_cg);
3284 } else if (mode_needs_gp_reg(mode)) {
3285 return ia32_new_Unknown_gp(env_cg);
3287 assert(0 && "unsupported Unknown-Mode");
3294 * Change some phi modes
3296 static ir_node *gen_Phi(ir_node *node) {
3297 ir_node *block = be_transform_node(get_nodes_block(node));
3298 ir_graph *irg = current_ir_graph;
3299 dbg_info *dbgi = get_irn_dbg_info(node);
3300 ir_mode *mode = get_irn_mode(node);
3303 if(mode_needs_gp_reg(mode)) {
3304 /* we shouldn't have any 64bit stuff around anymore */
3305 assert(get_mode_size_bits(mode) <= 32);
3306 /* all integer operations are on 32bit registers now */
3308 } else if(mode_is_float(mode)) {
3309 assert(mode == mode_D || mode == mode_F);
3310 if (USE_SSE2(env_cg)) {
3317 /* phi nodes allow loops, so we use the old arguments for now
3318 * and fix this later */
3319 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3320 copy_node_attr(node, phi);
3321 be_duplicate_deps(node, phi);
3323 be_set_transformed_node(node, phi);
3324 be_enqueue_preds(node);
3329 /**********************************************************************
3332 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3333 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3334 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3335 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3337 **********************************************************************/
3339 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3341 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3344 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3345 ir_node *val, ir_node *mem);
3348 * Transforms a lowered Load into a "real" one.
3350 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3351 ir_node *block = be_transform_node(get_nodes_block(node));
3352 ir_node *ptr = get_irn_n(node, 0);
3353 ir_node *new_ptr = be_transform_node(ptr);
3354 ir_node *mem = get_irn_n(node, 1);
3355 ir_node *new_mem = be_transform_node(mem);
3356 ir_graph *irg = current_ir_graph;
3357 dbg_info *dbgi = get_irn_dbg_info(node);
3358 ir_mode *mode = get_ia32_ls_mode(node);
3359 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3363 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3364 lowering we have x87 nodes, so we need to enforce simulation.
3366 if (mode_is_float(mode)) {
3368 if (fp_unit == fp_x87)
3372 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3374 set_ia32_am_support(new_op, ia32_am_Source);
3375 set_ia32_op_type(new_op, ia32_AddrModeS);
3376 set_ia32_am_flavour(new_op, ia32_am_OB);
3377 set_ia32_am_offs_int(new_op, 0);
3378 set_ia32_am_scale(new_op, 1);
3379 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3380 if (is_ia32_am_sc_sign(node))
3381 set_ia32_am_sc_sign(new_op);
3382 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3383 if (is_ia32_use_frame(node)) {
3384 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3385 set_ia32_use_frame(new_op);
3388 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3394 * Transforms a lowered Store into a "real" one.
3396 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3397 ir_node *block = be_transform_node(get_nodes_block(node));
3398 ir_node *ptr = get_irn_n(node, 0);
3399 ir_node *new_ptr = be_transform_node(ptr);
3400 ir_node *val = get_irn_n(node, 1);
3401 ir_node *new_val = be_transform_node(val);
3402 ir_node *mem = get_irn_n(node, 2);
3403 ir_node *new_mem = be_transform_node(mem);
3404 ir_graph *irg = current_ir_graph;
3405 dbg_info *dbgi = get_irn_dbg_info(node);
3406 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3407 ir_mode *mode = get_ia32_ls_mode(node);
3410 ia32_am_flavour_t am_flav = ia32_B;
3413 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3414 lowering we have x87 nodes, so we need to enforce simulation.
3416 if (mode_is_float(mode)) {
3418 if (fp_unit == fp_x87)
3422 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3424 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3426 add_ia32_am_offs_int(new_op, am_offs);
3429 set_ia32_am_support(new_op, ia32_am_Dest);
3430 set_ia32_op_type(new_op, ia32_AddrModeD);
3431 set_ia32_am_flavour(new_op, am_flav);
3432 set_ia32_ls_mode(new_op, mode);
3433 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3434 set_ia32_use_frame(new_op);
3436 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3443 * Transforms an ia32_l_XXX into a "real" XXX node
3445 * @param env The transformation environment
3446 * @return the created ia32 XXX node
3448 #define GEN_LOWERED_OP(op) \
3449 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3450 ir_mode *mode = get_irn_mode(node); \
3451 if (mode_is_float(mode)) \
3453 return gen_binop(node, get_binop_left(node), \
3454 get_binop_right(node), new_rd_ia32_##op,0); \
3457 #define GEN_LOWERED_x87_OP(op) \
3458 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3460 FORCE_x87(env_cg); \
3461 new_op = gen_binop_float(node, get_binop_left(node), \
3462 get_binop_right(node), new_rd_ia32_##op); \
3466 #define GEN_LOWERED_UNOP(op) \
3467 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3468 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3471 #define GEN_LOWERED_SHIFT_OP(op) \
3472 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3473 return gen_shift_binop(node, get_binop_left(node), \
3474 get_binop_right(node), new_rd_ia32_##op); \
3477 #define GEN_LOWERED_LOAD(op, fp_unit) \
3478 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3479 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3482 #define GEN_LOWERED_STORE(op, fp_unit) \
3483 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3484 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3491 GEN_LOWERED_OP(IMul)
3493 GEN_LOWERED_x87_OP(vfprem)
3494 GEN_LOWERED_x87_OP(vfmul)
3495 GEN_LOWERED_x87_OP(vfsub)
3497 GEN_LOWERED_UNOP(Neg)
3499 GEN_LOWERED_LOAD(vfild, fp_x87)
3500 GEN_LOWERED_LOAD(Load, fp_none)
3501 /*GEN_LOWERED_STORE(vfist, fp_x87)
3504 GEN_LOWERED_STORE(Store, fp_none)
3506 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3507 ir_node *block = be_transform_node(get_nodes_block(node));
3508 ir_node *left = get_binop_left(node);
3509 ir_node *new_left = be_transform_node(left);
3510 ir_node *right = get_binop_right(node);
3511 ir_node *new_right = be_transform_node(right);
3512 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3513 ir_graph *irg = current_ir_graph;
3514 dbg_info *dbgi = get_irn_dbg_info(node);
3517 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3518 clear_ia32_commutative(vfdiv);
3519 set_ia32_am_support(vfdiv, ia32_am_Source);
3520 fold_immediate(vfdiv, 2, 3);
3522 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3530 * Transforms a l_MulS into a "real" MulS node.
3532 * @param env The transformation environment
3533 * @return the created ia32 Mul node
3535 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3536 ir_node *block = be_transform_node(get_nodes_block(node));
3537 ir_node *left = get_binop_left(node);
3538 ir_node *new_left = be_transform_node(left);
3539 ir_node *right = get_binop_right(node);
3540 ir_node *new_right = be_transform_node(right);
3541 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3542 ir_graph *irg = current_ir_graph;
3543 dbg_info *dbgi = get_irn_dbg_info(node);
3546 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3547 /* and then skip the result Proj, because all needed Projs are already there. */
3548 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3549 clear_ia32_commutative(muls);
3550 set_ia32_am_support(muls, ia32_am_Source);
3551 fold_immediate(muls, 2, 3);
3553 /* check if EAX and EDX proj exist, add missing one */
3554 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3555 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3556 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3558 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3563 GEN_LOWERED_SHIFT_OP(Shl)
3564 GEN_LOWERED_SHIFT_OP(Shr)
3565 GEN_LOWERED_SHIFT_OP(Sar)
3568 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3569 * op1 - target to be shifted
3570 * op2 - contains bits to be shifted into target
3572 * Only op3 can be an immediate.
3574 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3575 ir_node *op2, ir_node *count)
3577 ir_node *block = be_transform_node(get_nodes_block(node));
3578 ir_node *new_op1 = be_transform_node(op1);
3579 ir_node *new_op2 = be_transform_node(op2);
3580 ir_node *new_count = be_transform_node(count);
3581 ir_node *new_op = NULL;
3582 ir_graph *irg = current_ir_graph;
3583 dbg_info *dbgi = get_irn_dbg_info(node);
3584 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3585 ir_node *nomem = new_NoMem();
3589 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3591 /* Check if immediate optimization is on and */
3592 /* if it's an operation with immediate. */
3593 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3595 /* Limit imm_op within range imm8 */
3597 tv = get_ia32_Immop_tarval(imm_op);
3600 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3601 set_ia32_Immop_tarval(imm_op, tv);
3608 /* integer operations */
3610 /* This is ShiftD with const */
3611 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3613 if (is_ia32_l_ShlD(node))
3614 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3615 new_op1, new_op2, noreg, nomem);
3617 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3618 new_op1, new_op2, noreg, nomem);
3619 copy_ia32_Immop_attr(new_op, imm_op);
3622 /* This is a normal ShiftD */
3623 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3624 if (is_ia32_l_ShlD(node))
3625 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3626 new_op1, new_op2, new_count, nomem);
3628 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3629 new_op1, new_op2, new_count, nomem);
3632 /* set AM support */
3633 // Matze: node has unsupported format (6inputs)
3634 //set_ia32_am_support(new_op, ia32_am_Dest);
3636 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3638 set_ia32_emit_cl(new_op);
3643 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3644 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3645 get_irn_n(node, 1), get_irn_n(node, 2));
3648 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3649 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3650 get_irn_n(node, 1), get_irn_n(node, 2));
3654 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3656 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3657 ir_node *block = be_transform_node(get_nodes_block(node));
3658 ir_node *val = get_irn_n(node, 1);
3659 ir_node *new_val = be_transform_node(val);
3660 ia32_code_gen_t *cg = env_cg;
3661 ir_node *res = NULL;
3662 ir_graph *irg = current_ir_graph;
3664 ir_node *noreg, *new_ptr, *new_mem;
3671 mem = get_irn_n(node, 2);
3672 new_mem = be_transform_node(mem);
3673 ptr = get_irn_n(node, 0);
3674 new_ptr = be_transform_node(ptr);
3675 noreg = ia32_new_NoReg_gp(cg);
3676 dbgi = get_irn_dbg_info(node);
3678 /* Store x87 -> MEM */
3679 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3680 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3681 set_ia32_use_frame(res);
3682 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3683 set_ia32_am_support(res, ia32_am_Dest);
3684 set_ia32_am_flavour(res, ia32_B);
3685 set_ia32_op_type(res, ia32_AddrModeD);
3687 /* Load MEM -> SSE */
3688 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3689 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3690 set_ia32_use_frame(res);
3691 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3692 set_ia32_am_support(res, ia32_am_Source);
3693 set_ia32_am_flavour(res, ia32_B);
3694 set_ia32_op_type(res, ia32_AddrModeS);
3695 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3701 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3703 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3704 ir_node *block = be_transform_node(get_nodes_block(node));
3705 ir_node *val = get_irn_n(node, 1);
3706 ir_node *new_val = be_transform_node(val);
3707 ia32_code_gen_t *cg = env_cg;
3708 ir_graph *irg = current_ir_graph;
3709 ir_node *res = NULL;
3710 ir_entity *fent = get_ia32_frame_ent(node);
3711 ir_mode *lsmode = get_ia32_ls_mode(node);
3713 ir_node *noreg, *new_ptr, *new_mem;
3717 if (! USE_SSE2(cg)) {
3718 /* SSE unit is not used -> skip this node. */
3722 ptr = get_irn_n(node, 0);
3723 new_ptr = be_transform_node(ptr);
3724 mem = get_irn_n(node, 2);
3725 new_mem = be_transform_node(mem);
3726 noreg = ia32_new_NoReg_gp(cg);
3727 dbgi = get_irn_dbg_info(node);
3729 /* Store SSE -> MEM */
3730 if (is_ia32_xLoad(skip_Proj(new_val))) {
3731 ir_node *ld = skip_Proj(new_val);
3733 /* we can vfld the value directly into the fpu */
3734 fent = get_ia32_frame_ent(ld);
3735 ptr = get_irn_n(ld, 0);
3736 offs = get_ia32_am_offs_int(ld);
3738 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3739 set_ia32_frame_ent(res, fent);
3740 set_ia32_use_frame(res);
3741 set_ia32_ls_mode(res, lsmode);
3742 set_ia32_am_support(res, ia32_am_Dest);
3743 set_ia32_am_flavour(res, ia32_B);
3744 set_ia32_op_type(res, ia32_AddrModeD);
3748 /* Load MEM -> x87 */
3749 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3750 set_ia32_frame_ent(res, fent);
3751 set_ia32_use_frame(res);
3752 set_ia32_ls_mode(res, lsmode);
3753 add_ia32_am_offs_int(res, offs);
3754 set_ia32_am_support(res, ia32_am_Source);
3755 set_ia32_am_flavour(res, ia32_B);
3756 set_ia32_op_type(res, ia32_AddrModeS);
3757 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3762 /*********************************************************
3765 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3766 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3767 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3768 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3770 *********************************************************/
3773 * the BAD transformer.
3775 static ir_node *bad_transform(ir_node *node) {
3776 panic("No transform function for %+F available.\n", node);
3780 static ir_node *gen_End(ir_node *node) {
3781 /* end has to be duplicated manually because we need a dynamic in array */
3782 ir_graph *irg = current_ir_graph;
3783 dbg_info *dbgi = get_irn_dbg_info(node);
3784 ir_node *block = be_transform_node(get_nodes_block(node));
3788 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3789 copy_node_attr(node, new_end);
3790 be_duplicate_deps(node, new_end);
3792 set_irg_end(irg, new_end);
3793 be_set_transformed_node(new_end, new_end);
3795 /* transform preds */
3796 arity = get_irn_arity(node);
3797 for (i = 0; i < arity; ++i) {
3798 ir_node *in = get_irn_n(node, i);
3799 ir_node *new_in = be_transform_node(in);
3801 add_End_keepalive(new_end, new_in);
3807 static ir_node *gen_Block(ir_node *node) {
3808 ir_graph *irg = current_ir_graph;
3809 dbg_info *dbgi = get_irn_dbg_info(node);
3810 ir_node *start_block = be_get_old_anchor(anchor_start_block);
3814 * We replace the ProjX from the start node with a jump,
3815 * so the startblock has no preds anymore now
3817 if (node == start_block) {
3818 return new_rd_Block(dbgi, irg, 0, NULL);
3821 /* we use the old blocks for now, because jumps allow cycles in the graph
3822 * we have to fix this later */
3823 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3824 get_irn_arity(node), get_irn_in(node) + 1);
3825 copy_node_attr(node, block);
3827 #ifdef DEBUG_libfirm
3828 block->node_nr = node->node_nr;
3830 be_set_transformed_node(node, block);
3832 /* put the preds in the worklist */
3833 be_enqueue_preds(node);
3838 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3839 ir_node *block = be_transform_node(get_nodes_block(node));
3840 ir_node *pred = get_Proj_pred(node);
3841 ir_node *new_pred = be_transform_node(pred);
3842 ir_graph *irg = current_ir_graph;
3843 dbg_info *dbgi = get_irn_dbg_info(node);
3844 long proj = get_Proj_proj(node);
3846 if (proj == pn_be_AddSP_res) {
3847 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3848 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3850 } else if (proj == pn_be_AddSP_M) {
3851 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3855 return new_rd_Unknown(irg, get_irn_mode(node));
3858 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3859 ir_node *block = be_transform_node(get_nodes_block(node));
3860 ir_node *pred = get_Proj_pred(node);
3861 ir_node *new_pred = be_transform_node(pred);
3862 ir_graph *irg = current_ir_graph;
3863 dbg_info *dbgi = get_irn_dbg_info(node);
3864 long proj = get_Proj_proj(node);
3866 if (proj == pn_be_SubSP_res) {
3867 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3868 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3870 } else if (proj == pn_be_SubSP_M) {
3871 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3875 return new_rd_Unknown(irg, get_irn_mode(node));
3878 static ir_node *gen_Proj_Load(ir_node *node) {
3879 ir_node *block = be_transform_node(get_nodes_block(node));
3880 ir_node *pred = get_Proj_pred(node);
3881 ir_node *new_pred = be_transform_node(pred);
3882 ir_graph *irg = current_ir_graph;
3883 dbg_info *dbgi = get_irn_dbg_info(node);
3884 long proj = get_Proj_proj(node);
3886 /* renumber the proj */
3887 if (is_ia32_Load(new_pred)) {
3888 if (proj == pn_Load_res) {
3889 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3890 } else if (proj == pn_Load_M) {
3891 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3893 } else if (is_ia32_xLoad(new_pred)) {
3894 if (proj == pn_Load_res) {
3895 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3896 } else if (proj == pn_Load_M) {
3897 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3899 } else if (is_ia32_vfld(new_pred)) {
3900 if (proj == pn_Load_res) {
3901 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3902 } else if (proj == pn_Load_M) {
3903 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3908 return new_rd_Unknown(irg, get_irn_mode(node));
3911 static ir_node *gen_Proj_DivMod(ir_node *node) {
3912 ir_node *block = be_transform_node(get_nodes_block(node));
3913 ir_node *pred = get_Proj_pred(node);
3914 ir_node *new_pred = be_transform_node(pred);
3915 ir_graph *irg = current_ir_graph;
3916 dbg_info *dbgi = get_irn_dbg_info(node);
3917 ir_mode *mode = get_irn_mode(node);
3918 long proj = get_Proj_proj(node);
3920 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3922 switch (get_irn_opcode(pred)) {
3926 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3928 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3936 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3938 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3946 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3947 case pn_DivMod_res_div:
3948 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3949 case pn_DivMod_res_mod:
3950 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3960 return new_rd_Unknown(irg, mode);
3963 static ir_node *gen_Proj_CopyB(ir_node *node) {
3964 ir_node *block = be_transform_node(get_nodes_block(node));
3965 ir_node *pred = get_Proj_pred(node);
3966 ir_node *new_pred = be_transform_node(pred);
3967 ir_graph *irg = current_ir_graph;
3968 dbg_info *dbgi = get_irn_dbg_info(node);
3969 ir_mode *mode = get_irn_mode(node);
3970 long proj = get_Proj_proj(node);
3973 case pn_CopyB_M_regular:
3974 if (is_ia32_CopyB_i(new_pred)) {
3975 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3976 } else if (is_ia32_CopyB(new_pred)) {
3977 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3985 return new_rd_Unknown(irg, mode);
3988 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3989 ir_node *block = be_transform_node(get_nodes_block(node));
3990 ir_node *pred = get_Proj_pred(node);
3991 ir_node *new_pred = be_transform_node(pred);
3992 ir_graph *irg = current_ir_graph;
3993 dbg_info *dbgi = get_irn_dbg_info(node);
3994 ir_mode *mode = get_irn_mode(node);
3995 long proj = get_Proj_proj(node);
3998 case pn_ia32_l_vfdiv_M:
3999 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4000 case pn_ia32_l_vfdiv_res:
4001 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4006 return new_rd_Unknown(irg, mode);
4009 static ir_node *gen_Proj_Quot(ir_node *node) {
4010 ir_node *block = be_transform_node(get_nodes_block(node));
4011 ir_node *pred = get_Proj_pred(node);
4012 ir_node *new_pred = be_transform_node(pred);
4013 ir_graph *irg = current_ir_graph;
4014 dbg_info *dbgi = get_irn_dbg_info(node);
4015 ir_mode *mode = get_irn_mode(node);
4016 long proj = get_Proj_proj(node);
4020 if (is_ia32_xDiv(new_pred)) {
4021 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4022 } else if (is_ia32_vfdiv(new_pred)) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4027 if (is_ia32_xDiv(new_pred)) {
4028 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4029 } else if (is_ia32_vfdiv(new_pred)) {
4030 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4038 return new_rd_Unknown(irg, mode);
4041 static ir_node *gen_Proj_tls(ir_node *node) {
4042 ir_node *block = be_transform_node(get_nodes_block(node));
4043 ir_graph *irg = current_ir_graph;
4044 dbg_info *dbgi = NULL;
4045 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4050 static ir_node *gen_Proj_be_Call(ir_node *node) {
4051 ir_node *block = be_transform_node(get_nodes_block(node));
4052 ir_node *call = get_Proj_pred(node);
4053 ir_node *new_call = be_transform_node(call);
4054 ir_graph *irg = current_ir_graph;
4055 dbg_info *dbgi = get_irn_dbg_info(node);
4056 long proj = get_Proj_proj(node);
4057 ir_mode *mode = get_irn_mode(node);
4059 const arch_register_class_t *cls;
4061 /* The following is kinda tricky: If we're using SSE, then we have to
4062 * move the result value of the call in floating point registers to an
4063 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4064 * after the call, we have to make sure to correctly make the
4065 * MemProj and the result Proj use these 2 nodes
4067 if (proj == pn_be_Call_M_regular) {
4068 // get new node for result, are we doing the sse load/store hack?
4069 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4070 ir_node *call_res_new;
4071 ir_node *call_res_pred = NULL;
4073 if (call_res != NULL) {
4074 call_res_new = be_transform_node(call_res);
4075 call_res_pred = get_Proj_pred(call_res_new);
4078 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4079 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4081 assert(is_ia32_xLoad(call_res_pred));
4082 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
4085 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
4087 ir_node *frame = get_irg_frame(irg);
4088 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4090 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4092 const arch_register_class_t *cls;
4094 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
4095 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4097 /* store st(0) onto stack */
4098 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
4100 set_ia32_ls_mode(fstp, mode);
4101 set_ia32_op_type(fstp, ia32_AddrModeD);
4102 set_ia32_use_frame(fstp);
4103 set_ia32_am_flavour(fstp, ia32_am_B);
4104 set_ia32_am_support(fstp, ia32_am_Dest);
4106 /* load into SSE register */
4107 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4108 set_ia32_ls_mode(sse_load, mode);
4109 set_ia32_op_type(sse_load, ia32_AddrModeS);
4110 set_ia32_use_frame(sse_load);
4111 set_ia32_am_flavour(sse_load, ia32_am_B);
4112 set_ia32_am_support(sse_load, ia32_am_Source);
4114 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
4116 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4118 /* get a Proj representing a caller save register */
4119 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4120 assert(is_Proj(p) && "Proj expected.");
4122 /* user of the the proj is the Keep */
4123 p = get_edge_src_irn(get_irn_out_edge_first(p));
4124 assert(be_is_Keep(p) && "Keep expected.");
4126 /* keep the result */
4127 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
4128 keepin[0] = sse_load;
4129 be_new_Keep(cls, irg, block, 1, keepin);
4134 /* transform call modes */
4135 if (mode_is_data(mode)) {
4136 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4140 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4143 static ir_node *gen_Proj_Cmp(ir_node *node)
4145 /* normally Cmps are processed when looking at Cond nodes, but this case
4146 * can happen in complicated Psi conditions */
4148 ir_graph *irg = current_ir_graph;
4149 dbg_info *dbgi = get_irn_dbg_info(node);
4150 ir_node *block = be_transform_node(get_nodes_block(node));
4151 ir_node *cmp = get_Proj_pred(node);
4152 long pnc = get_Proj_proj(node);
4153 ir_node *cmp_left = get_Cmp_left(cmp);
4154 ir_node *cmp_right = get_Cmp_right(cmp);
4155 ir_node *new_cmp_left;
4156 ir_node *new_cmp_right;
4157 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4158 ir_node *nomem = new_rd_NoMem(irg);
4159 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4162 assert(!mode_is_float(cmp_mode));
4164 /* (a != b) -> (a ^ b) */
4165 if(pnc == pn_Cmp_Lg) {
4166 if(is_Const_0(cmp_left)) {
4167 new_op = be_transform_node(cmp_right);
4168 } else if(is_Const_0(cmp_right)) {
4169 new_op = be_transform_node(cmp_left);
4171 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4177 * (a == b) -> !(a ^ b)
4178 * (a < 0) -> (a & 0x80000000)
4179 * (a <= 0) -> !(a & 0x7fffffff)
4180 * (a > 0) -> (a & 0x7fffffff)
4181 * (a >= 0) -> !(a & 0x80000000)
4184 if(!mode_is_signed(cmp_mode)) {
4185 pnc |= ia32_pn_Cmp_Unsigned;
4188 new_cmp_right = try_create_Immediate(cmp_right, 0);
4189 if(new_cmp_right == NULL) {
4190 new_cmp_right = try_create_Immediate(cmp_left, 0);
4191 if(new_cmp_left != NULL) {
4192 pnc = get_inversed_pnc(pnc);
4193 new_cmp_left = be_transform_node(cmp_right);
4196 new_cmp_left = be_transform_node(cmp_left);
4198 if(new_cmp_right == NULL) {
4199 new_cmp_left = be_transform_node(cmp_left);
4200 new_cmp_right = be_transform_node(cmp_right);
4203 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4204 new_cmp_right, nomem, pnc);
4205 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4210 static ir_node *gen_Proj(ir_node *node) {
4211 ir_graph *irg = current_ir_graph;
4212 dbg_info *dbgi = get_irn_dbg_info(node);
4213 ir_node *pred = get_Proj_pred(node);
4214 long proj = get_Proj_proj(node);
4216 if (is_Store(pred) || be_is_FrameStore(pred)) {
4217 if (proj == pn_Store_M) {
4218 return be_transform_node(pred);
4221 return new_r_Bad(irg);
4223 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4224 return gen_Proj_Load(node);
4225 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4226 return gen_Proj_DivMod(node);
4227 } else if (is_CopyB(pred)) {
4228 return gen_Proj_CopyB(node);
4229 } else if (is_Quot(pred)) {
4230 return gen_Proj_Quot(node);
4231 } else if (is_ia32_l_vfdiv(pred)) {
4232 return gen_Proj_l_vfdiv(node);
4233 } else if (be_is_SubSP(pred)) {
4234 return gen_Proj_be_SubSP(node);
4235 } else if (be_is_AddSP(pred)) {
4236 return gen_Proj_be_AddSP(node);
4237 } else if (be_is_Call(pred)) {
4238 return gen_Proj_be_Call(node);
4239 } else if (is_Cmp(pred)) {
4240 return gen_Proj_Cmp(node);
4241 } else if (get_irn_op(pred) == op_Start) {
4242 if (proj == pn_Start_X_initial_exec) {
4243 ir_node *block = get_nodes_block(pred);
4246 /* we exchange the ProjX with a jump */
4247 block = be_transform_node(block);
4248 jump = new_rd_Jmp(dbgi, irg, block);
4249 ir_fprintf(stderr, "created jump: %+F\n", jump);
4252 if (node == be_get_old_anchor(anchor_tls)) {
4253 return gen_Proj_tls(node);
4256 ir_node *new_pred = be_transform_node(pred);
4257 ir_node *block = be_transform_node(get_nodes_block(node));
4258 ir_mode *mode = get_irn_mode(node);
4259 if (mode_needs_gp_reg(mode)) {
4260 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4261 get_Proj_proj(node));
4262 #ifdef DEBUG_libfirm
4263 new_proj->node_nr = node->node_nr;
4269 return be_duplicate_node(node);
4273 * Enters all transform functions into the generic pointer
4275 static void register_transformers(void) {
4276 ir_op *op_Max, *op_Min, *op_Mulh;
4278 /* first clear the generic function pointer for all ops */
4279 clear_irp_opcodes_generic_func();
4281 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4282 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4322 /* transform ops from intrinsic lowering */
4342 /* GEN(ia32_l_vfist); TODO */
4344 GEN(ia32_l_X87toSSE);
4345 GEN(ia32_l_SSEtoX87);
4350 /* we should never see these nodes */
4365 /* handle generic backend nodes */
4376 /* set the register for all Unknown nodes */
4379 op_Max = get_op_Max();
4382 op_Min = get_op_Min();
4385 op_Mulh = get_op_Mulh();
4394 * Pre-transform all unknown and noreg nodes.
4396 static void ia32_pretransform_node(void *arch_cg) {
4397 ia32_code_gen_t *cg = arch_cg;
4399 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4400 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4401 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4402 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4403 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4404 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4407 /* do the transformation */
4408 void ia32_transform_graph(ia32_code_gen_t *cg) {
4409 register_transformers();
4411 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4414 void ia32_init_transform(void)
4416 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");