2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
68 #include "ia32_architecture.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define DFP_INTMAX "9223372036854775807"
78 #define TP_SFP_SIGN "ia32_sfp_sign"
79 #define TP_DFP_SIGN "ia32_dfp_sign"
80 #define TP_SFP_ABS "ia32_sfp_abs"
81 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define TP_INT_MAX "ia32_int_max"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
88 #define ENT_INT_MAX "IA32_INT_MAX"
90 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
91 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
95 /** hold the current code generator during transformation */
96 static ia32_code_gen_t *env_cg = NULL;
97 static ir_node *initial_fpcw = NULL;
98 static heights_t *heights = NULL;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 static ir_node *try_create_Immediate(ir_node *node,
128 char immediate_constraint_type);
130 static ir_node *create_immediate_or_transform(ir_node *node,
131 char immediate_constraint_type);
133 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
134 dbg_info *dbgi, ir_node *block,
135 ir_node *op, ir_node *orig_node);
138 * Return true if a mode can be stored in the GP register set
140 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
141 if(mode == mode_fpcw)
143 if(get_mode_size_bits(mode) > 32)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an atomic entity that is initialized with a tarval
186 static ir_entity *create_float_const_entity(ir_node *cnst)
188 ia32_isa_t *isa = env_cg->isa;
189 tarval *tv = get_Const_tarval(cnst);
190 pmap_entry *e = pmap_find(isa->tv_ent, tv);
195 ir_mode *mode = get_irn_mode(cnst);
196 ir_type *tp = get_Const_type(cnst);
197 if (tp == firm_unknown_type)
198 tp = get_prim_type(isa->types, mode);
200 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
202 set_entity_ld_ident(res, get_entity_ident(res));
203 set_entity_visibility(res, visibility_local);
204 set_entity_variability(res, variability_constant);
205 set_entity_allocation(res, allocation_static);
207 /* we create a new entity here: It's initialization must resist on the
209 rem = current_ir_graph;
210 current_ir_graph = get_const_code_irg();
211 set_atomic_ent_value(res, new_Const_type(tv, tp));
212 current_ir_graph = rem;
214 pmap_insert(isa->tv_ent, tv, res);
222 static int is_Const_0(ir_node *node) {
223 return is_Const(node) && is_Const_null(node);
226 static int is_Const_1(ir_node *node) {
227 return is_Const(node) && is_Const_one(node);
230 static int is_Const_Minus_1(ir_node *node) {
231 return is_Const(node) && is_Const_all_one(node);
235 * returns true if constant can be created with a simple float command
237 static int is_simple_x87_Const(ir_node *node)
239 tarval *tv = get_Const_tarval(node);
241 if(tarval_is_null(tv) || tarval_is_one(tv))
244 /* TODO: match all the other float constants */
249 * Transforms a Const.
251 static ir_node *gen_Const(ir_node *node) {
252 ir_graph *irg = current_ir_graph;
253 ir_node *old_block = get_nodes_block(node);
254 ir_node *block = be_transform_node(old_block);
255 dbg_info *dbgi = get_irn_dbg_info(node);
256 ir_mode *mode = get_irn_mode(node);
258 assert(is_Const(node));
260 if (mode_is_float(mode)) {
262 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
263 ir_node *nomem = new_NoMem();
267 if (ia32_cg_config.use_sse2) {
268 if (is_Const_null(node)) {
269 load = new_rd_ia32_xZero(dbgi, irg, block);
270 set_ia32_ls_mode(load, mode);
273 floatent = create_float_const_entity(node);
275 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
277 set_ia32_op_type(load, ia32_AddrModeS);
278 set_ia32_am_sc(load, floatent);
279 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
280 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
283 if (is_Const_null(node)) {
284 load = new_rd_ia32_vfldz(dbgi, irg, block);
286 } else if (is_Const_one(node)) {
287 load = new_rd_ia32_vfld1(dbgi, irg, block);
290 floatent = create_float_const_entity(node);
292 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
293 set_ia32_op_type(load, ia32_AddrModeS);
294 set_ia32_am_sc(load, floatent);
295 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
296 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
298 set_ia32_ls_mode(load, mode);
301 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
303 /* Const Nodes before the initial IncSP are a bad idea, because
304 * they could be spilled and we have no SP ready at that point yet.
305 * So add a dependency to the initial frame pointer calculation to
306 * avoid that situation.
308 if (get_irg_start_block(irg) == block) {
309 add_irn_dep(load, get_irg_frame(irg));
312 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 tarval *tv = get_Const_tarval(node);
319 tv = tarval_convert_to(tv, mode_Iu);
321 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
323 panic("couldn't convert constant tarval (%+F)", node);
325 val = get_tarval_long(tv);
327 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
328 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
340 * Transforms a SymConst.
342 static ir_node *gen_SymConst(ir_node *node) {
343 ir_graph *irg = current_ir_graph;
344 ir_node *old_block = get_nodes_block(node);
345 ir_node *block = be_transform_node(old_block);
346 dbg_info *dbgi = get_irn_dbg_info(node);
347 ir_mode *mode = get_irn_mode(node);
350 if (mode_is_float(mode)) {
351 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
352 ir_node *nomem = new_NoMem();
354 if (ia32_cg_config.use_sse2)
355 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
357 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
358 set_ia32_am_sc(cnst, get_SymConst_entity(node));
359 set_ia32_use_frame(cnst);
363 if(get_SymConst_kind(node) != symconst_addr_ent) {
364 panic("backend only support symconst_addr_ent (at %+F)", node);
366 entity = get_SymConst_entity(node);
367 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
382 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
383 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
384 static const struct {
386 const char *ent_name;
387 const char *cnst_str;
390 } names [ia32_known_const_max] = {
391 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
392 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
393 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
394 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
395 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
397 static ir_entity *ent_cache[ia32_known_const_max];
399 const char *tp_name, *ent_name, *cnst_str;
407 ent_name = names[kct].ent_name;
408 if (! ent_cache[kct]) {
409 tp_name = names[kct].tp_name;
410 cnst_str = names[kct].cnst_str;
412 switch (names[kct].mode) {
413 case 0: mode = mode_Iu; break;
414 case 1: mode = mode_Lu; break;
415 default: mode = mode_F; break;
417 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
418 tp = new_type_primitive(new_id_from_str(tp_name), mode);
419 /* set the specified alignment */
420 set_type_alignment_bytes(tp, names[kct].align);
422 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
424 set_entity_ld_ident(ent, get_entity_ident(ent));
425 set_entity_visibility(ent, visibility_local);
426 set_entity_variability(ent, variability_constant);
427 set_entity_allocation(ent, allocation_static);
429 /* we create a new entity here: It's initialization must resist on the
431 rem = current_ir_graph;
432 current_ir_graph = get_const_code_irg();
433 cnst = new_Const(mode, tv);
434 current_ir_graph = rem;
436 set_atomic_ent_value(ent, cnst);
438 /* cache the entry */
439 ent_cache[kct] = ent;
442 return ent_cache[kct];
447 * Prints the old node name on cg obst and returns a pointer to it.
449 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
450 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
452 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
453 obstack_1grow(isa->name_obst, 0);
454 return obstack_finish(isa->name_obst);
459 * return true if the node is a Proj(Load) and could be used in source address
460 * mode for another node. Will return only true if the @p other node is not
461 * dependent on the memory of the Load (for binary operations use the other
462 * input here, for unary operations use NULL).
464 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
465 ir_node *other, ir_node *other2)
467 ir_mode *mode = get_irn_mode(node);
471 /* float constants are always available */
472 if(is_Const(node) && mode_is_float(mode)) {
473 if(!is_simple_x87_Const(node))
475 if(get_irn_n_edges(node) > 1)
482 load = get_Proj_pred(node);
483 pn = get_Proj_proj(node);
484 if(!is_Load(load) || pn != pn_Load_res)
486 if(get_nodes_block(load) != block)
488 /* we only use address mode if we're the only user of the load */
489 if(get_irn_n_edges(node) > 1)
491 /* in some edge cases with address mode we might reach the load normally
492 * and through some AM sequence, if it is already materialized then we
493 * can't create an AM node from it */
494 if(be_is_transformed(node))
497 /* don't do AM if other node inputs depend on the load (via mem-proj) */
498 if(other != NULL && get_nodes_block(other) == block
499 && heights_reachable_in_block(heights, other, load))
501 if(other2 != NULL && get_nodes_block(other2) == block
502 && heights_reachable_in_block(heights, other2, load))
508 typedef struct ia32_address_mode_t ia32_address_mode_t;
509 struct ia32_address_mode_t {
513 ia32_op_type_t op_type;
517 unsigned commutative : 1;
518 unsigned ins_permuted : 1;
521 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
523 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
525 /* construct load address */
526 memset(addr, 0, sizeof(addr[0]));
527 ia32_create_address_mode(addr, ptr, /*force=*/0);
529 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
530 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
531 addr->mem = be_transform_node(mem);
534 static void build_address(ia32_address_mode_t *am, ir_node *node)
536 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
537 ia32_address_t *addr = &am->addr;
544 ir_entity *entity = create_float_const_entity(node);
545 addr->base = noreg_gp;
546 addr->index = noreg_gp;
547 addr->mem = new_NoMem();
548 addr->symconst_ent = entity;
550 am->ls_mode = get_irn_mode(node);
551 am->pinned = op_pin_state_floats;
555 load = get_Proj_pred(node);
556 ptr = get_Load_ptr(load);
557 mem = get_Load_mem(load);
558 new_mem = be_transform_node(mem);
559 am->pinned = get_irn_pinned(load);
560 am->ls_mode = get_Load_mode(load);
561 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
563 /* construct load address */
564 ia32_create_address_mode(addr, ptr, /*force=*/0);
566 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
567 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
571 static void set_address(ir_node *node, const ia32_address_t *addr)
573 set_ia32_am_scale(node, addr->scale);
574 set_ia32_am_sc(node, addr->symconst_ent);
575 set_ia32_am_offs_int(node, addr->offset);
576 if(addr->symconst_sign)
577 set_ia32_am_sc_sign(node);
579 set_ia32_use_frame(node);
580 set_ia32_frame_ent(node, addr->frame_entity);
583 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
585 set_address(node, &am->addr);
587 set_ia32_op_type(node, am->op_type);
588 set_ia32_ls_mode(node, am->ls_mode);
589 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
590 set_irn_pinned(node, am->pinned);
593 set_ia32_commutative(node);
597 * Check, if a given node is a Down-Conv, ie. a integer Conv
598 * from a mode with a mode with more bits to a mode with lesser bits.
599 * Moreover, we return only true if the node has not more than 1 user.
601 * @param node the node
602 * @return non-zero if node is a Down-Conv
604 static int is_downconv(const ir_node *node)
612 /* we only want to skip the conv when we're the only user
613 * (not optimal but for now...)
615 if(get_irn_n_edges(node) > 1)
618 src_mode = get_irn_mode(get_Conv_op(node));
619 dest_mode = get_irn_mode(node);
620 return mode_needs_gp_reg(src_mode)
621 && mode_needs_gp_reg(dest_mode)
622 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
625 /* Skip all Down-Conv's on a given node and return the resulting node. */
626 ir_node *ia32_skip_downconv(ir_node *node) {
627 while (is_downconv(node))
628 node = get_Conv_op(node);
634 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
636 ir_mode *mode = get_irn_mode(node);
641 if(mode_is_signed(mode)) {
646 block = get_nodes_block(node);
647 dbgi = get_irn_dbg_info(node);
649 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
654 * matches operands of a node into ia32 addressing/operand modes. This covers
655 * usage of source address mode, immediates, operations with non 32-bit modes,
657 * The resulting data is filled into the @p am struct. block is the block
658 * of the node whose arguments are matched. op1, op2 are the first and second
659 * input that are matched (op1 may be NULL). other_op is another unrelated
660 * input that is not matched! but which is needed sometimes to check if AM
661 * for op1/op2 is legal.
662 * @p flags describes the supported modes of the operation in detail.
664 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
665 ir_node *op1, ir_node *op2, ir_node *other_op,
668 ia32_address_t *addr = &am->addr;
669 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
672 ir_mode *mode = get_irn_mode(op2);
674 unsigned commutative;
675 int use_am_and_immediates;
677 int mode_bits = get_mode_size_bits(mode);
679 memset(am, 0, sizeof(am[0]));
681 commutative = (flags & match_commutative) != 0;
682 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
683 use_am = (flags & match_am) != 0;
684 use_immediate = (flags & match_immediate) != 0;
685 assert(!use_am_and_immediates || use_immediate);
688 assert(!commutative || op1 != NULL);
689 assert(use_am || !(flags & match_8bit_am));
690 assert(use_am || !(flags & match_16bit_am));
693 if (! (flags & match_8bit_am))
695 /* we don't automatically add upconvs yet */
696 assert((flags & match_mode_neutral) || (flags & match_8bit));
697 } else if(mode_bits == 16) {
698 if(! (flags & match_16bit_am))
700 /* we don't automatically add upconvs yet */
701 assert((flags & match_mode_neutral) || (flags & match_16bit));
704 /* we can simply skip downconvs for mode neutral nodes: the upper bits
705 * can be random for these operations */
706 if(flags & match_mode_neutral) {
707 op2 = ia32_skip_downconv(op2);
709 op1 = ia32_skip_downconv(op1);
713 /* match immediates. firm nodes are normalized: constants are always on the
716 if(! (flags & match_try_am) && use_immediate) {
717 new_op2 = try_create_Immediate(op2, 0);
721 && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
722 build_address(am, op2);
723 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
724 if(mode_is_float(mode)) {
725 new_op2 = ia32_new_NoReg_vfp(env_cg);
729 am->op_type = ia32_AddrModeS;
730 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
732 && ia32_use_source_address_mode(block, op1, op2, other_op)) {
734 build_address(am, op1);
736 if(mode_is_float(mode)) {
737 noreg = ia32_new_NoReg_vfp(env_cg);
742 if(new_op2 != NULL) {
745 new_op1 = be_transform_node(op2);
747 am->ins_permuted = 1;
749 am->op_type = ia32_AddrModeS;
751 if(flags & match_try_am) {
754 am->op_type = ia32_Normal;
758 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
760 new_op2 = be_transform_node(op2);
761 am->op_type = ia32_Normal;
762 am->ls_mode = get_irn_mode(op2);
763 if(flags & match_mode_neutral)
764 am->ls_mode = mode_Iu;
766 if(addr->base == NULL)
767 addr->base = noreg_gp;
768 if(addr->index == NULL)
769 addr->index = noreg_gp;
770 if(addr->mem == NULL)
771 addr->mem = new_NoMem();
773 am->new_op1 = new_op1;
774 am->new_op2 = new_op2;
775 am->commutative = commutative;
778 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
780 ir_graph *irg = current_ir_graph;
784 if(am->mem_proj == NULL)
787 /* we have to create a mode_T so the old MemProj can attach to us */
788 mode = get_irn_mode(node);
789 load = get_Proj_pred(am->mem_proj);
791 mark_irn_visited(load);
792 be_set_transformed_node(load, node);
795 set_irn_mode(node, mode_T);
796 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
803 * Construct a standard binary operation, set AM and immediate if required.
805 * @param op1 The first operand
806 * @param op2 The second operand
807 * @param func The node constructor function
808 * @return The constructed ia32 node.
810 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
811 construct_binop_func *func, match_flags_t flags)
813 ir_node *block = get_nodes_block(node);
814 ir_node *new_block = be_transform_node(block);
815 ir_graph *irg = current_ir_graph;
816 dbg_info *dbgi = get_irn_dbg_info(node);
818 ia32_address_mode_t am;
819 ia32_address_t *addr = &am.addr;
821 match_arguments(&am, block, op1, op2, NULL, flags);
823 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
824 am.new_op1, am.new_op2);
825 set_am_attributes(new_node, &am);
826 /* we can't use source address mode anymore when using immediates */
827 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
828 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
829 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
831 new_node = fix_mem_proj(new_node, &am);
838 n_ia32_l_binop_right,
839 n_ia32_l_binop_eflags
841 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
842 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
843 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
844 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
845 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
846 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
849 * Construct a binary operation which also consumes the eflags.
851 * @param node The node to transform
852 * @param func The node constructor function
853 * @param flags The match flags
854 * @return The constructor ia32 node
856 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
859 ir_node *src_block = get_nodes_block(node);
860 ir_node *block = be_transform_node(src_block);
861 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
862 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
863 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
864 ir_node *new_eflags = be_transform_node(eflags);
865 ir_graph *irg = current_ir_graph;
866 dbg_info *dbgi = get_irn_dbg_info(node);
868 ia32_address_mode_t am;
869 ia32_address_t *addr = &am.addr;
871 match_arguments(&am, src_block, op1, op2, NULL, flags);
873 new_node = func(dbgi, irg, block, addr->base, addr->index,
874 addr->mem, am.new_op1, am.new_op2, new_eflags);
875 set_am_attributes(new_node, &am);
876 /* we can't use source address mode anymore when using immediates */
877 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
878 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
879 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
881 new_node = fix_mem_proj(new_node, &am);
886 static ir_node *get_fpcw(void)
889 if(initial_fpcw != NULL)
892 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
893 &ia32_fp_cw_regs[REG_FPCW]);
894 initial_fpcw = be_transform_node(fpcw);
900 * Construct a standard binary operation, set AM and immediate if required.
902 * @param op1 The first operand
903 * @param op2 The second operand
904 * @param func The node constructor function
905 * @return The constructed ia32 node.
907 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
908 construct_binop_float_func *func,
911 ir_graph *irg = current_ir_graph;
912 dbg_info *dbgi = get_irn_dbg_info(node);
913 ir_node *block = get_nodes_block(node);
914 ir_node *new_block = be_transform_node(block);
915 ir_mode *mode = get_irn_mode(node);
917 ia32_address_mode_t am;
918 ia32_address_t *addr = &am.addr;
920 /* cannot use addresmode with long double on x87 */
921 if (get_mode_size_bits(mode) > 64)
924 match_arguments(&am, block, op1, op2, NULL, flags);
926 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
927 am.new_op1, am.new_op2, get_fpcw());
928 set_am_attributes(new_node, &am);
930 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
932 new_node = fix_mem_proj(new_node, &am);
938 * Construct a shift/rotate binary operation, sets AM and immediate if required.
940 * @param op1 The first operand
941 * @param op2 The second operand
942 * @param func The node constructor function
943 * @return The constructed ia32 node.
945 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
946 construct_shift_func *func,
949 dbg_info *dbgi = get_irn_dbg_info(node);
950 ir_graph *irg = current_ir_graph;
951 ir_node *block = get_nodes_block(node);
952 ir_node *new_block = be_transform_node(block);
957 assert(! mode_is_float(get_irn_mode(node)));
958 assert(flags & match_immediate);
959 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
961 if(flags & match_mode_neutral) {
962 op1 = ia32_skip_downconv(op1);
964 new_op1 = be_transform_node(op1);
966 /* the shift amount can be any mode that is bigger than 5 bits, since all
967 * other bits are ignored anyway */
968 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
969 op2 = get_Conv_op(op2);
970 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
972 new_op2 = create_immediate_or_transform(op2, 0);
974 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
975 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
977 /* lowered shift instruction may have a dependency operand, handle it here */
978 if (get_irn_arity(node) == 3) {
979 /* we have a dependency */
980 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
981 add_irn_dep(new_node, new_dep);
989 * Construct a standard unary operation, set AM and immediate if required.
991 * @param op The operand
992 * @param func The node constructor function
993 * @return The constructed ia32 node.
995 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
998 ir_graph *irg = current_ir_graph;
999 dbg_info *dbgi = get_irn_dbg_info(node);
1000 ir_node *block = get_nodes_block(node);
1001 ir_node *new_block = be_transform_node(block);
1005 assert(flags == 0 || flags == match_mode_neutral);
1006 if(flags & match_mode_neutral) {
1007 op = ia32_skip_downconv(op);
1010 new_op = be_transform_node(op);
1011 new_node = func(dbgi, irg, new_block, new_op);
1013 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1018 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1019 ia32_address_t *addr)
1021 ir_graph *irg = current_ir_graph;
1022 ir_node *base = addr->base;
1023 ir_node *index = addr->index;
1027 base = ia32_new_NoReg_gp(env_cg);
1029 base = be_transform_node(base);
1033 index = ia32_new_NoReg_gp(env_cg);
1035 index = be_transform_node(index);
1038 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1039 set_address(res, addr);
1044 static int am_has_immediates(const ia32_address_t *addr)
1046 return addr->offset != 0 || addr->symconst_ent != NULL
1047 || addr->frame_entity || addr->use_frame;
1051 * Creates an ia32 Add.
1053 * @return the created ia32 Add node
1055 static ir_node *gen_Add(ir_node *node) {
1056 ir_graph *irg = current_ir_graph;
1057 dbg_info *dbgi = get_irn_dbg_info(node);
1058 ir_node *block = get_nodes_block(node);
1059 ir_node *new_block = be_transform_node(block);
1060 ir_node *op1 = get_Add_left(node);
1061 ir_node *op2 = get_Add_right(node);
1062 ir_mode *mode = get_irn_mode(node);
1064 ir_node *add_immediate_op;
1065 ia32_address_t addr;
1066 ia32_address_mode_t am;
1068 if (mode_is_float(mode)) {
1069 if (ia32_cg_config.use_sse2)
1070 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1071 match_commutative | match_am);
1073 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1074 match_commutative | match_am);
1077 ia32_mark_non_am(node);
1079 op2 = ia32_skip_downconv(op2);
1080 op1 = ia32_skip_downconv(op1);
1084 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1085 * 1. Add with immediate -> Lea
1086 * 2. Add with possible source address mode -> Add
1087 * 3. Otherwise -> Lea
1089 memset(&addr, 0, sizeof(addr));
1090 ia32_create_address_mode(&addr, node, /*force=*/1);
1091 add_immediate_op = NULL;
1093 if(addr.base == NULL && addr.index == NULL) {
1094 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1095 addr.symconst_sign, addr.offset);
1096 add_irn_dep(new_node, get_irg_frame(irg));
1097 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1100 /* add with immediate? */
1101 if(addr.index == NULL) {
1102 add_immediate_op = addr.base;
1103 } else if(addr.base == NULL && addr.scale == 0) {
1104 add_immediate_op = addr.index;
1107 if(add_immediate_op != NULL) {
1108 if(!am_has_immediates(&addr)) {
1109 #ifdef DEBUG_libfirm
1110 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1113 return be_transform_node(add_immediate_op);
1116 new_node = create_lea_from_address(dbgi, new_block, &addr);
1117 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1121 /* test if we can use source address mode */
1122 match_arguments(&am, block, op1, op2, NULL, match_commutative
1123 | match_mode_neutral | match_am | match_immediate | match_try_am);
1125 /* construct an Add with source address mode */
1126 if (am.op_type == ia32_AddrModeS) {
1127 ia32_address_t *am_addr = &am.addr;
1128 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1129 am_addr->index, am_addr->mem, am.new_op1,
1131 set_am_attributes(new_node, &am);
1132 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1134 new_node = fix_mem_proj(new_node, &am);
1139 /* otherwise construct a lea */
1140 new_node = create_lea_from_address(dbgi, new_block, &addr);
1141 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1146 * Creates an ia32 Mul.
1148 * @return the created ia32 Mul node
1150 static ir_node *gen_Mul(ir_node *node) {
1151 ir_node *op1 = get_Mul_left(node);
1152 ir_node *op2 = get_Mul_right(node);
1153 ir_mode *mode = get_irn_mode(node);
1155 if (mode_is_float(mode)) {
1156 if (ia32_cg_config.use_sse2)
1157 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1158 match_commutative | match_am);
1160 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1161 match_commutative | match_am);
1164 /* for the lower 32bit of the result it doesn't matter whether we use
1165 * signed or unsigned multiplication so we use IMul as it has fewer
1167 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1168 match_commutative | match_am | match_mode_neutral |
1169 match_immediate | match_am_and_immediates);
1173 * Creates an ia32 Mulh.
1174 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1175 * this result while Mul returns the lower 32 bit.
1177 * @return the created ia32 Mulh node
1179 static ir_node *gen_Mulh(ir_node *node)
1181 ir_node *block = get_nodes_block(node);
1182 ir_node *new_block = be_transform_node(block);
1183 ir_graph *irg = current_ir_graph;
1184 dbg_info *dbgi = get_irn_dbg_info(node);
1185 ir_mode *mode = get_irn_mode(node);
1186 ir_node *op1 = get_Mulh_left(node);
1187 ir_node *op2 = get_Mulh_right(node);
1188 ir_node *proj_res_high;
1190 ia32_address_mode_t am;
1191 ia32_address_t *addr = &am.addr;
1193 assert(!mode_is_float(mode) && "Mulh with float not supported");
1194 assert(get_mode_size_bits(mode) == 32);
1196 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1198 if (mode_is_signed(mode)) {
1199 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1200 addr->index, addr->mem, am.new_op1,
1203 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1204 addr->index, addr->mem, am.new_op1,
1208 set_am_attributes(new_node, &am);
1209 /* we can't use source address mode anymore when using immediates */
1210 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1211 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1212 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1214 assert(get_irn_mode(new_node) == mode_T);
1216 fix_mem_proj(new_node, &am);
1218 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1219 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1220 mode_Iu, pn_ia32_IMul1OP_res_high);
1222 return proj_res_high;
1228 * Creates an ia32 And.
1230 * @return The created ia32 And node
1232 static ir_node *gen_And(ir_node *node) {
1233 ir_node *op1 = get_And_left(node);
1234 ir_node *op2 = get_And_right(node);
1235 assert(! mode_is_float(get_irn_mode(node)));
1237 /* is it a zero extension? */
1238 if (is_Const(op2)) {
1239 tarval *tv = get_Const_tarval(op2);
1240 long v = get_tarval_long(tv);
1242 if (v == 0xFF || v == 0xFFFF) {
1243 dbg_info *dbgi = get_irn_dbg_info(node);
1244 ir_node *block = get_nodes_block(node);
1251 assert(v == 0xFFFF);
1254 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1260 return gen_binop(node, op1, op2, new_rd_ia32_And,
1261 match_commutative | match_mode_neutral | match_am
1268 * Creates an ia32 Or.
1270 * @return The created ia32 Or node
1272 static ir_node *gen_Or(ir_node *node) {
1273 ir_node *op1 = get_Or_left(node);
1274 ir_node *op2 = get_Or_right(node);
1276 assert (! mode_is_float(get_irn_mode(node)));
1277 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1278 | match_mode_neutral | match_am | match_immediate);
1284 * Creates an ia32 Eor.
1286 * @return The created ia32 Eor node
1288 static ir_node *gen_Eor(ir_node *node) {
1289 ir_node *op1 = get_Eor_left(node);
1290 ir_node *op2 = get_Eor_right(node);
1292 assert(! mode_is_float(get_irn_mode(node)));
1293 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1294 | match_mode_neutral | match_am | match_immediate);
1299 * Creates an ia32 Sub.
1301 * @return The created ia32 Sub node
1303 static ir_node *gen_Sub(ir_node *node) {
1304 ir_node *op1 = get_Sub_left(node);
1305 ir_node *op2 = get_Sub_right(node);
1306 ir_mode *mode = get_irn_mode(node);
1308 if (mode_is_float(mode)) {
1309 if (ia32_cg_config.use_sse2)
1310 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1312 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1317 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1321 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1322 | match_am | match_immediate);
1326 * Generates an ia32 DivMod with additional infrastructure for the
1327 * register allocator if needed.
1329 static ir_node *create_Div(ir_node *node)
1331 ir_graph *irg = current_ir_graph;
1332 dbg_info *dbgi = get_irn_dbg_info(node);
1333 ir_node *block = get_nodes_block(node);
1334 ir_node *new_block = be_transform_node(block);
1341 ir_node *sign_extension;
1343 ia32_address_mode_t am;
1344 ia32_address_t *addr = &am.addr;
1346 /* the upper bits have random contents for smaller modes */
1348 switch (get_irn_opcode(node)) {
1350 op1 = get_Div_left(node);
1351 op2 = get_Div_right(node);
1352 mem = get_Div_mem(node);
1353 mode = get_Div_resmode(node);
1354 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1357 op1 = get_Mod_left(node);
1358 op2 = get_Mod_right(node);
1359 mem = get_Mod_mem(node);
1360 mode = get_Mod_resmode(node);
1361 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1364 op1 = get_DivMod_left(node);
1365 op2 = get_DivMod_right(node);
1366 mem = get_DivMod_mem(node);
1367 mode = get_DivMod_resmode(node);
1368 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1371 panic("invalid divmod node %+F", node);
1374 match_arguments(&am, block, op1, op2, NULL, match_am);
1376 if(!is_NoMem(mem)) {
1377 new_mem = be_transform_node(mem);
1378 if(!is_NoMem(addr->mem)) {
1382 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1385 new_mem = addr->mem;
1388 if (mode_is_signed(mode)) {
1389 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1390 add_irn_dep(produceval, get_irg_frame(irg));
1391 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1394 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1395 addr->index, new_mem, am.new_op1,
1396 sign_extension, am.new_op2);
1398 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1399 add_irn_dep(sign_extension, get_irg_frame(irg));
1401 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1402 addr->index, new_mem, am.new_op1,
1403 sign_extension, am.new_op2);
1406 set_ia32_exc_label(new_node, has_exc);
1407 set_irn_pinned(new_node, get_irn_pinned(node));
1409 set_am_attributes(new_node, &am);
1410 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1412 new_node = fix_mem_proj(new_node, &am);
1418 static ir_node *gen_Mod(ir_node *node) {
1419 return create_Div(node);
1422 static ir_node *gen_Div(ir_node *node) {
1423 return create_Div(node);
1426 static ir_node *gen_DivMod(ir_node *node) {
1427 return create_Div(node);
1433 * Creates an ia32 floating Div.
1435 * @return The created ia32 xDiv node
1437 static ir_node *gen_Quot(ir_node *node)
1439 ir_node *op1 = get_Quot_left(node);
1440 ir_node *op2 = get_Quot_right(node);
1442 if (ia32_cg_config.use_sse2) {
1443 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1445 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1451 * Creates an ia32 Shl.
1453 * @return The created ia32 Shl node
1455 static ir_node *gen_Shl(ir_node *node) {
1456 ir_node *left = get_Shl_left(node);
1457 ir_node *right = get_Shl_right(node);
1459 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1460 match_mode_neutral | match_immediate);
1464 * Creates an ia32 Shr.
1466 * @return The created ia32 Shr node
1468 static ir_node *gen_Shr(ir_node *node) {
1469 ir_node *left = get_Shr_left(node);
1470 ir_node *right = get_Shr_right(node);
1472 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1478 * Creates an ia32 Sar.
1480 * @return The created ia32 Shrs node
1482 static ir_node *gen_Shrs(ir_node *node) {
1483 ir_node *left = get_Shrs_left(node);
1484 ir_node *right = get_Shrs_right(node);
1485 ir_mode *mode = get_irn_mode(node);
1487 if(is_Const(right) && mode == mode_Is) {
1488 tarval *tv = get_Const_tarval(right);
1489 long val = get_tarval_long(tv);
1491 /* this is a sign extension */
1492 ir_graph *irg = current_ir_graph;
1493 dbg_info *dbgi = get_irn_dbg_info(node);
1494 ir_node *block = be_transform_node(get_nodes_block(node));
1496 ir_node *new_op = be_transform_node(op);
1497 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1498 add_irn_dep(pval, get_irg_frame(irg));
1500 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1504 /* 8 or 16 bit sign extension? */
1505 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1506 ir_node *shl_left = get_Shl_left(left);
1507 ir_node *shl_right = get_Shl_right(left);
1508 if(is_Const(shl_right)) {
1509 tarval *tv1 = get_Const_tarval(right);
1510 tarval *tv2 = get_Const_tarval(shl_right);
1511 if(tv1 == tv2 && tarval_is_long(tv1)) {
1512 long val = get_tarval_long(tv1);
1513 if(val == 16 || val == 24) {
1514 dbg_info *dbgi = get_irn_dbg_info(node);
1515 ir_node *block = get_nodes_block(node);
1525 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1534 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1540 * Creates an ia32 RotL.
1542 * @param op1 The first operator
1543 * @param op2 The second operator
1544 * @return The created ia32 RotL node
1546 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1547 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1553 * Creates an ia32 RotR.
1554 * NOTE: There is no RotR with immediate because this would always be a RotL
1555 * "imm-mode_size_bits" which can be pre-calculated.
1557 * @param op1 The first operator
1558 * @param op2 The second operator
1559 * @return The created ia32 RotR node
1561 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1562 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1568 * Creates an ia32 RotR or RotL (depending on the found pattern).
1570 * @return The created ia32 RotL or RotR node
1572 static ir_node *gen_Rot(ir_node *node) {
1573 ir_node *rotate = NULL;
1574 ir_node *op1 = get_Rot_left(node);
1575 ir_node *op2 = get_Rot_right(node);
1577 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1578 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1579 that means we can create a RotR instead of an Add and a RotL */
1581 if (get_irn_op(op2) == op_Add) {
1583 ir_node *left = get_Add_left(add);
1584 ir_node *right = get_Add_right(add);
1585 if (is_Const(right)) {
1586 tarval *tv = get_Const_tarval(right);
1587 ir_mode *mode = get_irn_mode(node);
1588 long bits = get_mode_size_bits(mode);
1590 if (get_irn_op(left) == op_Minus &&
1591 tarval_is_long(tv) &&
1592 get_tarval_long(tv) == bits &&
1595 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1596 rotate = gen_RotR(node, op1, get_Minus_op(left));
1601 if (rotate == NULL) {
1602 rotate = gen_RotL(node, op1, op2);
1611 * Transforms a Minus node.
1613 * @return The created ia32 Minus node
1615 static ir_node *gen_Minus(ir_node *node)
1617 ir_node *op = get_Minus_op(node);
1618 ir_node *block = be_transform_node(get_nodes_block(node));
1619 ir_graph *irg = current_ir_graph;
1620 dbg_info *dbgi = get_irn_dbg_info(node);
1621 ir_mode *mode = get_irn_mode(node);
1626 if (mode_is_float(mode)) {
1627 ir_node *new_op = be_transform_node(op);
1628 if (ia32_cg_config.use_sse2) {
1629 /* TODO: non-optimal... if we have many xXors, then we should
1630 * rather create a load for the const and use that instead of
1631 * several AM nodes... */
1632 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1633 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1634 ir_node *nomem = new_rd_NoMem(irg);
1636 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1637 nomem, new_op, noreg_xmm);
1639 size = get_mode_size_bits(mode);
1640 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1642 set_ia32_am_sc(new_node, ent);
1643 set_ia32_op_type(new_node, ia32_AddrModeS);
1644 set_ia32_ls_mode(new_node, mode);
1646 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1649 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1652 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1658 * Transforms a Not node.
1660 * @return The created ia32 Not node
1662 static ir_node *gen_Not(ir_node *node) {
1663 ir_node *op = get_Not_op(node);
1665 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1666 assert (! mode_is_float(get_irn_mode(node)));
1668 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1674 * Transforms an Abs node.
1676 * @return The created ia32 Abs node
1678 static ir_node *gen_Abs(ir_node *node)
1680 ir_node *block = get_nodes_block(node);
1681 ir_node *new_block = be_transform_node(block);
1682 ir_node *op = get_Abs_op(node);
1683 ir_graph *irg = current_ir_graph;
1684 dbg_info *dbgi = get_irn_dbg_info(node);
1685 ir_mode *mode = get_irn_mode(node);
1686 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1687 ir_node *nomem = new_NoMem();
1693 if (mode_is_float(mode)) {
1694 new_op = be_transform_node(op);
1696 if (ia32_cg_config.use_sse2) {
1697 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1698 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1699 nomem, new_op, noreg_fp);
1701 size = get_mode_size_bits(mode);
1702 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1704 set_ia32_am_sc(new_node, ent);
1706 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1708 set_ia32_op_type(new_node, ia32_AddrModeS);
1709 set_ia32_ls_mode(new_node, mode);
1711 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1712 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1715 ir_node *xor, *pval, *sign_extension;
1717 if (get_mode_size_bits(mode) == 32) {
1718 new_op = be_transform_node(op);
1720 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1723 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1724 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1727 add_irn_dep(pval, get_irg_frame(irg));
1728 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1730 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1731 nomem, new_op, sign_extension);
1732 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1734 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1735 nomem, xor, sign_extension);
1736 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1742 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1744 ir_graph *irg = current_ir_graph;
1752 /* we have a Cmp as input */
1754 ir_node *pred = get_Proj_pred(node);
1756 flags = be_transform_node(pred);
1757 *pnc_out = get_Proj_proj(node);
1762 /* a mode_b value, we have to compare it against 0 */
1763 dbgi = get_irn_dbg_info(node);
1764 new_block = be_transform_node(get_nodes_block(node));
1765 new_op = be_transform_node(node);
1766 noreg = ia32_new_NoReg_gp(env_cg);
1767 nomem = new_NoMem();
1768 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1769 new_op, new_op, 0, 0);
1770 *pnc_out = pn_Cmp_Lg;
1775 * Transforms a Load.
1777 * @return the created ia32 Load node
1779 static ir_node *gen_Load(ir_node *node) {
1780 ir_node *old_block = get_nodes_block(node);
1781 ir_node *block = be_transform_node(old_block);
1782 ir_node *ptr = get_Load_ptr(node);
1783 ir_node *mem = get_Load_mem(node);
1784 ir_node *new_mem = be_transform_node(mem);
1787 ir_graph *irg = current_ir_graph;
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1790 ir_mode *mode = get_Load_mode(node);
1793 ia32_address_t addr;
1795 /* construct load address */
1796 memset(&addr, 0, sizeof(addr));
1797 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1804 base = be_transform_node(base);
1810 index = be_transform_node(index);
1813 if (mode_is_float(mode)) {
1814 if (ia32_cg_config.use_sse2) {
1815 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1817 res_mode = mode_xmm;
1819 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1821 res_mode = mode_vfp;
1824 assert(mode != mode_b);
1826 /* create a conv node with address mode for smaller modes */
1827 if(get_mode_size_bits(mode) < 32) {
1828 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1829 new_mem, noreg, mode);
1831 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1836 set_irn_pinned(new_node, get_irn_pinned(node));
1837 set_ia32_op_type(new_node, ia32_AddrModeS);
1838 set_ia32_ls_mode(new_node, mode);
1839 set_address(new_node, &addr);
1841 if(get_irn_pinned(node) == op_pin_state_floats) {
1842 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1845 /* make sure we are scheduled behind the initial IncSP/Barrier
1846 * to avoid spills being placed before it
1848 if (block == get_irg_start_block(irg)) {
1849 add_irn_dep(new_node, get_irg_frame(irg));
1852 set_ia32_exc_label(new_node,
1853 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1854 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1859 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1860 ir_node *ptr, ir_node *other)
1867 /* we only use address mode if we're the only user of the load */
1868 if(get_irn_n_edges(node) > 1)
1871 load = get_Proj_pred(node);
1874 if(get_nodes_block(load) != block)
1877 /* Store should be attached to the load */
1878 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1880 /* store should have the same pointer as the load */
1881 if(get_Load_ptr(load) != ptr)
1884 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1885 if(other != NULL && get_nodes_block(other) == block
1886 && heights_reachable_in_block(heights, other, load))
1892 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1893 ir_node *mem, ir_node *ptr, ir_mode *mode,
1894 construct_binop_dest_func *func,
1895 construct_binop_dest_func *func8bit,
1896 match_flags_t flags)
1898 ir_node *src_block = get_nodes_block(node);
1900 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1901 ir_graph *irg = current_ir_graph;
1906 ia32_address_mode_t am;
1907 ia32_address_t *addr = &am.addr;
1908 memset(&am, 0, sizeof(am));
1910 assert(flags & match_dest_am);
1911 assert(flags & match_immediate); /* there is no destam node without... */
1912 commutative = (flags & match_commutative) != 0;
1914 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1915 build_address(&am, op1);
1916 new_op = create_immediate_or_transform(op2, 0);
1917 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1918 build_address(&am, op2);
1919 new_op = create_immediate_or_transform(op1, 0);
1924 if(addr->base == NULL)
1925 addr->base = noreg_gp;
1926 if(addr->index == NULL)
1927 addr->index = noreg_gp;
1928 if(addr->mem == NULL)
1929 addr->mem = new_NoMem();
1931 dbgi = get_irn_dbg_info(node);
1932 block = be_transform_node(src_block);
1933 if(get_mode_size_bits(mode) == 8) {
1934 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1937 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1940 set_address(new_node, addr);
1941 set_ia32_op_type(new_node, ia32_AddrModeD);
1942 set_ia32_ls_mode(new_node, mode);
1943 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1948 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1949 ir_node *ptr, ir_mode *mode,
1950 construct_unop_dest_func *func)
1952 ir_graph *irg = current_ir_graph;
1953 ir_node *src_block = get_nodes_block(node);
1957 ia32_address_mode_t am;
1958 ia32_address_t *addr = &am.addr;
1959 memset(&am, 0, sizeof(am));
1961 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1964 build_address(&am, op);
1966 dbgi = get_irn_dbg_info(node);
1967 block = be_transform_node(src_block);
1968 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1969 set_address(new_node, addr);
1970 set_ia32_op_type(new_node, ia32_AddrModeD);
1971 set_ia32_ls_mode(new_node, mode);
1972 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1977 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1978 ir_mode *mode = get_irn_mode(node);
1979 ir_node *psi_true = get_Psi_val(node, 0);
1980 ir_node *psi_default = get_Psi_default(node);
1991 ia32_address_t addr;
1993 if(get_mode_size_bits(mode) != 8)
1996 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1998 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2004 build_address_ptr(&addr, ptr, mem);
2006 irg = current_ir_graph;
2007 dbgi = get_irn_dbg_info(node);
2008 block = get_nodes_block(node);
2009 new_block = be_transform_node(block);
2010 cond = get_Psi_cond(node, 0);
2011 flags = get_flags_node(cond, &pnc);
2012 new_mem = be_transform_node(mem);
2013 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2014 addr.index, addr.mem, flags, pnc, negated);
2015 set_address(new_node, &addr);
2016 set_ia32_op_type(new_node, ia32_AddrModeD);
2017 set_ia32_ls_mode(new_node, mode);
2018 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2023 static ir_node *try_create_dest_am(ir_node *node) {
2024 ir_node *val = get_Store_value(node);
2025 ir_node *mem = get_Store_mem(node);
2026 ir_node *ptr = get_Store_ptr(node);
2027 ir_mode *mode = get_irn_mode(val);
2028 int bits = get_mode_size_bits(mode);
2033 /* handle only GP modes for now... */
2034 if(!mode_needs_gp_reg(mode))
2038 /* store must be the only user of the val node */
2039 if(get_irn_n_edges(val) > 1)
2041 /* skip pointless convs */
2043 ir_node *conv_op = get_Conv_op(val);
2044 ir_mode *pred_mode = get_irn_mode(conv_op);
2045 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2053 /* value must be in the same block */
2054 if(get_nodes_block(node) != get_nodes_block(val))
2057 switch(get_irn_opcode(val)) {
2059 op1 = get_Add_left(val);
2060 op2 = get_Add_right(val);
2061 if(is_Const_1(op2)) {
2062 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2063 new_rd_ia32_IncMem);
2065 } else if(is_Const_Minus_1(op2)) {
2066 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2067 new_rd_ia32_DecMem);
2070 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2071 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2072 match_dest_am | match_commutative |
2076 op1 = get_Sub_left(val);
2077 op2 = get_Sub_right(val);
2079 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2082 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2083 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2084 match_dest_am | match_immediate |
2088 op1 = get_And_left(val);
2089 op2 = get_And_right(val);
2090 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2091 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2092 match_dest_am | match_commutative |
2096 op1 = get_Or_left(val);
2097 op2 = get_Or_right(val);
2098 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2099 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2100 match_dest_am | match_commutative |
2104 op1 = get_Eor_left(val);
2105 op2 = get_Eor_right(val);
2106 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2107 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2108 match_dest_am | match_commutative |
2112 op1 = get_Shl_left(val);
2113 op2 = get_Shl_right(val);
2114 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2115 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2116 match_dest_am | match_immediate);
2119 op1 = get_Shr_left(val);
2120 op2 = get_Shr_right(val);
2121 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2122 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2123 match_dest_am | match_immediate);
2126 op1 = get_Shrs_left(val);
2127 op2 = get_Shrs_right(val);
2128 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2129 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2130 match_dest_am | match_immediate);
2133 op1 = get_Rot_left(val);
2134 op2 = get_Rot_right(val);
2135 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2136 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2137 match_dest_am | match_immediate);
2139 /* TODO: match ROR patterns... */
2141 new_node = try_create_SetMem(val, ptr, mem);
2144 op1 = get_Minus_op(val);
2145 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2148 /* should be lowered already */
2149 assert(mode != mode_b);
2150 op1 = get_Not_op(val);
2151 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2157 if(new_node != NULL) {
2158 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2159 get_irn_pinned(node) == op_pin_state_pinned) {
2160 set_irn_pinned(new_node, op_pin_state_pinned);
2167 static int is_float_to_int32_conv(const ir_node *node)
2169 ir_mode *mode = get_irn_mode(node);
2173 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2178 conv_op = get_Conv_op(node);
2179 conv_mode = get_irn_mode(conv_op);
2181 if(!mode_is_float(conv_mode))
2188 * Transforms a Store.
2190 * @return the created ia32 Store node
2192 static ir_node *gen_Store(ir_node *node)
2194 ir_node *block = get_nodes_block(node);
2195 ir_node *new_block = be_transform_node(block);
2196 ir_node *ptr = get_Store_ptr(node);
2197 ir_node *val = get_Store_value(node);
2198 ir_node *mem = get_Store_mem(node);
2199 ir_graph *irg = current_ir_graph;
2200 dbg_info *dbgi = get_irn_dbg_info(node);
2201 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2202 ir_mode *mode = get_irn_mode(val);
2205 ia32_address_t addr;
2207 /* check for destination address mode */
2208 new_node = try_create_dest_am(node);
2209 if(new_node != NULL)
2212 /* construct store address */
2213 memset(&addr, 0, sizeof(addr));
2214 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2216 if(addr.base == NULL) {
2219 addr.base = be_transform_node(addr.base);
2222 if(addr.index == NULL) {
2225 addr.index = be_transform_node(addr.index);
2227 addr.mem = be_transform_node(mem);
2229 if (mode_is_float(mode)) {
2230 /* convs (and strict-convs) before stores are unnecessary if the mode
2232 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2233 val = get_Conv_op(val);
2235 new_val = be_transform_node(val);
2236 if (ia32_cg_config.use_sse2) {
2237 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2238 addr.index, addr.mem, new_val);
2240 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2241 addr.index, addr.mem, new_val, mode);
2243 } else if(is_float_to_int32_conv(val)) {
2244 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2245 val = get_Conv_op(val);
2247 /* convs (and strict-convs) before stores are unnecessary if the mode
2249 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2250 val = get_Conv_op(val);
2252 new_val = be_transform_node(val);
2254 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2255 addr.index, addr.mem, new_val, trunc_mode);
2257 new_val = create_immediate_or_transform(val, 0);
2258 assert(mode != mode_b);
2260 if (get_mode_size_bits(mode) == 8) {
2261 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2262 addr.index, addr.mem, new_val);
2264 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2265 addr.index, addr.mem, new_val);
2269 set_irn_pinned(new_node, get_irn_pinned(node));
2270 set_ia32_op_type(new_node, ia32_AddrModeD);
2271 set_ia32_ls_mode(new_node, mode);
2273 set_ia32_exc_label(new_node,
2274 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2275 set_address(new_node, &addr);
2276 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2281 static ir_node *create_Switch(ir_node *node)
2283 ir_graph *irg = current_ir_graph;
2284 dbg_info *dbgi = get_irn_dbg_info(node);
2285 ir_node *block = be_transform_node(get_nodes_block(node));
2286 ir_node *sel = get_Cond_selector(node);
2287 ir_node *new_sel = be_transform_node(sel);
2288 int switch_min = INT_MAX;
2289 int switch_max = INT_MIN;
2290 long default_pn = get_Cond_defaultProj(node);
2292 const ir_edge_t *edge;
2294 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2296 /* determine the smallest switch case value */
2297 foreach_out_edge(node, edge) {
2298 ir_node *proj = get_edge_src_irn(edge);
2299 long pn = get_Proj_proj(proj);
2300 if(pn == default_pn)
2309 if((unsigned) (switch_max - switch_min) > 256000) {
2310 panic("Size of switch %+F bigger than 256000", node);
2313 if (switch_min != 0) {
2314 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2316 /* if smallest switch case is not 0 we need an additional sub */
2317 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2318 add_ia32_am_offs_int(new_sel, -switch_min);
2319 set_ia32_op_type(new_sel, ia32_AddrModeS);
2321 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2324 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
2325 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2330 static ir_node *gen_Cond(ir_node *node) {
2331 ir_node *block = get_nodes_block(node);
2332 ir_node *new_block = be_transform_node(block);
2333 ir_graph *irg = current_ir_graph;
2334 dbg_info *dbgi = get_irn_dbg_info(node);
2335 ir_node *sel = get_Cond_selector(node);
2336 ir_mode *sel_mode = get_irn_mode(sel);
2337 ir_node *flags = NULL;
2341 if (sel_mode != mode_b) {
2342 return create_Switch(node);
2345 /* we get flags from a cmp */
2346 flags = get_flags_node(sel, &pnc);
2348 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2349 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2357 * Transforms a CopyB node.
2359 * @return The transformed node.
2361 static ir_node *gen_CopyB(ir_node *node) {
2362 ir_node *block = be_transform_node(get_nodes_block(node));
2363 ir_node *src = get_CopyB_src(node);
2364 ir_node *new_src = be_transform_node(src);
2365 ir_node *dst = get_CopyB_dst(node);
2366 ir_node *new_dst = be_transform_node(dst);
2367 ir_node *mem = get_CopyB_mem(node);
2368 ir_node *new_mem = be_transform_node(mem);
2369 ir_node *res = NULL;
2370 ir_graph *irg = current_ir_graph;
2371 dbg_info *dbgi = get_irn_dbg_info(node);
2372 int size = get_type_size_bytes(get_CopyB_type(node));
2375 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2376 /* then we need the size explicitly in ECX. */
2377 if (size >= 32 * 4) {
2378 rem = size & 0x3; /* size % 4 */
2381 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2382 add_irn_dep(res, get_irg_frame(irg));
2384 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2387 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2390 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2393 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2398 static ir_node *gen_be_Copy(ir_node *node)
2400 ir_node *new_node = be_duplicate_node(node);
2401 ir_mode *mode = get_irn_mode(new_node);
2403 if (mode_needs_gp_reg(mode)) {
2404 set_irn_mode(new_node, mode_Iu);
2410 static ir_node *create_Fucom(ir_node *node)
2412 ir_graph *irg = current_ir_graph;
2413 dbg_info *dbgi = get_irn_dbg_info(node);
2414 ir_node *block = get_nodes_block(node);
2415 ir_node *new_block = be_transform_node(block);
2416 ir_node *left = get_Cmp_left(node);
2417 ir_node *new_left = be_transform_node(left);
2418 ir_node *right = get_Cmp_right(node);
2422 if(ia32_cg_config.use_fucomi) {
2423 new_right = be_transform_node(right);
2424 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2426 set_ia32_commutative(new_node);
2427 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2429 if(ia32_cg_config.use_ftst && is_Const_0(right)) {
2430 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2433 new_right = be_transform_node(right);
2434 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2438 set_ia32_commutative(new_node);
2440 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2442 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2443 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2449 static ir_node *create_Ucomi(ir_node *node)
2451 ir_graph *irg = current_ir_graph;
2452 dbg_info *dbgi = get_irn_dbg_info(node);
2453 ir_node *src_block = get_nodes_block(node);
2454 ir_node *new_block = be_transform_node(src_block);
2455 ir_node *left = get_Cmp_left(node);
2456 ir_node *right = get_Cmp_right(node);
2458 ia32_address_mode_t am;
2459 ia32_address_t *addr = &am.addr;
2461 match_arguments(&am, src_block, left, right, NULL,
2462 match_commutative | match_am);
2464 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2465 addr->mem, am.new_op1, am.new_op2,
2467 set_am_attributes(new_node, &am);
2469 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2471 new_node = fix_mem_proj(new_node, &am);
2477 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2478 * to fold an and into a test node
2480 static int can_fold_test_and(ir_node *node)
2482 const ir_edge_t *edge;
2484 /** we can only have eq and lg projs */
2485 foreach_out_edge(node, edge) {
2486 ir_node *proj = get_edge_src_irn(edge);
2487 pn_Cmp pnc = get_Proj_proj(proj);
2488 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2495 static ir_node *gen_Cmp(ir_node *node)
2497 ir_graph *irg = current_ir_graph;
2498 dbg_info *dbgi = get_irn_dbg_info(node);
2499 ir_node *block = get_nodes_block(node);
2500 ir_node *new_block = be_transform_node(block);
2501 ir_node *left = get_Cmp_left(node);
2502 ir_node *right = get_Cmp_right(node);
2503 ir_mode *cmp_mode = get_irn_mode(left);
2505 ia32_address_mode_t am;
2506 ia32_address_t *addr = &am.addr;
2509 if(mode_is_float(cmp_mode)) {
2510 if (ia32_cg_config.use_sse2) {
2511 return create_Ucomi(node);
2513 return create_Fucom(node);
2517 assert(mode_needs_gp_reg(cmp_mode));
2519 /* we prefer the Test instruction where possible except cases where
2520 * we can use SourceAM */
2521 cmp_unsigned = !mode_is_signed(cmp_mode);
2522 if (is_Const_0(right)) {
2524 get_irn_n_edges(left) == 1 &&
2525 can_fold_test_and(node)) {
2526 /* Test(and_left, and_right) */
2527 ir_node *and_left = get_And_left(left);
2528 ir_node *and_right = get_And_right(left);
2529 ir_mode *mode = get_irn_mode(and_left);
2531 match_arguments(&am, block, and_left, and_right, NULL,
2533 match_am | match_8bit_am | match_16bit_am |
2534 match_am_and_immediates | match_immediate |
2535 match_8bit | match_16bit);
2536 if (get_mode_size_bits(mode) == 8) {
2537 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2538 addr->index, addr->mem, am.new_op1,
2539 am.new_op2, am.ins_permuted,
2542 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2543 addr->index, addr->mem, am.new_op1,
2544 am.new_op2, am.ins_permuted, cmp_unsigned);
2547 match_arguments(&am, block, NULL, left, NULL,
2548 match_am | match_8bit_am | match_16bit_am |
2549 match_8bit | match_16bit);
2550 if (am.op_type == ia32_AddrModeS) {
2552 ir_node *imm_zero = try_create_Immediate(right, 0);
2553 if (get_mode_size_bits(cmp_mode) == 8) {
2554 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2555 addr->index, addr->mem, am.new_op2,
2556 imm_zero, am.ins_permuted,
2559 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2560 addr->index, addr->mem, am.new_op2,
2561 imm_zero, am.ins_permuted, cmp_unsigned);
2564 /* Test(left, left) */
2565 if (get_mode_size_bits(cmp_mode) == 8) {
2566 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2567 addr->index, addr->mem, am.new_op2,
2568 am.new_op2, am.ins_permuted,
2571 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2572 addr->index, addr->mem, am.new_op2,
2573 am.new_op2, am.ins_permuted,
2579 /* Cmp(left, right) */
2580 match_arguments(&am, block, left, right, NULL,
2581 match_commutative | match_am | match_8bit_am |
2582 match_16bit_am | match_am_and_immediates |
2583 match_immediate | match_8bit | match_16bit);
2584 if (get_mode_size_bits(cmp_mode) == 8) {
2585 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2586 addr->index, addr->mem, am.new_op1,
2587 am.new_op2, am.ins_permuted,
2590 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2591 addr->index, addr->mem, am.new_op1,
2592 am.new_op2, am.ins_permuted, cmp_unsigned);
2595 set_am_attributes(new_node, &am);
2596 assert(cmp_mode != NULL);
2597 set_ia32_ls_mode(new_node, cmp_mode);
2599 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2601 new_node = fix_mem_proj(new_node, &am);
2606 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2609 ir_graph *irg = current_ir_graph;
2610 dbg_info *dbgi = get_irn_dbg_info(node);
2611 ir_node *block = get_nodes_block(node);
2612 ir_node *new_block = be_transform_node(block);
2613 ir_node *val_true = get_Psi_val(node, 0);
2614 ir_node *val_false = get_Psi_default(node);
2616 match_flags_t match_flags;
2617 ia32_address_mode_t am;
2618 ia32_address_t *addr;
2620 assert(ia32_cg_config.use_cmov);
2621 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2625 match_flags = match_commutative | match_am | match_16bit_am |
2628 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2630 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2631 addr->mem, am.new_op1, am.new_op2, new_flags,
2632 am.ins_permuted, pnc);
2633 set_am_attributes(new_node, &am);
2635 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2637 new_node = fix_mem_proj(new_node, &am);
2644 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2645 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2648 ir_graph *irg = current_ir_graph;
2649 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2650 ir_node *nomem = new_NoMem();
2651 ir_mode *mode = get_irn_mode(orig_node);
2654 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2655 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2657 /* we might need to conv the result up */
2658 if(get_mode_size_bits(mode) > 8) {
2659 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2660 nomem, new_node, mode_Bu);
2661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2668 * Transforms a Psi node into CMov.
2670 * @return The transformed node.
2672 static ir_node *gen_Psi(ir_node *node)
2674 dbg_info *dbgi = get_irn_dbg_info(node);
2675 ir_node *block = get_nodes_block(node);
2676 ir_node *new_block = be_transform_node(block);
2677 ir_node *psi_true = get_Psi_val(node, 0);
2678 ir_node *psi_default = get_Psi_default(node);
2679 ir_node *cond = get_Psi_cond(node, 0);
2680 ir_node *flags = NULL;
2684 assert(get_Psi_n_conds(node) == 1);
2685 assert(get_irn_mode(cond) == mode_b);
2686 assert(mode_needs_gp_reg(get_irn_mode(node)));
2688 flags = get_flags_node(cond, &pnc);
2690 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2691 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2692 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2693 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2695 new_node = create_CMov(node, cond, flags, pnc);
2702 * Create a conversion from x87 state register to general purpose.
2704 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2705 ir_node *block = be_transform_node(get_nodes_block(node));
2706 ir_node *op = get_Conv_op(node);
2707 ir_node *new_op = be_transform_node(op);
2708 ia32_code_gen_t *cg = env_cg;
2709 ir_graph *irg = current_ir_graph;
2710 dbg_info *dbgi = get_irn_dbg_info(node);
2711 ir_node *noreg = ia32_new_NoReg_gp(cg);
2712 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2713 ir_mode *mode = get_irn_mode(node);
2714 ir_node *fist, *load;
2717 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2718 new_NoMem(), new_op, trunc_mode);
2720 set_irn_pinned(fist, op_pin_state_floats);
2721 set_ia32_use_frame(fist);
2722 set_ia32_op_type(fist, ia32_AddrModeD);
2724 assert(get_mode_size_bits(mode) <= 32);
2725 /* exception we can only store signed 32 bit integers, so for unsigned
2726 we store a 64bit (signed) integer and load the lower bits */
2727 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2728 set_ia32_ls_mode(fist, mode_Ls);
2730 set_ia32_ls_mode(fist, mode_Is);
2732 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2735 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2737 set_irn_pinned(load, op_pin_state_floats);
2738 set_ia32_use_frame(load);
2739 set_ia32_op_type(load, ia32_AddrModeS);
2740 set_ia32_ls_mode(load, mode_Is);
2741 if(get_ia32_ls_mode(fist) == mode_Ls) {
2742 ia32_attr_t *attr = get_ia32_attr(load);
2743 attr->data.need_64bit_stackent = 1;
2745 ia32_attr_t *attr = get_ia32_attr(load);
2746 attr->data.need_32bit_stackent = 1;
2748 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2750 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2754 * Creates a x87 strict Conv by placing a Sore and a Load
2756 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2758 ir_node *block = get_nodes_block(node);
2759 ir_graph *irg = current_ir_graph;
2760 dbg_info *dbgi = get_irn_dbg_info(node);
2761 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2762 ir_node *nomem = new_NoMem();
2763 ir_node *frame = get_irg_frame(irg);
2764 ir_node *store, *load;
2767 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2769 set_ia32_use_frame(store);
2770 set_ia32_op_type(store, ia32_AddrModeD);
2771 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2773 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2775 set_ia32_use_frame(load);
2776 set_ia32_op_type(load, ia32_AddrModeS);
2777 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2779 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2783 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2785 ir_graph *irg = current_ir_graph;
2786 ir_node *start_block = get_irg_start_block(irg);
2787 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2788 symconst, symconst_sign, val);
2789 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2795 * Create a conversion from general purpose to x87 register
2797 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2798 ir_node *src_block = get_nodes_block(node);
2799 ir_node *block = be_transform_node(src_block);
2800 ir_graph *irg = current_ir_graph;
2801 dbg_info *dbgi = get_irn_dbg_info(node);
2802 ir_node *op = get_Conv_op(node);
2803 ir_node *new_op = NULL;
2807 ir_mode *store_mode;
2813 /* fild can use source AM if the operand is a signed 32bit integer */
2814 if (src_mode == mode_Is) {
2815 ia32_address_mode_t am;
2817 match_arguments(&am, src_block, NULL, op, NULL,
2818 match_am | match_try_am);
2819 if (am.op_type == ia32_AddrModeS) {
2820 ia32_address_t *addr = &am.addr;
2822 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2823 addr->index, addr->mem);
2824 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2827 set_am_attributes(fild, &am);
2828 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2830 fix_mem_proj(fild, &am);
2835 if(new_op == NULL) {
2836 new_op = be_transform_node(op);
2839 noreg = ia32_new_NoReg_gp(env_cg);
2840 nomem = new_NoMem();
2841 mode = get_irn_mode(op);
2843 /* first convert to 32 bit signed if necessary */
2844 src_bits = get_mode_size_bits(src_mode);
2845 if (src_bits == 8) {
2846 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2848 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2850 } else if (src_bits < 32) {
2851 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2853 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2857 assert(get_mode_size_bits(mode) == 32);
2860 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2863 set_ia32_use_frame(store);
2864 set_ia32_op_type(store, ia32_AddrModeD);
2865 set_ia32_ls_mode(store, mode_Iu);
2867 /* exception for 32bit unsigned, do a 64bit spill+load */
2868 if(!mode_is_signed(mode)) {
2871 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2873 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2874 get_irg_frame(irg), noreg, nomem,
2877 set_ia32_use_frame(zero_store);
2878 set_ia32_op_type(zero_store, ia32_AddrModeD);
2879 add_ia32_am_offs_int(zero_store, 4);
2880 set_ia32_ls_mode(zero_store, mode_Iu);
2885 store = new_rd_Sync(dbgi, irg, block, 2, in);
2886 store_mode = mode_Ls;
2888 store_mode = mode_Is;
2892 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2894 set_ia32_use_frame(fild);
2895 set_ia32_op_type(fild, ia32_AddrModeS);
2896 set_ia32_ls_mode(fild, store_mode);
2898 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2904 * Create a conversion from one integer mode into another one
2906 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2907 dbg_info *dbgi, ir_node *block, ir_node *op,
2910 ir_graph *irg = current_ir_graph;
2911 int src_bits = get_mode_size_bits(src_mode);
2912 int tgt_bits = get_mode_size_bits(tgt_mode);
2913 ir_node *new_block = be_transform_node(block);
2915 ir_mode *smaller_mode;
2917 ia32_address_mode_t am;
2918 ia32_address_t *addr = &am.addr;
2921 if (src_bits < tgt_bits) {
2922 smaller_mode = src_mode;
2923 smaller_bits = src_bits;
2925 smaller_mode = tgt_mode;
2926 smaller_bits = tgt_bits;
2929 #ifdef DEBUG_libfirm
2931 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2936 match_arguments(&am, block, NULL, op, NULL,
2937 match_8bit | match_16bit |
2938 match_am | match_8bit_am | match_16bit_am);
2939 if (smaller_bits == 8) {
2940 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2941 addr->index, addr->mem, am.new_op2,
2944 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2945 addr->index, addr->mem, am.new_op2,
2948 set_am_attributes(new_node, &am);
2949 /* match_arguments assume that out-mode = in-mode, this isn't true here
2951 set_ia32_ls_mode(new_node, smaller_mode);
2952 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2953 new_node = fix_mem_proj(new_node, &am);
2958 * Transforms a Conv node.
2960 * @return The created ia32 Conv node
2962 static ir_node *gen_Conv(ir_node *node) {
2963 ir_node *block = get_nodes_block(node);
2964 ir_node *new_block = be_transform_node(block);
2965 ir_node *op = get_Conv_op(node);
2966 ir_node *new_op = NULL;
2967 ir_graph *irg = current_ir_graph;
2968 dbg_info *dbgi = get_irn_dbg_info(node);
2969 ir_mode *src_mode = get_irn_mode(op);
2970 ir_mode *tgt_mode = get_irn_mode(node);
2971 int src_bits = get_mode_size_bits(src_mode);
2972 int tgt_bits = get_mode_size_bits(tgt_mode);
2973 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2974 ir_node *nomem = new_rd_NoMem(irg);
2975 ir_node *res = NULL;
2977 if (src_mode == mode_b) {
2978 assert(mode_is_int(tgt_mode));
2979 /* nothing to do, we already model bools as 0/1 ints */
2980 return be_transform_node(op);
2983 if (src_mode == tgt_mode) {
2984 if (get_Conv_strict(node)) {
2985 if (ia32_cg_config.use_sse2) {
2986 /* when we are in SSE mode, we can kill all strict no-op conversion */
2987 return be_transform_node(op);
2990 /* this should be optimized already, but who knows... */
2991 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2992 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2993 return be_transform_node(op);
2997 if (mode_is_float(src_mode)) {
2998 new_op = be_transform_node(op);
2999 /* we convert from float ... */
3000 if (mode_is_float(tgt_mode)) {
3001 if(src_mode == mode_E && tgt_mode == mode_D
3002 && !get_Conv_strict(node)) {
3003 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3008 if (ia32_cg_config.use_sse2) {
3009 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3010 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3012 set_ia32_ls_mode(res, tgt_mode);
3014 if(get_Conv_strict(node)) {
3015 res = gen_x87_strict_conv(tgt_mode, new_op);
3016 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3019 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3024 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3025 if (ia32_cg_config.use_sse2) {
3026 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3028 set_ia32_ls_mode(res, src_mode);
3030 return gen_x87_fp_to_gp(node);
3034 /* we convert from int ... */
3035 if (mode_is_float(tgt_mode)) {
3037 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3038 if (ia32_cg_config.use_sse2) {
3039 new_op = be_transform_node(op);
3040 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3042 set_ia32_ls_mode(res, tgt_mode);
3044 res = gen_x87_gp_to_fp(node, src_mode);
3045 if(get_Conv_strict(node)) {
3046 res = gen_x87_strict_conv(tgt_mode, res);
3047 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3048 ia32_get_old_node_name(env_cg, node));
3052 } else if(tgt_mode == mode_b) {
3053 /* mode_b lowering already took care that we only have 0/1 values */
3054 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3055 src_mode, tgt_mode));
3056 return be_transform_node(op);
3059 if (src_bits == tgt_bits) {
3060 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3061 src_mode, tgt_mode));
3062 return be_transform_node(op);
3065 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3073 static int check_immediate_constraint(long val, char immediate_constraint_type)
3075 switch (immediate_constraint_type) {
3079 return val >= 0 && val <= 32;
3081 return val >= 0 && val <= 63;
3083 return val >= -128 && val <= 127;
3085 return val == 0xff || val == 0xffff;
3087 return val >= 0 && val <= 3;
3089 return val >= 0 && val <= 255;
3091 return val >= 0 && val <= 127;
3095 panic("Invalid immediate constraint found");
3099 static ir_node *try_create_Immediate(ir_node *node,
3100 char immediate_constraint_type)
3103 tarval *offset = NULL;
3104 int offset_sign = 0;
3106 ir_entity *symconst_ent = NULL;
3107 int symconst_sign = 0;
3109 ir_node *cnst = NULL;
3110 ir_node *symconst = NULL;
3113 mode = get_irn_mode(node);
3114 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3118 if(is_Minus(node)) {
3120 node = get_Minus_op(node);
3123 if(is_Const(node)) {
3126 offset_sign = minus;
3127 } else if(is_SymConst(node)) {
3130 symconst_sign = minus;
3131 } else if(is_Add(node)) {
3132 ir_node *left = get_Add_left(node);
3133 ir_node *right = get_Add_right(node);
3134 if(is_Const(left) && is_SymConst(right)) {
3137 symconst_sign = minus;
3138 offset_sign = minus;
3139 } else if(is_SymConst(left) && is_Const(right)) {
3142 symconst_sign = minus;
3143 offset_sign = minus;
3145 } else if(is_Sub(node)) {
3146 ir_node *left = get_Sub_left(node);
3147 ir_node *right = get_Sub_right(node);
3148 if(is_Const(left) && is_SymConst(right)) {
3151 symconst_sign = !minus;
3152 offset_sign = minus;
3153 } else if(is_SymConst(left) && is_Const(right)) {
3156 symconst_sign = minus;
3157 offset_sign = !minus;
3164 offset = get_Const_tarval(cnst);
3165 if(tarval_is_long(offset)) {
3166 val = get_tarval_long(offset);
3168 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3173 if(!check_immediate_constraint(val, immediate_constraint_type))
3176 if(symconst != NULL) {
3177 if(immediate_constraint_type != 0) {
3178 /* we need full 32bits for symconsts */
3182 /* unfortunately the assembler/linker doesn't support -symconst */
3186 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3188 symconst_ent = get_SymConst_entity(symconst);
3190 if(cnst == NULL && symconst == NULL)
3193 if(offset_sign && offset != NULL) {
3194 offset = tarval_neg(offset);
3197 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3202 static ir_node *create_immediate_or_transform(ir_node *node,
3203 char immediate_constraint_type)
3205 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3206 if (new_node == NULL) {
3207 new_node = be_transform_node(node);
3212 static const arch_register_req_t no_register_req = {
3213 arch_register_req_type_none,
3214 NULL, /* regclass */
3215 NULL, /* limit bitset */
3217 0 /* different pos */
3221 * An assembler constraint.
3223 typedef struct constraint_t constraint_t;
3224 struct constraint_t {
3227 const arch_register_req_t **out_reqs;
3229 const arch_register_req_t *req;
3230 unsigned immediate_possible;
3231 char immediate_type;
3234 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3236 int immediate_possible = 0;
3237 char immediate_type = 0;
3238 unsigned limited = 0;
3239 const arch_register_class_t *cls = NULL;
3240 ir_graph *irg = current_ir_graph;
3241 struct obstack *obst = get_irg_obstack(irg);
3242 arch_register_req_t *req;
3243 unsigned *limited_ptr = NULL;
3247 /* TODO: replace all the asserts with nice error messages */
3250 /* a memory constraint: no need to do anything in backend about it
3251 * (the dependencies are already respected by the memory edge of
3253 constraint->req = &no_register_req;
3265 assert(cls == NULL ||
3266 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3267 cls = &ia32_reg_classes[CLASS_ia32_gp];
3268 limited |= 1 << REG_EAX;
3271 assert(cls == NULL ||
3272 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3273 cls = &ia32_reg_classes[CLASS_ia32_gp];
3274 limited |= 1 << REG_EBX;
3277 assert(cls == NULL ||
3278 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3279 cls = &ia32_reg_classes[CLASS_ia32_gp];
3280 limited |= 1 << REG_ECX;
3283 assert(cls == NULL ||
3284 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3285 cls = &ia32_reg_classes[CLASS_ia32_gp];
3286 limited |= 1 << REG_EDX;
3289 assert(cls == NULL ||
3290 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3291 cls = &ia32_reg_classes[CLASS_ia32_gp];
3292 limited |= 1 << REG_EDI;
3295 assert(cls == NULL ||
3296 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3297 cls = &ia32_reg_classes[CLASS_ia32_gp];
3298 limited |= 1 << REG_ESI;
3301 case 'q': /* q means lower part of the regs only, this makes no
3302 * difference to Q for us (we only assigne whole registers) */
3303 assert(cls == NULL ||
3304 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3305 cls = &ia32_reg_classes[CLASS_ia32_gp];
3306 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3310 assert(cls == NULL ||
3311 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3312 cls = &ia32_reg_classes[CLASS_ia32_gp];
3313 limited |= 1 << REG_EAX | 1 << REG_EDX;
3316 assert(cls == NULL ||
3317 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3318 cls = &ia32_reg_classes[CLASS_ia32_gp];
3319 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3320 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3327 assert(cls == NULL);
3328 cls = &ia32_reg_classes[CLASS_ia32_gp];
3334 /* TODO: mark values so the x87 simulator knows about t and u */
3335 assert(cls == NULL);
3336 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3341 assert(cls == NULL);
3342 /* TODO: check that sse2 is supported */
3343 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3353 assert(!immediate_possible);
3354 immediate_possible = 1;
3355 immediate_type = *c;
3359 assert(!immediate_possible);
3360 immediate_possible = 1;
3364 assert(!immediate_possible && cls == NULL);
3365 immediate_possible = 1;
3366 cls = &ia32_reg_classes[CLASS_ia32_gp];
3379 assert(constraint->is_in && "can only specify same constraint "
3382 sscanf(c, "%d%n", &same_as, &p);
3390 /* memory constraint no need to do anything in backend about it
3391 * (the dependencies are already respected by the memory edge of
3393 constraint->req = &no_register_req;
3396 case 'E': /* no float consts yet */
3397 case 'F': /* no float consts yet */
3398 case 's': /* makes no sense on x86 */
3399 case 'X': /* we can't support that in firm */
3402 case '<': /* no autodecrement on x86 */
3403 case '>': /* no autoincrement on x86 */
3404 case 'C': /* sse constant not supported yet */
3405 case 'G': /* 80387 constant not supported yet */
3406 case 'y': /* we don't support mmx registers yet */
3407 case 'Z': /* not available in 32 bit mode */
3408 case 'e': /* not available in 32 bit mode */
3409 panic("unsupported asm constraint '%c' found in (%+F)",
3410 *c, current_ir_graph);
3413 panic("unknown asm constraint '%c' found in (%+F)", *c,
3421 const arch_register_req_t *other_constr;
3423 assert(cls == NULL && "same as and register constraint not supported");
3424 assert(!immediate_possible && "same as and immediate constraint not "
3426 assert(same_as < constraint->n_outs && "wrong constraint number in "
3427 "same_as constraint");
3429 other_constr = constraint->out_reqs[same_as];
3431 req = obstack_alloc(obst, sizeof(req[0]));
3432 req->cls = other_constr->cls;
3433 req->type = arch_register_req_type_should_be_same;
3434 req->limited = NULL;
3435 req->other_same = 1U << pos;
3436 req->other_different = 0;
3438 /* switch constraints. This is because in firm we have same_as
3439 * constraints on the output constraints while in the gcc asm syntax
3440 * they are specified on the input constraints */
3441 constraint->req = other_constr;
3442 constraint->out_reqs[same_as] = req;
3443 constraint->immediate_possible = 0;
3447 if(immediate_possible && cls == NULL) {
3448 cls = &ia32_reg_classes[CLASS_ia32_gp];
3450 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3451 assert(cls != NULL);
3453 if(immediate_possible) {
3454 assert(constraint->is_in
3455 && "immediate make no sense for output constraints");
3457 /* todo: check types (no float input on 'r' constrained in and such... */
3460 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3461 limited_ptr = (unsigned*) (req+1);
3463 req = obstack_alloc(obst, sizeof(req[0]));
3465 memset(req, 0, sizeof(req[0]));
3468 req->type = arch_register_req_type_limited;
3469 *limited_ptr = limited;
3470 req->limited = limited_ptr;
3472 req->type = arch_register_req_type_normal;
3476 constraint->req = req;
3477 constraint->immediate_possible = immediate_possible;
3478 constraint->immediate_type = immediate_type;
3481 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3488 panic("Clobbers not supported yet");
3491 static int is_memory_op(const ir_asm_constraint *constraint)
3493 ident *id = constraint->constraint;
3494 const char *str = get_id_str(id);
3497 for(c = str; *c != '\0'; ++c) {
3506 * generates code for a ASM node
3508 static ir_node *gen_ASM(ir_node *node)
3511 ir_graph *irg = current_ir_graph;
3512 ir_node *block = get_nodes_block(node);
3513 ir_node *new_block = be_transform_node(block);
3514 dbg_info *dbgi = get_irn_dbg_info(node);
3518 int n_out_constraints;
3520 const arch_register_req_t **out_reg_reqs;
3521 const arch_register_req_t **in_reg_reqs;
3522 ia32_asm_reg_t *register_map;
3523 unsigned reg_map_size = 0;
3524 struct obstack *obst;
3525 const ir_asm_constraint *in_constraints;
3526 const ir_asm_constraint *out_constraints;
3528 constraint_t parsed_constraint;
3530 arity = get_irn_arity(node);
3531 in = alloca(arity * sizeof(in[0]));
3532 memset(in, 0, arity * sizeof(in[0]));
3534 n_out_constraints = get_ASM_n_output_constraints(node);
3535 n_clobbers = get_ASM_n_clobbers(node);
3536 out_arity = n_out_constraints + n_clobbers;
3538 in_constraints = get_ASM_input_constraints(node);
3539 out_constraints = get_ASM_output_constraints(node);
3540 clobbers = get_ASM_clobbers(node);
3542 /* construct output constraints */
3543 obst = get_irg_obstack(irg);
3544 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3545 parsed_constraint.out_reqs = out_reg_reqs;
3546 parsed_constraint.n_outs = n_out_constraints;
3547 parsed_constraint.is_in = 0;
3549 for(i = 0; i < out_arity; ++i) {
3552 if(i < n_out_constraints) {
3553 const ir_asm_constraint *constraint = &out_constraints[i];
3554 c = get_id_str(constraint->constraint);
3555 parse_asm_constraint(i, &parsed_constraint, c);
3557 if(constraint->pos > reg_map_size)
3558 reg_map_size = constraint->pos;
3560 ident *glob_id = clobbers [i - n_out_constraints];
3561 c = get_id_str(glob_id);
3562 parse_clobber(node, i, &parsed_constraint, c);
3565 out_reg_reqs[i] = parsed_constraint.req;
3568 /* construct input constraints */
3569 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3570 parsed_constraint.is_in = 1;
3571 for(i = 0; i < arity; ++i) {
3572 const ir_asm_constraint *constraint = &in_constraints[i];
3573 ident *constr_id = constraint->constraint;
3574 const char *c = get_id_str(constr_id);
3576 parse_asm_constraint(i, &parsed_constraint, c);
3577 in_reg_reqs[i] = parsed_constraint.req;
3579 if(constraint->pos > reg_map_size)
3580 reg_map_size = constraint->pos;
3582 if(parsed_constraint.immediate_possible) {
3583 ir_node *pred = get_irn_n(node, i);
3584 char imm_type = parsed_constraint.immediate_type;
3585 ir_node *immediate = try_create_Immediate(pred, imm_type);
3587 if(immediate != NULL) {
3594 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3595 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3597 for(i = 0; i < n_out_constraints; ++i) {
3598 const ir_asm_constraint *constraint = &out_constraints[i];
3599 unsigned pos = constraint->pos;
3601 assert(pos < reg_map_size);
3602 register_map[pos].use_input = 0;
3603 register_map[pos].valid = 1;
3604 register_map[pos].memory = is_memory_op(constraint);
3605 register_map[pos].inout_pos = i;
3606 register_map[pos].mode = constraint->mode;
3609 /* transform inputs */
3610 for(i = 0; i < arity; ++i) {
3611 const ir_asm_constraint *constraint = &in_constraints[i];
3612 unsigned pos = constraint->pos;
3613 ir_node *pred = get_irn_n(node, i);
3614 ir_node *transformed;
3616 assert(pos < reg_map_size);
3617 register_map[pos].use_input = 1;
3618 register_map[pos].valid = 1;
3619 register_map[pos].memory = is_memory_op(constraint);
3620 register_map[pos].inout_pos = i;
3621 register_map[pos].mode = constraint->mode;
3626 transformed = be_transform_node(pred);
3627 in[i] = transformed;
3630 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3631 get_ASM_text(node), register_map);
3633 set_ia32_out_req_all(new_node, out_reg_reqs);
3634 set_ia32_in_req_all(new_node, in_reg_reqs);
3636 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3642 * Transforms a FrameAddr into an ia32 Add.
3644 static ir_node *gen_be_FrameAddr(ir_node *node) {
3645 ir_node *block = be_transform_node(get_nodes_block(node));
3646 ir_node *op = be_get_FrameAddr_frame(node);
3647 ir_node *new_op = be_transform_node(op);
3648 ir_graph *irg = current_ir_graph;
3649 dbg_info *dbgi = get_irn_dbg_info(node);
3650 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3653 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3654 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3655 set_ia32_use_frame(new_node);
3657 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3663 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3665 static ir_node *gen_be_Return(ir_node *node) {
3666 ir_graph *irg = current_ir_graph;
3667 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3668 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3669 ir_entity *ent = get_irg_entity(irg);
3670 ir_type *tp = get_entity_type(ent);
3675 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3676 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3679 int pn_ret_val, pn_ret_mem, arity, i;
3681 assert(ret_val != NULL);
3682 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3683 return be_duplicate_node(node);
3686 res_type = get_method_res_type(tp, 0);
3688 if (! is_Primitive_type(res_type)) {
3689 return be_duplicate_node(node);
3692 mode = get_type_mode(res_type);
3693 if (! mode_is_float(mode)) {
3694 return be_duplicate_node(node);
3697 assert(get_method_n_ress(tp) == 1);
3699 pn_ret_val = get_Proj_proj(ret_val);
3700 pn_ret_mem = get_Proj_proj(ret_mem);
3702 /* get the Barrier */
3703 barrier = get_Proj_pred(ret_val);
3705 /* get result input of the Barrier */
3706 ret_val = get_irn_n(barrier, pn_ret_val);
3707 new_ret_val = be_transform_node(ret_val);
3709 /* get memory input of the Barrier */
3710 ret_mem = get_irn_n(barrier, pn_ret_mem);
3711 new_ret_mem = be_transform_node(ret_mem);
3713 frame = get_irg_frame(irg);
3715 dbgi = get_irn_dbg_info(barrier);
3716 block = be_transform_node(get_nodes_block(barrier));
3718 noreg = ia32_new_NoReg_gp(env_cg);
3720 /* store xmm0 onto stack */
3721 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3722 new_ret_mem, new_ret_val);
3723 set_ia32_ls_mode(sse_store, mode);
3724 set_ia32_op_type(sse_store, ia32_AddrModeD);
3725 set_ia32_use_frame(sse_store);
3727 /* load into x87 register */
3728 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3729 set_ia32_op_type(fld, ia32_AddrModeS);
3730 set_ia32_use_frame(fld);
3732 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3733 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3735 /* create a new barrier */
3736 arity = get_irn_arity(barrier);
3737 in = alloca(arity * sizeof(in[0]));
3738 for (i = 0; i < arity; ++i) {
3741 if (i == pn_ret_val) {
3743 } else if (i == pn_ret_mem) {
3746 ir_node *in = get_irn_n(barrier, i);
3747 new_in = be_transform_node(in);
3752 new_barrier = new_ir_node(dbgi, irg, block,
3753 get_irn_op(barrier), get_irn_mode(barrier),
3755 copy_node_attr(barrier, new_barrier);
3756 be_duplicate_deps(barrier, new_barrier);
3757 be_set_transformed_node(barrier, new_barrier);
3758 mark_irn_visited(barrier);
3760 /* transform normally */
3761 return be_duplicate_node(node);
3765 * Transform a be_AddSP into an ia32_SubSP.
3767 static ir_node *gen_be_AddSP(ir_node *node)
3769 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3770 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3772 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3776 * Transform a be_SubSP into an ia32_AddSP
3778 static ir_node *gen_be_SubSP(ir_node *node)
3780 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3781 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3783 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3787 * This function just sets the register for the Unknown node
3788 * as this is not done during register allocation because Unknown
3789 * is an "ignore" node.
3791 static ir_node *gen_Unknown(ir_node *node) {
3792 ir_mode *mode = get_irn_mode(node);
3794 if (mode_is_float(mode)) {
3795 if (ia32_cg_config.use_sse2) {
3796 return ia32_new_Unknown_xmm(env_cg);
3798 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3799 ir_graph *irg = current_ir_graph;
3800 dbg_info *dbgi = get_irn_dbg_info(node);
3801 ir_node *block = get_irg_start_block(irg);
3802 return new_rd_ia32_vfldz(dbgi, irg, block);
3804 } else if (mode_needs_gp_reg(mode)) {
3805 return ia32_new_Unknown_gp(env_cg);
3807 panic("unsupported Unknown-Mode");
3813 * Change some phi modes
3815 static ir_node *gen_Phi(ir_node *node) {
3816 ir_node *block = be_transform_node(get_nodes_block(node));
3817 ir_graph *irg = current_ir_graph;
3818 dbg_info *dbgi = get_irn_dbg_info(node);
3819 ir_mode *mode = get_irn_mode(node);
3822 if(mode_needs_gp_reg(mode)) {
3823 /* we shouldn't have any 64bit stuff around anymore */
3824 assert(get_mode_size_bits(mode) <= 32);
3825 /* all integer operations are on 32bit registers now */
3827 } else if(mode_is_float(mode)) {
3828 if (ia32_cg_config.use_sse2) {
3835 /* phi nodes allow loops, so we use the old arguments for now
3836 * and fix this later */
3837 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3838 get_irn_in(node) + 1);
3839 copy_node_attr(node, phi);
3840 be_duplicate_deps(node, phi);
3842 be_set_transformed_node(node, phi);
3843 be_enqueue_preds(node);
3851 static ir_node *gen_IJmp(ir_node *node)
3853 ir_node *block = get_nodes_block(node);
3854 ir_node *new_block = be_transform_node(block);
3855 ir_graph *irg = current_ir_graph;
3856 dbg_info *dbgi = get_irn_dbg_info(node);
3857 ir_node *op = get_IJmp_target(node);
3859 ia32_address_mode_t am;
3860 ia32_address_t *addr = &am.addr;
3862 assert(get_irn_mode(op) == mode_P);
3864 match_arguments(&am, block, NULL, op, NULL,
3865 match_am | match_8bit_am | match_16bit_am |
3866 match_immediate | match_8bit | match_16bit);
3868 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3869 addr->mem, am.new_op2);
3870 set_am_attributes(new_node, &am);
3871 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3873 new_node = fix_mem_proj(new_node, &am);
3878 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3881 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3882 ir_node *val, ir_node *mem);
3885 * Transforms a lowered Load into a "real" one.
3887 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3889 ir_node *block = be_transform_node(get_nodes_block(node));
3890 ir_node *ptr = get_irn_n(node, 0);
3891 ir_node *new_ptr = be_transform_node(ptr);
3892 ir_node *mem = get_irn_n(node, 1);
3893 ir_node *new_mem = be_transform_node(mem);
3894 ir_graph *irg = current_ir_graph;
3895 dbg_info *dbgi = get_irn_dbg_info(node);
3896 ir_mode *mode = get_ia32_ls_mode(node);
3897 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3900 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3902 set_ia32_op_type(new_op, ia32_AddrModeS);
3903 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3904 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3905 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3906 if (is_ia32_am_sc_sign(node))
3907 set_ia32_am_sc_sign(new_op);
3908 set_ia32_ls_mode(new_op, mode);
3909 if (is_ia32_use_frame(node)) {
3910 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3911 set_ia32_use_frame(new_op);
3914 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3920 * Transforms a lowered Store into a "real" one.
3922 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3924 ir_node *block = be_transform_node(get_nodes_block(node));
3925 ir_node *ptr = get_irn_n(node, 0);
3926 ir_node *new_ptr = be_transform_node(ptr);
3927 ir_node *val = get_irn_n(node, 1);
3928 ir_node *new_val = be_transform_node(val);
3929 ir_node *mem = get_irn_n(node, 2);
3930 ir_node *new_mem = be_transform_node(mem);
3931 ir_graph *irg = current_ir_graph;
3932 dbg_info *dbgi = get_irn_dbg_info(node);
3933 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3934 ir_mode *mode = get_ia32_ls_mode(node);
3938 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3940 am_offs = get_ia32_am_offs_int(node);
3941 add_ia32_am_offs_int(new_op, am_offs);
3943 set_ia32_op_type(new_op, ia32_AddrModeD);
3944 set_ia32_ls_mode(new_op, mode);
3945 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3946 set_ia32_use_frame(new_op);
3948 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3953 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3955 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3956 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3958 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3959 match_immediate | match_mode_neutral);
3962 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3964 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
3965 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
3966 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3970 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3972 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
3973 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
3974 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3978 static ir_node *gen_ia32_l_Add(ir_node *node) {
3979 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3980 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3981 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3982 match_commutative | match_am | match_immediate |
3983 match_mode_neutral);
3985 if(is_Proj(lowered)) {
3986 lowered = get_Proj_pred(lowered);
3988 assert(is_ia32_Add(lowered));
3989 set_irn_mode(lowered, mode_T);
3995 static ir_node *gen_ia32_l_Adc(ir_node *node)
3997 return gen_binop_flags(node, new_rd_ia32_Adc,
3998 match_commutative | match_am | match_immediate |
3999 match_mode_neutral);
4003 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
4005 * @param node The node to transform
4006 * @return the created ia32 vfild node
4008 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4009 return gen_lowered_Load(node, new_rd_ia32_vfild);
4013 * Transforms an ia32_l_Load into a "real" ia32_Load node
4015 * @param node The node to transform
4016 * @return the created ia32 Load node
4018 static ir_node *gen_ia32_l_Load(ir_node *node) {
4019 return gen_lowered_Load(node, new_rd_ia32_Load);
4023 * Transforms an ia32_l_Store into a "real" ia32_Store node
4025 * @param node The node to transform
4026 * @return the created ia32 Store node
4028 static ir_node *gen_ia32_l_Store(ir_node *node) {
4029 return gen_lowered_Store(node, new_rd_ia32_Store);
4033 * Transforms a l_vfist into a "real" vfist node.
4035 * @param node The node to transform
4036 * @return the created ia32 vfist node
4038 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4039 ir_node *block = be_transform_node(get_nodes_block(node));
4040 ir_node *ptr = get_irn_n(node, 0);
4041 ir_node *new_ptr = be_transform_node(ptr);
4042 ir_node *val = get_irn_n(node, 1);
4043 ir_node *new_val = be_transform_node(val);
4044 ir_node *mem = get_irn_n(node, 2);
4045 ir_node *new_mem = be_transform_node(mem);
4046 ir_graph *irg = current_ir_graph;
4047 dbg_info *dbgi = get_irn_dbg_info(node);
4048 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4049 ir_mode *mode = get_ia32_ls_mode(node);
4050 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4054 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4055 new_val, trunc_mode);
4057 am_offs = get_ia32_am_offs_int(node);
4058 add_ia32_am_offs_int(new_op, am_offs);
4060 set_ia32_op_type(new_op, ia32_AddrModeD);
4061 set_ia32_ls_mode(new_op, mode);
4062 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4063 set_ia32_use_frame(new_op);
4065 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4071 * Transforms a l_MulS into a "real" MulS node.
4073 * @return the created ia32 Mul node
4075 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4076 ir_node *left = get_binop_left(node);
4077 ir_node *right = get_binop_right(node);
4079 return gen_binop(node, left, right, new_rd_ia32_Mul,
4080 match_commutative | match_am | match_mode_neutral);
4084 * Transforms a l_IMulS into a "real" IMul1OPS node.
4086 * @return the created ia32 IMul1OP node
4088 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4089 ir_node *left = get_binop_left(node);
4090 ir_node *right = get_binop_right(node);
4092 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4093 match_commutative | match_am | match_mode_neutral);
4096 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4097 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4098 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4099 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4100 match_am | match_immediate | match_mode_neutral);
4102 if(is_Proj(lowered)) {
4103 lowered = get_Proj_pred(lowered);
4105 assert(is_ia32_Sub(lowered));
4106 set_irn_mode(lowered, mode_T);
4112 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4113 return gen_binop_flags(node, new_rd_ia32_Sbb,
4114 match_am | match_immediate | match_mode_neutral);
4118 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4119 * op1 - target to be shifted
4120 * op2 - contains bits to be shifted into target
4122 * Only op3 can be an immediate.
4124 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4125 ir_node *low, ir_node *count)
4127 ir_node *block = get_nodes_block(node);
4128 ir_node *new_block = be_transform_node(block);
4129 ir_graph *irg = current_ir_graph;
4130 dbg_info *dbgi = get_irn_dbg_info(node);
4131 ir_node *new_high = be_transform_node(high);
4132 ir_node *new_low = be_transform_node(low);
4136 /* the shift amount can be any mode that is bigger than 5 bits, since all
4137 * other bits are ignored anyway */
4138 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4139 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4140 count = get_Conv_op(count);
4142 new_count = create_immediate_or_transform(count, 0);
4144 if (is_ia32_l_ShlD(node)) {
4145 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4148 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4151 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4156 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4158 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4159 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4160 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4161 return gen_lowered_64bit_shifts(node, high, low, count);
4164 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4166 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4167 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4168 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4169 return gen_lowered_64bit_shifts(node, high, low, count);
4173 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4175 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4176 ir_node *block = be_transform_node(get_nodes_block(node));
4177 ir_node *val = get_irn_n(node, 1);
4178 ir_node *new_val = be_transform_node(val);
4179 ir_node *res = NULL;
4180 ir_graph *irg = current_ir_graph;
4182 ir_node *noreg, *new_ptr, *new_mem;
4185 if (ia32_cg_config.use_sse2) {
4189 mem = get_irn_n(node, 2);
4190 new_mem = be_transform_node(mem);
4191 ptr = get_irn_n(node, 0);
4192 new_ptr = be_transform_node(ptr);
4193 noreg = ia32_new_NoReg_gp(env_cg);
4194 dbgi = get_irn_dbg_info(node);
4196 /* Store x87 -> MEM */
4197 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4198 get_ia32_ls_mode(node));
4199 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4200 set_ia32_use_frame(res);
4201 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4202 set_ia32_op_type(res, ia32_AddrModeD);
4204 /* Load MEM -> SSE */
4205 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4206 get_ia32_ls_mode(node));
4207 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4208 set_ia32_use_frame(res);
4209 set_ia32_op_type(res, ia32_AddrModeS);
4210 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4216 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4218 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4219 ir_node *block = be_transform_node(get_nodes_block(node));
4220 ir_node *val = get_irn_n(node, 1);
4221 ir_node *new_val = be_transform_node(val);
4222 ir_graph *irg = current_ir_graph;
4223 ir_node *res = NULL;
4224 ir_entity *fent = get_ia32_frame_ent(node);
4225 ir_mode *lsmode = get_ia32_ls_mode(node);
4227 ir_node *noreg, *new_ptr, *new_mem;
4231 if (! ia32_cg_config.use_sse2) {
4232 /* SSE unit is not used -> skip this node. */
4236 ptr = get_irn_n(node, 0);
4237 new_ptr = be_transform_node(ptr);
4238 mem = get_irn_n(node, 2);
4239 new_mem = be_transform_node(mem);
4240 noreg = ia32_new_NoReg_gp(env_cg);
4241 dbgi = get_irn_dbg_info(node);
4243 /* Store SSE -> MEM */
4244 if (is_ia32_xLoad(skip_Proj(new_val))) {
4245 ir_node *ld = skip_Proj(new_val);
4247 /* we can vfld the value directly into the fpu */
4248 fent = get_ia32_frame_ent(ld);
4249 ptr = get_irn_n(ld, 0);
4250 offs = get_ia32_am_offs_int(ld);
4252 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4254 set_ia32_frame_ent(res, fent);
4255 set_ia32_use_frame(res);
4256 set_ia32_ls_mode(res, lsmode);
4257 set_ia32_op_type(res, ia32_AddrModeD);
4261 /* Load MEM -> x87 */
4262 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4263 set_ia32_frame_ent(res, fent);
4264 set_ia32_use_frame(res);
4265 add_ia32_am_offs_int(res, offs);
4266 set_ia32_op_type(res, ia32_AddrModeS);
4267 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4273 * the BAD transformer.
4275 static ir_node *bad_transform(ir_node *node) {
4276 panic("No transform function for %+F available.\n", node);
4281 * Transform the Projs of an AddSP.
4283 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4284 ir_node *block = be_transform_node(get_nodes_block(node));
4285 ir_node *pred = get_Proj_pred(node);
4286 ir_node *new_pred = be_transform_node(pred);
4287 ir_graph *irg = current_ir_graph;
4288 dbg_info *dbgi = get_irn_dbg_info(node);
4289 long proj = get_Proj_proj(node);
4291 if (proj == pn_be_AddSP_sp) {
4292 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4293 pn_ia32_SubSP_stack);
4294 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4296 } else if(proj == pn_be_AddSP_res) {
4297 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4298 pn_ia32_SubSP_addr);
4299 } else if (proj == pn_be_AddSP_M) {
4300 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4304 return new_rd_Unknown(irg, get_irn_mode(node));
4308 * Transform the Projs of a SubSP.
4310 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4311 ir_node *block = be_transform_node(get_nodes_block(node));
4312 ir_node *pred = get_Proj_pred(node);
4313 ir_node *new_pred = be_transform_node(pred);
4314 ir_graph *irg = current_ir_graph;
4315 dbg_info *dbgi = get_irn_dbg_info(node);
4316 long proj = get_Proj_proj(node);
4318 if (proj == pn_be_SubSP_sp) {
4319 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4320 pn_ia32_AddSP_stack);
4321 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4323 } else if (proj == pn_be_SubSP_M) {
4324 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4328 return new_rd_Unknown(irg, get_irn_mode(node));
4332 * Transform and renumber the Projs from a Load.
4334 static ir_node *gen_Proj_Load(ir_node *node) {
4336 ir_node *block = be_transform_node(get_nodes_block(node));
4337 ir_node *pred = get_Proj_pred(node);
4338 ir_graph *irg = current_ir_graph;
4339 dbg_info *dbgi = get_irn_dbg_info(node);
4340 long proj = get_Proj_proj(node);
4343 /* loads might be part of source address mode matches, so we don't
4344 transform the ProjMs yet (with the exception of loads whose result is
4347 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4350 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4352 /* this is needed, because sometimes we have loops that are only
4353 reachable through the ProjM */
4354 be_enqueue_preds(node);
4355 /* do it in 2 steps, to silence firm verifier */
4356 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4357 set_Proj_proj(res, pn_ia32_Load_M);
4361 /* renumber the proj */
4362 new_pred = be_transform_node(pred);
4363 if (is_ia32_Load(new_pred)) {
4364 if (proj == pn_Load_res) {
4365 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4367 } else if (proj == pn_Load_M) {
4368 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4371 } else if(is_ia32_Conv_I2I(new_pred)
4372 || is_ia32_Conv_I2I8Bit(new_pred)) {
4373 set_irn_mode(new_pred, mode_T);
4374 if (proj == pn_Load_res) {
4375 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4376 } else if (proj == pn_Load_M) {
4377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4379 } else if (is_ia32_xLoad(new_pred)) {
4380 if (proj == pn_Load_res) {
4381 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4383 } else if (proj == pn_Load_M) {
4384 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4387 } else if (is_ia32_vfld(new_pred)) {
4388 if (proj == pn_Load_res) {
4389 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4391 } else if (proj == pn_Load_M) {
4392 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4396 /* can happen for ProJMs when source address mode happened for the
4399 /* however it should not be the result proj, as that would mean the
4400 load had multiple users and should not have been used for
4402 if(proj != pn_Load_M) {
4403 panic("internal error: transformed node not a Load");
4405 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4409 return new_rd_Unknown(irg, get_irn_mode(node));
4413 * Transform and renumber the Projs from a DivMod like instruction.
4415 static ir_node *gen_Proj_DivMod(ir_node *node) {
4416 ir_node *block = be_transform_node(get_nodes_block(node));
4417 ir_node *pred = get_Proj_pred(node);
4418 ir_node *new_pred = be_transform_node(pred);
4419 ir_graph *irg = current_ir_graph;
4420 dbg_info *dbgi = get_irn_dbg_info(node);
4421 ir_mode *mode = get_irn_mode(node);
4422 long proj = get_Proj_proj(node);
4424 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4426 switch (get_irn_opcode(pred)) {
4430 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4432 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4440 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4442 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4450 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4451 case pn_DivMod_res_div:
4452 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4453 case pn_DivMod_res_mod:
4454 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4464 return new_rd_Unknown(irg, mode);
4468 * Transform and renumber the Projs from a CopyB.
4470 static ir_node *gen_Proj_CopyB(ir_node *node) {
4471 ir_node *block = be_transform_node(get_nodes_block(node));
4472 ir_node *pred = get_Proj_pred(node);
4473 ir_node *new_pred = be_transform_node(pred);
4474 ir_graph *irg = current_ir_graph;
4475 dbg_info *dbgi = get_irn_dbg_info(node);
4476 ir_mode *mode = get_irn_mode(node);
4477 long proj = get_Proj_proj(node);
4480 case pn_CopyB_M_regular:
4481 if (is_ia32_CopyB_i(new_pred)) {
4482 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4483 } else if (is_ia32_CopyB(new_pred)) {
4484 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4492 return new_rd_Unknown(irg, mode);
4496 * Transform and renumber the Projs from a Quot.
4498 static ir_node *gen_Proj_Quot(ir_node *node) {
4499 ir_node *block = be_transform_node(get_nodes_block(node));
4500 ir_node *pred = get_Proj_pred(node);
4501 ir_node *new_pred = be_transform_node(pred);
4502 ir_graph *irg = current_ir_graph;
4503 dbg_info *dbgi = get_irn_dbg_info(node);
4504 ir_mode *mode = get_irn_mode(node);
4505 long proj = get_Proj_proj(node);
4509 if (is_ia32_xDiv(new_pred)) {
4510 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4511 } else if (is_ia32_vfdiv(new_pred)) {
4512 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4516 if (is_ia32_xDiv(new_pred)) {
4517 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4518 } else if (is_ia32_vfdiv(new_pred)) {
4519 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4527 return new_rd_Unknown(irg, mode);
4531 * Transform the Thread Local Storage Proj.
4533 static ir_node *gen_Proj_tls(ir_node *node) {
4534 ir_node *block = be_transform_node(get_nodes_block(node));
4535 ir_graph *irg = current_ir_graph;
4536 dbg_info *dbgi = NULL;
4537 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4542 static ir_node *gen_be_Call(ir_node *node) {
4543 ir_node *res = be_duplicate_node(node);
4544 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4549 static ir_node *gen_be_IncSP(ir_node *node) {
4550 ir_node *res = be_duplicate_node(node);
4551 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4557 * Transform the Projs from a be_Call.
4559 static ir_node *gen_Proj_be_Call(ir_node *node) {
4560 ir_node *block = be_transform_node(get_nodes_block(node));
4561 ir_node *call = get_Proj_pred(node);
4562 ir_node *new_call = be_transform_node(call);
4563 ir_graph *irg = current_ir_graph;
4564 dbg_info *dbgi = get_irn_dbg_info(node);
4565 ir_type *method_type = be_Call_get_type(call);
4566 int n_res = get_method_n_ress(method_type);
4567 long proj = get_Proj_proj(node);
4568 ir_mode *mode = get_irn_mode(node);
4570 const arch_register_class_t *cls;
4572 /* The following is kinda tricky: If we're using SSE, then we have to
4573 * move the result value of the call in floating point registers to an
4574 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4575 * after the call, we have to make sure to correctly make the
4576 * MemProj and the result Proj use these 2 nodes
4578 if (proj == pn_be_Call_M_regular) {
4579 // get new node for result, are we doing the sse load/store hack?
4580 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4581 ir_node *call_res_new;
4582 ir_node *call_res_pred = NULL;
4584 if (call_res != NULL) {
4585 call_res_new = be_transform_node(call_res);
4586 call_res_pred = get_Proj_pred(call_res_new);
4589 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4590 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4591 pn_be_Call_M_regular);
4593 assert(is_ia32_xLoad(call_res_pred));
4594 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4598 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4599 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4601 ir_node *frame = get_irg_frame(irg);
4602 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4604 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4607 /* in case there is no memory output: create one to serialize the copy
4609 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4610 pn_be_Call_M_regular);
4611 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4612 pn_be_Call_first_res);
4614 /* store st(0) onto stack */
4615 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4617 set_ia32_op_type(fstp, ia32_AddrModeD);
4618 set_ia32_use_frame(fstp);
4620 /* load into SSE register */
4621 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4623 set_ia32_op_type(sse_load, ia32_AddrModeS);
4624 set_ia32_use_frame(sse_load);
4626 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4632 /* transform call modes */
4633 if (mode_is_data(mode)) {
4634 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4638 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4642 * Transform the Projs from a Cmp.
4644 static ir_node *gen_Proj_Cmp(ir_node *node)
4646 /* this probably means not all mode_b nodes were lowered... */
4647 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
4652 * Transform and potentially renumber Proj nodes.
4654 static ir_node *gen_Proj(ir_node *node) {
4655 ir_graph *irg = current_ir_graph;
4656 dbg_info *dbgi = get_irn_dbg_info(node);
4657 ir_node *pred = get_Proj_pred(node);
4658 long proj = get_Proj_proj(node);
4660 if (is_Store(pred)) {
4661 if (proj == pn_Store_M) {
4662 return be_transform_node(pred);
4665 return new_r_Bad(irg);
4667 } else if (is_Load(pred)) {
4668 return gen_Proj_Load(node);
4669 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4670 return gen_Proj_DivMod(node);
4671 } else if (is_CopyB(pred)) {
4672 return gen_Proj_CopyB(node);
4673 } else if (is_Quot(pred)) {
4674 return gen_Proj_Quot(node);
4675 } else if (be_is_SubSP(pred)) {
4676 return gen_Proj_be_SubSP(node);
4677 } else if (be_is_AddSP(pred)) {
4678 return gen_Proj_be_AddSP(node);
4679 } else if (be_is_Call(pred)) {
4680 return gen_Proj_be_Call(node);
4681 } else if (is_Cmp(pred)) {
4682 return gen_Proj_Cmp(node);
4683 } else if (get_irn_op(pred) == op_Start) {
4684 if (proj == pn_Start_X_initial_exec) {
4685 ir_node *block = get_nodes_block(pred);
4688 /* we exchange the ProjX with a jump */
4689 block = be_transform_node(block);
4690 jump = new_rd_Jmp(dbgi, irg, block);
4693 if (node == be_get_old_anchor(anchor_tls)) {
4694 return gen_Proj_tls(node);
4697 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4701 ir_node *new_pred = be_transform_node(pred);
4702 ir_node *block = be_transform_node(get_nodes_block(node));
4703 ir_mode *mode = get_irn_mode(node);
4704 if (mode_needs_gp_reg(mode)) {
4705 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4706 get_Proj_proj(node));
4707 #ifdef DEBUG_libfirm
4708 new_proj->node_nr = node->node_nr;
4714 return be_duplicate_node(node);
4718 * Enters all transform functions into the generic pointer
4720 static void register_transformers(void)
4724 /* first clear the generic function pointer for all ops */
4725 clear_irp_opcodes_generic_func();
4727 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4728 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4766 /* transform ops from intrinsic lowering */
4782 GEN(ia32_l_X87toSSE);
4783 GEN(ia32_l_SSEtoX87);
4789 /* we should never see these nodes */
4804 /* handle generic backend nodes */
4813 op_Mulh = get_op_Mulh();
4822 * Pre-transform all unknown and noreg nodes.
4824 static void ia32_pretransform_node(void *arch_cg) {
4825 ia32_code_gen_t *cg = arch_cg;
4827 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4828 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4829 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4830 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4831 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4832 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4837 * Walker, checks if all ia32 nodes producing more than one result have
4838 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4840 static void add_missing_keep_walker(ir_node *node, void *data)
4843 unsigned found_projs = 0;
4844 const ir_edge_t *edge;
4845 ir_mode *mode = get_irn_mode(node);
4850 if(!is_ia32_irn(node))
4853 n_outs = get_ia32_n_res(node);
4856 if(is_ia32_SwitchJmp(node))
4859 assert(n_outs < (int) sizeof(unsigned) * 8);
4860 foreach_out_edge(node, edge) {
4861 ir_node *proj = get_edge_src_irn(edge);
4862 int pn = get_Proj_proj(proj);
4864 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4865 found_projs |= 1 << pn;
4869 /* are keeps missing? */
4871 for(i = 0; i < n_outs; ++i) {
4874 const arch_register_req_t *req;
4875 const arch_register_class_t *class;
4877 if(found_projs & (1 << i)) {
4881 req = get_ia32_out_req(node, i);
4886 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4890 block = get_nodes_block(node);
4891 in[0] = new_r_Proj(current_ir_graph, block, node,
4892 arch_register_class_mode(class), i);
4893 if(last_keep != NULL) {
4894 be_Keep_add_node(last_keep, class, in[0]);
4896 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4897 if(sched_is_scheduled(node)) {
4898 sched_add_after(node, last_keep);
4905 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4908 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4910 ir_graph *irg = be_get_birg_irg(cg->birg);
4911 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4914 /* do the transformation */
4915 void ia32_transform_graph(ia32_code_gen_t *cg) {
4917 ir_graph *irg = cg->irg;
4919 register_transformers();
4921 initial_fpcw = NULL;
4923 heights = heights_new(irg);
4924 ia32_calculate_non_address_mode_nodes(cg->birg);
4926 /* the transform phase is not safe for CSE (yet) because several nodes get
4927 * attributes set after their creation */
4928 cse_last = get_opt_cse();
4931 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4933 set_opt_cse(cse_last);
4935 ia32_free_non_address_mode_nodes();
4936 heights_free(heights);
4940 void ia32_init_transform(void)
4942 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");