2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
51 #include "../benode_t.h"
52 #include "../besched.h"
54 #include "../beutil.h"
55 #include "../beirg_t.h"
56 #include "../betranshlp.h"
58 #include "bearch_ia32_t.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_map_regs.h"
63 #include "ia32_dbg_stat.h"
64 #include "ia32_optimize.h"
65 #include "ia32_util.h"
67 #include "gen_ia32_regalloc_if.h"
69 #define SFP_SIGN "0x80000000"
70 #define DFP_SIGN "0x8000000000000000"
71 #define SFP_ABS "0x7FFFFFFF"
72 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
74 #define TP_SFP_SIGN "ia32_sfp_sign"
75 #define TP_DFP_SIGN "ia32_dfp_sign"
76 #define TP_SFP_ABS "ia32_sfp_abs"
77 #define TP_DFP_ABS "ia32_dfp_abs"
79 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
80 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
81 #define ENT_SFP_ABS "IA32_SFP_ABS"
82 #define ENT_DFP_ABS "IA32_DFP_ABS"
84 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
85 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
87 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
89 /** hold the current code generator during transformation */
90 static ia32_code_gen_t *env_cg = NULL;
92 extern ir_op *get_op_Mulh(void);
94 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
95 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
96 ir_node *op2, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
99 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
100 ir_node *op2, ir_node *mem, ir_node *fpcw);
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
106 /****************************************************************************************************
108 * | | | | / _| | | (_)
109 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
110 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
111 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
112 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
114 ****************************************************************************************************/
116 static ir_node *try_create_Immediate(ir_node *node,
117 char immediate_constraint_type);
119 static ir_node *create_immediate_or_transform(ir_node *node,
120 char immediate_constraint_type);
123 * Return true if a mode can be stored in the GP register set
125 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
126 if(mode == mode_fpcw)
128 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
281 if (! USE_SSE2(env_cg)) {
282 cnst_classify_t clss = classify_Const(node);
284 if (clss == CNST_NULL) {
285 load = new_rd_ia32_vfldz(dbgi, irg, block);
287 } else if (clss == CNST_ONE) {
288 load = new_rd_ia32_vfld1(dbgi, irg, block);
291 floatent = get_entity_for_tv(env_cg, node);
293 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
294 set_ia32_op_type(load, ia32_AddrModeS);
295 set_ia32_am_flavour(load, ia32_am_N);
296 set_ia32_am_sc(load, floatent);
297 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
298 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
300 set_ia32_ls_mode(load, mode);
302 floatent = get_entity_for_tv(env_cg, node);
304 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
305 set_ia32_op_type(load, ia32_AddrModeS);
306 set_ia32_am_flavour(load, ia32_am_N);
307 set_ia32_am_sc(load, floatent);
308 set_ia32_ls_mode(load, mode);
309 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
311 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
314 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 /* Const Nodes before the initial IncSP are a bad idea, because
317 * they could be spilled and we have no SP ready at that point yet.
318 * So add a dependency to the initial frame pointer calculation to
319 * avoid that situation.
321 if (get_irg_start_block(irg) == block) {
322 add_irn_dep(load, get_irg_frame(irg));
325 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
328 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
335 set_ia32_Const_attr(cnst, node);
336 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
341 return new_r_Bad(irg);
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *block = be_transform_node(get_nodes_block(node));
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
356 if (USE_SSE2(env_cg))
357 cnst = new_rd_ia32_xConst(dbgi, irg, block);
359 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
360 //set_ia32_ls_mode(cnst, mode);
361 set_ia32_ls_mode(cnst, mode_E);
363 cnst = new_rd_ia32_Const(dbgi, irg, block);
366 /* Const Nodes before the initial IncSP are a bad idea, because
367 * they could be spilled and we have no SP ready at that point yet
369 if (get_irg_start_block(irg) == block) {
370 add_irn_dep(cnst, get_irg_frame(irg));
373 set_ia32_Const_attr(cnst, node);
374 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
379 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
380 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
381 static const struct {
383 const char *ent_name;
384 const char *cnst_str;
385 } names [ia32_known_const_max] = {
386 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
387 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
388 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
389 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
391 static ir_entity *ent_cache[ia32_known_const_max];
393 const char *tp_name, *ent_name, *cnst_str;
401 ent_name = names[kct].ent_name;
402 if (! ent_cache[kct]) {
403 tp_name = names[kct].tp_name;
404 cnst_str = names[kct].cnst_str;
406 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
408 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
409 tp = new_type_primitive(new_id_from_str(tp_name), mode);
410 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
412 set_entity_ld_ident(ent, get_entity_ident(ent));
413 set_entity_visibility(ent, visibility_local);
414 set_entity_variability(ent, variability_constant);
415 set_entity_allocation(ent, allocation_static);
417 /* we create a new entity here: It's initialization must resist on the
419 rem = current_ir_graph;
420 current_ir_graph = get_const_code_irg();
421 cnst = new_Const(mode, tv);
422 current_ir_graph = rem;
424 set_atomic_ent_value(ent, cnst);
426 /* cache the entry */
427 ent_cache[kct] = ent;
430 return ent_cache[kct];
435 * Prints the old node name on cg obst and returns a pointer to it.
437 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
438 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
440 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
441 obstack_1grow(isa->name_obst, 0);
442 return obstack_finish(isa->name_obst);
446 /* determine if one operator is an Imm */
447 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
449 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
451 return is_ia32_Cnst(op2) ? op2 : NULL;
455 /* determine if one operator is not an Imm */
456 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
457 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
460 static void fold_immediate(ir_node *node, int in1, int in2) {
464 if (!(env_cg->opt & IA32_OPT_IMMOPS))
467 left = get_irn_n(node, in1);
468 right = get_irn_n(node, in2);
469 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
470 /* we can only set right operand to immediate */
471 if(!is_ia32_commutative(node))
473 /* exchange left/right */
474 set_irn_n(node, in1, right);
475 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
476 copy_ia32_Immop_attr(node, left);
477 } else if(is_ia32_Cnst(right)) {
478 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
479 copy_ia32_Immop_attr(node, right);
484 clear_ia32_commutative(node);
485 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
486 get_ia32_am_arity(node));
490 * Construct a standard binary operation, set AM and immediate if required.
492 * @param op1 The first operand
493 * @param op2 The second operand
494 * @param func The node constructor function
495 * @return The constructed ia32 node.
497 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
498 construct_binop_func *func, int commutative)
500 ir_node *block = be_transform_node(get_nodes_block(node));
501 ir_graph *irg = current_ir_graph;
502 dbg_info *dbgi = get_irn_dbg_info(node);
503 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
504 ir_node *nomem = new_NoMem();
507 ir_node *new_op1 = be_transform_node(op1);
508 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
509 if (is_ia32_Immediate(new_op2)) {
513 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
514 if (func == new_rd_ia32_IMul) {
515 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
517 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
520 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
522 set_ia32_commutative(new_node);
529 * Construct a standard binary operation, set AM and immediate if required.
531 * @param op1 The first operand
532 * @param op2 The second operand
533 * @param func The node constructor function
534 * @return The constructed ia32 node.
536 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
537 construct_binop_func *func)
539 ir_node *block = be_transform_node(get_nodes_block(node));
540 ir_node *new_op1 = be_transform_node(op1);
541 ir_node *new_op2 = be_transform_node(op2);
542 ir_node *new_node = NULL;
543 dbg_info *dbgi = get_irn_dbg_info(node);
544 ir_graph *irg = current_ir_graph;
545 ir_mode *mode = get_irn_mode(node);
546 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
547 ir_node *nomem = new_NoMem();
549 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
551 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
552 if (is_op_commutative(get_irn_op(node))) {
553 set_ia32_commutative(new_node);
555 if (USE_SSE2(env_cg)) {
556 set_ia32_ls_mode(new_node, mode);
559 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
565 * Construct a standard binary operation, set AM and immediate if required.
567 * @param op1 The first operand
568 * @param op2 The second operand
569 * @param func The node constructor function
570 * @return The constructed ia32 node.
572 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
573 construct_binop_float_func *func)
575 ir_node *block = be_transform_node(get_nodes_block(node));
576 ir_node *new_op1 = be_transform_node(op1);
577 ir_node *new_op2 = be_transform_node(op2);
578 ir_node *new_node = NULL;
579 dbg_info *dbgi = get_irn_dbg_info(node);
580 ir_graph *irg = current_ir_graph;
581 ir_mode *mode = get_irn_mode(node);
582 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
583 ir_node *nomem = new_NoMem();
584 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
585 &ia32_fp_cw_regs[REG_FPCW]);
587 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
589 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
590 if (is_op_commutative(get_irn_op(node))) {
591 set_ia32_commutative(new_node);
593 if (USE_SSE2(env_cg)) {
594 set_ia32_ls_mode(new_node, mode);
597 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
603 * Construct a shift/rotate binary operation, sets AM and immediate if required.
605 * @param op1 The first operand
606 * @param op2 The second operand
607 * @param func The node constructor function
608 * @return The constructed ia32 node.
610 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
611 construct_binop_func *func)
613 ir_node *block = be_transform_node(get_nodes_block(node));
614 ir_node *new_op1 = be_transform_node(op1);
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = current_ir_graph;
619 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
620 ir_node *nomem = new_NoMem();
622 assert(! mode_is_float(get_irn_mode(node))
623 && "Shift/Rotate with float not supported");
625 new_op2 = create_immediate_or_transform(op2, 'N');
627 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
630 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
632 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
634 set_ia32_emit_cl(new_op);
641 * Construct a standard unary operation, set AM and immediate if required.
643 * @param op The operand
644 * @param func The node constructor function
645 * @return The constructed ia32 node.
647 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
649 ir_node *block = be_transform_node(get_nodes_block(node));
650 ir_node *new_op = be_transform_node(op);
651 ir_node *new_node = NULL;
652 ir_graph *irg = current_ir_graph;
653 dbg_info *dbgi = get_irn_dbg_info(node);
654 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
655 ir_node *nomem = new_NoMem();
657 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
658 DB((dbg, LEVEL_1, "INT unop ..."));
659 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
661 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
667 * Creates an ia32 Add.
669 * @return the created ia32 Add node
671 static ir_node *gen_Add(ir_node *node) {
672 ir_node *block = be_transform_node(get_nodes_block(node));
673 ir_node *op1 = get_Add_left(node);
674 ir_node *new_op1 = be_transform_node(op1);
675 ir_node *op2 = get_Add_right(node);
676 ir_node *new_op2 = be_transform_node(op2);
677 ir_node *new_op = NULL;
678 ir_graph *irg = current_ir_graph;
679 dbg_info *dbgi = get_irn_dbg_info(node);
680 ir_mode *mode = get_irn_mode(node);
681 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
682 ir_node *nomem = new_NoMem();
683 ir_node *expr_op, *imm_op;
685 /* Check if immediate optimization is on and */
686 /* if it's an operation with immediate. */
687 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
688 expr_op = get_expr_op(new_op1, new_op2);
690 assert((expr_op || imm_op) && "invalid operands");
692 if (mode_is_float(mode)) {
694 if (USE_SSE2(env_cg))
695 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
697 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
702 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
703 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
705 /* No expr_op means, that we have two const - one symconst and */
706 /* one tarval or another symconst - because this case is not */
707 /* covered by constant folding */
708 /* We need to check for: */
709 /* 1) symconst + const -> becomes a LEA */
710 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
711 /* linker doesn't support two symconsts */
713 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
714 /* this is the 2nd case */
715 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
716 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
717 set_ia32_am_flavour(new_op, ia32_am_B);
718 set_ia32_op_type(new_op, ia32_AddrModeS);
720 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
721 } else if (tp1 == ia32_ImmSymConst) {
722 tarval *tv = get_ia32_Immop_tarval(new_op2);
723 long offs = get_tarval_long(tv);
725 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
726 add_irn_dep(new_op, get_irg_frame(irg));
727 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
729 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
730 add_ia32_am_offs_int(new_op, offs);
731 set_ia32_am_flavour(new_op, ia32_am_OB);
732 set_ia32_op_type(new_op, ia32_AddrModeS);
733 } else if (tp2 == ia32_ImmSymConst) {
734 tarval *tv = get_ia32_Immop_tarval(new_op1);
735 long offs = get_tarval_long(tv);
737 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
738 add_irn_dep(new_op, get_irg_frame(irg));
739 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
741 add_ia32_am_offs_int(new_op, offs);
742 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
743 set_ia32_am_flavour(new_op, ia32_am_OB);
744 set_ia32_op_type(new_op, ia32_AddrModeS);
746 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
747 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
748 tarval *restv = tarval_add(tv1, tv2);
750 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
752 new_op = new_rd_ia32_Const(dbgi, irg, block);
753 set_ia32_Const_tarval(new_op, restv);
754 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
757 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
760 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
761 tarval_classification_t class_tv, class_negtv;
762 tarval *tv = get_ia32_Immop_tarval(imm_op);
764 /* optimize tarvals */
765 class_tv = classify_tarval(tv);
766 class_negtv = classify_tarval(tarval_neg(tv));
768 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
769 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
770 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
771 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
773 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
774 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
775 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
776 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
782 /* This is a normal add */
783 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
786 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
787 set_ia32_commutative(new_op);
789 fold_immediate(new_op, 2, 3);
791 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
797 static ir_node *create_ia32_Mul(ir_node *node) {
798 ir_graph *irg = current_ir_graph;
799 dbg_info *dbgi = get_irn_dbg_info(node);
800 ir_node *block = be_transform_node(get_nodes_block(node));
801 ir_node *op1 = get_Mul_left(node);
802 ir_node *op2 = get_Mul_right(node);
803 ir_node *new_op1 = be_transform_node(op1);
804 ir_node *new_op2 = be_transform_node(op2);
805 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
806 ir_node *proj_EAX, *proj_EDX, *res;
809 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
810 set_ia32_commutative(res);
811 set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
813 /* imediates are not supported, so no fold_immediate */
814 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
815 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
819 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
827 * Creates an ia32 Mul.
829 * @return the created ia32 Mul node
831 static ir_node *gen_Mul(ir_node *node) {
832 ir_node *op1 = get_Mul_left(node);
833 ir_node *op2 = get_Mul_right(node);
834 ir_mode *mode = get_irn_mode(node);
836 if (mode_is_float(mode)) {
838 if (USE_SSE2(env_cg))
839 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
841 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
845 for the lower 32bit of the result it doesn't matter whether we use
846 signed or unsigned multiplication so we use IMul as it has fewer
849 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
853 * Creates an ia32 Mulh.
854 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
855 * this result while Mul returns the lower 32 bit.
857 * @return the created ia32 Mulh node
859 static ir_node *gen_Mulh(ir_node *node) {
860 ir_node *block = be_transform_node(get_nodes_block(node));
861 ir_node *op1 = get_irn_n(node, 0);
862 ir_node *new_op1 = be_transform_node(op1);
863 ir_node *op2 = get_irn_n(node, 1);
864 ir_node *new_op2 = be_transform_node(op2);
865 ir_graph *irg = current_ir_graph;
866 dbg_info *dbgi = get_irn_dbg_info(node);
867 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
868 ir_mode *mode = get_irn_mode(node);
869 ir_node *proj_EAX, *proj_EDX, *res;
872 assert(!mode_is_float(mode) && "Mulh with float not supported");
873 if (mode_is_signed(mode)) {
874 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
876 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
879 set_ia32_commutative(res);
880 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
882 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
883 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
887 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
895 * Creates an ia32 And.
897 * @return The created ia32 And node
899 static ir_node *gen_And(ir_node *node) {
900 ir_node *op1 = get_And_left(node);
901 ir_node *op2 = get_And_right(node);
903 assert (! mode_is_float(get_irn_mode(node)));
904 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
910 * Creates an ia32 Or.
912 * @return The created ia32 Or node
914 static ir_node *gen_Or(ir_node *node) {
915 ir_node *op1 = get_Or_left(node);
916 ir_node *op2 = get_Or_right(node);
918 assert (! mode_is_float(get_irn_mode(node)));
919 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
925 * Creates an ia32 Eor.
927 * @return The created ia32 Eor node
929 static ir_node *gen_Eor(ir_node *node) {
930 ir_node *op1 = get_Eor_left(node);
931 ir_node *op2 = get_Eor_right(node);
933 assert(! mode_is_float(get_irn_mode(node)));
934 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
940 * Creates an ia32 Max.
942 * @return the created ia32 Max node
944 static ir_node *gen_Max(ir_node *node) {
945 ir_node *block = be_transform_node(get_nodes_block(node));
946 ir_node *op1 = get_irn_n(node, 0);
947 ir_node *new_op1 = be_transform_node(op1);
948 ir_node *op2 = get_irn_n(node, 1);
949 ir_node *new_op2 = be_transform_node(op2);
950 ir_graph *irg = current_ir_graph;
951 ir_mode *mode = get_irn_mode(node);
952 dbg_info *dbgi = get_irn_dbg_info(node);
953 ir_mode *op_mode = get_irn_mode(op1);
956 assert(get_mode_size_bits(mode) == 32);
958 if (mode_is_float(mode)) {
960 if (USE_SSE2(env_cg)) {
961 new_op = gen_binop_sse_float(node, new_op1, new_op2, new_rd_ia32_xMax);
963 panic("Can't create Max node");
966 long pnc = pn_Cmp_Gt;
967 if (! mode_is_signed(op_mode)) {
968 pnc |= ia32_pn_Cmp_Unsigned;
970 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
971 new_op1, new_op2, pnc);
973 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
979 * Creates an ia32 Min.
981 * @return the created ia32 Min node
983 static ir_node *gen_Min(ir_node *node) {
984 ir_node *block = be_transform_node(get_nodes_block(node));
985 ir_node *op1 = get_irn_n(node, 0);
986 ir_node *new_op1 = be_transform_node(op1);
987 ir_node *op2 = get_irn_n(node, 1);
988 ir_node *new_op2 = be_transform_node(op2);
989 ir_graph *irg = current_ir_graph;
990 ir_mode *mode = get_irn_mode(node);
991 dbg_info *dbgi = get_irn_dbg_info(node);
992 ir_mode *op_mode = get_irn_mode(op1);
995 assert(get_mode_size_bits(mode) == 32);
997 if (mode_is_float(mode)) {
999 if (USE_SSE2(env_cg)) {
1000 new_op = gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMin);
1002 panic("can't create Min node");
1005 long pnc = pn_Cmp_Lt;
1006 if (! mode_is_signed(op_mode)) {
1007 pnc |= ia32_pn_Cmp_Unsigned;
1009 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2,
1010 new_op1, new_op2, pnc);
1012 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1019 * Creates an ia32 Sub.
1021 * @return The created ia32 Sub node
1023 static ir_node *gen_Sub(ir_node *node) {
1024 ir_node *block = be_transform_node(get_nodes_block(node));
1025 ir_node *op1 = get_Sub_left(node);
1026 ir_node *new_op1 = be_transform_node(op1);
1027 ir_node *op2 = get_Sub_right(node);
1028 ir_node *new_op2 = be_transform_node(op2);
1029 ir_node *new_op = NULL;
1030 ir_graph *irg = current_ir_graph;
1031 dbg_info *dbgi = get_irn_dbg_info(node);
1032 ir_mode *mode = get_irn_mode(node);
1033 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1034 ir_node *nomem = new_NoMem();
1035 ir_node *expr_op, *imm_op;
1037 /* Check if immediate optimization is on and */
1038 /* if it's an operation with immediate. */
1039 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1040 expr_op = get_expr_op(new_op1, new_op2);
1042 assert((expr_op || imm_op) && "invalid operands");
1044 if (mode_is_float(mode)) {
1046 if (USE_SSE2(env_cg))
1047 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1049 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1054 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1055 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1057 /* No expr_op means, that we have two const - one symconst and */
1058 /* one tarval or another symconst - because this case is not */
1059 /* covered by constant folding */
1060 /* We need to check for: */
1061 /* 1) symconst - const -> becomes a LEA */
1062 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1063 /* linker doesn't support two symconsts */
1064 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1065 /* this is the 2nd case */
1066 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1067 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1068 set_ia32_am_sc_sign(new_op);
1069 set_ia32_am_flavour(new_op, ia32_am_B);
1071 DBG_OPT_LEA3(op1, op2, node, new_op);
1072 } else if (tp1 == ia32_ImmSymConst) {
1073 tarval *tv = get_ia32_Immop_tarval(new_op2);
1074 long offs = get_tarval_long(tv);
1076 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1077 add_irn_dep(new_op, get_irg_frame(irg));
1078 DBG_OPT_LEA3(op1, op2, node, new_op);
1080 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1081 add_ia32_am_offs_int(new_op, -offs);
1082 set_ia32_am_flavour(new_op, ia32_am_OB);
1083 set_ia32_op_type(new_op, ia32_AddrModeS);
1084 } else if (tp2 == ia32_ImmSymConst) {
1085 tarval *tv = get_ia32_Immop_tarval(new_op1);
1086 long offs = get_tarval_long(tv);
1088 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1089 add_irn_dep(new_op, get_irg_frame(irg));
1090 DBG_OPT_LEA3(op1, op2, node, new_op);
1092 add_ia32_am_offs_int(new_op, offs);
1093 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1094 set_ia32_am_sc_sign(new_op);
1095 set_ia32_am_flavour(new_op, ia32_am_OB);
1096 set_ia32_op_type(new_op, ia32_AddrModeS);
1098 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1099 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1100 tarval *restv = tarval_sub(tv1, tv2);
1102 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1104 new_op = new_rd_ia32_Const(dbgi, irg, block);
1105 set_ia32_Const_tarval(new_op, restv);
1106 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1109 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1111 } else if (imm_op) {
1112 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1113 tarval_classification_t class_tv, class_negtv;
1114 tarval *tv = get_ia32_Immop_tarval(imm_op);
1116 /* optimize tarvals */
1117 class_tv = classify_tarval(tv);
1118 class_negtv = classify_tarval(tarval_neg(tv));
1120 if (class_tv == TV_CLASSIFY_ONE) {
1121 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1122 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1123 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1125 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1126 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1127 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1134 /* This is a normal sub */
1135 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1137 /* set AM support */
1138 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1140 fold_immediate(new_op, 2, 3);
1142 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1150 * Generates an ia32 DivMod with additional infrastructure for the
1151 * register allocator if needed.
1153 * @param dividend -no comment- :)
1154 * @param divisor -no comment- :)
1155 * @param dm_flav flavour_Div/Mod/DivMod
1156 * @return The created ia32 DivMod node
1158 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1159 ir_node *divisor, ia32_op_flavour_t dm_flav)
1161 ir_node *block = be_transform_node(get_nodes_block(node));
1162 ir_node *new_dividend = be_transform_node(dividend);
1163 ir_node *new_divisor = be_transform_node(divisor);
1164 ir_graph *irg = current_ir_graph;
1165 dbg_info *dbgi = get_irn_dbg_info(node);
1166 ir_mode *mode = get_irn_mode(node);
1167 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1168 ir_node *res, *proj_div, *proj_mod;
1169 ir_node *sign_extension;
1170 ir_node *in_keep[2];
1171 ir_node *mem, *new_mem;
1172 ir_node *projs[pn_DivMod_max];
1175 ia32_collect_Projs(node, projs, pn_DivMod_max);
1177 proj_div = proj_mod = NULL;
1181 mem = get_Div_mem(node);
1182 mode = get_Div_resmode(node);
1183 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1184 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1187 mem = get_Mod_mem(node);
1188 mode = get_Mod_resmode(node);
1189 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1190 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1192 case flavour_DivMod:
1193 mem = get_DivMod_mem(node);
1194 mode = get_DivMod_resmode(node);
1195 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1196 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1197 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1200 panic("invalid divmod flavour!");
1202 new_mem = be_transform_node(mem);
1204 if (mode_is_signed(mode)) {
1205 /* in signed mode, we need to sign extend the dividend */
1206 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1208 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1209 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1211 add_irn_dep(sign_extension, get_irg_frame(irg));
1214 if (mode_is_signed(mode)) {
1215 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1216 sign_extension, new_divisor, new_mem, dm_flav);
1218 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1219 sign_extension, new_divisor, new_mem, dm_flav);
1222 set_ia32_exc_label(res, has_exc);
1223 set_irn_pinned(res, get_irn_pinned(node));
1225 /* Matze: code can't handle this at the moment... */
1227 /* set AM support */
1228 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1231 /* check, which Proj-Keep, we need to add */
1233 if (proj_div == NULL) {
1234 /* We have only mod result: add div res Proj-Keep */
1235 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1238 if (proj_mod == NULL) {
1239 /* We have only div result: add mod res Proj-Keep */
1240 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1244 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1246 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1253 * Wrapper for generate_DivMod. Sets flavour_Mod.
1256 static ir_node *gen_Mod(ir_node *node) {
1257 return generate_DivMod(node, get_Mod_left(node),
1258 get_Mod_right(node), flavour_Mod);
1262 * Wrapper for generate_DivMod. Sets flavour_Div.
1265 static ir_node *gen_Div(ir_node *node) {
1266 return generate_DivMod(node, get_Div_left(node),
1267 get_Div_right(node), flavour_Div);
1271 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1273 static ir_node *gen_DivMod(ir_node *node) {
1274 return generate_DivMod(node, get_DivMod_left(node),
1275 get_DivMod_right(node), flavour_DivMod);
1281 * Creates an ia32 floating Div.
1283 * @return The created ia32 xDiv node
1285 static ir_node *gen_Quot(ir_node *node) {
1286 ir_node *block = be_transform_node(get_nodes_block(node));
1287 ir_node *op1 = get_Quot_left(node);
1288 ir_node *new_op1 = be_transform_node(op1);
1289 ir_node *op2 = get_Quot_right(node);
1290 ir_node *new_op2 = be_transform_node(op2);
1291 ir_graph *irg = current_ir_graph;
1292 dbg_info *dbgi = get_irn_dbg_info(node);
1293 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1294 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1298 if (USE_SSE2(env_cg)) {
1299 ir_mode *mode = get_irn_mode(op1);
1300 if (is_ia32_xConst(new_op2)) {
1301 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1302 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1303 copy_ia32_Immop_attr(new_op, new_op2);
1305 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1306 // Matze: disabled for now, spillslot coalescer fails
1307 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1309 set_ia32_ls_mode(new_op, mode);
1311 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1312 &ia32_fp_cw_regs[REG_FPCW]);
1313 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1314 new_op2, nomem, fpcw);
1315 // Matze: disabled for now (spillslot coalescer fails)
1316 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1318 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1324 * Creates an ia32 Shl.
1326 * @return The created ia32 Shl node
1328 static ir_node *gen_Shl(ir_node *node) {
1329 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1336 * Creates an ia32 Shr.
1338 * @return The created ia32 Shr node
1340 static ir_node *gen_Shr(ir_node *node) {
1341 return gen_shift_binop(node, get_Shr_left(node),
1342 get_Shr_right(node), new_rd_ia32_Shr);
1348 * Creates an ia32 Sar.
1350 * @return The created ia32 Shrs node
1352 static ir_node *gen_Shrs(ir_node *node) {
1353 ir_node *left = get_Shrs_left(node);
1354 ir_node *right = get_Shrs_right(node);
1355 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1356 tarval *tv = get_Const_tarval(right);
1357 long val = get_tarval_long(tv);
1359 /* this is a sign extension */
1360 ir_graph *irg = current_ir_graph;
1361 dbg_info *dbgi = get_irn_dbg_info(node);
1362 ir_node *block = be_transform_node(get_nodes_block(node));
1364 ir_node *new_op = be_transform_node(op);
1366 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1370 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1376 * Creates an ia32 RotL.
1378 * @param op1 The first operator
1379 * @param op2 The second operator
1380 * @return The created ia32 RotL node
1382 static ir_node *gen_RotL(ir_node *node,
1383 ir_node *op1, ir_node *op2) {
1384 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1390 * Creates an ia32 RotR.
1391 * NOTE: There is no RotR with immediate because this would always be a RotL
1392 * "imm-mode_size_bits" which can be pre-calculated.
1394 * @param op1 The first operator
1395 * @param op2 The second operator
1396 * @return The created ia32 RotR node
1398 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1400 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1406 * Creates an ia32 RotR or RotL (depending on the found pattern).
1408 * @return The created ia32 RotL or RotR node
1410 static ir_node *gen_Rot(ir_node *node) {
1411 ir_node *rotate = NULL;
1412 ir_node *op1 = get_Rot_left(node);
1413 ir_node *op2 = get_Rot_right(node);
1415 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1416 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1417 that means we can create a RotR instead of an Add and a RotL */
1419 if (get_irn_op(op2) == op_Add) {
1421 ir_node *left = get_Add_left(add);
1422 ir_node *right = get_Add_right(add);
1423 if (is_Const(right)) {
1424 tarval *tv = get_Const_tarval(right);
1425 ir_mode *mode = get_irn_mode(node);
1426 long bits = get_mode_size_bits(mode);
1428 if (get_irn_op(left) == op_Minus &&
1429 tarval_is_long(tv) &&
1430 get_tarval_long(tv) == bits)
1432 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1433 rotate = gen_RotR(node, op1, get_Minus_op(left));
1438 if (rotate == NULL) {
1439 rotate = gen_RotL(node, op1, op2);
1448 * Transforms a Minus node.
1450 * @param op The Minus operand
1451 * @return The created ia32 Minus node
1453 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1454 ir_node *block = be_transform_node(get_nodes_block(node));
1455 ir_graph *irg = current_ir_graph;
1456 dbg_info *dbgi = get_irn_dbg_info(node);
1457 ir_mode *mode = get_irn_mode(node);
1462 if (mode_is_float(mode)) {
1463 ir_node *new_op = be_transform_node(op);
1465 if (USE_SSE2(env_cg)) {
1466 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1467 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1468 ir_node *nomem = new_rd_NoMem(irg);
1470 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1472 size = get_mode_size_bits(mode);
1473 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1475 set_ia32_am_sc(res, ent);
1476 set_ia32_op_type(res, ia32_AddrModeS);
1477 set_ia32_ls_mode(res, mode);
1479 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1482 res = gen_unop(node, op, new_rd_ia32_Neg);
1485 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1491 * Transforms a Minus node.
1493 * @return The created ia32 Minus node
1495 static ir_node *gen_Minus(ir_node *node) {
1496 return gen_Minus_ex(node, get_Minus_op(node));
1501 * Transforms a Not node.
1503 * @return The created ia32 Not node
1505 static ir_node *gen_Not(ir_node *node) {
1506 ir_node *op = get_Not_op(node);
1508 assert (! mode_is_float(get_irn_mode(node)));
1509 return gen_unop(node, op, new_rd_ia32_Not);
1515 * Transforms an Abs node.
1517 * @return The created ia32 Abs node
1519 static ir_node *gen_Abs(ir_node *node) {
1520 ir_node *block = be_transform_node(get_nodes_block(node));
1521 ir_node *op = get_Abs_op(node);
1522 ir_node *new_op = be_transform_node(op);
1523 ir_graph *irg = current_ir_graph;
1524 dbg_info *dbgi = get_irn_dbg_info(node);
1525 ir_mode *mode = get_irn_mode(node);
1526 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1527 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1528 ir_node *nomem = new_NoMem();
1533 if (mode_is_float(mode)) {
1535 if (USE_SSE2(env_cg)) {
1536 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1538 size = get_mode_size_bits(mode);
1539 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1541 set_ia32_am_sc(res, ent);
1543 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1545 set_ia32_op_type(res, ia32_AddrModeS);
1546 set_ia32_ls_mode(res, mode);
1549 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1550 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1554 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1555 SET_IA32_ORIG_NODE(sign_extension,
1556 ia32_get_old_node_name(env_cg, node));
1558 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1559 sign_extension, nomem);
1560 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1562 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1563 sign_extension, nomem);
1564 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1573 * Transforms a Load.
1575 * @return the created ia32 Load node
1577 static ir_node *gen_Load(ir_node *node) {
1578 ir_node *block = be_transform_node(get_nodes_block(node));
1579 ir_node *ptr = get_Load_ptr(node);
1580 ir_node *new_ptr = be_transform_node(ptr);
1581 ir_node *mem = get_Load_mem(node);
1582 ir_node *new_mem = be_transform_node(mem);
1583 ir_graph *irg = current_ir_graph;
1584 dbg_info *dbgi = get_irn_dbg_info(node);
1585 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1586 ir_mode *mode = get_Load_mode(node);
1588 ir_node *lptr = new_ptr;
1591 ir_node *projs[pn_Load_max];
1592 ia32_am_flavour_t am_flav = ia32_am_B;
1594 ia32_collect_Projs(node, projs, pn_Load_max);
1596 /* address might be a constant (symconst or absolute address) */
1597 if (is_ia32_Const(new_ptr)) {
1602 if (mode_is_float(mode)) {
1604 if (USE_SSE2(env_cg)) {
1605 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1606 res_mode = mode_xmm;
1608 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1609 res_mode = mode_vfp;
1612 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1617 check for special case: the loaded value might not be used
1619 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1620 /* add a result proj and a Keep to produce a pseudo use */
1621 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1623 be_new_Keep(arch_get_irn_reg_class(env_cg->arch_env, proj, -1), irg, block, 1, &proj);
1626 /* base is a constant address */
1628 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1629 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1630 am_flav = ia32_am_N;
1632 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1633 long offs = get_tarval_long(tv);
1635 add_ia32_am_offs_int(new_op, offs);
1636 am_flav = ia32_am_O;
1640 set_irn_pinned(new_op, get_irn_pinned(node));
1641 set_ia32_op_type(new_op, ia32_AddrModeS);
1642 set_ia32_am_flavour(new_op, am_flav);
1643 set_ia32_ls_mode(new_op, mode);
1645 /* make sure we are scheduled behind the initial IncSP/Barrier
1646 * to avoid spills being placed before it
1648 if (block == get_irg_start_block(irg)) {
1649 add_irn_dep(new_op, get_irg_frame(irg));
1652 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1653 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1661 * Transforms a Store.
1663 * @return the created ia32 Store node
1665 static ir_node *gen_Store(ir_node *node) {
1666 ir_node *block = be_transform_node(get_nodes_block(node));
1667 ir_node *ptr = get_Store_ptr(node);
1668 ir_node *new_ptr = be_transform_node(ptr);
1669 ir_node *val = get_Store_value(node);
1671 ir_node *mem = get_Store_mem(node);
1672 ir_node *new_mem = be_transform_node(mem);
1673 ir_graph *irg = current_ir_graph;
1674 dbg_info *dbgi = get_irn_dbg_info(node);
1675 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1676 ir_node *sptr = new_ptr;
1677 ir_mode *mode = get_irn_mode(val);
1680 ia32_am_flavour_t am_flav = ia32_am_B;
1682 /* address might be a constant (symconst or absolute address) */
1683 if (is_ia32_Const(new_ptr)) {
1688 if (mode_is_float(mode)) {
1691 new_val = be_transform_node(val);
1692 if (USE_SSE2(env_cg)) {
1693 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1696 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1700 new_val = create_immediate_or_transform(val, 0);
1702 if (get_mode_size_bits(mode) == 8) {
1703 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1706 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1711 /* base is an constant address */
1713 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1714 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1715 am_flav = ia32_am_N;
1717 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1718 long offs = get_tarval_long(tv);
1720 add_ia32_am_offs_int(new_op, offs);
1721 am_flav = ia32_am_O;
1725 set_irn_pinned(new_op, get_irn_pinned(node));
1726 set_ia32_op_type(new_op, ia32_AddrModeD);
1727 set_ia32_am_flavour(new_op, am_flav);
1728 set_ia32_ls_mode(new_op, mode);
1730 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1731 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1736 static ir_node *try_create_TestJmp(ir_node *node, long pnc)
1738 ir_node *cmp_a = get_Cmp_left(node);
1740 ir_node *cmp_b = get_Cmp_right(node);
1751 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
1754 if(!is_Const(cmp_b))
1757 tv = get_Const_tarval(cmp_b);
1758 if(!tarval_is_null(tv))
1762 /* only fold if we're the only user of the And (it's not 100% clear that
1763 * this is better, as we could have a series of Conds as users...)
1765 if(get_irn_n_edges(cmp_a) > 1)
1768 and_left = get_And_left(cmp_a);
1769 and_right = get_And_right(cmp_a);
1771 dbgi = get_irn_dbg_info(node);
1772 block = be_transform_node(get_nodes_block(node));
1773 noreg = ia32_new_NoReg_gp(env_cg);
1774 nomem = new_NoMem();
1775 new_cmp_a = be_transform_node(and_left);
1776 new_cmp_b = create_immediate_or_transform(and_right, 0);
1778 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1779 new_cmp_a, new_cmp_b, nomem, pnc);
1780 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1785 static ir_node *create_Switch(ir_node *node)
1787 ir_graph *irg = current_ir_graph;
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_node *block = be_transform_node(get_nodes_block(node));
1790 ir_node *sel = get_Cond_selector(node);
1791 ir_node *new_sel = be_transform_node(sel);
1793 int switch_min = INT_MAX;
1794 const ir_edge_t *edge;
1796 /* determine the smallest switch case value */
1797 foreach_out_edge(node, edge) {
1798 ir_node *proj = get_edge_src_irn(edge);
1799 int pn = get_Proj_proj(proj);
1804 if (switch_min != 0) {
1805 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1807 /* if smallest switch case is not 0 we need an additional sub */
1808 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1809 add_ia32_am_offs_int(new_sel, -switch_min);
1810 set_ia32_am_flavour(new_sel, ia32_am_OB);
1811 set_ia32_op_type(new_sel, ia32_AddrModeS);
1813 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1816 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1817 set_ia32_pncode(res, get_Cond_defaultProj(node));
1819 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1825 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1827 * @return The transformed node.
1829 static ir_node *gen_Cond(ir_node *node) {
1830 ir_node *block = be_transform_node(get_nodes_block(node));
1831 ir_graph *irg = current_ir_graph;
1832 dbg_info *dbgi = get_irn_dbg_info(node);
1833 ir_node *sel = get_Cond_selector(node);
1834 ir_mode *sel_mode = get_irn_mode(sel);
1835 ir_node *res = NULL;
1836 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1843 ir_node *nomem = new_NoMem();
1846 if (sel_mode != mode_b) {
1847 return create_Switch(node);
1850 cmp = get_Proj_pred(sel);
1851 cmp_a = get_Cmp_left(cmp);
1852 cmp_b = get_Cmp_right(cmp);
1853 cmp_mode = get_irn_mode(cmp_a);
1854 pnc = get_Proj_proj(sel);
1855 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1856 pnc |= ia32_pn_Cmp_Unsigned;
1859 if(mode_needs_gp_reg(cmp_mode)) {
1860 res = try_create_TestJmp(cmp, pnc);
1865 new_cmp_a = be_transform_node(cmp_a);
1866 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1868 if (mode_is_float(cmp_mode)) {
1870 if (USE_SSE2(env_cg)) {
1871 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1872 set_ia32_pncode(res, pnc);
1873 set_ia32_ls_mode(res, cmp_mode);
1876 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1877 set_ia32_pncode(res, pnc);
1878 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1879 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1882 assert(get_mode_size_bits(cmp_mode) == 32);
1883 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1884 new_cmp_a, new_cmp_b, nomem, pnc);
1885 set_ia32_commutative(res);
1888 // Matze: disabled for now, because the default collect_spills_walker
1889 // is not able to detect the mode of the spilled value
1890 // moreover, the lea optimize phase freely exchanges left/right
1891 // without updating the pnc
1892 //set_ia32_am_support(res, ia32_am_Source | ia32_am_binary);
1894 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1902 * Transforms a CopyB node.
1904 * @return The transformed node.
1906 static ir_node *gen_CopyB(ir_node *node) {
1907 ir_node *block = be_transform_node(get_nodes_block(node));
1908 ir_node *src = get_CopyB_src(node);
1909 ir_node *new_src = be_transform_node(src);
1910 ir_node *dst = get_CopyB_dst(node);
1911 ir_node *new_dst = be_transform_node(dst);
1912 ir_node *mem = get_CopyB_mem(node);
1913 ir_node *new_mem = be_transform_node(mem);
1914 ir_node *res = NULL;
1915 ir_graph *irg = current_ir_graph;
1916 dbg_info *dbgi = get_irn_dbg_info(node);
1917 int size = get_type_size_bytes(get_CopyB_type(node));
1918 ir_mode *dst_mode = get_irn_mode(dst);
1919 ir_mode *src_mode = get_irn_mode(src);
1923 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1924 /* then we need the size explicitly in ECX. */
1925 if (size >= 32 * 4) {
1926 rem = size & 0x3; /* size % 4 */
1929 res = new_rd_ia32_Const(dbgi, irg, block);
1930 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1931 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1933 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1934 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1936 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1937 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1938 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1939 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1940 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1943 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1944 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1946 /* ok: now attach Proj's because movsd will destroy esi and edi */
1947 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1948 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1949 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1952 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1958 ir_node *gen_be_Copy(ir_node *node)
1960 ir_node *result = be_duplicate_node(node);
1961 ir_mode *mode = get_irn_mode(result);
1963 if (mode_needs_gp_reg(mode)) {
1964 set_irn_mode(result, mode_Iu);
1973 * Transforms a Mux node into CMov.
1975 * @return The transformed node.
1977 static ir_node *gen_Mux(ir_node *node) {
1978 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, current_ir_graph, env.block, \
1979 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1981 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1987 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1988 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1989 ir_node *psi_default);
1992 * Transforms a Psi node into CMov.
1994 * @return The transformed node.
1996 static ir_node *gen_Psi(ir_node *node) {
1997 ir_node *block = be_transform_node(get_nodes_block(node));
1998 ir_node *psi_true = get_Psi_val(node, 0);
1999 ir_node *psi_default = get_Psi_default(node);
2000 ia32_code_gen_t *cg = env_cg;
2001 ir_graph *irg = current_ir_graph;
2002 dbg_info *dbgi = get_irn_dbg_info(node);
2003 ir_node *cond = get_Psi_cond(node, 0);
2004 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2005 ir_node *nomem = new_NoMem();
2007 ir_node *cmp, *cmp_a, *cmp_b;
2008 ir_node *new_cmp_a, *new_cmp_b;
2012 assert(get_Psi_n_conds(node) == 1);
2013 assert(get_irn_mode(cond) == mode_b);
2015 if(is_And(cond) || is_Or(cond)) {
2016 ir_node *new_cond = be_transform_node(cond);
2017 ir_node *zero = new_rd_ia32_Immediate(NULL, irg, block, NULL, 0, 0);
2018 arch_set_irn_register(env_cg->arch_env, zero,
2019 &ia32_gp_regs[REG_GP_NOREG]);
2021 /* we have to compare the result against zero */
2022 new_cmp_a = new_cond;
2027 cmp = get_Proj_pred(cond);
2028 cmp_a = get_Cmp_left(cmp);
2029 cmp_b = get_Cmp_right(cmp);
2030 cmp_mode = get_irn_mode(cmp_a);
2031 pnc = get_Proj_proj(cond);
2033 new_cmp_a = be_transform_node(cmp_a);
2034 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2036 if (!mode_is_signed(cmp_mode)) {
2037 pnc |= ia32_pn_Cmp_Unsigned;
2041 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2042 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2043 new_cmp_a, new_cmp_b, nomem, pnc);
2044 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2045 pnc = get_negated_pnc(pnc, cmp_mode);
2046 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
2047 new_cmp_a, new_cmp_b, nomem, pnc);
2049 ir_node *new_psi_true = be_transform_node(psi_true);
2050 ir_node *new_psi_default = be_transform_node(psi_default);
2051 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_cmp_a, new_cmp_b,
2052 new_psi_true, new_psi_default, pnc);
2054 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2060 * Following conversion rules apply:
2064 * 1) n bit -> m bit n > m (downscale)
2066 * 2) n bit -> m bit n == m (sign change)
2068 * 3) n bit -> m bit n < m (upscale)
2069 * a) source is signed: movsx
2070 * b) source is unsigned: and with lower bits sets
2074 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2078 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2082 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2083 * x87 is mode_E internally, conversions happen only at load and store
2084 * in non-strict semantic
2088 * Create a conversion from x87 state register to general purpose.
2090 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2091 ir_node *block = be_transform_node(get_nodes_block(node));
2092 ir_node *op = get_Conv_op(node);
2093 ir_node *new_op = be_transform_node(op);
2094 ia32_code_gen_t *cg = env_cg;
2095 ir_graph *irg = current_ir_graph;
2096 dbg_info *dbgi = get_irn_dbg_info(node);
2097 ir_node *noreg = ia32_new_NoReg_gp(cg);
2098 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2099 ir_node *fist, *load;
2102 fist = new_rd_ia32_vfist(dbgi, irg, block,
2103 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2105 set_irn_pinned(fist, op_pin_state_floats);
2106 set_ia32_use_frame(fist);
2107 set_ia32_op_type(fist, ia32_AddrModeD);
2108 set_ia32_am_flavour(fist, ia32_am_B);
2109 set_ia32_ls_mode(fist, mode_Iu);
2110 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2113 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2115 set_irn_pinned(load, op_pin_state_floats);
2116 set_ia32_use_frame(load);
2117 set_ia32_op_type(load, ia32_AddrModeS);
2118 set_ia32_am_flavour(load, ia32_am_B);
2119 set_ia32_ls_mode(load, mode_Iu);
2120 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2122 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2126 * Create a conversion from general purpose to x87 register
2128 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2129 ir_node *block = be_transform_node(get_nodes_block(node));
2130 ir_node *op = get_Conv_op(node);
2131 ir_node *new_op = be_transform_node(op);
2132 ir_graph *irg = current_ir_graph;
2133 dbg_info *dbgi = get_irn_dbg_info(node);
2134 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2135 ir_node *nomem = new_NoMem();
2136 ir_node *fild, *store;
2139 /* first convert to 32 bit if necessary */
2140 src_bits = get_mode_size_bits(src_mode);
2141 if (src_bits == 8) {
2142 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2143 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2144 set_ia32_ls_mode(new_op, src_mode);
2145 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2146 } else if (src_bits < 32) {
2147 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2148 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2149 set_ia32_ls_mode(new_op, src_mode);
2150 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2154 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2156 set_ia32_use_frame(store);
2157 set_ia32_op_type(store, ia32_AddrModeD);
2158 set_ia32_am_flavour(store, ia32_am_OB);
2159 set_ia32_ls_mode(store, mode_Iu);
2162 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2164 set_ia32_use_frame(fild);
2165 set_ia32_op_type(fild, ia32_AddrModeS);
2166 set_ia32_am_flavour(fild, ia32_am_OB);
2167 set_ia32_ls_mode(fild, mode_Iu);
2169 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2172 static ir_node *create_Strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2175 ir_node *block = get_nodes_block(node);
2176 ir_graph *irg = current_ir_graph;
2177 dbg_info *dbgi = get_irn_dbg_info(node);
2178 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2179 ir_node *nomem = new_NoMem();
2180 int src_bits = get_mode_size_bits(src_mode);
2181 int tgt_bits = get_mode_size_bits(tgt_mode);
2182 ir_node *frame = get_irg_frame(irg);
2183 ir_mode *smaller_mode;
2184 ir_node *store, *load;
2187 if(src_bits <= tgt_bits)
2188 smaller_mode = src_mode;
2190 smaller_mode = tgt_mode;
2192 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2194 set_ia32_use_frame(store);
2195 set_ia32_op_type(store, ia32_AddrModeD);
2196 set_ia32_am_flavour(store, ia32_am_OB);
2198 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2200 set_ia32_use_frame(load);
2201 set_ia32_op_type(load, ia32_AddrModeS);
2202 set_ia32_am_flavour(load, ia32_am_OB);
2204 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2209 * Transforms a Conv node.
2211 * @return The created ia32 Conv node
2213 static ir_node *gen_Conv(ir_node *node) {
2214 ir_node *block = be_transform_node(get_nodes_block(node));
2215 ir_node *op = get_Conv_op(node);
2216 ir_node *new_op = be_transform_node(op);
2217 ir_graph *irg = current_ir_graph;
2218 dbg_info *dbgi = get_irn_dbg_info(node);
2219 ir_mode *src_mode = get_irn_mode(op);
2220 ir_mode *tgt_mode = get_irn_mode(node);
2221 int src_bits = get_mode_size_bits(src_mode);
2222 int tgt_bits = get_mode_size_bits(tgt_mode);
2223 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2224 ir_node *nomem = new_rd_NoMem(irg);
2227 if (src_mode == tgt_mode) {
2228 if (get_Conv_strict(node)) {
2229 if (USE_SSE2(env_cg)) {
2230 /* when we are in SSE mode, we can kill all strict no-op conversion */
2234 /* this should be optimized already, but who knows... */
2235 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2236 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2241 if (mode_is_float(src_mode)) {
2242 /* we convert from float ... */
2243 if (mode_is_float(tgt_mode)) {
2244 if(src_mode == mode_E && tgt_mode == mode_D
2245 && !get_Conv_strict(node)) {
2246 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2251 if (USE_SSE2(env_cg)) {
2252 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2253 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2254 set_ia32_ls_mode(res, tgt_mode);
2256 // Matze: TODO what about strict convs?
2257 if(get_Conv_strict(node)) {
2258 res = create_Strict_conv(src_mode, tgt_mode, new_op);
2259 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2262 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2267 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2268 if (USE_SSE2(env_cg)) {
2269 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2270 set_ia32_ls_mode(res, src_mode);
2272 return gen_x87_fp_to_gp(node);
2276 /* we convert from int ... */
2277 if (mode_is_float(tgt_mode)) {
2280 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2281 if (USE_SSE2(env_cg)) {
2282 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2283 set_ia32_ls_mode(res, tgt_mode);
2284 if(src_bits == 32) {
2285 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2288 return gen_x87_gp_to_fp(node, src_mode);
2292 ir_mode *smaller_mode;
2295 if (src_bits == tgt_bits) {
2296 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2300 if (src_bits < tgt_bits) {
2301 smaller_mode = src_mode;
2302 smaller_bits = src_bits;
2304 smaller_mode = tgt_mode;
2305 smaller_bits = tgt_bits;
2308 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2309 if (smaller_bits == 8) {
2310 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2311 set_ia32_ls_mode(res, smaller_mode);
2313 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2314 set_ia32_ls_mode(res, smaller_mode);
2316 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2320 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2326 int check_immediate_constraint(long val, char immediate_constraint_type)
2328 switch (immediate_constraint_type) {
2332 return val >= 0 && val <= 32;
2334 return val >= 0 && val <= 63;
2336 return val >= -128 && val <= 127;
2338 return val == 0xff || val == 0xffff;
2340 return val >= 0 && val <= 3;
2342 return val >= 0 && val <= 255;
2344 return val >= 0 && val <= 127;
2348 panic("Invalid immediate constraint found");
2353 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2356 tarval *offset = NULL;
2357 int offset_sign = 0;
2359 ir_entity *symconst_ent = NULL;
2360 int symconst_sign = 0;
2362 ir_node *cnst = NULL;
2363 ir_node *symconst = NULL;
2369 mode = get_irn_mode(node);
2370 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2371 !mode_is_reference(mode)) {
2375 if(is_Minus(node)) {
2377 node = get_Minus_op(node);
2380 if(is_Const(node)) {
2383 offset_sign = minus;
2384 } else if(is_SymConst(node)) {
2387 symconst_sign = minus;
2388 } else if(is_Add(node)) {
2389 ir_node *left = get_Add_left(node);
2390 ir_node *right = get_Add_right(node);
2391 if(is_Const(left) && is_SymConst(right)) {
2394 symconst_sign = minus;
2395 offset_sign = minus;
2396 } else if(is_SymConst(left) && is_Const(right)) {
2399 symconst_sign = minus;
2400 offset_sign = minus;
2402 } else if(is_Sub(node)) {
2403 ir_node *left = get_Sub_left(node);
2404 ir_node *right = get_Sub_right(node);
2405 if(is_Const(left) && is_SymConst(right)) {
2408 symconst_sign = !minus;
2409 offset_sign = minus;
2410 } else if(is_SymConst(left) && is_Const(right)) {
2413 symconst_sign = minus;
2414 offset_sign = !minus;
2421 offset = get_Const_tarval(cnst);
2422 if(tarval_is_long(offset)) {
2423 val = get_tarval_long(offset);
2424 } else if(tarval_is_null(offset)) {
2427 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2432 if(!check_immediate_constraint(val, immediate_constraint_type))
2435 if(symconst != NULL) {
2436 if(immediate_constraint_type != 0) {
2437 /* we need full 32bits for symconsts */
2441 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2443 symconst_ent = get_SymConst_entity(symconst);
2445 if(cnst == NULL && symconst == NULL)
2448 if(offset_sign && offset != NULL) {
2449 offset = tarval_neg(offset);
2452 irg = current_ir_graph;
2453 dbgi = get_irn_dbg_info(node);
2454 block = get_irg_start_block(irg);
2455 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2457 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2459 /* make sure we don't schedule stuff before the barrier */
2460 add_irn_dep(res, get_irg_frame(irg));
2466 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2468 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2469 if (new_node == NULL) {
2470 new_node = be_transform_node(node);
2475 typedef struct constraint_t constraint_t;
2476 struct constraint_t {
2479 const arch_register_req_t **out_reqs;
2481 const arch_register_req_t *req;
2482 unsigned immediate_possible;
2483 char immediate_type;
2486 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2488 int immediate_possible = 0;
2489 char immediate_type = 0;
2490 unsigned limited = 0;
2491 const arch_register_class_t *cls = NULL;
2493 struct obstack *obst;
2494 arch_register_req_t *req;
2495 unsigned *limited_ptr;
2499 /* TODO: replace all the asserts with nice error messages */
2501 printf("Constraint: %s\n", c);
2511 assert(cls == NULL ||
2512 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2513 cls = &ia32_reg_classes[CLASS_ia32_gp];
2514 limited |= 1 << REG_EAX;
2517 assert(cls == NULL ||
2518 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2519 cls = &ia32_reg_classes[CLASS_ia32_gp];
2520 limited |= 1 << REG_EBX;
2523 assert(cls == NULL ||
2524 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2525 cls = &ia32_reg_classes[CLASS_ia32_gp];
2526 limited |= 1 << REG_ECX;
2529 assert(cls == NULL ||
2530 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2531 cls = &ia32_reg_classes[CLASS_ia32_gp];
2532 limited |= 1 << REG_EDX;
2535 assert(cls == NULL ||
2536 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2537 cls = &ia32_reg_classes[CLASS_ia32_gp];
2538 limited |= 1 << REG_EDI;
2541 assert(cls == NULL ||
2542 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2543 cls = &ia32_reg_classes[CLASS_ia32_gp];
2544 limited |= 1 << REG_ESI;
2547 case 'q': /* q means lower part of the regs only, this makes no
2548 * difference to Q for us (we only assigne whole registers) */
2549 assert(cls == NULL ||
2550 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2551 cls = &ia32_reg_classes[CLASS_ia32_gp];
2552 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2556 assert(cls == NULL ||
2557 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2558 cls = &ia32_reg_classes[CLASS_ia32_gp];
2559 limited |= 1 << REG_EAX | 1 << REG_EDX;
2562 assert(cls == NULL ||
2563 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2564 cls = &ia32_reg_classes[CLASS_ia32_gp];
2565 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2566 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2573 assert(cls == NULL);
2574 cls = &ia32_reg_classes[CLASS_ia32_gp];
2580 /* TODO: mark values so the x87 simulator knows about t and u */
2581 assert(cls == NULL);
2582 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2587 assert(cls == NULL);
2588 /* TODO: check that sse2 is supported */
2589 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2599 assert(!immediate_possible);
2600 immediate_possible = 1;
2601 immediate_type = *c;
2605 assert(!immediate_possible);
2606 immediate_possible = 1;
2610 assert(!immediate_possible && cls == NULL);
2611 immediate_possible = 1;
2612 cls = &ia32_reg_classes[CLASS_ia32_gp];
2625 assert(constraint->is_in && "can only specify same constraint "
2628 sscanf(c, "%d%n", &same_as, &p);
2635 case 'E': /* no float consts yet */
2636 case 'F': /* no float consts yet */
2637 case 's': /* makes no sense on x86 */
2638 case 'X': /* we can't support that in firm */
2642 case '<': /* no autodecrement on x86 */
2643 case '>': /* no autoincrement on x86 */
2644 case 'C': /* sse constant not supported yet */
2645 case 'G': /* 80387 constant not supported yet */
2646 case 'y': /* we don't support mmx registers yet */
2647 case 'Z': /* not available in 32 bit mode */
2648 case 'e': /* not available in 32 bit mode */
2649 assert(0 && "asm constraint not supported");
2652 assert(0 && "unknown asm constraint found");
2659 const arch_register_req_t *other_constr;
2661 assert(cls == NULL && "same as and register constraint not supported");
2662 assert(!immediate_possible && "same as and immediate constraint not "
2664 assert(same_as < constraint->n_outs && "wrong constraint number in "
2665 "same_as constraint");
2667 other_constr = constraint->out_reqs[same_as];
2669 req = obstack_alloc(obst, sizeof(req[0]));
2670 req->cls = other_constr->cls;
2671 req->type = arch_register_req_type_should_be_same;
2672 req->limited = NULL;
2673 req->other_same = pos;
2674 req->other_different = -1;
2676 /* switch constraints. This is because in firm we have same_as
2677 * constraints on the output constraints while in the gcc asm syntax
2678 * they are specified on the input constraints */
2679 constraint->req = other_constr;
2680 constraint->out_reqs[same_as] = req;
2681 constraint->immediate_possible = 0;
2685 if(immediate_possible && cls == NULL) {
2686 cls = &ia32_reg_classes[CLASS_ia32_gp];
2688 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2689 assert(cls != NULL);
2691 if(immediate_possible) {
2692 assert(constraint->is_in
2693 && "imeediates make no sense for output constraints");
2695 /* todo: check types (no float input on 'r' constrainted in and such... */
2697 irg = current_ir_graph;
2698 obst = get_irg_obstack(irg);
2701 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2702 limited_ptr = (unsigned*) (req+1);
2704 req = obstack_alloc(obst, sizeof(req[0]));
2706 memset(req, 0, sizeof(req[0]));
2709 req->type = arch_register_req_type_limited;
2710 *limited_ptr = limited;
2711 req->limited = limited_ptr;
2713 req->type = arch_register_req_type_normal;
2717 constraint->req = req;
2718 constraint->immediate_possible = immediate_possible;
2719 constraint->immediate_type = immediate_type;
2723 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2730 panic("Clobbers not supported yet");
2733 ir_node *gen_ASM(ir_node *node)
2736 ir_graph *irg = current_ir_graph;
2737 ir_node *block = be_transform_node(get_nodes_block(node));
2738 dbg_info *dbgi = get_irn_dbg_info(node);
2745 ia32_asm_attr_t *attr;
2746 const arch_register_req_t **out_reqs;
2747 const arch_register_req_t **in_reqs;
2748 struct obstack *obst;
2749 constraint_t parsed_constraint;
2751 /* assembler could contain float statements */
2754 /* transform inputs */
2755 arity = get_irn_arity(node);
2756 in = alloca(arity * sizeof(in[0]));
2757 memset(in, 0, arity * sizeof(in[0]));
2759 n_outs = get_ASM_n_output_constraints(node);
2760 n_clobbers = get_ASM_n_clobbers(node);
2761 out_arity = n_outs + n_clobbers;
2763 /* construct register constraints */
2764 obst = get_irg_obstack(irg);
2765 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2766 parsed_constraint.out_reqs = out_reqs;
2767 parsed_constraint.n_outs = n_outs;
2768 parsed_constraint.is_in = 0;
2769 for(i = 0; i < out_arity; ++i) {
2773 const ir_asm_constraint *constraint;
2774 constraint = & get_ASM_output_constraints(node) [i];
2775 c = get_id_str(constraint->constraint);
2776 parse_asm_constraint(i, &parsed_constraint, c);
2778 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2779 c = get_id_str(glob_id);
2780 parse_clobber(node, i, &parsed_constraint, c);
2782 out_reqs[i] = parsed_constraint.req;
2785 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2786 parsed_constraint.is_in = 1;
2787 for(i = 0; i < arity; ++i) {
2788 const ir_asm_constraint *constraint;
2792 constraint = & get_ASM_input_constraints(node) [i];
2793 constr_id = constraint->constraint;
2794 c = get_id_str(constr_id);
2795 parse_asm_constraint(i, &parsed_constraint, c);
2796 in_reqs[i] = parsed_constraint.req;
2798 if(parsed_constraint.immediate_possible) {
2799 ir_node *pred = get_irn_n(node, i);
2800 char imm_type = parsed_constraint.immediate_type;
2801 ir_node *immediate = try_create_Immediate(pred, imm_type);
2803 if(immediate != NULL) {
2809 /* transform inputs */
2810 for(i = 0; i < arity; ++i) {
2812 ir_node *transformed;
2817 pred = get_irn_n(node, i);
2818 transformed = be_transform_node(pred);
2819 in[i] = transformed;
2822 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2824 generic_attr = get_irn_generic_attr(res);
2825 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2826 attr->asm_text = get_ASM_text(node);
2827 set_ia32_out_req_all(res, out_reqs);
2828 set_ia32_in_req_all(res, in_reqs);
2830 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2835 /********************************************
2838 * | |__ ___ _ __ ___ __| | ___ ___
2839 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2840 * | |_) | __/ | | | (_) | (_| | __/\__ \
2841 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2843 ********************************************/
2845 static ir_node *gen_be_StackParam(ir_node *node) {
2846 ir_node *block = be_transform_node(get_nodes_block(node));
2847 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2848 ir_node *new_ptr = be_transform_node(ptr);
2849 ir_node *new_op = NULL;
2850 ir_graph *irg = current_ir_graph;
2851 dbg_info *dbgi = get_irn_dbg_info(node);
2852 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2853 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2854 ir_mode *load_mode = get_irn_mode(node);
2855 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2859 if (mode_is_float(load_mode)) {
2861 if (USE_SSE2(env_cg)) {
2862 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2863 pn_res = pn_ia32_xLoad_res;
2864 proj_mode = mode_xmm;
2866 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2867 pn_res = pn_ia32_vfld_res;
2868 proj_mode = mode_vfp;
2871 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2872 proj_mode = mode_Iu;
2873 pn_res = pn_ia32_Load_res;
2876 set_irn_pinned(new_op, op_pin_state_floats);
2877 set_ia32_frame_ent(new_op, ent);
2878 set_ia32_use_frame(new_op);
2880 set_ia32_op_type(new_op, ia32_AddrModeS);
2881 set_ia32_am_flavour(new_op, ia32_am_B);
2882 set_ia32_ls_mode(new_op, load_mode);
2883 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2885 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2887 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2891 * Transforms a FrameAddr into an ia32 Add.
2893 static ir_node *gen_be_FrameAddr(ir_node *node) {
2894 ir_node *block = be_transform_node(get_nodes_block(node));
2895 ir_node *op = be_get_FrameAddr_frame(node);
2896 ir_node *new_op = be_transform_node(op);
2897 ir_graph *irg = current_ir_graph;
2898 dbg_info *dbgi = get_irn_dbg_info(node);
2899 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2902 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2903 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2904 set_ia32_use_frame(res);
2905 set_ia32_am_flavour(res, ia32_am_OB);
2907 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2913 * Transforms a FrameLoad into an ia32 Load.
2915 static ir_node *gen_be_FrameLoad(ir_node *node) {
2916 ir_node *block = be_transform_node(get_nodes_block(node));
2917 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2918 ir_node *new_mem = be_transform_node(mem);
2919 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2920 ir_node *new_ptr = be_transform_node(ptr);
2921 ir_node *new_op = NULL;
2922 ir_graph *irg = current_ir_graph;
2923 dbg_info *dbgi = get_irn_dbg_info(node);
2924 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2925 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2926 ir_mode *mode = get_type_mode(get_entity_type(ent));
2927 ir_node *projs[pn_Load_max];
2929 ia32_collect_Projs(node, projs, pn_Load_max);
2931 if (mode_is_float(mode)) {
2933 if (USE_SSE2(env_cg)) {
2934 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2937 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2941 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2944 set_irn_pinned(new_op, op_pin_state_floats);
2945 set_ia32_frame_ent(new_op, ent);
2946 set_ia32_use_frame(new_op);
2948 set_ia32_op_type(new_op, ia32_AddrModeS);
2949 set_ia32_am_flavour(new_op, ia32_am_B);
2950 set_ia32_ls_mode(new_op, mode);
2951 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2953 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2960 * Transforms a FrameStore into an ia32 Store.
2962 static ir_node *gen_be_FrameStore(ir_node *node) {
2963 ir_node *block = be_transform_node(get_nodes_block(node));
2964 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2965 ir_node *new_mem = be_transform_node(mem);
2966 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2967 ir_node *new_ptr = be_transform_node(ptr);
2968 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2969 ir_node *new_val = be_transform_node(val);
2970 ir_node *new_op = NULL;
2971 ir_graph *irg = current_ir_graph;
2972 dbg_info *dbgi = get_irn_dbg_info(node);
2973 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2974 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2975 ir_mode *mode = get_irn_mode(val);
2977 if (mode_is_float(mode)) {
2979 if (USE_SSE2(env_cg)) {
2980 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2982 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2984 } else if (get_mode_size_bits(mode) == 8) {
2985 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2987 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2990 set_ia32_frame_ent(new_op, ent);
2991 set_ia32_use_frame(new_op);
2993 set_ia32_op_type(new_op, ia32_AddrModeD);
2994 set_ia32_am_flavour(new_op, ia32_am_B);
2995 set_ia32_ls_mode(new_op, mode);
2997 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3003 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3005 static ir_node *gen_be_Return(ir_node *node) {
3006 ir_graph *irg = current_ir_graph;
3007 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3008 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3009 ir_entity *ent = get_irg_entity(irg);
3010 ir_type *tp = get_entity_type(ent);
3015 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3016 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3019 int pn_ret_val, pn_ret_mem, arity, i;
3021 assert(ret_val != NULL);
3022 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3023 return be_duplicate_node(node);
3026 res_type = get_method_res_type(tp, 0);
3028 if (! is_Primitive_type(res_type)) {
3029 return be_duplicate_node(node);
3032 mode = get_type_mode(res_type);
3033 if (! mode_is_float(mode)) {
3034 return be_duplicate_node(node);
3037 assert(get_method_n_ress(tp) == 1);
3039 pn_ret_val = get_Proj_proj(ret_val);
3040 pn_ret_mem = get_Proj_proj(ret_mem);
3042 /* get the Barrier */
3043 barrier = get_Proj_pred(ret_val);
3045 /* get result input of the Barrier */
3046 ret_val = get_irn_n(barrier, pn_ret_val);
3047 new_ret_val = be_transform_node(ret_val);
3049 /* get memory input of the Barrier */
3050 ret_mem = get_irn_n(barrier, pn_ret_mem);
3051 new_ret_mem = be_transform_node(ret_mem);
3053 frame = get_irg_frame(irg);
3055 dbgi = get_irn_dbg_info(barrier);
3056 block = be_transform_node(get_nodes_block(barrier));
3058 noreg = ia32_new_NoReg_gp(env_cg);
3060 /* store xmm0 onto stack */
3061 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3062 set_ia32_ls_mode(sse_store, mode);
3063 set_ia32_op_type(sse_store, ia32_AddrModeD);
3064 set_ia32_use_frame(sse_store);
3065 set_ia32_am_flavour(sse_store, ia32_am_B);
3068 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3069 set_ia32_ls_mode(fld, mode);
3070 set_ia32_op_type(fld, ia32_AddrModeS);
3071 set_ia32_use_frame(fld);
3072 set_ia32_am_flavour(fld, ia32_am_B);
3074 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3075 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3076 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3078 /* create a new barrier */
3079 arity = get_irn_arity(barrier);
3080 in = alloca(arity * sizeof(in[0]));
3081 for (i = 0; i < arity; ++i) {
3084 if (i == pn_ret_val) {
3086 } else if (i == pn_ret_mem) {
3089 ir_node *in = get_irn_n(barrier, i);
3090 new_in = be_transform_node(in);
3095 new_barrier = new_ir_node(dbgi, irg, block,
3096 get_irn_op(barrier), get_irn_mode(barrier),
3098 copy_node_attr(barrier, new_barrier);
3099 be_duplicate_deps(barrier, new_barrier);
3100 be_set_transformed_node(barrier, new_barrier);
3101 mark_irn_visited(barrier);
3103 /* transform normally */
3104 return be_duplicate_node(node);
3108 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3110 static ir_node *gen_be_AddSP(ir_node *node) {
3111 ir_node *block = be_transform_node(get_nodes_block(node));
3112 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3114 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3115 ir_node *new_sp = be_transform_node(sp);
3116 ir_graph *irg = current_ir_graph;
3117 dbg_info *dbgi = get_irn_dbg_info(node);
3118 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3119 ir_node *nomem = new_NoMem();
3122 new_sz = create_immediate_or_transform(sz, 0);
3124 /* ia32 stack grows in reverse direction, make a SubSP */
3125 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3127 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3134 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3136 static ir_node *gen_be_SubSP(ir_node *node) {
3137 ir_node *block = be_transform_node(get_nodes_block(node));
3138 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3140 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3141 ir_node *new_sp = be_transform_node(sp);
3142 ir_graph *irg = current_ir_graph;
3143 dbg_info *dbgi = get_irn_dbg_info(node);
3144 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3145 ir_node *nomem = new_NoMem();
3148 new_sz = create_immediate_or_transform(sz, 0);
3150 /* ia32 stack grows in reverse direction, make an AddSP */
3151 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3152 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3153 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3159 * This function just sets the register for the Unknown node
3160 * as this is not done during register allocation because Unknown
3161 * is an "ignore" node.
3163 static ir_node *gen_Unknown(ir_node *node) {
3164 ir_mode *mode = get_irn_mode(node);
3166 if (mode_is_float(mode)) {
3167 if (USE_SSE2(env_cg))
3168 return ia32_new_Unknown_xmm(env_cg);
3170 return ia32_new_Unknown_vfp(env_cg);
3171 } else if (mode_needs_gp_reg(mode)) {
3172 return ia32_new_Unknown_gp(env_cg);
3174 assert(0 && "unsupported Unknown-Mode");
3181 * Change some phi modes
3183 static ir_node *gen_Phi(ir_node *node) {
3184 ir_node *block = be_transform_node(get_nodes_block(node));
3185 ir_graph *irg = current_ir_graph;
3186 dbg_info *dbgi = get_irn_dbg_info(node);
3187 ir_mode *mode = get_irn_mode(node);
3190 if(mode_needs_gp_reg(mode)) {
3191 /* we shouldn't have any 64bit stuff around anymore */
3192 assert(get_mode_size_bits(mode) <= 32);
3193 /* all integer operations are on 32bit registers now */
3195 } else if(mode_is_float(mode)) {
3196 if (USE_SSE2(env_cg)) {
3203 /* phi nodes allow loops, so we use the old arguments for now
3204 * and fix this later */
3205 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3206 copy_node_attr(node, phi);
3207 be_duplicate_deps(node, phi);
3209 be_set_transformed_node(node, phi);
3210 be_enqueue_preds(node);
3215 /**********************************************************************
3218 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3219 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3220 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3221 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3223 **********************************************************************/
3225 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3227 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3230 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3231 ir_node *val, ir_node *mem);
3234 * Transforms a lowered Load into a "real" one.
3236 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3237 ir_node *block = be_transform_node(get_nodes_block(node));
3238 ir_node *ptr = get_irn_n(node, 0);
3239 ir_node *new_ptr = be_transform_node(ptr);
3240 ir_node *mem = get_irn_n(node, 1);
3241 ir_node *new_mem = be_transform_node(mem);
3242 ir_graph *irg = current_ir_graph;
3243 dbg_info *dbgi = get_irn_dbg_info(node);
3244 ir_mode *mode = get_ia32_ls_mode(node);
3245 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3249 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3250 lowering we have x87 nodes, so we need to enforce simulation.
3252 if (mode_is_float(mode)) {
3254 if (fp_unit == fp_x87)
3258 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3260 set_ia32_op_type(new_op, ia32_AddrModeS);
3261 set_ia32_am_flavour(new_op, ia32_am_OB);
3262 set_ia32_am_offs_int(new_op, 0);
3263 set_ia32_am_scale(new_op, 1);
3264 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3265 if (is_ia32_am_sc_sign(node))
3266 set_ia32_am_sc_sign(new_op);
3267 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3268 if (is_ia32_use_frame(node)) {
3269 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3270 set_ia32_use_frame(new_op);
3273 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3279 * Transforms a lowered Store into a "real" one.
3281 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3282 ir_node *block = be_transform_node(get_nodes_block(node));
3283 ir_node *ptr = get_irn_n(node, 0);
3284 ir_node *new_ptr = be_transform_node(ptr);
3285 ir_node *val = get_irn_n(node, 1);
3286 ir_node *new_val = be_transform_node(val);
3287 ir_node *mem = get_irn_n(node, 2);
3288 ir_node *new_mem = be_transform_node(mem);
3289 ir_graph *irg = current_ir_graph;
3290 dbg_info *dbgi = get_irn_dbg_info(node);
3291 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3292 ir_mode *mode = get_ia32_ls_mode(node);
3295 ia32_am_flavour_t am_flav = ia32_B;
3298 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3299 lowering we have x87 nodes, so we need to enforce simulation.
3301 if (mode_is_float(mode)) {
3303 if (fp_unit == fp_x87)
3307 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3309 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3311 add_ia32_am_offs_int(new_op, am_offs);
3314 set_ia32_op_type(new_op, ia32_AddrModeD);
3315 set_ia32_am_flavour(new_op, am_flav);
3316 set_ia32_ls_mode(new_op, mode);
3317 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3318 set_ia32_use_frame(new_op);
3320 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3327 * Transforms an ia32_l_XXX into a "real" XXX node
3329 * @param env The transformation environment
3330 * @return the created ia32 XXX node
3332 #define GEN_LOWERED_OP(op) \
3333 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3334 ir_mode *mode = get_irn_mode(node); \
3335 if (mode_is_float(mode)) \
3337 return gen_binop(node, get_binop_left(node), \
3338 get_binop_right(node), new_rd_ia32_##op,0); \
3341 #define GEN_LOWERED_x87_OP(op) \
3342 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3344 FORCE_x87(env_cg); \
3345 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3346 get_binop_right(node), new_rd_ia32_##op); \
3350 #define GEN_LOWERED_UNOP(op) \
3351 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3352 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3355 #define GEN_LOWERED_SHIFT_OP(op) \
3356 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3357 return gen_shift_binop(node, get_binop_left(node), \
3358 get_binop_right(node), new_rd_ia32_##op); \
3361 #define GEN_LOWERED_LOAD(op, fp_unit) \
3362 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3363 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3366 #define GEN_LOWERED_STORE(op, fp_unit) \
3367 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3368 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3375 GEN_LOWERED_OP(IMul)
3377 GEN_LOWERED_x87_OP(vfprem)
3378 GEN_LOWERED_x87_OP(vfmul)
3379 GEN_LOWERED_x87_OP(vfsub)
3381 GEN_LOWERED_UNOP(Neg)
3383 GEN_LOWERED_LOAD(vfild, fp_x87)
3384 GEN_LOWERED_LOAD(Load, fp_none)
3385 /*GEN_LOWERED_STORE(vfist, fp_x87)
3388 GEN_LOWERED_STORE(Store, fp_none)
3390 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3391 ir_node *block = be_transform_node(get_nodes_block(node));
3392 ir_node *left = get_binop_left(node);
3393 ir_node *new_left = be_transform_node(left);
3394 ir_node *right = get_binop_right(node);
3395 ir_node *new_right = be_transform_node(right);
3396 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3397 ir_graph *irg = current_ir_graph;
3398 dbg_info *dbgi = get_irn_dbg_info(node);
3399 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3400 &ia32_fp_cw_regs[REG_FPCW]);
3403 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3404 new_right, new_NoMem(), fpcw);
3405 clear_ia32_commutative(vfdiv);
3406 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3408 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3416 * Transforms a l_MulS into a "real" MulS node.
3418 * @param env The transformation environment
3419 * @return the created ia32 Mul node
3421 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3422 ir_node *block = be_transform_node(get_nodes_block(node));
3423 ir_node *left = get_binop_left(node);
3424 ir_node *new_left = be_transform_node(left);
3425 ir_node *right = get_binop_right(node);
3426 ir_node *new_right = be_transform_node(right);
3427 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3428 ir_graph *irg = current_ir_graph;
3429 dbg_info *dbgi = get_irn_dbg_info(node);
3432 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3433 /* and then skip the result Proj, because all needed Projs are already there. */
3434 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3435 new_right, new_NoMem());
3436 clear_ia32_commutative(muls);
3437 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3439 /* check if EAX and EDX proj exist, add missing one */
3440 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3441 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3442 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3444 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3449 GEN_LOWERED_SHIFT_OP(Shl)
3450 GEN_LOWERED_SHIFT_OP(Shr)
3451 GEN_LOWERED_SHIFT_OP(Sar)
3454 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3455 * op1 - target to be shifted
3456 * op2 - contains bits to be shifted into target
3458 * Only op3 can be an immediate.
3460 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3461 ir_node *op2, ir_node *count)
3463 ir_node *block = be_transform_node(get_nodes_block(node));
3464 ir_node *new_op1 = be_transform_node(op1);
3465 ir_node *new_op2 = be_transform_node(op2);
3466 ir_node *new_count = be_transform_node(count);
3467 ir_node *new_op = NULL;
3468 ir_graph *irg = current_ir_graph;
3469 dbg_info *dbgi = get_irn_dbg_info(node);
3470 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3471 ir_node *nomem = new_NoMem();
3475 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3477 /* Check if immediate optimization is on and */
3478 /* if it's an operation with immediate. */
3479 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3481 /* Limit imm_op within range imm8 */
3483 tv = get_ia32_Immop_tarval(imm_op);
3486 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3487 set_ia32_Immop_tarval(imm_op, tv);
3494 /* integer operations */
3496 /* This is ShiftD with const */
3497 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3499 if (is_ia32_l_ShlD(node))
3500 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3501 new_op1, new_op2, noreg, nomem);
3503 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3504 new_op1, new_op2, noreg, nomem);
3505 copy_ia32_Immop_attr(new_op, imm_op);
3508 /* This is a normal ShiftD */
3509 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3510 if (is_ia32_l_ShlD(node))
3511 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3512 new_op1, new_op2, new_count, nomem);
3514 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3515 new_op1, new_op2, new_count, nomem);
3518 /* set AM support */
3519 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3521 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3523 set_ia32_emit_cl(new_op);
3528 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3529 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3530 get_irn_n(node, 1), get_irn_n(node, 2));
3533 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3534 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3535 get_irn_n(node, 1), get_irn_n(node, 2));
3539 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3541 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3542 ir_node *block = be_transform_node(get_nodes_block(node));
3543 ir_node *val = get_irn_n(node, 1);
3544 ir_node *new_val = be_transform_node(val);
3545 ia32_code_gen_t *cg = env_cg;
3546 ir_node *res = NULL;
3547 ir_graph *irg = current_ir_graph;
3549 ir_node *noreg, *new_ptr, *new_mem;
3556 mem = get_irn_n(node, 2);
3557 new_mem = be_transform_node(mem);
3558 ptr = get_irn_n(node, 0);
3559 new_ptr = be_transform_node(ptr);
3560 noreg = ia32_new_NoReg_gp(cg);
3561 dbgi = get_irn_dbg_info(node);
3563 /* Store x87 -> MEM */
3564 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3565 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3566 set_ia32_use_frame(res);
3567 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3568 set_ia32_am_flavour(res, ia32_B);
3569 set_ia32_op_type(res, ia32_AddrModeD);
3571 /* Load MEM -> SSE */
3572 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3573 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3574 set_ia32_use_frame(res);
3575 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3576 set_ia32_am_flavour(res, ia32_B);
3577 set_ia32_op_type(res, ia32_AddrModeS);
3578 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3584 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3586 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3587 ir_node *block = be_transform_node(get_nodes_block(node));
3588 ir_node *val = get_irn_n(node, 1);
3589 ir_node *new_val = be_transform_node(val);
3590 ia32_code_gen_t *cg = env_cg;
3591 ir_graph *irg = current_ir_graph;
3592 ir_node *res = NULL;
3593 ir_entity *fent = get_ia32_frame_ent(node);
3594 ir_mode *lsmode = get_ia32_ls_mode(node);
3596 ir_node *noreg, *new_ptr, *new_mem;
3600 if (! USE_SSE2(cg)) {
3601 /* SSE unit is not used -> skip this node. */
3605 ptr = get_irn_n(node, 0);
3606 new_ptr = be_transform_node(ptr);
3607 mem = get_irn_n(node, 2);
3608 new_mem = be_transform_node(mem);
3609 noreg = ia32_new_NoReg_gp(cg);
3610 dbgi = get_irn_dbg_info(node);
3612 /* Store SSE -> MEM */
3613 if (is_ia32_xLoad(skip_Proj(new_val))) {
3614 ir_node *ld = skip_Proj(new_val);
3616 /* we can vfld the value directly into the fpu */
3617 fent = get_ia32_frame_ent(ld);
3618 ptr = get_irn_n(ld, 0);
3619 offs = get_ia32_am_offs_int(ld);
3621 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3622 set_ia32_frame_ent(res, fent);
3623 set_ia32_use_frame(res);
3624 set_ia32_ls_mode(res, lsmode);
3625 set_ia32_am_flavour(res, ia32_B);
3626 set_ia32_op_type(res, ia32_AddrModeD);
3630 /* Load MEM -> x87 */
3631 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3632 set_ia32_frame_ent(res, fent);
3633 set_ia32_use_frame(res);
3634 add_ia32_am_offs_int(res, offs);
3635 set_ia32_am_flavour(res, ia32_B);
3636 set_ia32_op_type(res, ia32_AddrModeS);
3637 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3642 /*********************************************************
3645 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3646 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3647 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3648 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3650 *********************************************************/
3653 * the BAD transformer.
3655 static ir_node *bad_transform(ir_node *node) {
3656 panic("No transform function for %+F available.\n", node);
3661 * Transform the Projs of an AddSP.
3663 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3664 ir_node *block = be_transform_node(get_nodes_block(node));
3665 ir_node *pred = get_Proj_pred(node);
3666 ir_node *new_pred = be_transform_node(pred);
3667 ir_graph *irg = current_ir_graph;
3668 dbg_info *dbgi = get_irn_dbg_info(node);
3669 long proj = get_Proj_proj(node);
3671 if (proj == pn_be_AddSP_res) {
3672 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3673 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3675 } else if (proj == pn_be_AddSP_M) {
3676 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3680 return new_rd_Unknown(irg, get_irn_mode(node));
3684 * Transform the Projs of a SubSP.
3686 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3687 ir_node *block = be_transform_node(get_nodes_block(node));
3688 ir_node *pred = get_Proj_pred(node);
3689 ir_node *new_pred = be_transform_node(pred);
3690 ir_graph *irg = current_ir_graph;
3691 dbg_info *dbgi = get_irn_dbg_info(node);
3692 long proj = get_Proj_proj(node);
3694 if (proj == pn_be_SubSP_res) {
3695 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3696 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3698 } else if (proj == pn_be_SubSP_M) {
3699 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3703 return new_rd_Unknown(irg, get_irn_mode(node));
3707 * Transform and renumber the Projs from a Load.
3709 static ir_node *gen_Proj_Load(ir_node *node) {
3710 ir_node *block = be_transform_node(get_nodes_block(node));
3711 ir_node *pred = get_Proj_pred(node);
3712 ir_node *new_pred = be_transform_node(pred);
3713 ir_graph *irg = current_ir_graph;
3714 dbg_info *dbgi = get_irn_dbg_info(node);
3715 long proj = get_Proj_proj(node);
3717 /* renumber the proj */
3718 if (is_ia32_Load(new_pred)) {
3719 if (proj == pn_Load_res) {
3720 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3721 } else if (proj == pn_Load_M) {
3722 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3724 } else if (is_ia32_xLoad(new_pred)) {
3725 if (proj == pn_Load_res) {
3726 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3727 } else if (proj == pn_Load_M) {
3728 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3730 } else if (is_ia32_vfld(new_pred)) {
3731 if (proj == pn_Load_res) {
3732 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3733 } else if (proj == pn_Load_M) {
3734 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3739 return new_rd_Unknown(irg, get_irn_mode(node));
3743 * Transform and renumber the Projs from a DivMod like instruction.
3745 static ir_node *gen_Proj_DivMod(ir_node *node) {
3746 ir_node *block = be_transform_node(get_nodes_block(node));
3747 ir_node *pred = get_Proj_pred(node);
3748 ir_node *new_pred = be_transform_node(pred);
3749 ir_graph *irg = current_ir_graph;
3750 dbg_info *dbgi = get_irn_dbg_info(node);
3751 ir_mode *mode = get_irn_mode(node);
3752 long proj = get_Proj_proj(node);
3754 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3756 switch (get_irn_opcode(pred)) {
3760 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3762 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3770 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3772 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3780 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3781 case pn_DivMod_res_div:
3782 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3783 case pn_DivMod_res_mod:
3784 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3794 return new_rd_Unknown(irg, mode);
3798 * Transform and renumber the Projs from a CopyB.
3800 static ir_node *gen_Proj_CopyB(ir_node *node) {
3801 ir_node *block = be_transform_node(get_nodes_block(node));
3802 ir_node *pred = get_Proj_pred(node);
3803 ir_node *new_pred = be_transform_node(pred);
3804 ir_graph *irg = current_ir_graph;
3805 dbg_info *dbgi = get_irn_dbg_info(node);
3806 ir_mode *mode = get_irn_mode(node);
3807 long proj = get_Proj_proj(node);
3810 case pn_CopyB_M_regular:
3811 if (is_ia32_CopyB_i(new_pred)) {
3812 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3813 } else if (is_ia32_CopyB(new_pred)) {
3814 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3822 return new_rd_Unknown(irg, mode);
3826 * Transform and renumber the Projs from a vfdiv.
3828 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3829 ir_node *block = be_transform_node(get_nodes_block(node));
3830 ir_node *pred = get_Proj_pred(node);
3831 ir_node *new_pred = be_transform_node(pred);
3832 ir_graph *irg = current_ir_graph;
3833 dbg_info *dbgi = get_irn_dbg_info(node);
3834 ir_mode *mode = get_irn_mode(node);
3835 long proj = get_Proj_proj(node);
3838 case pn_ia32_l_vfdiv_M:
3839 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3840 case pn_ia32_l_vfdiv_res:
3841 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3846 return new_rd_Unknown(irg, mode);
3850 * Transform and renumber the Projs from a Quot.
3852 static ir_node *gen_Proj_Quot(ir_node *node) {
3853 ir_node *block = be_transform_node(get_nodes_block(node));
3854 ir_node *pred = get_Proj_pred(node);
3855 ir_node *new_pred = be_transform_node(pred);
3856 ir_graph *irg = current_ir_graph;
3857 dbg_info *dbgi = get_irn_dbg_info(node);
3858 ir_mode *mode = get_irn_mode(node);
3859 long proj = get_Proj_proj(node);
3863 if (is_ia32_xDiv(new_pred)) {
3864 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3865 } else if (is_ia32_vfdiv(new_pred)) {
3866 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3870 if (is_ia32_xDiv(new_pred)) {
3871 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3872 } else if (is_ia32_vfdiv(new_pred)) {
3873 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3881 return new_rd_Unknown(irg, mode);
3885 * Transform the Thread Local Storage Proj.
3887 static ir_node *gen_Proj_tls(ir_node *node) {
3888 ir_node *block = be_transform_node(get_nodes_block(node));
3889 ir_graph *irg = current_ir_graph;
3890 dbg_info *dbgi = NULL;
3891 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3897 * Transform the Projs from a be_Call.
3899 static ir_node *gen_Proj_be_Call(ir_node *node) {
3900 ir_node *block = be_transform_node(get_nodes_block(node));
3901 ir_node *call = get_Proj_pred(node);
3902 ir_node *new_call = be_transform_node(call);
3903 ir_graph *irg = current_ir_graph;
3904 dbg_info *dbgi = get_irn_dbg_info(node);
3905 long proj = get_Proj_proj(node);
3906 ir_mode *mode = get_irn_mode(node);
3908 const arch_register_class_t *cls;
3910 /* The following is kinda tricky: If we're using SSE, then we have to
3911 * move the result value of the call in floating point registers to an
3912 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3913 * after the call, we have to make sure to correctly make the
3914 * MemProj and the result Proj use these 2 nodes
3916 if (proj == pn_be_Call_M_regular) {
3917 // get new node for result, are we doing the sse load/store hack?
3918 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3919 ir_node *call_res_new;
3920 ir_node *call_res_pred = NULL;
3922 if (call_res != NULL) {
3923 call_res_new = be_transform_node(call_res);
3924 call_res_pred = get_Proj_pred(call_res_new);
3927 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3928 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3930 assert(is_ia32_xLoad(call_res_pred));
3931 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3934 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3936 ir_node *frame = get_irg_frame(irg);
3937 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3939 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3941 const arch_register_class_t *cls;
3943 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3944 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3946 /* store st(0) onto stack */
3947 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3949 set_ia32_ls_mode(fstp, mode);
3950 set_ia32_op_type(fstp, ia32_AddrModeD);
3951 set_ia32_use_frame(fstp);
3952 set_ia32_am_flavour(fstp, ia32_am_B);
3954 /* load into SSE register */
3955 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3956 set_ia32_ls_mode(sse_load, mode);
3957 set_ia32_op_type(sse_load, ia32_AddrModeS);
3958 set_ia32_use_frame(sse_load);
3959 set_ia32_am_flavour(sse_load, ia32_am_B);
3961 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3963 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3965 /* get a Proj representing a caller save register */
3966 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3967 assert(is_Proj(p) && "Proj expected.");
3969 /* user of the the proj is the Keep */
3970 p = get_edge_src_irn(get_irn_out_edge_first(p));
3971 assert(be_is_Keep(p) && "Keep expected.");
3973 /* keep the result */
3974 cls = arch_get_irn_reg_class(env_cg->arch_env, sse_load, -1);
3975 keepin[0] = sse_load;
3976 be_new_Keep(cls, irg, block, 1, keepin);
3981 /* transform call modes */
3982 if (mode_is_data(mode)) {
3983 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3987 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3991 * Transform the Projs from a Cmp.
3993 static ir_node *gen_Proj_Cmp(ir_node *node)
3995 /* normally Cmps are processed when looking at Cond nodes, but this case
3996 * can happen in complicated Psi conditions */
3998 ir_graph *irg = current_ir_graph;
3999 dbg_info *dbgi = get_irn_dbg_info(node);
4000 ir_node *block = be_transform_node(get_nodes_block(node));
4001 ir_node *cmp = get_Proj_pred(node);
4002 long pnc = get_Proj_proj(node);
4003 ir_node *cmp_left = get_Cmp_left(cmp);
4004 ir_node *cmp_right = get_Cmp_right(cmp);
4005 ir_node *new_cmp_left;
4006 ir_node *new_cmp_right;
4007 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4008 ir_node *nomem = new_rd_NoMem(irg);
4009 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4012 assert(!mode_is_float(cmp_mode));
4014 /* (a != b) -> (a ^ b) */
4015 if(pnc == pn_Cmp_Lg) {
4016 if(is_Const_0(cmp_left)) {
4017 new_op = be_transform_node(cmp_right);
4018 } else if(is_Const_0(cmp_right)) {
4019 new_op = be_transform_node(cmp_left);
4021 new_op = gen_binop(cmp, cmp_left, cmp_right, new_rd_ia32_Xor, 1);
4027 * (a == b) -> !(a ^ b)
4028 * (a < 0) -> (a & 0x80000000) oder a >> 31
4029 * (a >= 0) -> (a >> 31) ^ 1
4032 if(!mode_is_signed(cmp_mode)) {
4033 pnc |= ia32_pn_Cmp_Unsigned;
4036 new_cmp_left = be_transform_node(cmp_left);
4037 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
4039 new_op = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
4040 new_cmp_right, nomem, pnc);
4041 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, cmp));
4047 * Transform and potentially renumber Proj nodes.
4049 static ir_node *gen_Proj(ir_node *node) {
4050 ir_graph *irg = current_ir_graph;
4051 dbg_info *dbgi = get_irn_dbg_info(node);
4052 ir_node *pred = get_Proj_pred(node);
4053 long proj = get_Proj_proj(node);
4055 if (is_Store(pred) || be_is_FrameStore(pred)) {
4056 if (proj == pn_Store_M) {
4057 return be_transform_node(pred);
4060 return new_r_Bad(irg);
4062 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4063 return gen_Proj_Load(node);
4064 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4065 return gen_Proj_DivMod(node);
4066 } else if (is_CopyB(pred)) {
4067 return gen_Proj_CopyB(node);
4068 } else if (is_Quot(pred)) {
4069 return gen_Proj_Quot(node);
4070 } else if (is_ia32_l_vfdiv(pred)) {
4071 return gen_Proj_l_vfdiv(node);
4072 } else if (be_is_SubSP(pred)) {
4073 return gen_Proj_be_SubSP(node);
4074 } else if (be_is_AddSP(pred)) {
4075 return gen_Proj_be_AddSP(node);
4076 } else if (be_is_Call(pred)) {
4077 return gen_Proj_be_Call(node);
4078 } else if (is_Cmp(pred)) {
4079 return gen_Proj_Cmp(node);
4080 } else if (get_irn_op(pred) == op_Start) {
4081 if (proj == pn_Start_X_initial_exec) {
4082 ir_node *block = get_nodes_block(pred);
4085 /* we exchange the ProjX with a jump */
4086 block = be_transform_node(block);
4087 jump = new_rd_Jmp(dbgi, irg, block);
4090 if (node == be_get_old_anchor(anchor_tls)) {
4091 return gen_Proj_tls(node);
4094 ir_node *new_pred = be_transform_node(pred);
4095 ir_node *block = be_transform_node(get_nodes_block(node));
4096 ir_mode *mode = get_irn_mode(node);
4097 if (mode_needs_gp_reg(mode)) {
4098 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4099 get_Proj_proj(node));
4100 #ifdef DEBUG_libfirm
4101 new_proj->node_nr = node->node_nr;
4107 return be_duplicate_node(node);
4111 * Enters all transform functions into the generic pointer
4113 static void register_transformers(void) {
4114 ir_op *op_Max, *op_Min, *op_Mulh;
4116 /* first clear the generic function pointer for all ops */
4117 clear_irp_opcodes_generic_func();
4119 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4120 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4157 /* transform ops from intrinsic lowering */
4177 /* GEN(ia32_l_vfist); TODO */
4179 GEN(ia32_l_X87toSSE);
4180 GEN(ia32_l_SSEtoX87);
4185 /* we should never see these nodes */
4200 /* handle generic backend nodes */
4211 /* set the register for all Unknown nodes */
4214 op_Max = get_op_Max();
4217 op_Min = get_op_Min();
4220 op_Mulh = get_op_Mulh();
4229 * Pre-transform all unknown and noreg nodes.
4231 static void ia32_pretransform_node(void *arch_cg) {
4232 ia32_code_gen_t *cg = arch_cg;
4234 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4235 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4236 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4237 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4238 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4239 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4242 /* do the transformation */
4243 void ia32_transform_graph(ia32_code_gen_t *cg) {
4244 register_transformers();
4246 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4249 void ia32_init_transform(void)
4251 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");