2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
55 #include "../benode_t.h"
56 #include "../besched.h"
58 #include "../beutil.h"
59 #include "../beirg_t.h"
61 #include "bearch_ia32_t.h"
62 #include "ia32_nodes_attr.h"
63 #include "ia32_transform.h"
64 #include "ia32_new_nodes.h"
65 #include "ia32_map_regs.h"
66 #include "ia32_dbg_stat.h"
67 #include "ia32_optimize.h"
68 #include "ia32_util.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
83 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
84 #define ENT_SFP_ABS "IA32_SFP_ABS"
85 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
88 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
90 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
92 typedef struct ia32_transform_env_t {
93 ir_graph *irg; /**< The irg, the node should be created in */
94 ia32_code_gen_t *cg; /**< The code generator */
95 int visited; /**< visited count that indicates whether a
96 node is already transformed */
97 pdeq *worklist; /**< worklist of nodes that still need to be
99 ir_node **old_anchors;/**< the list of anchors nodes in the old irg*/
100 } ia32_transform_env_t;
102 static ia32_transform_env_t env;
104 extern ir_op *get_op_Mulh(void);
106 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
108 ir_node *op2, ir_node *mem);
110 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
114 typedef ir_node *(transform_func)(ir_node *node);
116 /****************************************************************************************************
118 * | | | | / _| | | (_)
119 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
120 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
121 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
122 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
124 ****************************************************************************************************/
126 static ir_node *duplicate_node(ir_node *node);
127 static ir_node *transform_node(ir_node *node);
128 static void duplicate_deps(ir_node *old_node, ir_node *new_node);
130 static INLINE int mode_needs_gp_reg(ir_mode *mode)
132 if(mode == mode_fpcw)
135 return mode_is_int(mode) || mode_is_character(mode) || mode_is_reference(mode);
138 static INLINE void set_new_node(ir_node *old_node, ir_node *new_node)
140 set_irn_link(old_node, new_node);
143 static INLINE ir_node *get_new_node(ir_node *old_node)
145 assert(irn_visited(old_node));
146 return (ir_node*) get_irn_link(old_node);
150 * Returns 1 if irn is a Const representing 0, 0 otherwise
152 static INLINE int is_ia32_Const_0(ir_node *irn) {
153 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
154 && tarval_is_null(get_ia32_Immop_tarval(irn));
158 * Returns 1 if irn is a Const representing 1, 0 otherwise
160 static INLINE int is_ia32_Const_1(ir_node *irn) {
161 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
162 && tarval_is_one(get_ia32_Immop_tarval(irn));
166 * Collects all Projs of a node into the node array. Index is the projnum.
167 * BEWARE: The caller has to assure the appropriate array size!
169 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
170 const ir_edge_t *edge;
171 assert(get_irn_mode(irn) == mode_T && "need mode_T");
173 memset(projs, 0, size * sizeof(projs[0]));
175 foreach_out_edge(irn, edge) {
176 ir_node *proj = get_edge_src_irn(edge);
177 int proj_proj = get_Proj_proj(proj);
178 assert(proj_proj < size);
179 projs[proj_proj] = proj;
184 * Renumbers the proj having pn_old in the array tp pn_new
185 * and removes the proj from the array.
187 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
188 fprintf(stderr, "Warning: renumber_Proj used!\n");
190 set_Proj_proj(projs[pn_old], pn_new);
191 projs[pn_old] = NULL;
196 * creates a unique ident by adding a number to a tag
198 * @param tag the tag string, must contain a %d if a number
201 static ident *unique_id(const char *tag)
203 static unsigned id = 0;
206 snprintf(str, sizeof(str), tag, ++id);
207 return new_id_from_str(str);
211 * Get a primitive type for a mode.
213 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
215 pmap_entry *e = pmap_find(types, mode);
220 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
221 res = new_type_primitive(new_id_from_str(buf), mode);
222 pmap_insert(types, mode, res);
230 * Get an entity that is initialized with a tarval
232 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
234 tarval *tv = get_Const_tarval(cnst);
235 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
240 ir_mode *mode = get_irn_mode(cnst);
241 ir_type *tp = get_Const_type(cnst);
242 if (tp == firm_unknown_type)
243 tp = get_prim_type(cg->isa->types, mode);
245 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
247 set_entity_ld_ident(res, get_entity_ident(res));
248 set_entity_visibility(res, visibility_local);
249 set_entity_variability(res, variability_constant);
250 set_entity_allocation(res, allocation_static);
252 /* we create a new entity here: It's initialization must resist on the
254 rem = current_ir_graph;
255 current_ir_graph = get_const_code_irg();
256 set_atomic_ent_value(res, new_Const_type(tv, tp));
257 current_ir_graph = rem;
259 pmap_insert(cg->isa->tv_ent, tv, res);
268 * Transforms a Const.
270 static ir_node *gen_Const(ir_node *node) {
271 ir_graph *irg = env.irg;
272 ir_node *block = transform_node(get_nodes_block(node));
273 dbg_info *dbgi = get_irn_dbg_info(node);
274 ir_mode *mode = get_irn_mode(node);
276 if (mode_is_float(mode)) {
278 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
279 ir_node *nomem = new_NoMem();
284 if (! USE_SSE2(env.cg)) {
285 cnst_classify_t clss = classify_Const(node);
287 if (clss == CNST_NULL) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (clss == CNST_ONE) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = get_entity_for_tv(env.cg, node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem);
297 set_ia32_am_support(load, ia32_am_Source);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_flavour(load, ia32_am_N);
300 set_ia32_am_sc(load, floatent);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
305 floatent = get_entity_for_tv(env.cg, node);
307 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
308 set_ia32_am_support(load, ia32_am_Source);
309 set_ia32_op_type(load, ia32_AddrModeS);
310 set_ia32_am_flavour(load, ia32_am_N);
311 set_ia32_am_sc(load, floatent);
312 set_ia32_ls_mode(load, mode);
314 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node));
319 /* Const Nodes before the initial IncSP are a bad idea, because
320 * they could be spilled and we have no SP ready at that point yet.
321 * So add a dependency to the initial frame pointer calculation to
322 * avoid that situation.
324 if (get_irg_start_block(irg) == block) {
325 add_irn_dep(load, get_irg_frame(irg));
328 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env.cg, node));
331 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
334 if (get_irg_start_block(irg) == block) {
335 add_irn_dep(cnst, get_irg_frame(irg));
338 set_ia32_Const_attr(cnst, node);
339 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node));
344 return new_r_Bad(irg);
348 * Transforms a SymConst.
350 static ir_node *gen_SymConst(ir_node *node) {
351 ir_graph *irg = env.irg;
352 ir_node *block = transform_node(get_nodes_block(node));
353 dbg_info *dbgi = get_irn_dbg_info(node);
354 ir_mode *mode = get_irn_mode(node);
357 if (mode_is_float(mode)) {
359 if (USE_SSE2(env.cg))
360 cnst = new_rd_ia32_xConst(dbgi, irg, block);
362 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
363 set_ia32_ls_mode(cnst, mode);
365 cnst = new_rd_ia32_Const(dbgi, irg, block);
368 /* Const Nodes before the initial IncSP are a bad idea, because
369 * they could be spilled and we have no SP ready at that point yet
371 if (get_irg_start_block(irg) == block) {
372 add_irn_dep(cnst, get_irg_frame(irg));
375 set_ia32_Const_attr(cnst, node);
376 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env.cg, node));
382 * SSE convert of an integer node into a floating point node.
384 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbgi,
385 ir_graph *irg, ir_node *block,
386 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
388 ir_node *noreg = ia32_new_NoReg_gp(cg);
389 ir_node *nomem = new_rd_NoMem(irg);
390 ir_node *old_pred = get_Cmp_left(old_node);
391 ir_mode *in_mode = get_irn_mode(old_pred);
392 int in_bits = get_mode_size_bits(in_mode);
393 ir_node *conv = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, in, nomem);
395 set_ia32_ls_mode(conv, tgt_mode);
397 set_ia32_am_support(conv, ia32_am_Source);
399 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
405 * SSE convert of an float node into a double node.
407 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbgi,
408 ir_graph *irg, ir_node *block,
409 ir_node *in, ir_node *old_node)
411 ir_node *noreg = ia32_new_NoReg_gp(cg);
412 ir_node *nomem = new_rd_NoMem(irg);
413 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, in, nomem);
415 set_ia32_am_support(conv, ia32_am_Source);
416 set_ia32_ls_mode(conv, mode_xmm);
417 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
422 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
423 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
424 static const struct {
426 const char *ent_name;
427 const char *cnst_str;
428 } names [ia32_known_const_max] = {
429 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
430 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
431 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
432 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
434 static ir_entity *ent_cache[ia32_known_const_max];
436 const char *tp_name, *ent_name, *cnst_str;
444 ent_name = names[kct].ent_name;
445 if (! ent_cache[kct]) {
446 tp_name = names[kct].tp_name;
447 cnst_str = names[kct].cnst_str;
449 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
451 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
452 tp = new_type_primitive(new_id_from_str(tp_name), mode);
453 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
455 set_entity_ld_ident(ent, get_entity_ident(ent));
456 set_entity_visibility(ent, visibility_local);
457 set_entity_variability(ent, variability_constant);
458 set_entity_allocation(ent, allocation_static);
460 /* we create a new entity here: It's initialization must resist on the
462 rem = current_ir_graph;
463 current_ir_graph = get_const_code_irg();
464 cnst = new_Const(mode, tv);
465 current_ir_graph = rem;
467 set_atomic_ent_value(ent, cnst);
469 /* cache the entry */
470 ent_cache[kct] = ent;
473 return ent_cache[kct];
478 * Prints the old node name on cg obst and returns a pointer to it.
480 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
481 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
483 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
484 obstack_1grow(isa->name_obst, 0);
485 return obstack_finish(isa->name_obst);
489 /* determine if one operator is an Imm */
490 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
492 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
494 return is_ia32_Cnst(op2) ? op2 : NULL;
498 /* determine if one operator is not an Imm */
499 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
500 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
503 static void fold_immediate(ir_node *node, int in1, int in2) {
507 if (!(env.cg->opt & IA32_OPT_IMMOPS))
510 left = get_irn_n(node, in1);
511 right = get_irn_n(node, in2);
512 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
513 /* we can only set right operand to immediate */
514 if(!is_ia32_commutative(node))
516 /* exchange left/right */
517 set_irn_n(node, in1, right);
518 set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2));
519 copy_ia32_Immop_attr(node, left);
520 } else if(is_ia32_Cnst(right)) {
521 set_irn_n(node, in2, ia32_get_admissible_noreg(env.cg, node, in2));
522 copy_ia32_Immop_attr(node, right);
527 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source);
531 * Construct a standard binary operation, set AM and immediate if required.
533 * @param op1 The first operand
534 * @param op2 The second operand
535 * @param func The node constructor function
536 * @return The constructed ia32 node.
538 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
539 construct_binop_func *func)
541 ir_node *block = transform_node(get_nodes_block(node));
542 ir_node *new_op1 = transform_node(op1);
543 ir_node *new_op2 = transform_node(op2);
544 ir_node *new_node = NULL;
545 ir_graph *irg = env.irg;
546 dbg_info *dbgi = get_irn_dbg_info(node);
547 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
548 ir_node *nomem = new_NoMem();
550 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
551 if (func == new_rd_ia32_IMul) {
552 set_ia32_am_support(new_node, ia32_am_Source);
554 set_ia32_am_support(new_node, ia32_am_Full);
557 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
558 if (is_op_commutative(get_irn_op(node))) {
559 set_ia32_commutative(new_node);
561 fold_immediate(new_node, 2, 3);
567 * Construct a standard binary operation, set AM and immediate if required.
569 * @param op1 The first operand
570 * @param op2 The second operand
571 * @param func The node constructor function
572 * @return The constructed ia32 node.
574 static ir_node *gen_binop_float(ir_node *node, ir_node *op1, ir_node *op2,
575 construct_binop_func *func)
577 ir_node *block = transform_node(get_nodes_block(node));
578 ir_node *new_op1 = transform_node(op1);
579 ir_node *new_op2 = transform_node(op2);
580 ir_node *new_node = NULL;
581 dbg_info *dbgi = get_irn_dbg_info(node);
582 ir_graph *irg = env.irg;
583 ir_mode *mode = get_irn_mode(node);
584 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
585 ir_node *nomem = new_NoMem();
587 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
588 set_ia32_am_support(new_node, ia32_am_Source);
589 if (is_op_commutative(get_irn_op(node))) {
590 set_ia32_commutative(new_node);
592 if (USE_SSE2(env.cg)) {
593 set_ia32_ls_mode(new_node, mode);
596 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
603 * Construct a shift/rotate binary operation, sets AM and immediate if required.
605 * @param op1 The first operand
606 * @param op2 The second operand
607 * @param func The node constructor function
608 * @return The constructed ia32 node.
610 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
611 construct_binop_func *func)
613 ir_node *block = transform_node(get_nodes_block(node));
614 ir_node *new_op1 = transform_node(op1);
615 ir_node *new_op2 = transform_node(op2);
616 ir_node *new_op = NULL;
617 dbg_info *dbgi = get_irn_dbg_info(node);
618 ir_graph *irg = env.irg;
619 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
620 ir_node *nomem = new_NoMem();
625 assert(! mode_is_float(get_irn_mode(node))
626 && "Shift/Rotate with float not supported");
628 /* Check if immediate optimization is on and */
629 /* if it's an operation with immediate. */
630 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
631 expr_op = get_expr_op(new_op1, new_op2);
633 assert((expr_op || imm_op) && "invalid operands");
636 /* We have two consts here: not yet supported */
640 /* Limit imm_op within range imm8 */
642 tv = get_ia32_Immop_tarval(imm_op);
645 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
646 set_ia32_Immop_tarval(imm_op, tv);
653 /* integer operations */
655 /* This is shift/rot with const */
656 DB((dbg, LEVEL_1, "Shift/Rot with immediate ..."));
658 new_op = func(dbgi, irg, block, noreg, noreg, expr_op, noreg, nomem);
659 copy_ia32_Immop_attr(new_op, imm_op);
661 /* This is a normal shift/rot */
662 DB((dbg, LEVEL_1, "Shift/Rot binop ..."));
663 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
667 set_ia32_am_support(new_op, ia32_am_Dest);
669 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
671 set_ia32_emit_cl(new_op);
678 * Construct a standard unary operation, set AM and immediate if required.
680 * @param op The operand
681 * @param func The node constructor function
682 * @return The constructed ia32 node.
684 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
686 ir_node *block = transform_node(get_nodes_block(node));
687 ir_node *new_op = transform_node(op);
688 ir_node *new_node = NULL;
689 ir_graph *irg = env.irg;
690 dbg_info *dbgi = get_irn_dbg_info(node);
691 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
692 ir_node *nomem = new_NoMem();
694 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
695 DB((dbg, LEVEL_1, "INT unop ..."));
696 set_ia32_am_support(new_node, ia32_am_Dest);
698 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env.cg, node));
705 * Creates an ia32 Add.
707 * @return the created ia32 Add node
709 static ir_node *gen_Add(ir_node *node) {
710 ir_node *block = transform_node(get_nodes_block(node));
711 ir_node *op1 = get_Add_left(node);
712 ir_node *new_op1 = transform_node(op1);
713 ir_node *op2 = get_Add_right(node);
714 ir_node *new_op2 = transform_node(op2);
715 ir_node *new_op = NULL;
716 ir_graph *irg = env.irg;
717 dbg_info *dbgi = get_irn_dbg_info(node);
718 ir_mode *mode = get_irn_mode(node);
719 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
720 ir_node *nomem = new_NoMem();
721 ir_node *expr_op, *imm_op;
723 /* Check if immediate optimization is on and */
724 /* if it's an operation with immediate. */
725 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
726 expr_op = get_expr_op(new_op1, new_op2);
728 assert((expr_op || imm_op) && "invalid operands");
730 if (mode_is_float(mode)) {
732 if (USE_SSE2(env.cg))
733 return gen_binop_float(node, op1, op2, new_rd_ia32_xAdd);
735 return gen_binop_float(node, op1, op2, new_rd_ia32_vfadd);
740 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
741 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
743 /* No expr_op means, that we have two const - one symconst and */
744 /* one tarval or another symconst - because this case is not */
745 /* covered by constant folding */
746 /* We need to check for: */
747 /* 1) symconst + const -> becomes a LEA */
748 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
749 /* linker doesn't support two symconsts */
751 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
752 /* this is the 2nd case */
753 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
754 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
755 set_ia32_am_flavour(new_op, ia32_am_B);
756 set_ia32_am_support(new_op, ia32_am_Source);
757 set_ia32_op_type(new_op, ia32_AddrModeS);
759 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
760 } else if (tp1 == ia32_ImmSymConst) {
761 tarval *tv = get_ia32_Immop_tarval(new_op2);
762 long offs = get_tarval_long(tv);
764 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
765 add_irn_dep(new_op, get_irg_frame(irg));
766 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
768 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
769 add_ia32_am_offs_int(new_op, offs);
770 set_ia32_am_flavour(new_op, ia32_am_OB);
771 set_ia32_am_support(new_op, ia32_am_Source);
772 set_ia32_op_type(new_op, ia32_AddrModeS);
773 } else if (tp2 == ia32_ImmSymConst) {
774 tarval *tv = get_ia32_Immop_tarval(new_op1);
775 long offs = get_tarval_long(tv);
777 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
778 add_irn_dep(new_op, get_irg_frame(irg));
779 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
781 add_ia32_am_offs_int(new_op, offs);
782 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
783 set_ia32_am_flavour(new_op, ia32_am_OB);
784 set_ia32_am_support(new_op, ia32_am_Source);
785 set_ia32_op_type(new_op, ia32_AddrModeS);
787 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
788 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
789 tarval *restv = tarval_add(tv1, tv2);
791 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
793 new_op = new_rd_ia32_Const(dbgi, irg, block);
794 set_ia32_Const_tarval(new_op, restv);
795 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
798 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
801 if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
802 tarval_classification_t class_tv, class_negtv;
803 tarval *tv = get_ia32_Immop_tarval(imm_op);
805 /* optimize tarvals */
806 class_tv = classify_tarval(tv);
807 class_negtv = classify_tarval(tarval_neg(tv));
809 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
810 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
811 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
812 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
814 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
815 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
816 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
817 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
823 /* This is a normal add */
824 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
827 set_ia32_am_support(new_op, ia32_am_Full);
828 set_ia32_commutative(new_op);
830 fold_immediate(new_op, 2, 3);
832 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
838 static ir_node *create_ia32_Mul(ir_node *node) {
839 ir_graph *irg = env.irg;
840 dbg_info *dbgi = get_irn_dbg_info(node);
841 ir_node *block = transform_node(get_nodes_block(node));
842 ir_node *op1 = get_Mul_left(node);
843 ir_node *op2 = get_Mul_right(node);
844 ir_node *new_op1 = transform_node(op1);
845 ir_node *new_op2 = transform_node(op2);
846 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
847 ir_node *proj_EAX, *proj_EDX, *res;
850 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
851 set_ia32_commutative(res);
852 set_ia32_am_support(res, ia32_am_Source);
854 /* imediates are not supported, so no fold_immediate */
855 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
856 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
868 * Creates an ia32 Mul.
870 * @return the created ia32 Mul node
872 static ir_node *gen_Mul(ir_node *node) {
873 ir_node *op1 = get_Mul_left(node);
874 ir_node *op2 = get_Mul_right(node);
875 ir_mode *mode = get_irn_mode(node);
877 if (mode_is_float(mode)) {
879 if (USE_SSE2(env.cg))
880 return gen_binop_float(node, op1, op2, new_rd_ia32_xMul);
882 return gen_binop_float(node, op1, op2, new_rd_ia32_vfmul);
886 for the lower 32bit of the result it doesn't matter whether we use
887 signed or unsigned multiplication so we use IMul as it has fewer
890 return gen_binop(node, op1, op2, new_rd_ia32_IMul);
894 * Creates an ia32 Mulh.
895 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
896 * this result while Mul returns the lower 32 bit.
898 * @return the created ia32 Mulh node
900 static ir_node *gen_Mulh(ir_node *node) {
901 ir_node *block = transform_node(get_nodes_block(node));
902 ir_node *op1 = get_irn_n(node, 0);
903 ir_node *new_op1 = transform_node(op1);
904 ir_node *op2 = get_irn_n(node, 1);
905 ir_node *new_op2 = transform_node(op2);
906 ir_graph *irg = env.irg;
907 dbg_info *dbgi = get_irn_dbg_info(node);
908 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
909 ir_mode *mode = get_irn_mode(node);
910 ir_node *proj_EAX, *proj_EDX, *res;
913 assert(!mode_is_float(mode) && "Mulh with float not supported");
914 if (mode_is_signed(mode)) {
915 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
917 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
920 set_ia32_commutative(res);
921 set_ia32_am_support(res, ia32_am_Source);
923 set_ia32_am_support(res, ia32_am_Source);
925 proj_EAX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
926 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
930 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
938 * Creates an ia32 And.
940 * @return The created ia32 And node
942 static ir_node *gen_And(ir_node *node) {
943 ir_node *op1 = get_And_left(node);
944 ir_node *op2 = get_And_right(node);
946 assert (! mode_is_float(get_irn_mode(node)));
947 return gen_binop(node, op1, op2, new_rd_ia32_And);
953 * Creates an ia32 Or.
955 * @return The created ia32 Or node
957 static ir_node *gen_Or(ir_node *node) {
958 ir_node *op1 = get_Or_left(node);
959 ir_node *op2 = get_Or_right(node);
961 assert (! mode_is_float(get_irn_mode(node)));
962 return gen_binop(node, op1, op2, new_rd_ia32_Or);
968 * Creates an ia32 Eor.
970 * @return The created ia32 Eor node
972 static ir_node *gen_Eor(ir_node *node) {
973 ir_node *op1 = get_Eor_left(node);
974 ir_node *op2 = get_Eor_right(node);
976 assert(! mode_is_float(get_irn_mode(node)));
977 return gen_binop(node, op1, op2, new_rd_ia32_Xor);
983 * Creates an ia32 Max.
985 * @return the created ia32 Max node
987 static ir_node *gen_Max(ir_node *node) {
988 ir_node *block = transform_node(get_nodes_block(node));
989 ir_node *op1 = get_irn_n(node, 0);
990 ir_node *new_op1 = transform_node(op1);
991 ir_node *op2 = get_irn_n(node, 1);
992 ir_node *new_op2 = transform_node(op2);
993 ir_graph *irg = env.irg;
994 ir_mode *mode = get_irn_mode(node);
995 dbg_info *dbgi = get_irn_dbg_info(node);
996 ir_mode *op_mode = get_irn_mode(op1);
999 assert(get_mode_size_bits(mode) == 32);
1001 if (mode_is_float(mode)) {
1003 if (USE_SSE2(env.cg)) {
1004 new_op = gen_binop_float(node, new_op1, new_op2, new_rd_ia32_xMax);
1006 panic("Can't create Max node");
1009 long pnc = pn_Cmp_Gt;
1010 if (! mode_is_signed(op_mode)) {
1011 pnc |= ia32_pn_Cmp_Unsigned;
1013 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1014 set_ia32_pncode(new_op, pnc);
1015 set_ia32_am_support(new_op, ia32_am_None);
1017 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1023 * Creates an ia32 Min.
1025 * @return the created ia32 Min node
1027 static ir_node *gen_Min(ir_node *node) {
1028 ir_node *block = transform_node(get_nodes_block(node));
1029 ir_node *op1 = get_irn_n(node, 0);
1030 ir_node *new_op1 = transform_node(op1);
1031 ir_node *op2 = get_irn_n(node, 1);
1032 ir_node *new_op2 = transform_node(op2);
1033 ir_graph *irg = env.irg;
1034 ir_mode *mode = get_irn_mode(node);
1035 dbg_info *dbgi = get_irn_dbg_info(node);
1036 ir_mode *op_mode = get_irn_mode(op1);
1039 assert(get_mode_size_bits(mode) == 32);
1041 if (mode_is_float(mode)) {
1043 if (USE_SSE2(env.cg)) {
1044 new_op = gen_binop_float(node, op1, op2, new_rd_ia32_xMin);
1046 panic("can't create Min node");
1049 long pnc = pn_Cmp_Lt;
1050 if (! mode_is_signed(op_mode)) {
1051 pnc |= ia32_pn_Cmp_Unsigned;
1053 new_op = new_rd_ia32_CmpCMov(dbgi, irg, block, new_op1, new_op2, new_op1, new_op2);
1054 set_ia32_pncode(new_op, pnc);
1055 set_ia32_am_support(new_op, ia32_am_None);
1057 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1064 * Creates an ia32 Sub.
1066 * @return The created ia32 Sub node
1068 static ir_node *gen_Sub(ir_node *node) {
1069 ir_node *block = transform_node(get_nodes_block(node));
1070 ir_node *op1 = get_Sub_left(node);
1071 ir_node *new_op1 = transform_node(op1);
1072 ir_node *op2 = get_Sub_right(node);
1073 ir_node *new_op2 = transform_node(op2);
1074 ir_node *new_op = NULL;
1075 ir_graph *irg = env.irg;
1076 dbg_info *dbgi = get_irn_dbg_info(node);
1077 ir_mode *mode = get_irn_mode(node);
1078 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1079 ir_node *nomem = new_NoMem();
1080 ir_node *expr_op, *imm_op;
1082 /* Check if immediate optimization is on and */
1083 /* if it's an operation with immediate. */
1084 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
1085 expr_op = get_expr_op(new_op1, new_op2);
1087 assert((expr_op || imm_op) && "invalid operands");
1089 if (mode_is_float(mode)) {
1091 if (USE_SSE2(env.cg))
1092 return gen_binop_float(node, op1, op2, new_rd_ia32_xSub);
1094 return gen_binop_float(node, op1, op2, new_rd_ia32_vfsub);
1099 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
1100 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
1102 /* No expr_op means, that we have two const - one symconst and */
1103 /* one tarval or another symconst - because this case is not */
1104 /* covered by constant folding */
1105 /* We need to check for: */
1106 /* 1) symconst - const -> becomes a LEA */
1107 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
1108 /* linker doesn't support two symconsts */
1109 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
1110 /* this is the 2nd case */
1111 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
1112 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
1113 set_ia32_am_sc_sign(new_op);
1114 set_ia32_am_flavour(new_op, ia32_am_B);
1116 DBG_OPT_LEA3(op1, op2, node, new_op);
1117 } else if (tp1 == ia32_ImmSymConst) {
1118 tarval *tv = get_ia32_Immop_tarval(new_op2);
1119 long offs = get_tarval_long(tv);
1121 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1122 add_irn_dep(new_op, get_irg_frame(irg));
1123 DBG_OPT_LEA3(op1, op2, node, new_op);
1125 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
1126 add_ia32_am_offs_int(new_op, -offs);
1127 set_ia32_am_flavour(new_op, ia32_am_OB);
1128 set_ia32_am_support(new_op, ia32_am_Source);
1129 set_ia32_op_type(new_op, ia32_AddrModeS);
1130 } else if (tp2 == ia32_ImmSymConst) {
1131 tarval *tv = get_ia32_Immop_tarval(new_op1);
1132 long offs = get_tarval_long(tv);
1134 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
1135 add_irn_dep(new_op, get_irg_frame(irg));
1136 DBG_OPT_LEA3(op1, op2, node, new_op);
1138 add_ia32_am_offs_int(new_op, offs);
1139 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
1140 set_ia32_am_sc_sign(new_op);
1141 set_ia32_am_flavour(new_op, ia32_am_OB);
1142 set_ia32_am_support(new_op, ia32_am_Source);
1143 set_ia32_op_type(new_op, ia32_AddrModeS);
1145 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
1146 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
1147 tarval *restv = tarval_sub(tv1, tv2);
1149 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
1151 new_op = new_rd_ia32_Const(dbgi, irg, block);
1152 set_ia32_Const_tarval(new_op, restv);
1153 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
1156 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1158 } else if (imm_op) {
1159 if ((env.cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
1160 tarval_classification_t class_tv, class_negtv;
1161 tarval *tv = get_ia32_Immop_tarval(imm_op);
1163 /* optimize tarvals */
1164 class_tv = classify_tarval(tv);
1165 class_negtv = classify_tarval(tarval_neg(tv));
1167 if (class_tv == TV_CLASSIFY_ONE) {
1168 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
1169 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1170 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1172 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1173 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1174 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1175 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1181 /* This is a normal sub */
1182 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1184 /* set AM support */
1185 set_ia32_am_support(new_op, ia32_am_Full);
1187 fold_immediate(new_op, 2, 3);
1189 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1197 * Generates an ia32 DivMod with additional infrastructure for the
1198 * register allocator if needed.
1200 * @param dividend -no comment- :)
1201 * @param divisor -no comment- :)
1202 * @param dm_flav flavour_Div/Mod/DivMod
1203 * @return The created ia32 DivMod node
1205 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1206 ir_node *divisor, ia32_op_flavour_t dm_flav)
1208 ir_node *block = transform_node(get_nodes_block(node));
1209 ir_node *new_dividend = transform_node(dividend);
1210 ir_node *new_divisor = transform_node(divisor);
1211 ir_graph *irg = env.irg;
1212 dbg_info *dbgi = get_irn_dbg_info(node);
1213 ir_mode *mode = get_irn_mode(node);
1214 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1215 ir_node *res, *proj_div, *proj_mod;
1216 ir_node *edx_node, *cltd;
1217 ir_node *in_keep[2];
1218 ir_node *mem, *new_mem;
1219 ir_node *projs[pn_DivMod_max];
1222 ia32_collect_Projs(node, projs, pn_DivMod_max);
1224 proj_div = proj_mod = NULL;
1228 mem = get_Div_mem(node);
1229 mode = get_Div_resmode(node);
1230 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1231 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1234 mem = get_Mod_mem(node);
1235 mode = get_Mod_resmode(node);
1236 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1237 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1239 case flavour_DivMod:
1240 mem = get_DivMod_mem(node);
1241 mode = get_DivMod_resmode(node);
1242 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1243 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1244 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1247 panic("invalid divmod flavour!");
1249 new_mem = transform_node(mem);
1251 if (mode_is_signed(mode)) {
1252 /* in signed mode, we need to sign extend the dividend */
1253 cltd = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1254 new_dividend = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
1255 edx_node = new_rd_Proj(dbgi, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
1257 edx_node = new_rd_ia32_Const(dbgi, irg, block);
1258 add_irn_dep(edx_node, be_abi_get_start_barrier(env.cg->birg->abi));
1259 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
1262 if (mode_is_signed(mode)) {
1263 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1265 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
1268 set_ia32_exc_label(res, has_exc);
1270 /* Matze: code can't handle this at the moment... */
1272 /* set AM support */
1273 set_ia32_am_support(res, ia32_am_Source);
1276 /* check, which Proj-Keep, we need to add */
1278 if (proj_div == NULL) {
1279 /* We have only mod result: add div res Proj-Keep */
1280 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_div_res);
1283 if (proj_mod == NULL) {
1284 /* We have only div result: add mod res Proj-Keep */
1285 in_keep[i] = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_ia32_Div_mod_res);
1289 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, i, in_keep);
1291 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1298 * Wrapper for generate_DivMod. Sets flavour_Mod.
1301 static ir_node *gen_Mod(ir_node *node) {
1302 return generate_DivMod(node, get_Mod_left(node),
1303 get_Mod_right(node), flavour_Mod);
1307 * Wrapper for generate_DivMod. Sets flavour_Div.
1310 static ir_node *gen_Div(ir_node *node) {
1311 return generate_DivMod(node, get_Div_left(node),
1312 get_Div_right(node), flavour_Div);
1316 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1318 static ir_node *gen_DivMod(ir_node *node) {
1319 return generate_DivMod(node, get_DivMod_left(node),
1320 get_DivMod_right(node), flavour_DivMod);
1326 * Creates an ia32 floating Div.
1328 * @return The created ia32 xDiv node
1330 static ir_node *gen_Quot(ir_node *node) {
1331 ir_node *block = transform_node(get_nodes_block(node));
1332 ir_node *op1 = get_Quot_left(node);
1333 ir_node *new_op1 = transform_node(op1);
1334 ir_node *op2 = get_Quot_right(node);
1335 ir_node *new_op2 = transform_node(op2);
1336 ir_graph *irg = env.irg;
1337 dbg_info *dbgi = get_irn_dbg_info(node);
1338 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1339 ir_node *nomem = new_rd_NoMem(env.irg);
1343 if (USE_SSE2(env.cg)) {
1344 ir_mode *mode = get_irn_mode(op1);
1345 if (is_ia32_xConst(new_op2)) {
1346 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1347 set_ia32_am_support(new_op, ia32_am_None);
1348 copy_ia32_Immop_attr(new_op, new_op2);
1350 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1351 // Matze: disabled for now, spillslot coalescer fails
1352 //set_ia32_am_support(new_op, ia32_am_Source);
1354 set_ia32_ls_mode(new_op, mode);
1356 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1357 // Matze: disabled for now (spillslot coalescer fails)
1358 //set_ia32_am_support(new_op, ia32_am_Source);
1360 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1366 * Creates an ia32 Shl.
1368 * @return The created ia32 Shl node
1370 static ir_node *gen_Shl(ir_node *node) {
1371 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1378 * Creates an ia32 Shr.
1380 * @return The created ia32 Shr node
1382 static ir_node *gen_Shr(ir_node *node) {
1383 return gen_shift_binop(node, get_Shr_left(node),
1384 get_Shr_right(node), new_rd_ia32_Shr);
1390 * Creates an ia32 Sar.
1392 * @return The created ia32 Shrs node
1394 static ir_node *gen_Shrs(ir_node *node) {
1395 return gen_shift_binop(node, get_Shrs_left(node),
1396 get_Shrs_right(node), new_rd_ia32_Sar);
1402 * Creates an ia32 RotL.
1404 * @param op1 The first operator
1405 * @param op2 The second operator
1406 * @return The created ia32 RotL node
1408 static ir_node *gen_RotL(ir_node *node,
1409 ir_node *op1, ir_node *op2) {
1410 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1416 * Creates an ia32 RotR.
1417 * NOTE: There is no RotR with immediate because this would always be a RotL
1418 * "imm-mode_size_bits" which can be pre-calculated.
1420 * @param op1 The first operator
1421 * @param op2 The second operator
1422 * @return The created ia32 RotR node
1424 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1426 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1432 * Creates an ia32 RotR or RotL (depending on the found pattern).
1434 * @return The created ia32 RotL or RotR node
1436 static ir_node *gen_Rot(ir_node *node) {
1437 ir_node *rotate = NULL;
1438 ir_node *op1 = get_Rot_left(node);
1439 ir_node *op2 = get_Rot_right(node);
1441 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1442 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1443 that means we can create a RotR instead of an Add and a RotL */
1445 if (get_irn_op(op2) == op_Add) {
1447 ir_node *left = get_Add_left(add);
1448 ir_node *right = get_Add_right(add);
1449 if (is_Const(right)) {
1450 tarval *tv = get_Const_tarval(right);
1451 ir_mode *mode = get_irn_mode(node);
1452 long bits = get_mode_size_bits(mode);
1454 if (get_irn_op(left) == op_Minus &&
1455 tarval_is_long(tv) &&
1456 get_tarval_long(tv) == bits)
1458 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1459 rotate = gen_RotR(node, op1, get_Minus_op(left));
1464 if (rotate == NULL) {
1465 rotate = gen_RotL(node, op1, op2);
1474 * Transforms a Minus node.
1476 * @param op The Minus operand
1477 * @return The created ia32 Minus node
1479 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1480 ir_node *block = transform_node(get_nodes_block(node));
1481 ir_graph *irg = env.irg;
1482 dbg_info *dbgi = get_irn_dbg_info(node);
1483 ir_mode *mode = get_irn_mode(node);
1488 if (mode_is_float(mode)) {
1489 ir_node *new_op = transform_node(op);
1491 if (USE_SSE2(env.cg)) {
1492 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
1493 ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg);
1494 ir_node *nomem = new_rd_NoMem(irg);
1496 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1498 size = get_mode_size_bits(mode);
1499 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1501 set_ia32_am_sc(res, ent);
1502 set_ia32_op_type(res, ia32_AddrModeS);
1503 set_ia32_ls_mode(res, mode);
1505 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1508 res = gen_unop(node, op, new_rd_ia32_Neg);
1511 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1517 * Transforms a Minus node.
1519 * @return The created ia32 Minus node
1521 static ir_node *gen_Minus(ir_node *node) {
1522 return gen_Minus_ex(node, get_Minus_op(node));
1527 * Transforms a Not node.
1529 * @return The created ia32 Not node
1531 static ir_node *gen_Not(ir_node *node) {
1532 ir_node *op = get_Not_op(node);
1534 assert (! mode_is_float(get_irn_mode(node)));
1535 return gen_unop(node, op, new_rd_ia32_Not);
1541 * Transforms an Abs node.
1543 * @return The created ia32 Abs node
1545 static ir_node *gen_Abs(ir_node *node) {
1546 ir_node *block = transform_node(get_nodes_block(node));
1547 ir_node *op = get_Abs_op(node);
1548 ir_node *new_op = transform_node(op);
1549 ir_graph *irg = env.irg;
1550 dbg_info *dbgi = get_irn_dbg_info(node);
1551 ir_mode *mode = get_irn_mode(node);
1552 ir_node *noreg_gp = ia32_new_NoReg_gp(env.cg);
1553 ir_node *noreg_fp = ia32_new_NoReg_fp(env.cg);
1554 ir_node *nomem = new_NoMem();
1555 ir_node *res, *p_eax, *p_edx;
1559 if (mode_is_float(mode)) {
1561 if (USE_SSE2(env.cg)) {
1562 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1564 size = get_mode_size_bits(mode);
1565 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1567 set_ia32_am_sc(res, ent);
1569 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1571 set_ia32_op_type(res, ia32_AddrModeS);
1572 set_ia32_ls_mode(res, mode);
1575 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1576 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1580 res = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1581 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1583 p_eax = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EAX);
1584 p_edx = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1586 res = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1589 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1590 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1599 * Transforms a Load.
1601 * @return the created ia32 Load node
1603 static ir_node *gen_Load(ir_node *node) {
1604 ir_node *block = transform_node(get_nodes_block(node));
1605 ir_node *ptr = get_Load_ptr(node);
1606 ir_node *new_ptr = transform_node(ptr);
1607 ir_node *mem = get_Load_mem(node);
1608 ir_node *new_mem = transform_node(mem);
1609 ir_graph *irg = env.irg;
1610 dbg_info *dbgi = get_irn_dbg_info(node);
1611 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1612 ir_mode *mode = get_Load_mode(node);
1614 ir_node *lptr = new_ptr;
1617 ir_node *projs[pn_Load_max];
1618 ia32_am_flavour_t am_flav = ia32_am_B;
1620 ia32_collect_Projs(node, projs, pn_Load_max);
1622 /* address might be a constant (symconst or absolute address) */
1623 if (is_ia32_Const(new_ptr)) {
1628 if (mode_is_float(mode)) {
1630 if (USE_SSE2(env.cg)) {
1631 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1632 res_mode = mode_xmm;
1634 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem);
1635 res_mode = mode_vfp;
1638 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1643 check for special case: the loaded value might not be used
1645 if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
1646 /* add a result proj and a Keep to produce a pseudo use */
1647 ir_node *proj = new_r_Proj(irg, block, new_op, mode_Iu,
1649 be_new_Keep(arch_get_irn_reg_class(env.cg->arch_env, proj, -1), irg, block, 1, &proj);
1652 /* base is a constant address */
1654 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1655 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1656 am_flav = ia32_am_N;
1658 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1659 long offs = get_tarval_long(tv);
1661 add_ia32_am_offs_int(new_op, offs);
1662 am_flav = ia32_am_O;
1666 set_ia32_am_support(new_op, ia32_am_Source);
1667 set_ia32_op_type(new_op, ia32_AddrModeS);
1668 set_ia32_am_flavour(new_op, am_flav);
1669 set_ia32_ls_mode(new_op, mode);
1671 /* make sure we are scheduled behind the initial IncSP/Barrier
1672 * to avoid spills being placed before it
1674 if (block == get_irg_start_block(irg)) {
1675 add_irn_dep(new_op, get_irg_frame(irg));
1678 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1679 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1687 * Transforms a Store.
1689 * @return the created ia32 Store node
1691 static ir_node *gen_Store(ir_node *node) {
1692 ir_node *block = transform_node(get_nodes_block(node));
1693 ir_node *ptr = get_Store_ptr(node);
1694 ir_node *new_ptr = transform_node(ptr);
1695 ir_node *val = get_Store_value(node);
1696 ir_node *new_val = transform_node(val);
1697 ir_node *mem = get_Store_mem(node);
1698 ir_node *new_mem = transform_node(mem);
1699 ir_graph *irg = env.irg;
1700 dbg_info *dbgi = get_irn_dbg_info(node);
1701 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1702 ir_node *sptr = new_ptr;
1703 ir_mode *mode = get_irn_mode(val);
1704 ir_node *sval = new_val;
1707 ia32_am_flavour_t am_flav = ia32_am_B;
1709 if (is_ia32_Const(new_val)) {
1710 assert(!mode_is_float(mode));
1714 /* address might be a constant (symconst or absolute address) */
1715 if (is_ia32_Const(new_ptr)) {
1720 if (mode_is_float(mode)) {
1722 if (USE_SSE2(env.cg)) {
1723 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, sval, new_mem);
1725 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, sval, new_mem);
1727 } else if (get_mode_size_bits(mode) == 8) {
1728 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg, sval, new_mem);
1730 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, sval, new_mem);
1733 /* stored const is an immediate value */
1734 if (is_ia32_Const(new_val)) {
1735 assert(!mode_is_float(mode));
1736 copy_ia32_Immop_attr(new_op, new_val);
1739 /* base is an constant address */
1741 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1742 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1743 am_flav = ia32_am_N;
1745 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1746 long offs = get_tarval_long(tv);
1748 add_ia32_am_offs_int(new_op, offs);
1749 am_flav = ia32_am_O;
1753 set_ia32_am_support(new_op, ia32_am_Dest);
1754 set_ia32_op_type(new_op, ia32_AddrModeD);
1755 set_ia32_am_flavour(new_op, am_flav);
1756 set_ia32_ls_mode(new_op, mode);
1758 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1759 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1767 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1769 * @return The transformed node.
1771 static ir_node *gen_Cond(ir_node *node) {
1772 ir_node *block = transform_node(get_nodes_block(node));
1773 ir_graph *irg = env.irg;
1774 dbg_info *dbgi = get_irn_dbg_info(node);
1775 ir_node *sel = get_Cond_selector(node);
1776 ir_mode *sel_mode = get_irn_mode(sel);
1777 ir_node *res = NULL;
1778 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
1779 ir_node *cnst, *expr;
1781 if (is_Proj(sel) && sel_mode == mode_b) {
1782 ir_node *pred = get_Proj_pred(sel);
1783 ir_node *cmp_a = get_Cmp_left(pred);
1784 ir_node *new_cmp_a = transform_node(cmp_a);
1785 ir_node *cmp_b = get_Cmp_right(pred);
1786 ir_node *new_cmp_b = transform_node(cmp_b);
1787 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1788 ir_node *nomem = new_NoMem();
1790 int pnc = get_Proj_proj(sel);
1791 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1792 pnc |= ia32_pn_Cmp_Unsigned;
1795 /* check if we can use a CondJmp with immediate */
1796 cnst = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_cmp_a, new_cmp_b) : NULL;
1797 expr = get_expr_op(new_cmp_a, new_cmp_b);
1799 if (cnst != NULL && expr != NULL) {
1800 /* immop has to be the right operand, we might need to flip pnc */
1801 if(cnst != new_cmp_b) {
1802 pnc = get_inversed_pnc(pnc);
1805 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_needs_gp_reg(get_irn_mode(expr))) {
1806 if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
1807 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1809 /* a Cmp A =/!= 0 */
1810 ir_node *op1 = expr;
1811 ir_node *op2 = expr;
1814 /* check, if expr is an only once used And operation */
1815 if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
1816 op1 = get_irn_n(expr, 2);
1817 op2 = get_irn_n(expr, 3);
1819 is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
1821 res = new_rd_ia32_TestJmp(dbgi, irg, block, op1, op2);
1822 set_ia32_pncode(res, pnc);
1825 copy_ia32_Immop_attr(res, expr);
1828 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1833 if (mode_is_float(cmp_mode)) {
1835 if (USE_SSE2(env.cg)) {
1836 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1837 set_ia32_ls_mode(res, cmp_mode);
1843 assert(get_mode_size_bits(cmp_mode) == 32);
1844 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, expr, noreg, nomem);
1846 copy_ia32_Immop_attr(res, cnst);
1849 ir_mode *cmp_mode = get_irn_mode(cmp_a);
1851 if (mode_is_float(cmp_mode)) {
1853 if (USE_SSE2(env.cg)) {
1854 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1855 set_ia32_ls_mode(res, cmp_mode);
1858 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1859 proj_eax = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_vfCondJmp_temp_reg_eax);
1860 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1864 assert(get_mode_size_bits(cmp_mode) == 32);
1865 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1866 set_ia32_commutative(res);
1870 set_ia32_pncode(res, pnc);
1871 // Matze: disabled for now, because the default collect_spills_walker
1872 // is not able to detect the mode of the spilled value
1873 // moreover, the lea optimize phase freely exchanges left/right
1874 // without updating the pnc
1875 //set_ia32_am_support(res, ia32_am_Source);
1878 /* determine the smallest switch case value */
1879 ir_node *new_sel = transform_node(sel);
1880 int switch_min = INT_MAX;
1881 const ir_edge_t *edge;
1883 foreach_out_edge(node, edge) {
1884 int pn = get_Proj_proj(get_edge_src_irn(edge));
1885 switch_min = pn < switch_min ? pn : switch_min;
1889 /* if smallest switch case is not 0 we need an additional sub */
1890 res = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1891 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1892 add_ia32_am_offs_int(res, -switch_min);
1893 set_ia32_am_flavour(res, ia32_am_OB);
1894 set_ia32_am_support(res, ia32_am_Source);
1895 set_ia32_op_type(res, ia32_AddrModeS);
1898 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, switch_min ? res : new_sel, mode_T);
1899 set_ia32_pncode(res, get_Cond_defaultProj(node));
1902 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1909 * Transforms a CopyB node.
1911 * @return The transformed node.
1913 static ir_node *gen_CopyB(ir_node *node) {
1914 ir_node *block = transform_node(get_nodes_block(node));
1915 ir_node *src = get_CopyB_src(node);
1916 ir_node *new_src = transform_node(src);
1917 ir_node *dst = get_CopyB_dst(node);
1918 ir_node *new_dst = transform_node(dst);
1919 ir_node *mem = get_CopyB_mem(node);
1920 ir_node *new_mem = transform_node(mem);
1921 ir_node *res = NULL;
1922 ir_graph *irg = env.irg;
1923 dbg_info *dbgi = get_irn_dbg_info(node);
1924 int size = get_type_size_bytes(get_CopyB_type(node));
1925 ir_mode *dst_mode = get_irn_mode(dst);
1926 ir_mode *src_mode = get_irn_mode(src);
1930 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1931 /* then we need the size explicitly in ECX. */
1932 if (size >= 32 * 4) {
1933 rem = size & 0x3; /* size % 4 */
1936 res = new_rd_ia32_Const(dbgi, irg, block);
1937 add_irn_dep(res, be_abi_get_start_barrier(env.cg->birg->abi));
1938 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1940 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1941 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1943 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1944 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1945 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1946 in[2] = new_r_Proj(irg, block, res, mode_Iu, pn_ia32_CopyB_CNT);
1947 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1950 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1951 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1953 /* ok: now attach Proj's because movsd will destroy esi and edi */
1954 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1955 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1956 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1959 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
1967 * Transforms a Mux node into CMov.
1969 * @return The transformed node.
1971 static ir_node *gen_Mux(ir_node *node) {
1972 ir_node *new_op = new_rd_ia32_CMov(env.dbgi, env.irg, env.block, \
1973 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env.mode);
1975 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
1981 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block,
1982 ir_node *cmp_a, ir_node *cmp_b, ir_node *psi_true,
1983 ir_node *psi_default);
1986 * Transforms a Psi node into CMov.
1988 * @return The transformed node.
1990 static ir_node *gen_Psi(ir_node *node) {
1991 ir_node *block = transform_node(get_nodes_block(node));
1992 ir_node *psi_true = get_Psi_val(node, 0);
1993 ir_node *new_psi_true = transform_node(psi_true);
1994 ir_node *psi_default = get_Psi_default(node);
1995 ir_node *new_psi_default = transform_node(psi_default);
1996 ia32_code_gen_t *cg = env.cg;
1997 ir_graph *irg = env.irg;
1998 dbg_info *dbgi = get_irn_dbg_info(node);
1999 ir_mode *mode = get_irn_mode(node);
2000 ir_node *cmp_proj = get_Mux_sel(node);
2001 ir_node *noreg = ia32_new_NoReg_gp(cg);
2002 ir_node *nomem = new_rd_NoMem(irg);
2003 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
2004 ir_node *new_cmp_a, *new_cmp_b;
2008 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
2010 cmp = get_Proj_pred(cmp_proj);
2011 cmp_a = get_Cmp_left(cmp);
2012 cmp_b = get_Cmp_right(cmp);
2013 cmp_mode = get_irn_mode(cmp_a);
2014 new_cmp_a = transform_node(cmp_a);
2015 new_cmp_b = transform_node(cmp_b);
2017 pnc = get_Proj_proj(cmp_proj);
2018 if (mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2019 pnc |= ia32_pn_Cmp_Unsigned;
2022 if (mode_is_float(mode)) {
2023 /* floating point psi */
2026 /* 1st case: compare operands are float too */
2028 /* psi(cmp(a, b), t, f) can be done as: */
2029 /* tmp = cmp a, b */
2030 /* tmp2 = t and tmp */
2031 /* tmp3 = f and not tmp */
2032 /* res = tmp2 or tmp3 */
2034 /* in case the compare operands are int, we move them into xmm register */
2035 if (! mode_is_float(get_irn_mode(cmp_a))) {
2036 new_cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_a, node, mode_xmm);
2037 new_cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, new_cmp_b, node, mode_xmm);
2039 pnc |= 8; /* transform integer compare to fp compare */
2042 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, new_cmp_a, new_cmp_b, nomem);
2043 set_ia32_pncode(new_op, pnc);
2044 set_ia32_am_support(new_op, ia32_am_Source);
2045 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2047 and1 = new_rd_ia32_xAnd(dbgi, irg, block, noreg, noreg, new_psi_true, new_op, nomem);
2048 set_ia32_am_support(and1, ia32_am_None);
2049 set_ia32_commutative(and1);
2050 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
2052 and2 = new_rd_ia32_xAndNot(dbgi, irg, block, noreg, noreg, new_op, new_psi_default, nomem);
2053 set_ia32_am_support(and2, ia32_am_None);
2054 set_ia32_commutative(and2);
2055 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
2057 new_op = new_rd_ia32_xOr(dbgi, irg, block, noreg, noreg, and1, and2, nomem);
2058 set_ia32_am_support(new_op, ia32_am_None);
2059 set_ia32_commutative(new_op);
2060 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2064 new_op = new_rd_ia32_vfCMov(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2065 set_ia32_pncode(new_op, pnc);
2066 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2071 construct_binop_func *set_func = NULL;
2072 cmov_func_t *cmov_func = NULL;
2074 if (mode_is_float(get_irn_mode(cmp_a))) {
2075 /* 1st case: compare operands are floats */
2080 set_func = new_rd_ia32_xCmpSet;
2081 cmov_func = new_rd_ia32_xCmpCMov;
2085 set_func = new_rd_ia32_vfCmpSet;
2086 cmov_func = new_rd_ia32_vfCmpCMov;
2089 pnc &= ~0x8; /* fp compare -> int compare */
2092 /* 2nd case: compare operand are integer too */
2093 set_func = new_rd_ia32_CmpSet;
2094 cmov_func = new_rd_ia32_CmpCMov;
2097 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
2098 if (is_ia32_Const_0(new_cmp_b) && is_Proj(new_cmp_a) && (is_ia32_And(get_Proj_pred(new_cmp_a)) || is_ia32_Or(get_Proj_pred(new_cmp_a)))) {
2099 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2100 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2101 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2102 set_ia32_pncode(new_op, pnc);
2104 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2105 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2106 /* we invert condition and set default to 0 */
2107 new_op = new_rd_ia32_PsiCondSet(dbgi, irg, block, new_cmp_a);
2108 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2111 /* otherwise: use CMOVcc */
2112 new_op = new_rd_ia32_PsiCondCMov(dbgi, irg, block, new_cmp_a, new_psi_true, new_psi_default);
2113 set_ia32_pncode(new_op, pnc);
2116 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2119 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
2120 /* first case for SETcc: default is 0, set to 1 iff condition is true */
2121 new_op = gen_binop(node, cmp_a, cmp_b, set_func);
2122 set_ia32_pncode(new_op, pnc);
2123 set_ia32_am_support(new_op, ia32_am_Source);
2125 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
2126 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
2127 /* we invert condition and set default to 0 */
2128 new_op = gen_binop(node, cmp_a, cmp_b, set_func);
2129 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
2130 set_ia32_am_support(new_op, ia32_am_Source);
2133 /* otherwise: use CMOVcc */
2134 new_op = cmov_func(dbgi, irg, block, new_cmp_a, new_cmp_b, new_psi_true, new_psi_default);
2135 set_ia32_pncode(new_op, pnc);
2136 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2146 * Following conversion rules apply:
2150 * 1) n bit -> m bit n > m (downscale)
2152 * 2) n bit -> m bit n == m (sign change)
2154 * 3) n bit -> m bit n < m (upscale)
2155 * a) source is signed: movsx
2156 * b) source is unsigned: and with lower bits sets
2160 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
2164 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
2168 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
2169 * x87 is mode_E internally, conversions happen only at load and store
2170 * in non-strict semantic
2174 * Create a conversion from x87 state register to general purpose.
2176 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2177 ir_node *block = transform_node(get_nodes_block(node));
2178 ir_node *op = get_Conv_op(node);
2179 ir_node *new_op = transform_node(op);
2180 ia32_code_gen_t *cg = env.cg;
2181 ir_graph *irg = env.irg;
2182 dbg_info *dbgi = get_irn_dbg_info(node);
2183 ir_node *noreg = ia32_new_NoReg_gp(cg);
2184 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2185 ir_node *fist, *load;
2188 fist = new_rd_ia32_vfist(dbgi, irg, block,
2189 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2191 set_ia32_use_frame(fist);
2192 set_ia32_am_support(fist, ia32_am_Dest);
2193 set_ia32_op_type(fist, ia32_AddrModeD);
2194 set_ia32_am_flavour(fist, ia32_am_B);
2195 set_ia32_ls_mode(fist, mode_Iu);
2196 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2199 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2201 set_ia32_use_frame(load);
2202 set_ia32_am_support(load, ia32_am_Source);
2203 set_ia32_op_type(load, ia32_AddrModeS);
2204 set_ia32_am_flavour(load, ia32_am_B);
2205 set_ia32_ls_mode(load, mode_Iu);
2206 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2208 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2212 * Create a conversion from general purpose to x87 register
2214 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2215 ir_node *block = transform_node(get_nodes_block(node));
2216 ir_node *op = get_Conv_op(node);
2217 ir_node *new_op = transform_node(op);
2218 ir_graph *irg = env.irg;
2219 dbg_info *dbgi = get_irn_dbg_info(node);
2220 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2221 ir_node *nomem = new_NoMem();
2222 ir_node *fild, *store;
2225 /* first convert to 32 bit if necessary */
2226 src_bits = get_mode_size_bits(src_mode);
2227 if (src_bits == 8) {
2228 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2229 set_ia32_am_support(new_op, ia32_am_Source);
2230 set_ia32_ls_mode(new_op, src_mode);
2231 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2232 } else if (src_bits < 32) {
2233 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2234 set_ia32_am_support(new_op, ia32_am_Source);
2235 set_ia32_ls_mode(new_op, src_mode);
2236 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2240 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2242 set_ia32_use_frame(store);
2243 set_ia32_am_support(store, ia32_am_Dest);
2244 set_ia32_op_type(store, ia32_AddrModeD);
2245 set_ia32_am_flavour(store, ia32_am_OB);
2246 set_ia32_ls_mode(store, mode_Iu);
2249 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2251 set_ia32_use_frame(fild);
2252 set_ia32_am_support(fild, ia32_am_Source);
2253 set_ia32_op_type(fild, ia32_AddrModeS);
2254 set_ia32_am_flavour(fild, ia32_am_OB);
2255 set_ia32_ls_mode(fild, mode_Iu);
2257 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2261 * Transforms a Conv node.
2263 * @param env The transformation environment
2264 * @return The created ia32 Conv node
2266 static ir_node *gen_Conv(ir_node *node) {
2267 ir_node *block = transform_node(get_nodes_block(node));
2268 ir_node *op = get_Conv_op(node);
2269 ir_node *new_op = transform_node(op);
2270 ir_graph *irg = env.irg;
2271 dbg_info *dbgi = get_irn_dbg_info(node);
2272 ir_mode *src_mode = get_irn_mode(op);
2273 ir_mode *tgt_mode = get_irn_mode(node);
2274 int src_bits = get_mode_size_bits(src_mode);
2275 int tgt_bits = get_mode_size_bits(tgt_mode);
2276 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2277 ir_node *nomem = new_rd_NoMem(irg);
2280 if (src_mode == tgt_mode) {
2281 if (get_Conv_strict(node)) {
2282 if (USE_SSE2(env.cg)) {
2283 /* when we are in SSE mode, we can kill all strict no-op conversion */
2287 /* this should be optimized already, but who knows... */
2288 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2289 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2294 if (mode_is_float(src_mode)) {
2295 /* we convert from float ... */
2296 if (mode_is_float(tgt_mode)) {
2298 if (USE_SSE2(env.cg)) {
2299 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2300 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2301 set_ia32_ls_mode(res, tgt_mode);
2303 // Matze: TODO what about strict convs?
2304 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: strict conv %+F ignored yet\n", node));
2305 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2310 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2311 if (USE_SSE2(env.cg)) {
2312 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2313 set_ia32_ls_mode(res, src_mode);
2315 return gen_x87_fp_to_gp(node);
2319 /* we convert from int ... */
2320 if (mode_is_float(tgt_mode)) {
2323 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2324 if (USE_SSE2(env.cg)) {
2325 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2326 set_ia32_ls_mode(res, tgt_mode);
2327 if(src_bits == 32) {
2328 set_ia32_am_support(res, ia32_am_Source);
2331 return gen_x87_gp_to_fp(node, src_mode);
2335 ir_mode *smaller_mode;
2338 if (src_bits == tgt_bits) {
2339 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2343 if (src_bits < tgt_bits) {
2344 smaller_mode = src_mode;
2345 smaller_bits = src_bits;
2347 smaller_mode = tgt_mode;
2348 smaller_bits = tgt_bits;
2351 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2352 if (smaller_bits == 8) {
2353 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2354 set_ia32_ls_mode(res, smaller_mode);
2356 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2357 set_ia32_ls_mode(res, smaller_mode);
2359 set_ia32_am_support(res, ia32_am_Source);
2363 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2369 int check_immediate_constraint(tarval *tv, char immediate_constraint_type)
2373 assert(tarval_is_long(tv));
2374 val = get_tarval_long(tv);
2376 switch (immediate_constraint_type) {
2380 return val >= 0 && val <= 32;
2382 return val >= 0 && val <= 63;
2384 return val >= -128 && val <= 127;
2386 return val == 0xff || val == 0xffff;
2388 return val >= 0 && val <= 3;
2390 return val >= 0 && val <= 255;
2392 return val >= 0 && val <= 127;
2396 panic("Invalid immediate constraint found");
2400 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2403 tarval *offset = NULL;
2404 int offset_sign = 0;
2405 ir_entity *symconst_ent = NULL;
2406 int symconst_sign = 0;
2408 ir_node *cnst = NULL;
2409 ir_node *symconst = NULL;
2416 mode = get_irn_mode(node);
2417 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2418 !mode_is_reference(mode)) {
2422 if(is_Minus(node)) {
2424 node = get_Minus_op(node);
2427 if(is_Const(node)) {
2430 offset_sign = minus;
2431 } else if(is_SymConst(node)) {
2434 symconst_sign = minus;
2435 } else if(is_Add(node)) {
2436 ir_node *left = get_Add_left(node);
2437 ir_node *right = get_Add_right(node);
2438 if(is_Const(left) && is_SymConst(right)) {
2441 symconst_sign = minus;
2442 offset_sign = minus;
2443 } else if(is_SymConst(left) && is_Const(right)) {
2446 symconst_sign = minus;
2447 offset_sign = minus;
2449 } else if(is_Sub(node)) {
2450 ir_node *left = get_Add_left(node);
2451 ir_node *right = get_Add_right(node);
2452 if(is_Const(left) && is_SymConst(right)) {
2455 symconst_sign = !minus;
2456 offset_sign = minus;
2457 } else if(is_SymConst(left) && is_Const(right)) {
2460 symconst_sign = minus;
2461 offset_sign = !minus;
2468 offset = get_Const_tarval(cnst);
2469 if(!tarval_is_long(offset)) {
2470 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2475 if(!check_immediate_constraint(offset, immediate_constraint_type))
2478 if(symconst != NULL) {
2479 if(immediate_constraint_type != 0) {
2480 /* we need full 32bits for symconsts */
2484 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2486 symconst_ent = get_SymConst_entity(symconst);
2490 dbgi = get_irn_dbg_info(node);
2491 block = get_irg_start_block(irg);
2492 res = new_rd_ia32_Immediate(dbgi, irg, block);
2493 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2495 /* make sure we don't schedule stuff before the barrier */
2496 add_irn_dep(res, get_irg_frame(irg));
2498 /* misuse some fields for now... */
2499 attr = get_ia32_attr(res);
2500 attr->am_sc = symconst_ent;
2501 attr->data.am_sc_sign = symconst_sign;
2502 if(offset_sign && offset != NULL) {
2503 offset = tarval_neg(offset);
2505 attr->cnst_val.tv = offset;
2506 attr->data.imm_tp = ia32_ImmConst;
2511 typedef struct constraint_t constraint_t;
2512 struct constraint_t {
2515 const arch_register_req_t **out_reqs;
2517 const arch_register_req_t *req;
2518 unsigned immediate_possible;
2519 char immediate_type;
2522 void parse_asm_constraint(ir_node *node, int pos, constraint_t *constraint,
2525 int immediate_possible = 0;
2526 char immediate_type = 0;
2527 unsigned limited = 0;
2528 const arch_register_class_t *cls = NULL;
2530 struct obstack *obst;
2531 arch_register_req_t *req;
2532 unsigned *limited_ptr;
2536 /* TODO: replace all the asserts with nice error messages */
2538 printf("Constraint: %s\n", c);
2548 assert(cls == NULL ||
2549 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2550 cls = &ia32_reg_classes[CLASS_ia32_gp];
2551 limited |= 1 << REG_EAX;
2554 assert(cls == NULL ||
2555 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2556 cls = &ia32_reg_classes[CLASS_ia32_gp];
2557 limited |= 1 << REG_EBX;
2560 assert(cls == NULL ||
2561 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2562 cls = &ia32_reg_classes[CLASS_ia32_gp];
2563 limited |= 1 << REG_ECX;
2566 assert(cls == NULL ||
2567 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2568 cls = &ia32_reg_classes[CLASS_ia32_gp];
2569 limited |= 1 << REG_EDX;
2572 assert(cls == NULL ||
2573 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2574 cls = &ia32_reg_classes[CLASS_ia32_gp];
2575 limited |= 1 << REG_EDI;
2578 assert(cls == NULL ||
2579 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2580 cls = &ia32_reg_classes[CLASS_ia32_gp];
2581 limited |= 1 << REG_ESI;
2584 case 'q': /* q means lower part of the regs only, this makes no
2585 * difference to Q for us (we only assigne whole registers) */
2586 assert(cls == NULL ||
2587 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2588 cls = &ia32_reg_classes[CLASS_ia32_gp];
2589 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2593 assert(cls == NULL ||
2594 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2595 cls = &ia32_reg_classes[CLASS_ia32_gp];
2596 limited |= 1 << REG_EAX | 1 << REG_EDX;
2599 assert(cls == NULL ||
2600 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2601 cls = &ia32_reg_classes[CLASS_ia32_gp];
2602 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2603 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2610 assert(cls == NULL);
2611 cls = &ia32_reg_classes[CLASS_ia32_gp];
2617 assert(cls == NULL);
2618 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2623 assert(cls == NULL);
2624 /* TODO: check that sse2 is supported */
2625 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2635 assert(!immediate_possible);
2636 immediate_possible = 1;
2637 immediate_type = *c;
2641 assert(!immediate_possible);
2642 immediate_possible = 1;
2646 assert(!immediate_possible && cls == NULL);
2647 immediate_possible = 1;
2648 cls = &ia32_reg_classes[CLASS_ia32_gp];
2661 assert(constraint->is_in && "can only specify same constraint "
2664 sscanf(c, "%d%n", &same_as, &p);
2671 case 'E': /* no float consts yet */
2672 case 'F': /* no float consts yet */
2673 case 's': /* makes no sense on x86 */
2674 case 'X': /* we can't support that in firm */
2678 case '<': /* no autodecrement on x86 */
2679 case '>': /* no autoincrement on x86 */
2680 case 'C': /* sse constant not supported yet */
2681 case 'G': /* 80387 constant not supported yet */
2682 case 'y': /* we don't support mmx registers yet */
2683 case 'Z': /* not available in 32 bit mode */
2684 case 'e': /* not available in 32 bit mode */
2685 assert(0 && "asm constraint not supported");
2688 assert(0 && "unknown asm constraint found");
2695 const arch_register_req_t *other_constr;
2697 assert(cls == NULL && "same as and register constraint not supported");
2698 assert(!immediate_possible && "same as and immediate constraint not "
2700 assert(same_as < constraint->n_outs && "wrong constraint number in "
2701 "same_as constraint");
2703 other_constr = constraint->out_reqs[same_as];
2705 req = obstack_alloc(obst, sizeof(req[0]));
2706 req->cls = other_constr->cls;
2707 req->type = arch_register_req_type_should_be_same;
2708 req->limited = NULL;
2709 req->other_same = pos;
2710 req->other_different = -1;
2712 /* switch constraints. This is because in firm we have same_as
2713 * constraints on the output constraints while in the gcc asm syntax
2714 * they are specified on the input constraints */
2715 constraint->req = other_constr;
2716 constraint->out_reqs[same_as] = req;
2717 constraint->immediate_possible = 0;
2721 if(immediate_possible && cls == NULL) {
2722 cls = &ia32_reg_classes[CLASS_ia32_gp];
2724 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2725 assert(cls != NULL);
2727 if(immediate_possible) {
2728 assert(constraint->is_in
2729 && "imeediates make no sense for output constraints");
2731 /* todo: check types (no float input on 'r' constrainted in and such... */
2734 obst = get_irg_obstack(irg);
2737 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2738 limited_ptr = (unsigned*) (req+1);
2740 req = obstack_alloc(obst, sizeof(req[0]));
2742 memset(req, 0, sizeof(req[0]));
2745 req->type = arch_register_req_type_limited;
2746 *limited_ptr = limited;
2747 req->limited = limited_ptr;
2749 req->type = arch_register_req_type_normal;
2753 constraint->req = req;
2754 constraint->immediate_possible = immediate_possible;
2755 constraint->immediate_type = immediate_type;
2759 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2762 panic("Clobbers not supported yet");
2765 ir_node *gen_ASM(ir_node *node)
2768 ir_graph *irg = env.irg;
2769 ir_node *block = transform_node(get_nodes_block(node));
2770 dbg_info *dbgi = get_irn_dbg_info(node);
2777 ia32_asm_attr_t *attr;
2778 const arch_register_req_t **out_reqs;
2779 const arch_register_req_t **in_reqs;
2780 struct obstack *obst;
2781 constraint_t parsed_constraint;
2783 /* assembler could contain float statements */
2786 /* transform inputs */
2787 arity = get_irn_arity(node);
2788 in = alloca(arity * sizeof(in[0]));
2789 memset(in, 0, arity * sizeof(in[0]));
2791 n_outs = get_ASM_n_output_constraints(node);
2792 n_clobbers = get_ASM_n_clobbers(node);
2793 out_arity = n_outs + n_clobbers;
2795 /* construct register constraints */
2796 obst = get_irg_obstack(irg);
2797 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2798 parsed_constraint.out_reqs = out_reqs;
2799 parsed_constraint.n_outs = n_outs;
2800 parsed_constraint.is_in = 0;
2801 for(i = 0; i < out_arity; ++i) {
2805 const ir_asm_constraint *constraint;
2806 constraint = & get_ASM_output_constraints(node) [i];
2807 c = get_id_str(constraint->constraint);
2808 parse_asm_constraint(node, i, &parsed_constraint, c);
2810 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2811 c = get_id_str(glob_id);
2812 parse_clobber(node, i, &parsed_constraint, c);
2814 out_reqs[i] = parsed_constraint.req;
2817 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2818 parsed_constraint.is_in = 1;
2819 for(i = 0; i < arity; ++i) {
2820 const ir_asm_constraint *constraint;
2824 constraint = & get_ASM_input_constraints(node) [i];
2825 constr_id = constraint->constraint;
2826 c = get_id_str(constr_id);
2827 parse_asm_constraint(node, i, &parsed_constraint, c);
2828 in_reqs[i] = parsed_constraint.req;
2830 if(parsed_constraint.immediate_possible) {
2831 ir_node *pred = get_irn_n(node, i);
2832 char imm_type = parsed_constraint.immediate_type;
2833 ir_node *immediate = try_create_Immediate(pred, imm_type);
2835 if(immediate != NULL) {
2841 /* transform inputs */
2842 for(i = 0; i < arity; ++i) {
2844 ir_node *transformed;
2849 pred = get_irn_n(node, i);
2850 transformed = transform_node(pred);
2851 in[i] = transformed;
2854 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2856 generic_attr = get_irn_generic_attr(res);
2857 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2858 attr->asm_text = get_ASM_text(node);
2859 set_ia32_out_req_all(res, out_reqs);
2860 set_ia32_in_req_all(res, in_reqs);
2862 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2867 /********************************************
2870 * | |__ ___ _ __ ___ __| | ___ ___
2871 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2872 * | |_) | __/ | | | (_) | (_| | __/\__ \
2873 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2875 ********************************************/
2877 static ir_node *gen_be_StackParam(ir_node *node) {
2878 ir_node *block = transform_node(get_nodes_block(node));
2879 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2880 ir_node *new_ptr = transform_node(ptr);
2881 ir_node *new_op = NULL;
2882 ir_graph *irg = env.irg;
2883 dbg_info *dbgi = get_irn_dbg_info(node);
2884 ir_node *nomem = new_rd_NoMem(env.irg);
2885 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
2886 ir_mode *load_mode = get_irn_mode(node);
2887 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2891 if (mode_is_float(load_mode)) {
2893 if (USE_SSE2(env.cg)) {
2894 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2895 pn_res = pn_ia32_xLoad_res;
2896 proj_mode = mode_xmm;
2898 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem);
2899 pn_res = pn_ia32_vfld_res;
2900 proj_mode = mode_vfp;
2903 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2904 proj_mode = mode_Iu;
2905 pn_res = pn_ia32_Load_res;
2908 set_ia32_frame_ent(new_op, ent);
2909 set_ia32_use_frame(new_op);
2911 set_ia32_am_support(new_op, ia32_am_Source);
2912 set_ia32_op_type(new_op, ia32_AddrModeS);
2913 set_ia32_am_flavour(new_op, ia32_am_B);
2914 set_ia32_ls_mode(new_op, load_mode);
2915 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2917 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2919 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2923 * Transforms a FrameAddr into an ia32 Add.
2925 static ir_node *gen_be_FrameAddr(ir_node *node) {
2926 ir_node *block = transform_node(get_nodes_block(node));
2927 ir_node *op = get_irn_n(node, be_pos_FrameAddr_ptr);
2928 ir_node *new_op = transform_node(op);
2929 ir_graph *irg = env.irg;
2930 dbg_info *dbgi = get_irn_dbg_info(node);
2931 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2934 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2935 set_ia32_frame_ent(res, arch_get_frame_entity(env.cg->arch_env, node));
2936 set_ia32_am_support(res, ia32_am_Full);
2937 set_ia32_use_frame(res);
2938 set_ia32_am_flavour(res, ia32_am_OB);
2940 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env.cg, node));
2946 * Transforms a FrameLoad into an ia32 Load.
2948 static ir_node *gen_be_FrameLoad(ir_node *node) {
2949 ir_node *block = transform_node(get_nodes_block(node));
2950 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2951 ir_node *new_mem = transform_node(mem);
2952 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2953 ir_node *new_ptr = transform_node(ptr);
2954 ir_node *new_op = NULL;
2955 ir_graph *irg = env.irg;
2956 dbg_info *dbgi = get_irn_dbg_info(node);
2957 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
2958 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
2959 ir_mode *mode = get_type_mode(get_entity_type(ent));
2960 ir_node *projs[pn_Load_max];
2962 ia32_collect_Projs(node, projs, pn_Load_max);
2964 if (mode_is_float(mode)) {
2966 if (USE_SSE2(env.cg)) {
2967 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2970 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
2974 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2977 set_ia32_frame_ent(new_op, ent);
2978 set_ia32_use_frame(new_op);
2980 set_ia32_am_support(new_op, ia32_am_Source);
2981 set_ia32_op_type(new_op, ia32_AddrModeS);
2982 set_ia32_am_flavour(new_op, ia32_am_B);
2983 set_ia32_ls_mode(new_op, mode);
2985 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
2992 * Transforms a FrameStore into an ia32 Store.
2994 static ir_node *gen_be_FrameStore(ir_node *node) {
2995 ir_node *block = transform_node(get_nodes_block(node));
2996 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2997 ir_node *new_mem = transform_node(mem);
2998 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2999 ir_node *new_ptr = transform_node(ptr);
3000 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
3001 ir_node *new_val = transform_node(val);
3002 ir_node *new_op = NULL;
3003 ir_graph *irg = env.irg;
3004 dbg_info *dbgi = get_irn_dbg_info(node);
3005 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3006 ir_entity *ent = arch_get_frame_entity(env.cg->arch_env, node);
3007 ir_mode *mode = get_irn_mode(val);
3009 if (mode_is_float(mode)) {
3011 if (USE_SSE2(env.cg)) {
3012 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3014 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3016 } else if (get_mode_size_bits(mode) == 8) {
3017 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3019 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3022 set_ia32_frame_ent(new_op, ent);
3023 set_ia32_use_frame(new_op);
3025 set_ia32_am_support(new_op, ia32_am_Dest);
3026 set_ia32_op_type(new_op, ia32_AddrModeD);
3027 set_ia32_am_flavour(new_op, ia32_am_B);
3028 set_ia32_ls_mode(new_op, mode);
3030 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3036 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3038 static ir_node *gen_be_Return(ir_node *node) {
3039 ir_graph *irg = env.irg;
3040 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3041 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3042 ir_entity *ent = get_irg_entity(irg);
3043 ir_type *tp = get_entity_type(ent);
3048 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3049 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3052 int pn_ret_val, pn_ret_mem, arity, i;
3054 assert(ret_val != NULL);
3055 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env.cg)) {
3056 return duplicate_node(node);
3059 res_type = get_method_res_type(tp, 0);
3061 if (! is_Primitive_type(res_type)) {
3062 return duplicate_node(node);
3065 mode = get_type_mode(res_type);
3066 if (! mode_is_float(mode)) {
3067 return duplicate_node(node);
3070 assert(get_method_n_ress(tp) == 1);
3072 pn_ret_val = get_Proj_proj(ret_val);
3073 pn_ret_mem = get_Proj_proj(ret_mem);
3075 /* get the Barrier */
3076 barrier = get_Proj_pred(ret_val);
3078 /* get result input of the Barrier */
3079 ret_val = get_irn_n(barrier, pn_ret_val);
3080 new_ret_val = transform_node(ret_val);
3082 /* get memory input of the Barrier */
3083 ret_mem = get_irn_n(barrier, pn_ret_mem);
3084 new_ret_mem = transform_node(ret_mem);
3086 frame = get_irg_frame(irg);
3088 dbgi = get_irn_dbg_info(barrier);
3089 block = transform_node(get_nodes_block(barrier));
3091 noreg = ia32_new_NoReg_gp(env.cg);
3093 /* store xmm0 onto stack */
3094 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
3095 set_ia32_ls_mode(sse_store, mode);
3096 set_ia32_op_type(sse_store, ia32_AddrModeD);
3097 set_ia32_use_frame(sse_store);
3098 set_ia32_am_flavour(sse_store, ia32_am_B);
3099 set_ia32_am_support(sse_store, ia32_am_Dest);
3102 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
3103 set_ia32_ls_mode(fld, mode);
3104 set_ia32_op_type(fld, ia32_AddrModeS);
3105 set_ia32_use_frame(fld);
3106 set_ia32_am_flavour(fld, ia32_am_B);
3107 set_ia32_am_support(fld, ia32_am_Source);
3109 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
3110 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
3111 arch_set_irn_register(env.cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
3113 /* create a new barrier */
3114 arity = get_irn_arity(barrier);
3115 in = alloca(arity * sizeof(in[0]));
3116 for (i = 0; i < arity; ++i) {
3119 if (i == pn_ret_val) {
3121 } else if (i == pn_ret_mem) {
3124 ir_node *in = get_irn_n(barrier, i);
3125 new_in = transform_node(in);
3130 new_barrier = new_ir_node(dbgi, irg, block,
3131 get_irn_op(barrier), get_irn_mode(barrier),
3133 copy_node_attr(barrier, new_barrier);
3134 duplicate_deps(barrier, new_barrier);
3135 set_new_node(barrier, new_barrier);
3136 mark_irn_visited(barrier);
3138 /* transform normally */
3139 return duplicate_node(node);
3143 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3145 static ir_node *gen_be_AddSP(ir_node *node) {
3146 ir_node *block = transform_node(get_nodes_block(node));
3147 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3148 ir_node *new_sz = transform_node(sz);
3149 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3150 ir_node *new_sp = transform_node(sp);
3151 ir_graph *irg = env.irg;
3152 dbg_info *dbgi = get_irn_dbg_info(node);
3153 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3154 ir_node *nomem = new_NoMem();
3157 /* ia32 stack grows in reverse direction, make a SubSP */
3158 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3159 set_ia32_am_support(new_op, ia32_am_Source);
3160 fold_immediate(new_op, 2, 3);
3162 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3168 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3170 static ir_node *gen_be_SubSP(ir_node *node) {
3171 ir_node *block = transform_node(get_nodes_block(node));
3172 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3173 ir_node *new_sz = transform_node(sz);
3174 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3175 ir_node *new_sp = transform_node(sp);
3176 ir_graph *irg = env.irg;
3177 dbg_info *dbgi = get_irn_dbg_info(node);
3178 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3179 ir_node *nomem = new_NoMem();
3182 /* ia32 stack grows in reverse direction, make an AddSP */
3183 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3184 set_ia32_am_support(new_op, ia32_am_Source);
3185 fold_immediate(new_op, 2, 3);
3187 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3193 * This function just sets the register for the Unknown node
3194 * as this is not done during register allocation because Unknown
3195 * is an "ignore" node.
3197 static ir_node *gen_Unknown(ir_node *node) {
3198 ir_mode *mode = get_irn_mode(node);
3200 if (mode_is_float(mode)) {
3201 if (USE_SSE2(env.cg))
3202 return ia32_new_Unknown_xmm(env.cg);
3204 return ia32_new_Unknown_vfp(env.cg);
3205 } else if (mode_needs_gp_reg(mode)) {
3206 return ia32_new_Unknown_gp(env.cg);
3208 assert(0 && "unsupported Unknown-Mode");
3215 * Change some phi modes
3217 static ir_node *gen_Phi(ir_node *node) {
3218 ir_node *block = transform_node(get_nodes_block(node));
3219 ir_graph *irg = env.irg;
3220 dbg_info *dbgi = get_irn_dbg_info(node);
3221 ir_mode *mode = get_irn_mode(node);
3225 if(mode_needs_gp_reg(mode)) {
3226 /* we shouldn't have any 64bit stuff around anymore */
3227 assert(get_mode_size_bits(mode) <= 32);
3228 /* all integer operations are on 32bit registers now */
3230 } else if(mode_is_float(mode)) {
3231 assert(mode == mode_D || mode == mode_F);
3232 if (USE_SSE2(env.cg)) {
3239 /* phi nodes allow loops, so we use the old arguments for now
3240 * and fix this later */
3241 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3242 copy_node_attr(node, phi);
3243 duplicate_deps(node, phi);
3245 set_new_node(node, phi);
3247 /* put the preds in the worklist */
3248 arity = get_irn_arity(node);
3249 for (i = 0; i < arity; ++i) {
3250 ir_node *pred = get_irn_n(node, i);
3251 pdeq_putr(env.worklist, pred);
3257 /**********************************************************************
3260 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3261 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3262 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3263 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3265 **********************************************************************/
3267 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3269 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3272 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3273 ir_node *val, ir_node *mem);
3276 * Transforms a lowered Load into a "real" one.
3278 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func, char fp_unit) {
3279 ir_node *block = transform_node(get_nodes_block(node));
3280 ir_node *ptr = get_irn_n(node, 0);
3281 ir_node *new_ptr = transform_node(ptr);
3282 ir_node *mem = get_irn_n(node, 1);
3283 ir_node *new_mem = transform_node(mem);
3284 ir_graph *irg = env.irg;
3285 dbg_info *dbgi = get_irn_dbg_info(node);
3286 ir_mode *mode = get_ia32_ls_mode(node);
3287 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3291 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3292 lowering we have x87 nodes, so we need to enforce simulation.
3294 if (mode_is_float(mode)) {
3296 if (fp_unit == fp_x87)
3300 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3302 set_ia32_am_support(new_op, ia32_am_Source);
3303 set_ia32_op_type(new_op, ia32_AddrModeS);
3304 set_ia32_am_flavour(new_op, ia32_am_OB);
3305 set_ia32_am_offs_int(new_op, 0);
3306 set_ia32_am_scale(new_op, 1);
3307 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3308 if (is_ia32_am_sc_sign(node))
3309 set_ia32_am_sc_sign(new_op);
3310 set_ia32_ls_mode(new_op, get_ia32_ls_mode(node));
3311 if (is_ia32_use_frame(node)) {
3312 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3313 set_ia32_use_frame(new_op);
3316 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3322 * Transforms a lowered Store into a "real" one.
3324 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func, char fp_unit) {
3325 ir_node *block = transform_node(get_nodes_block(node));
3326 ir_node *ptr = get_irn_n(node, 0);
3327 ir_node *new_ptr = transform_node(ptr);
3328 ir_node *val = get_irn_n(node, 1);
3329 ir_node *new_val = transform_node(val);
3330 ir_node *mem = get_irn_n(node, 2);
3331 ir_node *new_mem = transform_node(mem);
3332 ir_graph *irg = env.irg;
3333 dbg_info *dbgi = get_irn_dbg_info(node);
3334 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3335 ir_mode *mode = get_ia32_ls_mode(node);
3338 ia32_am_flavour_t am_flav = ia32_B;
3341 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
3342 lowering we have x87 nodes, so we need to enforce simulation.
3344 if (mode_is_float(mode)) {
3346 if (fp_unit == fp_x87)
3350 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3352 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3354 add_ia32_am_offs_int(new_op, am_offs);
3357 set_ia32_am_support(new_op, ia32_am_Dest);
3358 set_ia32_op_type(new_op, ia32_AddrModeD);
3359 set_ia32_am_flavour(new_op, am_flav);
3360 set_ia32_ls_mode(new_op, mode);
3361 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3362 set_ia32_use_frame(new_op);
3364 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3371 * Transforms an ia32_l_XXX into a "real" XXX node
3373 * @param env The transformation environment
3374 * @return the created ia32 XXX node
3376 #define GEN_LOWERED_OP(op) \
3377 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3378 ir_mode *mode = get_irn_mode(node); \
3379 if (mode_is_float(mode)) \
3381 return gen_binop(node, get_binop_left(node), \
3382 get_binop_right(node), new_rd_ia32_##op); \
3385 #define GEN_LOWERED_x87_OP(op) \
3386 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3388 FORCE_x87(env.cg); \
3389 new_op = gen_binop_float(node, get_binop_left(node), \
3390 get_binop_right(node), new_rd_ia32_##op); \
3394 #define GEN_LOWERED_UNOP(op) \
3395 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3396 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3399 #define GEN_LOWERED_SHIFT_OP(op) \
3400 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3401 return gen_shift_binop(node, get_binop_left(node), \
3402 get_binop_right(node), new_rd_ia32_##op); \
3405 #define GEN_LOWERED_LOAD(op, fp_unit) \
3406 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3407 return gen_lowered_Load(node, new_rd_ia32_##op, fp_unit); \
3410 #define GEN_LOWERED_STORE(op, fp_unit) \
3411 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3412 return gen_lowered_Store(node, new_rd_ia32_##op, fp_unit); \
3419 GEN_LOWERED_OP(IMul)
3421 GEN_LOWERED_x87_OP(vfprem)
3422 GEN_LOWERED_x87_OP(vfmul)
3423 GEN_LOWERED_x87_OP(vfsub)
3425 GEN_LOWERED_UNOP(Neg)
3427 GEN_LOWERED_LOAD(vfild, fp_x87)
3428 GEN_LOWERED_LOAD(Load, fp_none)
3429 /*GEN_LOWERED_STORE(vfist, fp_x87)
3432 GEN_LOWERED_STORE(Store, fp_none)
3434 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3435 ir_node *block = transform_node(get_nodes_block(node));
3436 ir_node *left = get_binop_left(node);
3437 ir_node *new_left = transform_node(left);
3438 ir_node *right = get_binop_right(node);
3439 ir_node *new_right = transform_node(right);
3440 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3441 ir_graph *irg = env.irg;
3442 dbg_info *dbgi = get_irn_dbg_info(node);
3445 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3446 clear_ia32_commutative(vfdiv);
3447 set_ia32_am_support(vfdiv, ia32_am_Source);
3448 fold_immediate(vfdiv, 2, 3);
3450 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env.cg, node));
3458 * Transforms a l_MulS into a "real" MulS node.
3460 * @param env The transformation environment
3461 * @return the created ia32 Mul node
3463 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3464 ir_node *block = transform_node(get_nodes_block(node));
3465 ir_node *left = get_binop_left(node);
3466 ir_node *new_left = transform_node(left);
3467 ir_node *right = get_binop_right(node);
3468 ir_node *new_right = transform_node(right);
3469 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3470 ir_graph *irg = env.irg;
3471 dbg_info *dbgi = get_irn_dbg_info(node);
3474 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3475 /* and then skip the result Proj, because all needed Projs are already there. */
3476 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
3477 clear_ia32_commutative(muls);
3478 set_ia32_am_support(muls, ia32_am_Source);
3479 fold_immediate(muls, 2, 3);
3481 /* check if EAX and EDX proj exist, add missing one */
3482 in[0] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EAX);
3483 in[1] = new_rd_Proj(dbgi, irg, block, muls, mode_Iu, pn_EDX);
3484 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
3486 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env.cg, node));
3491 GEN_LOWERED_SHIFT_OP(Shl)
3492 GEN_LOWERED_SHIFT_OP(Shr)
3493 GEN_LOWERED_SHIFT_OP(Sar)
3496 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3497 * op1 - target to be shifted
3498 * op2 - contains bits to be shifted into target
3500 * Only op3 can be an immediate.
3502 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3503 ir_node *op2, ir_node *count)
3505 ir_node *block = transform_node(get_nodes_block(node));
3506 ir_node *new_op1 = transform_node(op1);
3507 ir_node *new_op2 = transform_node(op2);
3508 ir_node *new_count = transform_node(count);
3509 ir_node *new_op = NULL;
3510 ir_graph *irg = env.irg;
3511 dbg_info *dbgi = get_irn_dbg_info(node);
3512 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
3513 ir_node *nomem = new_NoMem();
3517 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3519 /* Check if immediate optimization is on and */
3520 /* if it's an operation with immediate. */
3521 imm_op = (env.cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3523 /* Limit imm_op within range imm8 */
3525 tv = get_ia32_Immop_tarval(imm_op);
3528 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3529 set_ia32_Immop_tarval(imm_op, tv);
3536 /* integer operations */
3538 /* This is ShiftD with const */
3539 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3541 if (is_ia32_l_ShlD(node))
3542 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3543 new_op1, new_op2, noreg, nomem);
3545 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3546 new_op1, new_op2, noreg, nomem);
3547 copy_ia32_Immop_attr(new_op, imm_op);
3550 /* This is a normal ShiftD */
3551 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3552 if (is_ia32_l_ShlD(node))
3553 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3554 new_op1, new_op2, new_count, nomem);
3556 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3557 new_op1, new_op2, new_count, nomem);
3560 /* set AM support */
3561 // Matze: node has unsupported format (6inputs)
3562 //set_ia32_am_support(new_op, ia32_am_Dest);
3564 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env.cg, node));
3566 set_ia32_emit_cl(new_op);
3571 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3572 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3573 get_irn_n(node, 1), get_irn_n(node, 2));
3576 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3577 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3578 get_irn_n(node, 1), get_irn_n(node, 2));
3582 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3584 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3585 ir_node *block = transform_node(get_nodes_block(node));
3586 ir_node *val = get_irn_n(node, 1);
3587 ir_node *new_val = transform_node(val);
3588 ia32_code_gen_t *cg = env.cg;
3589 ir_node *res = NULL;
3590 ir_graph *irg = env.irg;
3592 ir_node *noreg, *new_ptr, *new_mem;
3599 mem = get_irn_n(node, 2);
3600 new_mem = transform_node(mem);
3601 ptr = get_irn_n(node, 0);
3602 new_ptr = transform_node(ptr);
3603 noreg = ia32_new_NoReg_gp(cg);
3604 dbgi = get_irn_dbg_info(node);
3606 /* Store x87 -> MEM */
3607 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3608 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3609 set_ia32_use_frame(res);
3610 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3611 set_ia32_am_support(res, ia32_am_Dest);
3612 set_ia32_am_flavour(res, ia32_B);
3613 set_ia32_op_type(res, ia32_AddrModeD);
3615 /* Load MEM -> SSE */
3616 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3617 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3618 set_ia32_use_frame(res);
3619 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3620 set_ia32_am_support(res, ia32_am_Source);
3621 set_ia32_am_flavour(res, ia32_B);
3622 set_ia32_op_type(res, ia32_AddrModeS);
3623 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3629 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3631 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3632 ir_node *block = transform_node(get_nodes_block(node));
3633 ir_node *val = get_irn_n(node, 1);
3634 ir_node *new_val = transform_node(val);
3635 ia32_code_gen_t *cg = env.cg;
3636 ir_graph *irg = env.irg;
3637 ir_node *res = NULL;
3638 ir_entity *fent = get_ia32_frame_ent(node);
3639 ir_mode *lsmode = get_ia32_ls_mode(node);
3641 ir_node *noreg, *new_ptr, *new_mem;
3645 if (! USE_SSE2(cg)) {
3646 /* SSE unit is not used -> skip this node. */
3650 ptr = get_irn_n(node, 0);
3651 new_ptr = transform_node(ptr);
3652 mem = get_irn_n(node, 2);
3653 new_mem = transform_node(mem);
3654 noreg = ia32_new_NoReg_gp(cg);
3655 dbgi = get_irn_dbg_info(node);
3657 /* Store SSE -> MEM */
3658 if (is_ia32_xLoad(skip_Proj(new_val))) {
3659 ir_node *ld = skip_Proj(new_val);
3661 /* we can vfld the value directly into the fpu */
3662 fent = get_ia32_frame_ent(ld);
3663 ptr = get_irn_n(ld, 0);
3664 offs = get_ia32_am_offs_int(ld);
3666 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3667 set_ia32_frame_ent(res, fent);
3668 set_ia32_use_frame(res);
3669 set_ia32_ls_mode(res, lsmode);
3670 set_ia32_am_support(res, ia32_am_Dest);
3671 set_ia32_am_flavour(res, ia32_B);
3672 set_ia32_op_type(res, ia32_AddrModeD);
3676 /* Load MEM -> x87 */
3677 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem);
3678 set_ia32_frame_ent(res, fent);
3679 set_ia32_use_frame(res);
3680 set_ia32_ls_mode(res, lsmode);
3681 add_ia32_am_offs_int(res, offs);
3682 set_ia32_am_support(res, ia32_am_Source);
3683 set_ia32_am_flavour(res, ia32_B);
3684 set_ia32_op_type(res, ia32_AddrModeS);
3685 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3690 /*********************************************************
3693 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3694 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3695 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3696 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3698 *********************************************************/
3701 * the BAD transformer.
3703 static ir_node *bad_transform(ir_node *node) {
3704 panic("No transform function for %+F available.\n", node);
3708 static ir_node *gen_End(ir_node *node) {
3709 /* end has to be duplicated manually because we need a dynamic in array */
3710 ir_graph *irg = env.irg;
3711 dbg_info *dbgi = get_irn_dbg_info(node);
3712 ir_node *block = transform_node(get_nodes_block(node));
3716 new_end = new_ir_node(dbgi, irg, block, op_End, mode_X, -1, NULL);
3717 copy_node_attr(node, new_end);
3718 duplicate_deps(node, new_end);
3720 set_irg_end(irg, new_end);
3721 set_new_node(new_end, new_end);
3723 /* transform preds */
3724 arity = get_irn_arity(node);
3725 for (i = 0; i < arity; ++i) {
3726 ir_node *in = get_irn_n(node, i);
3727 ir_node *new_in = transform_node(in);
3729 add_End_keepalive(new_end, new_in);
3735 static ir_node *gen_Block(ir_node *node) {
3736 ir_graph *irg = env.irg;
3737 dbg_info *dbgi = get_irn_dbg_info(node);
3738 ir_node *start_block = env.old_anchors[anchor_start_block];
3743 * We replace the ProjX from the start node with a jump,
3744 * so the startblock has no preds anymore now
3746 if (node == start_block) {
3747 return new_rd_Block(dbgi, irg, 0, NULL);
3750 /* we use the old blocks for now, because jumps allow cycles in the graph
3751 * we have to fix this later */
3752 block = new_ir_node(dbgi, irg, NULL, get_irn_op(node), get_irn_mode(node),
3753 get_irn_arity(node), get_irn_in(node) + 1);
3754 copy_node_attr(node, block);
3756 #ifdef DEBUG_libfirm
3757 block->node_nr = node->node_nr;
3759 set_new_node(node, block);
3761 /* put the preds in the worklist */
3762 arity = get_irn_arity(node);
3763 for (i = 0; i < arity; ++i) {
3764 ir_node *in = get_irn_n(node, i);
3765 pdeq_putr(env.worklist, in);
3771 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3772 ir_node *block = transform_node(get_nodes_block(node));
3773 ir_node *pred = get_Proj_pred(node);
3774 ir_node *new_pred = transform_node(pred);
3775 ir_graph *irg = env.irg;
3776 dbg_info *dbgi = get_irn_dbg_info(node);
3777 long proj = get_Proj_proj(node);
3779 if (proj == pn_be_AddSP_res) {
3780 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3781 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3783 } else if (proj == pn_be_AddSP_M) {
3784 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3788 return new_rd_Unknown(irg, get_irn_mode(node));
3791 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3792 ir_node *block = transform_node(get_nodes_block(node));
3793 ir_node *pred = get_Proj_pred(node);
3794 ir_node *new_pred = transform_node(pred);
3795 ir_graph *irg = env.irg;
3796 dbg_info *dbgi = get_irn_dbg_info(node);
3797 long proj = get_Proj_proj(node);
3799 if (proj == pn_be_SubSP_res) {
3800 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3801 arch_set_irn_register(env.cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3803 } else if (proj == pn_be_SubSP_M) {
3804 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3808 return new_rd_Unknown(irg, get_irn_mode(node));
3811 static ir_node *gen_Proj_Load(ir_node *node) {
3812 ir_node *block = transform_node(get_nodes_block(node));
3813 ir_node *pred = get_Proj_pred(node);
3814 ir_node *new_pred = transform_node(pred);
3815 ir_graph *irg = env.irg;
3816 dbg_info *dbgi = get_irn_dbg_info(node);
3817 long proj = get_Proj_proj(node);
3819 /* renumber the proj */
3820 if (is_ia32_Load(new_pred)) {
3821 if (proj == pn_Load_res) {
3822 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3823 } else if (proj == pn_Load_M) {
3824 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3826 } else if (is_ia32_xLoad(new_pred)) {
3827 if (proj == pn_Load_res) {
3828 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3829 } else if (proj == pn_Load_M) {
3830 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3832 } else if (is_ia32_vfld(new_pred)) {
3833 if (proj == pn_Load_res) {
3834 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3835 } else if (proj == pn_Load_M) {
3836 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3841 return new_rd_Unknown(irg, get_irn_mode(node));
3844 static ir_node *gen_Proj_DivMod(ir_node *node) {
3845 ir_node *block = transform_node(get_nodes_block(node));
3846 ir_node *pred = get_Proj_pred(node);
3847 ir_node *new_pred = transform_node(pred);
3848 ir_graph *irg = env.irg;
3849 dbg_info *dbgi = get_irn_dbg_info(node);
3850 ir_mode *mode = get_irn_mode(node);
3851 long proj = get_Proj_proj(node);
3853 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3855 switch (get_irn_opcode(pred)) {
3859 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3861 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3869 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3871 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3879 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3880 case pn_DivMod_res_div:
3881 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3882 case pn_DivMod_res_mod:
3883 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3893 return new_rd_Unknown(irg, mode);
3896 static ir_node *gen_Proj_CopyB(ir_node *node) {
3897 ir_node *block = transform_node(get_nodes_block(node));
3898 ir_node *pred = get_Proj_pred(node);
3899 ir_node *new_pred = transform_node(pred);
3900 ir_graph *irg = env.irg;
3901 dbg_info *dbgi = get_irn_dbg_info(node);
3902 ir_mode *mode = get_irn_mode(node);
3903 long proj = get_Proj_proj(node);
3906 case pn_CopyB_M_regular:
3907 if (is_ia32_CopyB_i(new_pred)) {
3908 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3909 } else if (is_ia32_CopyB(new_pred)) {
3910 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3918 return new_rd_Unknown(irg, mode);
3921 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3922 ir_node *block = transform_node(get_nodes_block(node));
3923 ir_node *pred = get_Proj_pred(node);
3924 ir_node *new_pred = transform_node(pred);
3925 ir_graph *irg = env.irg;
3926 dbg_info *dbgi = get_irn_dbg_info(node);
3927 ir_mode *mode = get_irn_mode(node);
3928 long proj = get_Proj_proj(node);
3931 case pn_ia32_l_vfdiv_M:
3932 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3933 case pn_ia32_l_vfdiv_res:
3934 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3939 return new_rd_Unknown(irg, mode);
3942 static ir_node *gen_Proj_Quot(ir_node *node) {
3943 ir_node *block = transform_node(get_nodes_block(node));
3944 ir_node *pred = get_Proj_pred(node);
3945 ir_node *new_pred = transform_node(pred);
3946 ir_graph *irg = env.irg;
3947 dbg_info *dbgi = get_irn_dbg_info(node);
3948 ir_mode *mode = get_irn_mode(node);
3949 long proj = get_Proj_proj(node);
3953 if (is_ia32_xDiv(new_pred)) {
3954 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3955 } else if (is_ia32_vfdiv(new_pred)) {
3956 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3960 if (is_ia32_xDiv(new_pred)) {
3961 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3962 } else if (is_ia32_vfdiv(new_pred)) {
3963 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3971 return new_rd_Unknown(irg, mode);
3974 static ir_node *gen_Proj_tls(ir_node *node) {
3975 ir_node *block = transform_node(get_nodes_block(node));
3976 ir_graph *irg = env.irg;
3977 dbg_info *dbgi = NULL;
3978 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3983 static ir_node *gen_Proj_be_Call(ir_node *node) {
3984 ir_node *block = transform_node(get_nodes_block(node));
3985 ir_node *call = get_Proj_pred(node);
3986 ir_node *new_call = transform_node(call);
3987 ir_graph *irg = env.irg;
3988 dbg_info *dbgi = get_irn_dbg_info(node);
3989 long proj = get_Proj_proj(node);
3990 ir_mode *mode = get_irn_mode(node);
3992 const arch_register_class_t *cls;
3994 /* The following is kinda tricky: If we're using SSE, then we have to
3995 * move the result value of the call in floating point registers to an
3996 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3997 * after the call, we have to make sure to correctly make the
3998 * MemProj and the result Proj use these 2 nodes
4000 if (proj == pn_be_Call_M_regular) {
4001 // get new node for result, are we doing the sse load/store hack?
4002 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4003 ir_node *call_res_new;
4004 ir_node *call_res_pred = NULL;
4006 if (call_res != NULL) {
4007 call_res_new = transform_node(call_res);
4008 call_res_pred = get_Proj_pred(call_res_new);
4011 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4012 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4014 assert(is_ia32_xLoad(call_res_pred));
4015 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
4018 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env.cg)) {
4020 ir_node *frame = get_irg_frame(irg);
4021 ir_node *noreg = ia32_new_NoReg_gp(env.cg);
4023 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4025 const arch_register_class_t *cls;
4027 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
4028 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
4030 /* store st(0) onto stack */
4031 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
4033 set_ia32_ls_mode(fstp, mode);
4034 set_ia32_op_type(fstp, ia32_AddrModeD);
4035 set_ia32_use_frame(fstp);
4036 set_ia32_am_flavour(fstp, ia32_am_B);
4037 set_ia32_am_support(fstp, ia32_am_Dest);
4039 /* load into SSE register */
4040 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
4041 set_ia32_ls_mode(sse_load, mode);
4042 set_ia32_op_type(sse_load, ia32_AddrModeS);
4043 set_ia32_use_frame(sse_load);
4044 set_ia32_am_flavour(sse_load, ia32_am_B);
4045 set_ia32_am_support(sse_load, ia32_am_Source);
4047 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
4049 /* now: create new Keep whith all former ins and one additional in - the result Proj */
4051 /* get a Proj representing a caller save register */
4052 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
4053 assert(is_Proj(p) && "Proj expected.");
4055 /* user of the the proj is the Keep */
4056 p = get_edge_src_irn(get_irn_out_edge_first(p));
4057 assert(be_is_Keep(p) && "Keep expected.");
4059 /* keep the result */
4060 cls = arch_get_irn_reg_class(env.cg->arch_env, sse_load, -1);
4061 keepin[0] = sse_load;
4062 be_new_Keep(cls, irg, block, 1, keepin);
4067 /* transform call modes */
4068 if (mode_is_data(mode)) {
4069 cls = arch_get_irn_reg_class(env.cg->arch_env, node, -1);
4073 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4076 static ir_node *gen_Proj(ir_node *node) {
4077 ir_graph *irg = env.irg;
4078 dbg_info *dbgi = get_irn_dbg_info(node);
4079 ir_node *pred = get_Proj_pred(node);
4080 long proj = get_Proj_proj(node);
4082 if (is_Store(pred) || be_is_FrameStore(pred)) {
4083 if (proj == pn_Store_M) {
4084 return transform_node(pred);
4087 return new_r_Bad(irg);
4089 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
4090 return gen_Proj_Load(node);
4091 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4092 return gen_Proj_DivMod(node);
4093 } else if (is_CopyB(pred)) {
4094 return gen_Proj_CopyB(node);
4095 } else if (is_Quot(pred)) {
4096 return gen_Proj_Quot(node);
4097 } else if (is_ia32_l_vfdiv(pred)) {
4098 return gen_Proj_l_vfdiv(node);
4099 } else if (be_is_SubSP(pred)) {
4100 return gen_Proj_be_SubSP(node);
4101 } else if (be_is_AddSP(pred)) {
4102 return gen_Proj_be_AddSP(node);
4103 } else if (be_is_Call(pred)) {
4104 return gen_Proj_be_Call(node);
4105 } else if (get_irn_op(pred) == op_Start) {
4106 if (proj == pn_Start_X_initial_exec) {
4107 ir_node *block = get_nodes_block(pred);
4110 /* we exchange the ProjX with a jump */
4111 block = transform_node(block);
4112 jump = new_rd_Jmp(dbgi, irg, block);
4113 ir_fprintf(stderr, "created jump: %+F\n", jump);
4116 if (node == env.old_anchors[anchor_tls]) {
4117 return gen_Proj_tls(node);
4120 ir_node *new_pred = transform_node(pred);
4121 ir_node *block = transform_node(get_nodes_block(node));
4122 ir_mode *mode = get_irn_mode(node);
4123 if (mode_needs_gp_reg(mode)) {
4124 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4125 get_Proj_proj(node));
4126 #ifdef DEBUG_libfirm
4127 new_proj->node_nr = node->node_nr;
4133 return duplicate_node(node);
4137 * Enters all transform functions into the generic pointer
4139 static void register_transformers(void) {
4140 ir_op *op_Max, *op_Min, *op_Mulh;
4142 /* first clear the generic function pointer for all ops */
4143 clear_irp_opcodes_generic_func();
4145 #define GEN(a) { transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4146 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4186 /* transform ops from intrinsic lowering */
4206 /* GEN(ia32_l_vfist); TODO */
4208 GEN(ia32_l_X87toSSE);
4209 GEN(ia32_l_SSEtoX87);
4214 /* we should never see these nodes */
4229 /* handle generic backend nodes */
4239 /* set the register for all Unknown nodes */
4242 op_Max = get_op_Max();
4245 op_Min = get_op_Min();
4248 op_Mulh = get_op_Mulh();
4256 static void duplicate_deps(ir_node *old_node, ir_node *new_node)
4259 int deps = get_irn_deps(old_node);
4261 for (i = 0; i < deps; ++i) {
4262 ir_node *dep = get_irn_dep(old_node, i);
4263 ir_node *new_dep = transform_node(dep);
4265 add_irn_dep(new_node, new_dep);
4269 static ir_node *duplicate_node(ir_node *node)
4271 ir_node *block = transform_node(get_nodes_block(node));
4272 ir_graph *irg = env.irg;
4273 dbg_info *dbgi = get_irn_dbg_info(node);
4274 ir_mode *mode = get_irn_mode(node);
4275 ir_op *op = get_irn_op(node);
4279 arity = get_irn_arity(node);
4280 if (op->opar == oparity_dynamic) {
4281 new_node = new_ir_node(dbgi, irg, block, op, mode, -1, NULL);
4282 for (i = 0; i < arity; ++i) {
4283 ir_node *in = get_irn_n(node, i);
4284 in = transform_node(in);
4285 add_irn_n(new_node, in);
4288 ir_node **ins = alloca(arity * sizeof(ins[0]));
4289 for (i = 0; i < arity; ++i) {
4290 ir_node *in = get_irn_n(node, i);
4291 ins[i] = transform_node(in);
4294 new_node = new_ir_node(dbgi, irg, block, op, mode, arity, ins);
4297 copy_node_attr(node, new_node);
4298 duplicate_deps(node, new_node);
4300 #ifdef DEBUG_libfirm
4301 new_node->node_nr = node->node_nr;
4308 * Calls transformation function for given node and marks it visited.
4310 static ir_node *transform_node(ir_node *node) {
4314 if (irn_visited(node)) {
4315 new_node = get_new_node(node);
4316 assert(new_node != NULL);
4320 mark_irn_visited(node);
4321 DEBUG_ONLY(set_new_node(node, NULL));
4323 op = get_irn_op(node);
4324 if (op->ops.generic) {
4325 transform_func *transform = (transform_func *)op->ops.generic;
4327 new_node = transform(node);
4328 assert(new_node != NULL);
4330 new_node = duplicate_node(node);
4332 DB((dbg, LEVEL_4, "%+F -> %+F\n", node, new_node));
4334 set_new_node(node, new_node);
4335 mark_irn_visited(new_node);
4336 hook_dead_node_elim_subst(current_ir_graph, node, new_node);
4341 * Rewire nodes which are potential loops (like Phis) to avoid endless loops.
4343 static void fix_loops(ir_node *node) {
4346 if (irn_visited(node))
4349 mark_irn_visited(node);
4351 assert(node_is_in_irgs_storage(env.irg, node));
4353 if (! is_Block(node)) {
4354 ir_node *block = get_nodes_block(node);
4355 ir_node *new_block = (ir_node *)get_irn_link(block);
4357 if (new_block != NULL) {
4358 set_nodes_block(node, new_block);
4365 arity = get_irn_arity(node);
4366 for (i = 0; i < arity; ++i) {
4367 ir_node *in = get_irn_n(node, i);
4368 ir_node *nw = (ir_node *)get_irn_link(in);
4370 if (nw != NULL && nw != in) {
4371 set_irn_n(node, i, nw);
4378 arity = get_irn_deps(node);
4379 for (i = 0; i < arity; ++i) {
4380 ir_node *in = get_irn_dep(node, i);
4381 ir_node *nw = (ir_node *)get_irn_link(in);
4383 if (nw != NULL && nw != in) {
4384 set_irn_dep(node, i, nw);
4392 static void pre_transform_node(ir_node **place)
4397 *place = transform_node(*place);
4401 * Transforms all nodes. Deletes the old obstack and creates a new one.
4403 static void transform_nodes(ia32_code_gen_t *cg) {
4405 ir_graph *irg = cg->irg;
4408 hook_dead_node_elim(irg, 1);
4410 inc_irg_visited(irg);
4414 env.visited = get_irg_visited(irg);
4415 env.worklist = new_pdeq();
4416 env.old_anchors = alloca(anchor_max * sizeof(env.old_anchors[0]));
4418 old_end = get_irg_end(irg);
4420 /* put all anchor nodes in the worklist */
4421 for (i = 0; i < anchor_max; ++i) {
4422 ir_node *anchor = irg->anchors[i];
4426 pdeq_putr(env.worklist, anchor);
4428 /* remember anchor */
4429 env.old_anchors[i] = anchor;
4430 /* and set it to NULL to make sure we don't accidently use it */
4431 irg->anchors[i] = NULL;
4434 /* pre transform some anchors (so they are available in the other transform
4436 set_irg_bad(irg, transform_node(env.old_anchors[anchor_bad]));
4437 set_irg_no_mem(irg, transform_node(env.old_anchors[anchor_no_mem]));
4438 set_irg_start_block(irg, transform_node(env.old_anchors[anchor_start_block]));
4439 set_irg_start(irg, transform_node(env.old_anchors[anchor_start]));
4440 set_irg_frame(irg, transform_node(env.old_anchors[anchor_frame]));
4442 pre_transform_node(&cg->unknown_gp);
4443 pre_transform_node(&cg->unknown_vfp);
4444 pre_transform_node(&cg->unknown_xmm);
4445 pre_transform_node(&cg->noreg_gp);
4446 pre_transform_node(&cg->noreg_vfp);
4447 pre_transform_node(&cg->noreg_xmm);
4449 /* process worklist (this should transform all nodes in the graph) */
4450 while (! pdeq_empty(env.worklist)) {
4451 ir_node *node = pdeq_getl(env.worklist);
4452 transform_node(node);
4455 /* fix loops and set new anchors*/
4456 inc_irg_visited(irg);
4457 for (i = 0; i < anchor_max; ++i) {
4458 ir_node *anchor = env.old_anchors[i];
4463 anchor = get_irn_link(anchor);
4465 assert(irg->anchors[i] == NULL || irg->anchors[i] == anchor);
4466 irg->anchors[i] = anchor;
4469 del_pdeq(env.worklist);
4471 hook_dead_node_elim(irg, 0);
4474 void ia32_transform_graph(ia32_code_gen_t *cg)
4476 ir_graph *irg = cg->irg;
4477 be_irg_t *birg = cg->birg;
4478 ir_graph *old_current_ir_graph = current_ir_graph;
4479 int old_interprocedural_view = get_interprocedural_view();
4480 struct obstack *old_obst = NULL;
4481 struct obstack *new_obst = NULL;
4483 current_ir_graph = irg;
4484 set_interprocedural_view(0);
4485 register_transformers();
4487 /* most analysis info is wrong after transformation */
4488 free_callee_info(irg);
4490 irg->outs_state = outs_none;
4492 free_loop_information(irg);
4493 set_irg_doms_inconsistent(irg);
4494 be_invalidate_liveness(birg);
4495 be_invalidate_dom_front(birg);
4497 /* create a new obstack */
4498 old_obst = irg->obst;
4499 new_obst = xmalloc(sizeof(*new_obst));
4500 obstack_init(new_obst);
4501 irg->obst = new_obst;
4502 irg->last_node_idx = 0;
4504 /* create new value table for CSE */
4505 del_identities(irg->value_table);
4506 irg->value_table = new_identities();
4508 /* do the main transformation */
4509 transform_nodes(cg);
4511 /* we don't want the globals anchor anymore */
4512 set_irg_globals(irg, new_r_Bad(irg));
4514 /* free the old obstack */
4515 obstack_free(old_obst, 0);
4519 current_ir_graph = old_current_ir_graph;
4520 set_interprocedural_view(old_interprocedural_view);
4522 /* recalculate edges */
4523 edges_deactivate(irg);
4524 edges_activate(irg);
4528 * Transforms a psi condition.
4530 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
4533 /* if the mode is target mode, we have already seen this part of the tree */
4534 if (get_irn_mode(cond) == mode)
4537 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
4539 set_irn_mode(cond, mode);
4541 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
4542 ir_node *in = get_irn_n(cond, i);
4544 /* if in is a compare: transform into Set/xCmp */
4546 ir_node *new_op = NULL;
4547 ir_node *cmp = get_Proj_pred(in);
4548 ir_node *cmp_a = get_Cmp_left(cmp);
4549 ir_node *cmp_b = get_Cmp_right(cmp);
4550 dbg_info *dbgi = get_irn_dbg_info(cmp);
4551 ir_graph *irg = get_irn_irg(cmp);
4552 ir_node *block = get_nodes_block(cmp);
4553 ir_node *noreg = ia32_new_NoReg_gp(cg);
4554 ir_node *nomem = new_rd_NoMem(irg);
4555 int pnc = get_Proj_proj(in);
4557 /* this is a compare */
4558 if (mode_is_float(mode)) {
4559 /* Psi is float, we need a floating point compare */
4562 ir_mode *m = get_irn_mode(cmp_a);
4564 if (! mode_is_float(m)) {
4565 cmp_a = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_a, cmp_a, mode);
4566 cmp_b = gen_sse_conv_int2float(cg, dbgi, irg, block, cmp_b, cmp_b, mode);
4567 } else if (m == mode_F) {
4568 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
4569 cmp_a = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_a, cmp_a);
4570 cmp_b = gen_sse_conv_f2d(cg, dbgi, irg, block, cmp_b, cmp_b);
4573 new_op = new_rd_ia32_xCmp(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4574 set_ia32_pncode(new_op, pnc);
4575 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
4582 construct_binop_func *set_func = NULL;
4584 if (mode_is_float(get_irn_mode(cmp_a))) {
4585 /* 1st case: compare operands are floats */
4590 set_func = new_rd_ia32_xCmpSet;
4593 set_func = new_rd_ia32_vfCmpSet;
4596 pnc &= 7; /* fp compare -> int compare */
4598 /* 2nd case: compare operand are integer too */
4599 set_func = new_rd_ia32_CmpSet;
4602 new_op = set_func(dbgi, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
4603 if (! mode_is_signed(mode))
4604 pnc |= ia32_pn_Cmp_Unsigned;
4606 set_ia32_pncode(new_op, pnc);
4607 set_ia32_am_support(new_op, ia32_am_Source);
4610 /* the the new compare as in */
4611 set_irn_n(cond, i, new_op);
4613 /* another complex condition */
4614 transform_psi_cond(in, mode, cg);
4620 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
4621 * We create a Set node, respectively a xCmp in case the Psi is a float, for
4622 * each compare, which causes the compare result to be stored in a register. The
4623 * "And"s and "Or"s are transformed later, we just have to set their mode right.
4625 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
4626 ia32_code_gen_t *cg = env;
4627 ir_node *psi_sel, *new_cmp, *block;
4632 if (get_irn_opcode(node) != iro_Psi)
4635 psi_sel = get_Psi_cond(node, 0);
4637 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
4638 if (is_Proj(psi_sel)) {
4639 assert(is_Cmp(get_Proj_pred(psi_sel)));
4643 //mode = get_irn_mode(node);
4644 // TODO probably wrong...
4647 transform_psi_cond(psi_sel, mode, cg);
4649 irg = get_irn_irg(node);
4650 block = get_nodes_block(node);
4652 /* we need to compare the evaluated condition tree with 0 */
4653 mode = get_irn_mode(node);
4654 if (mode_is_float(mode)) {
4655 /* BEWARE: new_r_Const_long works for floating point as well */
4656 ir_node *zero = new_r_Const_long(irg, block, mode, 0);
4658 psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
4659 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4660 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
4662 ir_node *zero = new_r_Const_long(irg, block, mode_Iu, 0);
4663 new_cmp = new_r_Cmp(irg, block, psi_sel, zero);
4664 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
4667 set_Psi_cond(node, 0, new_cmp);
4670 void ia32_init_transform(void)
4672 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");