2 * This file implements the IR transformation from firm into
16 #include "irgraph_t.h"
21 #include "iredges_t.h"
28 #include "../benode_t.h"
29 #include "../besched.h"
31 #include "bearch_ia32_t.h"
33 #include "ia32_nodes_attr.h"
34 #include "../arch/archop.h" /* we need this for Min and Max nodes */
35 #include "ia32_transform.h"
36 #include "ia32_new_nodes.h"
37 #include "ia32_map_regs.h"
39 #include "gen_ia32_regalloc_if.h"
41 #define SFP_SIGN "0x80000000"
42 #define DFP_SIGN "0x8000000000000000"
43 #define SFP_ABS "0x7FFFFFFF"
44 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
46 #define TP_SFP_SIGN "ia32_sfp_sign"
47 #define TP_DFP_SIGN "ia32_dfp_sign"
48 #define TP_SFP_ABS "ia32_sfp_abs"
49 #define TP_DFP_ABS "ia32_dfp_abs"
51 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
52 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
53 #define ENT_SFP_ABS "IA32_SFP_ABS"
54 #define ENT_DFP_ABS "IA32_DFP_ABS"
56 extern ir_op *get_op_Mulh(void);
58 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
59 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
61 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
62 ir_node *op, ir_node *mem, ir_mode *mode);
65 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
68 /****************************************************************************************************
70 * | | | | / _| | | (_)
71 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
72 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
73 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
74 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
76 ****************************************************************************************************/
79 * Gets the Proj with number pn from irn.
81 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
82 const ir_edge_t *edge;
84 assert(get_irn_mode(irn) == mode_T && "need mode_T");
86 foreach_out_edge(irn, edge) {
87 proj = get_edge_src_irn(edge);
89 if (get_Proj_proj(proj) == pn)
96 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
97 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
100 const char *ent_name;
101 const char *cnst_str;
102 } names [ia32_known_const_max] = {
103 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
104 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
105 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
106 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
108 static struct entity *ent_cache[ia32_known_const_max];
110 const char *tp_name, *ent_name, *cnst_str;
117 ent_name = names[kct].ent_name;
118 if (! ent_cache[kct]) {
119 tp_name = names[kct].tp_name;
120 cnst_str = names[kct].cnst_str;
122 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
123 tp = new_type_primitive(new_id_from_str(tp_name), mode);
124 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
126 set_entity_ld_ident(ent, get_entity_ident(ent));
127 set_entity_visibility(ent, visibility_local);
128 set_entity_variability(ent, variability_constant);
129 set_entity_allocation(ent, allocation_static);
131 /* we create a new entity here: It's initialization must resist on the
133 rem = current_ir_graph;
134 current_ir_graph = get_const_code_irg();
135 cnst = new_Const(mode, tv);
136 current_ir_graph = rem;
138 set_atomic_ent_value(ent, cnst);
140 /* cache the entry */
141 ent_cache[kct] = ent;
144 return get_entity_ident(ent_cache[kct]);
149 * Prints the old node name on cg obst and returns a pointer to it.
151 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
152 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
154 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
155 obstack_1grow(isa->name_obst, 0);
156 isa->name_obst_size += obstack_object_size(isa->name_obst);
157 return obstack_finish(isa->name_obst);
161 /* determine if one operator is an Imm */
162 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
164 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
165 else return is_ia32_Cnst(op2) ? op2 : NULL;
168 /* determine if one operator is not an Imm */
169 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
170 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
175 * Construct a standard binary operation, set AM and immediate if required.
177 * @param env The transformation environment
178 * @param op1 The first operand
179 * @param op2 The second operand
180 * @param func The node constructor function
181 * @return The constructed ia32 node.
183 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
184 ir_node *new_op = NULL;
185 ir_mode *mode = env->mode;
186 dbg_info *dbg = env->dbg;
187 ir_graph *irg = env->irg;
188 ir_node *block = env->block;
189 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
190 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
191 ir_node *nomem = new_NoMem();
192 ir_node *expr_op, *imm_op;
193 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
195 /* Check if immediate optimization is on and */
196 /* if it's an operation with immediate. */
197 if (! env->cg->opt.immops) {
201 else if (is_op_commutative(get_irn_op(env->irn))) {
202 imm_op = get_immediate_op(op1, op2);
203 expr_op = get_expr_op(op1, op2);
206 imm_op = get_immediate_op(NULL, op2);
207 expr_op = get_expr_op(op1, op2);
210 assert((expr_op || imm_op) && "invalid operands");
213 /* We have two consts here: not yet supported */
217 if (mode_is_float(mode)) {
218 /* floating point operations */
220 DB((mod, LEVEL_1, "FP with immediate ..."));
221 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
222 set_ia32_Immop_attr(new_op, imm_op);
223 set_ia32_am_support(new_op, ia32_am_None);
226 DB((mod, LEVEL_1, "FP binop ..."));
227 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
228 set_ia32_am_support(new_op, ia32_am_Source);
232 /* integer operations */
234 /* This is expr + const */
235 DB((mod, LEVEL_1, "INT with immediate ..."));
236 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
237 set_ia32_Immop_attr(new_op, imm_op);
240 set_ia32_am_support(new_op, ia32_am_Dest);
243 DB((mod, LEVEL_1, "INT binop ..."));
244 /* This is a normal operation */
245 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
248 set_ia32_am_support(new_op, ia32_am_Full);
252 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
254 set_ia32_res_mode(new_op, mode);
256 if (is_op_commutative(get_irn_op(env->irn))) {
257 set_ia32_commutative(new_op);
260 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
266 * Construct a shift/rotate binary operation, sets AM and immediate if required.
268 * @param env The transformation environment
269 * @param op1 The first operand
270 * @param op2 The second operand
271 * @param func The node constructor function
272 * @return The constructed ia32 node.
274 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
275 ir_node *new_op = NULL;
276 ir_mode *mode = env->mode;
277 dbg_info *dbg = env->dbg;
278 ir_graph *irg = env->irg;
279 ir_node *block = env->block;
280 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
281 ir_node *nomem = new_NoMem();
282 ir_node *expr_op, *imm_op;
284 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
286 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
288 /* Check if immediate optimization is on and */
289 /* if it's an operation with immediate. */
290 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
291 expr_op = get_expr_op(op1, op2);
293 assert((expr_op || imm_op) && "invalid operands");
296 /* We have two consts here: not yet supported */
300 /* Limit imm_op within range imm8 */
302 tv = get_ia32_Immop_tarval(imm_op);
305 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
312 /* integer operations */
314 /* This is shift/rot with const */
315 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
317 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
318 set_ia32_Immop_attr(new_op, imm_op);
321 /* This is a normal shift/rot */
322 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
323 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
327 set_ia32_am_support(new_op, ia32_am_Dest);
329 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
331 set_ia32_res_mode(new_op, mode);
332 set_ia32_emit_cl(new_op);
334 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
339 * Construct a standard unary operation, set AM and immediate if required.
341 * @param env The transformation environment
342 * @param op The operand
343 * @param func The node constructor function
344 * @return The constructed ia32 node.
346 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
347 ir_node *new_op = NULL;
348 ir_mode *mode = env->mode;
349 dbg_info *dbg = env->dbg;
350 ir_graph *irg = env->irg;
351 ir_node *block = env->block;
352 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
353 ir_node *nomem = new_NoMem();
354 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
356 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
358 if (mode_is_float(mode)) {
359 DB((mod, LEVEL_1, "FP unop ..."));
360 /* floating point operations don't support implicit store */
361 set_ia32_am_support(new_op, ia32_am_None);
364 DB((mod, LEVEL_1, "INT unop ..."));
365 set_ia32_am_support(new_op, ia32_am_Dest);
368 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
370 set_ia32_res_mode(new_op, mode);
372 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
378 * Creates an ia32 Add with immediate.
380 * @param env The transformation environment
381 * @param expr_op The expression operator
382 * @param const_op The constant
383 * @return the created ia32 Add node
385 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
386 ir_node *new_op = NULL;
387 tarval *tv = get_ia32_Immop_tarval(const_op);
388 dbg_info *dbg = env->dbg;
389 ir_graph *irg = env->irg;
390 ir_node *block = env->block;
391 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
392 ir_node *nomem = new_NoMem();
394 tarval_classification_t class_tv, class_negtv;
395 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
397 /* try to optimize to inc/dec */
398 if (env->cg->opt.incdec && tv) {
399 /* optimize tarvals */
400 class_tv = classify_tarval(tv);
401 class_negtv = classify_tarval(tarval_neg(tv));
403 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
404 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
405 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
408 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
409 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
410 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
416 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
417 set_ia32_Immop_attr(new_op, const_op);
424 * Creates an ia32 Add.
426 * @param dbg firm node dbg
427 * @param block the block the new node should belong to
428 * @param op1 first operator
429 * @param op2 second operator
430 * @param mode node mode
431 * @return the created ia32 Add node
433 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
434 ir_node *new_op = NULL;
435 dbg_info *dbg = env->dbg;
436 ir_mode *mode = env->mode;
437 ir_graph *irg = env->irg;
438 ir_node *block = env->block;
439 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
440 ir_node *nomem = new_NoMem();
441 ir_node *expr_op, *imm_op;
443 /* Check if immediate optimization is on and */
444 /* if it's an operation with immediate. */
445 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
446 expr_op = get_expr_op(op1, op2);
448 assert((expr_op || imm_op) && "invalid operands");
450 if (mode_is_float(mode)) {
452 if (USE_SSE2(env->cg))
453 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
455 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
460 /* No expr_op means, that we have two const - one symconst and */
461 /* one tarval or another symconst - because this case is not */
462 /* covered by constant folding */
463 /* We need to check for: */
464 /* 1) symconst + const -> becomes a LEA */
465 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
466 /* linker doesn't support two symconsts */
468 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
469 /* this is the 2nd case */
470 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
471 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
472 set_ia32_am_flavour(new_op, ia32_am_OB);
475 /* this is the 1st case */
476 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
478 if (get_ia32_op_type(op1) == ia32_SymConst) {
479 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
480 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
483 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
484 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
486 set_ia32_am_flavour(new_op, ia32_am_O);
490 set_ia32_am_support(new_op, ia32_am_Source);
491 set_ia32_op_type(new_op, ia32_AddrModeS);
493 /* Lea doesn't need a Proj */
497 /* This is expr + const */
498 new_op = gen_imm_Add(env, expr_op, imm_op);
501 set_ia32_am_support(new_op, ia32_am_Dest);
504 /* This is a normal add */
505 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
508 set_ia32_am_support(new_op, ia32_am_Full);
512 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
514 set_ia32_res_mode(new_op, mode);
516 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
522 * Creates an ia32 Mul.
524 * @param dbg firm node dbg
525 * @param block the block the new node should belong to
526 * @param op1 first operator
527 * @param op2 second operator
528 * @param mode node mode
529 * @return the created ia32 Mul node
531 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
534 if (mode_is_float(env->mode)) {
536 if (USE_SSE2(env->cg))
537 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
539 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
542 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
551 * Creates an ia32 Mulh.
552 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
553 * this result while Mul returns the lower 32 bit.
555 * @param env The transformation environment
556 * @param op1 The first operator
557 * @param op2 The second operator
558 * @return the created ia32 Mulh node
560 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
561 ir_node *proj_EAX, *proj_EDX, *mulh;
564 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
565 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
566 mulh = get_Proj_pred(proj_EAX);
567 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
569 /* to be on the save side */
570 set_Proj_proj(proj_EAX, pn_EAX);
572 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
573 /* Mulh with const cannot have AM */
574 set_ia32_am_support(mulh, ia32_am_None);
577 /* Mulh cannot have AM for destination */
578 set_ia32_am_support(mulh, ia32_am_Source);
584 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
592 * Creates an ia32 And.
594 * @param env The transformation environment
595 * @param op1 The first operator
596 * @param op2 The second operator
597 * @return The created ia32 And node
599 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
600 assert (! mode_is_float(env->mode));
601 return gen_binop(env, op1, op2, new_rd_ia32_And);
607 * Creates an ia32 Or.
609 * @param env The transformation environment
610 * @param op1 The first operator
611 * @param op2 The second operator
612 * @return The created ia32 Or node
614 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
615 assert (! mode_is_float(env->mode));
616 return gen_binop(env, op1, op2, new_rd_ia32_Or);
622 * Creates an ia32 Eor.
624 * @param env The transformation environment
625 * @param op1 The first operator
626 * @param op2 The second operator
627 * @return The created ia32 Eor node
629 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
630 assert(! mode_is_float(env->mode));
631 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
637 * Creates an ia32 Max.
639 * @param env The transformation environment
640 * @param op1 The first operator
641 * @param op2 The second operator
642 * @return the created ia32 Max node
644 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
647 if (mode_is_float(env->mode)) {
649 if (USE_SSE2(env->cg))
650 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
656 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
657 set_ia32_am_support(new_op, ia32_am_None);
658 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
667 * Creates an ia32 Min.
669 * @param env The transformation environment
670 * @param op1 The first operator
671 * @param op2 The second operator
672 * @return the created ia32 Min node
674 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
677 if (mode_is_float(env->mode)) {
679 if (USE_SSE2(env->cg))
680 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
686 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
687 set_ia32_am_support(new_op, ia32_am_None);
688 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
697 * Creates an ia32 Sub with immediate.
699 * @param env The transformation environment
700 * @param op1 The first operator
701 * @param op2 The second operator
702 * @return The created ia32 Sub node
704 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
705 ir_node *new_op = NULL;
706 tarval *tv = get_ia32_Immop_tarval(const_op);
707 dbg_info *dbg = env->dbg;
708 ir_graph *irg = env->irg;
709 ir_node *block = env->block;
710 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
711 ir_node *nomem = new_NoMem();
713 tarval_classification_t class_tv, class_negtv;
714 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
716 /* try to optimize to inc/dec */
717 if (env->cg->opt.incdec && tv) {
718 /* optimize tarvals */
719 class_tv = classify_tarval(tv);
720 class_negtv = classify_tarval(tarval_neg(tv));
722 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
723 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
724 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
727 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
728 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
729 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
735 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
736 set_ia32_Immop_attr(new_op, const_op);
743 * Creates an ia32 Sub.
745 * @param env The transformation environment
746 * @param op1 The first operator
747 * @param op2 The second operator
748 * @return The created ia32 Sub node
750 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
751 ir_node *new_op = NULL;
752 dbg_info *dbg = env->dbg;
753 ir_mode *mode = env->mode;
754 ir_graph *irg = env->irg;
755 ir_node *block = env->block;
756 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
757 ir_node *nomem = new_NoMem();
758 ir_node *expr_op, *imm_op;
760 /* Check if immediate optimization is on and */
761 /* if it's an operation with immediate. */
762 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
763 expr_op = get_expr_op(op1, op2);
765 assert((expr_op || imm_op) && "invalid operands");
767 if (mode_is_float(mode)) {
769 if (USE_SSE2(env->cg))
770 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
772 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
777 /* No expr_op means, that we have two const - one symconst and */
778 /* one tarval or another symconst - because this case is not */
779 /* covered by constant folding */
780 /* We need to check for: */
781 /* 1) symconst + const -> becomes a LEA */
782 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
783 /* linker doesn't support two symconsts */
785 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
786 /* this is the 2nd case */
787 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
788 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
789 set_ia32_am_sc_sign(new_op);
790 set_ia32_am_flavour(new_op, ia32_am_OB);
793 /* this is the 1st case */
794 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
796 if (get_ia32_op_type(op1) == ia32_SymConst) {
797 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
798 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
801 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
802 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
803 set_ia32_am_sc_sign(new_op);
805 set_ia32_am_flavour(new_op, ia32_am_O);
809 set_ia32_am_support(new_op, ia32_am_Source);
810 set_ia32_op_type(new_op, ia32_AddrModeS);
812 /* Lea doesn't need a Proj */
816 /* This is expr - const */
817 new_op = gen_imm_Sub(env, expr_op, imm_op);
820 set_ia32_am_support(new_op, ia32_am_Dest);
823 /* This is a normal sub */
824 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
827 set_ia32_am_support(new_op, ia32_am_Full);
831 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
833 set_ia32_res_mode(new_op, mode);
835 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
841 * Generates an ia32 DivMod with additional infrastructure for the
842 * register allocator if needed.
844 * @param env The transformation environment
845 * @param dividend -no comment- :)
846 * @param divisor -no comment- :)
847 * @param dm_flav flavour_Div/Mod/DivMod
848 * @return The created ia32 DivMod node
850 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
852 ir_node *edx_node, *cltd;
854 dbg_info *dbg = env->dbg;
855 ir_graph *irg = env->irg;
856 ir_node *block = env->block;
857 ir_mode *mode = env->mode;
858 ir_node *irn = env->irn;
863 mem = get_Div_mem(irn);
864 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
867 mem = get_Mod_mem(irn);
868 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
871 mem = get_DivMod_mem(irn);
872 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
878 if (mode_is_signed(mode)) {
879 /* in signed mode, we need to sign extend the dividend */
880 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
881 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
882 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
885 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
886 set_ia32_Const_type(edx_node, ia32_Const);
887 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
890 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
892 set_ia32_flavour(res, dm_flav);
893 set_ia32_n_res(res, 2);
895 /* Only one proj is used -> We must add a second proj and */
896 /* connect this one to a Keep node to eat up the second */
897 /* destroyed register. */
898 if (get_irn_n_edges(irn) == 1) {
899 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
900 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
902 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
903 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
906 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
909 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
912 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
914 set_ia32_res_mode(res, mode_Is);
921 * Wrapper for generate_DivMod. Sets flavour_Mod.
923 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
924 return generate_DivMod(env, op1, op2, flavour_Mod);
930 * Wrapper for generate_DivMod. Sets flavour_Div.
932 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
933 return generate_DivMod(env, op1, op2, flavour_Div);
939 * Wrapper for generate_DivMod. Sets flavour_DivMod.
941 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
942 return generate_DivMod(env, op1, op2, flavour_DivMod);
948 * Creates an ia32 floating Div.
950 * @param env The transformation environment
951 * @param op1 The first operator
952 * @param op2 The second operator
953 * @return The created ia32 fDiv node
955 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
956 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
958 ir_node *nomem = new_rd_NoMem(env->irg);
960 if (USE_SSE2(env->cg)) {
962 if (is_ia32_fConst(op2)) {
963 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
964 set_ia32_am_support(new_op, ia32_am_None);
965 set_ia32_Immop_attr(new_op, op2);
968 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
969 set_ia32_am_support(new_op, ia32_am_Source);
973 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
974 set_ia32_am_support(new_op, ia32_am_Source);
976 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
977 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
985 * Creates an ia32 Shl.
987 * @param env The transformation environment
988 * @param op1 The first operator
989 * @param op2 The second operator
990 * @return The created ia32 Shl node
992 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
993 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
999 * Creates an ia32 Shr.
1001 * @param env The transformation environment
1002 * @param op1 The first operator
1003 * @param op2 The second operator
1004 * @return The created ia32 Shr node
1006 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1007 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
1013 * Creates an ia32 Shrs.
1015 * @param env The transformation environment
1016 * @param op1 The first operator
1017 * @param op2 The second operator
1018 * @return The created ia32 Shrs node
1020 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1021 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
1027 * Creates an ia32 RotL.
1029 * @param env The transformation environment
1030 * @param op1 The first operator
1031 * @param op2 The second operator
1032 * @return The created ia32 RotL node
1034 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1035 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1041 * Creates an ia32 RotR.
1042 * NOTE: There is no RotR with immediate because this would always be a RotL
1043 * "imm-mode_size_bits" which can be pre-calculated.
1045 * @param env The transformation environment
1046 * @param op1 The first operator
1047 * @param op2 The second operator
1048 * @return The created ia32 RotR node
1050 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1051 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1057 * Creates an ia32 RotR or RotL (depending on the found pattern).
1059 * @param env The transformation environment
1060 * @param op1 The first operator
1061 * @param op2 The second operator
1062 * @return The created ia32 RotL or RotR node
1064 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1065 ir_node *rotate = NULL;
1067 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1068 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1069 that means we can create a RotR instead of an Add and a RotL */
1072 ir_node *pred = get_Proj_pred(op2);
1074 if (is_ia32_Add(pred)) {
1075 ir_node *pred_pred = get_irn_n(pred, 2);
1076 tarval *tv = get_ia32_Immop_tarval(pred);
1077 long bits = get_mode_size_bits(env->mode);
1079 if (is_Proj(pred_pred)) {
1080 pred_pred = get_Proj_pred(pred_pred);
1083 if (is_ia32_Minus(pred_pred) &&
1084 tarval_is_long(tv) &&
1085 get_tarval_long(tv) == bits)
1087 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1088 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1095 rotate = gen_RotL(env, op1, op2);
1104 * Transforms a Minus node.
1106 * @param env The transformation environment
1107 * @param op The operator
1108 * @return The created ia32 Minus node
1110 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1113 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1114 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1115 ir_node *nomem = new_rd_NoMem(env->irg);
1118 if (mode_is_float(env->mode)) {
1120 if (USE_SSE2(env->cg)) {
1121 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1123 size = get_mode_size_bits(env->mode);
1124 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1126 set_ia32_sc(new_op, name);
1128 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1130 set_ia32_res_mode(new_op, env->mode);
1131 set_ia32_immop_type(new_op, ia32_ImmSymConst);
1133 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1136 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1137 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1141 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1150 * Transforms a Not node.
1152 * @param env The transformation environment
1153 * @param op The operator
1154 * @return The created ia32 Not node
1156 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1157 assert (! mode_is_float(env->mode));
1158 return gen_unop(env, op, new_rd_ia32_Not);
1164 * Transforms an Abs node.
1166 * @param env The transformation environment
1167 * @param op The operator
1168 * @return The created ia32 Abs node
1170 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1171 ir_node *res, *p_eax, *p_edx;
1172 dbg_info *dbg = env->dbg;
1173 ir_mode *mode = env->mode;
1174 ir_graph *irg = env->irg;
1175 ir_node *block = env->block;
1176 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1177 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1178 ir_node *nomem = new_NoMem();
1182 if (mode_is_float(mode)) {
1184 if (USE_SSE2(env->cg)) {
1185 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1187 size = get_mode_size_bits(mode);
1188 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1190 set_ia32_sc(res, name);
1192 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1194 set_ia32_res_mode(res, mode);
1195 set_ia32_immop_type(res, ia32_ImmSymConst);
1197 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1200 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1201 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1205 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1206 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1207 set_ia32_res_mode(res, mode);
1209 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1210 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1212 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1213 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1214 set_ia32_res_mode(res, mode);
1216 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1218 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1219 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1220 set_ia32_res_mode(res, mode);
1222 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1231 * Transforms a Load.
1233 * @param mod the debug module
1234 * @param block the block the new node should belong to
1235 * @param node the ir Load node
1236 * @param mode node mode
1237 * @return the created ia32 Load node
1239 static ir_node *gen_Load(ia32_transform_env_t *env) {
1240 ir_node *node = env->irn;
1241 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1242 ir_node *ptr = get_Load_ptr(node);
1243 ir_node *lptr = ptr;
1244 ir_mode *mode = get_Load_mode(node);
1247 ia32_am_flavour_t am_flav = ia32_B;
1249 /* address might be a constant (symconst or absolute address) */
1250 if (is_ia32_Const(ptr)) {
1255 if (mode_is_float(mode)) {
1257 if (USE_SSE2(env->cg))
1258 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1260 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1263 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
1266 /* base is an constant address */
1268 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1269 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1272 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1278 set_ia32_am_support(new_op, ia32_am_Source);
1279 set_ia32_op_type(new_op, ia32_AddrModeS);
1280 set_ia32_am_flavour(new_op, am_flav);
1281 set_ia32_ls_mode(new_op, mode);
1283 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1291 * Transforms a Store.
1293 * @param mod the debug module
1294 * @param block the block the new node should belong to
1295 * @param node the ir Store node
1296 * @param mode node mode
1297 * @return the created ia32 Store node
1299 static ir_node *gen_Store(ia32_transform_env_t *env) {
1300 ir_node *node = env->irn;
1301 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1302 ir_node *val = get_Store_value(node);
1303 ir_node *ptr = get_Store_ptr(node);
1304 ir_node *sptr = ptr;
1305 ir_node *mem = get_Store_mem(node);
1306 ir_mode *mode = get_irn_mode(val);
1307 ir_node *sval = val;
1310 ia32_am_flavour_t am_flav = ia32_B;
1311 ia32_immop_type_t immop = ia32_ImmNone;
1313 if (! mode_is_float(mode)) {
1314 /* in case of storing a const (but not a symconst) -> make it an attribute */
1315 if (is_ia32_Cnst(val)) {
1316 switch (get_ia32_op_type(val)) {
1318 immop = ia32_ImmConst;
1321 immop = ia32_ImmSymConst;
1324 assert(0 && "unsupported Const type");
1330 /* address might be a constant (symconst or absolute address) */
1331 if (is_ia32_Const(ptr)) {
1336 if (mode_is_float(mode)) {
1338 if (USE_SSE2(env->cg))
1339 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1341 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1343 else if (get_mode_size_bits(mode) == 8) {
1344 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
1347 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
1350 /* stored const is an attribute (saves a register) */
1351 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1352 set_ia32_Immop_attr(new_op, val);
1355 /* base is an constant address */
1357 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1358 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1361 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1367 set_ia32_am_support(new_op, ia32_am_Dest);
1368 set_ia32_op_type(new_op, ia32_AddrModeD);
1369 set_ia32_am_flavour(new_op, am_flav);
1370 set_ia32_ls_mode(new_op, get_irn_mode(val));
1371 set_ia32_immop_type(new_op, immop);
1373 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1381 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1383 * @param env The transformation environment
1384 * @return The transformed node.
1386 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1387 dbg_info *dbg = env->dbg;
1388 ir_graph *irg = env->irg;
1389 ir_node *block = env->block;
1390 ir_node *node = env->irn;
1391 ir_node *sel = get_Cond_selector(node);
1392 ir_mode *sel_mode = get_irn_mode(sel);
1393 ir_node *res = NULL;
1394 ir_node *pred = NULL;
1395 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1396 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1398 if (is_Proj(sel) && sel_mode == mode_b) {
1399 ir_node *nomem = new_NoMem();
1401 pred = get_Proj_pred(sel);
1403 /* get both compare operators */
1404 cmp_a = get_Cmp_left(pred);
1405 cmp_b = get_Cmp_right(pred);
1407 /* check if we can use a CondJmp with immediate */
1408 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1409 expr = get_expr_op(cmp_a, cmp_b);
1412 pn_Cmp pnc = get_Proj_proj(sel);
1414 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1415 if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
1416 /* a Cmp A =/!= 0 */
1417 ir_node *op1 = expr;
1418 ir_node *op2 = expr;
1419 ir_node *and = skip_Proj(expr);
1420 const char *cnst = NULL;
1422 /* check, if expr is an only once used And operation */
1423 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1424 op1 = get_irn_n(and, 2);
1425 op2 = get_irn_n(and, 3);
1427 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1429 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
1430 set_ia32_pncode(res, get_Proj_proj(sel));
1431 set_ia32_res_mode(res, get_irn_mode(op1));
1434 copy_ia32_Immop_attr(res, and);
1437 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1442 if (mode_is_float(get_irn_mode(expr))) {
1444 if (USE_SSE2(env->cg))
1445 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1451 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1453 set_ia32_Immop_attr(res, cnst);
1454 set_ia32_res_mode(res, get_irn_mode(expr));
1457 if (mode_is_float(get_irn_mode(cmp_a))) {
1459 if (USE_SSE2(env->cg))
1460 res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1466 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1468 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1471 set_ia32_pncode(res, get_Proj_proj(sel));
1472 set_ia32_am_support(res, ia32_am_Source);
1475 /* determine the smallest switch case value */
1476 int switch_min = INT_MAX;
1477 const ir_edge_t *edge;
1480 foreach_out_edge(node, edge) {
1481 int pn = get_Proj_proj(get_edge_src_irn(edge));
1482 switch_min = pn < switch_min ? pn : switch_min;
1486 /* if smallest switch case is not 0 we need an additional sub */
1487 snprintf(buf, sizeof(buf), "%d", switch_min);
1488 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1489 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1490 sub_ia32_am_offs(res, buf);
1491 set_ia32_am_flavour(res, ia32_am_OB);
1492 set_ia32_am_support(res, ia32_am_Source);
1493 set_ia32_op_type(res, ia32_AddrModeS);
1496 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1497 set_ia32_pncode(res, get_Cond_defaultProj(node));
1498 set_ia32_res_mode(res, get_irn_mode(sel));
1501 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1508 * Transforms a CopyB node.
1510 * @param env The transformation environment
1511 * @return The transformed node.
1513 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1514 ir_node *res = NULL;
1515 dbg_info *dbg = env->dbg;
1516 ir_graph *irg = env->irg;
1517 ir_mode *mode = env->mode;
1518 ir_node *block = env->block;
1519 ir_node *node = env->irn;
1520 ir_node *src = get_CopyB_src(node);
1521 ir_node *dst = get_CopyB_dst(node);
1522 ir_node *mem = get_CopyB_mem(node);
1523 int size = get_type_size_bytes(get_CopyB_type(node));
1526 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1527 /* then we need the size explicitly in ECX. */
1528 if (size >= 16 * 4) {
1529 rem = size & 0x3; /* size % 4 */
1532 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1533 set_ia32_op_type(res, ia32_Const);
1534 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1536 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1537 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1540 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1541 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1542 set_ia32_immop_type(res, ia32_ImmConst);
1545 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1553 * Transforms a Mux node into CMov.
1555 * @param env The transformation environment
1556 * @return The transformed node.
1558 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1559 ir_node *node = env->irn;
1560 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1561 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1563 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1570 * Following conversion rules apply:
1574 * 1) n bit -> m bit n > m (downscale)
1575 * a) target is signed: movsx
1576 * b) target is unsigned: and with lower bits sets
1577 * 2) n bit -> m bit n == m (sign change)
1579 * 3) n bit -> m bit n < m (upscale)
1580 * a) source is signed: movsx
1581 * b) source is unsigned: and with lower bits sets
1585 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1589 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1590 * if target mode < 32bit: additional INT -> INT conversion (see above)
1594 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1595 * x87 is mode_E internally, conversions happen only at load and store
1596 * in non-strict semantic
1599 //static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
1600 // ir_mode *src_mode, ir_mode *tgt_mode)
1602 // int n = get_mode_size_bits(src_mode);
1603 // int m = get_mode_size_bits(tgt_mode);
1604 // dbg_info *dbg = env->dbg;
1605 // ir_graph *irg = env->irg;
1606 // ir_node *block = env->block;
1607 // ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1608 // ir_node *nomem = new_rd_NoMem(irg);
1609 // ir_node *new_op, *proj;
1610 // assert(n > m && "downscale expected");
1611 // if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
1612 // /* ASHL Sn, n - m */
1613 // new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1614 // proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
1615 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1616 // set_ia32_am_support(new_op, ia32_am_Source);
1617 // SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1618 // /* ASHR Sn, n - m */
1619 // new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
1620 // set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
1623 // new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
1624 // set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
1630 * Transforms a Conv node.
1632 * @param env The transformation environment
1633 * @param op The operator
1634 * @return The created ia32 Conv node
1636 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
1637 dbg_info *dbg = env->dbg;
1638 ir_graph *irg = env->irg;
1639 ir_mode *src_mode = get_irn_mode(op);
1640 ir_mode *tgt_mode = env->mode;
1641 int src_bits = get_mode_size_bits(src_mode);
1642 int tgt_bits = get_mode_size_bits(tgt_mode);
1643 ir_node *block = env->block;
1644 ir_node *new_op = NULL;
1645 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1646 ir_node *nomem = new_rd_NoMem(irg);
1648 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1650 if (src_mode == tgt_mode) {
1651 /* this can happen when changing mode_P to mode_Is */
1652 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
1653 edges_reroute(env->irn, op, irg);
1655 else if (mode_is_float(src_mode)) {
1656 /* we convert from float ... */
1657 if (mode_is_float(tgt_mode)) {
1659 if (USE_SSE2(env->cg)) {
1660 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
1661 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1664 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
1665 edges_reroute(env->irn, op, irg);
1670 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
1671 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1672 /* if target mode is not int: add an additional downscale convert */
1673 if (tgt_bits < 32) {
1674 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1675 set_ia32_am_support(new_op, ia32_am_Source);
1676 set_ia32_tgt_mode(new_op, tgt_mode);
1677 set_ia32_src_mode(new_op, src_mode);
1679 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
1681 if (tgt_bits == 8 || src_bits == 8) {
1682 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1685 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
1691 /* we convert from int ... */
1692 if (mode_is_float(tgt_mode)) {
1694 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
1695 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1699 if (get_mode_size_bits(src_mode) == tgt_bits) {
1700 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
1701 edges_reroute(env->irn, op, irg);
1704 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
1705 if (tgt_bits == 8 || src_bits == 8) {
1706 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1709 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
1716 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1717 set_ia32_tgt_mode(new_op, tgt_mode);
1718 set_ia32_src_mode(new_op, src_mode);
1720 set_ia32_am_support(new_op, ia32_am_Source);
1722 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
1730 /********************************************
1733 * | |__ ___ _ __ ___ __| | ___ ___
1734 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1735 * | |_) | __/ | | | (_) | (_| | __/\__ \
1736 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1738 ********************************************/
1740 static ir_node *gen_StackParam(ia32_transform_env_t *env) {
1741 ir_node *new_op = NULL;
1742 ir_node *node = env->irn;
1743 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1744 ir_node *mem = new_rd_NoMem(env->irg);
1745 ir_node *ptr = get_irn_n(node, 0);
1746 entity *ent = be_get_frame_entity(node);
1747 ir_mode *mode = env->mode;
1749 // /* If the StackParam has only one user -> */
1750 // /* put it in the Block where the user resides */
1751 // if (get_irn_n_edges(node) == 1) {
1752 // env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
1755 if (mode_is_float(mode)) {
1757 if (USE_SSE2(env->cg))
1758 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1760 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1763 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1766 set_ia32_frame_ent(new_op, ent);
1767 set_ia32_use_frame(new_op);
1769 set_ia32_am_support(new_op, ia32_am_Source);
1770 set_ia32_op_type(new_op, ia32_AddrModeS);
1771 set_ia32_am_flavour(new_op, ia32_B);
1772 set_ia32_ls_mode(new_op, mode);
1774 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1776 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
1780 * Transforms a FrameAddr into an ia32 Add.
1782 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1783 ir_node *new_op = NULL;
1784 ir_node *node = env->irn;
1785 ir_node *op = get_irn_n(node, 0);
1786 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1787 ir_node *nomem = new_rd_NoMem(env->irg);
1789 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1790 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1791 set_ia32_am_support(new_op, ia32_am_Full);
1792 set_ia32_use_frame(new_op);
1793 set_ia32_immop_type(new_op, ia32_ImmConst);
1795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1797 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1801 * Transforms a FrameLoad into an ia32 Load.
1803 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1804 ir_node *new_op = NULL;
1805 ir_node *node = env->irn;
1806 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1807 ir_node *mem = get_irn_n(node, 0);
1808 ir_node *ptr = get_irn_n(node, 1);
1809 entity *ent = be_get_frame_entity(node);
1810 ir_mode *mode = get_type_mode(get_entity_type(ent));
1812 if (mode_is_float(mode)) {
1814 if (USE_SSE2(env->cg))
1815 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1817 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1820 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
1822 set_ia32_frame_ent(new_op, ent);
1823 set_ia32_use_frame(new_op);
1825 set_ia32_am_support(new_op, ia32_am_Source);
1826 set_ia32_op_type(new_op, ia32_AddrModeS);
1827 set_ia32_am_flavour(new_op, ia32_B);
1828 set_ia32_ls_mode(new_op, mode);
1830 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1837 * Transforms a FrameStore into an ia32 Store.
1839 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1840 ir_node *new_op = NULL;
1841 ir_node *node = env->irn;
1842 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1843 ir_node *mem = get_irn_n(node, 0);
1844 ir_node *ptr = get_irn_n(node, 1);
1845 ir_node *val = get_irn_n(node, 2);
1846 entity *ent = be_get_frame_entity(node);
1847 ir_mode *mode = get_irn_mode(val);
1849 if (mode_is_float(mode)) {
1851 if (USE_SSE2(env->cg))
1852 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1854 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1856 else if (get_mode_size_bits(mode) == 8) {
1857 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1860 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
1863 set_ia32_frame_ent(new_op, ent);
1864 set_ia32_use_frame(new_op);
1866 set_ia32_am_support(new_op, ia32_am_Dest);
1867 set_ia32_op_type(new_op, ia32_AddrModeD);
1868 set_ia32_am_flavour(new_op, ia32_B);
1869 set_ia32_ls_mode(new_op, mode);
1871 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1878 /*********************************************************
1881 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1882 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1883 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1884 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1886 *********************************************************/
1889 * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
1890 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1892 void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
1893 ia32_transform_env_t tenv;
1894 ir_node *in1, *in2, *noreg, *nomem, *res;
1895 const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
1897 /* Return if AM node or not a Sub or fSub */
1898 if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
1901 noreg = ia32_new_NoReg_gp(cg);
1902 nomem = new_rd_NoMem(cg->irg);
1903 in1 = get_irn_n(irn, 2);
1904 in2 = get_irn_n(irn, 3);
1905 in1_reg = arch_get_irn_register(cg->arch_env, in1);
1906 in2_reg = arch_get_irn_register(cg->arch_env, in2);
1907 out_reg = get_ia32_out_reg(irn, 0);
1909 tenv.block = get_nodes_block(irn);
1910 tenv.dbg = get_irn_dbg_info(irn);
1913 DEBUG_ONLY(tenv.mod = cg->mod;)
1914 tenv.mode = get_ia32_res_mode(irn);
1917 /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
1918 if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
1919 /* generate the neg src2 */
1920 res = gen_Minus(&tenv, in2);
1921 arch_set_irn_register(cg->arch_env, res, in2_reg);
1923 /* add to schedule */
1924 sched_add_before(irn, res);
1926 /* generate the add */
1927 if (mode_is_float(tenv.mode)) {
1928 res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1929 set_ia32_am_support(res, ia32_am_Source);
1932 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
1933 set_ia32_am_support(res, ia32_am_Full);
1936 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
1938 slots = get_ia32_slots(res);
1941 /* add to schedule */
1942 sched_add_before(irn, res);
1944 /* remove the old sub */
1947 /* exchange the add and the sub */
1953 * Transforms a LEA into an Add if possible
1954 * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
1956 void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
1957 ia32_am_flavour_t am_flav;
1959 ir_node *res = NULL;
1960 ir_node *nomem, *noreg, *base, *index, *op1, *op2;
1962 ia32_transform_env_t tenv;
1963 const arch_register_t *out_reg, *base_reg, *index_reg;
1966 if (! is_ia32_Lea(irn))
1969 am_flav = get_ia32_am_flavour(irn);
1971 /* only some LEAs can be transformed to an Add */
1972 if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
1975 noreg = ia32_new_NoReg_gp(cg);
1976 nomem = new_rd_NoMem(cg->irg);
1979 base = get_irn_n(irn, 0);
1980 index = get_irn_n(irn,1);
1982 offs = get_ia32_am_offs(irn);
1984 /* offset has a explicit sign -> we need to skip + */
1985 if (offs && offs[0] == '+')
1988 out_reg = arch_get_irn_register(cg->arch_env, irn);
1989 base_reg = arch_get_irn_register(cg->arch_env, base);
1990 index_reg = arch_get_irn_register(cg->arch_env, index);
1992 tenv.block = get_nodes_block(irn);
1993 tenv.dbg = get_irn_dbg_info(irn);
1996 DEBUG_ONLY(tenv.mod = cg->mod;)
1997 tenv.mode = get_irn_mode(irn);
2000 switch(get_ia32_am_flavour(irn)) {
2002 /* out register must be same as base register */
2003 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2009 /* out register must be same as base register */
2010 if (! REGS_ARE_EQUAL(out_reg, base_reg))
2017 /* out register must be same as index register */
2018 if (! REGS_ARE_EQUAL(out_reg, index_reg))
2025 /* out register must be same as one in register */
2026 if (REGS_ARE_EQUAL(out_reg, base_reg)) {
2030 else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
2035 /* in registers a different from out -> no Add possible */
2042 res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
2043 arch_set_irn_register(cg->arch_env, res, out_reg);
2044 set_ia32_op_type(res, ia32_Normal);
2047 set_ia32_cnst(res, offs);
2048 set_ia32_immop_type(res, ia32_ImmConst);
2051 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
2053 /* add Add to schedule */
2054 sched_add_before(irn, res);
2056 res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
2058 /* add result Proj to schedule */
2059 sched_add_before(irn, res);
2061 /* remove the old LEA */
2064 /* exchange the Add and the LEA */
2069 * Transforms the given firm node (and maybe some other related nodes)
2070 * into one or more assembler nodes.
2072 * @param node the firm node
2073 * @param env the debug module
2075 void ia32_transform_node(ir_node *node, void *env) {
2076 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
2078 ir_node *asm_node = NULL;
2079 ia32_transform_env_t tenv;
2084 tenv.block = get_nodes_block(node);
2085 tenv.dbg = get_irn_dbg_info(node);
2086 tenv.irg = current_ir_graph;
2088 DEBUG_ONLY(tenv.mod = cgenv->mod;)
2089 tenv.mode = get_irn_mode(node);
2092 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
2093 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
2094 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
2095 #define IGN(a) case iro_##a: break
2096 #define BAD(a) case iro_##a: goto bad
2097 #define OTHER_BIN(a) \
2098 if (get_irn_op(node) == get_op_##a()) { \
2099 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
2103 if (be_is_##a(node)) { \
2104 asm_node = gen_##a(&tenv); \
2108 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
2110 code = get_irn_opcode(node);
2156 /* constant transformation happens earlier */
2186 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
2190 /* exchange nodes if a new one was generated */
2192 exchange(node, asm_node);
2193 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
2196 DB((tenv.mod, LEVEL_1, "ignored\n"));