16 #include "../benode_t.h"
17 #include "bearch_ia32_t.h"
19 #include "ia32_nodes_attr.h"
20 #include "../arch/archop.h" /* we need this for Min and Max nodes */
21 #include "ia32_transform.h"
22 #include "ia32_new_nodes.h"
23 #include "ia32_map_regs.h"
25 #include "gen_ia32_regalloc_if.h"
27 extern ir_op *get_op_Mulh(void);
31 /****************************************************************************************************
33 * | | | | / _| | | (_)
34 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
35 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
36 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
37 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
39 ****************************************************************************************************/
43 /* determine if one operator is an Imm */
44 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
46 return is_ia32_Const(op1) ? op1 : (is_ia32_Const(op2) ? op2 : NULL);
47 else return is_ia32_Const(op2) ? op2 : NULL;
50 /* determine if one operator is not an Imm */
51 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
52 return !is_ia32_Const(op1) ? op1 : (!is_ia32_Const(op2) ? op2 : NULL);
58 * Creates an ia32 Add with immediate.
61 * @param block the block the new node should belong to
62 * @param expr_op operator
63 * @param mode node mode
64 * @return the created ia23 Add_i node
66 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
68 tarval *tv = get_ia32_Immop_tarval(const_op);
70 tarval_classification_t class_tv, class_negtv;
71 firm_dbg_module_t *mod = env->mod;
72 dbg_info *dbg = env->dbg;
73 ir_mode *mode = env->mode;
74 ir_graph *irg = env->irg;
75 ir_node *block = env->block;
77 /* const_op: tarval or SymConst? */
79 /* optimize tarvals */
80 class_tv = classify_tarval(tv);
81 class_negtv = classify_tarval(tarval_neg(tv));
83 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
84 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
85 new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
87 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
88 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
89 new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
98 new_op = new_rd_ia32_Lea_i(dbg, irg, block, expr_op, mode);
104 * Creates an ia32 Add.
106 * @param dbg firm node dbg
107 * @param block the block the new node should belong to
108 * @param op1 first operator
109 * @param op2 second operator
110 * @param mode node mode
111 * @return the created ia32 Add node
113 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
118 dbg_info *dbg = env->dbg;
119 ir_mode *mode = env->mode;
120 ir_graph *irg = env->irg;
121 ir_node *block = env->block;
123 if (mode_is_float(mode)) {
124 return new_rd_ia32_fAdd(dbg, irg, block, op1, op2, mode);
127 /* try to optimize with LEA */
129 shli_op = is_ia32_Shl_i(op1) ? op1 : (is_ia32_Shl_i(op2) ? op2 : NULL);
130 expr_op = shli_op == op1 ? op2 : (shli_op == op2 ? op1 : NULL);
133 tarval *tv = get_ia32_Immop_tarval(shli_op);
136 switch (get_tarval_long(tv)) {
140 // If the other operand of the LEA is an LEA_i (that means LEA ofs(%regop1)),
141 // we can skip it and transform the whole sequence into LEA ofs(%regop1, %regop2, shl_val),
142 if (is_ia32_Lea_i(expr_op)) {
143 offs = get_ia32_Immop_tarval(expr_op);
144 expr_op = get_irn_n(expr_op, 0);
147 new_op = new_rd_ia32_Lea(dbg, irg, block, expr_op, get_irn_n(shli_op, 0), mode);
148 set_ia32_Immop_tarval(new_op, tv);
149 set_ia32_am_offs(new_op, offs);
164 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, op2, mode);
165 set_ia32_Immop_tarval(new_op, get_tarval_null(mode_Iu));
166 set_ia32_am_offs(new_op, NULL);
175 * Generates an ia32 Mul node.
177 * @param env The transformation environment
178 * @param op1 The first faktor
179 * @param op2 The second factor
180 * @param mul_flav flavour_Mul/Mulh
181 * @return The ready-to-go Mul node
183 ir_node *generate_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, op_flavour_t mul_flav, int is_imm_op) {
184 ir_node *in_keep[1], *res;
185 long pn_good, pn_bad;
186 dbg_info *dbg = env->dbg;
187 ir_graph *irg = env->irg;
188 ir_node *block = env->block;
189 ir_mode *mode = env->mode;
194 mul = new_rd_ia32_Mul_i(dbg, irg, block, op1, mode_T);
195 set_ia32_Immop_attr(mul, op2);
198 mul = new_rd_ia32_Mul(dbg, irg, block, op1, op2, mode_T);
200 set_ia32_flavour(mul, mul_flav);
202 /* create the mul infrastructure */
203 if (mul_flav == flavour_Mul) {
212 res = new_rd_Proj(dbg, irg, block, mul, mode, pn_good);
213 in_keep[0] = new_rd_Proj(dbg, irg, block, mul, mode, pn_bad);
215 be_new_Keep(&ia32_reg_classes[CLASS_ia32_general_purpose], irg, block, 1, in_keep);
223 * Creates an ia32 Mul with immediate.
225 * @param dbg firm dbg
226 * @param block the block the new node should belong to
227 * @param expr_op operator
228 * @param mode node mode
229 * @return the created ia23 Mul_i node
231 static ir_node *gen_imm_Mul(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
232 /* Mul with immediate only possible with int, so we don't need to check for float */
233 return generate_Mul(env, expr_op, const_op, flavour_Mul, 1);
237 * Creates an ia32 Mul.
239 * @param dbg firm node dbg
240 * @param block the block the new node should belong to
241 * @param op1 first operator
242 * @param op2 second operator
243 * @param mode node mode
244 * @return the created ia32 Mul node
246 ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
247 if (mode_is_float(env->mode)) {
248 return new_rd_ia32_fMul(env->dbg, env->irg, env->block, op1, op2, env->mode);
251 return generate_Mul(env, op1, op2, flavour_Mul, 0);
258 * Creates an ia32 Mulh with immediate.
259 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
260 * this result while Mul returns the lower 32 bit.
262 * @param dbg firm dbg
263 * @param block the block the new node should belong to
264 * @param expr_op operator
265 * @param mode node mode
266 * @return the created ia23 Mulh_i node
268 static ir_node *gen_imm_Mulh(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
269 return generate_Mul(env, expr_op, const_op, flavour_Mulh, 1);
273 * Creates an ia32 Mulh.
274 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
275 * this result while Mul returns the lower 32 bit.
277 * @param dbg firm node dbg
278 * @param block the block the new node should belong to
279 * @param op1 first operator
280 * @param op2 second operator
281 * @param mode node mode
282 * @return the created ia32 Mulh node
284 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
285 return generate_Mul(env, op1, op2, flavour_Mulh, 0);
291 * Creates an ia32 And with immediate.
293 * @param dbg firm dbg
294 * @param block the block the new node should belong to
295 * @param expr_op operator
296 * @param mode node mode
297 * @return the created ia23 And_i node
299 static ir_node *gen_imm_And(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
300 return new_rd_ia32_And_i(env->dbg, env->irg, env->block, expr_op, env->mode);
304 * Creates an ia32 And.
306 * @param dbg firm node dbg
307 * @param block the block the new node should belong to
308 * @param op1 first operator
309 * @param op2 second operator
310 * @param mode node mode
311 * @return the created ia32 And node
313 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
314 return new_rd_ia32_And(env->dbg, env->irg, env->block, op1, op2, env->mode);
320 * Creates an ia32 Or with immediate.
322 * @param dbg firm dbg
323 * @param block the block the new node should belong to
324 * @param expr_op operator
325 * @param mode node mode
326 * @return the created ia23 Or_i node
328 static ir_node *gen_imm_Or(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
329 return new_rd_ia32_Or_i(env->dbg, env->irg, env->block, expr_op, env->mode);
333 * Creates an ia32 Or.
335 * @param dbg firm node dbg
336 * @param block the block the new node should belong to
337 * @param op1 first operator
338 * @param op2 second operator
339 * @param mode node mode
340 * @return the created ia32 Or node
342 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
343 return new_rd_ia32_Or(env->dbg, env->irg, env->block, op1, op2, env->mode);
349 * Creates an ia32 Eor with immediate.
351 * @param dbg firm dbg
352 * @param block the block the new node should belong to
353 * @param expr_op operator
354 * @param mode node mode
355 * @return the created ia23 Eor_i node
357 static ir_node *gen_imm_Eor(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
358 return new_rd_ia32_Eor_i(env->dbg, env->irg, env->block, expr_op, env->mode);
362 * Creates an ia32 Eor.
364 * @param dbg firm node dbg
365 * @param block the block the new node should belong to
366 * @param op1 first operator
367 * @param op2 second operator
368 * @param mode node mode
369 * @return the created ia32 Eor node
371 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
372 return new_rd_ia32_Eor(env->dbg, env->irg, env->block, op1, op2, env->mode);
378 * Creates an ia32 Max.
380 * @param dbg firm dbg
381 * @param block the block the new node should belong to
382 * @param expr_op operator
383 * @param mode node mode
384 * @return the created ia23 Max node
386 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
387 return new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
393 * Creates an ia32 Min.
395 * @param dbg firm dbg
396 * @param block the block the new node should belong to
397 * @param expr_op operator
398 * @param mode node mode
399 * @return the created ia23 Min node
401 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
402 return new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
408 * Creates an ia32 Sub with immediate.
410 * @param dbg firm dbg
411 * @param block the block the new node should belong to
412 * @param expr_op operator
413 * @param mode node mode
414 * @return the created ia23 Sub_i node
416 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
418 tarval *tv = get_ia32_Immop_tarval(const_op);
420 tarval_classification_t class_tv, class_negtv;
421 firm_dbg_module_t *mod = env->mod;
422 dbg_info *dbg = env->dbg;
423 ir_mode *mode = env->mode;
424 ir_graph *irg = env->irg;
425 ir_node *block = env->block;
427 /* const_op: tarval or SymConst? */
429 /* optimize tarvals */
430 class_tv = classify_tarval(tv);
431 class_negtv = classify_tarval(tarval_neg(tv));
433 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
434 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
435 new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
437 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
438 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
439 new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
448 new_op = new_rd_ia32_Sub_i(dbg, irg, block, expr_op, mode);
454 * Creates an ia32 Sub.
456 * @param dbg firm node dbg
457 * @param block the block the new node should belong to
458 * @param op1 first operator
459 * @param op2 second operator
460 * @param mode node mode
461 * @return the created ia32 Sub node
463 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
464 if (mode_is_float(env->mode)) {
465 return new_rd_ia32_fSub(env->dbg, env->irg, env->block, op1, op2, env->mode);
467 return new_rd_ia32_Sub(env->dbg, env->irg, env->block, op1, op2, env->mode);
473 * Generates an ia32 DivMod with additional infrastructure for the
474 * register allocator if needed.
476 * @param env The transformation environment
477 * @param dividend -no comment- :)
478 * @param divisor -no comment- :)
479 * @param dm_flav flavour_Div/Mod/DivMod
480 * @return The created ia32 DivMod node
482 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, op_flavour_t dm_flav) {
484 ir_node *edx_node, *cltd;
486 dbg_info *dbg = env->dbg;
487 ir_graph *irg = env->irg;
488 ir_node *block = env->block;
489 ir_mode *mode = env->mode;
490 ir_node *irn = env->irn;
491 ir_node *mem = get_DivMod_mem(irn);
493 if (mode_is_signed(mode)) {
494 /* in signed mode, we need to sign extend the dividend */
495 cltd = new_rd_ia32_Cltd(dbg, irg, block, dividend, mode_T);
496 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
497 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
500 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
501 set_ia32_Const_type(edx_node, asmop_Const);
502 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
505 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode);
507 set_ia32_flavour(res, dm_flav);
508 set_ia32_n_res(res, 2);
510 /* Only one proj is used -> We must add a second proj and */
511 /* connect this one to a Keep node to eat up the second */
512 /* destroyed register. */
513 if (get_irn_n_edges(irn) == 1) {
514 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
515 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
517 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
518 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
521 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
524 be_new_Keep(&ia32_reg_classes[CLASS_ia32_general_purpose], irg, block, 1, in_keep);
532 * Wrapper for generate_DivMod. Sets flavour_Mod.
534 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
535 return generate_DivMod(env, op1, op2, flavour_Mod);
541 * Wrapper for generate_DivMod. Sets flavour_Div.
543 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
544 return generate_DivMod(env, op1, op2, flavour_Div);
550 * Wrapper for generate_DivMod. Sets flavour_DivMod.
552 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
553 return generate_DivMod(env, op1, op2, flavour_DivMod);
559 * Creates an ia32 floating Div.
561 * @param dbg firm node dbg
562 * @param block the block the new node should belong to
563 * @param op1 first operator
564 * @param op2 second operator
565 * @param mode node mode
566 * @return the created ia32 fDiv node
568 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
569 return new_rd_ia32_fDiv(env->dbg, env->irg, env->block, op1, op2, env->mode);
575 * Creates an ia32 Shl with immediate.
577 * @param dbg firm dbg
578 * @param block the block the new node should belong to
579 * @param expr_op operator
580 * @param mode node mode
581 * @return the created ia23 Shl_i node
583 static ir_node *gen_imm_Shl(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
584 return new_rd_ia32_Shl_i(env->dbg, env->irg, env->block, expr_op, env->mode);
588 * Creates an ia32 Shl.
590 * @param dbg firm node dbg
591 * @param block the block the new node should belong to
592 * @param op1 first operator
593 * @param op2 second operator
594 * @param mode node mode
595 * @return the created ia32 Shl node
597 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
598 return new_rd_ia32_Shl(env->dbg, env->irg, env->block, op1, op2, env->mode);
604 * Creates an ia32 Shr with immediate.
606 * @param dbg firm dbg
607 * @param block the block the new node should belong to
608 * @param expr_op operator
609 * @param mode node mode
610 * @return the created ia23 Shr_i node
612 static ir_node *gen_imm_Shr(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
613 return new_rd_ia32_Shr_i(env->dbg, env->irg, env->block, expr_op, env->mode);
617 * Creates an ia32 Shr.
619 * @param dbg firm node dbg
620 * @param block the block the new node should belong to
621 * @param op1 first operator
622 * @param op2 second operator
623 * @param mode node mode
624 * @return the created ia32 Shr node
626 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
627 return new_rd_ia32_Shr(env->dbg, env->irg, env->block, op1, op2, env->mode);
633 * Creates an ia32 Shrs with immediate.
635 * @param dbg firm dbg
636 * @param block the block the new node should belong to
637 * @param expr_op operator
638 * @param mode node mode
639 * @return the created ia23 Shrs_i node
641 static ir_node *gen_imm_Shrs(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
642 return new_rd_ia32_Shrs_i(env->dbg, env->irg, env->block, expr_op, env->mode);
646 * Creates an ia32 Shrs.
648 * @param dbg firm node dbg
649 * @param block the block the new node should belong to
650 * @param op1 first operator
651 * @param op2 second operator
652 * @param mode node mode
653 * @return the created ia32 Shrs node
655 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
656 return new_rd_ia32_Shrs(env->dbg, env->irg, env->block, op1, op2, env->mode);
662 * Creates an ia32 RotL.
664 * @param dbg firm node dbg
665 * @param block the block the new node should belong to
666 * @param op1 first operator
667 * @param op2 second operator
668 * @param mode node mode
669 * @return the created ia32 RotL node
671 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
672 return new_rd_ia32_RotL(env->dbg, env->irg, env->block, op1, op2, env->mode);
678 * Creates an ia32 RotR.
679 * NOTE: There is no RotR with immediate because this would always be a RotL
680 * "imm-mode_size_bits" which can be pre-calculated.
682 * @param dbg firm node dbg
683 * @param block the block the new node should belong to
684 * @param op1 first operator
685 * @param op2 second operator
686 * @param mode node mode
687 * @return the created ia32 RotR node
689 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
690 return new_rd_ia32_RotR(env->dbg, env->irg, env->block, op1, op2, env->mode);
696 * Transforms a Rot with immediate into an ia32 RotL with immediate
697 * as the Firm Rot is a RotL (see NOTE on RotR with immediate above).
699 * @param dbg firm node dbg
700 * @param block the block the new node should belong to
701 * @param op1 first operator
702 * @param op2 second operator
703 * @param mode node mode
704 * @return the created ia32 RotL node
706 static ir_node *gen_imm_Rot(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
707 return new_rd_ia32_RotL_i(env->dbg, env->irg, env->block, expr_op, env->mode);
711 * Creates an ia32 RotR or RotL (depending on the found pattern).
713 * @param dbg firm node dbg
714 * @param block the block the new node should belong to
715 * @param op1 first operator
716 * @param op2 second operator
717 * @param mode node mode
718 * @return the created ia32 RotL or RotR node
720 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
721 ir_node *rotate = NULL;
723 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
724 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
725 that means we can create a RotR instead of an Add and a RotL */
727 if (is_ia32_Add_i(op2)) {
728 ir_node *minus = get_irn_n(op2, 0); // is there an op_Minus?
730 if (is_ia32_Minus(minus)) {
731 tarval *tv = get_ia32_Immop_tarval(op2);
732 long bits = get_mode_size_bits(env->mode);
734 if (tarval_is_long(tv) && get_tarval_long(tv) == bits) {
735 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
736 rotate = gen_RotR(env, op1, get_irn_n(minus, 0));
742 rotate = gen_RotL(env, op1, op2);
750 * Transforms commutative operations (op_Add, op_And, op_Or, op_Eor)
751 * and non-commutative operations with com == 0 (op_Sub, op_Shl, op_Shr, op_Shrs, op_Rot)
753 * @param mod the debug module
754 * @param block the block node belongs to
755 * @param node the node to transform
756 * @param op1 first operator
757 * @param op2 second operator
758 * @param mode node mode
759 * @param com flag if op is commutative
760 * @return the created assembler node
762 static ir_node *gen_arith_Op(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, int com) {
763 firm_dbg_module_t *mod = env->mod;
764 ir_node *node = env->irn;
765 ir_node *imm_op = NULL;
766 ir_node *expr_op = NULL;
767 ir_node *asm_node = NULL;
768 opcode opc = get_irn_opcode(node);
769 ir_op *op = get_irn_op(node);
773 #undef GENOPI_SETATTR
774 #define GENOP(a) case iro_##a: asm_node = gen_##a(env, op1, op2); break
775 #define GENOPI(a) case iro_##a: asm_node = gen_imm_##a(env, expr_op, imm_op); break
776 #define GENOPI_SETATTR(a) case iro_##a: asm_node = gen_imm_##a(env, expr_op, imm_op); set_ia32_Immop_attr(asm_node, imm_op); break
779 imm_op = get_immediate_op(op1, op2);
781 imm_op = get_immediate_op(NULL, op2);
783 expr_op = get_expr_op(op1, op2);
785 /* TODO: Op(Const, Const) support */
786 if (is_ia32_Const(op1) && is_ia32_Const(op2)) {
787 DB((mod, LEVEL_2, "%+F(Const, Const) -> binop ... ", get_irn_opname(node)));
791 /* There are arithmetic operations which can't take an immediate */
796 DB((mod, LEVEL_2, "Div/Mod/DivMod imm -> binop ... "));
800 if (op == get_op_Min() || op == get_op_Max()) {
801 DB((mod, LEVEL_2, "MIN/MAX imm -> binop ... "));
807 DB((mod, LEVEL_1, "(%+F -- %+F) ... ", op1, op2));
809 if (!mode_is_float(env->mode) && imm_op) {
810 DB((mod, LEVEL_1, "immop ... "));
822 GENOPI_SETATTR(Shrs);
825 if (op == get_op_Mulh()) {
826 asm_node = gen_imm_Mulh(env, expr_op, imm_op);
829 assert("binop_i: THIS SHOULD NOT HAPPEN");
834 DB((mod, LEVEL_1, "binop ... "));
855 if (op == get_op_Max()) {
856 asm_node = gen_Max(env, op1, op2);
858 else if (op == get_op_Min()) {
859 asm_node = gen_Min(env, op1, op2);
861 else if (op == get_op_Mulh()) {
862 asm_node = gen_Mulh(env, op1, op2);
865 assert("binop: THIS SHOULD NOT HAPPEN");
874 #undef GENOPI_SETATTR
879 * Transforms a Minus node.
881 * @param mod the debug module
882 * @param block the block the new node should belong to
883 * @param node the ir Minus node
885 * @param mode node mode
886 * @return the created ia32 Minus node
888 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
889 if (is_ia32_Minus(op) || is_ia32_fMinus(op)) {
890 DB((env->mod, LEVEL_1, "--(e) to e ..."));
891 return get_irn_n(op, 0);
894 if (mode_is_float(env->mode)) {
895 return new_rd_ia32_fMinus(env->dbg, env->irg, env->block, op, env->mode);
897 return new_rd_ia32_Minus(env->dbg, env->irg, env->block, op, env->mode);
904 * Transforms a Conv node.
906 * @param mod the debug module
907 * @param block the block the new node should belong to
908 * @param node the ir Conv node
910 * @param mode node mode
911 * @return the created ia32 Conv node
913 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
914 return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode);
920 * Transforms a Not node.
922 * @param mod the debug module
923 * @param block the block the new node should belong to
924 * @param node the ir Not node
926 * @param mode node mode
927 * @return the created ia32 Not node
929 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
930 return new_rd_ia32_Not(env->dbg, env->irg, env->block, op, env->mode);
936 * Transforms an Abs node.
938 * @param mod the debug module
939 * @param block the block the new node should belong to
940 * @param node the ir Abs node
942 * @param mode node mode
943 * @return the created ia32 Abs node
945 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
946 ir_node *res, *p_eax, *p_edx;
947 dbg_info *dbg = env->dbg;
948 ir_mode *mode = env->mode;
949 ir_graph *irg = env->irg;
950 ir_node *block = env->block;
952 res = new_rd_ia32_Cltd(dbg, irg, block, op, mode_T);
953 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
954 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
955 res = new_rd_ia32_Eor(dbg, irg, block, p_eax, p_edx, mode);
956 res = new_rd_ia32_Sub(dbg, irg, block, res, p_edx, mode);
966 * @param mod the debug module
967 * @param block the block the new node should belong to
968 * @param node the ir Load node
969 * @param mode node mode
970 * @return the created ia32 Load node
972 static ir_node *gen_Load(ia32_transform_env_t *env) {
973 ir_node *node = env->irn;
975 if (mode_is_float(env->mode)) {
976 return new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
978 return new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), get_Load_mem(node), env->mode);
984 * Transforms a Store.
986 * @param mod the debug module
987 * @param block the block the new node should belong to
988 * @param node the ir Store node
989 * @param mode node mode
990 * @return the created ia32 Store node
992 ir_node *gen_Store(ia32_transform_env_t *env) {
993 ir_node *node = env->irn;
995 if (mode_is_float(env->mode)) {
996 return new_rd_ia32_fStore(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
998 return new_rd_ia32_Store(env->dbg, env->irg, env->block, get_Store_ptr(node), get_Store_value(node), get_Store_mem(node), env->mode);
1004 * Transforms a Call and its arguments corresponding to the calling convention.
1006 * @param mod the debug module
1007 * @param block the block the new node should belong to
1008 * @param node the ir Call node
1009 * @param dummy mode doesn't matter
1010 * @return the created ia32 Call node
1012 static ir_node *gen_Call(ia32_transform_env_t *env) {
1013 const ia32_register_req_t **in_req;
1015 ir_node *new_call, *sync;
1016 int i, j, n_new_call_in, ignore = 0;
1018 dbg_info *dbg = env->dbg;
1019 ir_graph *irg = env->irg;
1020 ir_node *block = env->block;
1021 ir_node *call = env->irn;
1022 ir_node **stack_param = NULL;
1023 ir_node **param = get_Call_param_arr(call);
1024 ir_node *call_Mem = get_Call_mem(call);
1025 unsigned cc = get_method_calling_convention(get_Call_type(call));
1026 int n = get_Call_n_params(call);
1030 if (cc & cc_reg_param)
1031 biggest_n = ia32_get_n_regparam_class(n, param, &ignore, &ignore);
1033 /* remember: biggest_n = x means we can pass (x + 1) parameters in register */
1035 /* do we need to pass arguments on stack? */
1036 if (biggest_n + 1 < n)
1037 stack_param = xcalloc(n - biggest_n - 1, sizeof(ir_node *));
1039 /* we need at least one in, either for the stack params or the call_Mem */
1040 n_new_call_in = biggest_n + 2;
1042 /* the call has one IN for all stack parameter and one IN for each reg param */
1043 in = xcalloc(n_new_call_in, sizeof(ir_node *));
1044 in_req = xcalloc(n_new_call_in, sizeof(arch_register_req_t *));
1046 /* loop over all parameters and set the register requirements */
1047 for (i = 0; i <= biggest_n && (cc & cc_reg_param); i++) {
1048 in_req[i] = ia32_get_RegParam_req(n, param, i, cc);
1052 /* create remaining stack parameters */
1053 if (cc & cc_last_on_top) {
1054 for (i = stack_idx; i < n; i++) {
1055 /* pass it on stack */
1056 if (mode_is_float(get_irn_mode(param[i]))) {
1057 stack_param[i - stack_idx] = new_rd_ia32_fStackArg(get_irn_dbg_info(param[i]), irg,
1058 block, call_Mem, param[i], mode_M);
1061 stack_param[i - stack_idx] = new_rd_ia32_StackArg(get_irn_dbg_info(param[i]), irg,
1062 block, call_Mem, param[i], mode_M);
1067 for (i = n - 1, j = 0; i >= stack_idx; i--, j++) {
1068 /* pass it on stack */
1069 if (mode_is_float(get_irn_mode(param[i]))) {
1070 stack_param[j] = new_rd_ia32_fStackArg(get_irn_dbg_info(param[i]), irg,
1071 block, call_Mem, param[i], mode_M);
1074 stack_param[j] = new_rd_ia32_StackArg(get_irn_dbg_info(param[i]), irg,
1075 block, call_Mem, param[i], mode_M);
1081 sync = new_r_Sync(irg, block, n - biggest_n - 1, stack_param);
1082 in[n_new_call_in - 1] = sync;
1085 in[n_new_call_in - 1] = call_Mem;
1088 /* create the new node */
1089 new_call = new_rd_ia32_Call(dbg, irg, block, n_new_call_in, in);
1090 set_ia32_Immop_attr(new_call, get_Call_ptr(call));
1091 set_ia32_n_res(new_call, 1);
1093 /* set register requirements for in and out */
1094 attr = get_ia32_attr(new_call);
1095 attr->in_req = in_req;
1096 attr->out_req = xcalloc(2, sizeof(ia32_register_req_t *));
1097 attr->out_req[0] = &ia32_default_req_ia32_general_purpose_eax;
1098 attr->out_req[1] = &ia32_default_req_ia32_general_purpose_edx;
1099 attr->slots = xcalloc(2, sizeof(arch_register_t *));
1101 /* stack parameter has no OUT register */
1102 attr->in_req[n_new_call_in - 1] = &ia32_default_req_none;
1110 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1112 * @param mod the debug module
1113 * @param block the block the new node should belong to
1114 * @param node the ir Cond node
1115 * @param mode mode of the Cond
1116 * @return The transformed node.
1118 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1119 dbg_info *dbg = env->dbg;
1120 ir_graph *irg = env->irg;
1121 ir_node *block = env->block;
1122 ir_node *node = env->irn;
1123 ir_node *sel = get_Cond_selector(node);
1124 ir_mode *sel_mode = get_irn_mode(sel);
1125 ir_node *res = NULL;
1126 ir_node *pred = NULL;
1127 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1129 if (is_Proj(sel) && sel_mode == mode_b) {
1130 pred = get_Proj_pred(sel);
1132 /* get both compare operators */
1133 cmp_a = get_Cmp_left(pred);
1134 cmp_b = get_Cmp_right(pred);
1136 /* check if we can use a CondJmp with immediate */
1137 cnst = get_immediate_op(cmp_a, cmp_b);
1138 expr = get_expr_op(cmp_a, cmp_b);
1141 res = new_rd_ia32_CondJmp_i(dbg, irg, block, expr, mode_T);
1142 set_ia32_Immop_attr(res, cnst);
1145 res = new_rd_ia32_CondJmp(dbg, irg, block, cmp_a, cmp_b, mode_T);
1148 set_ia32_pncode(res, get_Proj_proj(sel));
1151 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1152 set_ia32_pncode(res, get_Cond_defaultProj(node));
1161 * Transform the argument projs from a start node corresponding to the
1162 * calling convention.
1163 * It transforms "Proj Arg x -> ProjT -> Start <- ProjM" into
1164 * "RegParam x -> ProjT -> Start" OR
1165 * "StackParam x -> ProjM -> Start"
1166 * whether parameter is passed in register or on stack.
1168 * @param mod the debug module
1169 * @param block the block the nodes should belong to
1170 * @param proj the ProjT node which points to Start
1171 * @param start the Start node
1172 * @return Should be always NULL
1174 static ir_node *gen_Proj_Start(ia32_transform_env_t *env, ir_node *proj, ir_node *start) {
1175 const ia32_register_req_t *temp_req;
1176 const ir_edge_t *edge;
1177 ir_node *succ, *irn;
1182 ir_node *proj_M = get_irg_initial_mem(current_ir_graph);
1183 entity *irg_ent = get_irg_entity(current_ir_graph);
1184 ir_type *tp = get_entity_type(irg_ent);
1186 ir_graph *irg = env->irg;
1187 ir_node *block = env->block;
1189 assert(is_Method_type(tp) && "irg type is not a method");
1191 switch(get_Proj_proj(proj)) {
1192 case pn_Start_T_args:
1193 /* We cannot use get_method_n_params here as the function might
1194 be variadic or one argument is not used. */
1195 n = get_irn_n_edges(proj);
1197 /* Allocate memory for all non variadic parameters in advance to be on the save side */
1198 env->cg->reg_param_req = xcalloc(get_method_n_params(tp), sizeof(ia32_register_req_t *));
1200 /* we are done here when there are no parameters */
1204 /* temporary remember all proj arg x */
1205 projargs = xcalloc(n, sizeof(ir_node *));
1208 foreach_out_edge((const ir_node *)proj, edge) {
1209 succ = get_edge_src_irn(edge);
1210 assert(is_Proj(succ) && "non-Proj from a Proj_T (pn_Start_T_args).");
1211 projargs[i++] = succ;
1214 cc = get_method_calling_convention(tp);
1216 /* loop over all parameters and check whether its a int or float */
1217 for (i = 0; i < n; i++) {
1218 mode = get_irn_mode(projargs[i]);
1219 cur_pn = get_Proj_proj(projargs[i]);
1221 if (cc & cc_reg_param) {
1222 temp_req = ia32_get_RegParam_req(n, projargs, cur_pn, cc);
1229 /* passed in register */
1230 env->cg->reg_param_req[cur_pn] = temp_req;
1233 /* passed on stack */
1234 if (mode_is_float(mode))
1235 irn = new_rd_ia32_fStackParam(get_irn_dbg_info(projargs[i]), irg, block, proj_M, mode);
1237 irn = new_rd_ia32_StackParam(get_irn_dbg_info(projargs[i]), irg, block, proj_M, mode);
1239 set_ia32_pncode(irn, cur_pn);
1241 /* kill the old "Proj Arg" and replace with the new stack param */
1242 exchange(projargs[i], irn);
1249 case pn_Start_P_frame_base:
1250 case pn_Start_X_initial_exec:
1252 case pn_Start_P_globals:
1253 case pn_Start_P_value_arg_base:
1256 assert(0 && "unsupported Proj(Start)");
1263 * Transform some Proj's (Proj_Proj, Proj_Start, Proj_Cmp, Proj_Cond, Proj_Call).
1264 * All others are ignored.
1266 * @param mod the debug module
1267 * @param block the block the new node should belong to
1268 * @param node the ir Proj node
1269 * @param mode mode of the Proj
1270 * @return The transformed node.
1272 static ir_node *gen_Proj(ia32_transform_env_t *env) {
1273 ir_node *new_node = NULL;
1274 ir_node *pred = get_Proj_pred(env->irn);
1276 if (env->mode == mode_M)
1279 if (get_irn_op(pred) == op_Start) {
1280 new_node = gen_Proj_Start(env, env->irn, pred);
1289 * Transforms an Alloc node into either ia32_Alloca or ia32_Malloc.
1291 static ir_node *gen_Alloc(ia32_transform_env_t *env) {
1292 dbg_info *dbg = env->dbg;
1293 ir_graph *irg = env->irg;
1294 ir_node *block = env->block;
1295 ir_node *irn = env->irn;
1296 ir_mode *mode = env->mode;
1297 ir_node *size = get_Alloc_size(irn);
1298 ir_node *mem = get_Alloc_mem(irn);
1301 if (get_Alloc_where(irn) == stack_alloc) {
1302 if (is_ia32_Const(size)) {
1303 res = new_rd_ia32_Alloca_i(dbg, irg, block, mem, mode);
1304 set_ia32_Immop_attr(res, size);
1307 res = new_rd_ia32_Alloca(dbg, irg, block, size, mem, mode);
1311 assert(0 && "malloc should be already lowered");
1318 /*********************************************************
1321 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1322 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1323 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1324 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1326 *********************************************************/
1331 * Transforms the given firm node (and maybe some other related nodes)
1332 * into one or more assembler nodes.
1334 * @param node the firm node
1335 * @param env the debug module
1337 void ia32_transform_node(ir_node *node, void *env) {
1338 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1339 opcode code = get_irn_opcode(node);
1340 ir_node *asm_node = NULL;
1341 ia32_transform_env_t tenv;
1346 tenv.arch_env = cgenv->arch_env;
1347 tenv.block = get_nodes_block(node);
1348 tenv.dbg = get_irn_dbg_info(node);
1349 tenv.irg = current_ir_graph;
1351 tenv.mod = cgenv->mod;
1352 tenv.mode = get_irn_mode(node);
1355 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1356 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1357 #define BINOP_COM(a) case iro_##a: asm_node = gen_arith_Op(&tenv, get_##a##_left(node), get_##a##_right(node), 1); break
1358 #define BINOP_NCOM(a) case iro_##a: asm_node = gen_arith_Op(&tenv, get_##a##_left(node), get_##a##_right(node), 0); break
1359 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1360 #define IGN(a) case iro_##a: break
1361 #define BAD(a) case iro_##a: goto bad
1363 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1402 /* constant transformation happens earlier */
1424 if (get_irn_op(node) == get_op_Max() ||
1425 get_irn_op(node) == get_op_Min() ||
1426 get_irn_op(node) == get_op_Mulh())
1428 asm_node = gen_arith_Op(&tenv, get_irn_n(node, 0), get_irn_n(node, 1), 1);
1432 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1437 exchange(node, asm_node);
1438 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1441 DB((tenv.mod, LEVEL_1, "ignored\n"));