2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
152 * creates a unique ident by adding a number to a tag
154 * @param tag the tag string, must contain a %d if a number
157 static ident *unique_id(const char *tag)
159 static unsigned id = 0;
162 snprintf(str, sizeof(str), tag, ++id);
163 return new_id_from_str(str);
167 * Get a primitive type for a mode.
169 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
171 pmap_entry *e = pmap_find(types, mode);
176 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
177 res = new_type_primitive(new_id_from_str(buf), mode);
178 set_type_alignment_bytes(res, 16);
179 pmap_insert(types, mode, res);
187 * Get an atomic entity that is initialized with a tarval
189 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
191 tarval *tv = get_Const_tarval(cnst);
192 pmap_entry *e = pmap_find(isa->tv_ent, tv);
197 ir_mode *mode = get_irn_mode(cnst);
198 ir_type *tp = get_Const_type(cnst);
199 if (tp == firm_unknown_type)
200 tp = get_prim_type(isa->types, mode);
202 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
204 set_entity_ld_ident(res, get_entity_ident(res));
205 set_entity_visibility(res, visibility_local);
206 set_entity_variability(res, variability_constant);
207 set_entity_allocation(res, allocation_static);
209 /* we create a new entity here: It's initialization must resist on the
211 rem = current_ir_graph;
212 current_ir_graph = get_const_code_irg();
213 set_atomic_ent_value(res, new_Const_type(tv, tp));
214 current_ir_graph = rem;
216 pmap_insert(isa->tv_ent, tv, res);
224 static int is_Const_0(ir_node *node) {
228 return classify_Const(node) == CNST_NULL;
231 static int is_Const_1(ir_node *node) {
235 return classify_Const(node) == CNST_ONE;
238 static int is_Const_Minus_1(ir_node *node) {
244 mode = get_irn_mode(node);
245 if(!mode_is_signed(mode))
248 tv = get_Const_tarval(node);
251 return classify_tarval(tv) == CNST_ONE;
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
270 cnst_classify_t clss = classify_Const(node);
272 if (USE_SSE2(env_cg)) {
273 if (clss == CNST_NULL) {
274 load = new_rd_ia32_xZero(dbgi, irg, block);
275 set_ia32_ls_mode(load, mode);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
282 set_ia32_op_type(load, ia32_AddrModeS);
283 set_ia32_am_sc(load, floatent);
284 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
285 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
288 if (clss == CNST_NULL) {
289 load = new_rd_ia32_vfldz(dbgi, irg, block);
291 } else if (clss == CNST_ONE) {
292 load = new_rd_ia32_vfld1(dbgi, irg, block);
295 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
297 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
298 set_ia32_op_type(load, ia32_AddrModeS);
299 set_ia32_am_sc(load, floatent);
300 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
301 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
303 set_ia32_ls_mode(load, mode);
306 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
308 /* Const Nodes before the initial IncSP are a bad idea, because
309 * they could be spilled and we have no SP ready at that point yet.
310 * So add a dependency to the initial frame pointer calculation to
311 * avoid that situation.
313 if (get_irg_start_block(irg) == block) {
314 add_irn_dep(load, get_irg_frame(irg));
317 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
321 tarval *tv = get_Const_tarval(node);
324 tv = tarval_convert_to(tv, mode_Iu);
326 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
328 panic("couldn't convert constant tarval (%+F)", node);
330 val = get_tarval_long(tv);
332 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
333 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
336 if (get_irg_start_block(irg) == block) {
337 add_irn_dep(cnst, get_irg_frame(irg));
345 * Transforms a SymConst.
347 static ir_node *gen_SymConst(ir_node *node) {
348 ir_graph *irg = current_ir_graph;
349 ir_node *old_block = get_nodes_block(node);
350 ir_node *block = be_transform_node(old_block);
351 dbg_info *dbgi = get_irn_dbg_info(node);
352 ir_mode *mode = get_irn_mode(node);
355 if (mode_is_float(mode)) {
356 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
357 ir_node *nomem = new_NoMem();
359 if (USE_SSE2(env_cg))
360 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
363 set_ia32_am_sc(cnst, get_SymConst_entity(node));
364 set_ia32_use_frame(cnst);
368 if(get_SymConst_kind(node) != symconst_addr_ent) {
369 panic("backend only support symconst_addr_ent (at %+F)", node);
371 entity = get_SymConst_entity(node);
372 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
375 /* Const Nodes before the initial IncSP are a bad idea, because
376 * they could be spilled and we have no SP ready at that point yet
378 if (get_irg_start_block(irg) == block) {
379 add_irn_dep(cnst, get_irg_frame(irg));
382 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
387 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
388 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
389 static const struct {
391 const char *ent_name;
392 const char *cnst_str;
395 } names [ia32_known_const_max] = {
396 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
397 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
398 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
399 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
400 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
402 static ir_entity *ent_cache[ia32_known_const_max];
404 const char *tp_name, *ent_name, *cnst_str;
412 ent_name = names[kct].ent_name;
413 if (! ent_cache[kct]) {
414 tp_name = names[kct].tp_name;
415 cnst_str = names[kct].cnst_str;
417 switch (names[kct].mode) {
418 case 0: mode = mode_Iu; break;
419 case 1: mode = mode_Lu; break;
420 default: mode = mode_F; break;
422 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
423 tp = new_type_primitive(new_id_from_str(tp_name), mode);
424 /* set the specified alignment */
425 set_type_alignment_bytes(tp, names[kct].align);
427 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
429 set_entity_ld_ident(ent, get_entity_ident(ent));
430 set_entity_visibility(ent, visibility_local);
431 set_entity_variability(ent, variability_constant);
432 set_entity_allocation(ent, allocation_static);
434 /* we create a new entity here: It's initialization must resist on the
436 rem = current_ir_graph;
437 current_ir_graph = get_const_code_irg();
438 cnst = new_Const(mode, tv);
439 current_ir_graph = rem;
441 set_atomic_ent_value(ent, cnst);
443 /* cache the entry */
444 ent_cache[kct] = ent;
447 return ent_cache[kct];
452 * Prints the old node name on cg obst and returns a pointer to it.
454 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
455 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
457 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
458 obstack_1grow(isa->name_obst, 0);
459 return obstack_finish(isa->name_obst);
463 static int use_source_address_mode(ir_node *block, ir_node *node,
472 load = get_Proj_pred(node);
473 pn = get_Proj_proj(node);
474 if(!is_Load(load) || pn != pn_Load_res)
476 if(get_nodes_block(load) != block)
478 /* we only use address mode if we're the only user of the load */
479 if(get_irn_n_edges(node) > 1)
482 mode = get_irn_mode(node);
483 if(!mode_needs_gp_reg(mode))
485 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
488 /* don't do AM if other node inputs depend on the load (via mem-proj) */
489 if(other != NULL && get_nodes_block(other) == block
490 && heights_reachable_in_block(heights, other, load))
496 typedef struct ia32_address_mode_t ia32_address_mode_t;
497 struct ia32_address_mode_t {
501 ia32_op_type_t op_type;
508 static void build_address(ia32_address_mode_t *am, ir_node *node)
510 ia32_address_t *addr = &am->addr;
511 ir_node *load = get_Proj_pred(node);
512 ir_node *ptr = get_Load_ptr(load);
513 ir_node *mem = get_Load_mem(load);
514 ir_node *new_mem = be_transform_node(mem);
518 am->ls_mode = get_Load_mode(load);
519 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
521 /* construct load address */
522 ia32_create_address_mode(addr, ptr, 0);
527 base = ia32_new_NoReg_gp(env_cg);
529 base = be_transform_node(base);
533 index = ia32_new_NoReg_gp(env_cg);
535 index = be_transform_node(index);
543 static void set_address(ir_node *node, ia32_address_t *addr)
545 set_ia32_am_scale(node, addr->scale);
546 set_ia32_am_sc(node, addr->symconst_ent);
547 set_ia32_am_offs_int(node, addr->offset);
548 if(addr->symconst_sign)
549 set_ia32_am_sc_sign(node);
551 set_ia32_use_frame(node);
552 set_ia32_frame_ent(node, addr->frame_entity);
555 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
557 set_address(node, &am->addr);
559 set_ia32_op_type(node, am->op_type);
560 set_ia32_ls_mode(node, am->ls_mode);
562 set_ia32_commutative(node);
565 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
566 ir_node *op1, ir_node *op2, int commutative,
567 int use_am_and_immediates, int use_am,
570 ia32_address_t *addr = &am->addr;
571 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
575 memset(am, 0, sizeof(am[0]));
577 if(!use_8_16_bit_am && get_mode_size_bits(get_irn_mode(op1)) < 32)
580 new_op2 = try_create_Immediate(op2, 0);
581 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
582 build_address(am, op2);
583 new_op1 = be_transform_node(op1);
585 am->op_type = ia32_AddrModeS;
586 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
587 use_am && use_source_address_mode(block, op1, op2)) {
588 build_address(am, op1);
589 if(new_op2 != NULL) {
592 new_op1 = be_transform_node(op2);
596 am->op_type = ia32_AddrModeS;
598 new_op1 = be_transform_node(op1);
600 new_op2 = be_transform_node(op2);
601 am->op_type = ia32_Normal;
603 if(addr->base == NULL)
604 addr->base = noreg_gp;
605 if(addr->index == NULL)
606 addr->index = noreg_gp;
607 if(addr->mem == NULL)
608 addr->mem = new_NoMem();
610 am->new_op1 = new_op1;
611 am->new_op2 = new_op2;
612 am->commutative = commutative;
615 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
617 ir_graph *irg = current_ir_graph;
621 if(am->mem_proj == NULL)
624 /* we have to create a mode_T so the old MemProj can attach to us */
625 mode = get_irn_mode(node);
626 load = get_Proj_pred(am->mem_proj);
628 mark_irn_visited(load);
629 be_set_transformed_node(load, node);
632 set_irn_mode(node, mode_T);
633 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
640 * Construct a standard binary operation, set AM and immediate if required.
642 * @param op1 The first operand
643 * @param op2 The second operand
644 * @param func The node constructor function
645 * @return The constructed ia32 node.
647 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
648 construct_binop_func *func, int commutative)
650 ir_node *src_block = get_nodes_block(node);
651 ir_node *block = be_transform_node(src_block);
652 ir_graph *irg = current_ir_graph;
653 dbg_info *dbgi = get_irn_dbg_info(node);
655 ia32_address_mode_t am;
656 ia32_address_t *addr = &am.addr;
658 match_arguments(&am, src_block, op1, op2, commutative, 0, 1, 0);
660 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
661 am.new_op1, am.new_op2);
662 set_am_attributes(new_node, &am);
663 /* we can't use source address mode anymore when using immediates */
664 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
665 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
666 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
668 new_node = fix_mem_proj(new_node, &am);
674 * Construct a standard binary operation, set AM and immediate if required.
676 * @param op1 The first operand
677 * @param op2 The second operand
678 * @param func The node constructor function
679 * @return The constructed ia32 node.
681 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
682 construct_binop_func *func)
684 ir_node *block = be_transform_node(get_nodes_block(node));
685 ir_node *new_op1 = be_transform_node(op1);
686 ir_node *new_op2 = be_transform_node(op2);
687 ir_node *new_node = NULL;
688 dbg_info *dbgi = get_irn_dbg_info(node);
689 ir_graph *irg = current_ir_graph;
690 ir_mode *mode = get_irn_mode(node);
691 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
692 ir_node *nomem = new_NoMem();
694 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
696 if (is_op_commutative(get_irn_op(node))) {
697 set_ia32_commutative(new_node);
699 set_ia32_ls_mode(new_node, mode);
701 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
706 static ir_node *get_fpcw(void)
709 if(initial_fpcw != NULL)
712 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
713 &ia32_fp_cw_regs[REG_FPCW]);
714 initial_fpcw = be_transform_node(fpcw);
720 * Construct a standard binary operation, set AM and immediate if required.
722 * @param op1 The first operand
723 * @param op2 The second operand
724 * @param func The node constructor function
725 * @return The constructed ia32 node.
727 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
728 construct_binop_float_func *func)
730 ir_node *block = be_transform_node(get_nodes_block(node));
731 ir_node *new_op1 = be_transform_node(op1);
732 ir_node *new_op2 = be_transform_node(op2);
733 ir_node *new_node = NULL;
734 dbg_info *dbgi = get_irn_dbg_info(node);
735 ir_graph *irg = current_ir_graph;
736 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
737 ir_node *nomem = new_NoMem();
739 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
741 if (is_op_commutative(get_irn_op(node))) {
742 set_ia32_commutative(new_node);
745 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
751 * Construct a shift/rotate binary operation, sets AM and immediate if required.
753 * @param op1 The first operand
754 * @param op2 The second operand
755 * @param func The node constructor function
756 * @return The constructed ia32 node.
758 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
759 construct_shift_func *func)
761 dbg_info *dbgi = get_irn_dbg_info(node);
762 ir_graph *irg = current_ir_graph;
763 ir_node *block = get_nodes_block(node);
764 ir_node *new_block = be_transform_node(block);
765 ir_node *new_op1 = be_transform_node(op1);
766 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
769 assert(! mode_is_float(get_irn_mode(node))
770 && "Shift/Rotate with float not supported");
772 res = func(dbgi, irg, new_block, new_op1, new_op2);
773 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
775 /* lowered shift instruction may have a dependency operand, handle it here */
776 if (get_irn_arity(node) == 3) {
777 /* we have a dependency */
778 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
779 add_irn_dep(res, new_dep);
787 * Construct a standard unary operation, set AM and immediate if required.
789 * @param op The operand
790 * @param func The node constructor function
791 * @return The constructed ia32 node.
793 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
795 ir_node *block = be_transform_node(get_nodes_block(node));
796 ir_node *new_op = be_transform_node(op);
797 ir_node *new_node = NULL;
798 ir_graph *irg = current_ir_graph;
799 dbg_info *dbgi = get_irn_dbg_info(node);
801 new_node = func(dbgi, irg, block, new_op);
803 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
808 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
809 ia32_address_t *addr)
811 ir_graph *irg = current_ir_graph;
812 ir_node *base = addr->base;
813 ir_node *index = addr->index;
817 base = ia32_new_NoReg_gp(env_cg);
819 base = be_transform_node(base);
823 index = ia32_new_NoReg_gp(env_cg);
825 index = be_transform_node(index);
828 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
829 set_address(res, addr);
834 static int am_has_immediates(const ia32_address_t *addr)
836 return addr->offset != 0 || addr->symconst_ent != NULL
837 || addr->frame_entity || addr->use_frame;
841 * Creates an ia32 Add.
843 * @return the created ia32 Add node
845 static ir_node *gen_Add(ir_node *node) {
846 ir_node *block = be_transform_node(get_nodes_block(node));
847 ir_node *op1 = get_Add_left(node);
848 ir_node *op2 = get_Add_right(node);
851 ir_graph *irg = current_ir_graph;
852 dbg_info *dbgi = get_irn_dbg_info(node);
853 ir_mode *mode = get_irn_mode(node);
854 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
855 ir_node *src_block = get_nodes_block(node);
856 ir_node *add_immediate_op;
858 ia32_address_mode_t am;
860 if (mode_is_float(mode)) {
861 if (USE_SSE2(env_cg))
862 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
864 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
869 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
870 * 1. Add with immediate -> Lea
871 * 2. Add with possible source address mode -> Add
872 * 3. Otherwise -> Lea
874 memset(&addr, 0, sizeof(addr));
875 ia32_create_address_mode(&addr, node, 1);
876 add_immediate_op = NULL;
878 if(addr.base == NULL && addr.index == NULL) {
879 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
880 addr.symconst_sign, addr.offset);
881 add_irn_dep(new_op, get_irg_frame(irg));
882 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
885 /* add with immediate? */
886 if(addr.index == NULL) {
887 add_immediate_op = addr.base;
888 } else if(addr.base == NULL && addr.scale == 0) {
889 add_immediate_op = addr.index;
892 if(add_immediate_op != NULL) {
893 if(!am_has_immediates(&addr)) {
895 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
898 return be_transform_node(add_immediate_op);
901 new_op = create_lea_from_address(dbgi, block, &addr);
902 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
906 /* test if we can use source address mode */
907 memset(&am, 0, sizeof(am));
909 if(use_source_address_mode(src_block, op2, op1)) {
910 build_address(&am, op2);
911 new_op1 = be_transform_node(op1);
912 } else if(use_source_address_mode(src_block, op1, op2)) {
913 build_address(&am, op1);
914 new_op1 = be_transform_node(op2);
916 /* construct an Add with source address mode */
917 if(new_op1 != NULL) {
918 ia32_address_t *am_addr = &am.addr;
919 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
920 am_addr->mem, new_op1, noreg);
921 set_address(new_op, am_addr);
922 set_ia32_op_type(new_op, ia32_AddrModeS);
923 set_ia32_ls_mode(new_op, am.ls_mode);
924 set_ia32_commutative(new_op);
925 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
927 new_op = fix_mem_proj(new_op, &am);
932 /* otherwise construct a lea */
933 new_op = create_lea_from_address(dbgi, block, &addr);
934 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
939 * Creates an ia32 Mul.
941 * @return the created ia32 Mul node
943 static ir_node *gen_Mul(ir_node *node) {
944 ir_node *op1 = get_Mul_left(node);
945 ir_node *op2 = get_Mul_right(node);
946 ir_mode *mode = get_irn_mode(node);
948 if (mode_is_float(mode)) {
949 if (USE_SSE2(env_cg))
950 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
952 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
956 for the lower 32bit of the result it doesn't matter whether we use
957 signed or unsigned multiplication so we use IMul as it has fewer
960 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
964 * Creates an ia32 Mulh.
965 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
966 * this result while Mul returns the lower 32 bit.
968 * @return the created ia32 Mulh node
970 static ir_node *gen_Mulh(ir_node *node) {
971 ir_node *block = be_transform_node(get_nodes_block(node));
972 ir_node *op1 = get_irn_n(node, 0);
973 ir_node *new_op1 = be_transform_node(op1);
974 ir_node *op2 = get_irn_n(node, 1);
975 ir_node *new_op2 = be_transform_node(op2);
976 ir_graph *irg = current_ir_graph;
977 dbg_info *dbgi = get_irn_dbg_info(node);
978 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
979 ir_mode *mode = get_irn_mode(node);
980 ir_node *proj_EDX, *res;
982 assert(!mode_is_float(mode) && "Mulh with float not supported");
983 if (mode_is_signed(mode)) {
984 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
987 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
991 set_ia32_commutative(res);
993 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1001 * Creates an ia32 And.
1003 * @return The created ia32 And node
1005 static ir_node *gen_And(ir_node *node) {
1006 ir_node *op1 = get_And_left(node);
1007 ir_node *op2 = get_And_right(node);
1008 assert(! mode_is_float(get_irn_mode(node)));
1010 /* is it a zero extension? */
1011 if (is_Const(op2)) {
1012 tarval *tv = get_Const_tarval(op2);
1013 long v = get_tarval_long(tv);
1015 if (v == 0xFF || v == 0xFFFF) {
1016 dbg_info *dbgi = get_irn_dbg_info(node);
1017 ir_node *block = get_nodes_block(node);
1024 assert(v == 0xFFFF);
1027 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1033 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1039 * Creates an ia32 Or.
1041 * @return The created ia32 Or node
1043 static ir_node *gen_Or(ir_node *node) {
1044 ir_node *op1 = get_Or_left(node);
1045 ir_node *op2 = get_Or_right(node);
1047 assert (! mode_is_float(get_irn_mode(node)));
1048 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1054 * Creates an ia32 Eor.
1056 * @return The created ia32 Eor node
1058 static ir_node *gen_Eor(ir_node *node) {
1059 ir_node *op1 = get_Eor_left(node);
1060 ir_node *op2 = get_Eor_right(node);
1062 assert(! mode_is_float(get_irn_mode(node)));
1063 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1068 * Creates an ia32 Sub.
1070 * @return The created ia32 Sub node
1072 static ir_node *gen_Sub(ir_node *node) {
1073 ir_node *op1 = get_Sub_left(node);
1074 ir_node *op2 = get_Sub_right(node);
1075 ir_mode *mode = get_irn_mode(node);
1077 if (mode_is_float(mode)) {
1078 if (USE_SSE2(env_cg))
1079 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1081 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1085 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1089 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1095 * Generates an ia32 DivMod with additional infrastructure for the
1096 * register allocator if needed.
1098 * @param dividend -no comment- :)
1099 * @param divisor -no comment- :)
1100 * @param dm_flav flavour_Div/Mod/DivMod
1101 * @return The created ia32 DivMod node
1103 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1104 ir_node *divisor, ia32_op_flavour_t dm_flav)
1106 ir_node *block = be_transform_node(get_nodes_block(node));
1107 ir_node *new_dividend = be_transform_node(dividend);
1108 ir_node *new_divisor = be_transform_node(divisor);
1109 ir_graph *irg = current_ir_graph;
1110 dbg_info *dbgi = get_irn_dbg_info(node);
1111 ir_mode *mode = get_irn_mode(node);
1112 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1113 ir_node *res, *proj_div, *proj_mod;
1114 ir_node *sign_extension;
1115 ir_node *mem, *new_mem;
1118 proj_div = proj_mod = NULL;
1122 mem = get_Div_mem(node);
1123 mode = get_Div_resmode(node);
1124 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1125 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1128 mem = get_Mod_mem(node);
1129 mode = get_Mod_resmode(node);
1130 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1131 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1133 case flavour_DivMod:
1134 mem = get_DivMod_mem(node);
1135 mode = get_DivMod_resmode(node);
1136 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1137 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1138 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1141 panic("invalid divmod flavour!");
1143 new_mem = be_transform_node(mem);
1145 if (mode_is_signed(mode)) {
1146 /* in signed mode, we need to sign extend the dividend */
1147 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1148 add_irn_dep(produceval, get_irg_frame(irg));
1149 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1152 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1153 add_irn_dep(sign_extension, get_irg_frame(irg));
1156 if (mode_is_signed(mode)) {
1157 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1158 new_dividend, sign_extension, new_divisor, dm_flav);
1160 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1161 sign_extension, new_divisor, dm_flav);
1164 set_ia32_exc_label(res, has_exc);
1165 set_irn_pinned(res, get_irn_pinned(node));
1167 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1174 * Wrapper for generate_DivMod. Sets flavour_Mod.
1177 static ir_node *gen_Mod(ir_node *node) {
1178 return generate_DivMod(node, get_Mod_left(node),
1179 get_Mod_right(node), flavour_Mod);
1183 * Wrapper for generate_DivMod. Sets flavour_Div.
1186 static ir_node *gen_Div(ir_node *node) {
1187 return generate_DivMod(node, get_Div_left(node),
1188 get_Div_right(node), flavour_Div);
1192 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1194 static ir_node *gen_DivMod(ir_node *node) {
1195 return generate_DivMod(node, get_DivMod_left(node),
1196 get_DivMod_right(node), flavour_DivMod);
1202 * Creates an ia32 floating Div.
1204 * @return The created ia32 xDiv node
1206 static ir_node *gen_Quot(ir_node *node) {
1207 ir_node *block = be_transform_node(get_nodes_block(node));
1208 ir_node *op1 = get_Quot_left(node);
1209 ir_node *new_op1 = be_transform_node(op1);
1210 ir_node *op2 = get_Quot_right(node);
1211 ir_node *new_op2 = be_transform_node(op2);
1212 ir_graph *irg = current_ir_graph;
1213 dbg_info *dbgi = get_irn_dbg_info(node);
1214 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1215 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1218 if (USE_SSE2(env_cg)) {
1219 ir_mode *mode = get_irn_mode(op1);
1220 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1222 set_ia32_ls_mode(new_op, mode);
1224 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1225 new_op2, get_fpcw());
1227 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1233 * Creates an ia32 Shl.
1235 * @return The created ia32 Shl node
1237 static ir_node *gen_Shl(ir_node *node) {
1238 ir_node *right = get_Shl_right(node);
1240 /* test whether we can build a lea */
1241 if(is_Const(right)) {
1242 tarval *tv = get_Const_tarval(right);
1243 if(tarval_is_long(tv)) {
1244 long val = get_tarval_long(tv);
1245 if(val >= 0 && val <= 3) {
1246 ir_graph *irg = current_ir_graph;
1247 dbg_info *dbgi = get_irn_dbg_info(node);
1248 ir_node *block = be_transform_node(get_nodes_block(node));
1249 ir_node *base = ia32_new_NoReg_gp(env_cg);
1250 ir_node *index = be_transform_node(get_Shl_left(node));
1251 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1252 set_ia32_am_scale(res, val);
1253 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1259 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1266 * Creates an ia32 Shr.
1268 * @return The created ia32 Shr node
1270 static ir_node *gen_Shr(ir_node *node) {
1271 return gen_shift_binop(node, get_Shr_left(node),
1272 get_Shr_right(node), new_rd_ia32_Shr);
1278 * Creates an ia32 Sar.
1280 * @return The created ia32 Shrs node
1282 static ir_node *gen_Shrs(ir_node *node) {
1283 ir_node *left = get_Shrs_left(node);
1284 ir_node *right = get_Shrs_right(node);
1285 ir_mode *mode = get_irn_mode(node);
1286 if(is_Const(right) && mode == mode_Is) {
1287 tarval *tv = get_Const_tarval(right);
1288 long val = get_tarval_long(tv);
1290 /* this is a sign extension */
1291 ir_graph *irg = current_ir_graph;
1292 dbg_info *dbgi = get_irn_dbg_info(node);
1293 ir_node *block = be_transform_node(get_nodes_block(node));
1295 ir_node *new_op = be_transform_node(op);
1296 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1297 add_irn_dep(pval, get_irg_frame(irg));
1299 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1303 /* 8 or 16 bit sign extension? */
1304 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1305 ir_node *shl_left = get_Shl_left(left);
1306 ir_node *shl_right = get_Shl_right(left);
1307 if(is_Const(shl_right)) {
1308 tarval *tv1 = get_Const_tarval(right);
1309 tarval *tv2 = get_Const_tarval(shl_right);
1310 if(tv1 == tv2 && tarval_is_long(tv1)) {
1311 long val = get_tarval_long(tv1);
1312 if(val == 16 || val == 24) {
1313 dbg_info *dbgi = get_irn_dbg_info(node);
1314 ir_node *block = get_nodes_block(node);
1324 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1333 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1339 * Creates an ia32 RotL.
1341 * @param op1 The first operator
1342 * @param op2 The second operator
1343 * @return The created ia32 RotL node
1345 static ir_node *gen_RotL(ir_node *node,
1346 ir_node *op1, ir_node *op2) {
1347 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1353 * Creates an ia32 RotR.
1354 * NOTE: There is no RotR with immediate because this would always be a RotL
1355 * "imm-mode_size_bits" which can be pre-calculated.
1357 * @param op1 The first operator
1358 * @param op2 The second operator
1359 * @return The created ia32 RotR node
1361 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1363 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1369 * Creates an ia32 RotR or RotL (depending on the found pattern).
1371 * @return The created ia32 RotL or RotR node
1373 static ir_node *gen_Rot(ir_node *node) {
1374 ir_node *rotate = NULL;
1375 ir_node *op1 = get_Rot_left(node);
1376 ir_node *op2 = get_Rot_right(node);
1378 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1379 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1380 that means we can create a RotR instead of an Add and a RotL */
1382 if (get_irn_op(op2) == op_Add) {
1384 ir_node *left = get_Add_left(add);
1385 ir_node *right = get_Add_right(add);
1386 if (is_Const(right)) {
1387 tarval *tv = get_Const_tarval(right);
1388 ir_mode *mode = get_irn_mode(node);
1389 long bits = get_mode_size_bits(mode);
1391 if (get_irn_op(left) == op_Minus &&
1392 tarval_is_long(tv) &&
1393 get_tarval_long(tv) == bits)
1395 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1396 rotate = gen_RotR(node, op1, get_Minus_op(left));
1401 if (rotate == NULL) {
1402 rotate = gen_RotL(node, op1, op2);
1411 * Transforms a Minus node.
1413 * @param op The Minus operand
1414 * @return The created ia32 Minus node
1416 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1417 ir_node *block = be_transform_node(get_nodes_block(node));
1418 ir_graph *irg = current_ir_graph;
1419 dbg_info *dbgi = get_irn_dbg_info(node);
1420 ir_mode *mode = get_irn_mode(node);
1425 if (mode_is_float(mode)) {
1426 ir_node *new_op = be_transform_node(op);
1427 if (USE_SSE2(env_cg)) {
1428 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1429 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1430 ir_node *nomem = new_rd_NoMem(irg);
1432 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1435 size = get_mode_size_bits(mode);
1436 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1438 set_ia32_am_sc(res, ent);
1439 set_ia32_op_type(res, ia32_AddrModeS);
1440 set_ia32_ls_mode(res, mode);
1442 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1445 res = gen_unop(node, op, new_rd_ia32_Neg);
1448 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1454 * Transforms a Minus node.
1456 * @return The created ia32 Minus node
1458 static ir_node *gen_Minus(ir_node *node) {
1459 return gen_Minus_ex(node, get_Minus_op(node));
1462 static ir_node *create_Immediate_from_int(int val)
1464 ir_graph *irg = current_ir_graph;
1465 ir_node *start_block = get_irg_start_block(irg);
1466 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1467 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1472 static ir_node *gen_bin_Not(ir_node *node)
1474 ir_graph *irg = current_ir_graph;
1475 dbg_info *dbgi = get_irn_dbg_info(node);
1476 ir_node *block = be_transform_node(get_nodes_block(node));
1477 ir_node *op = get_Not_op(node);
1478 ir_node *new_op = be_transform_node(op);
1479 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1480 ir_node *nomem = new_NoMem();
1481 ir_node *one = create_Immediate_from_int(1);
1483 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1487 * Transforms a Not node.
1489 * @return The created ia32 Not node
1491 static ir_node *gen_Not(ir_node *node) {
1492 ir_node *op = get_Not_op(node);
1493 ir_mode *mode = get_irn_mode(node);
1495 if(mode == mode_b) {
1496 return gen_bin_Not(node);
1499 assert (! mode_is_float(get_irn_mode(node)));
1500 return gen_unop(node, op, new_rd_ia32_Not);
1506 * Transforms an Abs node.
1508 * @return The created ia32 Abs node
1510 static ir_node *gen_Abs(ir_node *node) {
1511 ir_node *block = be_transform_node(get_nodes_block(node));
1512 ir_node *op = get_Abs_op(node);
1513 ir_node *new_op = be_transform_node(op);
1514 ir_graph *irg = current_ir_graph;
1515 dbg_info *dbgi = get_irn_dbg_info(node);
1516 ir_mode *mode = get_irn_mode(node);
1517 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1518 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1519 ir_node *nomem = new_NoMem();
1524 if (mode_is_float(mode)) {
1525 if (USE_SSE2(env_cg)) {
1526 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1528 size = get_mode_size_bits(mode);
1529 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1531 set_ia32_am_sc(res, ent);
1533 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1535 set_ia32_op_type(res, ia32_AddrModeS);
1536 set_ia32_ls_mode(res, mode);
1539 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1540 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1544 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1545 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1548 add_irn_dep(pval, get_irg_frame(irg));
1549 SET_IA32_ORIG_NODE(sign_extension,
1550 ia32_get_old_node_name(env_cg, node));
1552 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1554 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1556 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1558 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1565 * Transforms a Load.
1567 * @return the created ia32 Load node
1569 static ir_node *gen_Load(ir_node *node) {
1570 ir_node *old_block = get_nodes_block(node);
1571 ir_node *block = be_transform_node(old_block);
1572 ir_node *ptr = get_Load_ptr(node);
1573 ir_node *mem = get_Load_mem(node);
1574 ir_node *new_mem = be_transform_node(mem);
1577 ir_graph *irg = current_ir_graph;
1578 dbg_info *dbgi = get_irn_dbg_info(node);
1579 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1580 ir_mode *mode = get_Load_mode(node);
1583 ia32_address_t addr;
1585 /* construct load address */
1586 memset(&addr, 0, sizeof(addr));
1587 ia32_create_address_mode(&addr, ptr, 0);
1594 base = be_transform_node(base);
1600 index = be_transform_node(index);
1603 if (mode_is_float(mode)) {
1604 if (USE_SSE2(env_cg)) {
1605 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1607 res_mode = mode_xmm;
1609 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1611 res_mode = mode_vfp;
1617 /* create a conv node with address mode for smaller modes */
1618 if(get_mode_size_bits(mode) < 32) {
1619 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem,
1622 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1627 set_irn_pinned(new_op, get_irn_pinned(node));
1628 set_ia32_op_type(new_op, ia32_AddrModeS);
1629 set_ia32_ls_mode(new_op, mode);
1630 set_address(new_op, &addr);
1632 /* make sure we are scheduled behind the initial IncSP/Barrier
1633 * to avoid spills being placed before it
1635 if (block == get_irg_start_block(irg)) {
1636 add_irn_dep(new_op, get_irg_frame(irg));
1639 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1640 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1645 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1646 ir_node *ptr, ir_mode *mode, ir_node *other)
1653 /* we only use address mode if we're the only user of the load */
1654 if(get_irn_n_edges(node) > 1)
1657 load = get_Proj_pred(node);
1660 if(get_nodes_block(load) != block)
1663 /* Store should be attached to the load */
1664 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1666 /* store should have the same pointer as the load */
1667 if(get_Load_ptr(load) != ptr)
1670 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1671 if(other != NULL && get_nodes_block(other) == block
1672 && heights_reachable_in_block(heights, other, load))
1675 assert(get_Load_mode(load) == mode);
1680 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1681 ir_node *mem, ir_node *ptr, ir_mode *mode,
1682 construct_binop_dest_func *func, int commutative)
1684 ir_node *src_block = get_nodes_block(node);
1686 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1687 ir_graph *irg = current_ir_graph;
1691 ia32_address_mode_t am;
1692 ia32_address_t *addr = &am.addr;
1693 memset(&am, 0, sizeof(am));
1695 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1696 build_address(&am, op1);
1697 new_op = create_immediate_or_transform(op2, 0);
1698 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1699 build_address(&am, op2);
1700 new_op = create_immediate_or_transform(op1, 0);
1705 if(addr->base == NULL)
1706 addr->base = noreg_gp;
1707 if(addr->index == NULL)
1708 addr->index = noreg_gp;
1709 if(addr->mem == NULL)
1710 addr->mem = new_NoMem();
1712 dbgi = get_irn_dbg_info(node);
1713 block = be_transform_node(src_block);
1714 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem, new_op);
1715 set_address(new_node, addr);
1716 set_ia32_op_type(new_node, ia32_AddrModeD);
1717 set_ia32_ls_mode(new_node, mode);
1718 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1723 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1724 ir_node *ptr, ir_mode *mode,
1725 construct_unop_dest_func *func)
1727 ir_node *src_block = get_nodes_block(node);
1729 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1730 ir_graph *irg = current_ir_graph;
1733 ia32_address_mode_t am;
1734 ia32_address_t *addr = &am.addr;
1735 memset(&am, 0, sizeof(am));
1737 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1740 build_address(&am, op);
1742 if(addr->base == NULL)
1743 addr->base = noreg_gp;
1744 if(addr->index == NULL)
1745 addr->index = noreg_gp;
1746 if(addr->mem == NULL)
1747 addr->mem = new_NoMem();
1749 dbgi = get_irn_dbg_info(node);
1750 block = be_transform_node(src_block);
1751 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1752 set_address(new_node, addr);
1753 set_ia32_op_type(new_node, ia32_AddrModeD);
1754 set_ia32_ls_mode(new_node, mode);
1755 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1760 static ir_node *try_create_dest_am(ir_node *node) {
1761 ir_node *val = get_Store_value(node);
1762 ir_node *mem = get_Store_mem(node);
1763 ir_node *ptr = get_Store_ptr(node);
1764 ir_mode *mode = get_irn_mode(val);
1769 /* handle only GP modes for now... */
1770 if(!mode_needs_gp_reg(mode))
1773 /* TODO0000 8bit operations have stricter constraints. This is not handled yet */
1774 if (get_mode_size_bits(mode) < 16)
1777 /* store must be the only user of the val node */
1778 if(get_irn_n_edges(val) > 1)
1781 switch(get_irn_opcode(val)) {
1783 op1 = get_Add_left(val);
1784 op2 = get_Add_right(val);
1785 if(is_Const_1(op2)) {
1786 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1787 new_rd_ia32_IncMem);
1789 } else if(is_Const_Minus_1(op2)) {
1790 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1791 new_rd_ia32_DecMem);
1794 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1795 new_rd_ia32_AddMem, 1);
1798 op1 = get_Sub_left(val);
1799 op2 = get_Sub_right(val);
1800 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1801 new_rd_ia32_SubMem, 0);
1804 op1 = get_And_left(val);
1805 op2 = get_And_right(val);
1806 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1807 new_rd_ia32_AndMem, 1);
1810 op1 = get_Or_left(val);
1811 op2 = get_Or_right(val);
1812 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1813 new_rd_ia32_OrMem, 1);
1816 op1 = get_Eor_left(val);
1817 op2 = get_Eor_right(val);
1818 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1819 new_rd_ia32_XorMem, 1);
1822 op1 = get_Shl_left(val);
1823 op2 = get_Shl_right(val);
1824 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1825 new_rd_ia32_ShlMem, 0);
1828 op1 = get_Shr_left(val);
1829 op2 = get_Shr_right(val);
1830 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1831 new_rd_ia32_ShrMem, 0);
1834 op1 = get_Shrs_left(val);
1835 op2 = get_Shrs_right(val);
1836 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1837 new_rd_ia32_SarMem, 0);
1840 op1 = get_Rot_left(val);
1841 op2 = get_Rot_right(val);
1842 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1843 new_rd_ia32_RolMem, 0);
1845 /* TODO: match ROR patterns... */
1847 op1 = get_Minus_op(val);
1848 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1851 /* TODO this would be ^ 1 with DestAM */
1854 op1 = get_Not_op(val);
1855 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1865 * Transforms a Store.
1867 * @return the created ia32 Store node
1869 static ir_node *gen_Store(ir_node *node) {
1870 ir_node *block = be_transform_node(get_nodes_block(node));
1871 ir_node *ptr = get_Store_ptr(node);
1874 ir_node *val = get_Store_value(node);
1876 ir_node *mem = get_Store_mem(node);
1877 ir_node *new_mem = be_transform_node(mem);
1878 ir_graph *irg = current_ir_graph;
1879 dbg_info *dbgi = get_irn_dbg_info(node);
1880 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1881 ir_mode *mode = get_irn_mode(val);
1883 ia32_address_t addr;
1885 /* check for destination address mode */
1886 new_op = try_create_dest_am(node);
1890 /* construct store address */
1891 memset(&addr, 0, sizeof(addr));
1892 ia32_create_address_mode(&addr, ptr, 0);
1899 base = be_transform_node(base);
1905 index = be_transform_node(index);
1908 if (mode_is_float(mode)) {
1909 new_val = be_transform_node(val);
1910 if (USE_SSE2(env_cg)) {
1911 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1914 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1918 new_val = create_immediate_or_transform(val, 0);
1922 if (get_mode_size_bits(mode) == 8) {
1923 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1926 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1931 set_irn_pinned(new_op, get_irn_pinned(node));
1932 set_ia32_op_type(new_op, ia32_AddrModeD);
1933 set_ia32_ls_mode(new_op, mode);
1935 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1936 set_address(new_op, &addr);
1937 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1942 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1943 ir_node *cmp_left, ir_node *cmp_right,
1950 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1951 ia32_address_mode_t am;
1952 ia32_address_t *addr = &am.addr;
1954 if(cmp_right != NULL && !is_Const_0(cmp_right))
1957 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1958 mode = get_irn_mode(cmp_left);
1959 arg_left = get_And_left(cmp_left);
1960 arg_right = get_And_right(cmp_left);
1962 mode = get_irn_mode(cmp_left);
1963 arg_left = cmp_left;
1964 arg_right = cmp_left;
1970 assert(get_mode_size_bits(mode) <= 32);
1971 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
1973 pnc = get_inversed_pnc(pnc);
1975 if(get_mode_size_bits(mode) == 8) {
1976 res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
1977 addr->index, addr->mem, am.new_op1,
1980 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
1981 addr->index, addr->mem, am.new_op1, am.new_op2,
1984 set_am_attributes(res, &am);
1985 set_ia32_ls_mode(res, mode);
1987 res = fix_mem_proj(res, &am);
1992 static ir_node *create_Switch(ir_node *node)
1994 ir_graph *irg = current_ir_graph;
1995 dbg_info *dbgi = get_irn_dbg_info(node);
1996 ir_node *block = be_transform_node(get_nodes_block(node));
1997 ir_node *sel = get_Cond_selector(node);
1998 ir_node *new_sel = be_transform_node(sel);
2000 int switch_min = INT_MAX;
2001 const ir_edge_t *edge;
2003 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2005 /* determine the smallest switch case value */
2006 foreach_out_edge(node, edge) {
2007 ir_node *proj = get_edge_src_irn(edge);
2008 int pn = get_Proj_proj(proj);
2013 if (switch_min != 0) {
2014 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2016 /* if smallest switch case is not 0 we need an additional sub */
2017 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2018 add_ia32_am_offs_int(new_sel, -switch_min);
2019 set_ia32_op_type(new_sel, ia32_AddrModeS);
2021 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2024 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
2025 set_ia32_pncode(res, get_Cond_defaultProj(node));
2027 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2033 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
2035 * @return The transformed node.
2037 static ir_node *gen_Cond(ir_node *node) {
2038 ir_node *src_block = get_nodes_block(node);
2039 ir_node *block = be_transform_node(src_block);
2040 ir_graph *irg = current_ir_graph;
2041 dbg_info *dbgi = get_irn_dbg_info(node);
2042 ir_node *sel = get_Cond_selector(node);
2043 ir_mode *sel_mode = get_irn_mode(sel);
2044 ir_node *res = NULL;
2045 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2046 ir_node *nomem = new_NoMem();
2056 if (sel_mode != mode_b) {
2057 return create_Switch(node);
2060 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
2061 /* it's some mode_b value but not a direct comparison -> create a
2063 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
2064 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2068 /* address mode makes only sense when we're the only user of the cmp */
2069 use_am = get_irn_n_edges(node) <= 1;
2071 cmp = get_Proj_pred(sel);
2072 cmp_a = get_Cmp_left(cmp);
2073 cmp_b = get_Cmp_right(cmp);
2074 cmp_mode = get_irn_mode(cmp_a);
2075 pnc = get_Proj_proj(sel);
2076 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
2077 pnc |= ia32_pn_Cmp_Unsigned;
2080 if(mode_needs_gp_reg(cmp_mode)) {
2081 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
2083 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2088 if (mode_is_float(cmp_mode)) {
2089 new_cmp_a = be_transform_node(cmp_a);
2090 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
2091 if (USE_SSE2(env_cg)) {
2092 res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, nomem, cmp_a,
2094 set_ia32_commutative(res);
2095 set_ia32_ls_mode(res, cmp_mode);
2097 res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
2098 set_ia32_commutative(res);
2101 ia32_address_mode_t am;
2102 ia32_address_t *addr = &am.addr;
2103 match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am, 1);
2105 pnc = get_inversed_pnc(pnc);
2107 if(get_mode_size_bits(cmp_mode) == 8) {
2108 res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base, addr->index,
2109 addr->mem, am.new_op1, am.new_op2, pnc);
2111 res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
2112 addr->mem, am.new_op1, am.new_op2, pnc);
2114 set_am_attributes(res, &am);
2115 assert(cmp_mode != NULL);
2116 set_ia32_ls_mode(res, cmp_mode);
2118 res = fix_mem_proj(res, &am);
2121 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2129 * Transforms a CopyB node.
2131 * @return The transformed node.
2133 static ir_node *gen_CopyB(ir_node *node) {
2134 ir_node *block = be_transform_node(get_nodes_block(node));
2135 ir_node *src = get_CopyB_src(node);
2136 ir_node *new_src = be_transform_node(src);
2137 ir_node *dst = get_CopyB_dst(node);
2138 ir_node *new_dst = be_transform_node(dst);
2139 ir_node *mem = get_CopyB_mem(node);
2140 ir_node *new_mem = be_transform_node(mem);
2141 ir_node *res = NULL;
2142 ir_graph *irg = current_ir_graph;
2143 dbg_info *dbgi = get_irn_dbg_info(node);
2144 int size = get_type_size_bytes(get_CopyB_type(node));
2147 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2148 /* then we need the size explicitly in ECX. */
2149 if (size >= 32 * 4) {
2150 rem = size & 0x3; /* size % 4 */
2153 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2154 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
2156 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2157 /* we misuse the pncode field for the copyb size */
2158 set_ia32_pncode(res, rem);
2160 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2161 set_ia32_pncode(res, size);
2164 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2170 ir_node *gen_be_Copy(ir_node *node)
2172 ir_node *result = be_duplicate_node(node);
2173 ir_mode *mode = get_irn_mode(result);
2175 if (mode_needs_gp_reg(mode)) {
2176 set_irn_mode(result, mode_Iu);
2183 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2184 dbg_info *dbgi, ir_node *block, int use_am)
2186 ir_graph *irg = current_ir_graph;
2187 ir_node *new_block = be_transform_node(block);
2188 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2189 ir_node *nomem = new_rd_NoMem(irg);
2194 ia32_address_mode_t am;
2195 ia32_address_t *addr = &am.addr;
2197 /* can we use a test instruction? */
2198 if(cmp_right == NULL || is_Const_0(cmp_right)) {
2199 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2200 if(is_And(cmp_left) &&
2201 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2202 ir_node *and_left = get_And_left(cmp_left);
2203 ir_node *and_right = get_And_right(cmp_left);
2205 mode = get_irn_mode(and_left);
2206 arg_left = and_left;
2207 arg_right = and_right;
2209 mode = get_irn_mode(cmp_left);
2210 arg_left = cmp_left;
2211 arg_right = cmp_left;
2214 assert(get_mode_size_bits(mode) <= 32);
2216 match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am, 1);
2218 pnc = get_inversed_pnc(pnc);
2220 if(get_mode_size_bits(mode) == 8) {
2221 res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
2222 addr->index, addr->mem, am.new_op1,
2225 res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base, addr->index,
2226 addr->mem, am.new_op1, am.new_op2, pnc);
2228 set_am_attributes(res, &am);
2229 set_ia32_ls_mode(res, mode);
2231 res = fix_mem_proj(res, &am);
2233 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2239 mode = get_irn_mode(cmp_left);
2240 assert(get_mode_size_bits(mode) <= 32);
2242 match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am, 1);
2244 pnc = get_inversed_pnc(pnc);
2246 if(get_mode_size_bits(mode) == 8) {
2247 res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base, addr->index,
2248 addr->mem, am.new_op1, am.new_op2, pnc);
2250 res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
2251 addr->mem, am.new_op1, am.new_op2, pnc);
2253 set_am_attributes(res, &am);
2254 set_ia32_ls_mode(res, mode);
2256 res = fix_mem_proj(res, &am);
2258 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, nomem, res,
2264 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
2265 ir_node *val_true, ir_node *val_false,
2266 dbg_info *dbgi, ir_node *block)
2268 ir_graph *irg = current_ir_graph;
2269 ir_node *new_block = be_transform_node(block);
2270 ir_node *new_val_true = be_transform_node(val_true);
2271 ir_node *new_val_false = be_transform_node(val_false);
2272 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2273 ir_node *nomem = new_NoMem();
2274 ir_node *new_cmp_left;
2275 ir_node *new_cmp_right;
2279 /* cmovs with unknowns are pointless... */
2280 if(is_Unknown(val_true)) {
2281 #ifdef DEBUG_libfirm
2282 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2284 return new_val_false;
2286 if(is_Unknown(val_false)) {
2287 #ifdef DEBUG_libfirm
2288 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
2290 return new_val_true;
2293 /* can we use a test instruction? */
2294 if(is_Const_0(cmp_right)) {
2295 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
2296 if(is_And(cmp_left) &&
2297 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
2298 ir_node *and_left = get_And_left(cmp_left);
2299 ir_node *and_right = get_And_right(cmp_left);
2301 mode = get_irn_mode(and_left);
2302 new_cmp_left = be_transform_node(and_left);
2303 new_cmp_right = create_immediate_or_transform(and_right, 0);
2305 mode = get_irn_mode(cmp_left);
2306 new_cmp_left = be_transform_node(cmp_left);
2307 new_cmp_right = be_transform_node(cmp_left);
2310 assert(get_mode_size_bits(mode) <= 32);
2312 if(get_mode_size_bits(mode) == 8) {
2313 res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block, noreg,
2314 noreg, nomem, new_cmp_left, new_cmp_right,
2315 new_val_true, new_val_false, pnc);
2317 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
2318 noreg, nomem, new_cmp_left, new_cmp_right,
2319 new_val_true, new_val_false, pnc);
2321 set_ia32_ls_mode(res, mode);
2326 mode = get_irn_mode(cmp_left);
2327 new_cmp_left = be_transform_node(cmp_left);
2328 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
2330 /* no support for 8,16 bit modes yet */
2331 assert(get_mode_size_bits(mode) <= 32);
2333 if(get_mode_size_bits(mode) == 8) {
2334 res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg, nomem,
2335 new_cmp_left, new_cmp_right, new_val_true,
2336 new_val_false, pnc);
2338 res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg, nomem,
2339 new_cmp_left, new_cmp_right, new_val_true,
2340 new_val_false, pnc);
2342 set_ia32_ls_mode(res, mode);
2349 * Transforms a Psi node into CMov.
2351 * @return The transformed node.
2353 static ir_node *gen_Psi(ir_node *node) {
2354 ir_node *psi_true = get_Psi_val(node, 0);
2355 ir_node *psi_default = get_Psi_default(node);
2356 ia32_code_gen_t *cg = env_cg;
2357 ir_node *cond = get_Psi_cond(node, 0);
2358 ir_node *block = get_nodes_block(node);
2359 dbg_info *dbgi = get_irn_dbg_info(node);
2366 assert(get_Psi_n_conds(node) == 1);
2367 assert(get_irn_mode(cond) == mode_b);
2368 assert(mode_needs_gp_reg(get_irn_mode(node)));
2370 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
2371 /* a mode_b value, we have to compare it against 0 */
2373 cmp_right = new_Const_long(mode_Iu, 0);
2377 ir_node *cmp = get_Proj_pred(cond);
2379 cmp_left = get_Cmp_left(cmp);
2380 cmp_right = get_Cmp_right(cmp);
2381 cmp_mode = get_irn_mode(cmp_left);
2382 pnc = get_Proj_proj(cond);
2384 assert(!mode_is_float(cmp_mode));
2386 if (!mode_is_signed(cmp_mode)) {
2387 pnc |= ia32_pn_Cmp_Unsigned;
2391 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2392 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2393 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2394 pnc = get_negated_pnc(pnc, cmp_mode);
2395 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
2397 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
2400 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
2406 * Create a conversion from x87 state register to general purpose.
2408 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2409 ir_node *block = be_transform_node(get_nodes_block(node));
2410 ir_node *op = get_Conv_op(node);
2411 ir_node *new_op = be_transform_node(op);
2412 ia32_code_gen_t *cg = env_cg;
2413 ir_graph *irg = current_ir_graph;
2414 dbg_info *dbgi = get_irn_dbg_info(node);
2415 ir_node *noreg = ia32_new_NoReg_gp(cg);
2416 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2417 ir_mode *mode = get_irn_mode(node);
2418 ir_node *fist, *load;
2421 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2422 new_NoMem(), new_op, trunc_mode);
2424 set_irn_pinned(fist, op_pin_state_floats);
2425 set_ia32_use_frame(fist);
2426 set_ia32_op_type(fist, ia32_AddrModeD);
2428 assert(get_mode_size_bits(mode) <= 32);
2429 /* exception we can only store signed 32 bit integers, so for unsigned
2430 we store a 64bit (signed) integer and load the lower bits */
2431 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2432 set_ia32_ls_mode(fist, mode_Ls);
2434 set_ia32_ls_mode(fist, mode_Is);
2436 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2439 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2441 set_irn_pinned(load, op_pin_state_floats);
2442 set_ia32_use_frame(load);
2443 set_ia32_op_type(load, ia32_AddrModeS);
2444 set_ia32_ls_mode(load, mode_Is);
2445 if(get_ia32_ls_mode(fist) == mode_Ls) {
2446 ia32_attr_t *attr = get_ia32_attr(load);
2447 attr->data.need_64bit_stackent = 1;
2449 ia32_attr_t *attr = get_ia32_attr(load);
2450 attr->data.need_32bit_stackent = 1;
2452 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2454 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2458 * Creates a x87 strict Conv by placing a Sore and a Load
2460 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2462 ir_node *block = get_nodes_block(node);
2463 ir_graph *irg = current_ir_graph;
2464 dbg_info *dbgi = get_irn_dbg_info(node);
2465 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2466 ir_node *nomem = new_NoMem();
2467 ir_node *frame = get_irg_frame(irg);
2468 ir_node *store, *load;
2471 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2473 set_ia32_use_frame(store);
2474 set_ia32_op_type(store, ia32_AddrModeD);
2475 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2477 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2479 set_ia32_use_frame(load);
2480 set_ia32_op_type(load, ia32_AddrModeS);
2481 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2483 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2488 * Create a conversion from general purpose to x87 register
2490 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2491 ir_node *block = be_transform_node(get_nodes_block(node));
2492 ir_node *op = get_Conv_op(node);
2493 ir_node *new_op = be_transform_node(op);
2494 ir_graph *irg = current_ir_graph;
2495 dbg_info *dbgi = get_irn_dbg_info(node);
2496 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2497 ir_node *nomem = new_NoMem();
2498 ir_mode *mode = get_irn_mode(op);
2499 ir_mode *store_mode;
2500 ir_node *fild, *store;
2504 /* first convert to 32 bit signed if necessary */
2505 src_bits = get_mode_size_bits(src_mode);
2506 if (src_bits == 8) {
2507 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2509 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2511 } else if (src_bits < 32) {
2512 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2514 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2518 assert(get_mode_size_bits(mode) == 32);
2521 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2524 set_ia32_use_frame(store);
2525 set_ia32_op_type(store, ia32_AddrModeD);
2526 set_ia32_ls_mode(store, mode_Iu);
2528 /* exception for 32bit unsigned, do a 64bit spill+load */
2529 if(!mode_is_signed(mode)) {
2532 ir_node *zero_const = create_Immediate_from_int(0);
2534 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2535 get_irg_frame(irg), noreg, nomem,
2538 set_ia32_use_frame(zero_store);
2539 set_ia32_op_type(zero_store, ia32_AddrModeD);
2540 add_ia32_am_offs_int(zero_store, 4);
2541 set_ia32_ls_mode(zero_store, mode_Iu);
2546 store = new_rd_Sync(dbgi, irg, block, 2, in);
2547 store_mode = mode_Ls;
2549 store_mode = mode_Is;
2553 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2555 set_ia32_use_frame(fild);
2556 set_ia32_op_type(fild, ia32_AddrModeS);
2557 set_ia32_ls_mode(fild, store_mode);
2559 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2565 * Crete a conversion from one integer mode into another one
2567 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2568 dbg_info *dbgi, ir_node *block, ir_node *op,
2571 ir_graph *irg = current_ir_graph;
2572 int src_bits = get_mode_size_bits(src_mode);
2573 int tgt_bits = get_mode_size_bits(tgt_mode);
2574 ir_node *new_block = be_transform_node(block);
2575 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2578 ir_mode *smaller_mode;
2580 ia32_address_mode_t am;
2581 ia32_address_t *addr = &am.addr;
2583 if (src_bits < tgt_bits) {
2584 smaller_mode = src_mode;
2585 smaller_bits = src_bits;
2587 smaller_mode = tgt_mode;
2588 smaller_bits = tgt_bits;
2591 memset(&am, 0, sizeof(am));
2592 if(use_source_address_mode(block, op, NULL)) {
2593 build_address(&am, op);
2595 am.op_type = ia32_AddrModeS;
2597 new_op = be_transform_node(op);
2598 am.op_type = ia32_Normal;
2600 if(addr->base == NULL)
2602 if(addr->index == NULL)
2603 addr->index = noreg;
2604 if(addr->mem == NULL)
2605 addr->mem = new_NoMem();
2607 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2608 if (smaller_bits == 8) {
2609 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2610 addr->index, addr->mem, new_op,
2613 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2614 addr->index, addr->mem, new_op,
2618 set_am_attributes(res, &am);
2619 set_ia32_ls_mode(res, smaller_mode);
2620 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2621 res = fix_mem_proj(res, &am);
2627 * Transforms a Conv node.
2629 * @return The created ia32 Conv node
2631 static ir_node *gen_Conv(ir_node *node) {
2632 ir_node *block = get_nodes_block(node);
2633 ir_node *new_block = be_transform_node(block);
2634 ir_node *op = get_Conv_op(node);
2635 ir_node *new_op = NULL;
2636 ir_graph *irg = current_ir_graph;
2637 dbg_info *dbgi = get_irn_dbg_info(node);
2638 ir_mode *src_mode = get_irn_mode(op);
2639 ir_mode *tgt_mode = get_irn_mode(node);
2640 int src_bits = get_mode_size_bits(src_mode);
2641 int tgt_bits = get_mode_size_bits(tgt_mode);
2642 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2643 ir_node *nomem = new_rd_NoMem(irg);
2644 ir_node *res = NULL;
2646 if (src_mode == mode_b) {
2647 assert(mode_is_int(tgt_mode));
2648 /* nothing to do, we already model bools as 0/1 ints */
2649 return be_transform_node(op);
2652 if (src_mode == tgt_mode) {
2653 if (get_Conv_strict(node)) {
2654 if (USE_SSE2(env_cg)) {
2655 /* when we are in SSE mode, we can kill all strict no-op conversion */
2656 return be_transform_node(op);
2659 /* this should be optimized already, but who knows... */
2660 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2661 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2662 return be_transform_node(op);
2666 if (mode_is_float(src_mode)) {
2667 new_op = be_transform_node(op);
2668 /* we convert from float ... */
2669 if (mode_is_float(tgt_mode)) {
2670 if(src_mode == mode_E && tgt_mode == mode_D
2671 && !get_Conv_strict(node)) {
2672 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2677 if (USE_SSE2(env_cg)) {
2678 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2679 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2681 set_ia32_ls_mode(res, tgt_mode);
2683 if(get_Conv_strict(node)) {
2684 res = gen_x87_strict_conv(tgt_mode, new_op);
2685 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2688 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2693 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2694 if (USE_SSE2(env_cg)) {
2695 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2697 set_ia32_ls_mode(res, src_mode);
2699 return gen_x87_fp_to_gp(node);
2703 /* we convert from int ... */
2704 if (mode_is_float(tgt_mode)) {
2706 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2707 if (USE_SSE2(env_cg)) {
2708 new_op = be_transform_node(op);
2709 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2711 set_ia32_ls_mode(res, tgt_mode);
2713 res = gen_x87_gp_to_fp(node, src_mode);
2714 if(get_Conv_strict(node)) {
2715 res = gen_x87_strict_conv(tgt_mode, res);
2716 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2717 ia32_get_old_node_name(env_cg, node));
2721 } else if(tgt_mode == mode_b) {
2722 /* mode_b lowering already took care that we only have 0/1 values */
2723 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2724 src_mode, tgt_mode));
2725 return be_transform_node(op);
2728 if (src_bits == tgt_bits) {
2729 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2730 src_mode, tgt_mode));
2731 return be_transform_node(op);
2734 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2743 int check_immediate_constraint(long val, char immediate_constraint_type)
2745 switch (immediate_constraint_type) {
2749 return val >= 0 && val <= 32;
2751 return val >= 0 && val <= 63;
2753 return val >= -128 && val <= 127;
2755 return val == 0xff || val == 0xffff;
2757 return val >= 0 && val <= 3;
2759 return val >= 0 && val <= 255;
2761 return val >= 0 && val <= 127;
2765 panic("Invalid immediate constraint found");
2770 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2773 tarval *offset = NULL;
2774 int offset_sign = 0;
2776 ir_entity *symconst_ent = NULL;
2777 int symconst_sign = 0;
2779 ir_node *cnst = NULL;
2780 ir_node *symconst = NULL;
2786 mode = get_irn_mode(node);
2787 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2791 if(is_Minus(node)) {
2793 node = get_Minus_op(node);
2796 if(is_Const(node)) {
2799 offset_sign = minus;
2800 } else if(is_SymConst(node)) {
2803 symconst_sign = minus;
2804 } else if(is_Add(node)) {
2805 ir_node *left = get_Add_left(node);
2806 ir_node *right = get_Add_right(node);
2807 if(is_Const(left) && is_SymConst(right)) {
2810 symconst_sign = minus;
2811 offset_sign = minus;
2812 } else if(is_SymConst(left) && is_Const(right)) {
2815 symconst_sign = minus;
2816 offset_sign = minus;
2818 } else if(is_Sub(node)) {
2819 ir_node *left = get_Sub_left(node);
2820 ir_node *right = get_Sub_right(node);
2821 if(is_Const(left) && is_SymConst(right)) {
2824 symconst_sign = !minus;
2825 offset_sign = minus;
2826 } else if(is_SymConst(left) && is_Const(right)) {
2829 symconst_sign = minus;
2830 offset_sign = !minus;
2837 offset = get_Const_tarval(cnst);
2838 if(tarval_is_long(offset)) {
2839 val = get_tarval_long(offset);
2840 } else if(tarval_is_null(offset)) {
2843 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2848 if(!check_immediate_constraint(val, immediate_constraint_type))
2851 if(symconst != NULL) {
2852 if(immediate_constraint_type != 0) {
2853 /* we need full 32bits for symconsts */
2857 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2859 symconst_ent = get_SymConst_entity(symconst);
2861 if(cnst == NULL && symconst == NULL)
2864 if(offset_sign && offset != NULL) {
2865 offset = tarval_neg(offset);
2868 irg = current_ir_graph;
2869 dbgi = get_irn_dbg_info(node);
2870 block = get_irg_start_block(irg);
2871 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2872 symconst_sign, val);
2873 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2879 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2881 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2882 if (new_node == NULL) {
2883 new_node = be_transform_node(node);
2888 typedef struct constraint_t constraint_t;
2889 struct constraint_t {
2892 const arch_register_req_t **out_reqs;
2894 const arch_register_req_t *req;
2895 unsigned immediate_possible;
2896 char immediate_type;
2899 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2901 int immediate_possible = 0;
2902 char immediate_type = 0;
2903 unsigned limited = 0;
2904 const arch_register_class_t *cls = NULL;
2905 ir_graph *irg = current_ir_graph;
2906 struct obstack *obst = get_irg_obstack(irg);
2907 arch_register_req_t *req;
2908 unsigned *limited_ptr;
2912 /* TODO: replace all the asserts with nice error messages */
2914 printf("Constraint: %s\n", c);
2924 assert(cls == NULL ||
2925 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2926 cls = &ia32_reg_classes[CLASS_ia32_gp];
2927 limited |= 1 << REG_EAX;
2930 assert(cls == NULL ||
2931 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2932 cls = &ia32_reg_classes[CLASS_ia32_gp];
2933 limited |= 1 << REG_EBX;
2936 assert(cls == NULL ||
2937 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2938 cls = &ia32_reg_classes[CLASS_ia32_gp];
2939 limited |= 1 << REG_ECX;
2942 assert(cls == NULL ||
2943 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2944 cls = &ia32_reg_classes[CLASS_ia32_gp];
2945 limited |= 1 << REG_EDX;
2948 assert(cls == NULL ||
2949 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2950 cls = &ia32_reg_classes[CLASS_ia32_gp];
2951 limited |= 1 << REG_EDI;
2954 assert(cls == NULL ||
2955 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2956 cls = &ia32_reg_classes[CLASS_ia32_gp];
2957 limited |= 1 << REG_ESI;
2960 case 'q': /* q means lower part of the regs only, this makes no
2961 * difference to Q for us (we only assigne whole registers) */
2962 assert(cls == NULL ||
2963 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2964 cls = &ia32_reg_classes[CLASS_ia32_gp];
2965 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2969 assert(cls == NULL ||
2970 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2971 cls = &ia32_reg_classes[CLASS_ia32_gp];
2972 limited |= 1 << REG_EAX | 1 << REG_EDX;
2975 assert(cls == NULL ||
2976 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2977 cls = &ia32_reg_classes[CLASS_ia32_gp];
2978 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2979 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2986 assert(cls == NULL);
2987 cls = &ia32_reg_classes[CLASS_ia32_gp];
2993 /* TODO: mark values so the x87 simulator knows about t and u */
2994 assert(cls == NULL);
2995 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3000 assert(cls == NULL);
3001 /* TODO: check that sse2 is supported */
3002 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3012 assert(!immediate_possible);
3013 immediate_possible = 1;
3014 immediate_type = *c;
3018 assert(!immediate_possible);
3019 immediate_possible = 1;
3023 assert(!immediate_possible && cls == NULL);
3024 immediate_possible = 1;
3025 cls = &ia32_reg_classes[CLASS_ia32_gp];
3038 assert(constraint->is_in && "can only specify same constraint "
3041 sscanf(c, "%d%n", &same_as, &p);
3048 case 'E': /* no float consts yet */
3049 case 'F': /* no float consts yet */
3050 case 's': /* makes no sense on x86 */
3051 case 'X': /* we can't support that in firm */
3055 case '<': /* no autodecrement on x86 */
3056 case '>': /* no autoincrement on x86 */
3057 case 'C': /* sse constant not supported yet */
3058 case 'G': /* 80387 constant not supported yet */
3059 case 'y': /* we don't support mmx registers yet */
3060 case 'Z': /* not available in 32 bit mode */
3061 case 'e': /* not available in 32 bit mode */
3062 assert(0 && "asm constraint not supported");
3065 assert(0 && "unknown asm constraint found");
3072 const arch_register_req_t *other_constr;
3074 assert(cls == NULL && "same as and register constraint not supported");
3075 assert(!immediate_possible && "same as and immediate constraint not "
3077 assert(same_as < constraint->n_outs && "wrong constraint number in "
3078 "same_as constraint");
3080 other_constr = constraint->out_reqs[same_as];
3082 req = obstack_alloc(obst, sizeof(req[0]));
3083 req->cls = other_constr->cls;
3084 req->type = arch_register_req_type_should_be_same;
3085 req->limited = NULL;
3086 req->other_same = pos;
3087 req->other_different = -1;
3089 /* switch constraints. This is because in firm we have same_as
3090 * constraints on the output constraints while in the gcc asm syntax
3091 * they are specified on the input constraints */
3092 constraint->req = other_constr;
3093 constraint->out_reqs[same_as] = req;
3094 constraint->immediate_possible = 0;
3098 if(immediate_possible && cls == NULL) {
3099 cls = &ia32_reg_classes[CLASS_ia32_gp];
3101 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3102 assert(cls != NULL);
3104 if(immediate_possible) {
3105 assert(constraint->is_in
3106 && "imeediates make no sense for output constraints");
3108 /* todo: check types (no float input on 'r' constrained in and such... */
3111 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3112 limited_ptr = (unsigned*) (req+1);
3114 req = obstack_alloc(obst, sizeof(req[0]));
3116 memset(req, 0, sizeof(req[0]));
3119 req->type = arch_register_req_type_limited;
3120 *limited_ptr = limited;
3121 req->limited = limited_ptr;
3123 req->type = arch_register_req_type_normal;
3127 constraint->req = req;
3128 constraint->immediate_possible = immediate_possible;
3129 constraint->immediate_type = immediate_type;
3133 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3140 panic("Clobbers not supported yet");
3144 * generates code for a ASM node
3146 static ir_node *gen_ASM(ir_node *node)
3149 ir_graph *irg = current_ir_graph;
3150 ir_node *block = be_transform_node(get_nodes_block(node));
3151 dbg_info *dbgi = get_irn_dbg_info(node);
3158 ia32_asm_attr_t *attr;
3159 const arch_register_req_t **out_reqs;
3160 const arch_register_req_t **in_reqs;
3161 struct obstack *obst;
3162 constraint_t parsed_constraint;
3164 /* transform inputs */
3165 arity = get_irn_arity(node);
3166 in = alloca(arity * sizeof(in[0]));
3167 memset(in, 0, arity * sizeof(in[0]));
3169 n_outs = get_ASM_n_output_constraints(node);
3170 n_clobbers = get_ASM_n_clobbers(node);
3171 out_arity = n_outs + n_clobbers;
3173 /* construct register constraints */
3174 obst = get_irg_obstack(irg);
3175 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3176 parsed_constraint.out_reqs = out_reqs;
3177 parsed_constraint.n_outs = n_outs;
3178 parsed_constraint.is_in = 0;
3179 for(i = 0; i < out_arity; ++i) {
3183 const ir_asm_constraint *constraint;
3184 constraint = & get_ASM_output_constraints(node) [i];
3185 c = get_id_str(constraint->constraint);
3186 parse_asm_constraint(i, &parsed_constraint, c);
3188 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3189 c = get_id_str(glob_id);
3190 parse_clobber(node, i, &parsed_constraint, c);
3192 out_reqs[i] = parsed_constraint.req;
3195 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3196 parsed_constraint.is_in = 1;
3197 for(i = 0; i < arity; ++i) {
3198 const ir_asm_constraint *constraint;
3202 constraint = & get_ASM_input_constraints(node) [i];
3203 constr_id = constraint->constraint;
3204 c = get_id_str(constr_id);
3205 parse_asm_constraint(i, &parsed_constraint, c);
3206 in_reqs[i] = parsed_constraint.req;
3208 if(parsed_constraint.immediate_possible) {
3209 ir_node *pred = get_irn_n(node, i);
3210 char imm_type = parsed_constraint.immediate_type;
3211 ir_node *immediate = try_create_Immediate(pred, imm_type);
3213 if(immediate != NULL) {
3219 /* transform inputs */
3220 for(i = 0; i < arity; ++i) {
3222 ir_node *transformed;
3227 pred = get_irn_n(node, i);
3228 transformed = be_transform_node(pred);
3229 in[i] = transformed;
3232 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3234 generic_attr = get_irn_generic_attr(res);
3235 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3236 attr->asm_text = get_ASM_text(node);
3237 set_ia32_out_req_all(res, out_reqs);
3238 set_ia32_in_req_all(res, in_reqs);
3240 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3245 /********************************************
3248 * | |__ ___ _ __ ___ __| | ___ ___
3249 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3250 * | |_) | __/ | | | (_) | (_| | __/\__ \
3251 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3253 ********************************************/
3256 * Transforms a FrameAddr into an ia32 Add.
3258 static ir_node *gen_be_FrameAddr(ir_node *node) {
3259 ir_node *block = be_transform_node(get_nodes_block(node));
3260 ir_node *op = be_get_FrameAddr_frame(node);
3261 ir_node *new_op = be_transform_node(op);
3262 ir_graph *irg = current_ir_graph;
3263 dbg_info *dbgi = get_irn_dbg_info(node);
3264 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3267 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3268 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3269 set_ia32_use_frame(res);
3271 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3277 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3279 static ir_node *gen_be_Return(ir_node *node) {
3280 ir_graph *irg = current_ir_graph;
3281 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3282 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3283 ir_entity *ent = get_irg_entity(irg);
3284 ir_type *tp = get_entity_type(ent);
3289 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3290 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3293 int pn_ret_val, pn_ret_mem, arity, i;
3295 assert(ret_val != NULL);
3296 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3297 return be_duplicate_node(node);
3300 res_type = get_method_res_type(tp, 0);
3302 if (! is_Primitive_type(res_type)) {
3303 return be_duplicate_node(node);
3306 mode = get_type_mode(res_type);
3307 if (! mode_is_float(mode)) {
3308 return be_duplicate_node(node);
3311 assert(get_method_n_ress(tp) == 1);
3313 pn_ret_val = get_Proj_proj(ret_val);
3314 pn_ret_mem = get_Proj_proj(ret_mem);
3316 /* get the Barrier */
3317 barrier = get_Proj_pred(ret_val);
3319 /* get result input of the Barrier */
3320 ret_val = get_irn_n(barrier, pn_ret_val);
3321 new_ret_val = be_transform_node(ret_val);
3323 /* get memory input of the Barrier */
3324 ret_mem = get_irn_n(barrier, pn_ret_mem);
3325 new_ret_mem = be_transform_node(ret_mem);
3327 frame = get_irg_frame(irg);
3329 dbgi = get_irn_dbg_info(barrier);
3330 block = be_transform_node(get_nodes_block(barrier));
3332 noreg = ia32_new_NoReg_gp(env_cg);
3334 /* store xmm0 onto stack */
3335 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3336 new_ret_mem, new_ret_val);
3337 set_ia32_ls_mode(sse_store, mode);
3338 set_ia32_op_type(sse_store, ia32_AddrModeD);
3339 set_ia32_use_frame(sse_store);
3341 /* load into x87 register */
3342 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3343 set_ia32_op_type(fld, ia32_AddrModeS);
3344 set_ia32_use_frame(fld);
3346 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3347 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3349 /* create a new barrier */
3350 arity = get_irn_arity(barrier);
3351 in = alloca(arity * sizeof(in[0]));
3352 for (i = 0; i < arity; ++i) {
3355 if (i == pn_ret_val) {
3357 } else if (i == pn_ret_mem) {
3360 ir_node *in = get_irn_n(barrier, i);
3361 new_in = be_transform_node(in);
3366 new_barrier = new_ir_node(dbgi, irg, block,
3367 get_irn_op(barrier), get_irn_mode(barrier),
3369 copy_node_attr(barrier, new_barrier);
3370 be_duplicate_deps(barrier, new_barrier);
3371 be_set_transformed_node(barrier, new_barrier);
3372 mark_irn_visited(barrier);
3374 /* transform normally */
3375 return be_duplicate_node(node);
3379 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3381 static ir_node *gen_be_AddSP(ir_node *node) {
3382 ir_node *block = be_transform_node(get_nodes_block(node));
3383 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3385 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3386 ir_node *new_sp = be_transform_node(sp);
3387 ir_graph *irg = current_ir_graph;
3388 dbg_info *dbgi = get_irn_dbg_info(node);
3389 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3390 ir_node *nomem = new_NoMem();
3393 new_sz = create_immediate_or_transform(sz, 0);
3395 /* ia32 stack grows in reverse direction, make a SubSP */
3396 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3398 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3404 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3406 static ir_node *gen_be_SubSP(ir_node *node) {
3407 ir_node *block = be_transform_node(get_nodes_block(node));
3408 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3410 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3411 ir_node *new_sp = be_transform_node(sp);
3412 ir_graph *irg = current_ir_graph;
3413 dbg_info *dbgi = get_irn_dbg_info(node);
3414 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3415 ir_node *nomem = new_NoMem();
3418 new_sz = create_immediate_or_transform(sz, 0);
3420 /* ia32 stack grows in reverse direction, make an AddSP */
3421 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3423 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3429 * This function just sets the register for the Unknown node
3430 * as this is not done during register allocation because Unknown
3431 * is an "ignore" node.
3433 static ir_node *gen_Unknown(ir_node *node) {
3434 ir_mode *mode = get_irn_mode(node);
3436 if (mode_is_float(mode)) {
3437 if (USE_SSE2(env_cg)) {
3438 return ia32_new_Unknown_xmm(env_cg);
3440 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3441 ir_graph *irg = current_ir_graph;
3442 dbg_info *dbgi = get_irn_dbg_info(node);
3443 ir_node *block = get_irg_start_block(irg);
3444 return new_rd_ia32_vfldz(dbgi, irg, block);
3446 } else if (mode_needs_gp_reg(mode)) {
3447 return ia32_new_Unknown_gp(env_cg);
3449 assert(0 && "unsupported Unknown-Mode");
3456 * Change some phi modes
3458 static ir_node *gen_Phi(ir_node *node) {
3459 ir_node *block = be_transform_node(get_nodes_block(node));
3460 ir_graph *irg = current_ir_graph;
3461 dbg_info *dbgi = get_irn_dbg_info(node);
3462 ir_mode *mode = get_irn_mode(node);
3465 if(mode_needs_gp_reg(mode)) {
3466 /* we shouldn't have any 64bit stuff around anymore */
3467 assert(get_mode_size_bits(mode) <= 32);
3468 /* all integer operations are on 32bit registers now */
3470 } else if(mode_is_float(mode)) {
3471 if (USE_SSE2(env_cg)) {
3478 /* phi nodes allow loops, so we use the old arguments for now
3479 * and fix this later */
3480 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3481 get_irn_in(node) + 1);
3482 copy_node_attr(node, phi);
3483 be_duplicate_deps(node, phi);
3485 be_set_transformed_node(node, phi);
3486 be_enqueue_preds(node);
3494 static ir_node *gen_IJmp(ir_node *node) {
3495 /* TODO: support AM */
3496 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3500 /**********************************************************************
3503 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3504 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3505 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3506 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3508 **********************************************************************/
3510 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3512 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3515 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3516 ir_node *val, ir_node *mem);
3519 * Transforms a lowered Load into a "real" one.
3521 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3523 ir_node *block = be_transform_node(get_nodes_block(node));
3524 ir_node *ptr = get_irn_n(node, 0);
3525 ir_node *new_ptr = be_transform_node(ptr);
3526 ir_node *mem = get_irn_n(node, 1);
3527 ir_node *new_mem = be_transform_node(mem);
3528 ir_graph *irg = current_ir_graph;
3529 dbg_info *dbgi = get_irn_dbg_info(node);
3530 ir_mode *mode = get_ia32_ls_mode(node);
3531 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3534 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3536 set_ia32_op_type(new_op, ia32_AddrModeS);
3537 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3538 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3539 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3540 if (is_ia32_am_sc_sign(node))
3541 set_ia32_am_sc_sign(new_op);
3542 set_ia32_ls_mode(new_op, mode);
3543 if (is_ia32_use_frame(node)) {
3544 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3545 set_ia32_use_frame(new_op);
3548 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3554 * Transforms a lowered Store into a "real" one.
3556 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3558 ir_node *block = be_transform_node(get_nodes_block(node));
3559 ir_node *ptr = get_irn_n(node, 0);
3560 ir_node *new_ptr = be_transform_node(ptr);
3561 ir_node *val = get_irn_n(node, 1);
3562 ir_node *new_val = be_transform_node(val);
3563 ir_node *mem = get_irn_n(node, 2);
3564 ir_node *new_mem = be_transform_node(mem);
3565 ir_graph *irg = current_ir_graph;
3566 dbg_info *dbgi = get_irn_dbg_info(node);
3567 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3568 ir_mode *mode = get_ia32_ls_mode(node);
3572 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3574 am_offs = get_ia32_am_offs_int(node);
3575 add_ia32_am_offs_int(new_op, am_offs);
3577 set_ia32_op_type(new_op, ia32_AddrModeD);
3578 set_ia32_ls_mode(new_op, mode);
3579 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3580 set_ia32_use_frame(new_op);
3582 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3589 * Transforms an ia32_l_XXX into a "real" XXX node
3591 * @param node The node to transform
3592 * @return the created ia32 XXX node
3594 #define GEN_LOWERED_OP(op) \
3595 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3596 return gen_binop(node, get_binop_left(node), \
3597 get_binop_right(node), new_rd_ia32_##op,0); \
3600 #define GEN_LOWERED_x87_OP(op) \
3601 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3603 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3604 get_binop_right(node), new_rd_ia32_##op); \
3608 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3609 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3610 return gen_shift_binop(node, get_irn_n(node, 0), \
3611 get_irn_n(node, 1), new_rd_ia32_##op); \
3614 GEN_LOWERED_x87_OP(vfprem)
3615 GEN_LOWERED_x87_OP(vfmul)
3616 GEN_LOWERED_x87_OP(vfsub)
3617 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3618 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3619 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3620 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3622 static ir_node *gen_ia32_l_Add(ir_node *node) {
3623 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3624 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3625 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3627 if(is_Proj(lowered)) {
3628 lowered = get_Proj_pred(lowered);
3630 assert(is_ia32_Add(lowered));
3631 set_irn_mode(lowered, mode_T);
3637 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3638 ir_node *src_block = get_nodes_block(node);
3639 ir_node *block = be_transform_node(src_block);
3640 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3641 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3642 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3643 ir_node *new_flags = be_transform_node(flags);
3644 ir_graph *irg = current_ir_graph;
3645 dbg_info *dbgi = get_irn_dbg_info(node);
3647 ia32_address_mode_t am;
3648 ia32_address_t *addr = &am.addr;
3650 match_arguments(&am, src_block, op1, op2, 1, 0, 1, 0);
3652 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3653 addr->mem, am.new_op1, am.new_op2, new_flags);
3654 set_am_attributes(new_node, &am);
3655 /* we can't use source address mode anymore when using immediates */
3656 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3657 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3658 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3660 new_node = fix_mem_proj(new_node, &am);
3666 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3668 * @param node The node to transform
3669 * @return the created ia32 Neg node
3671 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3672 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3676 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3678 * @param node The node to transform
3679 * @return the created ia32 vfild node
3681 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3682 return gen_lowered_Load(node, new_rd_ia32_vfild);
3686 * Transforms an ia32_l_Load into a "real" ia32_Load node
3688 * @param node The node to transform
3689 * @return the created ia32 Load node
3691 static ir_node *gen_ia32_l_Load(ir_node *node) {
3692 return gen_lowered_Load(node, new_rd_ia32_Load);
3696 * Transforms an ia32_l_Store into a "real" ia32_Store node
3698 * @param node The node to transform
3699 * @return the created ia32 Store node
3701 static ir_node *gen_ia32_l_Store(ir_node *node) {
3702 return gen_lowered_Store(node, new_rd_ia32_Store);
3706 * Transforms a l_vfist into a "real" vfist node.
3708 * @param node The node to transform
3709 * @return the created ia32 vfist node
3711 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3712 ir_node *block = be_transform_node(get_nodes_block(node));
3713 ir_node *ptr = get_irn_n(node, 0);
3714 ir_node *new_ptr = be_transform_node(ptr);
3715 ir_node *val = get_irn_n(node, 1);
3716 ir_node *new_val = be_transform_node(val);
3717 ir_node *mem = get_irn_n(node, 2);
3718 ir_node *new_mem = be_transform_node(mem);
3719 ir_graph *irg = current_ir_graph;
3720 dbg_info *dbgi = get_irn_dbg_info(node);
3721 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3722 ir_mode *mode = get_ia32_ls_mode(node);
3723 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3727 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3728 new_val, trunc_mode);
3730 am_offs = get_ia32_am_offs_int(node);
3731 add_ia32_am_offs_int(new_op, am_offs);
3733 set_ia32_op_type(new_op, ia32_AddrModeD);
3734 set_ia32_ls_mode(new_op, mode);
3735 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3736 set_ia32_use_frame(new_op);
3738 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3744 * Transforms a l_vfdiv into a "real" vfdiv node.
3746 * @param env The transformation environment
3747 * @return the created ia32 vfdiv node
3749 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3750 ir_node *block = be_transform_node(get_nodes_block(node));
3751 ir_node *left = get_binop_left(node);
3752 ir_node *new_left = be_transform_node(left);
3753 ir_node *right = get_binop_right(node);
3754 ir_node *new_right = be_transform_node(right);
3755 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3756 ir_graph *irg = current_ir_graph;
3757 dbg_info *dbgi = get_irn_dbg_info(node);
3758 ir_node *fpcw = get_fpcw();
3761 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3762 new_left, new_right, fpcw);
3763 clear_ia32_commutative(vfdiv);
3765 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3771 * Transforms a l_MulS into a "real" MulS node.
3773 * @param env The transformation environment
3774 * @return the created ia32 Mul node
3776 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3777 ir_node *block = be_transform_node(get_nodes_block(node));
3778 ir_node *left = get_binop_left(node);
3779 ir_node *new_left = be_transform_node(left);
3780 ir_node *right = get_binop_right(node);
3781 ir_node *new_right = be_transform_node(right);
3782 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3783 ir_graph *irg = current_ir_graph;
3784 dbg_info *dbgi = get_irn_dbg_info(node);
3786 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3787 /* and then skip the result Proj, because all needed Projs are already there. */
3788 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3789 new_left, new_right);
3790 clear_ia32_commutative(muls);
3792 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3798 * Transforms a l_IMulS into a "real" IMul1OPS node.
3800 * @param env The transformation environment
3801 * @return the created ia32 IMul1OP node
3803 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3804 ir_node *block = be_transform_node(get_nodes_block(node));
3805 ir_node *left = get_binop_left(node);
3806 ir_node *new_left = be_transform_node(left);
3807 ir_node *right = get_binop_right(node);
3808 ir_node *new_right = be_transform_node(right);
3809 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3810 ir_graph *irg = current_ir_graph;
3811 dbg_info *dbgi = get_irn_dbg_info(node);
3813 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3814 /* and then skip the result Proj, because all needed Projs are already there. */
3815 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3816 new_NoMem(), new_left, new_right);
3817 clear_ia32_commutative(muls);
3819 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3824 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3826 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3827 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3828 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3829 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3830 ir_node *block = be_transform_node(get_nodes_block(node));
3831 dbg_info *dbgi = get_irn_dbg_info(node);
3832 ir_graph *irg = current_ir_graph;
3833 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3834 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3838 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3840 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3841 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3842 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3843 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3844 ir_node *block = be_transform_node(get_nodes_block(node));
3845 dbg_info *dbgi = get_irn_dbg_info(node);
3846 ir_graph *irg = current_ir_graph;
3847 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3848 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3853 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3854 * op1 - target to be shifted
3855 * op2 - contains bits to be shifted into target
3857 * Only op3 can be an immediate.
3859 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3860 ir_node *op2, ir_node *count)
3862 ir_node *block = be_transform_node(get_nodes_block(node));
3863 ir_node *new_op = NULL;
3864 ir_graph *irg = current_ir_graph;
3865 dbg_info *dbgi = get_irn_dbg_info(node);
3866 ir_node *new_op1 = be_transform_node(op1);
3867 ir_node *new_op2 = be_transform_node(op2);
3868 ir_node *new_count = create_immediate_or_transform(count, 'I');
3870 /* TODO proper AM support */
3872 if (is_ia32_l_ShlD(node))
3873 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3875 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3877 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3882 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3883 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3884 get_irn_n(node, 1), get_irn_n(node, 2));
3887 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3888 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3889 get_irn_n(node, 1), get_irn_n(node, 2));
3893 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3895 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3896 ir_node *block = be_transform_node(get_nodes_block(node));
3897 ir_node *val = get_irn_n(node, 1);
3898 ir_node *new_val = be_transform_node(val);
3899 ia32_code_gen_t *cg = env_cg;
3900 ir_node *res = NULL;
3901 ir_graph *irg = current_ir_graph;
3903 ir_node *noreg, *new_ptr, *new_mem;
3910 mem = get_irn_n(node, 2);
3911 new_mem = be_transform_node(mem);
3912 ptr = get_irn_n(node, 0);
3913 new_ptr = be_transform_node(ptr);
3914 noreg = ia32_new_NoReg_gp(cg);
3915 dbgi = get_irn_dbg_info(node);
3917 /* Store x87 -> MEM */
3918 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3919 get_ia32_ls_mode(node));
3920 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3921 set_ia32_use_frame(res);
3922 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3923 set_ia32_op_type(res, ia32_AddrModeD);
3925 /* Load MEM -> SSE */
3926 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3927 get_ia32_ls_mode(node));
3928 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3929 set_ia32_use_frame(res);
3930 set_ia32_op_type(res, ia32_AddrModeS);
3931 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3937 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3939 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3940 ir_node *block = be_transform_node(get_nodes_block(node));
3941 ir_node *val = get_irn_n(node, 1);
3942 ir_node *new_val = be_transform_node(val);
3943 ia32_code_gen_t *cg = env_cg;
3944 ir_graph *irg = current_ir_graph;
3945 ir_node *res = NULL;
3946 ir_entity *fent = get_ia32_frame_ent(node);
3947 ir_mode *lsmode = get_ia32_ls_mode(node);
3949 ir_node *noreg, *new_ptr, *new_mem;
3953 if (! USE_SSE2(cg)) {
3954 /* SSE unit is not used -> skip this node. */
3958 ptr = get_irn_n(node, 0);
3959 new_ptr = be_transform_node(ptr);
3960 mem = get_irn_n(node, 2);
3961 new_mem = be_transform_node(mem);
3962 noreg = ia32_new_NoReg_gp(cg);
3963 dbgi = get_irn_dbg_info(node);
3965 /* Store SSE -> MEM */
3966 if (is_ia32_xLoad(skip_Proj(new_val))) {
3967 ir_node *ld = skip_Proj(new_val);
3969 /* we can vfld the value directly into the fpu */
3970 fent = get_ia32_frame_ent(ld);
3971 ptr = get_irn_n(ld, 0);
3972 offs = get_ia32_am_offs_int(ld);
3974 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3976 set_ia32_frame_ent(res, fent);
3977 set_ia32_use_frame(res);
3978 set_ia32_ls_mode(res, lsmode);
3979 set_ia32_op_type(res, ia32_AddrModeD);
3983 /* Load MEM -> x87 */
3984 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3985 set_ia32_frame_ent(res, fent);
3986 set_ia32_use_frame(res);
3987 add_ia32_am_offs_int(res, offs);
3988 set_ia32_op_type(res, ia32_AddrModeS);
3989 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3994 /*********************************************************
3997 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3998 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3999 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4000 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4002 *********************************************************/
4005 * the BAD transformer.
4007 static ir_node *bad_transform(ir_node *node) {
4008 panic("No transform function for %+F available.\n", node);
4013 * Transform the Projs of an AddSP.
4015 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4016 ir_node *block = be_transform_node(get_nodes_block(node));
4017 ir_node *pred = get_Proj_pred(node);
4018 ir_node *new_pred = be_transform_node(pred);
4019 ir_graph *irg = current_ir_graph;
4020 dbg_info *dbgi = get_irn_dbg_info(node);
4021 long proj = get_Proj_proj(node);
4023 if (proj == pn_be_AddSP_sp) {
4024 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4025 pn_ia32_SubSP_stack);
4026 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4028 } else if(proj == pn_be_AddSP_res) {
4029 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4030 pn_ia32_SubSP_addr);
4031 } else if (proj == pn_be_AddSP_M) {
4032 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4036 return new_rd_Unknown(irg, get_irn_mode(node));
4040 * Transform the Projs of a SubSP.
4042 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4043 ir_node *block = be_transform_node(get_nodes_block(node));
4044 ir_node *pred = get_Proj_pred(node);
4045 ir_node *new_pred = be_transform_node(pred);
4046 ir_graph *irg = current_ir_graph;
4047 dbg_info *dbgi = get_irn_dbg_info(node);
4048 long proj = get_Proj_proj(node);
4050 if (proj == pn_be_SubSP_sp) {
4051 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4052 pn_ia32_AddSP_stack);
4053 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4055 } else if (proj == pn_be_SubSP_M) {
4056 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4060 return new_rd_Unknown(irg, get_irn_mode(node));
4064 * Transform and renumber the Projs from a Load.
4066 static ir_node *gen_Proj_Load(ir_node *node) {
4068 ir_node *block = be_transform_node(get_nodes_block(node));
4069 ir_node *pred = get_Proj_pred(node);
4070 ir_graph *irg = current_ir_graph;
4071 dbg_info *dbgi = get_irn_dbg_info(node);
4072 long proj = get_Proj_proj(node);
4075 /* loads might be part of source address mode matches, so we don't
4076 transform the ProjMs yet (with the exception of loads whose result is
4079 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4082 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4084 /* this is needed, because sometimes we have loops that are only
4085 reachable through the ProjM */
4086 be_enqueue_preds(node);
4087 /* do it in 2 steps, to silence firm verifier */
4088 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4089 set_Proj_proj(res, pn_ia32_Load_M);
4093 /* renumber the proj */
4094 new_pred = be_transform_node(pred);
4095 if (is_ia32_Load(new_pred)) {
4096 if (proj == pn_Load_res) {
4097 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4099 } else if (proj == pn_Load_M) {
4100 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4103 } else if(is_ia32_Conv_I2I(new_pred)) {
4104 set_irn_mode(new_pred, mode_T);
4105 if (proj == pn_Load_res) {
4106 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4107 } else if (proj == pn_Load_M) {
4108 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4110 } else if (is_ia32_xLoad(new_pred)) {
4111 if (proj == pn_Load_res) {
4112 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4114 } else if (proj == pn_Load_M) {
4115 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4118 } else if (is_ia32_vfld(new_pred)) {
4119 if (proj == pn_Load_res) {
4120 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4122 } else if (proj == pn_Load_M) {
4123 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4127 /* can happen for ProJMs when source address mode happened for the
4130 /* however it should not be the result proj, as that would mean the
4131 load had multiple users and should not have been used for
4133 if(proj != pn_Load_M) {
4134 panic("internal error: transformed node not a Load");
4136 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4140 return new_rd_Unknown(irg, get_irn_mode(node));
4144 * Transform and renumber the Projs from a DivMod like instruction.
4146 static ir_node *gen_Proj_DivMod(ir_node *node) {
4147 ir_node *block = be_transform_node(get_nodes_block(node));
4148 ir_node *pred = get_Proj_pred(node);
4149 ir_node *new_pred = be_transform_node(pred);
4150 ir_graph *irg = current_ir_graph;
4151 dbg_info *dbgi = get_irn_dbg_info(node);
4152 ir_mode *mode = get_irn_mode(node);
4153 long proj = get_Proj_proj(node);
4155 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4157 switch (get_irn_opcode(pred)) {
4161 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4163 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4171 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4173 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4181 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4182 case pn_DivMod_res_div:
4183 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4184 case pn_DivMod_res_mod:
4185 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4195 return new_rd_Unknown(irg, mode);
4199 * Transform and renumber the Projs from a CopyB.
4201 static ir_node *gen_Proj_CopyB(ir_node *node) {
4202 ir_node *block = be_transform_node(get_nodes_block(node));
4203 ir_node *pred = get_Proj_pred(node);
4204 ir_node *new_pred = be_transform_node(pred);
4205 ir_graph *irg = current_ir_graph;
4206 dbg_info *dbgi = get_irn_dbg_info(node);
4207 ir_mode *mode = get_irn_mode(node);
4208 long proj = get_Proj_proj(node);
4211 case pn_CopyB_M_regular:
4212 if (is_ia32_CopyB_i(new_pred)) {
4213 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4214 } else if (is_ia32_CopyB(new_pred)) {
4215 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4223 return new_rd_Unknown(irg, mode);
4227 * Transform and renumber the Projs from a vfdiv.
4229 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4230 ir_node *block = be_transform_node(get_nodes_block(node));
4231 ir_node *pred = get_Proj_pred(node);
4232 ir_node *new_pred = be_transform_node(pred);
4233 ir_graph *irg = current_ir_graph;
4234 dbg_info *dbgi = get_irn_dbg_info(node);
4235 ir_mode *mode = get_irn_mode(node);
4236 long proj = get_Proj_proj(node);
4239 case pn_ia32_l_vfdiv_M:
4240 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4241 case pn_ia32_l_vfdiv_res:
4242 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4247 return new_rd_Unknown(irg, mode);
4251 * Transform and renumber the Projs from a Quot.
4253 static ir_node *gen_Proj_Quot(ir_node *node) {
4254 ir_node *block = be_transform_node(get_nodes_block(node));
4255 ir_node *pred = get_Proj_pred(node);
4256 ir_node *new_pred = be_transform_node(pred);
4257 ir_graph *irg = current_ir_graph;
4258 dbg_info *dbgi = get_irn_dbg_info(node);
4259 ir_mode *mode = get_irn_mode(node);
4260 long proj = get_Proj_proj(node);
4264 if (is_ia32_xDiv(new_pred)) {
4265 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4266 } else if (is_ia32_vfdiv(new_pred)) {
4267 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4271 if (is_ia32_xDiv(new_pred)) {
4272 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4273 } else if (is_ia32_vfdiv(new_pred)) {
4274 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4282 return new_rd_Unknown(irg, mode);
4286 * Transform the Thread Local Storage Proj.
4288 static ir_node *gen_Proj_tls(ir_node *node) {
4289 ir_node *block = be_transform_node(get_nodes_block(node));
4290 ir_graph *irg = current_ir_graph;
4291 dbg_info *dbgi = NULL;
4292 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4298 * Transform the Projs from a be_Call.
4300 static ir_node *gen_Proj_be_Call(ir_node *node) {
4301 ir_node *block = be_transform_node(get_nodes_block(node));
4302 ir_node *call = get_Proj_pred(node);
4303 ir_node *new_call = be_transform_node(call);
4304 ir_graph *irg = current_ir_graph;
4305 dbg_info *dbgi = get_irn_dbg_info(node);
4306 ir_type *method_type = be_Call_get_type(call);
4307 int n_res = get_method_n_ress(method_type);
4308 long proj = get_Proj_proj(node);
4309 ir_mode *mode = get_irn_mode(node);
4311 const arch_register_class_t *cls;
4313 /* The following is kinda tricky: If we're using SSE, then we have to
4314 * move the result value of the call in floating point registers to an
4315 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4316 * after the call, we have to make sure to correctly make the
4317 * MemProj and the result Proj use these 2 nodes
4319 if (proj == pn_be_Call_M_regular) {
4320 // get new node for result, are we doing the sse load/store hack?
4321 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4322 ir_node *call_res_new;
4323 ir_node *call_res_pred = NULL;
4325 if (call_res != NULL) {
4326 call_res_new = be_transform_node(call_res);
4327 call_res_pred = get_Proj_pred(call_res_new);
4330 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4331 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4332 pn_be_Call_M_regular);
4334 assert(is_ia32_xLoad(call_res_pred));
4335 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4339 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4340 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4341 && USE_SSE2(env_cg)) {
4343 ir_node *frame = get_irg_frame(irg);
4344 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4346 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4349 /* in case there is no memory output: create one to serialize the copy
4351 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4352 pn_be_Call_M_regular);
4353 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4354 pn_be_Call_first_res);
4356 /* store st(0) onto stack */
4357 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4359 set_ia32_op_type(fstp, ia32_AddrModeD);
4360 set_ia32_use_frame(fstp);
4362 /* load into SSE register */
4363 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4365 set_ia32_op_type(sse_load, ia32_AddrModeS);
4366 set_ia32_use_frame(sse_load);
4368 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4374 /* transform call modes */
4375 if (mode_is_data(mode)) {
4376 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4380 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4384 * Transform the Projs from a Cmp.
4386 static ir_node *gen_Proj_Cmp(ir_node *node)
4388 /* normally Cmps are processed when looking at Cond nodes, but this case
4389 * can happen in complicated Psi conditions */
4391 ir_node *cmp = get_Proj_pred(node);
4392 long pnc = get_Proj_proj(node);
4393 ir_node *cmp_left = get_Cmp_left(cmp);
4394 ir_node *cmp_right = get_Cmp_right(cmp);
4395 ir_mode *cmp_mode = get_irn_mode(cmp_left);
4396 dbg_info *dbgi = get_irn_dbg_info(cmp);
4397 ir_node *block = get_nodes_block(node);
4401 assert(!mode_is_float(cmp_mode));
4403 if(!mode_is_signed(cmp_mode)) {
4404 pnc |= ia32_pn_Cmp_Unsigned;
4408 * address mode makes only sense when we'll be the only node using the cmp
4410 use_am = get_irn_n_edges(cmp) <= 1;
4412 res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
4413 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
4419 * Transform and potentially renumber Proj nodes.
4421 static ir_node *gen_Proj(ir_node *node) {
4422 ir_graph *irg = current_ir_graph;
4423 dbg_info *dbgi = get_irn_dbg_info(node);
4424 ir_node *pred = get_Proj_pred(node);
4425 long proj = get_Proj_proj(node);
4427 if (is_Store(pred)) {
4428 if (proj == pn_Store_M) {
4429 return be_transform_node(pred);
4432 return new_r_Bad(irg);
4434 } else if (is_Load(pred)) {
4435 return gen_Proj_Load(node);
4436 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4437 return gen_Proj_DivMod(node);
4438 } else if (is_CopyB(pred)) {
4439 return gen_Proj_CopyB(node);
4440 } else if (is_Quot(pred)) {
4441 return gen_Proj_Quot(node);
4442 } else if (is_ia32_l_vfdiv(pred)) {
4443 return gen_Proj_l_vfdiv(node);
4444 } else if (be_is_SubSP(pred)) {
4445 return gen_Proj_be_SubSP(node);
4446 } else if (be_is_AddSP(pred)) {
4447 return gen_Proj_be_AddSP(node);
4448 } else if (be_is_Call(pred)) {
4449 return gen_Proj_be_Call(node);
4450 } else if (is_Cmp(pred)) {
4451 return gen_Proj_Cmp(node);
4452 } else if (get_irn_op(pred) == op_Start) {
4453 if (proj == pn_Start_X_initial_exec) {
4454 ir_node *block = get_nodes_block(pred);
4457 /* we exchange the ProjX with a jump */
4458 block = be_transform_node(block);
4459 jump = new_rd_Jmp(dbgi, irg, block);
4462 if (node == be_get_old_anchor(anchor_tls)) {
4463 return gen_Proj_tls(node);
4466 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4470 ir_node *new_pred = be_transform_node(pred);
4471 ir_node *block = be_transform_node(get_nodes_block(node));
4472 ir_mode *mode = get_irn_mode(node);
4473 if (mode_needs_gp_reg(mode)) {
4474 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4475 get_Proj_proj(node));
4476 #ifdef DEBUG_libfirm
4477 new_proj->node_nr = node->node_nr;
4483 return be_duplicate_node(node);
4487 * Enters all transform functions into the generic pointer
4489 static void register_transformers(void)
4493 /* first clear the generic function pointer for all ops */
4494 clear_irp_opcodes_generic_func();
4496 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4497 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4534 /* transform ops from intrinsic lowering */
4556 GEN(ia32_l_X87toSSE);
4557 GEN(ia32_l_SSEtoX87);
4563 /* we should never see these nodes */
4578 /* handle generic backend nodes */
4586 op_Mulh = get_op_Mulh();
4595 * Pre-transform all unknown and noreg nodes.
4597 static void ia32_pretransform_node(void *arch_cg) {
4598 ia32_code_gen_t *cg = arch_cg;
4600 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4601 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4602 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4603 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4604 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4605 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4610 * Walker, checks if all ia32 nodes producing more than one result have
4611 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4614 void add_missing_keep_walker(ir_node *node, void *data)
4617 unsigned found_projs = 0;
4618 const ir_edge_t *edge;
4619 ir_mode *mode = get_irn_mode(node);
4624 if(!is_ia32_irn(node))
4627 n_outs = get_ia32_n_res(node);
4630 if(is_ia32_SwitchJmp(node))
4633 assert(n_outs < (int) sizeof(unsigned) * 8);
4634 foreach_out_edge(node, edge) {
4635 ir_node *proj = get_edge_src_irn(edge);
4636 int pn = get_Proj_proj(proj);
4638 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4639 found_projs |= 1 << pn;
4643 /* are keeps missing? */
4645 for(i = 0; i < n_outs; ++i) {
4648 const arch_register_req_t *req;
4649 const arch_register_class_t *class;
4651 if(found_projs & (1 << i)) {
4655 req = get_ia32_out_req(node, i);
4660 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4664 block = get_nodes_block(node);
4665 in[0] = new_r_Proj(current_ir_graph, block, node,
4666 arch_register_class_mode(class), i);
4667 if(last_keep != NULL) {
4668 be_Keep_add_node(last_keep, class, in[0]);
4670 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4671 if(sched_is_scheduled(node)) {
4672 sched_add_after(node, last_keep);
4679 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4682 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4684 ir_graph *irg = be_get_birg_irg(cg->birg);
4685 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4688 /* do the transformation */
4689 void ia32_transform_graph(ia32_code_gen_t *cg) {
4690 register_transformers();
4692 initial_fpcw = NULL;
4694 heights = heights_new(cg->irg);
4696 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4698 heights_free(heights);
4702 void ia32_init_transform(void)
4704 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");