18 #include "../benode_t.h"
19 #include "bearch_ia32_t.h"
21 #include "ia32_nodes_attr.h"
22 #include "../arch/archop.h" /* we need this for Min and Max nodes */
23 #include "ia32_transform.h"
24 #include "ia32_new_nodes.h"
26 #include "gen_ia32_regalloc_if.h"
28 #define SFP_SIGN "0x80000000"
29 #define DFP_SIGN "0x8000000000000000"
30 #define SFP_ABS "0x7FFFFFFF"
31 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
33 #define TP_SFP_SIGN "ia32_sfp_sign"
34 #define TP_DFP_SIGN "ia32_dfp_sign"
35 #define TP_SFP_ABS "ia32_sfp_abs"
36 #define TP_DFP_ABS "ia32_dfp_abs"
38 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
39 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
40 #define ENT_SFP_ABS "IA32_SFP_ABS"
41 #define ENT_DFP_ABS "IA32_DFP_ABS"
43 extern ir_op *get_op_Mulh(void);
45 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
46 ir_node *op1, ir_node *op2, ir_node *mem, ir_mode *mode);
48 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
49 ir_node *op, ir_node *mem, ir_mode *mode);
52 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
55 /****************************************************************************************************
57 * | | | | / _| | | (_)
58 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
59 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
60 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
61 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
63 ****************************************************************************************************/
70 /* Compares two (entity, tarval) combinations */
71 static int cmp_tv_ent(const void *a, const void *b, size_t len) {
72 const struct tv_ent *e1 = a;
73 const struct tv_ent *e2 = b;
75 return !(e1->tv == e2->tv);
78 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
79 static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
80 static set *const_set = NULL;
92 const_set = new_set(cmp_tv_ent, 10);
97 tp_name = TP_SFP_SIGN;
98 ent_name = ENT_SFP_SIGN;
102 tp_name = TP_DFP_SIGN;
103 ent_name = ENT_DFP_SIGN;
107 tp_name = TP_SFP_ABS;
108 ent_name = ENT_SFP_ABS;
112 tp_name = TP_DFP_ABS;
113 ent_name = ENT_DFP_ABS;
119 key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
122 entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
125 tp = new_type_primitive(new_id_from_str(tp_name), mode);
126 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
128 set_entity_ld_ident(ent, get_entity_ident(ent));
129 set_entity_visibility(ent, visibility_local);
130 set_entity_variability(ent, variability_constant);
131 set_entity_allocation(ent, allocation_static);
133 /* we create a new entity here: It's initialization must resist on the
135 rem = current_ir_graph;
136 current_ir_graph = get_const_code_irg();
137 cnst = new_Const(mode, key.tv);
138 current_ir_graph = rem;
140 set_atomic_ent_value(ent, cnst);
142 /* set the entry for hashmap */
151 /* determine if one operator is an Imm */
152 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
154 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
155 else return is_ia32_Cnst(op2) ? op2 : NULL;
158 /* determine if one operator is not an Imm */
159 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
160 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
165 * Construct a standard binary operation, set AM and immediate if required.
167 * @param env The transformation environment
168 * @param op1 The first operand
169 * @param op2 The second operand
170 * @param func The node constructor function
171 * @return The constructed ia32 node.
173 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
174 ir_node *new_op = NULL;
175 ir_mode *mode = env->mode;
176 dbg_info *dbg = env->dbg;
177 ir_graph *irg = env->irg;
178 ir_node *block = env->block;
179 firm_dbg_module_t *mod = env->mod;
180 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
181 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
182 ir_node *nomem = new_NoMem();
183 ir_node *expr_op, *imm_op;
186 /* Check if immediate optimization is on and */
187 /* if it's an operation with immediate. */
188 if (! env->cg->opt.immops) {
192 else if (is_op_commutative(get_irn_op(env->irn))) {
193 imm_op = get_immediate_op(op1, op2);
194 expr_op = get_expr_op(op1, op2);
197 imm_op = get_immediate_op(NULL, op2);
198 expr_op = get_expr_op(op1, op2);
201 assert((expr_op || imm_op) && "invalid operands");
204 /* We have two consts here: not yet supported */
208 if (mode_is_float(mode)) {
209 /* floating point operations */
211 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
212 set_ia32_Immop_attr(new_op, imm_op);
213 set_ia32_am_support(new_op, ia32_am_None);
216 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
217 set_ia32_am_support(new_op, ia32_am_Source);
221 /* integer operations */
223 /* This is expr + const */
224 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
225 set_ia32_Immop_attr(new_op, imm_op);
228 set_ia32_am_support(new_op, ia32_am_Dest);
231 /* This is a normal operation */
232 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
235 set_ia32_am_support(new_op, ia32_am_Full);
239 if (is_op_commutative(get_irn_op(env->irn))) {
240 set_ia32_commutative(new_op);
243 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
249 * Construct a shift/rotate binary operation, sets AM and immediate if required.
251 * @param env The transformation environment
252 * @param op1 The first operand
253 * @param op2 The second operand
254 * @param func The node constructor function
255 * @return The constructed ia32 node.
257 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
258 ir_node *new_op = NULL;
259 ir_mode *mode = env->mode;
260 dbg_info *dbg = env->dbg;
261 ir_graph *irg = env->irg;
262 ir_node *block = env->block;
263 firm_dbg_module_t *mod = env->mod;
264 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
265 ir_node *nomem = new_NoMem();
266 ir_node *expr_op, *imm_op;
269 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
271 /* Check if immediate optimization is on and */
272 /* if it's an operation with immediate. */
273 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
274 expr_op = get_expr_op(op1, op2);
276 assert((expr_op || imm_op) && "invalid operands");
279 /* We have two consts here: not yet supported */
283 /* Limit imm_op within range imm8 */
285 tv = get_ia32_Immop_tarval(imm_op);
288 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
295 /* integer operations */
297 /* This is shift/rot with const */
299 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
300 set_ia32_Immop_attr(new_op, imm_op);
303 /* This is a normal shift/rot */
304 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
308 set_ia32_am_support(new_op, ia32_am_Dest);
310 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
315 * Construct a standard unary operation, set AM and immediate if required.
317 * @param env The transformation environment
318 * @param op The operand
319 * @param func The node constructor function
320 * @return The constructed ia32 node.
322 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
323 ir_node *new_op = NULL;
324 ir_mode *mode = env->mode;
325 dbg_info *dbg = env->dbg;
326 ir_graph *irg = env->irg;
327 ir_node *block = env->block;
328 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
329 ir_node *nomem = new_NoMem();
331 new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
333 if (mode_is_float(mode)) {
334 /* floating point operations don't support implicit store */
335 set_ia32_am_support(new_op, ia32_am_None);
338 set_ia32_am_support(new_op, ia32_am_Dest);
341 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
347 * Creates an ia32 Add with immediate.
349 * @param env The transformation environment
350 * @param expr_op The expression operator
351 * @param const_op The constant
352 * @return the created ia32 Add node
354 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
355 ir_node *new_op = NULL;
356 tarval *tv = get_ia32_Immop_tarval(const_op);
357 firm_dbg_module_t *mod = env->mod;
358 dbg_info *dbg = env->dbg;
359 ir_mode *mode = env->mode;
360 ir_graph *irg = env->irg;
361 ir_node *block = env->block;
362 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
363 ir_node *nomem = new_NoMem();
365 tarval_classification_t class_tv, class_negtv;
367 /* try to optimize to inc/dec */
368 if (env->cg->opt.incdec && tv) {
369 /* optimize tarvals */
370 class_tv = classify_tarval(tv);
371 class_negtv = classify_tarval(tarval_neg(tv));
373 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
374 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
375 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
378 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
379 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
380 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
386 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
387 set_ia32_Immop_attr(new_op, const_op);
394 * Creates an ia32 Add.
396 * @param dbg firm node dbg
397 * @param block the block the new node should belong to
398 * @param op1 first operator
399 * @param op2 second operator
400 * @param mode node mode
401 * @return the created ia32 Add node
403 static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
404 ir_node *new_op = NULL;
405 dbg_info *dbg = env->dbg;
406 ir_mode *mode = env->mode;
407 ir_graph *irg = env->irg;
408 ir_node *block = env->block;
409 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
410 ir_node *nomem = new_NoMem();
411 ir_node *expr_op, *imm_op;
413 /* Check if immediate optimization is on and */
414 /* if it's an operation with immediate. */
415 imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
416 expr_op = get_expr_op(op1, op2);
418 assert((expr_op || imm_op) && "invalid operands");
420 if (mode_is_float(mode)) {
421 return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
426 /* No expr_op means, that we have two const - one symconst and */
427 /* one tarval or another symconst - because this case is not */
428 /* covered by constant folding */
430 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
431 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
432 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
435 set_ia32_am_support(new_op, ia32_am_Source);
436 set_ia32_op_type(new_op, ia32_AddrModeS);
437 set_ia32_am_flavour(new_op, ia32_am_O);
439 /* Lea doesn't need a Proj */
443 /* This is expr + const */
444 new_op = gen_imm_Add(env, expr_op, imm_op);
447 set_ia32_am_support(new_op, ia32_am_Dest);
450 /* This is a normal add */
451 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
454 set_ia32_am_support(new_op, ia32_am_Full);
458 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
464 * Creates an ia32 Mul.
466 * @param dbg firm node dbg
467 * @param block the block the new node should belong to
468 * @param op1 first operator
469 * @param op2 second operator
470 * @param mode node mode
471 * @return the created ia32 Mul node
473 static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
476 if (mode_is_float(env->mode)) {
477 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
480 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
489 * Creates an ia32 Mulh.
490 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
491 * this result while Mul returns the lower 32 bit.
493 * @param env The transformation environment
494 * @param op1 The first operator
495 * @param op2 The second operator
496 * @return the created ia32 Mulh node
498 static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
499 ir_node *proj_EAX, *proj_EDX, *mulh;
502 assert(mode_is_float(env->mode) && "Mulh with float not supported");
503 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
504 mulh = get_Proj_pred(proj_EAX);
505 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
507 /* to be on the save side */
508 set_Proj_proj(proj_EAX, pn_EAX);
510 if (get_ia32_cnst(mulh)) {
511 /* Mulh with const cannot have AM */
512 set_ia32_am_support(mulh, ia32_am_None);
515 /* Mulh cannot have AM for destination */
516 set_ia32_am_support(mulh, ia32_am_Source);
522 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
530 * Creates an ia32 And.
532 * @param env The transformation environment
533 * @param op1 The first operator
534 * @param op2 The second operator
535 * @return The created ia32 And node
537 static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
538 if (mode_is_float(env->mode)) {
539 return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
542 return gen_binop(env, op1, op2, new_rd_ia32_And);
549 * Creates an ia32 Or.
551 * @param env The transformation environment
552 * @param op1 The first operator
553 * @param op2 The second operator
554 * @return The created ia32 Or node
556 static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
557 if (mode_is_float(env->mode)) {
558 return gen_binop(env, op1, op2, new_rd_ia32_fOr);
561 return gen_binop(env, op1, op2, new_rd_ia32_Or);
568 * Creates an ia32 Eor.
570 * @param env The transformation environment
571 * @param op1 The first operator
572 * @param op2 The second operator
573 * @return The created ia32 Eor node
575 static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
576 if (mode_is_float(env->mode)) {
577 return gen_binop(env, op1, op2, new_rd_ia32_fEor);
580 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
587 * Creates an ia32 Max.
589 * @param env The transformation environment
590 * @param op1 The first operator
591 * @param op2 The second operator
592 * @return the created ia32 Max node
594 static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
597 if (mode_is_float(env->mode)) {
598 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
601 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
602 set_ia32_am_support(new_op, ia32_am_None);
611 * Creates an ia32 Min.
613 * @param env The transformation environment
614 * @param op1 The first operator
615 * @param op2 The second operator
616 * @return the created ia32 Min node
618 static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
621 if (mode_is_float(env->mode)) {
622 new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
625 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
626 set_ia32_am_support(new_op, ia32_am_None);
635 * Creates an ia32 Sub with immediate.
637 * @param env The transformation environment
638 * @param op1 The first operator
639 * @param op2 The second operator
640 * @return The created ia32 Sub node
642 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
643 ir_node *new_op = NULL;
644 tarval *tv = get_ia32_Immop_tarval(const_op);
645 firm_dbg_module_t *mod = env->mod;
646 dbg_info *dbg = env->dbg;
647 ir_mode *mode = env->mode;
648 ir_graph *irg = env->irg;
649 ir_node *block = env->block;
650 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
651 ir_node *nomem = new_NoMem();
653 tarval_classification_t class_tv, class_negtv;
655 /* try to optimize to inc/dec */
656 if (env->cg->opt.incdec && tv) {
657 /* optimize tarvals */
658 class_tv = classify_tarval(tv);
659 class_negtv = classify_tarval(tarval_neg(tv));
661 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
662 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
663 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
666 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
667 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
668 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem, mode_T);
674 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
675 set_ia32_Immop_attr(new_op, const_op);
682 * Creates an ia32 Sub.
684 * @param env The transformation environment
685 * @param op1 The first operator
686 * @param op2 The second operator
687 * @return The created ia32 Sub node
689 static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
690 ir_node *new_op = NULL;
691 dbg_info *dbg = env->dbg;
692 ir_mode *mode = env->mode;
693 ir_graph *irg = env->irg;
694 ir_node *block = env->block;
695 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
696 ir_node *nomem = new_NoMem();
697 ir_node *expr_op, *imm_op;
699 /* Check if immediate optimization is on and */
700 /* if it's an operation with immediate. */
701 imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
702 expr_op = get_expr_op(op1, op2);
704 assert((expr_op || imm_op) && "invalid operands");
706 if (mode_is_float(mode)) {
707 return gen_binop(env, op1, op2, new_rd_ia32_fSub);
712 /* No expr_op means, that we have two const - one symconst and */
713 /* one tarval or another symconst - because this case is not */
714 /* covered by constant folding */
716 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
717 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
718 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
721 set_ia32_am_support(new_op, ia32_am_Source);
722 set_ia32_op_type(new_op, ia32_AddrModeS);
723 set_ia32_am_flavour(new_op, ia32_am_O);
725 /* Lea doesn't need a Proj */
729 /* This is expr - const */
730 new_op = gen_imm_Sub(env, expr_op, imm_op);
733 set_ia32_am_support(new_op, ia32_am_Dest);
736 /* This is a normal sub */
737 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
740 set_ia32_am_support(new_op, ia32_am_Full);
744 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
750 * Generates an ia32 DivMod with additional infrastructure for the
751 * register allocator if needed.
753 * @param env The transformation environment
754 * @param dividend -no comment- :)
755 * @param divisor -no comment- :)
756 * @param dm_flav flavour_Div/Mod/DivMod
757 * @return The created ia32 DivMod node
759 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
761 ir_node *edx_node, *cltd;
763 dbg_info *dbg = env->dbg;
764 ir_graph *irg = env->irg;
765 ir_node *block = env->block;
766 ir_mode *mode = env->mode;
767 ir_node *irn = env->irn;
772 mem = get_Div_mem(irn);
775 mem = get_Mod_mem(irn);
778 mem = get_DivMod_mem(irn);
784 if (mode_is_signed(mode)) {
785 /* in signed mode, we need to sign extend the dividend */
786 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend, mode_T);
787 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EAX);
788 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_EDX);
791 edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
792 set_ia32_Const_type(edx_node, ia32_Const);
793 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
796 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode);
798 set_ia32_flavour(res, dm_flav);
799 set_ia32_n_res(res, 2);
801 /* Only one proj is used -> We must add a second proj and */
802 /* connect this one to a Keep node to eat up the second */
803 /* destroyed register. */
804 if (get_irn_n_edges(irn) == 1) {
805 proj = get_edge_src_irn(get_irn_out_edge_first(irn));
806 assert(is_Proj(proj) && "non-Proj to Div/Mod node");
808 if (get_Proj_proj(proj) == pn_DivMod_res_div) {
809 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
812 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
815 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
823 * Wrapper for generate_DivMod. Sets flavour_Mod.
825 static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
826 return generate_DivMod(env, op1, op2, flavour_Mod);
832 * Wrapper for generate_DivMod. Sets flavour_Div.
834 static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
835 return generate_DivMod(env, op1, op2, flavour_Div);
841 * Wrapper for generate_DivMod. Sets flavour_DivMod.
843 static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
844 return generate_DivMod(env, op1, op2, flavour_DivMod);
850 * Creates an ia32 floating Div.
852 * @param env The transformation environment
853 * @param op1 The first operator
854 * @param op2 The second operator
855 * @return The created ia32 fDiv node
857 static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
858 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
859 ir_node *nomem = new_rd_NoMem(env->irg);
862 new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
863 set_ia32_am_support(new_op, ia32_am_Source);
871 * Creates an ia32 Shl.
873 * @param env The transformation environment
874 * @param op1 The first operator
875 * @param op2 The second operator
876 * @return The created ia32 Shl node
878 static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
879 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
885 * Creates an ia32 Shr.
887 * @param env The transformation environment
888 * @param op1 The first operator
889 * @param op2 The second operator
890 * @return The created ia32 Shr node
892 static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
893 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
899 * Creates an ia32 Shrs.
901 * @param env The transformation environment
902 * @param op1 The first operator
903 * @param op2 The second operator
904 * @return The created ia32 Shrs node
906 static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
907 return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
913 * Creates an ia32 RotL.
915 * @param env The transformation environment
916 * @param op1 The first operator
917 * @param op2 The second operator
918 * @return The created ia32 RotL node
920 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
921 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
927 * Creates an ia32 RotR.
928 * NOTE: There is no RotR with immediate because this would always be a RotL
929 * "imm-mode_size_bits" which can be pre-calculated.
931 * @param env The transformation environment
932 * @param op1 The first operator
933 * @param op2 The second operator
934 * @return The created ia32 RotR node
936 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
937 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
943 * Creates an ia32 RotR or RotL (depending on the found pattern).
945 * @param env The transformation environment
946 * @param op1 The first operator
947 * @param op2 The second operator
948 * @return The created ia32 RotL or RotR node
950 static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
951 ir_node *rotate = NULL;
953 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
954 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
955 that means we can create a RotR instead of an Add and a RotL */
958 ir_node *pred = get_Proj_pred(op2);
960 if (is_ia32_Add(pred)) {
961 ir_node *pred_pred = get_irn_n(pred, 2);
962 tarval *tv = get_ia32_Immop_tarval(pred);
963 long bits = get_mode_size_bits(env->mode);
965 if (is_Proj(pred_pred)) {
966 pred_pred = get_Proj_pred(pred_pred);
969 if (is_ia32_Minus(pred_pred) &&
970 tarval_is_long(tv) &&
971 get_tarval_long(tv) == bits)
973 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
974 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
981 rotate = gen_RotL(env, op1, op2);
990 * Transforms a Conv node.
992 * @param env The transformation environment
993 * @param op The operator
994 * @return The created ia32 Conv node
996 static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
997 return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode);
1003 * Transforms a Minus node.
1005 * @param env The transformation environment
1006 * @param op The operator
1007 * @return The created ia32 Minus node
1009 static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
1012 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1013 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1014 ir_node *nomem = new_rd_NoMem(env->irg);
1017 if (mode_is_float(env->mode)) {
1018 new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1020 size = get_mode_size_bits(env->mode);
1021 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1023 set_ia32_sc(new_op, name);
1025 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1028 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1037 * Transforms a Not node.
1039 * @param env The transformation environment
1040 * @param op The operator
1041 * @return The created ia32 Not node
1043 static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
1046 if (mode_is_float(env->mode)) {
1050 new_op = gen_unop(env, op, new_rd_ia32_Not);
1059 * Transforms an Abs node.
1061 * @param env The transformation environment
1062 * @param op The operator
1063 * @return The created ia32 Abs node
1065 static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
1066 ir_node *res, *p_eax, *p_edx;
1067 dbg_info *dbg = env->dbg;
1068 ir_mode *mode = env->mode;
1069 ir_graph *irg = env->irg;
1070 ir_node *block = env->block;
1071 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1072 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1073 ir_node *nomem = new_NoMem();
1077 if (mode_is_float(mode)) {
1078 res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
1080 size = get_mode_size_bits(mode);
1081 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1083 set_ia32_sc(res, name);
1085 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1088 res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
1089 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
1090 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
1091 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
1092 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1093 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
1094 res = new_rd_Proj(dbg, irg, block, res, mode, 0);
1103 * Transforms a Load.
1105 * @param mod the debug module
1106 * @param block the block the new node should belong to
1107 * @param node the ir Load node
1108 * @param mode node mode
1109 * @return the created ia32 Load node
1111 static ir_node *gen_Load(ia32_transform_env_t *env) {
1112 ir_node *node = env->irn;
1113 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1116 if (mode_is_float(env->mode)) {
1117 new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1120 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
1123 set_ia32_am_support(new_op, ia32_am_Source);
1124 set_ia32_op_type(new_op, ia32_AddrModeS);
1125 set_ia32_am_flavour(new_op, ia32_B);
1126 set_ia32_ls_mode(new_op, get_Load_mode(node));
1134 * Transforms a Store.
1136 * @param mod the debug module
1137 * @param block the block the new node should belong to
1138 * @param node the ir Store node
1139 * @param mode node mode
1140 * @return the created ia32 Store node
1142 static ir_node *gen_Store(ia32_transform_env_t *env) {
1143 ir_node *node = env->irn;
1144 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1145 ir_node *val = get_Store_value(node);
1146 ir_node *ptr = get_Store_ptr(node);
1147 ir_node *mem = get_Store_mem(node);
1148 ir_node *sval = val;
1151 /* in case of storing a const -> make it an attribute */
1152 if (is_ia32_Cnst(val)) {
1156 if (mode_is_float(env->mode)) {
1157 new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1160 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
1163 /* stored const is an attribute (saves a register) */
1164 if (is_ia32_Cnst(val)) {
1165 set_ia32_Immop_attr(new_op, val);
1168 set_ia32_am_support(new_op, ia32_am_Dest);
1169 set_ia32_op_type(new_op, ia32_AddrModeD);
1170 set_ia32_am_flavour(new_op, ia32_B);
1171 set_ia32_ls_mode(new_op, get_irn_mode(val));
1178 * Transforms a Call and its arguments corresponding to the calling convention.
1180 * @param env The transformation environment
1181 * @return The created ia32 Call node
1183 static ir_node *gen_Call(ia32_transform_env_t *env) {
1189 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
1191 * @param env The transformation environment
1192 * @return The transformed node.
1194 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1195 dbg_info *dbg = env->dbg;
1196 ir_graph *irg = env->irg;
1197 ir_node *block = env->block;
1198 ir_node *node = env->irn;
1199 ir_node *sel = get_Cond_selector(node);
1200 ir_mode *sel_mode = get_irn_mode(sel);
1201 ir_node *res = NULL;
1202 ir_node *pred = NULL;
1203 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1204 ir_node *nomem = new_NoMem();
1205 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1207 if (is_Proj(sel) && sel_mode == mode_b) {
1208 pred = get_Proj_pred(sel);
1210 /* get both compare operators */
1211 cmp_a = get_Cmp_left(pred);
1212 cmp_b = get_Cmp_right(pred);
1214 /* check if we can use a CondJmp with immediate */
1215 cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
1216 expr = get_expr_op(cmp_a, cmp_b);
1219 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
1220 set_ia32_Immop_attr(res, cnst);
1223 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
1226 set_ia32_pncode(res, get_Proj_proj(sel));
1227 set_ia32_am_support(res, ia32_am_Source);
1230 res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
1231 set_ia32_pncode(res, get_Cond_defaultProj(node));
1240 * Transforms a CopyB node.
1242 * @param env The transformation environment
1243 * @return The transformed node.
1245 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1246 ir_node *res = NULL;
1247 dbg_info *dbg = env->dbg;
1248 ir_graph *irg = env->irg;
1249 ir_mode *mode = env->mode;
1250 ir_node *block = env->block;
1251 ir_node *node = env->irn;
1252 ir_node *src = get_CopyB_src(node);
1253 ir_node *dst = get_CopyB_dst(node);
1254 ir_node *mem = get_CopyB_mem(node);
1255 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1256 int size = get_type_size_bytes(get_CopyB_type(node));
1259 /* If we have to copy more than 16 bytes, we use REP MOVSx and */
1260 /* then we need the size explicitly in ECX. */
1261 if (size >= 16 * 4) {
1262 rem = size & 0x3; /* size % 4 */
1265 res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
1266 set_ia32_op_type(res, ia32_Const);
1267 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1269 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
1270 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1273 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
1274 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1283 * Transforms a Mux node into CMov.
1285 * @param env The transformation environment
1286 * @return The transformed node.
1288 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1289 ir_node *node = env->irn;
1291 return new_rd_ia32_CMov(env->dbg, env->irg, env->block,
1292 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1297 /********************************************
1300 * | |__ ___ _ __ ___ __| | ___ ___
1301 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1302 * | |_) | __/ | | | (_) | (_| | __/\__ \
1303 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1305 ********************************************/
1307 static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
1308 ir_node *new_op = NULL;
1309 ir_node *node = env->irn;
1310 ir_node *op = get_irn_n(node, 0);
1311 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1312 ir_node *nomem = new_rd_NoMem(env->irg);
1314 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
1315 set_ia32_frame_ent(new_op, be_get_frame_entity(node));
1316 set_ia32_am_support(new_op, ia32_am_Full);
1317 set_ia32_use_frame(new_op);
1319 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
1322 static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
1323 ir_node *new_op = NULL;
1328 static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
1329 ir_node *new_op = NULL;
1336 /*********************************************************
1339 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
1340 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
1341 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
1342 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
1344 *********************************************************/
1347 * Transforms the given firm node (and maybe some other related nodes)
1348 * into one or more assembler nodes.
1350 * @param node the firm node
1351 * @param env the debug module
1353 void ia32_transform_node(ir_node *node, void *env) {
1354 ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
1355 opcode code = get_irn_opcode(node);
1356 ir_node *asm_node = NULL;
1357 ia32_transform_env_t tenv;
1362 tenv.block = get_nodes_block(node);
1363 tenv.dbg = get_irn_dbg_info(node);
1364 tenv.irg = current_ir_graph;
1366 tenv.mod = cgenv->mod;
1367 tenv.mode = get_irn_mode(node);
1370 #define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
1371 #define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
1372 #define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
1373 #define IGN(a) case iro_##a: break
1374 #define BAD(a) case iro_##a: goto bad
1375 #define OTHER_BIN(a) \
1376 if (get_irn_op(node) == get_op_##a()) { \
1377 asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
1381 if (be_is_##a(node)) { \
1382 asm_node = gen_##a(&tenv); \
1386 DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
1432 /* constant transformation happens earlier */
1461 fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
1465 /* exchange nodes if a new one was generated */
1467 exchange(node, asm_node);
1468 DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
1471 DB((tenv.mod, LEVEL_1, "ignored\n"));