2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
68 #include "ia32_architecture.h"
70 #include "gen_ia32_regalloc_if.h"
72 #define SFP_SIGN "0x80000000"
73 #define DFP_SIGN "0x8000000000000000"
74 #define SFP_ABS "0x7FFFFFFF"
75 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
76 #define DFP_INTMAX "9223372036854775807"
78 #define TP_SFP_SIGN "ia32_sfp_sign"
79 #define TP_DFP_SIGN "ia32_dfp_sign"
80 #define TP_SFP_ABS "ia32_sfp_abs"
81 #define TP_DFP_ABS "ia32_dfp_abs"
82 #define TP_INT_MAX "ia32_int_max"
84 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
85 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
86 #define ENT_SFP_ABS "IA32_SFP_ABS"
87 #define ENT_DFP_ABS "IA32_DFP_ABS"
88 #define ENT_INT_MAX "IA32_INT_MAX"
90 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
91 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
93 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
95 /** hold the current code generator during transformation */
96 static ia32_code_gen_t *env_cg = NULL;
97 static ir_node *initial_fpcw = NULL;
98 static heights_t *heights = NULL;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
108 ir_node *op1, ir_node *op2, ir_node *flags);
110 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
111 ir_node *block, ir_node *op1, ir_node *op2);
113 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
118 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
120 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
122 ir_node *op1, ir_node *op2, ir_node *fpcw);
124 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
125 ir_node *block, ir_node *op);
127 static ir_node *try_create_Immediate(ir_node *node,
128 char immediate_constraint_type);
130 static ir_node *create_immediate_or_transform(ir_node *node,
131 char immediate_constraint_type);
133 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
134 dbg_info *dbgi, ir_node *block,
135 ir_node *op, ir_node *orig_node);
138 * Return true if a mode can be stored in the GP register set
140 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
141 if(mode == mode_fpcw)
143 if(get_mode_size_bits(mode) > 32)
145 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
149 * creates a unique ident by adding a number to a tag
151 * @param tag the tag string, must contain a %d if a number
154 static ident *unique_id(const char *tag)
156 static unsigned id = 0;
159 snprintf(str, sizeof(str), tag, ++id);
160 return new_id_from_str(str);
164 * Get a primitive type for a mode.
166 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
168 pmap_entry *e = pmap_find(types, mode);
173 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
174 res = new_type_primitive(new_id_from_str(buf), mode);
175 set_type_alignment_bytes(res, 16);
176 pmap_insert(types, mode, res);
184 * Get an atomic entity that is initialized with a tarval
186 static ir_entity *create_float_const_entity(ir_node *cnst)
188 ia32_isa_t *isa = env_cg->isa;
189 tarval *tv = get_Const_tarval(cnst);
190 pmap_entry *e = pmap_find(isa->tv_ent, tv);
195 ir_mode *mode = get_irn_mode(cnst);
196 ir_type *tp = get_Const_type(cnst);
197 if (tp == firm_unknown_type)
198 tp = get_prim_type(isa->types, mode);
200 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
202 set_entity_ld_ident(res, get_entity_ident(res));
203 set_entity_visibility(res, visibility_local);
204 set_entity_variability(res, variability_constant);
205 set_entity_allocation(res, allocation_static);
207 /* we create a new entity here: It's initialization must resist on the
209 rem = current_ir_graph;
210 current_ir_graph = get_const_code_irg();
211 set_atomic_ent_value(res, new_Const_type(tv, tp));
212 current_ir_graph = rem;
214 pmap_insert(isa->tv_ent, tv, res);
222 static int is_Const_0(ir_node *node) {
223 return is_Const(node) && is_Const_null(node);
226 static int is_Const_1(ir_node *node) {
227 return is_Const(node) && is_Const_one(node);
230 static int is_Const_Minus_1(ir_node *node) {
231 return is_Const(node) && is_Const_all_one(node);
235 * returns true if constant can be created with a simple float command
237 static int is_simple_x87_Const(ir_node *node)
239 tarval *tv = get_Const_tarval(node);
241 if(tarval_is_null(tv) || tarval_is_one(tv))
244 /* TODO: match all the other float constants */
249 * Transforms a Const.
251 static ir_node *gen_Const(ir_node *node) {
252 ir_graph *irg = current_ir_graph;
253 ir_node *old_block = get_nodes_block(node);
254 ir_node *block = be_transform_node(old_block);
255 dbg_info *dbgi = get_irn_dbg_info(node);
256 ir_mode *mode = get_irn_mode(node);
258 assert(is_Const(node));
260 if (mode_is_float(mode)) {
262 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
263 ir_node *nomem = new_NoMem();
267 if (ia32_cg_config.use_sse2) {
268 if (is_Const_null(node)) {
269 load = new_rd_ia32_xZero(dbgi, irg, block);
270 set_ia32_ls_mode(load, mode);
273 floatent = create_float_const_entity(node);
275 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
277 set_ia32_op_type(load, ia32_AddrModeS);
278 set_ia32_am_sc(load, floatent);
279 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
280 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
283 if (is_Const_null(node)) {
284 load = new_rd_ia32_vfldz(dbgi, irg, block);
286 } else if (is_Const_one(node)) {
287 load = new_rd_ia32_vfld1(dbgi, irg, block);
290 floatent = create_float_const_entity(node);
292 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
293 set_ia32_op_type(load, ia32_AddrModeS);
294 set_ia32_am_sc(load, floatent);
295 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
296 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
298 set_ia32_ls_mode(load, mode);
301 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
303 /* Const Nodes before the initial IncSP are a bad idea, because
304 * they could be spilled and we have no SP ready at that point yet.
305 * So add a dependency to the initial frame pointer calculation to
306 * avoid that situation.
308 if (get_irg_start_block(irg) == block) {
309 add_irn_dep(load, get_irg_frame(irg));
312 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
316 tarval *tv = get_Const_tarval(node);
319 tv = tarval_convert_to(tv, mode_Iu);
321 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
323 panic("couldn't convert constant tarval (%+F)", node);
325 val = get_tarval_long(tv);
327 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
328 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
331 if (get_irg_start_block(irg) == block) {
332 add_irn_dep(cnst, get_irg_frame(irg));
340 * Transforms a SymConst.
342 static ir_node *gen_SymConst(ir_node *node) {
343 ir_graph *irg = current_ir_graph;
344 ir_node *old_block = get_nodes_block(node);
345 ir_node *block = be_transform_node(old_block);
346 dbg_info *dbgi = get_irn_dbg_info(node);
347 ir_mode *mode = get_irn_mode(node);
350 if (mode_is_float(mode)) {
351 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
352 ir_node *nomem = new_NoMem();
354 if (ia32_cg_config.use_sse2)
355 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
357 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
358 set_ia32_am_sc(cnst, get_SymConst_entity(node));
359 set_ia32_use_frame(cnst);
363 if(get_SymConst_kind(node) != symconst_addr_ent) {
364 panic("backend only support symconst_addr_ent (at %+F)", node);
366 entity = get_SymConst_entity(node);
367 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
370 /* Const Nodes before the initial IncSP are a bad idea, because
371 * they could be spilled and we have no SP ready at that point yet
373 if (get_irg_start_block(irg) == block) {
374 add_irn_dep(cnst, get_irg_frame(irg));
377 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
382 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
383 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
384 static const struct {
386 const char *ent_name;
387 const char *cnst_str;
390 } names [ia32_known_const_max] = {
391 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
392 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
393 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
394 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
395 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
397 static ir_entity *ent_cache[ia32_known_const_max];
399 const char *tp_name, *ent_name, *cnst_str;
407 ent_name = names[kct].ent_name;
408 if (! ent_cache[kct]) {
409 tp_name = names[kct].tp_name;
410 cnst_str = names[kct].cnst_str;
412 switch (names[kct].mode) {
413 case 0: mode = mode_Iu; break;
414 case 1: mode = mode_Lu; break;
415 default: mode = mode_F; break;
417 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
418 tp = new_type_primitive(new_id_from_str(tp_name), mode);
419 /* set the specified alignment */
420 set_type_alignment_bytes(tp, names[kct].align);
422 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
424 set_entity_ld_ident(ent, get_entity_ident(ent));
425 set_entity_visibility(ent, visibility_local);
426 set_entity_variability(ent, variability_constant);
427 set_entity_allocation(ent, allocation_static);
429 /* we create a new entity here: It's initialization must resist on the
431 rem = current_ir_graph;
432 current_ir_graph = get_const_code_irg();
433 cnst = new_Const(mode, tv);
434 current_ir_graph = rem;
436 set_atomic_ent_value(ent, cnst);
438 /* cache the entry */
439 ent_cache[kct] = ent;
442 return ent_cache[kct];
447 * Prints the old node name on cg obst and returns a pointer to it.
449 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
450 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
452 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
453 obstack_1grow(isa->name_obst, 0);
454 return obstack_finish(isa->name_obst);
459 * return true if the node is a Proj(Load) and could be used in source address
460 * mode for another node. Will return only true if the @p other node is not
461 * dependent on the memory of the Load (for binary operations use the other
462 * input here, for unary operations use NULL).
464 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
465 ir_node *other, ir_node *other2)
467 ir_mode *mode = get_irn_mode(node);
471 /* float constants are always available */
472 if(is_Const(node) && mode_is_float(mode)) {
473 if(!is_simple_x87_Const(node))
475 if(get_irn_n_edges(node) > 1)
482 load = get_Proj_pred(node);
483 pn = get_Proj_proj(node);
484 if(!is_Load(load) || pn != pn_Load_res)
486 if(get_nodes_block(load) != block)
488 /* we only use address mode if we're the only user of the load */
489 if(get_irn_n_edges(node) > 1)
491 /* in some edge cases with address mode we might reach the load normally
492 * and through some AM sequence, if it is already materialized then we
493 * can't create an AM node from it */
494 if(be_is_transformed(node))
497 /* don't do AM if other node inputs depend on the load (via mem-proj) */
498 if(other != NULL && get_nodes_block(other) == block
499 && heights_reachable_in_block(heights, other, load))
501 if(other2 != NULL && get_nodes_block(other2) == block
502 && heights_reachable_in_block(heights, other2, load))
508 typedef struct ia32_address_mode_t ia32_address_mode_t;
509 struct ia32_address_mode_t {
513 ia32_op_type_t op_type;
517 unsigned commutative : 1;
518 unsigned ins_permuted : 1;
521 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
523 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
525 /* construct load address */
526 memset(addr, 0, sizeof(addr[0]));
527 ia32_create_address_mode(addr, ptr, /*force=*/0);
529 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
530 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
531 addr->mem = be_transform_node(mem);
534 static void build_address(ia32_address_mode_t *am, ir_node *node)
536 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
537 ia32_address_t *addr = &am->addr;
544 ir_entity *entity = create_float_const_entity(node);
545 addr->base = noreg_gp;
546 addr->index = noreg_gp;
547 addr->mem = new_NoMem();
548 addr->symconst_ent = entity;
550 am->ls_mode = get_irn_mode(node);
551 am->pinned = op_pin_state_floats;
555 load = get_Proj_pred(node);
556 ptr = get_Load_ptr(load);
557 mem = get_Load_mem(load);
558 new_mem = be_transform_node(mem);
559 am->pinned = get_irn_pinned(load);
560 am->ls_mode = get_Load_mode(load);
561 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
563 /* construct load address */
564 ia32_create_address_mode(addr, ptr, /*force=*/0);
566 addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
567 addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
571 static void set_address(ir_node *node, const ia32_address_t *addr)
573 set_ia32_am_scale(node, addr->scale);
574 set_ia32_am_sc(node, addr->symconst_ent);
575 set_ia32_am_offs_int(node, addr->offset);
576 if(addr->symconst_sign)
577 set_ia32_am_sc_sign(node);
579 set_ia32_use_frame(node);
580 set_ia32_frame_ent(node, addr->frame_entity);
583 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
585 set_address(node, &am->addr);
587 set_ia32_op_type(node, am->op_type);
588 set_ia32_ls_mode(node, am->ls_mode);
589 if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
590 set_irn_pinned(node, am->pinned);
593 set_ia32_commutative(node);
597 * Check, if a given node is a Down-Conv, ie. a integer Conv
598 * from a mode with a mode with more bits to a mode with lesser bits.
599 * Moreover, we return only true if the node has not more than 1 user.
601 * @param node the node
602 * @return non-zero if node is a Down-Conv
604 static int is_downconv(const ir_node *node)
612 /* we only want to skip the conv when we're the only user
613 * (not optimal but for now...)
615 if(get_irn_n_edges(node) > 1)
618 src_mode = get_irn_mode(get_Conv_op(node));
619 dest_mode = get_irn_mode(node);
620 return mode_needs_gp_reg(src_mode)
621 && mode_needs_gp_reg(dest_mode)
622 && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
625 /* Skip all Down-Conv's on a given node and return the resulting node. */
626 ir_node *ia32_skip_downconv(ir_node *node) {
627 while (is_downconv(node))
628 node = get_Conv_op(node);
634 static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
636 ir_mode *mode = get_irn_mode(node);
641 if(mode_is_signed(mode)) {
646 block = get_nodes_block(node);
647 dbgi = get_irn_dbg_info(node);
649 return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
654 * matches operands of a node into ia32 addressing/operand modes. This covers
655 * usage of source address mode, immediates, operations with non 32-bit modes,
657 * The resulting data is filled into the @p am struct. block is the block
658 * of the node whose arguments are matched. op1, op2 are the first and second
659 * input that are matched (op1 may be NULL). other_op is another unrelated
660 * input that is not matched! but which is needed sometimes to check if AM
661 * for op1/op2 is legal.
662 * @p flags describes the supported modes of the operation in detail.
664 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
665 ir_node *op1, ir_node *op2, ir_node *other_op,
668 ia32_address_t *addr = &am->addr;
669 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
672 ir_mode *mode = get_irn_mode(op2);
674 unsigned commutative;
675 int use_am_and_immediates;
677 int mode_bits = get_mode_size_bits(mode);
679 memset(am, 0, sizeof(am[0]));
681 commutative = (flags & match_commutative) != 0;
682 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
683 use_am = (flags & match_am) != 0;
684 use_immediate = (flags & match_immediate) != 0;
685 assert(!use_am_and_immediates || use_immediate);
688 assert(!commutative || op1 != NULL);
689 assert(use_am || !(flags & match_8bit_am));
690 assert(use_am || !(flags & match_16bit_am));
693 if (! (flags & match_8bit_am))
695 /* we don't automatically add upconvs yet */
696 assert((flags & match_mode_neutral) || (flags & match_8bit));
697 } else if(mode_bits == 16) {
698 if(! (flags & match_16bit_am))
700 /* we don't automatically add upconvs yet */
701 assert((flags & match_mode_neutral) || (flags & match_16bit));
704 /* we can simply skip downconvs for mode neutral nodes: the upper bits
705 * can be random for these operations */
706 if(flags & match_mode_neutral) {
707 op2 = ia32_skip_downconv(op2);
709 op1 = ia32_skip_downconv(op1);
713 /* match immediates. firm nodes are normalized: constants are always on the
716 if(! (flags & match_try_am) && use_immediate) {
717 new_op2 = try_create_Immediate(op2, 0);
721 && use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
722 build_address(am, op2);
723 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
724 if(mode_is_float(mode)) {
725 new_op2 = ia32_new_NoReg_vfp(env_cg);
729 am->op_type = ia32_AddrModeS;
730 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
732 && ia32_use_source_address_mode(block, op1, op2, other_op)) {
734 build_address(am, op1);
736 if(mode_is_float(mode)) {
737 noreg = ia32_new_NoReg_vfp(env_cg);
742 if(new_op2 != NULL) {
745 new_op1 = be_transform_node(op2);
747 am->ins_permuted = 1;
749 am->op_type = ia32_AddrModeS;
751 if(flags & match_try_am) {
754 am->op_type = ia32_Normal;
758 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
760 new_op2 = be_transform_node(op2);
761 am->op_type = ia32_Normal;
762 am->ls_mode = get_irn_mode(op2);
763 if(flags & match_mode_neutral)
764 am->ls_mode = mode_Iu;
766 if(addr->base == NULL)
767 addr->base = noreg_gp;
768 if(addr->index == NULL)
769 addr->index = noreg_gp;
770 if(addr->mem == NULL)
771 addr->mem = new_NoMem();
773 am->new_op1 = new_op1;
774 am->new_op2 = new_op2;
775 am->commutative = commutative;
778 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
780 ir_graph *irg = current_ir_graph;
784 if(am->mem_proj == NULL)
787 /* we have to create a mode_T so the old MemProj can attach to us */
788 mode = get_irn_mode(node);
789 load = get_Proj_pred(am->mem_proj);
791 mark_irn_visited(load);
792 be_set_transformed_node(load, node);
795 set_irn_mode(node, mode_T);
796 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
803 * Construct a standard binary operation, set AM and immediate if required.
805 * @param op1 The first operand
806 * @param op2 The second operand
807 * @param func The node constructor function
808 * @return The constructed ia32 node.
810 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
811 construct_binop_func *func, match_flags_t flags)
813 ir_node *block = get_nodes_block(node);
814 ir_node *new_block = be_transform_node(block);
815 ir_graph *irg = current_ir_graph;
816 dbg_info *dbgi = get_irn_dbg_info(node);
818 ia32_address_mode_t am;
819 ia32_address_t *addr = &am.addr;
821 match_arguments(&am, block, op1, op2, NULL, flags);
823 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
824 am.new_op1, am.new_op2);
825 set_am_attributes(new_node, &am);
826 /* we can't use source address mode anymore when using immediates */
827 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
828 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
829 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
831 new_node = fix_mem_proj(new_node, &am);
838 n_ia32_l_binop_right,
839 n_ia32_l_binop_eflags
841 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
842 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
843 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
844 COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
845 COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
846 COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
849 * Construct a binary operation which also consumes the eflags.
851 * @param node The node to transform
852 * @param func The node constructor function
853 * @param flags The match flags
854 * @return The constructor ia32 node
856 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
859 ir_node *src_block = get_nodes_block(node);
860 ir_node *block = be_transform_node(src_block);
861 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
862 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
863 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
864 ir_node *new_eflags = be_transform_node(eflags);
865 ir_graph *irg = current_ir_graph;
866 dbg_info *dbgi = get_irn_dbg_info(node);
868 ia32_address_mode_t am;
869 ia32_address_t *addr = &am.addr;
871 match_arguments(&am, src_block, op1, op2, NULL, flags);
873 new_node = func(dbgi, irg, block, addr->base, addr->index,
874 addr->mem, am.new_op1, am.new_op2, new_eflags);
875 set_am_attributes(new_node, &am);
876 /* we can't use source address mode anymore when using immediates */
877 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
878 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
879 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
881 new_node = fix_mem_proj(new_node, &am);
886 static ir_node *get_fpcw(void)
889 if(initial_fpcw != NULL)
892 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
893 &ia32_fp_cw_regs[REG_FPCW]);
894 initial_fpcw = be_transform_node(fpcw);
900 * Construct a standard binary operation, set AM and immediate if required.
902 * @param op1 The first operand
903 * @param op2 The second operand
904 * @param func The node constructor function
905 * @return The constructed ia32 node.
907 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
908 construct_binop_float_func *func,
911 ir_graph *irg = current_ir_graph;
912 dbg_info *dbgi = get_irn_dbg_info(node);
913 ir_node *block = get_nodes_block(node);
914 ir_node *new_block = be_transform_node(block);
915 ir_mode *mode = get_irn_mode(node);
917 ia32_address_mode_t am;
918 ia32_address_t *addr = &am.addr;
920 /* cannot use addresmode with long double on x87 */
921 if (get_mode_size_bits(mode) > 64)
924 match_arguments(&am, block, op1, op2, NULL, flags);
926 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
927 am.new_op1, am.new_op2, get_fpcw());
928 set_am_attributes(new_node, &am);
930 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
932 new_node = fix_mem_proj(new_node, &am);
938 * Construct a shift/rotate binary operation, sets AM and immediate if required.
940 * @param op1 The first operand
941 * @param op2 The second operand
942 * @param func The node constructor function
943 * @return The constructed ia32 node.
945 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
946 construct_shift_func *func,
949 dbg_info *dbgi = get_irn_dbg_info(node);
950 ir_graph *irg = current_ir_graph;
951 ir_node *block = get_nodes_block(node);
952 ir_node *new_block = be_transform_node(block);
957 assert(! mode_is_float(get_irn_mode(node)));
958 assert(flags & match_immediate);
959 assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
961 if(flags & match_mode_neutral) {
962 op1 = ia32_skip_downconv(op1);
964 new_op1 = be_transform_node(op1);
966 /* the shift amount can be any mode that is bigger than 5 bits, since all
967 * other bits are ignored anyway */
968 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
969 op2 = get_Conv_op(op2);
970 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
972 new_op2 = create_immediate_or_transform(op2, 0);
974 new_node = func(dbgi, irg, new_block, new_op1, new_op2);
975 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
977 /* lowered shift instruction may have a dependency operand, handle it here */
978 if (get_irn_arity(node) == 3) {
979 /* we have a dependency */
980 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
981 add_irn_dep(new_node, new_dep);
989 * Construct a standard unary operation, set AM and immediate if required.
991 * @param op The operand
992 * @param func The node constructor function
993 * @return The constructed ia32 node.
995 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
998 ir_graph *irg = current_ir_graph;
999 dbg_info *dbgi = get_irn_dbg_info(node);
1000 ir_node *block = get_nodes_block(node);
1001 ir_node *new_block = be_transform_node(block);
1005 assert(flags == 0 || flags == match_mode_neutral);
1006 if(flags & match_mode_neutral) {
1007 op = ia32_skip_downconv(op);
1010 new_op = be_transform_node(op);
1011 new_node = func(dbgi, irg, new_block, new_op);
1013 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1018 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1019 ia32_address_t *addr)
1021 ir_graph *irg = current_ir_graph;
1022 ir_node *base = addr->base;
1023 ir_node *index = addr->index;
1027 base = ia32_new_NoReg_gp(env_cg);
1029 base = be_transform_node(base);
1033 index = ia32_new_NoReg_gp(env_cg);
1035 index = be_transform_node(index);
1038 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1039 set_address(res, addr);
1044 static int am_has_immediates(const ia32_address_t *addr)
1046 return addr->offset != 0 || addr->symconst_ent != NULL
1047 || addr->frame_entity || addr->use_frame;
1051 * Creates an ia32 Add.
1053 * @return the created ia32 Add node
1055 static ir_node *gen_Add(ir_node *node) {
1056 ir_graph *irg = current_ir_graph;
1057 dbg_info *dbgi = get_irn_dbg_info(node);
1058 ir_node *block = get_nodes_block(node);
1059 ir_node *new_block = be_transform_node(block);
1060 ir_node *op1 = get_Add_left(node);
1061 ir_node *op2 = get_Add_right(node);
1062 ir_mode *mode = get_irn_mode(node);
1064 ir_node *add_immediate_op;
1065 ia32_address_t addr;
1066 ia32_address_mode_t am;
1068 if (mode_is_float(mode)) {
1069 if (ia32_cg_config.use_sse2)
1070 return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
1071 match_commutative | match_am);
1073 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
1074 match_commutative | match_am);
1077 ia32_mark_non_am(node);
1079 op2 = ia32_skip_downconv(op2);
1080 op1 = ia32_skip_downconv(op1);
1084 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1085 * 1. Add with immediate -> Lea
1086 * 2. Add with possible source address mode -> Add
1087 * 3. Otherwise -> Lea
1089 memset(&addr, 0, sizeof(addr));
1090 ia32_create_address_mode(&addr, node, /*force=*/1);
1091 add_immediate_op = NULL;
1093 if(addr.base == NULL && addr.index == NULL) {
1094 new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
1095 addr.symconst_sign, addr.offset);
1096 add_irn_dep(new_node, get_irg_frame(irg));
1097 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1100 /* add with immediate? */
1101 if(addr.index == NULL) {
1102 add_immediate_op = addr.base;
1103 } else if(addr.base == NULL && addr.scale == 0) {
1104 add_immediate_op = addr.index;
1107 if(add_immediate_op != NULL) {
1108 if(!am_has_immediates(&addr)) {
1109 #ifdef DEBUG_libfirm
1110 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1113 return be_transform_node(add_immediate_op);
1116 new_node = create_lea_from_address(dbgi, new_block, &addr);
1117 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1121 /* test if we can use source address mode */
1122 match_arguments(&am, block, op1, op2, NULL, match_commutative
1123 | match_mode_neutral | match_am | match_immediate | match_try_am);
1125 /* construct an Add with source address mode */
1126 if (am.op_type == ia32_AddrModeS) {
1127 ia32_address_t *am_addr = &am.addr;
1128 new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
1129 am_addr->index, am_addr->mem, am.new_op1,
1131 set_am_attributes(new_node, &am);
1132 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1134 new_node = fix_mem_proj(new_node, &am);
1139 /* otherwise construct a lea */
1140 new_node = create_lea_from_address(dbgi, new_block, &addr);
1141 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1146 * Creates an ia32 Mul.
1148 * @return the created ia32 Mul node
1150 static ir_node *gen_Mul(ir_node *node) {
1151 ir_node *op1 = get_Mul_left(node);
1152 ir_node *op2 = get_Mul_right(node);
1153 ir_mode *mode = get_irn_mode(node);
1155 if (mode_is_float(mode)) {
1156 if (ia32_cg_config.use_sse2)
1157 return gen_binop(node, op1, op2, new_rd_ia32_xMul,
1158 match_commutative | match_am);
1160 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
1161 match_commutative | match_am);
1164 /* for the lower 32bit of the result it doesn't matter whether we use
1165 * signed or unsigned multiplication so we use IMul as it has fewer
1167 return gen_binop(node, op1, op2, new_rd_ia32_IMul,
1168 match_commutative | match_am | match_mode_neutral |
1169 match_immediate | match_am_and_immediates);
1173 * Creates an ia32 Mulh.
1174 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1175 * this result while Mul returns the lower 32 bit.
1177 * @return the created ia32 Mulh node
1179 static ir_node *gen_Mulh(ir_node *node)
1181 ir_node *block = get_nodes_block(node);
1182 ir_node *new_block = be_transform_node(block);
1183 ir_graph *irg = current_ir_graph;
1184 dbg_info *dbgi = get_irn_dbg_info(node);
1185 ir_mode *mode = get_irn_mode(node);
1186 ir_node *op1 = get_Mulh_left(node);
1187 ir_node *op2 = get_Mulh_right(node);
1188 ir_node *proj_res_high;
1190 ia32_address_mode_t am;
1191 ia32_address_t *addr = &am.addr;
1193 assert(!mode_is_float(mode) && "Mulh with float not supported");
1194 assert(get_mode_size_bits(mode) == 32);
1196 match_arguments(&am, block, op1, op2, NULL, match_commutative | match_am);
1198 if (mode_is_signed(mode)) {
1199 new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
1200 addr->index, addr->mem, am.new_op1,
1203 new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
1204 addr->index, addr->mem, am.new_op1,
1208 set_am_attributes(new_node, &am);
1209 /* we can't use source address mode anymore when using immediates */
1210 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
1211 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
1212 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1214 assert(get_irn_mode(new_node) == mode_T);
1216 fix_mem_proj(new_node, &am);
1218 assert(pn_ia32_IMul1OP_res_high == pn_ia32_Mul_res_high);
1219 proj_res_high = new_rd_Proj(dbgi, irg, block, new_node,
1220 mode_Iu, pn_ia32_IMul1OP_res_high);
1222 return proj_res_high;
1228 * Creates an ia32 And.
1230 * @return The created ia32 And node
1232 static ir_node *gen_And(ir_node *node) {
1233 ir_node *op1 = get_And_left(node);
1234 ir_node *op2 = get_And_right(node);
1235 assert(! mode_is_float(get_irn_mode(node)));
1237 /* is it a zero extension? */
1238 if (is_Const(op2)) {
1239 tarval *tv = get_Const_tarval(op2);
1240 long v = get_tarval_long(tv);
1242 if (v == 0xFF || v == 0xFFFF) {
1243 dbg_info *dbgi = get_irn_dbg_info(node);
1244 ir_node *block = get_nodes_block(node);
1251 assert(v == 0xFFFF);
1254 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1260 return gen_binop(node, op1, op2, new_rd_ia32_And,
1261 match_commutative | match_mode_neutral | match_am
1268 * Creates an ia32 Or.
1270 * @return The created ia32 Or node
1272 static ir_node *gen_Or(ir_node *node) {
1273 ir_node *op1 = get_Or_left(node);
1274 ir_node *op2 = get_Or_right(node);
1276 assert (! mode_is_float(get_irn_mode(node)));
1277 return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
1278 | match_mode_neutral | match_am | match_immediate);
1284 * Creates an ia32 Eor.
1286 * @return The created ia32 Eor node
1288 static ir_node *gen_Eor(ir_node *node) {
1289 ir_node *op1 = get_Eor_left(node);
1290 ir_node *op2 = get_Eor_right(node);
1292 assert(! mode_is_float(get_irn_mode(node)));
1293 return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
1294 | match_mode_neutral | match_am | match_immediate);
1299 * Creates an ia32 Sub.
1301 * @return The created ia32 Sub node
1303 static ir_node *gen_Sub(ir_node *node) {
1304 ir_node *op1 = get_Sub_left(node);
1305 ir_node *op2 = get_Sub_right(node);
1306 ir_mode *mode = get_irn_mode(node);
1308 if (mode_is_float(mode)) {
1309 if (ia32_cg_config.use_sse2)
1310 return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
1312 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
1317 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1321 return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
1322 | match_am | match_immediate);
1326 * Generates an ia32 DivMod with additional infrastructure for the
1327 * register allocator if needed.
1329 static ir_node *create_Div(ir_node *node)
1331 ir_graph *irg = current_ir_graph;
1332 dbg_info *dbgi = get_irn_dbg_info(node);
1333 ir_node *block = get_nodes_block(node);
1334 ir_node *new_block = be_transform_node(block);
1341 ir_node *sign_extension;
1343 ia32_address_mode_t am;
1344 ia32_address_t *addr = &am.addr;
1346 /* the upper bits have random contents for smaller modes */
1348 switch (get_irn_opcode(node)) {
1350 op1 = get_Div_left(node);
1351 op2 = get_Div_right(node);
1352 mem = get_Div_mem(node);
1353 mode = get_Div_resmode(node);
1354 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1357 op1 = get_Mod_left(node);
1358 op2 = get_Mod_right(node);
1359 mem = get_Mod_mem(node);
1360 mode = get_Mod_resmode(node);
1361 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1364 op1 = get_DivMod_left(node);
1365 op2 = get_DivMod_right(node);
1366 mem = get_DivMod_mem(node);
1367 mode = get_DivMod_resmode(node);
1368 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1371 panic("invalid divmod node %+F", node);
1374 match_arguments(&am, block, op1, op2, NULL, match_am);
1376 if(!is_NoMem(mem)) {
1377 new_mem = be_transform_node(mem);
1378 if(!is_NoMem(addr->mem)) {
1382 new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
1385 new_mem = addr->mem;
1388 if (mode_is_signed(mode)) {
1389 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1390 add_irn_dep(produceval, get_irg_frame(irg));
1391 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
1394 new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
1395 addr->index, new_mem, am.new_op1,
1396 sign_extension, am.new_op2);
1398 sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
1399 add_irn_dep(sign_extension, get_irg_frame(irg));
1401 new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
1402 addr->index, new_mem, am.new_op1,
1403 sign_extension, am.new_op2);
1406 set_ia32_exc_label(new_node, has_exc);
1407 set_irn_pinned(new_node, get_irn_pinned(node));
1409 set_am_attributes(new_node, &am);
1410 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1412 new_node = fix_mem_proj(new_node, &am);
1418 static ir_node *gen_Mod(ir_node *node) {
1419 return create_Div(node);
1422 static ir_node *gen_Div(ir_node *node) {
1423 return create_Div(node);
1426 static ir_node *gen_DivMod(ir_node *node) {
1427 return create_Div(node);
1433 * Creates an ia32 floating Div.
1435 * @return The created ia32 xDiv node
1437 static ir_node *gen_Quot(ir_node *node)
1439 ir_node *op1 = get_Quot_left(node);
1440 ir_node *op2 = get_Quot_right(node);
1442 if (ia32_cg_config.use_sse2) {
1443 return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
1445 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
1451 * Creates an ia32 Shl.
1453 * @return The created ia32 Shl node
1455 static ir_node *gen_Shl(ir_node *node) {
1456 ir_node *left = get_Shl_left(node);
1457 ir_node *right = get_Shl_right(node);
1459 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
1460 match_mode_neutral | match_immediate);
1464 * Creates an ia32 Shr.
1466 * @return The created ia32 Shr node
1468 static ir_node *gen_Shr(ir_node *node) {
1469 ir_node *left = get_Shr_left(node);
1470 ir_node *right = get_Shr_right(node);
1472 return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
1478 * Creates an ia32 Sar.
1480 * @return The created ia32 Shrs node
1482 static ir_node *gen_Shrs(ir_node *node) {
1483 ir_node *left = get_Shrs_left(node);
1484 ir_node *right = get_Shrs_right(node);
1485 ir_mode *mode = get_irn_mode(node);
1487 if(is_Const(right) && mode == mode_Is) {
1488 tarval *tv = get_Const_tarval(right);
1489 long val = get_tarval_long(tv);
1491 /* this is a sign extension */
1492 ir_graph *irg = current_ir_graph;
1493 dbg_info *dbgi = get_irn_dbg_info(node);
1494 ir_node *block = be_transform_node(get_nodes_block(node));
1496 ir_node *new_op = be_transform_node(op);
1497 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1498 add_irn_dep(pval, get_irg_frame(irg));
1500 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1504 /* 8 or 16 bit sign extension? */
1505 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1506 ir_node *shl_left = get_Shl_left(left);
1507 ir_node *shl_right = get_Shl_right(left);
1508 if(is_Const(shl_right)) {
1509 tarval *tv1 = get_Const_tarval(right);
1510 tarval *tv2 = get_Const_tarval(shl_right);
1511 if(tv1 == tv2 && tarval_is_long(tv1)) {
1512 long val = get_tarval_long(tv1);
1513 if(val == 16 || val == 24) {
1514 dbg_info *dbgi = get_irn_dbg_info(node);
1515 ir_node *block = get_nodes_block(node);
1525 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1534 return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
1540 * Creates an ia32 RotL.
1542 * @param op1 The first operator
1543 * @param op2 The second operator
1544 * @return The created ia32 RotL node
1546 static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
1547 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
1553 * Creates an ia32 RotR.
1554 * NOTE: There is no RotR with immediate because this would always be a RotL
1555 * "imm-mode_size_bits" which can be pre-calculated.
1557 * @param op1 The first operator
1558 * @param op2 The second operator
1559 * @return The created ia32 RotR node
1561 static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
1562 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
1568 * Creates an ia32 RotR or RotL (depending on the found pattern).
1570 * @return The created ia32 RotL or RotR node
1572 static ir_node *gen_Rot(ir_node *node) {
1573 ir_node *rotate = NULL;
1574 ir_node *op1 = get_Rot_left(node);
1575 ir_node *op2 = get_Rot_right(node);
1577 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1578 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1579 that means we can create a RotR instead of an Add and a RotL */
1581 if (get_irn_op(op2) == op_Add) {
1583 ir_node *left = get_Add_left(add);
1584 ir_node *right = get_Add_right(add);
1585 if (is_Const(right)) {
1586 tarval *tv = get_Const_tarval(right);
1587 ir_mode *mode = get_irn_mode(node);
1588 long bits = get_mode_size_bits(mode);
1590 if (get_irn_op(left) == op_Minus &&
1591 tarval_is_long(tv) &&
1592 get_tarval_long(tv) == bits &&
1595 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1596 rotate = gen_RotR(node, op1, get_Minus_op(left));
1601 if (rotate == NULL) {
1602 rotate = gen_RotL(node, op1, op2);
1611 * Transforms a Minus node.
1613 * @return The created ia32 Minus node
1615 static ir_node *gen_Minus(ir_node *node)
1617 ir_node *op = get_Minus_op(node);
1618 ir_node *block = be_transform_node(get_nodes_block(node));
1619 ir_graph *irg = current_ir_graph;
1620 dbg_info *dbgi = get_irn_dbg_info(node);
1621 ir_mode *mode = get_irn_mode(node);
1626 if (mode_is_float(mode)) {
1627 ir_node *new_op = be_transform_node(op);
1628 if (ia32_cg_config.use_sse2) {
1629 /* TODO: non-optimal... if we have many xXors, then we should
1630 * rather create a load for the const and use that instead of
1631 * several AM nodes... */
1632 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1633 ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
1634 ir_node *nomem = new_rd_NoMem(irg);
1636 new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
1637 nomem, new_op, noreg_xmm);
1639 size = get_mode_size_bits(mode);
1640 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1642 set_ia32_am_sc(new_node, ent);
1643 set_ia32_op_type(new_node, ia32_AddrModeS);
1644 set_ia32_ls_mode(new_node, mode);
1646 new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1649 new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
1652 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1658 * Transforms a Not node.
1660 * @return The created ia32 Not node
1662 static ir_node *gen_Not(ir_node *node) {
1663 ir_node *op = get_Not_op(node);
1665 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
1666 assert (! mode_is_float(get_irn_mode(node)));
1668 return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
1674 * Transforms an Abs node.
1676 * @return The created ia32 Abs node
1678 static ir_node *gen_Abs(ir_node *node)
1680 ir_node *block = get_nodes_block(node);
1681 ir_node *new_block = be_transform_node(block);
1682 ir_node *op = get_Abs_op(node);
1683 ir_graph *irg = current_ir_graph;
1684 dbg_info *dbgi = get_irn_dbg_info(node);
1685 ir_mode *mode = get_irn_mode(node);
1686 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1687 ir_node *nomem = new_NoMem();
1693 if (mode_is_float(mode)) {
1694 new_op = be_transform_node(op);
1696 if (ia32_cg_config.use_sse2) {
1697 ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
1698 new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
1699 nomem, new_op, noreg_fp);
1701 size = get_mode_size_bits(mode);
1702 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1704 set_ia32_am_sc(new_node, ent);
1706 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1708 set_ia32_op_type(new_node, ia32_AddrModeS);
1709 set_ia32_ls_mode(new_node, mode);
1711 new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
1712 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1715 ir_node *xor, *pval, *sign_extension;
1717 if (get_mode_size_bits(mode) == 32) {
1718 new_op = be_transform_node(op);
1720 new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
1723 pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
1724 sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
1727 add_irn_dep(pval, get_irg_frame(irg));
1728 SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
1730 xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
1731 nomem, new_op, sign_extension);
1732 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1734 new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
1735 nomem, xor, sign_extension);
1736 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1742 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1744 ir_graph *irg = current_ir_graph;
1752 /* we have a Cmp as input */
1754 ir_node *pred = get_Proj_pred(node);
1756 flags = be_transform_node(pred);
1757 *pnc_out = get_Proj_proj(node);
1762 /* a mode_b value, we have to compare it against 0 */
1763 dbgi = get_irn_dbg_info(node);
1764 new_block = be_transform_node(get_nodes_block(node));
1765 new_op = be_transform_node(node);
1766 noreg = ia32_new_NoReg_gp(env_cg);
1767 nomem = new_NoMem();
1768 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
1769 new_op, new_op, 0, 0);
1770 *pnc_out = pn_Cmp_Lg;
1775 * Transforms a Load.
1777 * @return the created ia32 Load node
1779 static ir_node *gen_Load(ir_node *node) {
1780 ir_node *old_block = get_nodes_block(node);
1781 ir_node *block = be_transform_node(old_block);
1782 ir_node *ptr = get_Load_ptr(node);
1783 ir_node *mem = get_Load_mem(node);
1784 ir_node *new_mem = be_transform_node(mem);
1787 ir_graph *irg = current_ir_graph;
1788 dbg_info *dbgi = get_irn_dbg_info(node);
1789 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1790 ir_mode *mode = get_Load_mode(node);
1793 ia32_address_t addr;
1795 /* construct load address */
1796 memset(&addr, 0, sizeof(addr));
1797 ia32_create_address_mode(&addr, ptr, /*force=*/0);
1804 base = be_transform_node(base);
1810 index = be_transform_node(index);
1813 if (mode_is_float(mode)) {
1814 if (ia32_cg_config.use_sse2) {
1815 new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1817 res_mode = mode_xmm;
1819 new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1821 res_mode = mode_vfp;
1824 assert(mode != mode_b);
1826 /* create a conv node with address mode for smaller modes */
1827 if(get_mode_size_bits(mode) < 32) {
1828 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1829 new_mem, noreg, mode);
1831 new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1836 set_irn_pinned(new_node, get_irn_pinned(node));
1837 set_ia32_op_type(new_node, ia32_AddrModeS);
1838 set_ia32_ls_mode(new_node, mode);
1839 set_address(new_node, &addr);
1841 if(get_irn_pinned(node) == op_pin_state_floats) {
1842 add_ia32_flags(new_node, arch_irn_flags_rematerializable);
1845 /* make sure we are scheduled behind the initial IncSP/Barrier
1846 * to avoid spills being placed before it
1848 if (block == get_irg_start_block(irg)) {
1849 add_irn_dep(new_node, get_irg_frame(irg));
1852 set_ia32_exc_label(new_node,
1853 be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1854 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1859 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1860 ir_node *ptr, ir_node *other)
1867 /* we only use address mode if we're the only user of the load */
1868 if(get_irn_n_edges(node) > 1)
1871 load = get_Proj_pred(node);
1874 if(get_nodes_block(load) != block)
1877 /* Store should be attached to the load */
1878 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1880 /* store should have the same pointer as the load */
1881 if(get_Load_ptr(load) != ptr)
1884 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1885 if(other != NULL && get_nodes_block(other) == block
1886 && heights_reachable_in_block(heights, other, load))
1892 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1893 ir_node *mem, ir_node *ptr, ir_mode *mode,
1894 construct_binop_dest_func *func,
1895 construct_binop_dest_func *func8bit,
1896 match_flags_t flags)
1898 ir_node *src_block = get_nodes_block(node);
1900 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1901 ir_graph *irg = current_ir_graph;
1906 ia32_address_mode_t am;
1907 ia32_address_t *addr = &am.addr;
1908 memset(&am, 0, sizeof(am));
1910 assert(flags & match_dest_am);
1911 assert(flags & match_immediate); /* there is no destam node without... */
1912 commutative = (flags & match_commutative) != 0;
1914 if(use_dest_am(src_block, op1, mem, ptr, op2)) {
1915 build_address(&am, op1);
1916 new_op = create_immediate_or_transform(op2, 0);
1917 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
1918 build_address(&am, op2);
1919 new_op = create_immediate_or_transform(op1, 0);
1924 if(addr->base == NULL)
1925 addr->base = noreg_gp;
1926 if(addr->index == NULL)
1927 addr->index = noreg_gp;
1928 if(addr->mem == NULL)
1929 addr->mem = new_NoMem();
1931 dbgi = get_irn_dbg_info(node);
1932 block = be_transform_node(src_block);
1933 if(get_mode_size_bits(mode) == 8) {
1934 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1937 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1940 set_address(new_node, addr);
1941 set_ia32_op_type(new_node, ia32_AddrModeD);
1942 set_ia32_ls_mode(new_node, mode);
1943 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1948 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1949 ir_node *ptr, ir_mode *mode,
1950 construct_unop_dest_func *func)
1952 ir_graph *irg = current_ir_graph;
1953 ir_node *src_block = get_nodes_block(node);
1957 ia32_address_mode_t am;
1958 ia32_address_t *addr = &am.addr;
1959 memset(&am, 0, sizeof(am));
1961 if(!use_dest_am(src_block, op, mem, ptr, NULL))
1964 build_address(&am, op);
1966 dbgi = get_irn_dbg_info(node);
1967 block = be_transform_node(src_block);
1968 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1969 set_address(new_node, addr);
1970 set_ia32_op_type(new_node, ia32_AddrModeD);
1971 set_ia32_ls_mode(new_node, mode);
1972 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1977 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
1978 ir_mode *mode = get_irn_mode(node);
1979 ir_node *psi_true = get_Psi_val(node, 0);
1980 ir_node *psi_default = get_Psi_default(node);
1991 ia32_address_t addr;
1993 if(get_mode_size_bits(mode) != 8)
1996 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1998 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2004 build_address_ptr(&addr, ptr, mem);
2006 irg = current_ir_graph;
2007 dbgi = get_irn_dbg_info(node);
2008 block = get_nodes_block(node);
2009 new_block = be_transform_node(block);
2010 cond = get_Psi_cond(node, 0);
2011 flags = get_flags_node(cond, &pnc);
2012 new_mem = be_transform_node(mem);
2013 new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
2014 addr.index, addr.mem, flags, pnc, negated);
2015 set_address(new_node, &addr);
2016 set_ia32_op_type(new_node, ia32_AddrModeD);
2017 set_ia32_ls_mode(new_node, mode);
2018 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2023 static ir_node *try_create_dest_am(ir_node *node) {
2024 ir_node *val = get_Store_value(node);
2025 ir_node *mem = get_Store_mem(node);
2026 ir_node *ptr = get_Store_ptr(node);
2027 ir_mode *mode = get_irn_mode(val);
2028 int bits = get_mode_size_bits(mode);
2033 /* handle only GP modes for now... */
2034 if(!mode_needs_gp_reg(mode))
2038 /* store must be the only user of the val node */
2039 if(get_irn_n_edges(val) > 1)
2041 /* skip pointless convs */
2043 ir_node *conv_op = get_Conv_op(val);
2044 ir_mode *pred_mode = get_irn_mode(conv_op);
2045 if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2053 /* value must be in the same block */
2054 if(get_nodes_block(node) != get_nodes_block(val))
2057 switch(get_irn_opcode(val)) {
2059 op1 = get_Add_left(val);
2060 op2 = get_Add_right(val);
2061 if(is_Const_1(op2)) {
2062 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2063 new_rd_ia32_IncMem);
2065 } else if(is_Const_Minus_1(op2)) {
2066 new_node = dest_am_unop(val, op1, mem, ptr, mode,
2067 new_rd_ia32_DecMem);
2070 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2071 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
2072 match_dest_am | match_commutative |
2076 op1 = get_Sub_left(val);
2077 op2 = get_Sub_right(val);
2079 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
2082 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2083 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
2084 match_dest_am | match_immediate |
2088 op1 = get_And_left(val);
2089 op2 = get_And_right(val);
2090 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2091 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
2092 match_dest_am | match_commutative |
2096 op1 = get_Or_left(val);
2097 op2 = get_Or_right(val);
2098 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2099 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
2100 match_dest_am | match_commutative |
2104 op1 = get_Eor_left(val);
2105 op2 = get_Eor_right(val);
2106 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2107 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
2108 match_dest_am | match_commutative |
2112 op1 = get_Shl_left(val);
2113 op2 = get_Shl_right(val);
2114 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2115 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
2116 match_dest_am | match_immediate);
2119 op1 = get_Shr_left(val);
2120 op2 = get_Shr_right(val);
2121 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2122 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
2123 match_dest_am | match_immediate);
2126 op1 = get_Shrs_left(val);
2127 op2 = get_Shrs_right(val);
2128 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2129 new_rd_ia32_SarMem, new_rd_ia32_SarMem,
2130 match_dest_am | match_immediate);
2133 op1 = get_Rot_left(val);
2134 op2 = get_Rot_right(val);
2135 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2136 new_rd_ia32_RolMem, new_rd_ia32_RolMem,
2137 match_dest_am | match_immediate);
2139 /* TODO: match ROR patterns... */
2141 new_node = try_create_SetMem(val, ptr, mem);
2144 op1 = get_Minus_op(val);
2145 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
2148 /* should be lowered already */
2149 assert(mode != mode_b);
2150 op1 = get_Not_op(val);
2151 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
2157 if(new_node != NULL) {
2158 if(get_irn_pinned(new_node) != op_pin_state_pinned &&
2159 get_irn_pinned(node) == op_pin_state_pinned) {
2160 set_irn_pinned(new_node, op_pin_state_pinned);
2167 static int is_float_to_int32_conv(const ir_node *node)
2169 ir_mode *mode = get_irn_mode(node);
2173 if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
2178 conv_op = get_Conv_op(node);
2179 conv_mode = get_irn_mode(conv_op);
2181 if(!mode_is_float(conv_mode))
2188 * Transforms a Store.
2190 * @return the created ia32 Store node
2192 static ir_node *gen_Store(ir_node *node)
2194 ir_node *block = get_nodes_block(node);
2195 ir_node *new_block = be_transform_node(block);
2196 ir_node *ptr = get_Store_ptr(node);
2197 ir_node *val = get_Store_value(node);
2198 ir_node *mem = get_Store_mem(node);
2199 ir_graph *irg = current_ir_graph;
2200 dbg_info *dbgi = get_irn_dbg_info(node);
2201 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2202 ir_mode *mode = get_irn_mode(val);
2205 ia32_address_t addr;
2207 /* check for destination address mode */
2208 new_node = try_create_dest_am(node);
2209 if(new_node != NULL)
2212 /* construct store address */
2213 memset(&addr, 0, sizeof(addr));
2214 ia32_create_address_mode(&addr, ptr, /*force=*/0);
2216 if(addr.base == NULL) {
2219 addr.base = be_transform_node(addr.base);
2222 if(addr.index == NULL) {
2225 addr.index = be_transform_node(addr.index);
2227 addr.mem = be_transform_node(mem);
2229 if (mode_is_float(mode)) {
2230 /* convs (and strict-convs) before stores are unnecessary if the mode
2232 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2233 val = get_Conv_op(val);
2235 new_val = be_transform_node(val);
2236 if (ia32_cg_config.use_sse2) {
2237 new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
2238 addr.index, addr.mem, new_val);
2240 new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
2241 addr.index, addr.mem, new_val, mode);
2243 } else if(is_float_to_int32_conv(val)) {
2244 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
2245 val = get_Conv_op(val);
2247 /* convs (and strict-convs) before stores are unnecessary if the mode
2249 while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
2250 val = get_Conv_op(val);
2252 new_val = be_transform_node(val);
2254 new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
2255 addr.index, addr.mem, new_val, trunc_mode);
2257 new_val = create_immediate_or_transform(val, 0);
2258 assert(mode != mode_b);
2260 if (get_mode_size_bits(mode) == 8) {
2261 new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
2262 addr.index, addr.mem, new_val);
2264 new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
2265 addr.index, addr.mem, new_val);
2269 set_irn_pinned(new_node, get_irn_pinned(node));
2270 set_ia32_op_type(new_node, ia32_AddrModeD);
2271 set_ia32_ls_mode(new_node, mode);
2273 set_ia32_exc_label(new_node,
2274 be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
2275 set_address(new_node, &addr);
2276 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2281 static ir_node *create_Switch(ir_node *node)
2283 ir_graph *irg = current_ir_graph;
2284 dbg_info *dbgi = get_irn_dbg_info(node);
2285 ir_node *block = be_transform_node(get_nodes_block(node));
2286 ir_node *sel = get_Cond_selector(node);
2287 ir_node *new_sel = be_transform_node(sel);
2288 int switch_min = INT_MAX;
2289 long default_pn = get_Cond_defaultProj(node);
2291 const ir_edge_t *edge;
2293 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
2295 /* determine the smallest switch case value */
2296 foreach_out_edge(node, edge) {
2297 ir_node *proj = get_edge_src_irn(edge);
2298 long pn = get_Proj_proj(proj);
2299 if(pn == default_pn)
2306 if (switch_min != 0) {
2307 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2309 /* if smallest switch case is not 0 we need an additional sub */
2310 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
2311 add_ia32_am_offs_int(new_sel, -switch_min);
2312 set_ia32_op_type(new_sel, ia32_AddrModeS);
2314 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
2317 new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
2318 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2323 static ir_node *gen_Cond(ir_node *node) {
2324 ir_node *block = get_nodes_block(node);
2325 ir_node *new_block = be_transform_node(block);
2326 ir_graph *irg = current_ir_graph;
2327 dbg_info *dbgi = get_irn_dbg_info(node);
2328 ir_node *sel = get_Cond_selector(node);
2329 ir_mode *sel_mode = get_irn_mode(sel);
2330 ir_node *flags = NULL;
2334 if (sel_mode != mode_b) {
2335 return create_Switch(node);
2338 /* we get flags from a cmp */
2339 flags = get_flags_node(sel, &pnc);
2341 new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2342 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2350 * Transforms a CopyB node.
2352 * @return The transformed node.
2354 static ir_node *gen_CopyB(ir_node *node) {
2355 ir_node *block = be_transform_node(get_nodes_block(node));
2356 ir_node *src = get_CopyB_src(node);
2357 ir_node *new_src = be_transform_node(src);
2358 ir_node *dst = get_CopyB_dst(node);
2359 ir_node *new_dst = be_transform_node(dst);
2360 ir_node *mem = get_CopyB_mem(node);
2361 ir_node *new_mem = be_transform_node(mem);
2362 ir_node *res = NULL;
2363 ir_graph *irg = current_ir_graph;
2364 dbg_info *dbgi = get_irn_dbg_info(node);
2365 int size = get_type_size_bytes(get_CopyB_type(node));
2368 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2369 /* then we need the size explicitly in ECX. */
2370 if (size >= 32 * 4) {
2371 rem = size & 0x3; /* size % 4 */
2374 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2375 add_irn_dep(res, get_irg_frame(irg));
2377 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
2380 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2383 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
2386 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2391 static ir_node *gen_be_Copy(ir_node *node)
2393 ir_node *new_node = be_duplicate_node(node);
2394 ir_mode *mode = get_irn_mode(new_node);
2396 if (mode_needs_gp_reg(mode)) {
2397 set_irn_mode(new_node, mode_Iu);
2403 static ir_node *create_Fucom(ir_node *node)
2405 ir_graph *irg = current_ir_graph;
2406 dbg_info *dbgi = get_irn_dbg_info(node);
2407 ir_node *block = get_nodes_block(node);
2408 ir_node *new_block = be_transform_node(block);
2409 ir_node *left = get_Cmp_left(node);
2410 ir_node *new_left = be_transform_node(left);
2411 ir_node *right = get_Cmp_right(node);
2415 if(ia32_cg_config.use_fucomi) {
2416 new_right = be_transform_node(right);
2417 new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
2419 set_ia32_commutative(new_node);
2420 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2422 if(ia32_cg_config.use_ftst && is_Const_0(right)) {
2423 new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
2426 new_right = be_transform_node(right);
2427 new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2431 set_ia32_commutative(new_node);
2433 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2435 new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
2436 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2442 static ir_node *create_Ucomi(ir_node *node)
2444 ir_graph *irg = current_ir_graph;
2445 dbg_info *dbgi = get_irn_dbg_info(node);
2446 ir_node *src_block = get_nodes_block(node);
2447 ir_node *new_block = be_transform_node(src_block);
2448 ir_node *left = get_Cmp_left(node);
2449 ir_node *right = get_Cmp_right(node);
2451 ia32_address_mode_t am;
2452 ia32_address_t *addr = &am.addr;
2454 match_arguments(&am, src_block, left, right, NULL,
2455 match_commutative | match_am);
2457 new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
2458 addr->mem, am.new_op1, am.new_op2,
2460 set_am_attributes(new_node, &am);
2462 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2464 new_node = fix_mem_proj(new_node, &am);
2470 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2471 * to fold an and into a test node
2473 static int can_fold_test_and(ir_node *node)
2475 const ir_edge_t *edge;
2477 /** we can only have eq and lg projs */
2478 foreach_out_edge(node, edge) {
2479 ir_node *proj = get_edge_src_irn(edge);
2480 pn_Cmp pnc = get_Proj_proj(proj);
2481 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2488 static ir_node *gen_Cmp(ir_node *node)
2490 ir_graph *irg = current_ir_graph;
2491 dbg_info *dbgi = get_irn_dbg_info(node);
2492 ir_node *block = get_nodes_block(node);
2493 ir_node *new_block = be_transform_node(block);
2494 ir_node *left = get_Cmp_left(node);
2495 ir_node *right = get_Cmp_right(node);
2496 ir_mode *cmp_mode = get_irn_mode(left);
2498 ia32_address_mode_t am;
2499 ia32_address_t *addr = &am.addr;
2502 if(mode_is_float(cmp_mode)) {
2503 if (ia32_cg_config.use_sse2) {
2504 return create_Ucomi(node);
2506 return create_Fucom(node);
2510 assert(mode_needs_gp_reg(cmp_mode));
2512 /* we prefer the Test instruction where possible except cases where
2513 * we can use SourceAM */
2514 cmp_unsigned = !mode_is_signed(cmp_mode);
2515 if (is_Const_0(right)) {
2517 get_irn_n_edges(left) == 1 &&
2518 can_fold_test_and(node)) {
2519 /* Test(and_left, and_right) */
2520 ir_node *and_left = get_And_left(left);
2521 ir_node *and_right = get_And_right(left);
2522 ir_mode *mode = get_irn_mode(and_left);
2524 match_arguments(&am, block, and_left, and_right, NULL,
2526 match_am | match_8bit_am | match_16bit_am |
2527 match_am_and_immediates | match_immediate |
2528 match_8bit | match_16bit);
2529 if (get_mode_size_bits(mode) == 8) {
2530 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2531 addr->index, addr->mem, am.new_op1,
2532 am.new_op2, am.ins_permuted,
2535 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2536 addr->index, addr->mem, am.new_op1,
2537 am.new_op2, am.ins_permuted, cmp_unsigned);
2540 match_arguments(&am, block, NULL, left, NULL,
2541 match_am | match_8bit_am | match_16bit_am |
2542 match_8bit | match_16bit);
2543 if (am.op_type == ia32_AddrModeS) {
2545 ir_node *imm_zero = try_create_Immediate(right, 0);
2546 if (get_mode_size_bits(cmp_mode) == 8) {
2547 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2548 addr->index, addr->mem, am.new_op2,
2549 imm_zero, am.ins_permuted,
2552 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2553 addr->index, addr->mem, am.new_op2,
2554 imm_zero, am.ins_permuted, cmp_unsigned);
2557 /* Test(left, left) */
2558 if (get_mode_size_bits(cmp_mode) == 8) {
2559 new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2560 addr->index, addr->mem, am.new_op2,
2561 am.new_op2, am.ins_permuted,
2564 new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
2565 addr->index, addr->mem, am.new_op2,
2566 am.new_op2, am.ins_permuted,
2572 /* Cmp(left, right) */
2573 match_arguments(&am, block, left, right, NULL,
2574 match_commutative | match_am | match_8bit_am |
2575 match_16bit_am | match_am_and_immediates |
2576 match_immediate | match_8bit | match_16bit);
2577 if (get_mode_size_bits(cmp_mode) == 8) {
2578 new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
2579 addr->index, addr->mem, am.new_op1,
2580 am.new_op2, am.ins_permuted,
2583 new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
2584 addr->index, addr->mem, am.new_op1,
2585 am.new_op2, am.ins_permuted, cmp_unsigned);
2588 set_am_attributes(new_node, &am);
2589 assert(cmp_mode != NULL);
2590 set_ia32_ls_mode(new_node, cmp_mode);
2592 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2594 new_node = fix_mem_proj(new_node, &am);
2599 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
2602 ir_graph *irg = current_ir_graph;
2603 dbg_info *dbgi = get_irn_dbg_info(node);
2604 ir_node *block = get_nodes_block(node);
2605 ir_node *new_block = be_transform_node(block);
2606 ir_node *val_true = get_Psi_val(node, 0);
2607 ir_node *val_false = get_Psi_default(node);
2609 match_flags_t match_flags;
2610 ia32_address_mode_t am;
2611 ia32_address_t *addr;
2613 assert(ia32_cg_config.use_cmov);
2614 assert(mode_needs_gp_reg(get_irn_mode(val_true)));
2618 match_flags = match_commutative | match_am | match_16bit_am |
2621 match_arguments(&am, block, val_false, val_true, flags, match_flags);
2623 new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
2624 addr->mem, am.new_op1, am.new_op2, new_flags,
2625 am.ins_permuted, pnc);
2626 set_am_attributes(new_node, &am);
2628 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2630 new_node = fix_mem_proj(new_node, &am);
2637 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2638 ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
2641 ir_graph *irg = current_ir_graph;
2642 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2643 ir_node *nomem = new_NoMem();
2644 ir_mode *mode = get_irn_mode(orig_node);
2647 new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
2648 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2650 /* we might need to conv the result up */
2651 if(get_mode_size_bits(mode) > 8) {
2652 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2653 nomem, new_node, mode_Bu);
2654 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
2661 * Transforms a Psi node into CMov.
2663 * @return The transformed node.
2665 static ir_node *gen_Psi(ir_node *node)
2667 dbg_info *dbgi = get_irn_dbg_info(node);
2668 ir_node *block = get_nodes_block(node);
2669 ir_node *new_block = be_transform_node(block);
2670 ir_node *psi_true = get_Psi_val(node, 0);
2671 ir_node *psi_default = get_Psi_default(node);
2672 ir_node *cond = get_Psi_cond(node, 0);
2673 ir_node *flags = NULL;
2677 assert(get_Psi_n_conds(node) == 1);
2678 assert(get_irn_mode(cond) == mode_b);
2679 assert(mode_needs_gp_reg(get_irn_mode(node)));
2681 flags = get_flags_node(cond, &pnc);
2683 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2684 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
2685 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2686 new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
2688 new_node = create_CMov(node, cond, flags, pnc);
2695 * Create a conversion from x87 state register to general purpose.
2697 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2698 ir_node *block = be_transform_node(get_nodes_block(node));
2699 ir_node *op = get_Conv_op(node);
2700 ir_node *new_op = be_transform_node(op);
2701 ia32_code_gen_t *cg = env_cg;
2702 ir_graph *irg = current_ir_graph;
2703 dbg_info *dbgi = get_irn_dbg_info(node);
2704 ir_node *noreg = ia32_new_NoReg_gp(cg);
2705 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2706 ir_mode *mode = get_irn_mode(node);
2707 ir_node *fist, *load;
2710 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2711 new_NoMem(), new_op, trunc_mode);
2713 set_irn_pinned(fist, op_pin_state_floats);
2714 set_ia32_use_frame(fist);
2715 set_ia32_op_type(fist, ia32_AddrModeD);
2717 assert(get_mode_size_bits(mode) <= 32);
2718 /* exception we can only store signed 32 bit integers, so for unsigned
2719 we store a 64bit (signed) integer and load the lower bits */
2720 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2721 set_ia32_ls_mode(fist, mode_Ls);
2723 set_ia32_ls_mode(fist, mode_Is);
2725 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2728 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2730 set_irn_pinned(load, op_pin_state_floats);
2731 set_ia32_use_frame(load);
2732 set_ia32_op_type(load, ia32_AddrModeS);
2733 set_ia32_ls_mode(load, mode_Is);
2734 if(get_ia32_ls_mode(fist) == mode_Ls) {
2735 ia32_attr_t *attr = get_ia32_attr(load);
2736 attr->data.need_64bit_stackent = 1;
2738 ia32_attr_t *attr = get_ia32_attr(load);
2739 attr->data.need_32bit_stackent = 1;
2741 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2743 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2747 * Creates a x87 strict Conv by placing a Sore and a Load
2749 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2751 ir_node *block = get_nodes_block(node);
2752 ir_graph *irg = current_ir_graph;
2753 dbg_info *dbgi = get_irn_dbg_info(node);
2754 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2755 ir_node *nomem = new_NoMem();
2756 ir_node *frame = get_irg_frame(irg);
2757 ir_node *store, *load;
2760 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2762 set_ia32_use_frame(store);
2763 set_ia32_op_type(store, ia32_AddrModeD);
2764 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2766 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2768 set_ia32_use_frame(load);
2769 set_ia32_op_type(load, ia32_AddrModeS);
2770 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2772 new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2776 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2778 ir_graph *irg = current_ir_graph;
2779 ir_node *start_block = get_irg_start_block(irg);
2780 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2781 symconst, symconst_sign, val);
2782 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2788 * Create a conversion from general purpose to x87 register
2790 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2791 ir_node *src_block = get_nodes_block(node);
2792 ir_node *block = be_transform_node(src_block);
2793 ir_graph *irg = current_ir_graph;
2794 dbg_info *dbgi = get_irn_dbg_info(node);
2795 ir_node *op = get_Conv_op(node);
2796 ir_node *new_op = NULL;
2800 ir_mode *store_mode;
2806 /* fild can use source AM if the operand is a signed 32bit integer */
2807 if (src_mode == mode_Is) {
2808 ia32_address_mode_t am;
2810 match_arguments(&am, src_block, NULL, op, NULL,
2811 match_am | match_try_am);
2812 if (am.op_type == ia32_AddrModeS) {
2813 ia32_address_t *addr = &am.addr;
2815 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
2816 addr->index, addr->mem);
2817 new_node = new_r_Proj(irg, block, fild, mode_vfp,
2820 set_am_attributes(fild, &am);
2821 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2823 fix_mem_proj(fild, &am);
2828 if(new_op == NULL) {
2829 new_op = be_transform_node(op);
2832 noreg = ia32_new_NoReg_gp(env_cg);
2833 nomem = new_NoMem();
2834 mode = get_irn_mode(op);
2836 /* first convert to 32 bit signed if necessary */
2837 src_bits = get_mode_size_bits(src_mode);
2838 if (src_bits == 8) {
2839 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2841 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2843 } else if (src_bits < 32) {
2844 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2846 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2850 assert(get_mode_size_bits(mode) == 32);
2853 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2856 set_ia32_use_frame(store);
2857 set_ia32_op_type(store, ia32_AddrModeD);
2858 set_ia32_ls_mode(store, mode_Iu);
2860 /* exception for 32bit unsigned, do a 64bit spill+load */
2861 if(!mode_is_signed(mode)) {
2864 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2866 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2867 get_irg_frame(irg), noreg, nomem,
2870 set_ia32_use_frame(zero_store);
2871 set_ia32_op_type(zero_store, ia32_AddrModeD);
2872 add_ia32_am_offs_int(zero_store, 4);
2873 set_ia32_ls_mode(zero_store, mode_Iu);
2878 store = new_rd_Sync(dbgi, irg, block, 2, in);
2879 store_mode = mode_Ls;
2881 store_mode = mode_Is;
2885 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2887 set_ia32_use_frame(fild);
2888 set_ia32_op_type(fild, ia32_AddrModeS);
2889 set_ia32_ls_mode(fild, store_mode);
2891 new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2897 * Create a conversion from one integer mode into another one
2899 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2900 dbg_info *dbgi, ir_node *block, ir_node *op,
2903 ir_graph *irg = current_ir_graph;
2904 int src_bits = get_mode_size_bits(src_mode);
2905 int tgt_bits = get_mode_size_bits(tgt_mode);
2906 ir_node *new_block = be_transform_node(block);
2908 ir_mode *smaller_mode;
2910 ia32_address_mode_t am;
2911 ia32_address_t *addr = &am.addr;
2914 if (src_bits < tgt_bits) {
2915 smaller_mode = src_mode;
2916 smaller_bits = src_bits;
2918 smaller_mode = tgt_mode;
2919 smaller_bits = tgt_bits;
2922 #ifdef DEBUG_libfirm
2924 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
2929 match_arguments(&am, block, NULL, op, NULL,
2930 match_8bit | match_16bit |
2931 match_am | match_8bit_am | match_16bit_am);
2932 if (smaller_bits == 8) {
2933 new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2934 addr->index, addr->mem, am.new_op2,
2937 new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2938 addr->index, addr->mem, am.new_op2,
2941 set_am_attributes(new_node, &am);
2942 /* match_arguments assume that out-mode = in-mode, this isn't true here
2944 set_ia32_ls_mode(new_node, smaller_mode);
2945 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
2946 new_node = fix_mem_proj(new_node, &am);
2951 * Transforms a Conv node.
2953 * @return The created ia32 Conv node
2955 static ir_node *gen_Conv(ir_node *node) {
2956 ir_node *block = get_nodes_block(node);
2957 ir_node *new_block = be_transform_node(block);
2958 ir_node *op = get_Conv_op(node);
2959 ir_node *new_op = NULL;
2960 ir_graph *irg = current_ir_graph;
2961 dbg_info *dbgi = get_irn_dbg_info(node);
2962 ir_mode *src_mode = get_irn_mode(op);
2963 ir_mode *tgt_mode = get_irn_mode(node);
2964 int src_bits = get_mode_size_bits(src_mode);
2965 int tgt_bits = get_mode_size_bits(tgt_mode);
2966 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2967 ir_node *nomem = new_rd_NoMem(irg);
2968 ir_node *res = NULL;
2970 if (src_mode == mode_b) {
2971 assert(mode_is_int(tgt_mode));
2972 /* nothing to do, we already model bools as 0/1 ints */
2973 return be_transform_node(op);
2976 if (src_mode == tgt_mode) {
2977 if (get_Conv_strict(node)) {
2978 if (ia32_cg_config.use_sse2) {
2979 /* when we are in SSE mode, we can kill all strict no-op conversion */
2980 return be_transform_node(op);
2983 /* this should be optimized already, but who knows... */
2984 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2985 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2986 return be_transform_node(op);
2990 if (mode_is_float(src_mode)) {
2991 new_op = be_transform_node(op);
2992 /* we convert from float ... */
2993 if (mode_is_float(tgt_mode)) {
2994 if(src_mode == mode_E && tgt_mode == mode_D
2995 && !get_Conv_strict(node)) {
2996 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3001 if (ia32_cg_config.use_sse2) {
3002 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3003 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
3005 set_ia32_ls_mode(res, tgt_mode);
3007 if(get_Conv_strict(node)) {
3008 res = gen_x87_strict_conv(tgt_mode, new_op);
3009 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
3012 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3017 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3018 if (ia32_cg_config.use_sse2) {
3019 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
3021 set_ia32_ls_mode(res, src_mode);
3023 return gen_x87_fp_to_gp(node);
3027 /* we convert from int ... */
3028 if (mode_is_float(tgt_mode)) {
3030 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3031 if (ia32_cg_config.use_sse2) {
3032 new_op = be_transform_node(op);
3033 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
3035 set_ia32_ls_mode(res, tgt_mode);
3037 res = gen_x87_gp_to_fp(node, src_mode);
3038 if(get_Conv_strict(node)) {
3039 res = gen_x87_strict_conv(tgt_mode, res);
3040 SET_IA32_ORIG_NODE(get_Proj_pred(res),
3041 ia32_get_old_node_name(env_cg, node));
3045 } else if(tgt_mode == mode_b) {
3046 /* mode_b lowering already took care that we only have 0/1 values */
3047 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3048 src_mode, tgt_mode));
3049 return be_transform_node(op);
3052 if (src_bits == tgt_bits) {
3053 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3054 src_mode, tgt_mode));
3055 return be_transform_node(op);
3058 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3066 static int check_immediate_constraint(long val, char immediate_constraint_type)
3068 switch (immediate_constraint_type) {
3072 return val >= 0 && val <= 32;
3074 return val >= 0 && val <= 63;
3076 return val >= -128 && val <= 127;
3078 return val == 0xff || val == 0xffff;
3080 return val >= 0 && val <= 3;
3082 return val >= 0 && val <= 255;
3084 return val >= 0 && val <= 127;
3088 panic("Invalid immediate constraint found");
3092 static ir_node *try_create_Immediate(ir_node *node,
3093 char immediate_constraint_type)
3096 tarval *offset = NULL;
3097 int offset_sign = 0;
3099 ir_entity *symconst_ent = NULL;
3100 int symconst_sign = 0;
3102 ir_node *cnst = NULL;
3103 ir_node *symconst = NULL;
3106 mode = get_irn_mode(node);
3107 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
3111 if(is_Minus(node)) {
3113 node = get_Minus_op(node);
3116 if(is_Const(node)) {
3119 offset_sign = minus;
3120 } else if(is_SymConst(node)) {
3123 symconst_sign = minus;
3124 } else if(is_Add(node)) {
3125 ir_node *left = get_Add_left(node);
3126 ir_node *right = get_Add_right(node);
3127 if(is_Const(left) && is_SymConst(right)) {
3130 symconst_sign = minus;
3131 offset_sign = minus;
3132 } else if(is_SymConst(left) && is_Const(right)) {
3135 symconst_sign = minus;
3136 offset_sign = minus;
3138 } else if(is_Sub(node)) {
3139 ir_node *left = get_Sub_left(node);
3140 ir_node *right = get_Sub_right(node);
3141 if(is_Const(left) && is_SymConst(right)) {
3144 symconst_sign = !minus;
3145 offset_sign = minus;
3146 } else if(is_SymConst(left) && is_Const(right)) {
3149 symconst_sign = minus;
3150 offset_sign = !minus;
3157 offset = get_Const_tarval(cnst);
3158 if(tarval_is_long(offset)) {
3159 val = get_tarval_long(offset);
3161 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
3166 if(!check_immediate_constraint(val, immediate_constraint_type))
3169 if(symconst != NULL) {
3170 if(immediate_constraint_type != 0) {
3171 /* we need full 32bits for symconsts */
3175 /* unfortunately the assembler/linker doesn't support -symconst */
3179 if(get_SymConst_kind(symconst) != symconst_addr_ent)
3181 symconst_ent = get_SymConst_entity(symconst);
3183 if(cnst == NULL && symconst == NULL)
3186 if(offset_sign && offset != NULL) {
3187 offset = tarval_neg(offset);
3190 new_node = create_Immediate(symconst_ent, symconst_sign, val);
3195 static ir_node *create_immediate_or_transform(ir_node *node,
3196 char immediate_constraint_type)
3198 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
3199 if (new_node == NULL) {
3200 new_node = be_transform_node(node);
3205 static const arch_register_req_t no_register_req = {
3206 arch_register_req_type_none,
3207 NULL, /* regclass */
3208 NULL, /* limit bitset */
3210 0 /* different pos */
3214 * An assembler constraint.
3216 typedef struct constraint_t constraint_t;
3217 struct constraint_t {
3220 const arch_register_req_t **out_reqs;
3222 const arch_register_req_t *req;
3223 unsigned immediate_possible;
3224 char immediate_type;
3227 static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
3229 int immediate_possible = 0;
3230 char immediate_type = 0;
3231 unsigned limited = 0;
3232 const arch_register_class_t *cls = NULL;
3233 ir_graph *irg = current_ir_graph;
3234 struct obstack *obst = get_irg_obstack(irg);
3235 arch_register_req_t *req;
3236 unsigned *limited_ptr = NULL;
3240 /* TODO: replace all the asserts with nice error messages */
3243 /* a memory constraint: no need to do anything in backend about it
3244 * (the dependencies are already respected by the memory edge of
3246 constraint->req = &no_register_req;
3258 assert(cls == NULL ||
3259 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3260 cls = &ia32_reg_classes[CLASS_ia32_gp];
3261 limited |= 1 << REG_EAX;
3264 assert(cls == NULL ||
3265 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3266 cls = &ia32_reg_classes[CLASS_ia32_gp];
3267 limited |= 1 << REG_EBX;
3270 assert(cls == NULL ||
3271 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3272 cls = &ia32_reg_classes[CLASS_ia32_gp];
3273 limited |= 1 << REG_ECX;
3276 assert(cls == NULL ||
3277 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3278 cls = &ia32_reg_classes[CLASS_ia32_gp];
3279 limited |= 1 << REG_EDX;
3282 assert(cls == NULL ||
3283 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3284 cls = &ia32_reg_classes[CLASS_ia32_gp];
3285 limited |= 1 << REG_EDI;
3288 assert(cls == NULL ||
3289 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3290 cls = &ia32_reg_classes[CLASS_ia32_gp];
3291 limited |= 1 << REG_ESI;
3294 case 'q': /* q means lower part of the regs only, this makes no
3295 * difference to Q for us (we only assigne whole registers) */
3296 assert(cls == NULL ||
3297 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3298 cls = &ia32_reg_classes[CLASS_ia32_gp];
3299 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3303 assert(cls == NULL ||
3304 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3305 cls = &ia32_reg_classes[CLASS_ia32_gp];
3306 limited |= 1 << REG_EAX | 1 << REG_EDX;
3309 assert(cls == NULL ||
3310 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
3311 cls = &ia32_reg_classes[CLASS_ia32_gp];
3312 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
3313 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3320 assert(cls == NULL);
3321 cls = &ia32_reg_classes[CLASS_ia32_gp];
3327 /* TODO: mark values so the x87 simulator knows about t and u */
3328 assert(cls == NULL);
3329 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3334 assert(cls == NULL);
3335 /* TODO: check that sse2 is supported */
3336 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3346 assert(!immediate_possible);
3347 immediate_possible = 1;
3348 immediate_type = *c;
3352 assert(!immediate_possible);
3353 immediate_possible = 1;
3357 assert(!immediate_possible && cls == NULL);
3358 immediate_possible = 1;
3359 cls = &ia32_reg_classes[CLASS_ia32_gp];
3372 assert(constraint->is_in && "can only specify same constraint "
3375 sscanf(c, "%d%n", &same_as, &p);
3383 /* memory constraint no need to do anything in backend about it
3384 * (the dependencies are already respected by the memory edge of
3386 constraint->req = &no_register_req;
3389 case 'E': /* no float consts yet */
3390 case 'F': /* no float consts yet */
3391 case 's': /* makes no sense on x86 */
3392 case 'X': /* we can't support that in firm */
3395 case '<': /* no autodecrement on x86 */
3396 case '>': /* no autoincrement on x86 */
3397 case 'C': /* sse constant not supported yet */
3398 case 'G': /* 80387 constant not supported yet */
3399 case 'y': /* we don't support mmx registers yet */
3400 case 'Z': /* not available in 32 bit mode */
3401 case 'e': /* not available in 32 bit mode */
3402 panic("unsupported asm constraint '%c' found in (%+F)",
3403 *c, current_ir_graph);
3406 panic("unknown asm constraint '%c' found in (%+F)", *c,
3414 const arch_register_req_t *other_constr;
3416 assert(cls == NULL && "same as and register constraint not supported");
3417 assert(!immediate_possible && "same as and immediate constraint not "
3419 assert(same_as < constraint->n_outs && "wrong constraint number in "
3420 "same_as constraint");
3422 other_constr = constraint->out_reqs[same_as];
3424 req = obstack_alloc(obst, sizeof(req[0]));
3425 req->cls = other_constr->cls;
3426 req->type = arch_register_req_type_should_be_same;
3427 req->limited = NULL;
3428 req->other_same = 1U << pos;
3429 req->other_different = 0;
3431 /* switch constraints. This is because in firm we have same_as
3432 * constraints on the output constraints while in the gcc asm syntax
3433 * they are specified on the input constraints */
3434 constraint->req = other_constr;
3435 constraint->out_reqs[same_as] = req;
3436 constraint->immediate_possible = 0;
3440 if(immediate_possible && cls == NULL) {
3441 cls = &ia32_reg_classes[CLASS_ia32_gp];
3443 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3444 assert(cls != NULL);
3446 if(immediate_possible) {
3447 assert(constraint->is_in
3448 && "immediate make no sense for output constraints");
3450 /* todo: check types (no float input on 'r' constrained in and such... */
3453 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3454 limited_ptr = (unsigned*) (req+1);
3456 req = obstack_alloc(obst, sizeof(req[0]));
3458 memset(req, 0, sizeof(req[0]));
3461 req->type = arch_register_req_type_limited;
3462 *limited_ptr = limited;
3463 req->limited = limited_ptr;
3465 req->type = arch_register_req_type_normal;
3469 constraint->req = req;
3470 constraint->immediate_possible = immediate_possible;
3471 constraint->immediate_type = immediate_type;
3474 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3481 panic("Clobbers not supported yet");
3484 static int is_memory_op(const ir_asm_constraint *constraint)
3486 ident *id = constraint->constraint;
3487 const char *str = get_id_str(id);
3490 for(c = str; *c != '\0'; ++c) {
3499 * generates code for a ASM node
3501 static ir_node *gen_ASM(ir_node *node)
3504 ir_graph *irg = current_ir_graph;
3505 ir_node *block = get_nodes_block(node);
3506 ir_node *new_block = be_transform_node(block);
3507 dbg_info *dbgi = get_irn_dbg_info(node);
3511 int n_out_constraints;
3513 const arch_register_req_t **out_reg_reqs;
3514 const arch_register_req_t **in_reg_reqs;
3515 ia32_asm_reg_t *register_map;
3516 unsigned reg_map_size = 0;
3517 struct obstack *obst;
3518 const ir_asm_constraint *in_constraints;
3519 const ir_asm_constraint *out_constraints;
3521 constraint_t parsed_constraint;
3523 arity = get_irn_arity(node);
3524 in = alloca(arity * sizeof(in[0]));
3525 memset(in, 0, arity * sizeof(in[0]));
3527 n_out_constraints = get_ASM_n_output_constraints(node);
3528 n_clobbers = get_ASM_n_clobbers(node);
3529 out_arity = n_out_constraints + n_clobbers;
3531 in_constraints = get_ASM_input_constraints(node);
3532 out_constraints = get_ASM_output_constraints(node);
3533 clobbers = get_ASM_clobbers(node);
3535 /* construct output constraints */
3536 obst = get_irg_obstack(irg);
3537 out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
3538 parsed_constraint.out_reqs = out_reg_reqs;
3539 parsed_constraint.n_outs = n_out_constraints;
3540 parsed_constraint.is_in = 0;
3542 for(i = 0; i < out_arity; ++i) {
3545 if(i < n_out_constraints) {
3546 const ir_asm_constraint *constraint = &out_constraints[i];
3547 c = get_id_str(constraint->constraint);
3548 parse_asm_constraint(i, &parsed_constraint, c);
3550 if(constraint->pos > reg_map_size)
3551 reg_map_size = constraint->pos;
3553 ident *glob_id = clobbers [i - n_out_constraints];
3554 c = get_id_str(glob_id);
3555 parse_clobber(node, i, &parsed_constraint, c);
3558 out_reg_reqs[i] = parsed_constraint.req;
3561 /* construct input constraints */
3562 in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
3563 parsed_constraint.is_in = 1;
3564 for(i = 0; i < arity; ++i) {
3565 const ir_asm_constraint *constraint = &in_constraints[i];
3566 ident *constr_id = constraint->constraint;
3567 const char *c = get_id_str(constr_id);
3569 parse_asm_constraint(i, &parsed_constraint, c);
3570 in_reg_reqs[i] = parsed_constraint.req;
3572 if(constraint->pos > reg_map_size)
3573 reg_map_size = constraint->pos;
3575 if(parsed_constraint.immediate_possible) {
3576 ir_node *pred = get_irn_n(node, i);
3577 char imm_type = parsed_constraint.immediate_type;
3578 ir_node *immediate = try_create_Immediate(pred, imm_type);
3580 if(immediate != NULL) {
3587 register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
3588 memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
3590 for(i = 0; i < n_out_constraints; ++i) {
3591 const ir_asm_constraint *constraint = &out_constraints[i];
3592 unsigned pos = constraint->pos;
3594 assert(pos < reg_map_size);
3595 register_map[pos].use_input = 0;
3596 register_map[pos].valid = 1;
3597 register_map[pos].memory = is_memory_op(constraint);
3598 register_map[pos].inout_pos = i;
3599 register_map[pos].mode = constraint->mode;
3602 /* transform inputs */
3603 for(i = 0; i < arity; ++i) {
3604 const ir_asm_constraint *constraint = &in_constraints[i];
3605 unsigned pos = constraint->pos;
3606 ir_node *pred = get_irn_n(node, i);
3607 ir_node *transformed;
3609 assert(pos < reg_map_size);
3610 register_map[pos].use_input = 1;
3611 register_map[pos].valid = 1;
3612 register_map[pos].memory = is_memory_op(constraint);
3613 register_map[pos].inout_pos = i;
3614 register_map[pos].mode = constraint->mode;
3619 transformed = be_transform_node(pred);
3620 in[i] = transformed;
3623 new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
3624 get_ASM_text(node), register_map);
3626 set_ia32_out_req_all(new_node, out_reg_reqs);
3627 set_ia32_in_req_all(new_node, in_reg_reqs);
3629 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3635 * Transforms a FrameAddr into an ia32 Add.
3637 static ir_node *gen_be_FrameAddr(ir_node *node) {
3638 ir_node *block = be_transform_node(get_nodes_block(node));
3639 ir_node *op = be_get_FrameAddr_frame(node);
3640 ir_node *new_op = be_transform_node(op);
3641 ir_graph *irg = current_ir_graph;
3642 dbg_info *dbgi = get_irn_dbg_info(node);
3643 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3646 new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3647 set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
3648 set_ia32_use_frame(new_node);
3650 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3656 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3658 static ir_node *gen_be_Return(ir_node *node) {
3659 ir_graph *irg = current_ir_graph;
3660 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3661 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3662 ir_entity *ent = get_irg_entity(irg);
3663 ir_type *tp = get_entity_type(ent);
3668 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3669 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3672 int pn_ret_val, pn_ret_mem, arity, i;
3674 assert(ret_val != NULL);
3675 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3676 return be_duplicate_node(node);
3679 res_type = get_method_res_type(tp, 0);
3681 if (! is_Primitive_type(res_type)) {
3682 return be_duplicate_node(node);
3685 mode = get_type_mode(res_type);
3686 if (! mode_is_float(mode)) {
3687 return be_duplicate_node(node);
3690 assert(get_method_n_ress(tp) == 1);
3692 pn_ret_val = get_Proj_proj(ret_val);
3693 pn_ret_mem = get_Proj_proj(ret_mem);
3695 /* get the Barrier */
3696 barrier = get_Proj_pred(ret_val);
3698 /* get result input of the Barrier */
3699 ret_val = get_irn_n(barrier, pn_ret_val);
3700 new_ret_val = be_transform_node(ret_val);
3702 /* get memory input of the Barrier */
3703 ret_mem = get_irn_n(barrier, pn_ret_mem);
3704 new_ret_mem = be_transform_node(ret_mem);
3706 frame = get_irg_frame(irg);
3708 dbgi = get_irn_dbg_info(barrier);
3709 block = be_transform_node(get_nodes_block(barrier));
3711 noreg = ia32_new_NoReg_gp(env_cg);
3713 /* store xmm0 onto stack */
3714 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3715 new_ret_mem, new_ret_val);
3716 set_ia32_ls_mode(sse_store, mode);
3717 set_ia32_op_type(sse_store, ia32_AddrModeD);
3718 set_ia32_use_frame(sse_store);
3720 /* load into x87 register */
3721 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3722 set_ia32_op_type(fld, ia32_AddrModeS);
3723 set_ia32_use_frame(fld);
3725 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3726 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3728 /* create a new barrier */
3729 arity = get_irn_arity(barrier);
3730 in = alloca(arity * sizeof(in[0]));
3731 for (i = 0; i < arity; ++i) {
3734 if (i == pn_ret_val) {
3736 } else if (i == pn_ret_mem) {
3739 ir_node *in = get_irn_n(barrier, i);
3740 new_in = be_transform_node(in);
3745 new_barrier = new_ir_node(dbgi, irg, block,
3746 get_irn_op(barrier), get_irn_mode(barrier),
3748 copy_node_attr(barrier, new_barrier);
3749 be_duplicate_deps(barrier, new_barrier);
3750 be_set_transformed_node(barrier, new_barrier);
3751 mark_irn_visited(barrier);
3753 /* transform normally */
3754 return be_duplicate_node(node);
3758 * Transform a be_AddSP into an ia32_SubSP.
3760 static ir_node *gen_be_AddSP(ir_node *node)
3762 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3763 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3765 return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
3769 * Transform a be_SubSP into an ia32_AddSP
3771 static ir_node *gen_be_SubSP(ir_node *node)
3773 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3774 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3776 return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
3780 * This function just sets the register for the Unknown node
3781 * as this is not done during register allocation because Unknown
3782 * is an "ignore" node.
3784 static ir_node *gen_Unknown(ir_node *node) {
3785 ir_mode *mode = get_irn_mode(node);
3787 if (mode_is_float(mode)) {
3788 if (ia32_cg_config.use_sse2) {
3789 return ia32_new_Unknown_xmm(env_cg);
3791 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3792 ir_graph *irg = current_ir_graph;
3793 dbg_info *dbgi = get_irn_dbg_info(node);
3794 ir_node *block = get_irg_start_block(irg);
3795 return new_rd_ia32_vfldz(dbgi, irg, block);
3797 } else if (mode_needs_gp_reg(mode)) {
3798 return ia32_new_Unknown_gp(env_cg);
3800 panic("unsupported Unknown-Mode");
3806 * Change some phi modes
3808 static ir_node *gen_Phi(ir_node *node) {
3809 ir_node *block = be_transform_node(get_nodes_block(node));
3810 ir_graph *irg = current_ir_graph;
3811 dbg_info *dbgi = get_irn_dbg_info(node);
3812 ir_mode *mode = get_irn_mode(node);
3815 if(mode_needs_gp_reg(mode)) {
3816 /* we shouldn't have any 64bit stuff around anymore */
3817 assert(get_mode_size_bits(mode) <= 32);
3818 /* all integer operations are on 32bit registers now */
3820 } else if(mode_is_float(mode)) {
3821 if (ia32_cg_config.use_sse2) {
3828 /* phi nodes allow loops, so we use the old arguments for now
3829 * and fix this later */
3830 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3831 get_irn_in(node) + 1);
3832 copy_node_attr(node, phi);
3833 be_duplicate_deps(node, phi);
3835 be_set_transformed_node(node, phi);
3836 be_enqueue_preds(node);
3844 static ir_node *gen_IJmp(ir_node *node)
3846 ir_node *block = get_nodes_block(node);
3847 ir_node *new_block = be_transform_node(block);
3848 ir_graph *irg = current_ir_graph;
3849 dbg_info *dbgi = get_irn_dbg_info(node);
3850 ir_node *op = get_IJmp_target(node);
3852 ia32_address_mode_t am;
3853 ia32_address_t *addr = &am.addr;
3855 assert(get_irn_mode(op) == mode_P);
3857 match_arguments(&am, block, NULL, op, NULL,
3858 match_am | match_8bit_am | match_16bit_am |
3859 match_immediate | match_8bit | match_16bit);
3861 new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
3862 addr->mem, am.new_op2);
3863 set_am_attributes(new_node, &am);
3864 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3866 new_node = fix_mem_proj(new_node, &am);
3871 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3874 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3875 ir_node *val, ir_node *mem);
3878 * Transforms a lowered Load into a "real" one.
3880 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3882 ir_node *block = be_transform_node(get_nodes_block(node));
3883 ir_node *ptr = get_irn_n(node, 0);
3884 ir_node *new_ptr = be_transform_node(ptr);
3885 ir_node *mem = get_irn_n(node, 1);
3886 ir_node *new_mem = be_transform_node(mem);
3887 ir_graph *irg = current_ir_graph;
3888 dbg_info *dbgi = get_irn_dbg_info(node);
3889 ir_mode *mode = get_ia32_ls_mode(node);
3890 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3893 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3895 set_ia32_op_type(new_op, ia32_AddrModeS);
3896 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3897 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3898 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3899 if (is_ia32_am_sc_sign(node))
3900 set_ia32_am_sc_sign(new_op);
3901 set_ia32_ls_mode(new_op, mode);
3902 if (is_ia32_use_frame(node)) {
3903 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3904 set_ia32_use_frame(new_op);
3907 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3913 * Transforms a lowered Store into a "real" one.
3915 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3917 ir_node *block = be_transform_node(get_nodes_block(node));
3918 ir_node *ptr = get_irn_n(node, 0);
3919 ir_node *new_ptr = be_transform_node(ptr);
3920 ir_node *val = get_irn_n(node, 1);
3921 ir_node *new_val = be_transform_node(val);
3922 ir_node *mem = get_irn_n(node, 2);
3923 ir_node *new_mem = be_transform_node(mem);
3924 ir_graph *irg = current_ir_graph;
3925 dbg_info *dbgi = get_irn_dbg_info(node);
3926 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3927 ir_mode *mode = get_ia32_ls_mode(node);
3931 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3933 am_offs = get_ia32_am_offs_int(node);
3934 add_ia32_am_offs_int(new_op, am_offs);
3936 set_ia32_op_type(new_op, ia32_AddrModeD);
3937 set_ia32_ls_mode(new_op, mode);
3938 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3939 set_ia32_use_frame(new_op);
3941 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3946 static ir_node *gen_ia32_l_ShlDep(ir_node *node)
3948 ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
3949 ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
3951 return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
3952 match_immediate | match_mode_neutral);
3955 static ir_node *gen_ia32_l_ShrDep(ir_node *node)
3957 ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
3958 ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
3959 return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
3963 static ir_node *gen_ia32_l_SarDep(ir_node *node)
3965 ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
3966 ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
3967 return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
3971 static ir_node *gen_ia32_l_Add(ir_node *node) {
3972 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3973 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3974 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
3975 match_commutative | match_am | match_immediate |
3976 match_mode_neutral);
3978 if(is_Proj(lowered)) {
3979 lowered = get_Proj_pred(lowered);
3981 assert(is_ia32_Add(lowered));
3982 set_irn_mode(lowered, mode_T);
3988 static ir_node *gen_ia32_l_Adc(ir_node *node)
3990 return gen_binop_flags(node, new_rd_ia32_Adc,
3991 match_commutative | match_am | match_immediate |
3992 match_mode_neutral);
3996 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3998 * @param node The node to transform
3999 * @return the created ia32 vfild node
4001 static ir_node *gen_ia32_l_vfild(ir_node *node) {
4002 return gen_lowered_Load(node, new_rd_ia32_vfild);
4006 * Transforms an ia32_l_Load into a "real" ia32_Load node
4008 * @param node The node to transform
4009 * @return the created ia32 Load node
4011 static ir_node *gen_ia32_l_Load(ir_node *node) {
4012 return gen_lowered_Load(node, new_rd_ia32_Load);
4016 * Transforms an ia32_l_Store into a "real" ia32_Store node
4018 * @param node The node to transform
4019 * @return the created ia32 Store node
4021 static ir_node *gen_ia32_l_Store(ir_node *node) {
4022 return gen_lowered_Store(node, new_rd_ia32_Store);
4026 * Transforms a l_vfist into a "real" vfist node.
4028 * @param node The node to transform
4029 * @return the created ia32 vfist node
4031 static ir_node *gen_ia32_l_vfist(ir_node *node) {
4032 ir_node *block = be_transform_node(get_nodes_block(node));
4033 ir_node *ptr = get_irn_n(node, 0);
4034 ir_node *new_ptr = be_transform_node(ptr);
4035 ir_node *val = get_irn_n(node, 1);
4036 ir_node *new_val = be_transform_node(val);
4037 ir_node *mem = get_irn_n(node, 2);
4038 ir_node *new_mem = be_transform_node(mem);
4039 ir_graph *irg = current_ir_graph;
4040 dbg_info *dbgi = get_irn_dbg_info(node);
4041 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4042 ir_mode *mode = get_ia32_ls_mode(node);
4043 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
4047 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
4048 new_val, trunc_mode);
4050 am_offs = get_ia32_am_offs_int(node);
4051 add_ia32_am_offs_int(new_op, am_offs);
4053 set_ia32_op_type(new_op, ia32_AddrModeD);
4054 set_ia32_ls_mode(new_op, mode);
4055 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
4056 set_ia32_use_frame(new_op);
4058 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
4064 * Transforms a l_MulS into a "real" MulS node.
4066 * @return the created ia32 Mul node
4068 static ir_node *gen_ia32_l_Mul(ir_node *node) {
4069 ir_node *left = get_binop_left(node);
4070 ir_node *right = get_binop_right(node);
4072 return gen_binop(node, left, right, new_rd_ia32_Mul,
4073 match_commutative | match_am | match_mode_neutral);
4077 * Transforms a l_IMulS into a "real" IMul1OPS node.
4079 * @return the created ia32 IMul1OP node
4081 static ir_node *gen_ia32_l_IMul(ir_node *node) {
4082 ir_node *left = get_binop_left(node);
4083 ir_node *right = get_binop_right(node);
4085 return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
4086 match_commutative | match_am | match_mode_neutral);
4089 static ir_node *gen_ia32_l_Sub(ir_node *node) {
4090 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
4091 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
4092 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
4093 match_am | match_immediate | match_mode_neutral);
4095 if(is_Proj(lowered)) {
4096 lowered = get_Proj_pred(lowered);
4098 assert(is_ia32_Sub(lowered));
4099 set_irn_mode(lowered, mode_T);
4105 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
4106 return gen_binop_flags(node, new_rd_ia32_Sbb,
4107 match_am | match_immediate | match_mode_neutral);
4111 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
4112 * op1 - target to be shifted
4113 * op2 - contains bits to be shifted into target
4115 * Only op3 can be an immediate.
4117 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
4118 ir_node *low, ir_node *count)
4120 ir_node *block = get_nodes_block(node);
4121 ir_node *new_block = be_transform_node(block);
4122 ir_graph *irg = current_ir_graph;
4123 dbg_info *dbgi = get_irn_dbg_info(node);
4124 ir_node *new_high = be_transform_node(high);
4125 ir_node *new_low = be_transform_node(low);
4129 /* the shift amount can be any mode that is bigger than 5 bits, since all
4130 * other bits are ignored anyway */
4131 while (is_Conv(count) && get_irn_n_edges(count) == 1) {
4132 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
4133 count = get_Conv_op(count);
4135 new_count = create_immediate_or_transform(count, 0);
4137 if (is_ia32_l_ShlD(node)) {
4138 new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
4141 new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
4144 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
4149 static ir_node *gen_ia32_l_ShlD(ir_node *node)
4151 ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
4152 ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
4153 ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
4154 return gen_lowered_64bit_shifts(node, high, low, count);
4157 static ir_node *gen_ia32_l_ShrD(ir_node *node)
4159 ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
4160 ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
4161 ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
4162 return gen_lowered_64bit_shifts(node, high, low, count);
4166 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
4168 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
4169 ir_node *block = be_transform_node(get_nodes_block(node));
4170 ir_node *val = get_irn_n(node, 1);
4171 ir_node *new_val = be_transform_node(val);
4172 ir_node *res = NULL;
4173 ir_graph *irg = current_ir_graph;
4175 ir_node *noreg, *new_ptr, *new_mem;
4178 if (ia32_cg_config.use_sse2) {
4182 mem = get_irn_n(node, 2);
4183 new_mem = be_transform_node(mem);
4184 ptr = get_irn_n(node, 0);
4185 new_ptr = be_transform_node(ptr);
4186 noreg = ia32_new_NoReg_gp(env_cg);
4187 dbgi = get_irn_dbg_info(node);
4189 /* Store x87 -> MEM */
4190 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
4191 get_ia32_ls_mode(node));
4192 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4193 set_ia32_use_frame(res);
4194 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
4195 set_ia32_op_type(res, ia32_AddrModeD);
4197 /* Load MEM -> SSE */
4198 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
4199 get_ia32_ls_mode(node));
4200 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
4201 set_ia32_use_frame(res);
4202 set_ia32_op_type(res, ia32_AddrModeS);
4203 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
4209 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
4211 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
4212 ir_node *block = be_transform_node(get_nodes_block(node));
4213 ir_node *val = get_irn_n(node, 1);
4214 ir_node *new_val = be_transform_node(val);
4215 ir_graph *irg = current_ir_graph;
4216 ir_node *res = NULL;
4217 ir_entity *fent = get_ia32_frame_ent(node);
4218 ir_mode *lsmode = get_ia32_ls_mode(node);
4220 ir_node *noreg, *new_ptr, *new_mem;
4224 if (! ia32_cg_config.use_sse2) {
4225 /* SSE unit is not used -> skip this node. */
4229 ptr = get_irn_n(node, 0);
4230 new_ptr = be_transform_node(ptr);
4231 mem = get_irn_n(node, 2);
4232 new_mem = be_transform_node(mem);
4233 noreg = ia32_new_NoReg_gp(env_cg);
4234 dbgi = get_irn_dbg_info(node);
4236 /* Store SSE -> MEM */
4237 if (is_ia32_xLoad(skip_Proj(new_val))) {
4238 ir_node *ld = skip_Proj(new_val);
4240 /* we can vfld the value directly into the fpu */
4241 fent = get_ia32_frame_ent(ld);
4242 ptr = get_irn_n(ld, 0);
4243 offs = get_ia32_am_offs_int(ld);
4245 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4247 set_ia32_frame_ent(res, fent);
4248 set_ia32_use_frame(res);
4249 set_ia32_ls_mode(res, lsmode);
4250 set_ia32_op_type(res, ia32_AddrModeD);
4254 /* Load MEM -> x87 */
4255 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4256 set_ia32_frame_ent(res, fent);
4257 set_ia32_use_frame(res);
4258 add_ia32_am_offs_int(res, offs);
4259 set_ia32_op_type(res, ia32_AddrModeS);
4260 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4266 * the BAD transformer.
4268 static ir_node *bad_transform(ir_node *node) {
4269 panic("No transform function for %+F available.\n", node);
4274 * Transform the Projs of an AddSP.
4276 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4277 ir_node *block = be_transform_node(get_nodes_block(node));
4278 ir_node *pred = get_Proj_pred(node);
4279 ir_node *new_pred = be_transform_node(pred);
4280 ir_graph *irg = current_ir_graph;
4281 dbg_info *dbgi = get_irn_dbg_info(node);
4282 long proj = get_Proj_proj(node);
4284 if (proj == pn_be_AddSP_sp) {
4285 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4286 pn_ia32_SubSP_stack);
4287 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4289 } else if(proj == pn_be_AddSP_res) {
4290 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4291 pn_ia32_SubSP_addr);
4292 } else if (proj == pn_be_AddSP_M) {
4293 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4297 return new_rd_Unknown(irg, get_irn_mode(node));
4301 * Transform the Projs of a SubSP.
4303 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4304 ir_node *block = be_transform_node(get_nodes_block(node));
4305 ir_node *pred = get_Proj_pred(node);
4306 ir_node *new_pred = be_transform_node(pred);
4307 ir_graph *irg = current_ir_graph;
4308 dbg_info *dbgi = get_irn_dbg_info(node);
4309 long proj = get_Proj_proj(node);
4311 if (proj == pn_be_SubSP_sp) {
4312 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4313 pn_ia32_AddSP_stack);
4314 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4316 } else if (proj == pn_be_SubSP_M) {
4317 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4321 return new_rd_Unknown(irg, get_irn_mode(node));
4325 * Transform and renumber the Projs from a Load.
4327 static ir_node *gen_Proj_Load(ir_node *node) {
4329 ir_node *block = be_transform_node(get_nodes_block(node));
4330 ir_node *pred = get_Proj_pred(node);
4331 ir_graph *irg = current_ir_graph;
4332 dbg_info *dbgi = get_irn_dbg_info(node);
4333 long proj = get_Proj_proj(node);
4336 /* loads might be part of source address mode matches, so we don't
4337 transform the ProjMs yet (with the exception of loads whose result is
4340 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4343 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4345 /* this is needed, because sometimes we have loops that are only
4346 reachable through the ProjM */
4347 be_enqueue_preds(node);
4348 /* do it in 2 steps, to silence firm verifier */
4349 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4350 set_Proj_proj(res, pn_ia32_Load_M);
4354 /* renumber the proj */
4355 new_pred = be_transform_node(pred);
4356 if (is_ia32_Load(new_pred)) {
4357 if (proj == pn_Load_res) {
4358 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4360 } else if (proj == pn_Load_M) {
4361 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4364 } else if(is_ia32_Conv_I2I(new_pred)
4365 || is_ia32_Conv_I2I8Bit(new_pred)) {
4366 set_irn_mode(new_pred, mode_T);
4367 if (proj == pn_Load_res) {
4368 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4369 } else if (proj == pn_Load_M) {
4370 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4372 } else if (is_ia32_xLoad(new_pred)) {
4373 if (proj == pn_Load_res) {
4374 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4376 } else if (proj == pn_Load_M) {
4377 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4380 } else if (is_ia32_vfld(new_pred)) {
4381 if (proj == pn_Load_res) {
4382 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4384 } else if (proj == pn_Load_M) {
4385 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4389 /* can happen for ProJMs when source address mode happened for the
4392 /* however it should not be the result proj, as that would mean the
4393 load had multiple users and should not have been used for
4395 if(proj != pn_Load_M) {
4396 panic("internal error: transformed node not a Load");
4398 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4402 return new_rd_Unknown(irg, get_irn_mode(node));
4406 * Transform and renumber the Projs from a DivMod like instruction.
4408 static ir_node *gen_Proj_DivMod(ir_node *node) {
4409 ir_node *block = be_transform_node(get_nodes_block(node));
4410 ir_node *pred = get_Proj_pred(node);
4411 ir_node *new_pred = be_transform_node(pred);
4412 ir_graph *irg = current_ir_graph;
4413 dbg_info *dbgi = get_irn_dbg_info(node);
4414 ir_mode *mode = get_irn_mode(node);
4415 long proj = get_Proj_proj(node);
4417 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4419 switch (get_irn_opcode(pred)) {
4423 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4425 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4433 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4435 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4443 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4444 case pn_DivMod_res_div:
4445 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4446 case pn_DivMod_res_mod:
4447 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4457 return new_rd_Unknown(irg, mode);
4461 * Transform and renumber the Projs from a CopyB.
4463 static ir_node *gen_Proj_CopyB(ir_node *node) {
4464 ir_node *block = be_transform_node(get_nodes_block(node));
4465 ir_node *pred = get_Proj_pred(node);
4466 ir_node *new_pred = be_transform_node(pred);
4467 ir_graph *irg = current_ir_graph;
4468 dbg_info *dbgi = get_irn_dbg_info(node);
4469 ir_mode *mode = get_irn_mode(node);
4470 long proj = get_Proj_proj(node);
4473 case pn_CopyB_M_regular:
4474 if (is_ia32_CopyB_i(new_pred)) {
4475 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4476 } else if (is_ia32_CopyB(new_pred)) {
4477 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4485 return new_rd_Unknown(irg, mode);
4489 * Transform and renumber the Projs from a Quot.
4491 static ir_node *gen_Proj_Quot(ir_node *node) {
4492 ir_node *block = be_transform_node(get_nodes_block(node));
4493 ir_node *pred = get_Proj_pred(node);
4494 ir_node *new_pred = be_transform_node(pred);
4495 ir_graph *irg = current_ir_graph;
4496 dbg_info *dbgi = get_irn_dbg_info(node);
4497 ir_mode *mode = get_irn_mode(node);
4498 long proj = get_Proj_proj(node);
4502 if (is_ia32_xDiv(new_pred)) {
4503 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4504 } else if (is_ia32_vfdiv(new_pred)) {
4505 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4509 if (is_ia32_xDiv(new_pred)) {
4510 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4511 } else if (is_ia32_vfdiv(new_pred)) {
4512 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4520 return new_rd_Unknown(irg, mode);
4524 * Transform the Thread Local Storage Proj.
4526 static ir_node *gen_Proj_tls(ir_node *node) {
4527 ir_node *block = be_transform_node(get_nodes_block(node));
4528 ir_graph *irg = current_ir_graph;
4529 dbg_info *dbgi = NULL;
4530 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4535 static ir_node *gen_be_Call(ir_node *node) {
4536 ir_node *res = be_duplicate_node(node);
4537 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4542 static ir_node *gen_be_IncSP(ir_node *node) {
4543 ir_node *res = be_duplicate_node(node);
4544 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4550 * Transform the Projs from a be_Call.
4552 static ir_node *gen_Proj_be_Call(ir_node *node) {
4553 ir_node *block = be_transform_node(get_nodes_block(node));
4554 ir_node *call = get_Proj_pred(node);
4555 ir_node *new_call = be_transform_node(call);
4556 ir_graph *irg = current_ir_graph;
4557 dbg_info *dbgi = get_irn_dbg_info(node);
4558 ir_type *method_type = be_Call_get_type(call);
4559 int n_res = get_method_n_ress(method_type);
4560 long proj = get_Proj_proj(node);
4561 ir_mode *mode = get_irn_mode(node);
4563 const arch_register_class_t *cls;
4565 /* The following is kinda tricky: If we're using SSE, then we have to
4566 * move the result value of the call in floating point registers to an
4567 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4568 * after the call, we have to make sure to correctly make the
4569 * MemProj and the result Proj use these 2 nodes
4571 if (proj == pn_be_Call_M_regular) {
4572 // get new node for result, are we doing the sse load/store hack?
4573 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4574 ir_node *call_res_new;
4575 ir_node *call_res_pred = NULL;
4577 if (call_res != NULL) {
4578 call_res_new = be_transform_node(call_res);
4579 call_res_pred = get_Proj_pred(call_res_new);
4582 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4583 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4584 pn_be_Call_M_regular);
4586 assert(is_ia32_xLoad(call_res_pred));
4587 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4591 if (ia32_cg_config.use_sse2 && proj >= pn_be_Call_first_res
4592 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)) {
4594 ir_node *frame = get_irg_frame(irg);
4595 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4597 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4600 /* in case there is no memory output: create one to serialize the copy
4602 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4603 pn_be_Call_M_regular);
4604 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4605 pn_be_Call_first_res);
4607 /* store st(0) onto stack */
4608 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4610 set_ia32_op_type(fstp, ia32_AddrModeD);
4611 set_ia32_use_frame(fstp);
4613 /* load into SSE register */
4614 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4616 set_ia32_op_type(sse_load, ia32_AddrModeS);
4617 set_ia32_use_frame(sse_load);
4619 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4625 /* transform call modes */
4626 if (mode_is_data(mode)) {
4627 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4631 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4635 * Transform the Projs from a Cmp.
4637 static ir_node *gen_Proj_Cmp(ir_node *node)
4639 /* this probably means not all mode_b nodes were lowered... */
4640 panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
4645 * Transform and potentially renumber Proj nodes.
4647 static ir_node *gen_Proj(ir_node *node) {
4648 ir_graph *irg = current_ir_graph;
4649 dbg_info *dbgi = get_irn_dbg_info(node);
4650 ir_node *pred = get_Proj_pred(node);
4651 long proj = get_Proj_proj(node);
4653 if (is_Store(pred)) {
4654 if (proj == pn_Store_M) {
4655 return be_transform_node(pred);
4658 return new_r_Bad(irg);
4660 } else if (is_Load(pred)) {
4661 return gen_Proj_Load(node);
4662 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4663 return gen_Proj_DivMod(node);
4664 } else if (is_CopyB(pred)) {
4665 return gen_Proj_CopyB(node);
4666 } else if (is_Quot(pred)) {
4667 return gen_Proj_Quot(node);
4668 } else if (be_is_SubSP(pred)) {
4669 return gen_Proj_be_SubSP(node);
4670 } else if (be_is_AddSP(pred)) {
4671 return gen_Proj_be_AddSP(node);
4672 } else if (be_is_Call(pred)) {
4673 return gen_Proj_be_Call(node);
4674 } else if (is_Cmp(pred)) {
4675 return gen_Proj_Cmp(node);
4676 } else if (get_irn_op(pred) == op_Start) {
4677 if (proj == pn_Start_X_initial_exec) {
4678 ir_node *block = get_nodes_block(pred);
4681 /* we exchange the ProjX with a jump */
4682 block = be_transform_node(block);
4683 jump = new_rd_Jmp(dbgi, irg, block);
4686 if (node == be_get_old_anchor(anchor_tls)) {
4687 return gen_Proj_tls(node);
4690 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4694 ir_node *new_pred = be_transform_node(pred);
4695 ir_node *block = be_transform_node(get_nodes_block(node));
4696 ir_mode *mode = get_irn_mode(node);
4697 if (mode_needs_gp_reg(mode)) {
4698 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4699 get_Proj_proj(node));
4700 #ifdef DEBUG_libfirm
4701 new_proj->node_nr = node->node_nr;
4707 return be_duplicate_node(node);
4711 * Enters all transform functions into the generic pointer
4713 static void register_transformers(void)
4717 /* first clear the generic function pointer for all ops */
4718 clear_irp_opcodes_generic_func();
4720 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4721 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4759 /* transform ops from intrinsic lowering */
4775 GEN(ia32_l_X87toSSE);
4776 GEN(ia32_l_SSEtoX87);
4782 /* we should never see these nodes */
4797 /* handle generic backend nodes */
4806 op_Mulh = get_op_Mulh();
4815 * Pre-transform all unknown and noreg nodes.
4817 static void ia32_pretransform_node(void *arch_cg) {
4818 ia32_code_gen_t *cg = arch_cg;
4820 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4821 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4822 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4823 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4824 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4825 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4830 * Walker, checks if all ia32 nodes producing more than one result have
4831 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4833 static void add_missing_keep_walker(ir_node *node, void *data)
4836 unsigned found_projs = 0;
4837 const ir_edge_t *edge;
4838 ir_mode *mode = get_irn_mode(node);
4843 if(!is_ia32_irn(node))
4846 n_outs = get_ia32_n_res(node);
4849 if(is_ia32_SwitchJmp(node))
4852 assert(n_outs < (int) sizeof(unsigned) * 8);
4853 foreach_out_edge(node, edge) {
4854 ir_node *proj = get_edge_src_irn(edge);
4855 int pn = get_Proj_proj(proj);
4857 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4858 found_projs |= 1 << pn;
4862 /* are keeps missing? */
4864 for(i = 0; i < n_outs; ++i) {
4867 const arch_register_req_t *req;
4868 const arch_register_class_t *class;
4870 if(found_projs & (1 << i)) {
4874 req = get_ia32_out_req(node, i);
4879 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4883 block = get_nodes_block(node);
4884 in[0] = new_r_Proj(current_ir_graph, block, node,
4885 arch_register_class_mode(class), i);
4886 if(last_keep != NULL) {
4887 be_Keep_add_node(last_keep, class, in[0]);
4889 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4890 if(sched_is_scheduled(node)) {
4891 sched_add_after(node, last_keep);
4898 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4901 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4903 ir_graph *irg = be_get_birg_irg(cg->birg);
4904 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4907 /* do the transformation */
4908 void ia32_transform_graph(ia32_code_gen_t *cg) {
4910 ir_graph *irg = cg->irg;
4912 register_transformers();
4914 initial_fpcw = NULL;
4916 heights = heights_new(irg);
4917 ia32_calculate_non_address_mode_nodes(cg->birg);
4919 /* the transform phase is not safe for CSE (yet) because several nodes get
4920 * attributes set after their creation */
4921 cse_last = get_opt_cse();
4924 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4926 set_opt_cse(cse_last);
4928 ia32_free_non_address_mode_nodes();
4929 heights_free(heights);
4933 void ia32_init_transform(void)
4935 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");