2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
98 static transform_config_t transform_config;
100 extern ir_op *get_op_Mulh(void);
102 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
103 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
104 ir_node *op1, ir_node *op2);
106 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
107 ir_node *block, ir_node *op1, ir_node *op2);
109 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
110 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
113 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
114 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
116 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
117 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
118 ir_node *op1, ir_node *op2, ir_node *fpcw);
120 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
121 ir_node *block, ir_node *op);
123 /****************************************************************************************************
125 * | | | | / _| | | (_)
126 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
127 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
128 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
129 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
131 ****************************************************************************************************/
133 static ir_node *try_create_Immediate(ir_node *node,
134 char immediate_constraint_type);
136 static ir_node *create_immediate_or_transform(ir_node *node,
137 char immediate_constraint_type);
139 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
140 dbg_info *dbgi, ir_node *block,
141 ir_node *op, ir_node *orig_node);
144 * Return true if a mode can be stored in the GP register set
146 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
147 if(mode == mode_fpcw)
149 if(get_mode_size_bits(mode) > 32)
151 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
155 * creates a unique ident by adding a number to a tag
157 * @param tag the tag string, must contain a %d if a number
160 static ident *unique_id(const char *tag)
162 static unsigned id = 0;
165 snprintf(str, sizeof(str), tag, ++id);
166 return new_id_from_str(str);
170 * Get a primitive type for a mode.
172 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
174 pmap_entry *e = pmap_find(types, mode);
179 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
180 res = new_type_primitive(new_id_from_str(buf), mode);
181 set_type_alignment_bytes(res, 16);
182 pmap_insert(types, mode, res);
190 * Get an atomic entity that is initialized with a tarval
192 static ir_entity *create_float_const_entity(ir_node *cnst)
194 ia32_isa_t *isa = env_cg->isa;
195 tarval *tv = get_Const_tarval(cnst);
196 pmap_entry *e = pmap_find(isa->tv_ent, tv);
201 ir_mode *mode = get_irn_mode(cnst);
202 ir_type *tp = get_Const_type(cnst);
203 if (tp == firm_unknown_type)
204 tp = get_prim_type(isa->types, mode);
206 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
208 set_entity_ld_ident(res, get_entity_ident(res));
209 set_entity_visibility(res, visibility_local);
210 set_entity_variability(res, variability_constant);
211 set_entity_allocation(res, allocation_static);
213 /* we create a new entity here: It's initialization must resist on the
215 rem = current_ir_graph;
216 current_ir_graph = get_const_code_irg();
217 set_atomic_ent_value(res, new_Const_type(tv, tp));
218 current_ir_graph = rem;
220 pmap_insert(isa->tv_ent, tv, res);
228 static int is_Const_0(ir_node *node) {
229 return is_Const(node) && is_Const_null(node);
232 static int is_Const_1(ir_node *node) {
233 return is_Const(node) && is_Const_one(node);
236 static int is_Const_Minus_1(ir_node *node) {
237 return is_Const(node) && is_Const_all_one(node);
241 * returns true if constant can be created with a simple float command
243 static int is_simple_x87_Const(ir_node *node)
245 tarval *tv = get_Const_tarval(node);
247 if(tarval_is_null(tv) || tarval_is_one(tv))
250 /* TODO: match all the other float constants */
255 * Transforms a Const.
257 static ir_node *gen_Const(ir_node *node) {
258 ir_graph *irg = current_ir_graph;
259 ir_node *old_block = get_nodes_block(node);
260 ir_node *block = be_transform_node(old_block);
261 dbg_info *dbgi = get_irn_dbg_info(node);
262 ir_mode *mode = get_irn_mode(node);
264 if (mode_is_float(mode)) {
266 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
267 ir_node *nomem = new_NoMem();
271 if (USE_SSE2(env_cg)) {
272 if (is_Const_null(node)) {
273 load = new_rd_ia32_xZero(dbgi, irg, block);
274 set_ia32_ls_mode(load, mode);
277 floatent = create_float_const_entity(node);
279 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
287 if (is_Const_null(node)) {
288 load = new_rd_ia32_vfldz(dbgi, irg, block);
290 } else if (is_Const_one(node)) {
291 load = new_rd_ia32_vfld1(dbgi, irg, block);
294 floatent = create_float_const_entity(node);
296 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
297 set_ia32_op_type(load, ia32_AddrModeS);
298 set_ia32_am_sc(load, floatent);
299 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
300 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
302 set_ia32_ls_mode(load, mode);
305 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
307 /* Const Nodes before the initial IncSP are a bad idea, because
308 * they could be spilled and we have no SP ready at that point yet.
309 * So add a dependency to the initial frame pointer calculation to
310 * avoid that situation.
312 if (get_irg_start_block(irg) == block) {
313 add_irn_dep(load, get_irg_frame(irg));
316 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
320 tarval *tv = get_Const_tarval(node);
323 tv = tarval_convert_to(tv, mode_Iu);
325 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
327 panic("couldn't convert constant tarval (%+F)", node);
329 val = get_tarval_long(tv);
331 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
332 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
335 if (get_irg_start_block(irg) == block) {
336 add_irn_dep(cnst, get_irg_frame(irg));
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *old_block = get_nodes_block(node);
349 ir_node *block = be_transform_node(old_block);
350 dbg_info *dbgi = get_irn_dbg_info(node);
351 ir_mode *mode = get_irn_mode(node);
354 if (mode_is_float(mode)) {
355 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
356 ir_node *nomem = new_NoMem();
358 if (USE_SSE2(env_cg))
359 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
361 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
362 set_ia32_am_sc(cnst, get_SymConst_entity(node));
363 set_ia32_use_frame(cnst);
367 if(get_SymConst_kind(node) != symconst_addr_ent) {
368 panic("backend only support symconst_addr_ent (at %+F)", node);
370 entity = get_SymConst_entity(node);
371 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
374 /* Const Nodes before the initial IncSP are a bad idea, because
375 * they could be spilled and we have no SP ready at that point yet
377 if (get_irg_start_block(irg) == block) {
378 add_irn_dep(cnst, get_irg_frame(irg));
381 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
386 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
387 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
388 static const struct {
390 const char *ent_name;
391 const char *cnst_str;
394 } names [ia32_known_const_max] = {
395 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
396 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
397 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
398 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
399 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
401 static ir_entity *ent_cache[ia32_known_const_max];
403 const char *tp_name, *ent_name, *cnst_str;
411 ent_name = names[kct].ent_name;
412 if (! ent_cache[kct]) {
413 tp_name = names[kct].tp_name;
414 cnst_str = names[kct].cnst_str;
416 switch (names[kct].mode) {
417 case 0: mode = mode_Iu; break;
418 case 1: mode = mode_Lu; break;
419 default: mode = mode_F; break;
421 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
422 tp = new_type_primitive(new_id_from_str(tp_name), mode);
423 /* set the specified alignment */
424 set_type_alignment_bytes(tp, names[kct].align);
426 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
428 set_entity_ld_ident(ent, get_entity_ident(ent));
429 set_entity_visibility(ent, visibility_local);
430 set_entity_variability(ent, variability_constant);
431 set_entity_allocation(ent, allocation_static);
433 /* we create a new entity here: It's initialization must resist on the
435 rem = current_ir_graph;
436 current_ir_graph = get_const_code_irg();
437 cnst = new_Const(mode, tv);
438 current_ir_graph = rem;
440 set_atomic_ent_value(ent, cnst);
442 /* cache the entry */
443 ent_cache[kct] = ent;
446 return ent_cache[kct];
451 * Prints the old node name on cg obst and returns a pointer to it.
453 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
454 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
456 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
457 obstack_1grow(isa->name_obst, 0);
458 return obstack_finish(isa->name_obst);
462 int use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
464 ir_mode *mode = get_irn_mode(node);
468 /* float constants are always available */
469 if(is_Const(node) && mode_is_float(mode)
470 && !is_simple_x87_Const(node) && get_irn_n_edges(node) == 1) {
476 load = get_Proj_pred(node);
477 pn = get_Proj_proj(node);
478 if(!is_Load(load) || pn != pn_Load_res)
480 if(get_nodes_block(load) != block)
482 /* we only use address mode if we're the only user of the load */
483 if(get_irn_n_edges(node) > 1)
486 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
489 /* don't do AM if other node inputs depend on the load (via mem-proj) */
490 if(other != NULL && get_nodes_block(other) == block
491 && heights_reachable_in_block(heights, other, load))
497 typedef struct ia32_address_mode_t ia32_address_mode_t;
498 struct ia32_address_mode_t {
502 ia32_op_type_t op_type;
509 static void build_address(ia32_address_mode_t *am, ir_node *node)
511 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
512 ia32_address_t *addr = &am->addr;
521 ir_entity *entity = create_float_const_entity(node);
522 addr->base = noreg_gp;
523 addr->index = noreg_gp;
524 addr->mem = new_NoMem();
525 addr->symconst_ent = entity;
527 am->ls_mode = get_irn_mode(node);
531 load = get_Proj_pred(node);
532 ptr = get_Load_ptr(load);
533 mem = get_Load_mem(load);
534 new_mem = be_transform_node(mem);
535 am->ls_mode = get_Load_mode(load);
536 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
538 /* construct load address */
539 ia32_create_address_mode(addr, ptr, 0);
546 base = be_transform_node(base);
552 index = be_transform_node(index);
560 static void set_address(ir_node *node, ia32_address_t *addr)
562 set_ia32_am_scale(node, addr->scale);
563 set_ia32_am_sc(node, addr->symconst_ent);
564 set_ia32_am_offs_int(node, addr->offset);
565 if(addr->symconst_sign)
566 set_ia32_am_sc_sign(node);
568 set_ia32_use_frame(node);
569 set_ia32_frame_ent(node, addr->frame_entity);
572 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
574 set_address(node, &am->addr);
576 set_ia32_op_type(node, am->op_type);
577 set_ia32_ls_mode(node, am->ls_mode);
579 set_ia32_commutative(node);
583 match_commutative = 1 << 0,
584 match_am_and_immediates = 1 << 1,
585 match_no_am = 1 << 2,
586 match_8_16_bit_am = 1 << 3,
587 match_no_immediate = 1 << 4
590 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
591 ir_node *op1, ir_node *op2, match_flags_t flags)
593 ia32_address_t *addr = &am->addr;
594 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
597 ir_mode *mode = get_irn_mode(op2);
600 int use_am_and_immediates;
603 memset(am, 0, sizeof(am[0]));
605 commutative = (flags & match_commutative) != 0;
606 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
607 use_am = ! (flags & match_no_am);
608 use_immediate = !(flags & match_no_immediate);
611 assert(!commutative || op1 != NULL);
613 if(!(flags & match_8_16_bit_am)
614 && get_mode_size_bits(mode) < 32)
617 new_op2 = (use_immediate ? try_create_Immediate(op2, 0) : NULL);
618 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
619 build_address(am, op2);
620 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
621 if(mode_is_float(mode)) {
622 new_op2 = ia32_new_NoReg_vfp(env_cg);
626 am->op_type = ia32_AddrModeS;
627 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
628 use_am && use_source_address_mode(block, op1, op2)) {
630 build_address(am, op1);
632 if(mode_is_float(mode)) {
633 noreg = ia32_new_NoReg_vfp(env_cg);
638 if(new_op2 != NULL) {
641 new_op1 = be_transform_node(op2);
645 am->op_type = ia32_AddrModeS;
647 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
649 new_op2 = be_transform_node(op2);
650 am->op_type = ia32_Normal;
652 if(addr->base == NULL)
653 addr->base = noreg_gp;
654 if(addr->index == NULL)
655 addr->index = noreg_gp;
656 if(addr->mem == NULL)
657 addr->mem = new_NoMem();
659 am->new_op1 = new_op1;
660 am->new_op2 = new_op2;
661 am->commutative = commutative;
664 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
666 ir_graph *irg = current_ir_graph;
670 if(am->mem_proj == NULL)
673 /* we have to create a mode_T so the old MemProj can attach to us */
674 mode = get_irn_mode(node);
675 load = get_Proj_pred(am->mem_proj);
677 mark_irn_visited(load);
678 be_set_transformed_node(load, node);
681 set_irn_mode(node, mode_T);
682 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
689 * Construct a standard binary operation, set AM and immediate if required.
691 * @param op1 The first operand
692 * @param op2 The second operand
693 * @param func The node constructor function
694 * @return The constructed ia32 node.
696 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
697 construct_binop_func *func, int commutative)
699 ir_node *src_block = get_nodes_block(node);
700 ir_node *block = be_transform_node(src_block);
701 ir_graph *irg = current_ir_graph;
702 dbg_info *dbgi = get_irn_dbg_info(node);
704 ia32_address_mode_t am;
705 ia32_address_t *addr = &am.addr;
706 match_flags_t flags = 0;
709 flags |= match_commutative;
711 match_arguments(&am, src_block, op1, op2, flags);
713 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
714 am.new_op1, am.new_op2);
715 set_am_attributes(new_node, &am);
716 /* we can't use source address mode anymore when using immediates */
717 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
718 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
719 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
721 new_node = fix_mem_proj(new_node, &am);
727 * Construct a standard binary operation, set AM and immediate if required.
729 * @param op1 The first operand
730 * @param op2 The second operand
731 * @param func The node constructor function
732 * @return The constructed ia32 node.
734 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
735 construct_binop_func *func,
738 ir_node *block = be_transform_node(get_nodes_block(node));
739 ir_node *new_op1 = be_transform_node(op1);
740 ir_node *new_op2 = be_transform_node(op2);
741 ir_node *new_node = NULL;
742 dbg_info *dbgi = get_irn_dbg_info(node);
743 ir_graph *irg = current_ir_graph;
744 ir_mode *mode = get_irn_mode(node);
745 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
746 ir_node *nomem = new_NoMem();
748 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
751 set_ia32_commutative(new_node);
753 set_ia32_ls_mode(new_node, mode);
755 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
760 static ir_node *get_fpcw(void)
763 if(initial_fpcw != NULL)
766 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
767 &ia32_fp_cw_regs[REG_FPCW]);
768 initial_fpcw = be_transform_node(fpcw);
774 * Construct a standard binary operation, set AM and immediate if required.
776 * @param op1 The first operand
777 * @param op2 The second operand
778 * @param func The node constructor function
779 * @return The constructed ia32 node.
781 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
782 construct_binop_float_func *func,
785 ir_graph *irg = current_ir_graph;
786 dbg_info *dbgi = get_irn_dbg_info(node);
787 ir_node *src_block = get_nodes_block(node);
788 ir_node *new_block = be_transform_node(src_block);
790 ia32_address_mode_t am;
791 ia32_address_t *addr = &am.addr;
792 match_flags_t flags = 0;
795 flags |= match_commutative;
797 match_arguments(&am, src_block, op1, op2, flags);
799 new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
800 am.new_op1, am.new_op2, get_fpcw());
801 set_am_attributes(new_node, &am);
803 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
805 new_node = fix_mem_proj(new_node, &am);
811 * Construct a shift/rotate binary operation, sets AM and immediate if required.
813 * @param op1 The first operand
814 * @param op2 The second operand
815 * @param func The node constructor function
816 * @return The constructed ia32 node.
818 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
819 construct_shift_func *func)
821 dbg_info *dbgi = get_irn_dbg_info(node);
822 ir_graph *irg = current_ir_graph;
823 ir_node *block = get_nodes_block(node);
824 ir_node *new_block = be_transform_node(block);
825 ir_node *new_op1 = be_transform_node(op1);
826 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
829 assert(! mode_is_float(get_irn_mode(node))
830 && "Shift/Rotate with float not supported");
832 res = func(dbgi, irg, new_block, new_op1, new_op2);
833 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
835 /* lowered shift instruction may have a dependency operand, handle it here */
836 if (get_irn_arity(node) == 3) {
837 /* we have a dependency */
838 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
839 add_irn_dep(res, new_dep);
847 * Construct a standard unary operation, set AM and immediate if required.
849 * @param op The operand
850 * @param func The node constructor function
851 * @return The constructed ia32 node.
853 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
855 ir_node *block = be_transform_node(get_nodes_block(node));
856 ir_node *new_op = be_transform_node(op);
857 ir_node *new_node = NULL;
858 ir_graph *irg = current_ir_graph;
859 dbg_info *dbgi = get_irn_dbg_info(node);
861 new_node = func(dbgi, irg, block, new_op);
863 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
868 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
869 ia32_address_t *addr)
871 ir_graph *irg = current_ir_graph;
872 ir_node *base = addr->base;
873 ir_node *index = addr->index;
877 base = ia32_new_NoReg_gp(env_cg);
879 base = be_transform_node(base);
883 index = ia32_new_NoReg_gp(env_cg);
885 index = be_transform_node(index);
888 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
889 set_address(res, addr);
894 static int am_has_immediates(const ia32_address_t *addr)
896 return addr->offset != 0 || addr->symconst_ent != NULL
897 || addr->frame_entity || addr->use_frame;
901 * Creates an ia32 Add.
903 * @return the created ia32 Add node
905 static ir_node *gen_Add(ir_node *node) {
906 ir_node *block = be_transform_node(get_nodes_block(node));
907 ir_node *op1 = get_Add_left(node);
908 ir_node *op2 = get_Add_right(node);
911 ir_graph *irg = current_ir_graph;
912 dbg_info *dbgi = get_irn_dbg_info(node);
913 ir_mode *mode = get_irn_mode(node);
914 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
915 ir_node *src_block = get_nodes_block(node);
916 ir_node *add_immediate_op;
918 ia32_address_mode_t am;
920 if (mode_is_float(mode)) {
921 if (USE_SSE2(env_cg))
922 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd, 1);
924 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd, 1);
929 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
930 * 1. Add with immediate -> Lea
931 * 2. Add with possible source address mode -> Add
932 * 3. Otherwise -> Lea
934 memset(&addr, 0, sizeof(addr));
935 ia32_create_address_mode(&addr, node, 1);
936 add_immediate_op = NULL;
938 if(addr.base == NULL && addr.index == NULL) {
939 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
940 addr.symconst_sign, addr.offset);
941 add_irn_dep(new_op, get_irg_frame(irg));
942 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
945 /* add with immediate? */
946 if(addr.index == NULL) {
947 add_immediate_op = addr.base;
948 } else if(addr.base == NULL && addr.scale == 0) {
949 add_immediate_op = addr.index;
952 if(add_immediate_op != NULL) {
953 if(!am_has_immediates(&addr)) {
955 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
958 return be_transform_node(add_immediate_op);
961 new_op = create_lea_from_address(dbgi, block, &addr);
962 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
966 /* test if we can use source address mode */
967 memset(&am, 0, sizeof(am));
969 if(use_source_address_mode(src_block, op2, op1)) {
970 build_address(&am, op2);
971 new_op1 = be_transform_node(op1);
972 } else if(use_source_address_mode(src_block, op1, op2)) {
973 build_address(&am, op1);
974 new_op1 = be_transform_node(op2);
976 /* construct an Add with source address mode */
977 if(new_op1 != NULL) {
978 ia32_address_t *am_addr = &am.addr;
979 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
980 am_addr->mem, new_op1, noreg);
981 set_address(new_op, am_addr);
982 set_ia32_op_type(new_op, ia32_AddrModeS);
983 set_ia32_ls_mode(new_op, am.ls_mode);
984 set_ia32_commutative(new_op);
985 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
987 new_op = fix_mem_proj(new_op, &am);
992 /* otherwise construct a lea */
993 new_op = create_lea_from_address(dbgi, block, &addr);
994 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
999 * Creates an ia32 Mul.
1001 * @return the created ia32 Mul node
1003 static ir_node *gen_Mul(ir_node *node) {
1004 ir_node *op1 = get_Mul_left(node);
1005 ir_node *op2 = get_Mul_right(node);
1006 ir_mode *mode = get_irn_mode(node);
1008 if (mode_is_float(mode)) {
1009 if (USE_SSE2(env_cg))
1010 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul, 1);
1012 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul, 1);
1016 for the lower 32bit of the result it doesn't matter whether we use
1017 signed or unsigned multiplication so we use IMul as it has fewer
1020 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
1024 * Creates an ia32 Mulh.
1025 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1026 * this result while Mul returns the lower 32 bit.
1028 * @return the created ia32 Mulh node
1030 static ir_node *gen_Mulh(ir_node *node) {
1031 ir_node *block = be_transform_node(get_nodes_block(node));
1032 ir_node *op1 = get_irn_n(node, 0);
1033 ir_node *new_op1 = be_transform_node(op1);
1034 ir_node *op2 = get_irn_n(node, 1);
1035 ir_node *new_op2 = be_transform_node(op2);
1036 ir_graph *irg = current_ir_graph;
1037 dbg_info *dbgi = get_irn_dbg_info(node);
1038 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1039 ir_mode *mode = get_irn_mode(node);
1040 ir_node *proj_EDX, *res;
1042 assert(!mode_is_float(mode) && "Mulh with float not supported");
1043 if (mode_is_signed(mode)) {
1044 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
1047 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
1051 set_ia32_commutative(res);
1053 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1061 * Creates an ia32 And.
1063 * @return The created ia32 And node
1065 static ir_node *gen_And(ir_node *node) {
1066 ir_node *op1 = get_And_left(node);
1067 ir_node *op2 = get_And_right(node);
1068 assert(! mode_is_float(get_irn_mode(node)));
1070 /* is it a zero extension? */
1071 if (is_Const(op2)) {
1072 tarval *tv = get_Const_tarval(op2);
1073 long v = get_tarval_long(tv);
1075 if (v == 0xFF || v == 0xFFFF) {
1076 dbg_info *dbgi = get_irn_dbg_info(node);
1077 ir_node *block = get_nodes_block(node);
1084 assert(v == 0xFFFF);
1087 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1093 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1099 * Creates an ia32 Or.
1101 * @return The created ia32 Or node
1103 static ir_node *gen_Or(ir_node *node) {
1104 ir_node *op1 = get_Or_left(node);
1105 ir_node *op2 = get_Or_right(node);
1107 assert (! mode_is_float(get_irn_mode(node)));
1108 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1114 * Creates an ia32 Eor.
1116 * @return The created ia32 Eor node
1118 static ir_node *gen_Eor(ir_node *node) {
1119 ir_node *op1 = get_Eor_left(node);
1120 ir_node *op2 = get_Eor_right(node);
1122 assert(! mode_is_float(get_irn_mode(node)));
1123 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1128 * Creates an ia32 Sub.
1130 * @return The created ia32 Sub node
1132 static ir_node *gen_Sub(ir_node *node) {
1133 ir_node *op1 = get_Sub_left(node);
1134 ir_node *op2 = get_Sub_right(node);
1135 ir_mode *mode = get_irn_mode(node);
1137 if (mode_is_float(mode)) {
1138 if (USE_SSE2(env_cg))
1139 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub, 0);
1141 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub, 0);
1145 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1149 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1155 * Generates an ia32 DivMod with additional infrastructure for the
1156 * register allocator if needed.
1158 * @param dividend -no comment- :)
1159 * @param divisor -no comment- :)
1160 * @param dm_flav flavour_Div/Mod/DivMod
1161 * @return The created ia32 DivMod node
1163 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1164 ir_node *divisor, ia32_op_flavour_t dm_flav)
1166 ir_node *block = be_transform_node(get_nodes_block(node));
1167 ir_node *new_dividend = be_transform_node(dividend);
1168 ir_node *new_divisor = be_transform_node(divisor);
1169 ir_graph *irg = current_ir_graph;
1170 dbg_info *dbgi = get_irn_dbg_info(node);
1171 ir_mode *mode = get_irn_mode(node);
1172 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1173 ir_node *res, *proj_div, *proj_mod;
1174 ir_node *sign_extension;
1175 ir_node *mem, *new_mem;
1178 proj_div = proj_mod = NULL;
1182 mem = get_Div_mem(node);
1183 mode = get_Div_resmode(node);
1184 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1185 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1188 mem = get_Mod_mem(node);
1189 mode = get_Mod_resmode(node);
1190 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1191 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1193 case flavour_DivMod:
1194 mem = get_DivMod_mem(node);
1195 mode = get_DivMod_resmode(node);
1196 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1197 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1198 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1201 panic("invalid divmod flavour!");
1203 new_mem = be_transform_node(mem);
1205 if (mode_is_signed(mode)) {
1206 /* in signed mode, we need to sign extend the dividend */
1207 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1208 add_irn_dep(produceval, get_irg_frame(irg));
1209 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1212 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1213 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1214 add_irn_dep(sign_extension, get_irg_frame(irg));
1217 if (mode_is_signed(mode)) {
1218 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1219 new_dividend, sign_extension, new_divisor, dm_flav);
1221 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1222 sign_extension, new_divisor, dm_flav);
1225 set_ia32_exc_label(res, has_exc);
1226 set_irn_pinned(res, get_irn_pinned(node));
1228 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1235 * Wrapper for generate_DivMod. Sets flavour_Mod.
1238 static ir_node *gen_Mod(ir_node *node) {
1239 return generate_DivMod(node, get_Mod_left(node),
1240 get_Mod_right(node), flavour_Mod);
1244 * Wrapper for generate_DivMod. Sets flavour_Div.
1247 static ir_node *gen_Div(ir_node *node) {
1248 return generate_DivMod(node, get_Div_left(node),
1249 get_Div_right(node), flavour_Div);
1253 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1255 static ir_node *gen_DivMod(ir_node *node) {
1256 return generate_DivMod(node, get_DivMod_left(node),
1257 get_DivMod_right(node), flavour_DivMod);
1263 * Creates an ia32 floating Div.
1265 * @return The created ia32 xDiv node
1267 static ir_node *gen_Quot(ir_node *node)
1269 ir_node *op1 = get_Quot_left(node);
1270 ir_node *op2 = get_Quot_right(node);
1272 if (USE_SSE2(env_cg)) {
1273 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xDiv, 0);
1275 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, 0);
1281 * Creates an ia32 Shl.
1283 * @return The created ia32 Shl node
1285 static ir_node *gen_Shl(ir_node *node) {
1286 ir_node *right = get_Shl_right(node);
1288 /* test whether we can build a lea */
1289 if(is_Const(right)) {
1290 tarval *tv = get_Const_tarval(right);
1291 if(tarval_is_long(tv)) {
1292 long val = get_tarval_long(tv);
1293 if(val >= 0 && val <= 3) {
1294 ir_graph *irg = current_ir_graph;
1295 dbg_info *dbgi = get_irn_dbg_info(node);
1296 ir_node *block = be_transform_node(get_nodes_block(node));
1297 ir_node *base = ia32_new_NoReg_gp(env_cg);
1298 ir_node *index = be_transform_node(get_Shl_left(node));
1299 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1300 set_ia32_am_scale(res, val);
1301 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1307 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1314 * Creates an ia32 Shr.
1316 * @return The created ia32 Shr node
1318 static ir_node *gen_Shr(ir_node *node) {
1319 return gen_shift_binop(node, get_Shr_left(node),
1320 get_Shr_right(node), new_rd_ia32_Shr);
1326 * Creates an ia32 Sar.
1328 * @return The created ia32 Shrs node
1330 static ir_node *gen_Shrs(ir_node *node) {
1331 ir_node *left = get_Shrs_left(node);
1332 ir_node *right = get_Shrs_right(node);
1333 ir_mode *mode = get_irn_mode(node);
1334 if(is_Const(right) && mode == mode_Is) {
1335 tarval *tv = get_Const_tarval(right);
1336 long val = get_tarval_long(tv);
1338 /* this is a sign extension */
1339 ir_graph *irg = current_ir_graph;
1340 dbg_info *dbgi = get_irn_dbg_info(node);
1341 ir_node *block = be_transform_node(get_nodes_block(node));
1343 ir_node *new_op = be_transform_node(op);
1344 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1345 add_irn_dep(pval, get_irg_frame(irg));
1347 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1351 /* 8 or 16 bit sign extension? */
1352 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1353 ir_node *shl_left = get_Shl_left(left);
1354 ir_node *shl_right = get_Shl_right(left);
1355 if(is_Const(shl_right)) {
1356 tarval *tv1 = get_Const_tarval(right);
1357 tarval *tv2 = get_Const_tarval(shl_right);
1358 if(tv1 == tv2 && tarval_is_long(tv1)) {
1359 long val = get_tarval_long(tv1);
1360 if(val == 16 || val == 24) {
1361 dbg_info *dbgi = get_irn_dbg_info(node);
1362 ir_node *block = get_nodes_block(node);
1372 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1381 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1387 * Creates an ia32 RotL.
1389 * @param op1 The first operator
1390 * @param op2 The second operator
1391 * @return The created ia32 RotL node
1393 static ir_node *gen_RotL(ir_node *node,
1394 ir_node *op1, ir_node *op2) {
1395 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1401 * Creates an ia32 RotR.
1402 * NOTE: There is no RotR with immediate because this would always be a RotL
1403 * "imm-mode_size_bits" which can be pre-calculated.
1405 * @param op1 The first operator
1406 * @param op2 The second operator
1407 * @return The created ia32 RotR node
1409 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1411 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1417 * Creates an ia32 RotR or RotL (depending on the found pattern).
1419 * @return The created ia32 RotL or RotR node
1421 static ir_node *gen_Rot(ir_node *node) {
1422 ir_node *rotate = NULL;
1423 ir_node *op1 = get_Rot_left(node);
1424 ir_node *op2 = get_Rot_right(node);
1426 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1427 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1428 that means we can create a RotR instead of an Add and a RotL */
1430 if (get_irn_op(op2) == op_Add) {
1432 ir_node *left = get_Add_left(add);
1433 ir_node *right = get_Add_right(add);
1434 if (is_Const(right)) {
1435 tarval *tv = get_Const_tarval(right);
1436 ir_mode *mode = get_irn_mode(node);
1437 long bits = get_mode_size_bits(mode);
1439 if (get_irn_op(left) == op_Minus &&
1440 tarval_is_long(tv) &&
1441 get_tarval_long(tv) == bits)
1443 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1444 rotate = gen_RotR(node, op1, get_Minus_op(left));
1449 if (rotate == NULL) {
1450 rotate = gen_RotL(node, op1, op2);
1459 * Transforms a Minus node.
1461 * @return The created ia32 Minus node
1463 static ir_node *gen_Minus(ir_node *node)
1465 ir_node *op = get_Minus_op(node);
1466 ir_node *block = be_transform_node(get_nodes_block(node));
1467 ir_graph *irg = current_ir_graph;
1468 dbg_info *dbgi = get_irn_dbg_info(node);
1469 ir_mode *mode = get_irn_mode(node);
1474 if (mode_is_float(mode)) {
1475 ir_node *new_op = be_transform_node(op);
1476 if (USE_SSE2(env_cg)) {
1477 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1478 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1479 ir_node *nomem = new_rd_NoMem(irg);
1481 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1484 size = get_mode_size_bits(mode);
1485 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1487 set_ia32_am_sc(res, ent);
1488 set_ia32_op_type(res, ia32_AddrModeS);
1489 set_ia32_ls_mode(res, mode);
1491 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1494 res = gen_unop(node, op, new_rd_ia32_Neg);
1497 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1503 * Transforms a Not node.
1505 * @return The created ia32 Not node
1507 static ir_node *gen_Not(ir_node *node) {
1508 ir_node *op = get_Not_op(node);
1509 ir_mode *mode = get_irn_mode(node);
1511 assert(mode != mode_b); /* should be lowered already */
1513 assert (! mode_is_float(get_irn_mode(node)));
1514 return gen_unop(node, op, new_rd_ia32_Not);
1520 * Transforms an Abs node.
1522 * @return The created ia32 Abs node
1524 static ir_node *gen_Abs(ir_node *node)
1526 ir_node *block = be_transform_node(get_nodes_block(node));
1527 ir_node *op = get_Abs_op(node);
1528 ir_node *new_op = be_transform_node(op);
1529 ir_graph *irg = current_ir_graph;
1530 dbg_info *dbgi = get_irn_dbg_info(node);
1531 ir_mode *mode = get_irn_mode(node);
1532 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1533 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1534 ir_node *nomem = new_NoMem();
1539 if (mode_is_float(mode)) {
1540 if (USE_SSE2(env_cg)) {
1541 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1543 size = get_mode_size_bits(mode);
1544 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1546 set_ia32_am_sc(res, ent);
1548 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1550 set_ia32_op_type(res, ia32_AddrModeS);
1551 set_ia32_ls_mode(res, mode);
1553 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1554 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1558 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1559 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1562 add_irn_dep(pval, get_irg_frame(irg));
1563 SET_IA32_ORIG_NODE(sign_extension,
1564 ia32_get_old_node_name(env_cg, node));
1566 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1568 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1570 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1572 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1579 * Transforms a Load.
1581 * @return the created ia32 Load node
1583 static ir_node *gen_Load(ir_node *node) {
1584 ir_node *old_block = get_nodes_block(node);
1585 ir_node *block = be_transform_node(old_block);
1586 ir_node *ptr = get_Load_ptr(node);
1587 ir_node *mem = get_Load_mem(node);
1588 ir_node *new_mem = be_transform_node(mem);
1591 ir_graph *irg = current_ir_graph;
1592 dbg_info *dbgi = get_irn_dbg_info(node);
1593 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1594 ir_mode *mode = get_Load_mode(node);
1597 ia32_address_t addr;
1599 /* construct load address */
1600 memset(&addr, 0, sizeof(addr));
1601 ia32_create_address_mode(&addr, ptr, 0);
1608 base = be_transform_node(base);
1614 index = be_transform_node(index);
1617 if (mode_is_float(mode)) {
1618 if (USE_SSE2(env_cg)) {
1619 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1621 res_mode = mode_xmm;
1623 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1625 res_mode = mode_vfp;
1631 /* create a conv node with address mode for smaller modes */
1632 if(get_mode_size_bits(mode) < 32) {
1633 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
1634 new_mem, noreg, mode);
1636 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1641 set_irn_pinned(new_op, get_irn_pinned(node));
1642 set_ia32_op_type(new_op, ia32_AddrModeS);
1643 set_ia32_ls_mode(new_op, mode);
1644 set_address(new_op, &addr);
1646 /* make sure we are scheduled behind the initial IncSP/Barrier
1647 * to avoid spills being placed before it
1649 if (block == get_irg_start_block(irg)) {
1650 add_irn_dep(new_op, get_irg_frame(irg));
1653 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1654 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1659 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1660 ir_node *ptr, ir_mode *mode, ir_node *other)
1667 /* we only use address mode if we're the only user of the load */
1668 if(get_irn_n_edges(node) > 1)
1671 load = get_Proj_pred(node);
1674 if(get_nodes_block(load) != block)
1677 /* Store should be attached to the load */
1678 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1680 /* store should have the same pointer as the load */
1681 if(get_Load_ptr(load) != ptr)
1684 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1685 if(other != NULL && get_nodes_block(other) == block
1686 && heights_reachable_in_block(heights, other, load))
1689 assert(get_Load_mode(load) == mode);
1694 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1695 ir_node *mem, ir_node *ptr, ir_mode *mode,
1696 construct_binop_dest_func *func,
1697 construct_binop_dest_func *func8bit,
1700 ir_node *src_block = get_nodes_block(node);
1702 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1703 ir_graph *irg = current_ir_graph;
1707 ia32_address_mode_t am;
1708 ia32_address_t *addr = &am.addr;
1709 memset(&am, 0, sizeof(am));
1711 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1712 build_address(&am, op1);
1713 new_op = create_immediate_or_transform(op2, 0);
1714 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1715 build_address(&am, op2);
1716 new_op = create_immediate_or_transform(op1, 0);
1721 if(addr->base == NULL)
1722 addr->base = noreg_gp;
1723 if(addr->index == NULL)
1724 addr->index = noreg_gp;
1725 if(addr->mem == NULL)
1726 addr->mem = new_NoMem();
1728 dbgi = get_irn_dbg_info(node);
1729 block = be_transform_node(src_block);
1730 if(get_mode_size_bits(mode) == 8) {
1731 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1734 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1737 set_address(new_node, addr);
1738 set_ia32_op_type(new_node, ia32_AddrModeD);
1739 set_ia32_ls_mode(new_node, mode);
1740 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1745 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1746 ir_node *ptr, ir_mode *mode,
1747 construct_unop_dest_func *func)
1749 ir_node *src_block = get_nodes_block(node);
1751 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1752 ir_graph *irg = current_ir_graph;
1755 ia32_address_mode_t am;
1756 ia32_address_t *addr = &am.addr;
1757 memset(&am, 0, sizeof(am));
1759 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1762 build_address(&am, op);
1764 if(addr->base == NULL)
1765 addr->base = noreg_gp;
1766 if(addr->index == NULL)
1767 addr->index = noreg_gp;
1768 if(addr->mem == NULL)
1769 addr->mem = new_NoMem();
1771 dbgi = get_irn_dbg_info(node);
1772 block = be_transform_node(src_block);
1773 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1774 set_address(new_node, addr);
1775 set_ia32_op_type(new_node, ia32_AddrModeD);
1776 set_ia32_ls_mode(new_node, mode);
1777 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1782 static ir_node *try_create_dest_am(ir_node *node) {
1783 ir_node *val = get_Store_value(node);
1784 ir_node *mem = get_Store_mem(node);
1785 ir_node *ptr = get_Store_ptr(node);
1786 ir_mode *mode = get_irn_mode(val);
1791 /* handle only GP modes for now... */
1792 if(!mode_needs_gp_reg(mode))
1795 /* store must be the only user of the val node */
1796 if(get_irn_n_edges(val) > 1)
1799 switch(get_irn_opcode(val)) {
1801 op1 = get_Add_left(val);
1802 op2 = get_Add_right(val);
1803 if(is_Const_1(op2)) {
1804 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1805 new_rd_ia32_IncMem);
1807 } else if(is_Const_Minus_1(op2)) {
1808 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1809 new_rd_ia32_DecMem);
1812 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1813 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1816 op1 = get_Sub_left(val);
1817 op2 = get_Sub_right(val);
1819 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1822 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1823 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1826 op1 = get_And_left(val);
1827 op2 = get_And_right(val);
1828 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1829 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1832 op1 = get_Or_left(val);
1833 op2 = get_Or_right(val);
1834 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1835 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1838 op1 = get_Eor_left(val);
1839 op2 = get_Eor_right(val);
1840 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1841 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1844 op1 = get_Shl_left(val);
1845 op2 = get_Shl_right(val);
1846 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1847 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1850 op1 = get_Shr_left(val);
1851 op2 = get_Shr_right(val);
1852 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1853 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1856 op1 = get_Shrs_left(val);
1857 op2 = get_Shrs_right(val);
1858 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1859 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1862 op1 = get_Rot_left(val);
1863 op2 = get_Rot_right(val);
1864 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1865 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1867 /* TODO: match ROR patterns... */
1869 op1 = get_Minus_op(val);
1870 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1873 /* should be lowered already */
1874 assert(mode != mode_b);
1875 op1 = get_Not_op(val);
1876 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1886 * Transforms a Store.
1888 * @return the created ia32 Store node
1890 static ir_node *gen_Store(ir_node *node) {
1891 ir_node *block = be_transform_node(get_nodes_block(node));
1892 ir_node *ptr = get_Store_ptr(node);
1895 ir_node *val = get_Store_value(node);
1897 ir_node *mem = get_Store_mem(node);
1898 ir_node *new_mem = be_transform_node(mem);
1899 ir_graph *irg = current_ir_graph;
1900 dbg_info *dbgi = get_irn_dbg_info(node);
1901 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1902 ir_mode *mode = get_irn_mode(val);
1904 ia32_address_t addr;
1906 /* check for destination address mode */
1907 new_op = try_create_dest_am(node);
1911 /* construct store address */
1912 memset(&addr, 0, sizeof(addr));
1913 ia32_create_address_mode(&addr, ptr, 0);
1920 base = be_transform_node(base);
1926 index = be_transform_node(index);
1929 if (mode_is_float(mode)) {
1930 new_val = be_transform_node(val);
1931 if (USE_SSE2(env_cg)) {
1932 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1935 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1939 new_val = create_immediate_or_transform(val, 0);
1943 if (get_mode_size_bits(mode) == 8) {
1944 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1947 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1952 set_irn_pinned(new_op, get_irn_pinned(node));
1953 set_ia32_op_type(new_op, ia32_AddrModeD);
1954 set_ia32_ls_mode(new_op, mode);
1956 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1957 set_address(new_op, &addr);
1958 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1963 static ir_node *create_Switch(ir_node *node)
1965 ir_graph *irg = current_ir_graph;
1966 dbg_info *dbgi = get_irn_dbg_info(node);
1967 ir_node *block = be_transform_node(get_nodes_block(node));
1968 ir_node *sel = get_Cond_selector(node);
1969 ir_node *new_sel = be_transform_node(sel);
1971 int switch_min = INT_MAX;
1972 const ir_edge_t *edge;
1974 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1976 /* determine the smallest switch case value */
1977 foreach_out_edge(node, edge) {
1978 ir_node *proj = get_edge_src_irn(edge);
1979 int pn = get_Proj_proj(proj);
1984 if (switch_min != 0) {
1985 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1987 /* if smallest switch case is not 0 we need an additional sub */
1988 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1989 add_ia32_am_offs_int(new_sel, -switch_min);
1990 set_ia32_op_type(new_sel, ia32_AddrModeS);
1992 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1995 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1996 set_ia32_pncode(res, get_Cond_defaultProj(node));
1998 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2003 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
2005 ir_graph *irg = current_ir_graph;
2013 /* we have a Cmp as input */
2015 ir_node *pred = get_Proj_pred(node);
2017 flags = be_transform_node(pred);
2018 *pnc_out = get_Proj_proj(node);
2023 /* a mode_b value, we have to compare it against 0 */
2024 dbgi = get_irn_dbg_info(node);
2025 new_block = be_transform_node(get_nodes_block(node));
2026 new_op = be_transform_node(node);
2027 noreg = ia32_new_NoReg_gp(env_cg);
2028 nomem = new_NoMem();
2029 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2030 new_op, new_op, 0, 0);
2031 *pnc_out = pn_Cmp_Lg;
2035 static ir_node *gen_Cond(ir_node *node) {
2036 ir_node *block = get_nodes_block(node);
2037 ir_node *new_block = be_transform_node(block);
2038 ir_graph *irg = current_ir_graph;
2039 dbg_info *dbgi = get_irn_dbg_info(node);
2040 ir_node *sel = get_Cond_selector(node);
2041 ir_mode *sel_mode = get_irn_mode(sel);
2043 ir_node *flags = NULL;
2046 if (sel_mode != mode_b) {
2047 return create_Switch(node);
2050 /* we get flags from a cmp */
2051 flags = get_flags_node(sel, &pnc);
2053 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2054 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2062 * Transforms a CopyB node.
2064 * @return The transformed node.
2066 static ir_node *gen_CopyB(ir_node *node) {
2067 ir_node *block = be_transform_node(get_nodes_block(node));
2068 ir_node *src = get_CopyB_src(node);
2069 ir_node *new_src = be_transform_node(src);
2070 ir_node *dst = get_CopyB_dst(node);
2071 ir_node *new_dst = be_transform_node(dst);
2072 ir_node *mem = get_CopyB_mem(node);
2073 ir_node *new_mem = be_transform_node(mem);
2074 ir_node *res = NULL;
2075 ir_graph *irg = current_ir_graph;
2076 dbg_info *dbgi = get_irn_dbg_info(node);
2077 int size = get_type_size_bytes(get_CopyB_type(node));
2080 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2081 /* then we need the size explicitly in ECX. */
2082 if (size >= 32 * 4) {
2083 rem = size & 0x3; /* size % 4 */
2086 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2088 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2090 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2092 add_irn_dep(res, get_irg_frame(irg));
2094 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2095 /* we misuse the pncode field for the copyb size */
2096 set_ia32_pncode(res, rem);
2098 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2099 set_ia32_pncode(res, size);
2102 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2107 static ir_node *gen_be_Copy(ir_node *node)
2109 ir_node *result = be_duplicate_node(node);
2110 ir_mode *mode = get_irn_mode(result);
2112 if (mode_needs_gp_reg(mode)) {
2113 set_irn_mode(result, mode_Iu);
2120 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2121 * to fold an and into a test node
2123 static int can_fold_test_and(ir_node *node)
2125 const ir_edge_t *edge;
2127 /** we can only have eq and lg projs */
2128 foreach_out_edge(node, edge) {
2129 ir_node *proj = get_edge_src_irn(edge);
2130 pn_Cmp pnc = get_Proj_proj(proj);
2131 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2138 static ir_node *try_create_Test(ir_node *node)
2140 ir_graph *irg = current_ir_graph;
2141 dbg_info *dbgi = get_irn_dbg_info(node);
2142 ir_node *block = get_nodes_block(node);
2143 ir_node *new_block = be_transform_node(block);
2144 ir_node *cmp_left = get_Cmp_left(node);
2145 ir_node *cmp_right = get_Cmp_right(node);
2150 ia32_address_mode_t am;
2151 ia32_address_t *addr = &am.addr;
2154 /* can we use a test instruction? */
2155 if(!is_Const_0(cmp_right))
2158 if(is_And(cmp_left) && get_irn_n_edges(cmp_left) == 1 &&
2159 can_fold_test_and(node)) {
2160 ir_node *and_left = get_And_left(cmp_left);
2161 ir_node *and_right = get_And_right(cmp_left);
2163 mode = get_irn_mode(and_left);
2167 mode = get_irn_mode(cmp_left);
2172 assert(get_mode_size_bits(mode) <= 32);
2174 match_arguments(&am, block, left, right, match_commutative |
2175 match_8_16_bit_am | match_am_and_immediates);
2177 cmp_unsigned = !mode_is_signed(mode);
2178 if(get_mode_size_bits(mode) == 8) {
2179 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2180 addr->index, addr->mem, am.new_op1,
2181 am.new_op2, am.flipped, cmp_unsigned);
2183 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2184 addr->mem, am.new_op1, am.new_op2, am.flipped,
2187 set_am_attributes(res, &am);
2188 assert(mode != NULL);
2189 set_ia32_ls_mode(res, mode);
2191 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2193 res = fix_mem_proj(res, &am);
2197 static ir_node *create_Fucom(ir_node *node)
2199 ir_graph *irg = current_ir_graph;
2200 dbg_info *dbgi = get_irn_dbg_info(node);
2201 ir_node *block = get_nodes_block(node);
2202 ir_node *new_block = be_transform_node(block);
2203 ir_node *left = get_Cmp_left(node);
2204 ir_node *new_left = be_transform_node(left);
2205 ir_node *right = get_Cmp_right(node);
2209 if(transform_config.use_ftst && is_Const_null(right)) {
2210 res = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left, 0);
2212 new_right = be_transform_node(right);
2213 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
2217 set_ia32_commutative(res);
2219 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2221 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2222 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2227 static ir_node *create_Ucomi(ir_node *node)
2229 ir_graph *irg = current_ir_graph;
2230 dbg_info *dbgi = get_irn_dbg_info(node);
2231 ir_node *block = get_nodes_block(node);
2232 ir_node *new_block = be_transform_node(block);
2233 ir_node *left = get_Cmp_left(node);
2234 ir_node *new_left = be_transform_node(left);
2235 ir_node *right = get_Cmp_right(node);
2236 ir_node *new_right = be_transform_node(right);
2237 ir_mode *mode = get_irn_mode(left);
2238 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2239 ir_node *nomem = new_NoMem();
2242 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2244 set_ia32_commutative(res);
2245 set_ia32_ls_mode(res, mode);
2247 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2252 static ir_node *gen_Cmp(ir_node *node)
2254 ir_graph *irg = current_ir_graph;
2255 dbg_info *dbgi = get_irn_dbg_info(node);
2256 ir_node *block = get_nodes_block(node);
2257 ir_node *new_block = be_transform_node(block);
2258 ir_node *left = get_Cmp_left(node);
2259 ir_node *right = get_Cmp_right(node);
2260 ir_mode *cmp_mode = get_irn_mode(left);
2262 ia32_address_mode_t am;
2263 ia32_address_t *addr = &am.addr;
2266 if(mode_is_float(cmp_mode)) {
2267 if (USE_SSE2(env_cg)) {
2268 return create_Ucomi(node);
2270 return create_Fucom(node);
2274 assert(mode_needs_gp_reg(cmp_mode));
2276 /* we prefer the Test instruction where possible except cases where
2277 * we can use SourceAM */
2278 if(!use_source_address_mode(block, left, right) &&
2279 !use_source_address_mode(block, right, left)) {
2280 res = try_create_Test(node);
2285 match_arguments(&am, block, left, right,
2286 match_commutative | match_8_16_bit_am |
2287 match_am_and_immediates);
2289 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2290 if(get_mode_size_bits(cmp_mode) == 8) {
2291 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2292 addr->mem, am.new_op1, am.new_op2,
2293 am.flipped, cmp_unsigned);
2295 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2296 addr->mem, am.new_op1, am.new_op2, am.flipped,
2299 set_am_attributes(res, &am);
2300 assert(cmp_mode != NULL);
2301 set_ia32_ls_mode(res, cmp_mode);
2303 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2305 res = fix_mem_proj(res, &am);
2310 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2312 ir_graph *irg = current_ir_graph;
2313 dbg_info *dbgi = get_irn_dbg_info(node);
2314 ir_node *block = get_nodes_block(node);
2315 ir_node *new_block = be_transform_node(block);
2316 ir_node *val_true = get_Psi_val(node, 0);
2317 ir_node *new_val_true = be_transform_node(val_true);
2318 ir_node *val_false = get_Psi_default(node);
2319 ir_node *new_val_false = be_transform_node(val_false);
2320 ir_mode *mode = get_irn_mode(node);
2321 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2322 ir_node *nomem = new_NoMem();
2325 assert(mode_needs_gp_reg(mode));
2327 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2328 new_val_false, new_val_true, new_flags, pnc);
2329 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2336 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2337 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2339 ir_graph *irg = current_ir_graph;
2340 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2341 ir_node *nomem = new_NoMem();
2344 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2345 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2346 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2347 nomem, res, mode_Bu);
2348 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2354 * Transforms a Psi node into CMov.
2356 * @return The transformed node.
2358 static ir_node *gen_Psi(ir_node *node)
2360 dbg_info *dbgi = get_irn_dbg_info(node);
2361 ir_node *block = get_nodes_block(node);
2362 ir_node *new_block = be_transform_node(block);
2363 ir_node *psi_true = get_Psi_val(node, 0);
2364 ir_node *psi_default = get_Psi_default(node);
2365 ir_node *cond = get_Psi_cond(node, 0);
2366 ir_node *flags = NULL;
2371 assert(get_Psi_n_conds(node) == 1);
2372 assert(get_irn_mode(cond) == mode_b);
2373 assert(mode_needs_gp_reg(get_irn_mode(node)));
2375 flags = get_flags_node(cond, &pnc);
2377 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2378 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2379 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2380 pnc = get_negated_pnc(pnc, cmp_mode);
2381 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2383 res = create_CMov(node, flags, pnc);
2390 * Create a conversion from x87 state register to general purpose.
2392 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2393 ir_node *block = be_transform_node(get_nodes_block(node));
2394 ir_node *op = get_Conv_op(node);
2395 ir_node *new_op = be_transform_node(op);
2396 ia32_code_gen_t *cg = env_cg;
2397 ir_graph *irg = current_ir_graph;
2398 dbg_info *dbgi = get_irn_dbg_info(node);
2399 ir_node *noreg = ia32_new_NoReg_gp(cg);
2400 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2401 ir_mode *mode = get_irn_mode(node);
2402 ir_node *fist, *load;
2405 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2406 new_NoMem(), new_op, trunc_mode);
2408 set_irn_pinned(fist, op_pin_state_floats);
2409 set_ia32_use_frame(fist);
2410 set_ia32_op_type(fist, ia32_AddrModeD);
2412 assert(get_mode_size_bits(mode) <= 32);
2413 /* exception we can only store signed 32 bit integers, so for unsigned
2414 we store a 64bit (signed) integer and load the lower bits */
2415 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2416 set_ia32_ls_mode(fist, mode_Ls);
2418 set_ia32_ls_mode(fist, mode_Is);
2420 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2423 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2425 set_irn_pinned(load, op_pin_state_floats);
2426 set_ia32_use_frame(load);
2427 set_ia32_op_type(load, ia32_AddrModeS);
2428 set_ia32_ls_mode(load, mode_Is);
2429 if(get_ia32_ls_mode(fist) == mode_Ls) {
2430 ia32_attr_t *attr = get_ia32_attr(load);
2431 attr->data.need_64bit_stackent = 1;
2433 ia32_attr_t *attr = get_ia32_attr(load);
2434 attr->data.need_32bit_stackent = 1;
2436 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2438 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2442 * Creates a x87 strict Conv by placing a Sore and a Load
2444 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2446 ir_node *block = get_nodes_block(node);
2447 ir_graph *irg = current_ir_graph;
2448 dbg_info *dbgi = get_irn_dbg_info(node);
2449 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2450 ir_node *nomem = new_NoMem();
2451 ir_node *frame = get_irg_frame(irg);
2452 ir_node *store, *load;
2455 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2457 set_ia32_use_frame(store);
2458 set_ia32_op_type(store, ia32_AddrModeD);
2459 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2461 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2463 set_ia32_use_frame(load);
2464 set_ia32_op_type(load, ia32_AddrModeS);
2465 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2467 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2471 static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
2473 ir_graph *irg = current_ir_graph;
2474 ir_node *start_block = get_irg_start_block(irg);
2475 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
2476 symconst, symconst_sign, val);
2477 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
2483 * Create a conversion from general purpose to x87 register
2485 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2486 ir_node *src_block = get_nodes_block(node);
2487 ir_node *block = be_transform_node(src_block);
2488 ir_graph *irg = current_ir_graph;
2489 dbg_info *dbgi = get_irn_dbg_info(node);
2490 ir_node *op = get_Conv_op(node);
2495 ir_mode *store_mode;
2501 /* fild can use source AM if the operand is a signed 32bit integer */
2502 if (src_mode == mode_Is) {
2503 ia32_address_mode_t am;
2505 match_arguments(&am, src_block, NULL, op, match_no_immediate);
2506 if (am.op_type == ia32_AddrModeS) {
2507 ia32_address_t *addr = &am.addr;
2509 fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base, addr->index, addr->mem);
2510 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2512 set_am_attributes(fild, &am);
2513 SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
2515 fix_mem_proj(fild, &am);
2519 new_op = am.new_op2;
2521 new_op = be_transform_node(op);
2524 noreg = ia32_new_NoReg_gp(env_cg);
2525 nomem = new_NoMem();
2526 mode = get_irn_mode(op);
2528 /* first convert to 32 bit signed if necessary */
2529 src_bits = get_mode_size_bits(src_mode);
2530 if (src_bits == 8) {
2531 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2533 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2535 } else if (src_bits < 32) {
2536 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2538 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2542 assert(get_mode_size_bits(mode) == 32);
2545 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2548 set_ia32_use_frame(store);
2549 set_ia32_op_type(store, ia32_AddrModeD);
2550 set_ia32_ls_mode(store, mode_Iu);
2552 /* exception for 32bit unsigned, do a 64bit spill+load */
2553 if(!mode_is_signed(mode)) {
2556 ir_node *zero_const = create_Immediate(NULL, 0, 0);
2558 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2559 get_irg_frame(irg), noreg, nomem,
2562 set_ia32_use_frame(zero_store);
2563 set_ia32_op_type(zero_store, ia32_AddrModeD);
2564 add_ia32_am_offs_int(zero_store, 4);
2565 set_ia32_ls_mode(zero_store, mode_Iu);
2570 store = new_rd_Sync(dbgi, irg, block, 2, in);
2571 store_mode = mode_Ls;
2573 store_mode = mode_Is;
2577 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2579 set_ia32_use_frame(fild);
2580 set_ia32_op_type(fild, ia32_AddrModeS);
2581 set_ia32_ls_mode(fild, store_mode);
2583 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2589 * Crete a conversion from one integer mode into another one
2591 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2592 dbg_info *dbgi, ir_node *block, ir_node *op,
2595 ir_graph *irg = current_ir_graph;
2596 int src_bits = get_mode_size_bits(src_mode);
2597 int tgt_bits = get_mode_size_bits(tgt_mode);
2598 ir_node *new_block = be_transform_node(block);
2599 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2602 ir_mode *smaller_mode;
2604 ia32_address_mode_t am;
2605 ia32_address_t *addr = &am.addr;
2607 if (src_bits < tgt_bits) {
2608 smaller_mode = src_mode;
2609 smaller_bits = src_bits;
2611 smaller_mode = tgt_mode;
2612 smaller_bits = tgt_bits;
2615 memset(&am, 0, sizeof(am));
2616 if(use_source_address_mode(block, op, NULL)) {
2617 build_address(&am, op);
2619 am.op_type = ia32_AddrModeS;
2621 new_op = be_transform_node(op);
2622 am.op_type = ia32_Normal;
2624 if(addr->base == NULL)
2626 if(addr->index == NULL)
2627 addr->index = noreg;
2628 if(addr->mem == NULL)
2629 addr->mem = new_NoMem();
2631 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2632 if (smaller_bits == 8) {
2633 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2634 addr->index, addr->mem, new_op,
2637 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2638 addr->index, addr->mem, new_op,
2642 set_am_attributes(res, &am);
2643 set_ia32_ls_mode(res, smaller_mode);
2644 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2645 res = fix_mem_proj(res, &am);
2651 * Transforms a Conv node.
2653 * @return The created ia32 Conv node
2655 static ir_node *gen_Conv(ir_node *node) {
2656 ir_node *block = get_nodes_block(node);
2657 ir_node *new_block = be_transform_node(block);
2658 ir_node *op = get_Conv_op(node);
2659 ir_node *new_op = NULL;
2660 ir_graph *irg = current_ir_graph;
2661 dbg_info *dbgi = get_irn_dbg_info(node);
2662 ir_mode *src_mode = get_irn_mode(op);
2663 ir_mode *tgt_mode = get_irn_mode(node);
2664 int src_bits = get_mode_size_bits(src_mode);
2665 int tgt_bits = get_mode_size_bits(tgt_mode);
2666 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2667 ir_node *nomem = new_rd_NoMem(irg);
2668 ir_node *res = NULL;
2670 if (src_mode == mode_b) {
2671 assert(mode_is_int(tgt_mode));
2672 /* nothing to do, we already model bools as 0/1 ints */
2673 return be_transform_node(op);
2676 if (src_mode == tgt_mode) {
2677 if (get_Conv_strict(node)) {
2678 if (USE_SSE2(env_cg)) {
2679 /* when we are in SSE mode, we can kill all strict no-op conversion */
2680 return be_transform_node(op);
2683 /* this should be optimized already, but who knows... */
2684 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2685 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2686 return be_transform_node(op);
2690 if (mode_is_float(src_mode)) {
2691 new_op = be_transform_node(op);
2692 /* we convert from float ... */
2693 if (mode_is_float(tgt_mode)) {
2694 if(src_mode == mode_E && tgt_mode == mode_D
2695 && !get_Conv_strict(node)) {
2696 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2701 if (USE_SSE2(env_cg)) {
2702 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2703 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2705 set_ia32_ls_mode(res, tgt_mode);
2707 if(get_Conv_strict(node)) {
2708 res = gen_x87_strict_conv(tgt_mode, new_op);
2709 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2712 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2717 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2718 if (USE_SSE2(env_cg)) {
2719 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2721 set_ia32_ls_mode(res, src_mode);
2723 return gen_x87_fp_to_gp(node);
2727 /* we convert from int ... */
2728 if (mode_is_float(tgt_mode)) {
2730 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2731 if (USE_SSE2(env_cg)) {
2732 new_op = be_transform_node(op);
2733 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2735 set_ia32_ls_mode(res, tgt_mode);
2737 res = gen_x87_gp_to_fp(node, src_mode);
2738 if(get_Conv_strict(node)) {
2739 res = gen_x87_strict_conv(tgt_mode, res);
2740 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2741 ia32_get_old_node_name(env_cg, node));
2745 } else if(tgt_mode == mode_b) {
2746 /* mode_b lowering already took care that we only have 0/1 values */
2747 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2748 src_mode, tgt_mode));
2749 return be_transform_node(op);
2752 if (src_bits == tgt_bits) {
2753 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2754 src_mode, tgt_mode));
2755 return be_transform_node(op);
2758 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2766 static int check_immediate_constraint(long val, char immediate_constraint_type)
2768 switch (immediate_constraint_type) {
2772 return val >= 0 && val <= 32;
2774 return val >= 0 && val <= 63;
2776 return val >= -128 && val <= 127;
2778 return val == 0xff || val == 0xffff;
2780 return val >= 0 && val <= 3;
2782 return val >= 0 && val <= 255;
2784 return val >= 0 && val <= 127;
2788 panic("Invalid immediate constraint found");
2792 static ir_node *try_create_Immediate(ir_node *node,
2793 char immediate_constraint_type)
2796 tarval *offset = NULL;
2797 int offset_sign = 0;
2799 ir_entity *symconst_ent = NULL;
2800 int symconst_sign = 0;
2802 ir_node *cnst = NULL;
2803 ir_node *symconst = NULL;
2806 mode = get_irn_mode(node);
2807 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2811 if(is_Minus(node)) {
2813 node = get_Minus_op(node);
2816 if(is_Const(node)) {
2819 offset_sign = minus;
2820 } else if(is_SymConst(node)) {
2823 symconst_sign = minus;
2824 } else if(is_Add(node)) {
2825 ir_node *left = get_Add_left(node);
2826 ir_node *right = get_Add_right(node);
2827 if(is_Const(left) && is_SymConst(right)) {
2830 symconst_sign = minus;
2831 offset_sign = minus;
2832 } else if(is_SymConst(left) && is_Const(right)) {
2835 symconst_sign = minus;
2836 offset_sign = minus;
2838 } else if(is_Sub(node)) {
2839 ir_node *left = get_Sub_left(node);
2840 ir_node *right = get_Sub_right(node);
2841 if(is_Const(left) && is_SymConst(right)) {
2844 symconst_sign = !minus;
2845 offset_sign = minus;
2846 } else if(is_SymConst(left) && is_Const(right)) {
2849 symconst_sign = minus;
2850 offset_sign = !minus;
2857 offset = get_Const_tarval(cnst);
2858 if(tarval_is_long(offset)) {
2859 val = get_tarval_long(offset);
2861 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2866 if(!check_immediate_constraint(val, immediate_constraint_type))
2869 if(symconst != NULL) {
2870 if(immediate_constraint_type != 0) {
2871 /* we need full 32bits for symconsts */
2875 /* unfortunately the assembler/linker doesn't support -symconst */
2879 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2881 symconst_ent = get_SymConst_entity(symconst);
2883 if(cnst == NULL && symconst == NULL)
2886 if(offset_sign && offset != NULL) {
2887 offset = tarval_neg(offset);
2890 res = create_Immediate(symconst_ent, symconst_sign, val);
2895 static ir_node *create_immediate_or_transform(ir_node *node,
2896 char immediate_constraint_type)
2898 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2899 if (new_node == NULL) {
2900 new_node = be_transform_node(node);
2905 typedef struct constraint_t constraint_t;
2906 struct constraint_t {
2909 const arch_register_req_t **out_reqs;
2911 const arch_register_req_t *req;
2912 unsigned immediate_possible;
2913 char immediate_type;
2916 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2918 int immediate_possible = 0;
2919 char immediate_type = 0;
2920 unsigned limited = 0;
2921 const arch_register_class_t *cls = NULL;
2922 ir_graph *irg = current_ir_graph;
2923 struct obstack *obst = get_irg_obstack(irg);
2924 arch_register_req_t *req;
2925 unsigned *limited_ptr;
2929 /* TODO: replace all the asserts with nice error messages */
2931 printf("Constraint: %s\n", c);
2941 assert(cls == NULL ||
2942 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2943 cls = &ia32_reg_classes[CLASS_ia32_gp];
2944 limited |= 1 << REG_EAX;
2947 assert(cls == NULL ||
2948 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2949 cls = &ia32_reg_classes[CLASS_ia32_gp];
2950 limited |= 1 << REG_EBX;
2953 assert(cls == NULL ||
2954 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2955 cls = &ia32_reg_classes[CLASS_ia32_gp];
2956 limited |= 1 << REG_ECX;
2959 assert(cls == NULL ||
2960 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2961 cls = &ia32_reg_classes[CLASS_ia32_gp];
2962 limited |= 1 << REG_EDX;
2965 assert(cls == NULL ||
2966 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2967 cls = &ia32_reg_classes[CLASS_ia32_gp];
2968 limited |= 1 << REG_EDI;
2971 assert(cls == NULL ||
2972 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2973 cls = &ia32_reg_classes[CLASS_ia32_gp];
2974 limited |= 1 << REG_ESI;
2977 case 'q': /* q means lower part of the regs only, this makes no
2978 * difference to Q for us (we only assigne whole registers) */
2979 assert(cls == NULL ||
2980 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2981 cls = &ia32_reg_classes[CLASS_ia32_gp];
2982 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2986 assert(cls == NULL ||
2987 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2988 cls = &ia32_reg_classes[CLASS_ia32_gp];
2989 limited |= 1 << REG_EAX | 1 << REG_EDX;
2992 assert(cls == NULL ||
2993 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2994 cls = &ia32_reg_classes[CLASS_ia32_gp];
2995 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2996 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
3003 assert(cls == NULL);
3004 cls = &ia32_reg_classes[CLASS_ia32_gp];
3010 /* TODO: mark values so the x87 simulator knows about t and u */
3011 assert(cls == NULL);
3012 cls = &ia32_reg_classes[CLASS_ia32_vfp];
3017 assert(cls == NULL);
3018 /* TODO: check that sse2 is supported */
3019 cls = &ia32_reg_classes[CLASS_ia32_xmm];
3029 assert(!immediate_possible);
3030 immediate_possible = 1;
3031 immediate_type = *c;
3035 assert(!immediate_possible);
3036 immediate_possible = 1;
3040 assert(!immediate_possible && cls == NULL);
3041 immediate_possible = 1;
3042 cls = &ia32_reg_classes[CLASS_ia32_gp];
3055 assert(constraint->is_in && "can only specify same constraint "
3058 sscanf(c, "%d%n", &same_as, &p);
3065 case 'E': /* no float consts yet */
3066 case 'F': /* no float consts yet */
3067 case 's': /* makes no sense on x86 */
3068 case 'X': /* we can't support that in firm */
3072 case '<': /* no autodecrement on x86 */
3073 case '>': /* no autoincrement on x86 */
3074 case 'C': /* sse constant not supported yet */
3075 case 'G': /* 80387 constant not supported yet */
3076 case 'y': /* we don't support mmx registers yet */
3077 case 'Z': /* not available in 32 bit mode */
3078 case 'e': /* not available in 32 bit mode */
3079 panic("unsupported asm constraint '%c' found in (%+F)",
3080 *c, current_ir_graph);
3083 panic("unknown asm constraint '%c' found in (%+F)", *c,
3091 const arch_register_req_t *other_constr;
3093 assert(cls == NULL && "same as and register constraint not supported");
3094 assert(!immediate_possible && "same as and immediate constraint not "
3096 assert(same_as < constraint->n_outs && "wrong constraint number in "
3097 "same_as constraint");
3099 other_constr = constraint->out_reqs[same_as];
3101 req = obstack_alloc(obst, sizeof(req[0]));
3102 req->cls = other_constr->cls;
3103 req->type = arch_register_req_type_should_be_same;
3104 req->limited = NULL;
3105 req->other_same[0] = pos;
3106 req->other_same[1] = -1;
3107 req->other_different = -1;
3109 /* switch constraints. This is because in firm we have same_as
3110 * constraints on the output constraints while in the gcc asm syntax
3111 * they are specified on the input constraints */
3112 constraint->req = other_constr;
3113 constraint->out_reqs[same_as] = req;
3114 constraint->immediate_possible = 0;
3118 if(immediate_possible && cls == NULL) {
3119 cls = &ia32_reg_classes[CLASS_ia32_gp];
3121 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3122 assert(cls != NULL);
3124 if(immediate_possible) {
3125 assert(constraint->is_in
3126 && "imeediates make no sense for output constraints");
3128 /* todo: check types (no float input on 'r' constrained in and such... */
3131 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3132 limited_ptr = (unsigned*) (req+1);
3134 req = obstack_alloc(obst, sizeof(req[0]));
3136 memset(req, 0, sizeof(req[0]));
3139 req->type = arch_register_req_type_limited;
3140 *limited_ptr = limited;
3141 req->limited = limited_ptr;
3143 req->type = arch_register_req_type_normal;
3147 constraint->req = req;
3148 constraint->immediate_possible = immediate_possible;
3149 constraint->immediate_type = immediate_type;
3152 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3159 panic("Clobbers not supported yet");
3163 * generates code for a ASM node
3165 static ir_node *gen_ASM(ir_node *node)
3168 ir_graph *irg = current_ir_graph;
3169 ir_node *block = be_transform_node(get_nodes_block(node));
3170 dbg_info *dbgi = get_irn_dbg_info(node);
3177 ia32_asm_attr_t *attr;
3178 const arch_register_req_t **out_reqs;
3179 const arch_register_req_t **in_reqs;
3180 struct obstack *obst;
3181 constraint_t parsed_constraint;
3183 /* transform inputs */
3184 arity = get_irn_arity(node);
3185 in = alloca(arity * sizeof(in[0]));
3186 memset(in, 0, arity * sizeof(in[0]));
3188 n_outs = get_ASM_n_output_constraints(node);
3189 n_clobbers = get_ASM_n_clobbers(node);
3190 out_arity = n_outs + n_clobbers;
3192 /* construct register constraints */
3193 obst = get_irg_obstack(irg);
3194 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3195 parsed_constraint.out_reqs = out_reqs;
3196 parsed_constraint.n_outs = n_outs;
3197 parsed_constraint.is_in = 0;
3198 for(i = 0; i < out_arity; ++i) {
3202 const ir_asm_constraint *constraint;
3203 constraint = & get_ASM_output_constraints(node) [i];
3204 c = get_id_str(constraint->constraint);
3205 parse_asm_constraint(i, &parsed_constraint, c);
3207 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3208 c = get_id_str(glob_id);
3209 parse_clobber(node, i, &parsed_constraint, c);
3211 out_reqs[i] = parsed_constraint.req;
3214 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3215 parsed_constraint.is_in = 1;
3216 for(i = 0; i < arity; ++i) {
3217 const ir_asm_constraint *constraint;
3221 constraint = & get_ASM_input_constraints(node) [i];
3222 constr_id = constraint->constraint;
3223 c = get_id_str(constr_id);
3224 parse_asm_constraint(i, &parsed_constraint, c);
3225 in_reqs[i] = parsed_constraint.req;
3227 if(parsed_constraint.immediate_possible) {
3228 ir_node *pred = get_irn_n(node, i);
3229 char imm_type = parsed_constraint.immediate_type;
3230 ir_node *immediate = try_create_Immediate(pred, imm_type);
3232 if(immediate != NULL) {
3238 /* transform inputs */
3239 for(i = 0; i < arity; ++i) {
3241 ir_node *transformed;
3246 pred = get_irn_n(node, i);
3247 transformed = be_transform_node(pred);
3248 in[i] = transformed;
3251 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3253 generic_attr = get_irn_generic_attr(res);
3254 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3255 attr->asm_text = get_ASM_text(node);
3256 set_ia32_out_req_all(res, out_reqs);
3257 set_ia32_in_req_all(res, in_reqs);
3259 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3264 /********************************************
3267 * | |__ ___ _ __ ___ __| | ___ ___
3268 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3269 * | |_) | __/ | | | (_) | (_| | __/\__ \
3270 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3272 ********************************************/
3275 * Transforms a FrameAddr into an ia32 Add.
3277 static ir_node *gen_be_FrameAddr(ir_node *node) {
3278 ir_node *block = be_transform_node(get_nodes_block(node));
3279 ir_node *op = be_get_FrameAddr_frame(node);
3280 ir_node *new_op = be_transform_node(op);
3281 ir_graph *irg = current_ir_graph;
3282 dbg_info *dbgi = get_irn_dbg_info(node);
3283 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3286 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3287 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3288 set_ia32_use_frame(res);
3290 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3296 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3298 static ir_node *gen_be_Return(ir_node *node) {
3299 ir_graph *irg = current_ir_graph;
3300 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3301 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3302 ir_entity *ent = get_irg_entity(irg);
3303 ir_type *tp = get_entity_type(ent);
3308 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3309 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3312 int pn_ret_val, pn_ret_mem, arity, i;
3314 assert(ret_val != NULL);
3315 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3316 return be_duplicate_node(node);
3319 res_type = get_method_res_type(tp, 0);
3321 if (! is_Primitive_type(res_type)) {
3322 return be_duplicate_node(node);
3325 mode = get_type_mode(res_type);
3326 if (! mode_is_float(mode)) {
3327 return be_duplicate_node(node);
3330 assert(get_method_n_ress(tp) == 1);
3332 pn_ret_val = get_Proj_proj(ret_val);
3333 pn_ret_mem = get_Proj_proj(ret_mem);
3335 /* get the Barrier */
3336 barrier = get_Proj_pred(ret_val);
3338 /* get result input of the Barrier */
3339 ret_val = get_irn_n(barrier, pn_ret_val);
3340 new_ret_val = be_transform_node(ret_val);
3342 /* get memory input of the Barrier */
3343 ret_mem = get_irn_n(barrier, pn_ret_mem);
3344 new_ret_mem = be_transform_node(ret_mem);
3346 frame = get_irg_frame(irg);
3348 dbgi = get_irn_dbg_info(barrier);
3349 block = be_transform_node(get_nodes_block(barrier));
3351 noreg = ia32_new_NoReg_gp(env_cg);
3353 /* store xmm0 onto stack */
3354 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3355 new_ret_mem, new_ret_val);
3356 set_ia32_ls_mode(sse_store, mode);
3357 set_ia32_op_type(sse_store, ia32_AddrModeD);
3358 set_ia32_use_frame(sse_store);
3360 /* load into x87 register */
3361 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3362 set_ia32_op_type(fld, ia32_AddrModeS);
3363 set_ia32_use_frame(fld);
3365 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3366 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3368 /* create a new barrier */
3369 arity = get_irn_arity(barrier);
3370 in = alloca(arity * sizeof(in[0]));
3371 for (i = 0; i < arity; ++i) {
3374 if (i == pn_ret_val) {
3376 } else if (i == pn_ret_mem) {
3379 ir_node *in = get_irn_n(barrier, i);
3380 new_in = be_transform_node(in);
3385 new_barrier = new_ir_node(dbgi, irg, block,
3386 get_irn_op(barrier), get_irn_mode(barrier),
3388 copy_node_attr(barrier, new_barrier);
3389 be_duplicate_deps(barrier, new_barrier);
3390 be_set_transformed_node(barrier, new_barrier);
3391 mark_irn_visited(barrier);
3393 /* transform normally */
3394 return be_duplicate_node(node);
3398 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3400 static ir_node *gen_be_AddSP(ir_node *node) {
3401 ir_node *block = be_transform_node(get_nodes_block(node));
3402 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3404 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3405 ir_node *new_sp = be_transform_node(sp);
3406 ir_graph *irg = current_ir_graph;
3407 dbg_info *dbgi = get_irn_dbg_info(node);
3408 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3409 ir_node *nomem = new_NoMem();
3412 new_sz = create_immediate_or_transform(sz, 0);
3414 /* ia32 stack grows in reverse direction, make a SubSP */
3415 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3417 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3423 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3425 static ir_node *gen_be_SubSP(ir_node *node) {
3426 ir_node *block = be_transform_node(get_nodes_block(node));
3427 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3429 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3430 ir_node *new_sp = be_transform_node(sp);
3431 ir_graph *irg = current_ir_graph;
3432 dbg_info *dbgi = get_irn_dbg_info(node);
3433 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3434 ir_node *nomem = new_NoMem();
3437 new_sz = create_immediate_or_transform(sz, 0);
3439 /* ia32 stack grows in reverse direction, make an AddSP */
3440 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3442 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3448 * This function just sets the register for the Unknown node
3449 * as this is not done during register allocation because Unknown
3450 * is an "ignore" node.
3452 static ir_node *gen_Unknown(ir_node *node) {
3453 ir_mode *mode = get_irn_mode(node);
3455 if (mode_is_float(mode)) {
3456 if (USE_SSE2(env_cg)) {
3457 return ia32_new_Unknown_xmm(env_cg);
3459 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3460 ir_graph *irg = current_ir_graph;
3461 dbg_info *dbgi = get_irn_dbg_info(node);
3462 ir_node *block = get_irg_start_block(irg);
3463 return new_rd_ia32_vfldz(dbgi, irg, block);
3465 } else if (mode_needs_gp_reg(mode)) {
3466 return ia32_new_Unknown_gp(env_cg);
3468 assert(0 && "unsupported Unknown-Mode");
3475 * Change some phi modes
3477 static ir_node *gen_Phi(ir_node *node) {
3478 ir_node *block = be_transform_node(get_nodes_block(node));
3479 ir_graph *irg = current_ir_graph;
3480 dbg_info *dbgi = get_irn_dbg_info(node);
3481 ir_mode *mode = get_irn_mode(node);
3484 if(mode_needs_gp_reg(mode)) {
3485 /* we shouldn't have any 64bit stuff around anymore */
3486 assert(get_mode_size_bits(mode) <= 32);
3487 /* all integer operations are on 32bit registers now */
3489 } else if(mode_is_float(mode)) {
3490 if (USE_SSE2(env_cg)) {
3497 /* phi nodes allow loops, so we use the old arguments for now
3498 * and fix this later */
3499 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3500 get_irn_in(node) + 1);
3501 copy_node_attr(node, phi);
3502 be_duplicate_deps(node, phi);
3504 be_set_transformed_node(node, phi);
3505 be_enqueue_preds(node);
3513 static ir_node *gen_IJmp(ir_node *node) {
3514 /* TODO: support AM */
3515 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3519 /**********************************************************************
3522 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3523 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3524 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3525 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3527 **********************************************************************/
3529 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3531 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3534 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3535 ir_node *val, ir_node *mem);
3538 * Transforms a lowered Load into a "real" one.
3540 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3542 ir_node *block = be_transform_node(get_nodes_block(node));
3543 ir_node *ptr = get_irn_n(node, 0);
3544 ir_node *new_ptr = be_transform_node(ptr);
3545 ir_node *mem = get_irn_n(node, 1);
3546 ir_node *new_mem = be_transform_node(mem);
3547 ir_graph *irg = current_ir_graph;
3548 dbg_info *dbgi = get_irn_dbg_info(node);
3549 ir_mode *mode = get_ia32_ls_mode(node);
3550 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3553 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3555 set_ia32_op_type(new_op, ia32_AddrModeS);
3556 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3557 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3558 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3559 if (is_ia32_am_sc_sign(node))
3560 set_ia32_am_sc_sign(new_op);
3561 set_ia32_ls_mode(new_op, mode);
3562 if (is_ia32_use_frame(node)) {
3563 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3564 set_ia32_use_frame(new_op);
3567 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3573 * Transforms a lowered Store into a "real" one.
3575 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3577 ir_node *block = be_transform_node(get_nodes_block(node));
3578 ir_node *ptr = get_irn_n(node, 0);
3579 ir_node *new_ptr = be_transform_node(ptr);
3580 ir_node *val = get_irn_n(node, 1);
3581 ir_node *new_val = be_transform_node(val);
3582 ir_node *mem = get_irn_n(node, 2);
3583 ir_node *new_mem = be_transform_node(mem);
3584 ir_graph *irg = current_ir_graph;
3585 dbg_info *dbgi = get_irn_dbg_info(node);
3586 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3587 ir_mode *mode = get_ia32_ls_mode(node);
3591 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3593 am_offs = get_ia32_am_offs_int(node);
3594 add_ia32_am_offs_int(new_op, am_offs);
3596 set_ia32_op_type(new_op, ia32_AddrModeD);
3597 set_ia32_ls_mode(new_op, mode);
3598 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3599 set_ia32_use_frame(new_op);
3601 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3608 * Transforms an ia32_l_XXX into a "real" XXX node
3610 * @param node The node to transform
3611 * @return the created ia32 XXX node
3613 #define GEN_LOWERED_OP(op) \
3614 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3615 return gen_binop(node, get_binop_left(node), \
3616 get_binop_right(node), new_rd_ia32_##op,0); \
3619 #define GEN_LOWERED_x87_OP(op) \
3620 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3622 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3623 get_binop_right(node), new_rd_ia32_##op, 0); \
3627 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3628 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3629 return gen_shift_binop(node, get_irn_n(node, 0), \
3630 get_irn_n(node, 1), new_rd_ia32_##op); \
3633 GEN_LOWERED_x87_OP(vfprem)
3634 GEN_LOWERED_x87_OP(vfmul)
3635 GEN_LOWERED_x87_OP(vfsub)
3636 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3637 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3638 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3639 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3641 static ir_node *gen_ia32_l_Add(ir_node *node) {
3642 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3643 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3644 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3646 if(is_Proj(lowered)) {
3647 lowered = get_Proj_pred(lowered);
3649 assert(is_ia32_Add(lowered));
3650 set_irn_mode(lowered, mode_T);
3656 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3657 ir_node *src_block = get_nodes_block(node);
3658 ir_node *block = be_transform_node(src_block);
3659 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3660 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3661 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3662 ir_node *new_flags = be_transform_node(flags);
3663 ir_graph *irg = current_ir_graph;
3664 dbg_info *dbgi = get_irn_dbg_info(node);
3666 ia32_address_mode_t am;
3667 ia32_address_t *addr = &am.addr;
3669 match_arguments(&am, src_block, op1, op2, match_commutative);
3671 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3672 addr->mem, am.new_op1, am.new_op2, new_flags);
3673 set_am_attributes(new_node, &am);
3674 /* we can't use source address mode anymore when using immediates */
3675 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3676 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3677 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3679 new_node = fix_mem_proj(new_node, &am);
3685 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3687 * @param node The node to transform
3688 * @return the created ia32 Neg node
3690 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3691 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3695 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3697 * @param node The node to transform
3698 * @return the created ia32 vfild node
3700 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3701 return gen_lowered_Load(node, new_rd_ia32_vfild);
3705 * Transforms an ia32_l_Load into a "real" ia32_Load node
3707 * @param node The node to transform
3708 * @return the created ia32 Load node
3710 static ir_node *gen_ia32_l_Load(ir_node *node) {
3711 return gen_lowered_Load(node, new_rd_ia32_Load);
3715 * Transforms an ia32_l_Store into a "real" ia32_Store node
3717 * @param node The node to transform
3718 * @return the created ia32 Store node
3720 static ir_node *gen_ia32_l_Store(ir_node *node) {
3721 return gen_lowered_Store(node, new_rd_ia32_Store);
3725 * Transforms a l_vfist into a "real" vfist node.
3727 * @param node The node to transform
3728 * @return the created ia32 vfist node
3730 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3731 ir_node *block = be_transform_node(get_nodes_block(node));
3732 ir_node *ptr = get_irn_n(node, 0);
3733 ir_node *new_ptr = be_transform_node(ptr);
3734 ir_node *val = get_irn_n(node, 1);
3735 ir_node *new_val = be_transform_node(val);
3736 ir_node *mem = get_irn_n(node, 2);
3737 ir_node *new_mem = be_transform_node(mem);
3738 ir_graph *irg = current_ir_graph;
3739 dbg_info *dbgi = get_irn_dbg_info(node);
3740 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3741 ir_mode *mode = get_ia32_ls_mode(node);
3742 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3746 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3747 new_val, trunc_mode);
3749 am_offs = get_ia32_am_offs_int(node);
3750 add_ia32_am_offs_int(new_op, am_offs);
3752 set_ia32_op_type(new_op, ia32_AddrModeD);
3753 set_ia32_ls_mode(new_op, mode);
3754 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3755 set_ia32_use_frame(new_op);
3757 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3763 * Transforms a l_vfdiv into a "real" vfdiv node.
3765 * @param env The transformation environment
3766 * @return the created ia32 vfdiv node
3768 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3769 ir_node *block = be_transform_node(get_nodes_block(node));
3770 ir_node *left = get_binop_left(node);
3771 ir_node *new_left = be_transform_node(left);
3772 ir_node *right = get_binop_right(node);
3773 ir_node *new_right = be_transform_node(right);
3774 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3775 ir_graph *irg = current_ir_graph;
3776 dbg_info *dbgi = get_irn_dbg_info(node);
3777 ir_node *fpcw = get_fpcw();
3780 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3781 new_left, new_right, fpcw);
3782 clear_ia32_commutative(vfdiv);
3784 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3790 * Transforms a l_MulS into a "real" MulS node.
3792 * @param env The transformation environment
3793 * @return the created ia32 Mul node
3795 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3796 ir_node *block = be_transform_node(get_nodes_block(node));
3797 ir_node *left = get_binop_left(node);
3798 ir_node *new_left = be_transform_node(left);
3799 ir_node *right = get_binop_right(node);
3800 ir_node *new_right = be_transform_node(right);
3801 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3802 ir_graph *irg = current_ir_graph;
3803 dbg_info *dbgi = get_irn_dbg_info(node);
3805 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3806 /* and then skip the result Proj, because all needed Projs are already there. */
3807 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3808 new_left, new_right);
3809 clear_ia32_commutative(muls);
3811 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3817 * Transforms a l_IMulS into a "real" IMul1OPS node.
3819 * @param env The transformation environment
3820 * @return the created ia32 IMul1OP node
3822 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3823 ir_node *block = be_transform_node(get_nodes_block(node));
3824 ir_node *left = get_binop_left(node);
3825 ir_node *new_left = be_transform_node(left);
3826 ir_node *right = get_binop_right(node);
3827 ir_node *new_right = be_transform_node(right);
3828 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3829 ir_graph *irg = current_ir_graph;
3830 dbg_info *dbgi = get_irn_dbg_info(node);
3832 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3833 /* and then skip the result Proj, because all needed Projs are already there. */
3834 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3835 new_NoMem(), new_left, new_right);
3836 clear_ia32_commutative(muls);
3838 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3843 static ir_node *gen_ia32_l_Sub(ir_node *node) {
3844 ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
3845 ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
3846 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub, 0);
3848 if(is_Proj(lowered)) {
3849 lowered = get_Proj_pred(lowered);
3851 assert(is_ia32_Sub(lowered));
3852 set_irn_mode(lowered, mode_T);
3858 static ir_node *gen_ia32_l_Sbb(ir_node *node) {
3859 ir_node *src_block = get_nodes_block(node);
3860 ir_node *block = be_transform_node(src_block);
3861 ir_node *op1 = get_irn_n(node, n_ia32_l_Sbb_left);
3862 ir_node *op2 = get_irn_n(node, n_ia32_l_Sbb_right);
3863 ir_node *flags = get_irn_n(node, n_ia32_l_Sbb_eflags);
3864 ir_node *new_flags = be_transform_node(flags);
3865 ir_graph *irg = current_ir_graph;
3866 dbg_info *dbgi = get_irn_dbg_info(node);
3868 ia32_address_mode_t am;
3869 ia32_address_t *addr = &am.addr;
3871 match_arguments(&am, src_block, op1, op2, match_commutative);
3873 new_node = new_rd_ia32_Sbb(dbgi, irg, block, addr->base, addr->index,
3874 addr->mem, am.new_op1, am.new_op2, new_flags);
3875 set_am_attributes(new_node, &am);
3876 /* we can't use source address mode anymore when using immediates */
3877 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3878 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3879 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3881 new_node = fix_mem_proj(new_node, &am);
3887 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3888 * op1 - target to be shifted
3889 * op2 - contains bits to be shifted into target
3891 * Only op3 can be an immediate.
3893 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3894 ir_node *op2, ir_node *count)
3896 ir_node *block = be_transform_node(get_nodes_block(node));
3897 ir_node *new_op = NULL;
3898 ir_graph *irg = current_ir_graph;
3899 dbg_info *dbgi = get_irn_dbg_info(node);
3900 ir_node *new_op1 = be_transform_node(op1);
3901 ir_node *new_op2 = be_transform_node(op2);
3902 ir_node *new_count = create_immediate_or_transform(count, 'I');
3904 /* TODO proper AM support */
3906 if (is_ia32_l_ShlD(node))
3907 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3909 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3911 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3916 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3917 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3918 get_irn_n(node, 1), get_irn_n(node, 2));
3921 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3922 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3923 get_irn_n(node, 1), get_irn_n(node, 2));
3927 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3929 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3930 ir_node *block = be_transform_node(get_nodes_block(node));
3931 ir_node *val = get_irn_n(node, 1);
3932 ir_node *new_val = be_transform_node(val);
3933 ia32_code_gen_t *cg = env_cg;
3934 ir_node *res = NULL;
3935 ir_graph *irg = current_ir_graph;
3937 ir_node *noreg, *new_ptr, *new_mem;
3944 mem = get_irn_n(node, 2);
3945 new_mem = be_transform_node(mem);
3946 ptr = get_irn_n(node, 0);
3947 new_ptr = be_transform_node(ptr);
3948 noreg = ia32_new_NoReg_gp(cg);
3949 dbgi = get_irn_dbg_info(node);
3951 /* Store x87 -> MEM */
3952 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3953 get_ia32_ls_mode(node));
3954 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3955 set_ia32_use_frame(res);
3956 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3957 set_ia32_op_type(res, ia32_AddrModeD);
3959 /* Load MEM -> SSE */
3960 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3961 get_ia32_ls_mode(node));
3962 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3963 set_ia32_use_frame(res);
3964 set_ia32_op_type(res, ia32_AddrModeS);
3965 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3971 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3973 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3974 ir_node *block = be_transform_node(get_nodes_block(node));
3975 ir_node *val = get_irn_n(node, 1);
3976 ir_node *new_val = be_transform_node(val);
3977 ia32_code_gen_t *cg = env_cg;
3978 ir_graph *irg = current_ir_graph;
3979 ir_node *res = NULL;
3980 ir_entity *fent = get_ia32_frame_ent(node);
3981 ir_mode *lsmode = get_ia32_ls_mode(node);
3983 ir_node *noreg, *new_ptr, *new_mem;
3987 if (! USE_SSE2(cg)) {
3988 /* SSE unit is not used -> skip this node. */
3992 ptr = get_irn_n(node, 0);
3993 new_ptr = be_transform_node(ptr);
3994 mem = get_irn_n(node, 2);
3995 new_mem = be_transform_node(mem);
3996 noreg = ia32_new_NoReg_gp(cg);
3997 dbgi = get_irn_dbg_info(node);
3999 /* Store SSE -> MEM */
4000 if (is_ia32_xLoad(skip_Proj(new_val))) {
4001 ir_node *ld = skip_Proj(new_val);
4003 /* we can vfld the value directly into the fpu */
4004 fent = get_ia32_frame_ent(ld);
4005 ptr = get_irn_n(ld, 0);
4006 offs = get_ia32_am_offs_int(ld);
4008 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
4010 set_ia32_frame_ent(res, fent);
4011 set_ia32_use_frame(res);
4012 set_ia32_ls_mode(res, lsmode);
4013 set_ia32_op_type(res, ia32_AddrModeD);
4017 /* Load MEM -> x87 */
4018 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
4019 set_ia32_frame_ent(res, fent);
4020 set_ia32_use_frame(res);
4021 add_ia32_am_offs_int(res, offs);
4022 set_ia32_op_type(res, ia32_AddrModeS);
4023 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
4028 /*********************************************************
4031 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
4032 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
4033 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
4034 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
4036 *********************************************************/
4039 * the BAD transformer.
4041 static ir_node *bad_transform(ir_node *node) {
4042 panic("No transform function for %+F available.\n", node);
4047 * Transform the Projs of an AddSP.
4049 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
4050 ir_node *block = be_transform_node(get_nodes_block(node));
4051 ir_node *pred = get_Proj_pred(node);
4052 ir_node *new_pred = be_transform_node(pred);
4053 ir_graph *irg = current_ir_graph;
4054 dbg_info *dbgi = get_irn_dbg_info(node);
4055 long proj = get_Proj_proj(node);
4057 if (proj == pn_be_AddSP_sp) {
4058 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4059 pn_ia32_SubSP_stack);
4060 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4062 } else if(proj == pn_be_AddSP_res) {
4063 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4064 pn_ia32_SubSP_addr);
4065 } else if (proj == pn_be_AddSP_M) {
4066 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4070 return new_rd_Unknown(irg, get_irn_mode(node));
4074 * Transform the Projs of a SubSP.
4076 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4077 ir_node *block = be_transform_node(get_nodes_block(node));
4078 ir_node *pred = get_Proj_pred(node);
4079 ir_node *new_pred = be_transform_node(pred);
4080 ir_graph *irg = current_ir_graph;
4081 dbg_info *dbgi = get_irn_dbg_info(node);
4082 long proj = get_Proj_proj(node);
4084 if (proj == pn_be_SubSP_sp) {
4085 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4086 pn_ia32_AddSP_stack);
4087 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4089 } else if (proj == pn_be_SubSP_M) {
4090 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4094 return new_rd_Unknown(irg, get_irn_mode(node));
4098 * Transform and renumber the Projs from a Load.
4100 static ir_node *gen_Proj_Load(ir_node *node) {
4102 ir_node *block = be_transform_node(get_nodes_block(node));
4103 ir_node *pred = get_Proj_pred(node);
4104 ir_graph *irg = current_ir_graph;
4105 dbg_info *dbgi = get_irn_dbg_info(node);
4106 long proj = get_Proj_proj(node);
4109 /* loads might be part of source address mode matches, so we don't
4110 transform the ProjMs yet (with the exception of loads whose result is
4113 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4116 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4118 /* this is needed, because sometimes we have loops that are only
4119 reachable through the ProjM */
4120 be_enqueue_preds(node);
4121 /* do it in 2 steps, to silence firm verifier */
4122 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4123 set_Proj_proj(res, pn_ia32_Load_M);
4127 /* renumber the proj */
4128 new_pred = be_transform_node(pred);
4129 if (is_ia32_Load(new_pred)) {
4130 if (proj == pn_Load_res) {
4131 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4133 } else if (proj == pn_Load_M) {
4134 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4137 } else if(is_ia32_Conv_I2I(new_pred)) {
4138 set_irn_mode(new_pred, mode_T);
4139 if (proj == pn_Load_res) {
4140 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4141 } else if (proj == pn_Load_M) {
4142 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4144 } else if (is_ia32_xLoad(new_pred)) {
4145 if (proj == pn_Load_res) {
4146 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4148 } else if (proj == pn_Load_M) {
4149 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4152 } else if (is_ia32_vfld(new_pred)) {
4153 if (proj == pn_Load_res) {
4154 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4156 } else if (proj == pn_Load_M) {
4157 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4161 /* can happen for ProJMs when source address mode happened for the
4164 /* however it should not be the result proj, as that would mean the
4165 load had multiple users and should not have been used for
4167 if(proj != pn_Load_M) {
4168 panic("internal error: transformed node not a Load");
4170 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4174 return new_rd_Unknown(irg, get_irn_mode(node));
4178 * Transform and renumber the Projs from a DivMod like instruction.
4180 static ir_node *gen_Proj_DivMod(ir_node *node) {
4181 ir_node *block = be_transform_node(get_nodes_block(node));
4182 ir_node *pred = get_Proj_pred(node);
4183 ir_node *new_pred = be_transform_node(pred);
4184 ir_graph *irg = current_ir_graph;
4185 dbg_info *dbgi = get_irn_dbg_info(node);
4186 ir_mode *mode = get_irn_mode(node);
4187 long proj = get_Proj_proj(node);
4189 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4191 switch (get_irn_opcode(pred)) {
4195 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4197 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4205 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4207 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4215 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4216 case pn_DivMod_res_div:
4217 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4218 case pn_DivMod_res_mod:
4219 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4229 return new_rd_Unknown(irg, mode);
4233 * Transform and renumber the Projs from a CopyB.
4235 static ir_node *gen_Proj_CopyB(ir_node *node) {
4236 ir_node *block = be_transform_node(get_nodes_block(node));
4237 ir_node *pred = get_Proj_pred(node);
4238 ir_node *new_pred = be_transform_node(pred);
4239 ir_graph *irg = current_ir_graph;
4240 dbg_info *dbgi = get_irn_dbg_info(node);
4241 ir_mode *mode = get_irn_mode(node);
4242 long proj = get_Proj_proj(node);
4245 case pn_CopyB_M_regular:
4246 if (is_ia32_CopyB_i(new_pred)) {
4247 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4248 } else if (is_ia32_CopyB(new_pred)) {
4249 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4257 return new_rd_Unknown(irg, mode);
4261 * Transform and renumber the Projs from a vfdiv.
4263 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4264 ir_node *block = be_transform_node(get_nodes_block(node));
4265 ir_node *pred = get_Proj_pred(node);
4266 ir_node *new_pred = be_transform_node(pred);
4267 ir_graph *irg = current_ir_graph;
4268 dbg_info *dbgi = get_irn_dbg_info(node);
4269 ir_mode *mode = get_irn_mode(node);
4270 long proj = get_Proj_proj(node);
4273 case pn_ia32_l_vfdiv_M:
4274 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4275 case pn_ia32_l_vfdiv_res:
4276 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4281 return new_rd_Unknown(irg, mode);
4285 * Transform and renumber the Projs from a Quot.
4287 static ir_node *gen_Proj_Quot(ir_node *node) {
4288 ir_node *block = be_transform_node(get_nodes_block(node));
4289 ir_node *pred = get_Proj_pred(node);
4290 ir_node *new_pred = be_transform_node(pred);
4291 ir_graph *irg = current_ir_graph;
4292 dbg_info *dbgi = get_irn_dbg_info(node);
4293 ir_mode *mode = get_irn_mode(node);
4294 long proj = get_Proj_proj(node);
4298 if (is_ia32_xDiv(new_pred)) {
4299 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4300 } else if (is_ia32_vfdiv(new_pred)) {
4301 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4305 if (is_ia32_xDiv(new_pred)) {
4306 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4307 } else if (is_ia32_vfdiv(new_pred)) {
4308 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4316 return new_rd_Unknown(irg, mode);
4320 * Transform the Thread Local Storage Proj.
4322 static ir_node *gen_Proj_tls(ir_node *node) {
4323 ir_node *block = be_transform_node(get_nodes_block(node));
4324 ir_graph *irg = current_ir_graph;
4325 dbg_info *dbgi = NULL;
4326 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4331 static ir_node *gen_be_Call(ir_node *node) {
4332 ir_node *res = be_duplicate_node(node);
4333 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4338 static ir_node *gen_be_IncSP(ir_node *node) {
4339 ir_node *res = be_duplicate_node(node);
4340 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4346 * Transform the Projs from a be_Call.
4348 static ir_node *gen_Proj_be_Call(ir_node *node) {
4349 ir_node *block = be_transform_node(get_nodes_block(node));
4350 ir_node *call = get_Proj_pred(node);
4351 ir_node *new_call = be_transform_node(call);
4352 ir_graph *irg = current_ir_graph;
4353 dbg_info *dbgi = get_irn_dbg_info(node);
4354 ir_type *method_type = be_Call_get_type(call);
4355 int n_res = get_method_n_ress(method_type);
4356 long proj = get_Proj_proj(node);
4357 ir_mode *mode = get_irn_mode(node);
4359 const arch_register_class_t *cls;
4361 /* The following is kinda tricky: If we're using SSE, then we have to
4362 * move the result value of the call in floating point registers to an
4363 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4364 * after the call, we have to make sure to correctly make the
4365 * MemProj and the result Proj use these 2 nodes
4367 if (proj == pn_be_Call_M_regular) {
4368 // get new node for result, are we doing the sse load/store hack?
4369 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4370 ir_node *call_res_new;
4371 ir_node *call_res_pred = NULL;
4373 if (call_res != NULL) {
4374 call_res_new = be_transform_node(call_res);
4375 call_res_pred = get_Proj_pred(call_res_new);
4378 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4379 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4380 pn_be_Call_M_regular);
4382 assert(is_ia32_xLoad(call_res_pred));
4383 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4387 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4388 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4389 && USE_SSE2(env_cg)) {
4391 ir_node *frame = get_irg_frame(irg);
4392 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4394 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4397 /* in case there is no memory output: create one to serialize the copy
4399 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4400 pn_be_Call_M_regular);
4401 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4402 pn_be_Call_first_res);
4404 /* store st(0) onto stack */
4405 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4407 set_ia32_op_type(fstp, ia32_AddrModeD);
4408 set_ia32_use_frame(fstp);
4410 /* load into SSE register */
4411 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4413 set_ia32_op_type(sse_load, ia32_AddrModeS);
4414 set_ia32_use_frame(sse_load);
4416 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4422 /* transform call modes */
4423 if (mode_is_data(mode)) {
4424 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4428 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4432 * Transform the Projs from a Cmp.
4434 static ir_node *gen_Proj_Cmp(ir_node *node)
4436 /* normally Cmps are processed when looking at Cond nodes, but this case
4437 * can happen in complicated Psi conditions */
4438 dbg_info *dbgi = get_irn_dbg_info(node);
4439 ir_node *block = get_nodes_block(node);
4440 ir_node *new_block = be_transform_node(block);
4441 ir_node *cmp = get_Proj_pred(node);
4442 ir_node *new_cmp = be_transform_node(cmp);
4443 long pnc = get_Proj_proj(node);
4446 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4452 * Transform and potentially renumber Proj nodes.
4454 static ir_node *gen_Proj(ir_node *node) {
4455 ir_graph *irg = current_ir_graph;
4456 dbg_info *dbgi = get_irn_dbg_info(node);
4457 ir_node *pred = get_Proj_pred(node);
4458 long proj = get_Proj_proj(node);
4460 if (is_Store(pred)) {
4461 if (proj == pn_Store_M) {
4462 return be_transform_node(pred);
4465 return new_r_Bad(irg);
4467 } else if (is_Load(pred)) {
4468 return gen_Proj_Load(node);
4469 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4470 return gen_Proj_DivMod(node);
4471 } else if (is_CopyB(pred)) {
4472 return gen_Proj_CopyB(node);
4473 } else if (is_Quot(pred)) {
4474 return gen_Proj_Quot(node);
4475 } else if (is_ia32_l_vfdiv(pred)) {
4476 return gen_Proj_l_vfdiv(node);
4477 } else if (be_is_SubSP(pred)) {
4478 return gen_Proj_be_SubSP(node);
4479 } else if (be_is_AddSP(pred)) {
4480 return gen_Proj_be_AddSP(node);
4481 } else if (be_is_Call(pred)) {
4482 return gen_Proj_be_Call(node);
4483 } else if (is_Cmp(pred)) {
4484 return gen_Proj_Cmp(node);
4485 } else if (get_irn_op(pred) == op_Start) {
4486 if (proj == pn_Start_X_initial_exec) {
4487 ir_node *block = get_nodes_block(pred);
4490 /* we exchange the ProjX with a jump */
4491 block = be_transform_node(block);
4492 jump = new_rd_Jmp(dbgi, irg, block);
4495 if (node == be_get_old_anchor(anchor_tls)) {
4496 return gen_Proj_tls(node);
4499 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4503 ir_node *new_pred = be_transform_node(pred);
4504 ir_node *block = be_transform_node(get_nodes_block(node));
4505 ir_mode *mode = get_irn_mode(node);
4506 if (mode_needs_gp_reg(mode)) {
4507 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4508 get_Proj_proj(node));
4509 #ifdef DEBUG_libfirm
4510 new_proj->node_nr = node->node_nr;
4516 return be_duplicate_node(node);
4520 * Enters all transform functions into the generic pointer
4522 static void register_transformers(void)
4526 /* first clear the generic function pointer for all ops */
4527 clear_irp_opcodes_generic_func();
4529 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4530 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4568 /* transform ops from intrinsic lowering */
4590 GEN(ia32_l_X87toSSE);
4591 GEN(ia32_l_SSEtoX87);
4597 /* we should never see these nodes */
4612 /* handle generic backend nodes */
4621 op_Mulh = get_op_Mulh();
4630 * Pre-transform all unknown and noreg nodes.
4632 static void ia32_pretransform_node(void *arch_cg) {
4633 ia32_code_gen_t *cg = arch_cg;
4635 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4636 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4637 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4638 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4639 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4640 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4645 * Walker, checks if all ia32 nodes producing more than one result have
4646 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4648 static void add_missing_keep_walker(ir_node *node, void *data)
4651 unsigned found_projs = 0;
4652 const ir_edge_t *edge;
4653 ir_mode *mode = get_irn_mode(node);
4658 if(!is_ia32_irn(node))
4661 n_outs = get_ia32_n_res(node);
4664 if(is_ia32_SwitchJmp(node))
4667 assert(n_outs < (int) sizeof(unsigned) * 8);
4668 foreach_out_edge(node, edge) {
4669 ir_node *proj = get_edge_src_irn(edge);
4670 int pn = get_Proj_proj(proj);
4672 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4673 found_projs |= 1 << pn;
4677 /* are keeps missing? */
4679 for(i = 0; i < n_outs; ++i) {
4682 const arch_register_req_t *req;
4683 const arch_register_class_t *class;
4685 if(found_projs & (1 << i)) {
4689 req = get_ia32_out_req(node, i);
4694 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4698 block = get_nodes_block(node);
4699 in[0] = new_r_Proj(current_ir_graph, block, node,
4700 arch_register_class_mode(class), i);
4701 if(last_keep != NULL) {
4702 be_Keep_add_node(last_keep, class, in[0]);
4704 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4705 if(sched_is_scheduled(node)) {
4706 sched_add_after(node, last_keep);
4713 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4716 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4718 ir_graph *irg = be_get_birg_irg(cg->birg);
4719 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4722 /* do the transformation */
4723 void ia32_transform_graph(ia32_code_gen_t *cg) {
4724 ir_graph *irg = cg->irg;
4726 register_transformers();
4728 initial_fpcw = NULL;
4730 heights = heights_new(irg);
4731 calculate_non_address_mode_nodes(irg);
4733 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4735 free_non_address_mode_nodes();
4736 heights_free(heights);
4740 void ia32_init_transform(void)
4742 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");