2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
33 #include "irgraph_t.h"
38 #include "iredges_t.h"
54 #include "betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_common_transform.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_transform.h"
61 #include "ia32_new_nodes.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_address_mode.h"
65 #include "ia32_architecture.h"
67 #include "gen_ia32_regalloc_if.h"
69 /* define this to construct SSE constants instead of load them */
70 #undef CONSTRUCT_SSE_CONST
72 #define mode_fp (ia32_reg_classes[CLASS_ia32_fp].mode)
73 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
75 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
77 static ir_node *old_initial_fpcw = NULL;
78 static ir_node *initial_fpcw = NULL;
79 int ia32_no_pic_adjust;
81 typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
82 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
85 typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
86 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
89 typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
90 ir_node *op1, ir_node *op2);
92 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
93 ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
95 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
96 ir_node *base, ir_node *index, ir_node *mem);
98 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
99 ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
102 typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
104 static ir_node *create_immediate_or_transform(ir_node *node);
106 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
107 dbg_info *dbgi, ir_node *block,
108 ir_node *op, ir_node *orig_node);
110 /* its enough to have those once */
111 static ir_node *nomem, *noreg_GP;
113 /** a list to postprocess all calls */
114 static ir_node **call_list;
115 static ir_type **call_types;
117 /** Return non-zero is a node represents the 0 constant. */
118 static bool is_Const_0(ir_node *node)
120 return is_Const(node) && is_Const_null(node);
123 /** Return non-zero is a node represents the 1 constant. */
124 static bool is_Const_1(ir_node *node)
126 return is_Const(node) && is_Const_one(node);
129 /** Return non-zero is a node represents the -1 constant. */
130 static bool is_Const_Minus_1(ir_node *node)
132 return is_Const(node) && is_Const_all_one(node);
136 * returns true if constant can be created with a simple float command
138 static bool is_simple_x87_Const(ir_node *node)
140 ir_tarval *tv = get_Const_tarval(node);
141 if (tarval_is_null(tv) || tarval_is_one(tv))
144 /* TODO: match all the other float constants */
149 * returns true if constant can be created with a simple float command
151 static bool is_simple_sse_Const(ir_node *node)
153 ir_tarval *tv = get_Const_tarval(node);
154 ir_mode *mode = get_tarval_mode(tv);
159 if (tarval_is_null(tv)
160 #ifdef CONSTRUCT_SSE_CONST
165 #ifdef CONSTRUCT_SSE_CONST
166 if (mode == mode_D) {
167 unsigned val = get_tarval_sub_bits(tv, 0) |
168 (get_tarval_sub_bits(tv, 1) << 8) |
169 (get_tarval_sub_bits(tv, 2) << 16) |
170 (get_tarval_sub_bits(tv, 3) << 24);
172 /* lower 32bit are zero, really a 32bit constant */
175 #endif /* CONSTRUCT_SSE_CONST */
176 /* TODO: match all the other float constants */
181 * return NoREG or pic_base in case of PIC.
182 * This is necessary as base address for newly created symbols
184 static ir_node *get_symconst_base(void)
186 ir_graph *irg = current_ir_graph;
188 if (be_options.pic) {
189 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
190 return arch_env->impl->get_pic_base(irg);
197 * Transforms a Const.
199 static ir_node *gen_Const(ir_node *node)
201 ir_node *old_block = get_nodes_block(node);
202 ir_node *block = be_transform_node(old_block);
203 dbg_info *dbgi = get_irn_dbg_info(node);
204 ir_mode *mode = get_irn_mode(node);
205 ir_tarval *tv = get_Const_tarval(node);
207 assert(is_Const(node));
209 if (mode_is_float(mode)) {
210 ir_graph *irg = get_irn_irg(node);
211 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
212 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
217 if (ia32_cg_config.use_sse2) {
218 if (tarval_is_null(tv)) {
219 load = new_bd_ia32_xZero(dbgi, block);
220 set_ia32_ls_mode(load, mode);
222 #ifdef CONSTRUCT_SSE_CONST
223 } else if (tarval_is_one(tv)) {
224 int cnst = mode == mode_F ? 26 : 55;
225 ir_node *imm1 = ia32_create_Immediate(irg, NULL, 0, cnst);
226 ir_node *imm2 = ia32_create_Immediate(irg, NULL, 0, 2);
227 ir_node *pslld, *psrld;
229 load = new_bd_ia32_xAllOnes(dbgi, block);
230 set_ia32_ls_mode(load, mode);
231 pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
232 set_ia32_ls_mode(pslld, mode);
233 psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
234 set_ia32_ls_mode(psrld, mode);
236 #endif /* CONSTRUCT_SSE_CONST */
237 } else if (mode == mode_F) {
238 /* we can place any 32bit constant by using a movd gp, sse */
239 unsigned val = get_tarval_sub_bits(tv, 0) |
240 (get_tarval_sub_bits(tv, 1) << 8) |
241 (get_tarval_sub_bits(tv, 2) << 16) |
242 (get_tarval_sub_bits(tv, 3) << 24);
243 ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
244 load = new_bd_ia32_xMovd(dbgi, block, cnst);
245 set_ia32_ls_mode(load, mode);
249 #ifdef CONSTRUCT_SSE_CONST
250 if (mode == mode_D) {
251 unsigned val = get_tarval_sub_bits(tv, 0) |
252 (get_tarval_sub_bits(tv, 1) << 8) |
253 (get_tarval_sub_bits(tv, 2) << 16) |
254 (get_tarval_sub_bits(tv, 3) << 24);
256 ir_node *imm32 = ia32_create_Immediate(irg, NULL, 0, 32);
257 ir_node *cnst, *psllq;
259 /* fine, lower 32bit are zero, produce 32bit value */
260 val = get_tarval_sub_bits(tv, 4) |
261 (get_tarval_sub_bits(tv, 5) << 8) |
262 (get_tarval_sub_bits(tv, 6) << 16) |
263 (get_tarval_sub_bits(tv, 7) << 24);
264 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
265 load = new_bd_ia32_xMovd(dbgi, block, cnst);
266 set_ia32_ls_mode(load, mode);
267 psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
268 set_ia32_ls_mode(psllq, mode);
273 #endif /* CONSTRUCT_SSE_CONST */
274 floatent = ia32_create_float_const_entity(isa, tv, NULL);
276 base = get_symconst_base();
277 load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
279 set_ia32_op_type(load, ia32_AddrModeS);
280 set_ia32_am_sc(load, floatent);
281 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
282 res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
285 if (tarval_is_null(tv)) {
286 load = new_bd_ia32_fldz(dbgi, block);
288 set_ia32_ls_mode(load, mode);
289 } else if (tarval_is_one(tv)) {
290 load = new_bd_ia32_fld1(dbgi, block);
292 set_ia32_ls_mode(load, mode);
297 floatent = ia32_create_float_const_entity(isa, tv, NULL);
298 /* create_float_const_ent is smart and sometimes creates
300 ls_mode = get_type_mode(get_entity_type(floatent));
301 base = get_symconst_base();
302 load = new_bd_ia32_fld(dbgi, block, base, noreg_GP, nomem,
304 set_ia32_op_type(load, ia32_AddrModeS);
305 set_ia32_am_sc(load, floatent);
306 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
307 res = new_r_Proj(load, mode_fp, pn_ia32_fld_res);
310 #ifdef CONSTRUCT_SSE_CONST
312 #endif /* CONSTRUCT_SSE_CONST */
313 SET_IA32_ORIG_NODE(load, node);
315 } else { /* non-float mode */
319 tv = tarval_convert_to(tv, mode_Iu);
321 if (tv == get_tarval_bad() || tv == get_tarval_undefined() ||
323 panic("couldn't convert constant tarval (%+F)", node);
325 val = get_tarval_long(tv);
327 cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
328 SET_IA32_ORIG_NODE(cnst, node);
335 * Transforms a SymConst.
337 static ir_node *gen_SymConst(ir_node *node)
339 ir_node *old_block = get_nodes_block(node);
340 ir_node *block = be_transform_node(old_block);
341 dbg_info *dbgi = get_irn_dbg_info(node);
342 ir_mode *mode = get_irn_mode(node);
345 if (mode_is_float(mode)) {
346 if (ia32_cg_config.use_sse2)
347 cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D);
349 cnst = new_bd_ia32_fld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if (get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 if (get_entity_owner(entity) == get_tls_type()) {
360 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
361 ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
362 set_ia32_am_sc(lea, entity);
365 cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
369 SET_IA32_ORIG_NODE(cnst, node);
374 static ir_type *make_array_type(ir_type *tp)
376 unsigned alignment = get_type_alignment_bytes(tp);
377 unsigned size = get_type_size_bytes(tp);
378 ir_type *res = new_type_array(1, tp);
379 set_type_alignment_bytes(res, alignment);
380 set_array_bounds_int(res, 0, 0, 2);
381 if (alignment > size)
383 set_type_size_bytes(res, 2 * size);
384 set_type_state(res, layout_fixed);
389 * Create a float[2] array type for the given atomic type.
391 * @param tp the atomic type
393 static ir_type *ia32_create_float_array(ir_type *tp)
395 ir_mode *mode = get_type_mode(tp);
398 if (mode == mode_F) {
399 static ir_type *float_F;
403 arr = float_F = make_array_type(tp);
404 } else if (mode == mode_D) {
405 static ir_type *float_D;
409 arr = float_D = make_array_type(tp);
411 static ir_type *float_E;
415 arr = float_E = make_array_type(tp);
420 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
421 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
423 static const struct {
425 const char *cnst_str;
427 } names [ia32_known_const_max] = {
428 { "C_sfp_sign", "0x80000000", 0 },
429 { "C_dfp_sign", "0x8000000000000000", 1 },
430 { "C_sfp_abs", "0x7FFFFFFF", 0 },
431 { "C_dfp_abs", "0x7FFFFFFFFFFFFFFF", 1 },
432 { "C_ull_bias", "0x10000000000000000", 2 }
434 static ir_entity *ent_cache[ia32_known_const_max];
436 ir_entity *ent = ent_cache[kct];
439 ir_graph *irg = current_ir_graph;
440 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
441 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
442 const char *cnst_str = names[kct].cnst_str;
443 ident *name = new_id_from_str(names[kct].name);
446 switch (names[kct].mode) {
447 case 0: mode = mode_Iu; break;
448 case 1: mode = mode_Lu; break;
449 case 2: mode = mode_F; break;
450 default: panic("internal compiler error");
452 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
454 if (kct == ia32_ULLBIAS) {
455 ir_type *type = ia32_get_prim_type(mode_F);
456 ir_type *atype = ia32_create_float_array(type);
457 ir_initializer_t *initializer;
459 ent = new_entity(get_glob_type(), name, atype);
461 set_entity_ld_ident(ent, name);
462 set_entity_visibility(ent, ir_visibility_private);
463 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
465 initializer = create_initializer_compound(2);
466 set_initializer_compound_value(initializer, 0,
467 create_initializer_tarval(get_mode_null(mode)));
468 set_initializer_compound_value(initializer, 1,
469 create_initializer_tarval(tv));
470 set_entity_initializer(ent, initializer);
472 ent = ia32_create_float_const_entity(isa, tv, name);
474 /* cache the entry */
475 ent_cache[kct] = ent;
478 return ent_cache[kct];
482 * return true if the node is a Proj(Load) and could be used in source address
483 * mode for another node. Will return only true if the @p other node is not
484 * dependent on the memory of the Load (for binary operations use the other
485 * input here, for unary operations use NULL).
487 static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
488 ir_node *other, ir_node *other2,
495 /* float constants are always available */
496 if (is_Const(node)) {
497 mode = get_irn_mode(node);
498 if (mode_is_float(mode)) {
499 ir_tarval *tv = get_Const_tarval(node);
500 if (!tarval_ieee754_can_conv_lossless(tv, mode_D))
502 if (ia32_cg_config.use_sse2) {
503 if (is_simple_sse_Const(node))
506 if (is_simple_x87_Const(node))
509 if (get_irn_n_edges(node) > 1)
518 load = get_Proj_pred(node);
519 pn = get_Proj_proj(node);
520 if (!is_Load(load) || pn != pn_Load_res)
522 if (get_nodes_block(load) != block)
524 mode = get_irn_mode(node);
525 /* we can't fold mode_E AM */
526 if (mode == ia32_mode_E)
528 /* we only use address mode if we're the only user of the load */
529 if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
531 /* in some edge cases with address mode we might reach the load normally
532 * and through some AM sequence, if it is already materialized then we
533 * can't create an AM node from it */
534 if (be_is_transformed(node))
537 /* don't do AM if other node inputs depend on the load (via mem-proj) */
538 if (other != NULL && ia32_prevents_AM(block, load, other))
541 if (other2 != NULL && ia32_prevents_AM(block, load, other2))
547 typedef struct ia32_address_mode_t ia32_address_mode_t;
548 struct ia32_address_mode_t {
553 ia32_op_type_t op_type;
557 unsigned commutative : 1;
558 unsigned ins_permuted : 1;
561 static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
563 /* construct load address */
564 memset(addr, 0, sizeof(addr[0]));
565 ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
567 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
568 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
569 addr->mem = be_transform_node(mem);
572 static void build_address(ia32_address_mode_t *am, ir_node *node,
573 ia32_create_am_flags_t flags)
575 ia32_address_t *addr = &am->addr;
581 /* floating point immediates */
582 if (is_Const(node)) {
583 ir_graph *irg = get_irn_irg(node);
584 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
585 ia32_isa_t *isa = (ia32_isa_t*) arch_env;
586 ir_tarval *tv = get_Const_tarval(node);
587 ir_entity *entity = ia32_create_float_const_entity(isa, tv, NULL);
588 addr->base = get_symconst_base();
589 addr->index = noreg_GP;
591 addr->symconst_ent = entity;
592 addr->tls_segment = false;
594 am->ls_mode = get_type_mode(get_entity_type(entity));
595 am->pinned = op_pin_state_floats;
599 load = get_Proj_pred(node);
600 ptr = get_Load_ptr(load);
601 mem = get_Load_mem(load);
602 new_mem = be_transform_node(mem);
603 am->pinned = get_irn_pinned(load);
604 am->ls_mode = get_Load_mode(load);
605 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
608 /* construct load address */
609 ia32_create_address_mode(addr, ptr, flags);
611 addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
612 addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
616 static void set_address(ir_node *node, const ia32_address_t *addr)
618 set_ia32_am_scale(node, addr->scale);
619 set_ia32_am_sc(node, addr->symconst_ent);
620 set_ia32_am_offs_int(node, addr->offset);
621 set_ia32_am_tls_segment(node, addr->tls_segment);
622 if (addr->symconst_sign)
623 set_ia32_am_sc_sign(node);
625 set_ia32_use_frame(node);
626 set_ia32_frame_ent(node, addr->frame_entity);
630 * Apply attributes of a given address mode to a node.
632 static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
634 set_address(node, &am->addr);
636 set_ia32_op_type(node, am->op_type);
637 set_ia32_ls_mode(node, am->ls_mode);
638 if (am->pinned == op_pin_state_pinned) {
639 /* beware: some nodes are already pinned and did not allow to change the state */
640 if (get_irn_pinned(node) != op_pin_state_pinned)
641 set_irn_pinned(node, op_pin_state_pinned);
644 set_ia32_commutative(node);
648 * Check, if a given node is a Down-Conv, ie. a integer Conv
649 * from a mode with a mode with more bits to a mode with lesser bits.
650 * Moreover, we return only true if the node has not more than 1 user.
652 * @param node the node
653 * @return non-zero if node is a Down-Conv
655 static int is_downconv(const ir_node *node)
663 src_mode = get_irn_mode(get_Conv_op(node));
664 dest_mode = get_irn_mode(node);
666 ia32_mode_needs_gp_reg(src_mode) &&
667 ia32_mode_needs_gp_reg(dest_mode) &&
668 get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
671 /** Skip all Down-Conv's on a given node and return the resulting node. */
672 ir_node *ia32_skip_downconv(ir_node *node)
674 while (is_downconv(node)) {
675 /* we only want to skip the conv when we're the only user
676 * (because this test is used in the context of address-mode selection
677 * and we don't want to use address mode for multiple users) */
678 if (get_irn_n_edges(node) > 1)
681 node = get_Conv_op(node);
687 static bool is_float_downconv(const ir_node *node)
691 ir_node *pred = get_Conv_op(node);
692 ir_mode *pred_mode = get_irn_mode(pred);
693 ir_mode *mode = get_irn_mode(node);
694 return mode_is_float(pred_mode)
695 && get_mode_size_bits(mode) <= get_mode_size_bits(pred_mode);
698 static ir_node *ia32_skip_float_downconv(ir_node *node)
700 while (is_float_downconv(node)) {
701 node = get_Conv_op(node);
706 static bool is_sameconv(ir_node *node)
714 /* we only want to skip the conv when we're the only user
715 * (because this test is used in the context of address-mode selection
716 * and we don't want to use address mode for multiple users) */
717 if (get_irn_n_edges(node) > 1)
720 src_mode = get_irn_mode(get_Conv_op(node));
721 dest_mode = get_irn_mode(node);
723 ia32_mode_needs_gp_reg(src_mode) &&
724 ia32_mode_needs_gp_reg(dest_mode) &&
725 get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
728 /** Skip all signedness convs */
729 static ir_node *ia32_skip_sameconv(ir_node *node)
731 while (is_sameconv(node)) {
732 node = get_Conv_op(node);
738 static ir_node *transform_sext(ir_node *node, ir_node *orig_node)
740 ir_mode *mode = get_irn_mode(node);
741 ir_node *block = get_nodes_block(node);
742 dbg_info *dbgi = get_irn_dbg_info(node);
743 return create_I2I_Conv(mode, mode_Is, dbgi, block, node, orig_node);
746 static ir_node *transform_zext(ir_node *node, ir_node *orig_node)
748 ir_mode *mode = get_irn_mode(node);
749 ir_node *block = get_nodes_block(node);
750 dbg_info *dbgi = get_irn_dbg_info(node);
751 /* normalize to an unsigned mode */
752 switch (get_mode_size_bits(mode)) {
753 case 8: mode = mode_Bu; break;
754 case 16: mode = mode_Hu; break;
756 panic("ia32: invalid mode in zest: %+F", node);
758 return create_I2I_Conv(mode, mode_Iu, dbgi, block, node, orig_node);
761 static ir_node *transform_upconv(ir_node *node, ir_node *orig_node)
763 ir_mode *mode = get_irn_mode(node);
764 if (mode_is_signed(mode)) {
765 return transform_sext(node, orig_node);
767 return transform_zext(node, orig_node);
771 static ir_node *get_noreg(ir_mode *const mode)
773 if (!mode_is_float(mode)) {
775 } else if (ia32_cg_config.use_sse2) {
776 return ia32_new_NoReg_xmm(current_ir_graph);
778 return ia32_new_NoReg_fp(current_ir_graph);
783 * matches operands of a node into ia32 addressing/operand modes. This covers
784 * usage of source address mode, immediates, operations with non 32-bit modes,
786 * The resulting data is filled into the @p am struct. block is the block
787 * of the node whose arguments are matched. op1, op2 are the first and second
788 * input that are matched (op1 may be NULL). other_op is another unrelated
789 * input that is not matched! but which is needed sometimes to check if AM
790 * for op1/op2 is legal.
791 * @p flags describes the supported modes of the operation in detail.
793 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
794 ir_node *op1, ir_node *op2, ir_node *other_op,
797 ia32_address_t *addr = &am->addr;
798 ir_mode *mode = get_irn_mode(op2);
799 int mode_bits = get_mode_size_bits(mode);
800 ir_node *new_op1, *new_op2;
802 unsigned commutative;
803 int use_am_and_immediates;
806 memset(am, 0, sizeof(am[0]));
808 commutative = (flags & match_commutative) != 0;
809 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
810 use_am = (flags & match_am) != 0;
811 use_immediate = (flags & match_immediate) != 0;
812 assert(!use_am_and_immediates || use_immediate);
815 assert(!commutative || op1 != NULL);
816 assert(use_am || !(flags & match_8bit_am));
817 assert(use_am || !(flags & match_16bit_am));
819 if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
820 (mode_bits == 16 && !(flags & match_16bit_am))) {
824 /* we can simply skip downconvs for mode neutral nodes: the upper bits
825 * can be random for these operations */
826 if (flags & match_mode_neutral) {
827 op2 = ia32_skip_downconv(op2);
829 op1 = ia32_skip_downconv(op1);
832 op2 = ia32_skip_sameconv(op2);
834 op1 = ia32_skip_sameconv(op1);
838 /* match immediates. firm nodes are normalized: constants are always on the
841 if (!(flags & match_try_am) && use_immediate) {
842 new_op2 = ia32_try_create_Immediate(op2, 'i');
845 if (new_op2 == NULL &&
846 use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
847 build_address(am, op2, ia32_create_am_normal);
848 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
849 new_op2 = get_noreg(mode);
850 am->op_type = ia32_AddrModeS;
851 } else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
853 ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
854 build_address(am, op1, ia32_create_am_normal);
856 ir_node *const noreg = get_noreg(mode);
857 if (new_op2 != NULL) {
860 new_op1 = be_transform_node(op2);
862 am->ins_permuted = true;
864 am->op_type = ia32_AddrModeS;
866 am->op_type = ia32_Normal;
868 if (flags & match_try_am) {
874 mode = get_irn_mode(op2);
875 if (get_mode_size_bits(mode) != 32
876 && (flags & (match_mode_neutral | match_upconv | match_zero_ext))) {
877 if (flags & match_upconv) {
878 new_op1 = (op1 == NULL ? NULL : transform_upconv(op1, op1));
880 new_op2 = transform_upconv(op2, op2);
881 } else if (flags & match_zero_ext) {
882 new_op1 = (op1 == NULL ? NULL : transform_zext(op1, op1));
884 new_op2 = transform_zext(op2, op2);
886 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
888 new_op2 = be_transform_node(op2);
889 assert(flags & match_mode_neutral);
893 new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
895 new_op2 = be_transform_node(op2);
899 if (addr->base == NULL)
900 addr->base = noreg_GP;
901 if (addr->index == NULL)
902 addr->index = noreg_GP;
903 if (addr->mem == NULL)
906 am->new_op1 = new_op1;
907 am->new_op2 = new_op2;
908 am->commutative = commutative;
912 * "Fixes" a node that uses address mode by turning it into mode_T
913 * and returning a pn_ia32_res Proj.
915 * @param node the node
916 * @param am its address mode
918 * @return a Proj(pn_ia32_res) if a memory address mode is used,
921 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
926 if (am->mem_proj == NULL)
929 /* we have to create a mode_T so the old MemProj can attach to us */
930 mode = get_irn_mode(node);
931 load = get_Proj_pred(am->mem_proj);
933 be_set_transformed_node(load, node);
935 if (mode != mode_T) {
936 set_irn_mode(node, mode_T);
937 return new_rd_Proj(NULL, node, mode, pn_ia32_res);
944 * Construct a standard binary operation, set AM and immediate if required.
946 * @param node The original node for which the binop is created
947 * @param op1 The first operand
948 * @param op2 The second operand
949 * @param func The node constructor function
950 * @return The constructed ia32 node.
952 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
953 construct_binop_func *func, match_flags_t flags)
956 ir_node *block, *new_block, *new_node;
957 ia32_address_mode_t am;
958 ia32_address_t *addr = &am.addr;
960 block = get_nodes_block(node);
961 match_arguments(&am, block, op1, op2, NULL, flags);
963 dbgi = get_irn_dbg_info(node);
964 new_block = be_transform_node(block);
965 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
966 am.new_op1, am.new_op2);
967 set_am_attributes(new_node, &am);
968 /* we can't use source address mode anymore when using immediates */
969 if (!(flags & match_am_and_immediates) &&
970 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
971 set_ia32_am_support(new_node, ia32_am_none);
972 SET_IA32_ORIG_NODE(new_node, node);
974 new_node = fix_mem_proj(new_node, &am);
980 * Generic names for the inputs of an ia32 binary op.
983 n_ia32_l_binop_left, /**< ia32 left input */
984 n_ia32_l_binop_right, /**< ia32 right input */
985 n_ia32_l_binop_eflags /**< ia32 eflags input */
987 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
988 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
989 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
990 COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
991 COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
992 COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
995 * Construct a binary operation which also consumes the eflags.
997 * @param node The node to transform
998 * @param func The node constructor function
999 * @param flags The match flags
1000 * @return The constructor ia32 node
1002 static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
1003 match_flags_t flags)
1005 ir_node *src_block = get_nodes_block(node);
1006 ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
1007 ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
1008 ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
1010 ir_node *block, *new_node, *new_eflags;
1011 ia32_address_mode_t am;
1012 ia32_address_t *addr = &am.addr;
1014 match_arguments(&am, src_block, op1, op2, eflags, flags);
1016 dbgi = get_irn_dbg_info(node);
1017 block = be_transform_node(src_block);
1018 new_eflags = be_transform_node(eflags);
1019 new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
1020 am.new_op1, am.new_op2, new_eflags);
1021 set_am_attributes(new_node, &am);
1022 /* we can't use source address mode anymore when using immediates */
1023 if (!(flags & match_am_and_immediates) &&
1024 (is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
1025 set_ia32_am_support(new_node, ia32_am_none);
1026 SET_IA32_ORIG_NODE(new_node, node);
1028 new_node = fix_mem_proj(new_node, &am);
1033 static ir_node *get_fpcw(void)
1035 if (initial_fpcw != NULL)
1036 return initial_fpcw;
1038 initial_fpcw = be_transform_node(old_initial_fpcw);
1039 return initial_fpcw;
1042 static ir_node *skip_float_upconv(ir_node *node)
1044 ir_mode *mode = get_irn_mode(node);
1045 assert(mode_is_float(mode));
1047 while (is_Conv(node)) {
1048 ir_node *pred = get_Conv_op(node);
1049 ir_mode *pred_mode = get_irn_mode(pred);
1052 * suboptimal, but without this check the address mode matcher
1053 * can incorrectly think that something has only 1 user
1055 if (get_irn_n_edges(node) > 1)
1058 if (!mode_is_float(pred_mode)
1059 || get_mode_size_bits(pred_mode) > get_mode_size_bits(mode))
1067 static void check_x87_floatmode(ir_mode *mode)
1069 if (mode != ia32_mode_E) {
1070 panic("ia32: x87 only supports x86 extended float mode");
1075 * Construct a standard binary operation, set AM and immediate if required.
1077 * @param op1 The first operand
1078 * @param op2 The second operand
1079 * @param func The node constructor function
1080 * @return The constructed ia32 node.
1082 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
1083 construct_binop_float_func *func)
1089 ia32_address_mode_t am;
1090 ia32_address_t *addr = &am.addr;
1091 ia32_x87_attr_t *attr;
1092 /* All operations are considered commutative, because there are reverse
1094 match_flags_t flags = match_commutative | match_am;
1096 = is_Div(node) ? get_Div_resmode(node) : get_irn_mode(node);
1097 check_x87_floatmode(mode);
1099 op1 = skip_float_upconv(op1);
1100 op2 = skip_float_upconv(op2);
1102 block = get_nodes_block(node);
1103 match_arguments(&am, block, op1, op2, NULL, flags);
1105 dbgi = get_irn_dbg_info(node);
1106 new_block = be_transform_node(block);
1107 new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
1108 am.new_op1, am.new_op2, get_fpcw());
1109 set_am_attributes(new_node, &am);
1111 attr = get_ia32_x87_attr(new_node);
1112 attr->attr.data.ins_permuted = am.ins_permuted;
1114 SET_IA32_ORIG_NODE(new_node, node);
1116 new_node = fix_mem_proj(new_node, &am);
1122 * Construct a shift/rotate binary operation, sets AM and immediate if required.
1124 * @param op1 The first operand
1125 * @param op2 The second operand
1126 * @param func The node constructor function
1127 * @return The constructed ia32 node.
1129 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
1130 construct_shift_func *func,
1131 match_flags_t flags)
1133 ir_mode *mode = get_irn_mode(node);
1135 assert(! mode_is_float(mode));
1136 assert(flags & match_immediate);
1137 assert((flags & ~(match_mode_neutral | match_zero_ext | match_upconv | match_immediate)) == 0);
1139 if (get_mode_modulo_shift(mode) != 32) {
1140 /* TODO: implement special cases for non-modulo shifts */
1141 panic("modulo shift!=32 not supported by ia32 backend");
1146 if (flags & match_mode_neutral) {
1147 op1 = ia32_skip_downconv(op1);
1148 new_op1 = be_transform_node(op1);
1150 op1 = ia32_skip_sameconv(op1);
1151 if (get_mode_size_bits(mode) != 32) {
1152 if (flags & match_upconv) {
1153 new_op1 = transform_upconv(op1, node);
1154 } else if (flags & match_zero_ext) {
1155 new_op1 = transform_zext(op1, node);
1157 /* match_mode_neutral not handled here because it makes no
1158 * sense for shift operations */
1159 panic("ia32 code selection failed for %+F", node);
1162 new_op1 = be_transform_node(op1);
1166 /* the shift amount can be any mode that is bigger than 5 bits, since all
1167 * other bits are ignored anyway */
1168 while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
1169 ir_node *const op = get_Conv_op(op2);
1170 if (mode_is_float(get_irn_mode(op)))
1173 assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
1175 new_op2 = create_immediate_or_transform(op2);
1177 dbg_info *dbgi = get_irn_dbg_info(node);
1178 ir_node *block = get_nodes_block(node);
1179 ir_node *new_block = be_transform_node(block);
1180 ir_node *new_node = func(dbgi, new_block, new_op1, new_op2);
1181 SET_IA32_ORIG_NODE(new_node, node);
1183 /* lowered shift instruction may have a dependency operand, handle it here */
1184 if (get_irn_arity(node) == 3) {
1185 /* we have a dependency */
1186 ir_node* dep = get_irn_n(node, 2);
1187 if (get_irn_n_edges(dep) > 1) {
1188 /* ... which has at least one user other than 'node' */
1189 ir_node *new_dep = be_transform_node(dep);
1190 add_irn_dep(new_node, new_dep);
1199 * Construct a standard unary operation, set AM and immediate if required.
1201 * @param op The operand
1202 * @param func The node constructor function
1203 * @return The constructed ia32 node.
1205 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
1206 match_flags_t flags)
1209 ir_node *block, *new_block, *new_op, *new_node;
1211 assert(flags == 0 || flags == match_mode_neutral);
1212 if (flags & match_mode_neutral) {
1213 op = ia32_skip_downconv(op);
1216 new_op = be_transform_node(op);
1217 dbgi = get_irn_dbg_info(node);
1218 block = get_nodes_block(node);
1219 new_block = be_transform_node(block);
1220 new_node = func(dbgi, new_block, new_op);
1222 SET_IA32_ORIG_NODE(new_node, node);
1227 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
1228 ia32_address_t *addr)
1238 base = be_transform_node(base);
1245 idx = be_transform_node(idx);
1248 /* segment overrides are ineffective for Leas :-( so we have to patch
1250 if (addr->tls_segment) {
1251 ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
1252 assert(addr->symconst_ent != NULL);
1253 if (base == noreg_GP)
1256 base = new_bd_ia32_Lea(dbgi, block, tls_base, base);
1257 addr->tls_segment = false;
1260 res = new_bd_ia32_Lea(dbgi, block, base, idx);
1261 set_address(res, addr);
1267 * Returns non-zero if a given address mode has a symbolic or
1268 * numerical offset != 0.
1270 static int am_has_immediates(const ia32_address_t *addr)
1272 return addr->offset != 0 || addr->symconst_ent != NULL
1273 || addr->frame_entity || addr->use_frame;
1276 typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block,
1277 ir_node *high, ir_node *low,
1281 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
1282 * op1 - target to be shifted
1283 * op2 - contains bits to be shifted into target
1285 * Only op3 can be an immediate.
1287 static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block,
1288 ir_node *high, ir_node *low, ir_node *count,
1289 new_shiftd_func func)
1291 ir_node *new_block = be_transform_node(block);
1292 ir_node *new_high = be_transform_node(high);
1293 ir_node *new_low = be_transform_node(low);
1297 /* the shift amount can be any mode that is bigger than 5 bits, since all
1298 * other bits are ignored anyway */
1299 while (is_Conv(count) &&
1300 get_irn_n_edges(count) == 1 &&
1301 mode_is_int(get_irn_mode(count))) {
1302 assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
1303 count = get_Conv_op(count);
1305 new_count = create_immediate_or_transform(count);
1307 new_node = func(dbgi, new_block, new_high, new_low, new_count);
1312 * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
1315 static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
1317 if (is_Const(value1) && is_Const(value2)) {
1318 ir_tarval *tv1 = get_Const_tarval(value1);
1319 ir_tarval *tv2 = get_Const_tarval(value2);
1320 if (tarval_is_long(tv1) && tarval_is_long(tv2)) {
1321 long v1 = get_tarval_long(tv1);
1322 long v2 = get_tarval_long(tv2);
1323 return v1 <= v2 && v2 == 32-v1;
1329 static ir_node *match_64bit_shift(ir_node *node)
1331 ir_node *op1 = get_binop_left(node);
1332 ir_node *op2 = get_binop_right(node);
1333 assert(is_Or(node) || is_Add(node));
1341 /* match ShlD operation */
1342 if (is_Shl(op1) && is_Shr(op2)) {
1343 ir_node *shl_right = get_Shl_right(op1);
1344 ir_node *shl_left = get_Shl_left(op1);
1345 ir_node *shr_right = get_Shr_right(op2);
1346 ir_node *shr_left = get_Shr_left(op2);
1347 /* constant ShlD operation */
1348 if (is_complementary_shifts(shl_right, shr_right)) {
1349 dbg_info *dbgi = get_irn_dbg_info(node);
1350 ir_node *block = get_nodes_block(node);
1351 return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right,
1354 /* constant ShrD operation */
1355 if (is_complementary_shifts(shr_right, shl_right)) {
1356 dbg_info *dbgi = get_irn_dbg_info(node);
1357 ir_node *block = get_nodes_block(node);
1358 return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right,
1361 /* lower_dw produces the following for ShlD:
1362 * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */
1363 if (is_Shr(shr_left) && is_Not(shr_right)
1364 && is_Const_1(get_Shr_right(shr_left))
1365 && get_Not_op(shr_right) == shl_right) {
1366 dbg_info *dbgi = get_irn_dbg_info(node);
1367 ir_node *block = get_nodes_block(node);
1368 ir_node *val_h = get_Shr_left(shr_left);
1369 return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right,
1372 /* lower_dw produces the following for ShrD:
1373 * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */
1374 if (is_Shl(shl_left) && is_Not(shl_right)
1375 && is_Const_1(get_Shl_right(shl_left))
1376 && get_Not_op(shl_right) == shr_right) {
1377 dbg_info *dbgi = get_irn_dbg_info(node);
1378 ir_node *block = get_nodes_block(node);
1379 ir_node *val_h = get_Shl_left(shl_left);
1380 return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right,
1389 * Creates an ia32 Add.
1391 * @return the created ia32 Add node
1393 static ir_node *gen_Add(ir_node *node)
1395 ir_mode *mode = get_irn_mode(node);
1396 ir_node *op1 = get_Add_left(node);
1397 ir_node *op2 = get_Add_right(node);
1399 ir_node *block, *new_block, *new_node, *add_immediate_op;
1400 ia32_address_t addr;
1401 ia32_address_mode_t am;
1403 new_node = match_64bit_shift(node);
1404 if (new_node != NULL)
1407 if (mode_is_float(mode)) {
1408 if (ia32_cg_config.use_sse2)
1409 return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
1410 match_commutative | match_am);
1412 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fadd);
1415 ia32_mark_non_am(node);
1419 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
1420 * 1. Add with immediate -> Lea
1421 * 2. Add with possible source address mode -> Add
1422 * 3. Otherwise -> Lea
1424 memset(&addr, 0, sizeof(addr));
1425 ia32_create_address_mode(&addr, node, ia32_create_am_force);
1426 add_immediate_op = NULL;
1428 dbgi = get_irn_dbg_info(node);
1429 block = get_nodes_block(node);
1430 new_block = be_transform_node(block);
1433 if (addr.base == NULL && addr.index == NULL) {
1434 new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
1435 addr.symconst_sign, 0, addr.offset);
1436 SET_IA32_ORIG_NODE(new_node, node);
1439 /* add with immediate? */
1440 if (addr.index == NULL) {
1441 add_immediate_op = addr.base;
1442 } else if (addr.base == NULL && addr.scale == 0) {
1443 add_immediate_op = addr.index;
1446 if (add_immediate_op != NULL) {
1447 if (!am_has_immediates(&addr)) {
1448 #ifdef DEBUG_libfirm
1449 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
1452 return be_transform_node(add_immediate_op);
1455 new_node = create_lea_from_address(dbgi, new_block, &addr);
1456 SET_IA32_ORIG_NODE(new_node, node);
1460 /* test if we can use source address mode */
1461 match_arguments(&am, block, op1, op2, NULL, match_commutative
1462 | match_mode_neutral | match_am | match_immediate | match_try_am);
1464 /* construct an Add with source address mode */
1465 if (am.op_type == ia32_AddrModeS) {
1466 ia32_address_t *am_addr = &am.addr;
1467 new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
1468 am_addr->index, am_addr->mem, am.new_op1,
1470 set_am_attributes(new_node, &am);
1471 SET_IA32_ORIG_NODE(new_node, node);
1473 new_node = fix_mem_proj(new_node, &am);
1478 /* otherwise construct a lea */
1479 new_node = create_lea_from_address(dbgi, new_block, &addr);
1480 SET_IA32_ORIG_NODE(new_node, node);
1485 * Creates an ia32 Mul.
1487 * @return the created ia32 Mul node
1489 static ir_node *gen_Mul(ir_node *node)
1491 ir_node *op1 = get_Mul_left(node);
1492 ir_node *op2 = get_Mul_right(node);
1493 ir_mode *mode = get_irn_mode(node);
1495 if (mode_is_float(mode)) {
1496 if (ia32_cg_config.use_sse2)
1497 return gen_binop(node, op1, op2, new_bd_ia32_xMul,
1498 match_commutative | match_am);
1500 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fmul);
1502 return gen_binop(node, op1, op2, new_bd_ia32_IMul,
1503 match_commutative | match_am | match_mode_neutral |
1504 match_immediate | match_am_and_immediates);
1508 * Creates an ia32 Mulh.
1509 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
1510 * this result while Mul returns the lower 32 bit.
1512 * @return the created ia32 Mulh node
1514 static ir_node *gen_Mulh(ir_node *node)
1516 dbg_info *dbgi = get_irn_dbg_info(node);
1517 ir_node *op1 = get_Mulh_left(node);
1518 ir_node *op2 = get_Mulh_right(node);
1519 ir_mode *mode = get_irn_mode(node);
1521 ir_node *proj_res_high;
1523 if (get_mode_size_bits(mode) != 32) {
1524 panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
1527 if (mode_is_signed(mode)) {
1528 new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
1529 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
1531 new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
1532 proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_Mul_res_high);
1534 return proj_res_high;
1538 * Creates an ia32 And.
1540 * @return The created ia32 And node
1542 static ir_node *gen_And(ir_node *node)
1544 ir_node *op1 = get_And_left(node);
1545 ir_node *op2 = get_And_right(node);
1546 assert(! mode_is_float(get_irn_mode(node)));
1548 /* is it a zero extension? */
1549 if (is_Const(op2)) {
1550 ir_tarval *tv = get_Const_tarval(op2);
1551 long v = get_tarval_long(tv);
1553 if (v == 0xFF || v == 0xFFFF) {
1554 dbg_info *dbgi = get_irn_dbg_info(node);
1555 ir_node *block = get_nodes_block(node);
1562 assert(v == 0xFFFF);
1565 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1570 return gen_binop(node, op1, op2, new_bd_ia32_And,
1571 match_commutative | match_mode_neutral | match_am | match_immediate);
1575 * Creates an ia32 Or.
1577 * @return The created ia32 Or node
1579 static ir_node *gen_Or(ir_node *node)
1581 ir_node *op1 = get_Or_left(node);
1582 ir_node *op2 = get_Or_right(node);
1585 res = match_64bit_shift(node);
1589 assert (! mode_is_float(get_irn_mode(node)));
1590 return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
1591 | match_mode_neutral | match_am | match_immediate);
1597 * Creates an ia32 Eor.
1599 * @return The created ia32 Eor node
1601 static ir_node *gen_Eor(ir_node *node)
1603 ir_node *op1 = get_Eor_left(node);
1604 ir_node *op2 = get_Eor_right(node);
1606 assert(! mode_is_float(get_irn_mode(node)));
1607 return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
1608 | match_mode_neutral | match_am | match_immediate);
1613 * Creates an ia32 Sub.
1615 * @return The created ia32 Sub node
1617 static ir_node *gen_Sub(ir_node *node)
1619 ir_node *op1 = get_Sub_left(node);
1620 ir_node *op2 = get_Sub_right(node);
1621 ir_mode *mode = get_irn_mode(node);
1623 if (mode_is_float(mode)) {
1624 if (ia32_cg_config.use_sse2)
1625 return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
1627 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fsub);
1630 if (is_Const(op2)) {
1631 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1635 return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
1636 | match_am | match_immediate);
1639 static ir_node *transform_AM_mem(ir_node *const block,
1640 ir_node *const src_val,
1641 ir_node *const src_mem,
1642 ir_node *const am_mem)
1644 if (is_NoMem(am_mem)) {
1645 return be_transform_node(src_mem);
1646 } else if (is_Proj(src_val) &&
1648 get_Proj_pred(src_val) == get_Proj_pred(src_mem)) {
1649 /* avoid memory loop */
1651 } else if (is_Proj(src_val) && is_Sync(src_mem)) {
1652 ir_node *const ptr_pred = get_Proj_pred(src_val);
1653 int const arity = get_Sync_n_preds(src_mem);
1658 NEW_ARR_A(ir_node*, ins, arity + 1);
1660 /* NOTE: This sometimes produces dead-code because the old sync in
1661 * src_mem might not be used anymore, we should detect this case
1662 * and kill the sync... */
1663 for (i = arity - 1; i >= 0; --i) {
1664 ir_node *const pred = get_Sync_pred(src_mem, i);
1666 /* avoid memory loop */
1667 if (is_Proj(pred) && get_Proj_pred(pred) == ptr_pred)
1670 ins[n++] = be_transform_node(pred);
1673 if (n==1 && ins[0] == am_mem) {
1675 /* creating a new Sync and relying on CSE may fail,
1676 * if am_mem is a ProjM, which does not yet verify. */
1680 return new_r_Sync(block, n, ins);
1684 ins[0] = be_transform_node(src_mem);
1686 return new_r_Sync(block, 2, ins);
1691 * Create a 32bit to 64bit signed extension.
1693 * @param dbgi debug info
1694 * @param block the block where node nodes should be placed
1695 * @param val the value to extend
1696 * @param orig the original node
1698 static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
1699 ir_node *val, const ir_node *orig)
1704 if (ia32_cg_config.use_short_sex_eax) {
1705 ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
1706 res = new_bd_ia32_Cltd(dbgi, block, val, pval);
1708 ir_graph *const irg = get_Block_irg(block);
1709 ir_node *const imm31 = ia32_create_Immediate(irg, NULL, 0, 31);
1710 res = new_bd_ia32_Sar(dbgi, block, val, imm31);
1712 SET_IA32_ORIG_NODE(res, orig);
1717 * Generates an ia32 Div with additional infrastructure for the
1718 * register allocator if needed.
1720 static ir_node *create_Div(ir_node *node)
1722 dbg_info *dbgi = get_irn_dbg_info(node);
1723 ir_node *block = get_nodes_block(node);
1724 ir_node *new_block = be_transform_node(block);
1725 int throws_exception = ir_throws_exception(node);
1732 ir_node *sign_extension;
1733 ia32_address_mode_t am;
1734 ia32_address_t *addr = &am.addr;
1736 /* the upper bits have random contents for smaller modes */
1737 switch (get_irn_opcode(node)) {
1739 op1 = get_Div_left(node);
1740 op2 = get_Div_right(node);
1741 mem = get_Div_mem(node);
1742 mode = get_Div_resmode(node);
1745 op1 = get_Mod_left(node);
1746 op2 = get_Mod_right(node);
1747 mem = get_Mod_mem(node);
1748 mode = get_Mod_resmode(node);
1751 panic("invalid divmod node %+F", node);
1754 match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv);
1756 /* Beware: We don't need a Sync, if the memory predecessor of the Div node
1757 is the memory of the consumed address. We can have only the second op as address
1758 in Div nodes, so check only op2. */
1759 new_mem = transform_AM_mem(block, op2, mem, addr->mem);
1761 if (mode_is_signed(mode)) {
1762 sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
1763 new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
1764 addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
1766 sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
1768 new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
1769 addr->index, new_mem, am.new_op2,
1770 am.new_op1, sign_extension);
1772 ir_set_throws_exception(new_node, throws_exception);
1774 set_irn_pinned(new_node, get_irn_pinned(node));
1776 set_am_attributes(new_node, &am);
1777 SET_IA32_ORIG_NODE(new_node, node);
1779 new_node = fix_mem_proj(new_node, &am);
1785 * Generates an ia32 Mod.
1787 static ir_node *gen_Mod(ir_node *node)
1789 return create_Div(node);
1793 * Generates an ia32 Div.
1795 static ir_node *gen_Div(ir_node *node)
1797 ir_mode *mode = get_Div_resmode(node);
1798 if (mode_is_float(mode)) {
1799 ir_node *op1 = get_Div_left(node);
1800 ir_node *op2 = get_Div_right(node);
1802 if (ia32_cg_config.use_sse2) {
1803 return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
1805 return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fdiv);
1809 return create_Div(node);
1813 * Creates an ia32 Shl.
1815 * @return The created ia32 Shl node
1817 static ir_node *gen_Shl(ir_node *node)
1819 ir_node *left = get_Shl_left(node);
1820 ir_node *right = get_Shl_right(node);
1822 return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
1823 match_mode_neutral | match_immediate);
1827 * Creates an ia32 Shr.
1829 * @return The created ia32 Shr node
1831 static ir_node *gen_Shr(ir_node *node)
1833 ir_node *left = get_Shr_left(node);
1834 ir_node *right = get_Shr_right(node);
1836 return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
1837 match_immediate | match_zero_ext);
1841 * Creates an ia32 Sar.
1843 * @return The created ia32 Shrs node
1845 static ir_node *gen_Shrs(ir_node *node)
1847 ir_node *left = get_Shrs_left(node);
1848 ir_node *right = get_Shrs_right(node);
1850 if (is_Const(right)) {
1851 ir_tarval *tv = get_Const_tarval(right);
1852 long val = get_tarval_long(tv);
1854 /* this is a sign extension */
1855 dbg_info *dbgi = get_irn_dbg_info(node);
1856 ir_node *block = be_transform_node(get_nodes_block(node));
1857 ir_node *new_op = be_transform_node(left);
1859 return create_sex_32_64(dbgi, block, new_op, node);
1863 /* 8 or 16 bit sign extension? */
1864 if (is_Const(right) && is_Shl(left)) {
1865 ir_node *shl_left = get_Shl_left(left);
1866 ir_node *shl_right = get_Shl_right(left);
1867 if (is_Const(shl_right)) {
1868 ir_tarval *tv1 = get_Const_tarval(right);
1869 ir_tarval *tv2 = get_Const_tarval(shl_right);
1870 if (tv1 == tv2 && tarval_is_long(tv1)) {
1871 long val = get_tarval_long(tv1);
1872 if (val == 16 || val == 24) {
1873 dbg_info *dbgi = get_irn_dbg_info(node);
1874 ir_node *block = get_nodes_block(node);
1884 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1893 return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
1894 match_immediate | match_upconv);
1900 * Creates an ia32 Rol.
1902 * @param op1 The first operator
1903 * @param op2 The second operator
1904 * @return The created ia32 RotL node
1906 static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
1908 return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
1914 * Creates an ia32 Ror.
1915 * NOTE: There is no RotR with immediate because this would always be a RotL
1916 * "imm-mode_size_bits" which can be pre-calculated.
1918 * @param op1 The first operator
1919 * @param op2 The second operator
1920 * @return The created ia32 RotR node
1922 static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
1924 return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
1930 * Creates an ia32 RotR or RotL (depending on the found pattern).
1932 * @return The created ia32 RotL or RotR node
1934 static ir_node *gen_Rotl(ir_node *node)
1936 ir_node *op1 = get_Rotl_left(node);
1937 ir_node *op2 = get_Rotl_right(node);
1939 if (is_Minus(op2)) {
1940 return gen_Ror(node, op1, get_Minus_op(op2));
1943 return gen_Rol(node, op1, op2);
1949 * Transforms a Minus node.
1951 * @return The created ia32 Minus node
1953 static ir_node *gen_Minus(ir_node *node)
1955 ir_node *op = get_Minus_op(node);
1956 ir_node *block = be_transform_node(get_nodes_block(node));
1957 dbg_info *dbgi = get_irn_dbg_info(node);
1958 ir_mode *mode = get_irn_mode(node);
1963 if (mode_is_float(mode)) {
1964 ir_node *new_op = be_transform_node(op);
1965 if (ia32_cg_config.use_sse2) {
1966 /* TODO: non-optimal... if we have many xXors, then we should
1967 * rather create a load for the const and use that instead of
1968 * several AM nodes... */
1969 ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
1971 new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
1972 noreg_GP, nomem, new_op, noreg_xmm);
1974 size = get_mode_size_bits(mode);
1975 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1977 set_ia32_am_sc(new_node, ent);
1978 set_ia32_op_type(new_node, ia32_AddrModeS);
1979 set_ia32_ls_mode(new_node, mode);
1981 new_node = new_bd_ia32_fchs(dbgi, block, new_op);
1984 new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
1987 SET_IA32_ORIG_NODE(new_node, node);
1993 * Transforms a Not node.
1995 * @return The created ia32 Not node
1997 static ir_node *gen_Not(ir_node *node)
1999 ir_node *op = get_Not_op(node);
2001 assert(get_irn_mode(node) != mode_b); /* should be lowered already */
2002 assert(!mode_is_float(get_irn_mode(node)));
2004 return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
2007 static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
2008 bool negate, ir_node *node)
2010 ir_node *new_block = be_transform_node(block);
2011 ir_mode *mode = get_irn_mode(op);
2012 ir_node *new_op = be_transform_node(op);
2017 assert(mode_is_float(mode));
2019 if (ia32_cg_config.use_sse2) {
2020 ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
2021 new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
2022 noreg_GP, nomem, new_op, noreg_fp);
2024 size = get_mode_size_bits(mode);
2025 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
2027 set_ia32_am_sc(new_node, ent);
2029 SET_IA32_ORIG_NODE(new_node, node);
2031 set_ia32_op_type(new_node, ia32_AddrModeS);
2032 set_ia32_ls_mode(new_node, mode);
2034 /* TODO, implement -Abs case */
2037 check_x87_floatmode(mode);
2038 new_node = new_bd_ia32_fabs(dbgi, new_block, new_op);
2039 SET_IA32_ORIG_NODE(new_node, node);
2041 new_node = new_bd_ia32_fchs(dbgi, new_block, new_node);
2042 SET_IA32_ORIG_NODE(new_node, node);
2050 * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
2052 static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n)
2054 dbg_info *dbgi = get_irn_dbg_info(cmp);
2055 ir_node *block = get_nodes_block(cmp);
2056 ir_node *new_block = be_transform_node(block);
2057 ir_node *op1 = be_transform_node(x);
2058 ir_node *op2 = be_transform_node(n);
2060 return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
2063 static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
2065 bool overflow_possible)
2067 if (mode_is_float(mode)) {
2069 case ir_relation_equal: return ia32_cc_float_equal;
2070 case ir_relation_less: return ia32_cc_float_below;
2071 case ir_relation_less_equal: return ia32_cc_float_below_equal;
2072 case ir_relation_greater: return ia32_cc_float_above;
2073 case ir_relation_greater_equal: return ia32_cc_float_above_equal;
2074 case ir_relation_less_greater: return ia32_cc_not_equal;
2075 case ir_relation_less_equal_greater: return ia32_cc_not_parity;
2076 case ir_relation_unordered: return ia32_cc_parity;
2077 case ir_relation_unordered_equal: return ia32_cc_equal;
2078 case ir_relation_unordered_less: return ia32_cc_float_unordered_below;
2079 case ir_relation_unordered_less_equal:
2080 return ia32_cc_float_unordered_below_equal;
2081 case ir_relation_unordered_greater:
2082 return ia32_cc_float_unordered_above;
2083 case ir_relation_unordered_greater_equal:
2084 return ia32_cc_float_unordered_above_equal;
2085 case ir_relation_unordered_less_greater:
2086 return ia32_cc_float_not_equal;
2087 case ir_relation_false:
2088 case ir_relation_true:
2089 /* should we introduce a jump always/jump never? */
2092 panic("Unexpected float pnc");
2093 } else if (mode_is_signed(mode)) {
2095 case ir_relation_unordered_equal:
2096 case ir_relation_equal: return ia32_cc_equal;
2097 case ir_relation_unordered_less:
2098 case ir_relation_less:
2099 return overflow_possible ? ia32_cc_less : ia32_cc_sign;
2100 case ir_relation_unordered_less_equal:
2101 case ir_relation_less_equal: return ia32_cc_less_equal;
2102 case ir_relation_unordered_greater:
2103 case ir_relation_greater: return ia32_cc_greater;
2104 case ir_relation_unordered_greater_equal:
2105 case ir_relation_greater_equal:
2106 return overflow_possible ? ia32_cc_greater_equal : ia32_cc_not_sign;
2107 case ir_relation_unordered_less_greater:
2108 case ir_relation_less_greater: return ia32_cc_not_equal;
2109 case ir_relation_less_equal_greater:
2110 case ir_relation_unordered:
2111 case ir_relation_false:
2112 case ir_relation_true:
2113 /* introduce jump always/jump never? */
2116 panic("Unexpected pnc");
2119 case ir_relation_unordered_equal:
2120 case ir_relation_equal: return ia32_cc_equal;
2121 case ir_relation_unordered_less:
2122 case ir_relation_less: return ia32_cc_below;
2123 case ir_relation_unordered_less_equal:
2124 case ir_relation_less_equal: return ia32_cc_below_equal;
2125 case ir_relation_unordered_greater:
2126 case ir_relation_greater: return ia32_cc_above;
2127 case ir_relation_unordered_greater_equal:
2128 case ir_relation_greater_equal: return ia32_cc_above_equal;
2129 case ir_relation_unordered_less_greater:
2130 case ir_relation_less_greater: return ia32_cc_not_equal;
2131 case ir_relation_less_equal_greater:
2132 case ir_relation_unordered:
2133 case ir_relation_false:
2134 case ir_relation_true:
2135 /* introduce jump always/jump never? */
2138 panic("Unexpected pnc");
2142 static ir_node *get_flags_node(ir_node *cmp, ia32_condition_code_t *cc_out)
2144 /* must have a Cmp as input */
2145 ir_relation relation = get_Cmp_relation(cmp);
2146 ir_node *l = get_Cmp_left(cmp);
2147 ir_node *r = get_Cmp_right(cmp);
2148 ir_mode *mode = get_irn_mode(l);
2149 bool overflow_possible;
2152 /* check for bit-test */
2153 if (ia32_cg_config.use_bt
2154 && (relation == ir_relation_equal
2155 || (mode_is_signed(mode) && relation == ir_relation_less_greater)
2156 || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
2158 ir_node *la = get_And_left(l);
2159 ir_node *ra = get_And_right(l);
2166 ir_node *c = get_Shl_left(la);
2167 if (is_Const_1(c) && is_Const_0(r)) {
2168 /* (1 << n) & ra) */
2169 ir_node *n = get_Shl_right(la);
2170 flags = gen_bt(cmp, ra, n);
2171 /* the bit is copied into the CF flag */
2172 if (relation & ir_relation_equal)
2173 *cc_out = ia32_cc_above_equal; /* test for CF=0 */
2175 *cc_out = ia32_cc_below; /* test for CF=1 */
2181 /* the middle-end tries to eliminate impossible relations, so a ptr <> 0
2182 * test becomes ptr > 0. But for x86 an equal comparison is preferable to
2183 * a >0 (we can sometimes eliminate the cmp in favor of flags produced by
2184 * a predecessor node). So add the < bit.
2185 * (Note that we do not want to produce <=> (which can happen for
2186 * unoptimized code), because no x86 flag can represent that */
2187 if (!(relation & ir_relation_equal) && relation & ir_relation_less_greater)
2188 relation |= get_negated_relation(ir_get_possible_cmp_relations(l, r)) & ir_relation_less_greater;
2190 overflow_possible = true;
2191 if (is_Const(r) && is_Const_null(r))
2192 overflow_possible = false;
2194 /* just do a normal transformation of the Cmp */
2195 *cc_out = relation_to_condition_code(relation, mode, overflow_possible);
2196 flags = be_transform_node(cmp);
2201 * Transforms a Load.
2203 * @return the created ia32 Load node
2205 static ir_node *gen_Load(ir_node *node)
2207 ir_node *old_block = get_nodes_block(node);
2208 ir_node *block = be_transform_node(old_block);
2209 ir_node *ptr = get_Load_ptr(node);
2210 ir_node *mem = get_Load_mem(node);
2211 ir_node *new_mem = be_transform_node(mem);
2212 dbg_info *dbgi = get_irn_dbg_info(node);
2213 ir_mode *mode = get_Load_mode(node);
2214 int throws_exception = ir_throws_exception(node);
2218 ia32_address_t addr;
2220 /* construct load address */
2221 memset(&addr, 0, sizeof(addr));
2222 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2229 base = be_transform_node(base);
2235 idx = be_transform_node(idx);
2238 if (mode_is_float(mode)) {
2239 if (ia32_cg_config.use_sse2) {
2240 new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
2243 new_node = new_bd_ia32_fld(dbgi, block, base, idx, new_mem,
2247 assert(mode != mode_b);
2249 /* create a conv node with address mode for smaller modes */
2250 if (get_mode_size_bits(mode) < 32) {
2251 new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx,
2252 new_mem, noreg_GP, mode);
2254 new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem);
2257 ir_set_throws_exception(new_node, throws_exception);
2259 set_irn_pinned(new_node, get_irn_pinned(node));
2260 set_ia32_op_type(new_node, ia32_AddrModeS);
2261 set_ia32_ls_mode(new_node, mode);
2262 set_address(new_node, &addr);
2264 if (get_irn_pinned(node) == op_pin_state_floats) {
2265 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
2266 && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
2267 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
2268 arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
2271 SET_IA32_ORIG_NODE(new_node, node);
2276 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
2277 ir_node *ptr, ir_node *other)
2284 /* we only use address mode if we're the only user of the load */
2285 if (get_irn_n_edges(node) > 1)
2288 load = get_Proj_pred(node);
2291 if (get_nodes_block(load) != block)
2294 /* store should have the same pointer as the load */
2295 if (get_Load_ptr(load) != ptr)
2298 /* don't do AM if other node inputs depend on the load (via mem-proj) */
2299 if (other != NULL &&
2300 get_nodes_block(other) == block &&
2301 heights_reachable_in_block(ia32_heights, other, load)) {
2305 if (ia32_prevents_AM(block, load, mem))
2307 /* Store should be attached to the load via mem */
2308 assert(heights_reachable_in_block(ia32_heights, mem, load));
2313 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
2314 ir_node *mem, ir_node *ptr, ir_mode *mode,
2315 construct_binop_dest_func *func,
2316 construct_binop_dest_func *func8bit,
2317 match_flags_t flags)
2319 ir_node *src_block = get_nodes_block(node);
2327 ia32_address_mode_t am;
2328 ia32_address_t *addr = &am.addr;
2329 memset(&am, 0, sizeof(am));
2331 assert(flags & match_immediate); /* there is no destam node without... */
2332 commutative = (flags & match_commutative) != 0;
2334 if (use_dest_am(src_block, op1, mem, ptr, op2)) {
2335 build_address(&am, op1, ia32_create_am_double_use);
2336 new_op = create_immediate_or_transform(op2);
2337 } else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
2338 build_address(&am, op2, ia32_create_am_double_use);
2339 new_op = create_immediate_or_transform(op1);
2344 if (addr->base == NULL)
2345 addr->base = noreg_GP;
2346 if (addr->index == NULL)
2347 addr->index = noreg_GP;
2348 if (addr->mem == NULL)
2351 dbgi = get_irn_dbg_info(node);
2352 block = be_transform_node(src_block);
2353 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2355 if (get_mode_size_bits(mode) == 8) {
2356 new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
2358 new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
2360 set_address(new_node, addr);
2361 set_ia32_op_type(new_node, ia32_AddrModeD);
2362 set_ia32_ls_mode(new_node, mode);
2363 SET_IA32_ORIG_NODE(new_node, node);
2365 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2366 mem_proj = be_transform_node(am.mem_proj);
2367 be_set_transformed_node(am.mem_proj, new_node);
2368 be_set_transformed_node(mem_proj, new_node);
2373 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
2374 ir_node *ptr, ir_mode *mode,
2375 construct_unop_dest_func *func)
2377 ir_node *src_block = get_nodes_block(node);
2383 ia32_address_mode_t am;
2384 ia32_address_t *addr = &am.addr;
2386 if (!use_dest_am(src_block, op, mem, ptr, NULL))
2389 memset(&am, 0, sizeof(am));
2390 build_address(&am, op, ia32_create_am_double_use);
2392 dbgi = get_irn_dbg_info(node);
2393 block = be_transform_node(src_block);
2394 new_mem = transform_AM_mem(block, am.am_node, mem, addr->mem);
2395 new_node = func(dbgi, block, addr->base, addr->index, new_mem);
2396 set_address(new_node, addr);
2397 set_ia32_op_type(new_node, ia32_AddrModeD);
2398 set_ia32_ls_mode(new_node, mode);
2399 SET_IA32_ORIG_NODE(new_node, node);
2401 be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
2402 mem_proj = be_transform_node(am.mem_proj);
2403 be_set_transformed_node(am.mem_proj, new_node);
2404 be_set_transformed_node(mem_proj, new_node);
2409 static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
2411 ir_mode *mode = get_irn_mode(node);
2412 ir_node *mux_true = get_Mux_true(node);
2413 ir_node *mux_false = get_Mux_false(node);
2421 ia32_condition_code_t cc;
2422 ia32_address_t addr;
2424 if (get_mode_size_bits(mode) != 8)
2427 if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
2429 } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
2435 cond = get_Mux_sel(node);
2436 flags = get_flags_node(cond, &cc);
2437 /* we can't handle the float special cases with SetM */
2438 if (cc & ia32_cc_additional_float_cases)
2441 cc = ia32_negate_condition_code(cc);
2443 build_address_ptr(&addr, ptr, mem);
2445 dbgi = get_irn_dbg_info(node);
2446 block = get_nodes_block(node);
2447 new_block = be_transform_node(block);
2448 new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
2449 addr.index, addr.mem, flags, cc);
2450 set_address(new_node, &addr);
2451 set_ia32_op_type(new_node, ia32_AddrModeD);
2452 set_ia32_ls_mode(new_node, mode);
2453 SET_IA32_ORIG_NODE(new_node, node);
2458 static ir_node *try_create_dest_am(ir_node *node)
2460 ir_node *val = get_Store_value(node);
2461 ir_node *mem = get_Store_mem(node);
2462 ir_node *ptr = get_Store_ptr(node);
2463 ir_mode *mode = get_irn_mode(val);
2464 unsigned bits = get_mode_size_bits(mode);
2469 /* handle only GP modes for now... */
2470 if (!ia32_mode_needs_gp_reg(mode))
2474 /* store must be the only user of the val node */
2475 if (get_irn_n_edges(val) > 1)
2477 /* skip pointless convs */
2479 ir_node *conv_op = get_Conv_op(val);
2480 ir_mode *pred_mode = get_irn_mode(conv_op);
2481 if (!ia32_mode_needs_gp_reg(pred_mode))
2483 if (pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
2491 /* value must be in the same block */
2492 if (get_nodes_block(node) != get_nodes_block(val))
2495 switch (get_irn_opcode(val)) {
2497 op1 = get_Add_left(val);
2498 op2 = get_Add_right(val);
2499 if (ia32_cg_config.use_incdec) {
2500 if (is_Const_1(op2)) {
2501 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
2503 } else if (is_Const_Minus_1(op2)) {
2504 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
2508 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2509 new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
2510 match_commutative | match_immediate);
2513 op1 = get_Sub_left(val);
2514 op2 = get_Sub_right(val);
2515 if (is_Const(op2)) {
2516 ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
2518 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2519 new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
2523 op1 = get_And_left(val);
2524 op2 = get_And_right(val);
2525 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2526 new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
2527 match_commutative | match_immediate);
2530 op1 = get_Or_left(val);
2531 op2 = get_Or_right(val);
2532 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2533 new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
2534 match_commutative | match_immediate);
2537 op1 = get_Eor_left(val);
2538 op2 = get_Eor_right(val);
2539 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2540 new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
2541 match_commutative | match_immediate);
2544 op1 = get_Shl_left(val);
2545 op2 = get_Shl_right(val);
2546 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2547 new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
2551 op1 = get_Shr_left(val);
2552 op2 = get_Shr_right(val);
2553 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2554 new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
2558 op1 = get_Shrs_left(val);
2559 op2 = get_Shrs_right(val);
2560 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2561 new_bd_ia32_SarMem, new_bd_ia32_SarMem,
2565 op1 = get_Rotl_left(val);
2566 op2 = get_Rotl_right(val);
2567 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
2568 new_bd_ia32_RolMem, new_bd_ia32_RolMem,
2571 /* TODO: match ROR patterns... */
2573 new_node = try_create_SetMem(val, ptr, mem);
2577 op1 = get_Minus_op(val);
2578 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
2581 /* should be lowered already */
2582 assert(mode != mode_b);
2583 op1 = get_Not_op(val);
2584 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
2590 if (new_node != NULL) {
2591 if (get_irn_pinned(new_node) != op_pin_state_pinned &&
2592 get_irn_pinned(node) == op_pin_state_pinned) {
2593 set_irn_pinned(new_node, op_pin_state_pinned);
2600 static bool possible_int_mode_for_fp(ir_mode *mode)
2604 if (!mode_is_signed(mode))
2606 size = get_mode_size_bits(mode);
2607 if (size != 16 && size != 32)
2612 static int is_float_to_int_conv(const ir_node *node)
2614 ir_mode *mode = get_irn_mode(node);
2618 if (!possible_int_mode_for_fp(mode))
2623 conv_op = get_Conv_op(node);
2624 conv_mode = get_irn_mode(conv_op);
2626 if (!mode_is_float(conv_mode))
2633 * Transform a Store(floatConst) into a sequence of
2636 * @return the created ia32 Store node
2638 static ir_node *gen_float_const_Store(ir_node *node, ir_node *cns)
2640 ir_mode *mode = get_irn_mode(cns);
2641 unsigned size = get_mode_size_bytes(mode);
2642 ir_tarval *tv = get_Const_tarval(cns);
2643 ir_node *block = get_nodes_block(node);
2644 ir_node *new_block = be_transform_node(block);
2645 ir_node *ptr = get_Store_ptr(node);
2646 ir_node *mem = get_Store_mem(node);
2647 dbg_info *dbgi = get_irn_dbg_info(node);
2650 int throws_exception = ir_throws_exception(node);
2652 ia32_address_t addr;
2654 build_address_ptr(&addr, ptr, mem);
2661 val= get_tarval_sub_bits(tv, ofs) |
2662 (get_tarval_sub_bits(tv, ofs + 1) << 8) |
2663 (get_tarval_sub_bits(tv, ofs + 2) << 16) |
2664 (get_tarval_sub_bits(tv, ofs + 3) << 24);
2667 } else if (size >= 2) {
2668 val= get_tarval_sub_bits(tv, ofs) |
2669 (get_tarval_sub_bits(tv, ofs + 1) << 8);
2673 panic("invalid size of Store float to mem (%+F)", node);
2675 ir_graph *const irg = get_Block_irg(new_block);
2676 ir_node *const imm = ia32_create_Immediate(irg, NULL, 0, val);
2678 ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2679 addr.index, addr.mem, imm);
2680 ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M);
2682 ir_set_throws_exception(new_node, throws_exception);
2683 set_irn_pinned(new_node, get_irn_pinned(node));
2684 set_ia32_op_type(new_node, ia32_AddrModeD);
2685 set_ia32_ls_mode(new_node, mode);
2686 set_address(new_node, &addr);
2687 SET_IA32_ORIG_NODE(new_node, node);
2694 addr.offset += delta;
2695 } while (size != 0);
2698 return new_rd_Sync(dbgi, new_block, i, ins);
2700 return get_Proj_pred(ins[0]);
2705 * Generate a vfist or vfisttp instruction.
2707 static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base,
2708 ir_node *index, ir_node *mem, ir_node *val)
2710 if (ia32_cg_config.use_fisttp) {
2711 /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
2712 if other users exists */
2713 ir_node *vfisttp = new_bd_ia32_fisttp(dbgi, block, base, index, mem, val);
2714 ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_fisttp_res);
2715 be_new_Keep(block, 1, &value);
2719 ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
2722 ir_node *vfist = new_bd_ia32_fist(dbgi, block, base, index, mem, val, trunc_mode);
2728 * Transforms a general (no special case) Store.
2730 * @return the created ia32 Store node
2732 static ir_node *gen_general_Store(ir_node *node)
2734 ir_node *val = get_Store_value(node);
2735 ir_mode *mode = get_irn_mode(val);
2736 ir_node *block = get_nodes_block(node);
2737 ir_node *new_block = be_transform_node(block);
2738 ir_node *ptr = get_Store_ptr(node);
2739 ir_node *mem = get_Store_mem(node);
2740 dbg_info *dbgi = get_irn_dbg_info(node);
2741 int throws_exception = ir_throws_exception(node);
2744 ia32_address_t addr;
2746 /* check for destination address mode */
2747 new_node = try_create_dest_am(node);
2748 if (new_node != NULL)
2751 /* construct store address */
2752 memset(&addr, 0, sizeof(addr));
2753 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
2755 if (addr.base == NULL) {
2756 addr.base = noreg_GP;
2758 addr.base = be_transform_node(addr.base);
2761 if (addr.index == NULL) {
2762 addr.index = noreg_GP;
2764 addr.index = be_transform_node(addr.index);
2766 addr.mem = be_transform_node(mem);
2768 if (mode_is_float(mode)) {
2769 if (ia32_cg_config.use_sse2) {
2770 new_val = be_transform_node(val);
2771 new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
2772 addr.index, addr.mem, new_val);
2774 val = ia32_skip_float_downconv(val);
2775 new_val = be_transform_node(val);
2776 new_node = new_bd_ia32_fst(dbgi, new_block, addr.base,
2777 addr.index, addr.mem, new_val, mode);
2779 } else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
2780 val = get_Conv_op(val);
2781 new_val = be_transform_node(val);
2782 new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
2784 unsigned dest_bits = get_mode_size_bits(mode);
2785 while (is_downconv(val)
2786 && get_mode_size_bits(get_irn_mode(val)) >= dest_bits) {
2787 val = get_Conv_op(val);
2789 new_val = create_immediate_or_transform(val);
2790 assert(mode != mode_b);
2792 if (dest_bits == 8) {
2793 new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
2794 addr.index, addr.mem, new_val);
2796 new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
2797 addr.index, addr.mem, new_val);
2800 ir_set_throws_exception(new_node, throws_exception);
2802 set_irn_pinned(new_node, get_irn_pinned(node));
2803 set_ia32_op_type(new_node, ia32_AddrModeD);
2804 set_ia32_ls_mode(new_node, mode);
2806 set_address(new_node, &addr);
2807 SET_IA32_ORIG_NODE(new_node, node);
2813 * Transforms a Store.
2815 * @return the created ia32 Store node
2817 static ir_node *gen_Store(ir_node *node)
2819 ir_node *val = get_Store_value(node);
2820 ir_mode *mode = get_irn_mode(val);
2822 if (mode_is_float(mode) && is_Const(val)) {
2823 /* We can transform every floating const store
2824 into a sequence of integer stores.
2825 If the constant is already in a register,
2826 it would be better to use it, but we don't
2827 have this information here. */
2828 return gen_float_const_Store(node, val);
2830 return gen_general_Store(node);
2834 * Transforms a Switch.
2836 * @return the created ia32 SwitchJmp node
2838 static ir_node *gen_Switch(ir_node *node)
2840 dbg_info *dbgi = get_irn_dbg_info(node);
2841 ir_graph *irg = get_irn_irg(node);
2842 ir_node *block = be_transform_node(get_nodes_block(node));
2843 ir_node *sel = get_Switch_selector(node);
2844 ir_node *new_sel = be_transform_node(sel);
2845 ir_mode *sel_mode = get_irn_mode(sel);
2846 const ir_switch_table *table = get_Switch_table(node);
2847 unsigned n_outs = get_Switch_n_outs(node);
2851 assert(get_mode_size_bits(sel_mode) <= 32);
2852 assert(!mode_is_float(sel_mode));
2853 sel = ia32_skip_sameconv(sel);
2854 if (get_mode_size_bits(sel_mode) < 32)
2855 new_sel = transform_upconv(sel, node);
2857 entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
2858 set_entity_visibility(entity, ir_visibility_private);
2859 add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
2861 table = ir_switch_table_duplicate(irg, table);
2863 new_node = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, n_outs, table);
2864 set_ia32_am_scale(new_node, 2);
2865 set_ia32_am_sc(new_node, entity);
2866 set_ia32_op_type(new_node, ia32_AddrModeS);
2867 set_ia32_ls_mode(new_node, mode_Iu);
2868 SET_IA32_ORIG_NODE(new_node, node);
2869 // FIXME This seems wrong. GCC uses PIC for switch on OS X.
2870 get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true;
2876 * Transform a Cond node.
2878 static ir_node *gen_Cond(ir_node *node)
2880 ir_node *block = get_nodes_block(node);
2881 ir_node *new_block = be_transform_node(block);
2882 dbg_info *dbgi = get_irn_dbg_info(node);
2883 ir_node *sel = get_Cond_selector(node);
2884 ir_node *flags = NULL;
2886 ia32_condition_code_t cc;
2888 /* we get flags from a Cmp */
2889 flags = get_flags_node(sel, &cc);
2891 new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc);
2892 SET_IA32_ORIG_NODE(new_node, node);
2898 * Transform a be_Copy.
2900 static ir_node *gen_be_Copy(ir_node *node)
2902 ir_node *new_node = be_duplicate_node(node);
2903 ir_mode *mode = get_irn_mode(new_node);
2905 if (ia32_mode_needs_gp_reg(mode)) {
2906 set_irn_mode(new_node, mode_Iu);
2912 static ir_node *create_Fucom(ir_node *node)
2914 dbg_info *dbgi = get_irn_dbg_info(node);
2915 ir_node *block = get_nodes_block(node);
2916 ir_node *new_block = be_transform_node(block);
2917 ir_node *left = get_Cmp_left(node);
2918 ir_node *new_left = be_transform_node(left);
2919 ir_node *right = get_Cmp_right(node);
2920 ir_mode *cmp_mode = get_irn_mode(left);
2923 check_x87_floatmode(cmp_mode);
2925 if (ia32_cg_config.use_fucomi) {
2926 new_right = be_transform_node(right);
2927 new_node = new_bd_ia32_Fucomi(dbgi, new_block, new_left,
2929 set_ia32_commutative(new_node);
2930 SET_IA32_ORIG_NODE(new_node, node);
2932 if (is_Const_0(right)) {
2933 new_node = new_bd_ia32_FtstFnstsw(dbgi, new_block, new_left, 0);
2935 new_right = be_transform_node(right);
2936 new_node = new_bd_ia32_FucomFnstsw(dbgi, new_block, new_left, new_right, 0);
2937 set_ia32_commutative(new_node);
2940 SET_IA32_ORIG_NODE(new_node, node);
2942 new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
2943 SET_IA32_ORIG_NODE(new_node, node);
2949 static ir_node *create_Ucomi(ir_node *node)
2951 dbg_info *dbgi = get_irn_dbg_info(node);
2952 ir_node *src_block = get_nodes_block(node);
2953 ir_node *new_block = be_transform_node(src_block);
2954 ir_node *left = get_Cmp_left(node);
2955 ir_node *right = get_Cmp_right(node);
2957 ia32_address_mode_t am;
2958 ia32_address_t *addr = &am.addr;
2960 match_arguments(&am, src_block, left, right, NULL,
2961 match_commutative | match_am);
2963 new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
2964 addr->mem, am.new_op1, am.new_op2,
2966 set_am_attributes(new_node, &am);
2968 SET_IA32_ORIG_NODE(new_node, node);
2970 new_node = fix_mem_proj(new_node, &am);
2975 static bool ia32_mux_upper_bits_clean(const ir_node *node, ir_mode *mode)
2977 ir_node *mux_true = get_Mux_true(node);
2978 ir_node *mux_false = get_Mux_false(node);
2979 ir_mode *mux_mode = get_irn_mode(node);
2980 /* mux nodes which get transformed to the set instruction are not clean */
2981 if (is_Const(mux_true) && is_Const(mux_false)
2982 && get_mode_size_bits(mux_mode) == 8) {
2985 return be_upper_bits_clean(mux_true, mode)
2986 && be_upper_bits_clean(mux_false, mode);
2990 * Generate code for a Cmp.
2992 static ir_node *gen_Cmp(ir_node *node)
2994 dbg_info *dbgi = get_irn_dbg_info(node);
2995 ir_node *block = get_nodes_block(node);
2996 ir_node *new_block = be_transform_node(block);
2997 ir_node *left = get_Cmp_left(node);
2998 ir_node *right = get_Cmp_right(node);
2999 ir_mode *cmp_mode = get_irn_mode(left);
3001 ia32_address_mode_t am;
3002 ia32_address_t *addr = &am.addr;
3004 if (mode_is_float(cmp_mode)) {
3005 if (ia32_cg_config.use_sse2) {
3006 return create_Ucomi(node);
3008 return create_Fucom(node);
3012 assert(ia32_mode_needs_gp_reg(cmp_mode));
3014 /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
3015 if (is_Const_0(right) &&
3017 get_irn_n_edges(left) == 1) {
3018 /* Test(and_left, and_right) */
3019 ir_node *and_left = get_And_left(left);
3020 ir_node *and_right = get_And_right(left);
3022 /* matze: code here used mode instead of cmd_mode, I think it is always
3023 * the same as cmp_mode, but I leave this here to see if this is really
3026 assert(get_irn_mode(and_left) == cmp_mode);
3028 match_arguments(&am, block, and_left, and_right, NULL,
3030 match_am | match_8bit_am | match_16bit_am |
3031 match_am_and_immediates | match_immediate);
3033 /* use 32bit compare mode if possible since the opcode is smaller */
3034 if (am.op_type == ia32_Normal &&
3035 be_upper_bits_clean(and_left, cmp_mode) &&
3036 be_upper_bits_clean(and_right, cmp_mode)) {
3037 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3040 if (get_mode_size_bits(cmp_mode) == 8) {
3041 new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
3042 addr->index, addr->mem,
3043 am.new_op1, am.new_op2,
3046 new_node = new_bd_ia32_Test(dbgi, new_block, addr->base,
3047 addr->index, addr->mem, am.new_op1,
3048 am.new_op2, am.ins_permuted);
3051 /* Cmp(left, right) */
3052 match_arguments(&am, block, left, right, NULL,
3054 match_am | match_8bit_am | match_16bit_am |
3055 match_am_and_immediates | match_immediate);
3056 /* use 32bit compare mode if possible since the opcode is smaller */
3057 if (am.op_type == ia32_Normal &&
3058 be_upper_bits_clean(left, cmp_mode) &&
3059 be_upper_bits_clean(right, cmp_mode)) {
3060 cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
3063 if (get_mode_size_bits(cmp_mode) == 8) {
3064 new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
3065 addr->index, addr->mem, am.new_op1,
3066 am.new_op2, am.ins_permuted);
3068 new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
3069 addr->mem, am.new_op1, am.new_op2,
3073 set_am_attributes(new_node, &am);
3074 set_ia32_ls_mode(new_node, cmp_mode);
3076 SET_IA32_ORIG_NODE(new_node, node);
3078 new_node = fix_mem_proj(new_node, &am);
3083 static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
3084 ia32_condition_code_t cc)
3086 dbg_info *dbgi = get_irn_dbg_info(node);
3087 ir_node *block = get_nodes_block(node);
3088 ir_node *new_block = be_transform_node(block);
3089 ir_node *val_true = get_Mux_true(node);
3090 ir_node *val_false = get_Mux_false(node);
3092 ia32_address_mode_t am;
3093 ia32_address_t *addr;
3095 assert(ia32_cg_config.use_cmov);
3096 assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
3100 match_arguments(&am, block, val_false, val_true, flags,
3101 match_commutative | match_am | match_16bit_am | match_mode_neutral);
3103 if (am.ins_permuted)
3104 cc = ia32_negate_condition_code(cc);
3106 new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
3107 addr->mem, am.new_op1, am.new_op2, new_flags,
3109 set_am_attributes(new_node, &am);
3111 SET_IA32_ORIG_NODE(new_node, node);
3113 new_node = fix_mem_proj(new_node, &am);
3119 * Creates a ia32 Setcc instruction.
3121 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
3122 ir_node *flags, ia32_condition_code_t cc,
3125 ir_mode *mode = get_irn_mode(orig_node);
3128 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc);
3129 SET_IA32_ORIG_NODE(new_node, orig_node);
3131 /* we might need to conv the result up */
3132 if (get_mode_size_bits(mode) > 8) {
3133 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
3134 nomem, new_node, mode_Bu);
3135 SET_IA32_ORIG_NODE(new_node, orig_node);
3142 * Create instruction for an unsigned Difference or Zero.
3144 static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
3146 ir_mode *mode = get_irn_mode(psi);
3156 new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
3157 match_mode_neutral | match_am | match_immediate | match_two_users);
3159 block = get_nodes_block(new_node);
3161 if (is_Proj(new_node)) {
3162 sub = get_Proj_pred(new_node);
3165 set_irn_mode(sub, mode_T);
3166 new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
3168 assert(is_ia32_Sub(sub));
3169 eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
3171 dbgi = get_irn_dbg_info(psi);
3172 sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
3173 set_ia32_ls_mode(sbb, mode_Iu);
3174 notn = new_bd_ia32_Not(dbgi, block, sbb);
3176 new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
3177 set_ia32_ls_mode(new_node, mode_Iu);
3178 set_ia32_commutative(new_node);
3183 * Create an const array of two float consts.
3185 * @param c0 the first constant
3186 * @param c1 the second constant
3187 * @param new_mode IN/OUT for the mode of the constants, if NULL
3188 * smallest possible mode will be used
3190 static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
3193 ir_mode *mode = *new_mode;
3195 ir_initializer_t *initializer;
3196 ir_tarval *tv0 = get_Const_tarval(c0);
3197 ir_tarval *tv1 = get_Const_tarval(c1);
3200 /* detect the best mode for the constants */
3201 mode = get_tarval_mode(tv0);
3203 if (mode != mode_F) {
3204 if (tarval_ieee754_can_conv_lossless(tv0, mode_F) &&
3205 tarval_ieee754_can_conv_lossless(tv1, mode_F)) {
3207 tv0 = tarval_convert_to(tv0, mode);
3208 tv1 = tarval_convert_to(tv1, mode);
3209 } else if (mode != mode_D) {
3210 if (tarval_ieee754_can_conv_lossless(tv0, mode_D) &&
3211 tarval_ieee754_can_conv_lossless(tv1, mode_D)) {
3213 tv0 = tarval_convert_to(tv0, mode);
3214 tv1 = tarval_convert_to(tv1, mode);
3221 tp = ia32_get_prim_type(mode);
3222 tp = ia32_create_float_array(tp);
3224 ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
3226 set_entity_ld_ident(ent, get_entity_ident(ent));
3227 set_entity_visibility(ent, ir_visibility_private);
3228 add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
3230 initializer = create_initializer_compound(2);
3232 set_initializer_compound_value(initializer, 0, create_initializer_tarval(tv0));
3233 set_initializer_compound_value(initializer, 1, create_initializer_tarval(tv1));
3235 set_entity_initializer(ent, initializer);
3242 * Possible transformations for creating a Setcc.
3244 enum setcc_transform_insn {
3256 typedef struct setcc_transform {
3258 ia32_condition_code_t cc;
3260 enum setcc_transform_insn transform;
3264 } setcc_transform_t;
3267 * Setcc can only handle 0 and 1 result.
3268 * Find a transformation that creates 0 and 1 from
3271 static void find_const_transform(ia32_condition_code_t cc,
3272 ir_tarval *t, ir_tarval *f,
3273 setcc_transform_t *res)
3279 if (tarval_is_null(t)) {
3283 cc = ia32_negate_condition_code(cc);
3284 } else if (tarval_cmp(t, f) == ir_relation_less) {
3285 // now, t is the bigger one
3289 cc = ia32_negate_condition_code(cc);
3293 if (! tarval_is_null(f)) {
3294 ir_tarval *t_sub = tarval_sub(t, f, NULL);
3297 res->steps[step].transform = SETCC_TR_ADD;
3299 if (t == tarval_bad)
3300 panic("constant subtract failed");
3301 if (! tarval_is_long(f))
3302 panic("tarval is not long");
3304 res->steps[step].val = get_tarval_long(f);
3306 f = tarval_sub(f, f, NULL);
3307 assert(tarval_is_null(f));
3310 if (tarval_is_one(t)) {
3311 res->steps[step].transform = SETCC_TR_SET;
3312 res->num_steps = ++step;
3316 if (tarval_is_minus_one(t)) {
3317 res->steps[step].transform = SETCC_TR_NEG;
3319 res->steps[step].transform = SETCC_TR_SET;
3320 res->num_steps = ++step;
3323 if (tarval_is_long(t)) {
3324 long v = get_tarval_long(t);
3326 res->steps[step].val = 0;
3329 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3331 res->steps[step].transform = SETCC_TR_LEAxx;
3332 res->steps[step].scale = 3; /* (a << 3) + a */
3335 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3337 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3338 res->steps[step].scale = 3; /* (a << 3) */
3341 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3343 res->steps[step].transform = SETCC_TR_LEAxx;
3344 res->steps[step].scale = 2; /* (a << 2) + a */
3347 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3349 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3350 res->steps[step].scale = 2; /* (a << 2) */
3353 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3355 res->steps[step].transform = SETCC_TR_LEAxx;
3356 res->steps[step].scale = 1; /* (a << 1) + a */
3359 if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
3361 res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
3362 res->steps[step].scale = 1; /* (a << 1) */
3365 res->num_steps = step;
3368 if (! tarval_is_single_bit(t)) {
3369 res->steps[step].transform = SETCC_TR_AND;
3370 res->steps[step].val = v;
3372 res->steps[step].transform = SETCC_TR_NEG;
3374 int val = get_tarval_lowest_bit(t);
3377 res->steps[step].transform = SETCC_TR_SHL;
3378 res->steps[step].scale = val;
3382 res->steps[step].transform = SETCC_TR_SET;
3383 res->num_steps = ++step;
3386 panic("tarval is not long");
3390 * Transforms a Mux node into some code sequence.
3392 * @return The transformed node.
3394 static ir_node *gen_Mux(ir_node *node)
3396 dbg_info *dbgi = get_irn_dbg_info(node);
3397 ir_node *block = get_nodes_block(node);
3398 ir_node *new_block = be_transform_node(block);
3399 ir_node *mux_true = get_Mux_true(node);
3400 ir_node *mux_false = get_Mux_false(node);
3401 ir_node *sel = get_Mux_sel(node);
3402 ir_mode *mode = get_irn_mode(node);
3406 ia32_condition_code_t cc;
3408 assert(get_irn_mode(sel) == mode_b);
3410 is_abs = ir_mux_is_abs(sel, mux_false, mux_true);
3412 if (ia32_mode_needs_gp_reg(mode)) {
3413 ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n",
3416 ir_node *op = ir_get_abs_op(sel, mux_false, mux_true);
3417 return create_float_abs(dbgi, block, op, is_abs < 0, node);
3421 /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
3422 if (mode_is_float(mode)) {
3423 ir_node *cmp_left = get_Cmp_left(sel);
3424 ir_node *cmp_right = get_Cmp_right(sel);
3425 ir_relation relation = get_Cmp_relation(sel);
3427 if (ia32_cg_config.use_sse2) {
3428 if (relation == ir_relation_less || relation == ir_relation_less_equal) {
3429 if (cmp_left == mux_true && cmp_right == mux_false) {
3430 /* Mux(a <= b, a, b) => MIN */
3431 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3432 match_commutative | match_am | match_two_users);
3433 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3434 /* Mux(a <= b, b, a) => MAX */
3435 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3436 match_commutative | match_am | match_two_users);
3438 } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
3439 if (cmp_left == mux_true && cmp_right == mux_false) {
3440 /* Mux(a >= b, a, b) => MAX */
3441 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
3442 match_commutative | match_am | match_two_users);
3443 } else if (cmp_left == mux_false && cmp_right == mux_true) {
3444 /* Mux(a >= b, b, a) => MIN */
3445 return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
3446 match_commutative | match_am | match_two_users);
3451 if (is_Const(mux_true) && is_Const(mux_false)) {
3452 ia32_address_mode_t am;
3457 flags = get_flags_node(sel, &cc);
3458 new_node = create_set_32bit(dbgi, new_block, flags, cc, node);
3460 if (ia32_cg_config.use_sse2) {
3461 /* cannot load from different mode on SSE */
3464 /* x87 can load any mode */
3468 am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
3470 if (new_mode == mode_F) {
3472 } else if (new_mode == mode_D) {
3474 } else if (new_mode == ia32_mode_E) {
3475 /* arg, shift 16 NOT supported */
3477 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3479 panic("Unsupported constant size");
3482 am.ls_mode = new_mode;
3483 am.addr.base = get_symconst_base();
3484 am.addr.index = new_node;
3485 am.addr.mem = nomem;
3487 am.addr.scale = scale;
3488 am.addr.use_frame = 0;
3489 am.addr.tls_segment = false;
3490 am.addr.frame_entity = NULL;
3491 am.addr.symconst_sign = 0;
3492 am.mem_proj = am.addr.mem;
3493 am.op_type = ia32_AddrModeS;
3496 am.pinned = op_pin_state_floats;
3498 am.ins_permuted = false;
3500 if (ia32_cg_config.use_sse2)
3501 load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3503 load = new_bd_ia32_fld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
3504 set_am_attributes(load, &am);
3506 return new_rd_Proj(NULL, load, mode_fp, pn_ia32_res);
3508 panic("cannot transform floating point Mux");
3511 assert(ia32_mode_needs_gp_reg(mode));
3514 ir_node *cmp_left = get_Cmp_left(sel);
3515 ir_node *cmp_right = get_Cmp_right(sel);
3516 ir_relation relation = get_Cmp_relation(sel);
3517 ir_node *val_true = mux_true;
3518 ir_node *val_false = mux_false;
3520 if (is_Const(val_true) && is_Const_null(val_true)) {
3521 ir_node *tmp = val_false;
3522 val_false = val_true;
3524 relation = get_negated_relation(relation);
3526 if (is_Const_0(val_false) && is_Sub(val_true)) {
3527 if ((relation & ir_relation_greater)
3528 && get_Sub_left(val_true) == cmp_left
3529 && get_Sub_right(val_true) == cmp_right) {
3530 return create_doz(node, cmp_left, cmp_right);
3532 if ((relation & ir_relation_less)
3533 && get_Sub_left(val_true) == cmp_right
3534 && get_Sub_right(val_true) == cmp_left) {
3535 return create_doz(node, cmp_right, cmp_left);
3540 flags = get_flags_node(sel, &cc);
3542 if (is_Const(mux_true) && is_Const(mux_false)) {
3543 /* both are const, good */
3544 ir_tarval *tv_true = get_Const_tarval(mux_true);
3545 ir_tarval *tv_false = get_Const_tarval(mux_false);
3546 setcc_transform_t res;
3549 find_const_transform(cc, tv_true, tv_false, &res);
3551 for (step = (int)res.num_steps - 1; step >= 0; --step) {
3554 switch (res.steps[step].transform) {
3556 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP);
3557 add_ia32_am_offs_int(new_node, res.steps[step].val);
3559 case SETCC_TR_ADDxx:
3560 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3563 new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
3564 set_ia32_am_scale(new_node, res.steps[step].scale);
3565 set_ia32_am_offs_int(new_node, res.steps[step].val);
3567 case SETCC_TR_LEAxx:
3568 new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
3569 set_ia32_am_scale(new_node, res.steps[step].scale);
3570 set_ia32_am_offs_int(new_node, res.steps[step].val);
3573 imm = ia32_immediate_from_long(res.steps[step].scale);
3574 new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
3577 new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
3580 new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
3583 imm = ia32_immediate_from_long(res.steps[step].val);
3584 new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
3587 new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
3590 panic("unknown setcc transform");
3594 new_node = create_CMov(node, sel, flags, cc);
3601 * Create a conversion from x87 state register to general purpose.
3603 static ir_node *gen_x87_fp_to_gp(ir_node *node)
3605 ir_node *block = be_transform_node(get_nodes_block(node));
3606 ir_node *op = get_Conv_op(node);
3607 ir_node *new_op = be_transform_node(op);
3608 ir_graph *irg = current_ir_graph;
3609 dbg_info *dbgi = get_irn_dbg_info(node);
3610 ir_mode *mode = get_irn_mode(node);
3611 ir_node *frame = get_irg_frame(irg);
3612 ir_node *fist, *load, *mem;
3614 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op);
3615 set_irn_pinned(fist, op_pin_state_floats);
3616 set_ia32_use_frame(fist);
3617 set_ia32_op_type(fist, ia32_AddrModeD);
3619 assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
3620 mem = new_r_Proj(fist, mode_M, pn_ia32_fist_M);
3622 assert(get_mode_size_bits(mode) <= 32);
3623 /* exception we can only store signed 32 bit integers, so for unsigned
3624 we store a 64bit (signed) integer and load the lower bits */
3625 if (get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
3626 set_ia32_ls_mode(fist, mode_Ls);
3628 set_ia32_ls_mode(fist, mode_Is);
3630 SET_IA32_ORIG_NODE(fist, node);
3633 load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg_GP, mem);
3635 set_irn_pinned(load, op_pin_state_floats);
3636 set_ia32_use_frame(load);
3637 set_ia32_op_type(load, ia32_AddrModeS);
3638 set_ia32_ls_mode(load, mode_Is);
3639 if (get_ia32_ls_mode(fist) == mode_Ls) {
3640 ia32_attr_t *attr = get_ia32_attr(load);
3641 attr->data.need_64bit_stackent = 1;
3643 ia32_attr_t *attr = get_ia32_attr(load);
3644 attr->data.need_32bit_stackent = 1;
3646 SET_IA32_ORIG_NODE(load, node);
3648 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
3652 * Creates a x87 Conv by placing a Store and a Load
3654 static ir_node *gen_x87_conv(ir_mode *tgt_mode, ir_node *node)
3656 ir_node *block = get_nodes_block(node);
3657 ir_graph *irg = get_Block_irg(block);
3658 dbg_info *dbgi = get_irn_dbg_info(node);
3659 ir_node *frame = get_irg_frame(irg);
3661 ir_node *store, *load;
3664 store = new_bd_ia32_fst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
3665 set_ia32_use_frame(store);
3666 set_ia32_op_type(store, ia32_AddrModeD);
3667 SET_IA32_ORIG_NODE(store, node);
3669 store_mem = new_r_Proj(store, mode_M, pn_ia32_fst_M);
3671 load = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
3672 set_ia32_use_frame(load);
3673 set_ia32_op_type(load, ia32_AddrModeS);
3674 SET_IA32_ORIG_NODE(load, node);
3676 new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_fld_res);
3680 static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
3681 ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
3683 ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
3685 func = get_mode_size_bits(mode) == 8 ?
3686 new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
3687 return func(dbgi, block, base, index, mem, val, mode);
3691 * Create a conversion from general purpose to x87 register
3693 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode)
3695 ir_node *src_block = get_nodes_block(node);
3696 ir_node *block = be_transform_node(src_block);
3697 ir_graph *irg = get_Block_irg(block);
3698 dbg_info *dbgi = get_irn_dbg_info(node);
3699 ir_node *op = get_Conv_op(node);
3700 ir_node *new_op = NULL;
3702 ir_mode *store_mode;
3708 /* fild can use source AM if the operand is a signed 16bit or 32bit integer */
3709 if (possible_int_mode_for_fp(src_mode)) {
3710 ia32_address_mode_t am;
3712 match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am | match_upconv);
3713 if (am.op_type == ia32_AddrModeS) {
3714 ia32_address_t *addr = &am.addr;
3716 fild = new_bd_ia32_fild(dbgi, block, addr->base, addr->index, addr->mem);
3717 new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
3719 set_am_attributes(fild, &am);
3720 SET_IA32_ORIG_NODE(fild, node);
3722 fix_mem_proj(fild, &am);
3727 if (new_op == NULL) {
3728 new_op = be_transform_node(op);
3731 mode = get_irn_mode(op);
3733 /* first convert to 32 bit signed if necessary */
3734 if (get_mode_size_bits(src_mode) < 32) {
3735 if (!be_upper_bits_clean(op, src_mode)) {
3736 new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
3737 SET_IA32_ORIG_NODE(new_op, node);
3742 assert(get_mode_size_bits(mode) == 32);
3745 store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op);
3747 set_ia32_use_frame(store);
3748 set_ia32_op_type(store, ia32_AddrModeD);
3749 set_ia32_ls_mode(store, mode_Iu);
3751 store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
3753 /* exception for 32bit unsigned, do a 64bit spill+load */
3754 if (!mode_is_signed(mode)) {
3757 ir_node *zero_const = ia32_create_Immediate(irg, NULL, 0, 0);
3759 ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
3760 noreg_GP, nomem, zero_const);
3761 ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M);
3763 set_ia32_use_frame(zero_store);
3764 set_ia32_op_type(zero_store, ia32_AddrModeD);
3765 add_ia32_am_offs_int(zero_store, 4);
3766 set_ia32_ls_mode(zero_store, mode_Iu);
3768 in[0] = zero_store_mem;
3771 store_mem = new_rd_Sync(dbgi, block, 2, in);
3772 store_mode = mode_Ls;
3774 store_mode = mode_Is;
3778 fild = new_bd_ia32_fild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
3780 set_ia32_use_frame(fild);
3781 set_ia32_op_type(fild, ia32_AddrModeS);
3782 set_ia32_ls_mode(fild, store_mode);
3784 new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
3790 * Create a conversion from one integer mode into another one
3792 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
3793 dbg_info *dbgi, ir_node *block, ir_node *op,
3796 ir_node *new_block = be_transform_node(block);
3798 ia32_address_mode_t am;
3799 ia32_address_t *addr = &am.addr;
3802 assert(get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode));
3804 #ifdef DEBUG_libfirm
3806 ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
3811 if (be_upper_bits_clean(op, src_mode)) {
3812 return be_transform_node(op);
3815 match_arguments(&am, block, NULL, op, NULL,
3816 match_am | match_8bit_am | match_16bit_am);
3818 new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
3819 addr->mem, am.new_op2, src_mode);
3820 set_am_attributes(new_node, &am);
3821 /* match_arguments assume that out-mode = in-mode, this isn't true here
3823 set_ia32_ls_mode(new_node, src_mode);
3824 SET_IA32_ORIG_NODE(new_node, node);
3825 new_node = fix_mem_proj(new_node, &am);
3830 * Transforms a Conv node.
3832 * @return The created ia32 Conv node
3834 static ir_node *gen_Conv(ir_node *node)
3836 ir_node *block = get_nodes_block(node);
3837 ir_node *new_block = be_transform_node(block);
3838 ir_node *op = get_Conv_op(node);
3839 ir_node *new_op = NULL;
3840 dbg_info *dbgi = get_irn_dbg_info(node);
3841 ir_mode *src_mode = get_irn_mode(op);
3842 ir_mode *tgt_mode = get_irn_mode(node);
3843 int src_bits = get_mode_size_bits(src_mode);
3844 int tgt_bits = get_mode_size_bits(tgt_mode);
3845 ir_node *res = NULL;
3847 assert(!mode_is_int(src_mode) || src_bits <= 32);
3848 assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
3850 /* modeB -> X should already be lowered by the lower_mode_b pass */
3851 if (src_mode == mode_b) {
3852 panic("ConvB not lowered %+F", node);
3855 if (src_mode == tgt_mode) {
3856 /* this should be optimized already, but who knows... */
3857 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
3858 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
3859 return be_transform_node(op);
3862 if (mode_is_float(src_mode)) {
3863 new_op = be_transform_node(op);
3864 /* we convert from float ... */
3865 if (mode_is_float(tgt_mode)) {
3867 if (ia32_cg_config.use_sse2) {
3868 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
3869 res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg_GP, noreg_GP,
3871 set_ia32_ls_mode(res, tgt_mode);
3873 if (src_bits < tgt_bits) {
3874 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
3877 res = gen_x87_conv(tgt_mode, new_op);
3878 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3884 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
3885 if (ia32_cg_config.use_sse2) {
3886 res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg_GP, noreg_GP,
3888 set_ia32_ls_mode(res, src_mode);
3890 return gen_x87_fp_to_gp(node);
3894 /* we convert from int ... */
3895 if (mode_is_float(tgt_mode)) {
3897 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
3898 if (ia32_cg_config.use_sse2) {
3899 new_op = be_transform_node(op);
3900 res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg_GP, noreg_GP,
3902 set_ia32_ls_mode(res, tgt_mode);
3904 unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
3905 unsigned float_mantissa = get_mode_mantissa_size(tgt_mode);
3906 res = gen_x87_gp_to_fp(node, src_mode);
3908 /* we need a float-conv, if the int mode has more bits than the
3910 if (float_mantissa < int_mantissa) {
3911 res = gen_x87_conv(tgt_mode, res);
3912 SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
3916 } else if (tgt_mode == mode_b) {
3917 /* mode_b lowering already took care that we only have 0/1 values */
3918 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3919 src_mode, tgt_mode));
3920 return be_transform_node(op);
3923 if (src_bits >= tgt_bits) {
3924 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
3925 src_mode, tgt_mode));
3926 return be_transform_node(op);
3929 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
3937 static ir_node *create_immediate_or_transform(ir_node *const node)
3939 ir_node *new_node = ia32_try_create_Immediate(node, 'i');
3940 if (new_node == NULL) {
3941 new_node = be_transform_node(node);
3947 * Transforms a FrameAddr into an ia32 Add.
3949 static ir_node *gen_be_FrameAddr(ir_node *node)
3951 ir_node *block = be_transform_node(get_nodes_block(node));
3952 ir_node *op = be_get_FrameAddr_frame(node);
3953 ir_node *new_op = be_transform_node(op);
3954 dbg_info *dbgi = get_irn_dbg_info(node);
3957 new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg_GP);
3958 set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
3959 set_ia32_use_frame(new_node);
3961 SET_IA32_ORIG_NODE(new_node, node);
3967 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3969 static ir_node *gen_be_Return(ir_node *node)
3971 ir_node *ret_val = get_irn_n(node, n_be_Return_val);
3972 ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
3973 ir_node *new_ret_val = be_transform_node(ret_val);
3974 ir_node *new_ret_mem = be_transform_node(ret_mem);
3975 dbg_info *dbgi = get_irn_dbg_info(node);
3976 ir_node *block = be_transform_node(get_nodes_block(node));
3977 ir_graph *irg = get_Block_irg(block);
3978 ir_entity *ent = get_irg_entity(irg);
3979 ir_type *tp = get_entity_type(ent);
3993 assert(ret_val != NULL);
3994 if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
3995 return be_duplicate_node(node);
3998 res_type = get_method_res_type(tp, 0);
4000 if (! is_Primitive_type(res_type)) {
4001 return be_duplicate_node(node);
4004 mode = get_type_mode(res_type);
4005 if (! mode_is_float(mode)) {
4006 return be_duplicate_node(node);
4009 assert(get_method_n_ress(tp) == 1);
4011 frame = get_irg_frame(irg);
4013 /* store xmm0 onto stack */
4014 sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
4015 new_ret_mem, new_ret_val);
4016 set_ia32_ls_mode(sse_store, mode);
4017 set_ia32_op_type(sse_store, ia32_AddrModeD);
4018 set_ia32_use_frame(sse_store);
4019 store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
4021 /* load into x87 register */
4022 fld = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, mode);
4023 set_ia32_op_type(fld, ia32_AddrModeS);
4024 set_ia32_use_frame(fld);
4026 mproj = new_r_Proj(fld, mode_M, pn_ia32_fld_M);
4027 fld = new_r_Proj(fld, mode_fp, pn_ia32_fld_res);
4029 /* create a new return */
4030 arity = get_irn_arity(node);
4031 in = ALLOCAN(ir_node*, arity);
4032 pop = be_Return_get_pop(node);
4033 for (i = 0; i < arity; ++i) {
4034 ir_node *op = get_irn_n(node, i);
4035 if (op == ret_val) {
4037 } else if (op == ret_mem) {
4040 in[i] = be_transform_node(op);
4043 new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
4044 copy_node_attr(irg, node, new_node);
4050 * Transform a be_AddSP into an ia32_SubSP.
4052 static ir_node *gen_be_AddSP(ir_node *node)
4054 ir_node *sz = get_irn_n(node, n_be_AddSP_size);
4055 ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp);
4057 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
4058 match_am | match_immediate);
4059 assert(is_ia32_SubSP(new_node));
4060 arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack,
4061 &ia32_registers[REG_ESP]);
4066 * Transform a be_SubSP into an ia32_AddSP
4068 static ir_node *gen_be_SubSP(ir_node *node)
4070 ir_node *sz = get_irn_n(node, n_be_SubSP_size);
4071 ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp);
4073 ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
4074 match_am | match_immediate);
4075 assert(is_ia32_AddSP(new_node));
4076 arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack,
4077 &ia32_registers[REG_ESP]);
4081 static ir_node *gen_Phi(ir_node *node)
4083 ir_mode *mode = get_irn_mode(node);
4084 const arch_register_req_t *req;
4085 if (ia32_mode_needs_gp_reg(mode)) {
4086 /* we shouldn't have any 64bit stuff around anymore */
4087 assert(get_mode_size_bits(mode) <= 32);
4088 /* all integer operations are on 32bit registers now */
4090 req = ia32_reg_classes[CLASS_ia32_gp].class_req;
4091 } else if (mode_is_float(mode)) {
4092 if (ia32_cg_config.use_sse2) {
4094 req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
4097 req = ia32_reg_classes[CLASS_ia32_fp].class_req;
4100 req = arch_no_register_req;
4103 return be_transform_phi(node, req);
4106 static ir_node *gen_Jmp(ir_node *node)
4108 ir_node *block = get_nodes_block(node);
4109 ir_node *new_block = be_transform_node(block);
4110 dbg_info *dbgi = get_irn_dbg_info(node);
4113 new_node = new_bd_ia32_Jmp(dbgi, new_block);
4114 SET_IA32_ORIG_NODE(new_node, node);
4122 static ir_node *gen_IJmp(ir_node *node)
4124 ir_node *block = get_nodes_block(node);
4125 ir_node *new_block = be_transform_node(block);
4126 dbg_info *dbgi = get_irn_dbg_info(node);
4127 ir_node *op = get_IJmp_target(node);
4129 ia32_address_mode_t am;
4130 ia32_address_t *addr = &am.addr;
4132 assert(get_irn_mode(op) == mode_P);
4134 match_arguments(&am, block, NULL, op, NULL,
4135 match_am | match_immediate | match_upconv);
4137 new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
4138 addr->mem, am.new_op2);
4139 set_am_attributes(new_node, &am);
4140 SET_IA32_ORIG_NODE(new_node, node);
4142 new_node = fix_mem_proj(new_node, &am);
4147 static ir_node *gen_ia32_l_Add(ir_node *node)
4149 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
4150 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
4151 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
4152 match_commutative | match_am | match_immediate |
4153 match_mode_neutral);
4155 if (is_Proj(lowered)) {
4156 lowered = get_Proj_pred(lowered);
4158 assert(is_ia32_Add(lowered));
4159 set_irn_mode(lowered, mode_T);
4165 static ir_node *gen_ia32_l_Adc(ir_node *node)
4167 return gen_binop_flags(node, new_bd_ia32_Adc,
4168 match_commutative | match_am | match_immediate |
4169 match_mode_neutral);
4173 * Transforms a l_MulS into a "real" MulS node.
4175 * @return the created ia32 Mul node
4177 static ir_node *gen_ia32_l_Mul(ir_node *node)
4179 ir_node *left = get_binop_left(node);
4180 ir_node *right = get_binop_right(node);
4182 return gen_binop(node, left, right, new_bd_ia32_Mul,
4183 match_commutative | match_am | match_mode_neutral);
4187 * Transforms a l_IMulS into a "real" IMul1OPS node.
4189 * @return the created ia32 IMul1OP node
4191 static ir_node *gen_ia32_l_IMul(ir_node *node)
4193 ir_node *left = get_binop_left(node);
4194 ir_node *right = get_binop_right(node);
4196 return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
4197 match_commutative | match_am | match_mode_neutral);
4200 static ir_node *gen_ia32_l_Sub(ir_node *node)
4202 ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
4203 ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
4204 ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
4205 match_am | match_immediate | match_mode_neutral);
4207 if (is_Proj(lowered)) {
4208 lowered = get_Proj_pred(lowered);
4210 assert(is_ia32_Sub(lowered));
4211 set_irn_mode(lowered, mode_T);
4217 static ir_node *gen_ia32_l_Sbb(ir_node *node)
4219 return gen_binop_flags(node, new_bd_ia32_Sbb,
4220 match_am | match_immediate | match_mode_neutral);
4223 static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
4225 ir_node *src_block = get_nodes_block(node);
4226 ir_node *block = be_transform_node(src_block);
4227 ir_graph *irg = get_Block_irg(block);
4228 dbg_info *dbgi = get_irn_dbg_info(node);
4229 ir_node *frame = get_irg_frame(irg);
4230 ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
4231 ir_node *val_high = get_irn_n(node, n_ia32_l_LLtoFloat_val_high);
4232 ir_node *new_val_low = be_transform_node(val_low);
4233 ir_node *new_val_high = be_transform_node(val_high);
4235 ir_node *sync, *fild, *res;
4237 ir_node *store_high;
4241 if (ia32_cg_config.use_sse2) {
4242 panic("not implemented for SSE2");
4246 store_low = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4248 store_high = new_bd_ia32_Store(dbgi, block, frame, noreg_GP, nomem,
4250 SET_IA32_ORIG_NODE(store_low, node);
4251 SET_IA32_ORIG_NODE(store_high, node);
4253 mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M);
4254 mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M);
4256 set_ia32_use_frame(store_low);
4257 set_ia32_use_frame(store_high);
4258 set_ia32_op_type(store_low, ia32_AddrModeD);
4259 set_ia32_op_type(store_high, ia32_AddrModeD);
4260 set_ia32_ls_mode(store_low, mode_Iu);
4261 set_ia32_ls_mode(store_high, mode_Is);
4262 add_ia32_am_offs_int(store_high, 4);
4266 sync = new_rd_Sync(dbgi, block, 2, in);
4269 fild = new_bd_ia32_fild(dbgi, block, frame, noreg_GP, sync);
4271 set_ia32_use_frame(fild);
4272 set_ia32_op_type(fild, ia32_AddrModeS);
4273 set_ia32_ls_mode(fild, mode_Ls);
4275 SET_IA32_ORIG_NODE(fild, node);
4277 res = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
4279 if (! mode_is_signed(get_irn_mode(val_high))) {
4280 ia32_address_mode_t am;
4282 ir_node *count = ia32_create_Immediate(irg, NULL, 0, 31);
4285 am.addr.base = get_symconst_base();
4286 am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
4287 am.addr.mem = nomem;
4290 am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
4291 am.addr.tls_segment = false;
4292 am.addr.use_frame = 0;
4293 am.addr.frame_entity = NULL;
4294 am.addr.symconst_sign = 0;
4295 am.ls_mode = mode_F;
4296 am.mem_proj = nomem;
4297 am.op_type = ia32_AddrModeS;
4299 am.new_op2 = ia32_new_NoReg_fp(irg);
4300 am.pinned = op_pin_state_floats;
4302 am.ins_permuted = false;
4304 fadd = new_bd_ia32_fadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
4305 am.new_op1, am.new_op2, get_fpcw());
4306 set_am_attributes(fadd, &am);
4308 set_irn_mode(fadd, mode_T);
4309 res = new_rd_Proj(NULL, fadd, mode_fp, pn_ia32_res);
4314 static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
4316 ir_node *src_block = get_nodes_block(node);
4317 ir_node *block = be_transform_node(src_block);
4318 ir_graph *irg = get_Block_irg(block);
4319 dbg_info *dbgi = get_irn_dbg_info(node);
4320 ir_node *frame = get_irg_frame(irg);
4321 ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
4322 ir_node *new_val = be_transform_node(val);
4325 fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val);
4326 SET_IA32_ORIG_NODE(fist, node);
4327 set_ia32_use_frame(fist);
4328 set_ia32_op_type(fist, ia32_AddrModeD);
4329 set_ia32_ls_mode(fist, mode_Ls);
4331 assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
4332 return new_r_Proj(fist, mode_M, pn_ia32_fist_M);
4335 static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
4337 ir_node *block = be_transform_node(get_nodes_block(node));
4338 ir_graph *irg = get_Block_irg(block);
4339 ir_node *pred = get_Proj_pred(node);
4340 ir_node *new_pred = be_transform_node(pred);
4341 ir_node *frame = get_irg_frame(irg);
4342 dbg_info *dbgi = get_irn_dbg_info(node);
4343 long pn = get_Proj_proj(node);
4348 load = new_bd_ia32_Load(dbgi, block, frame, noreg_GP, new_pred);
4349 SET_IA32_ORIG_NODE(load, node);
4350 set_ia32_use_frame(load);
4351 set_ia32_op_type(load, ia32_AddrModeS);
4352 set_ia32_ls_mode(load, mode_Iu);
4353 /* we need a 64bit stackslot (fist stores 64bit) even though we only load
4354 * 32 bit from it with this particular load */
4355 attr = get_ia32_attr(load);
4356 attr->data.need_64bit_stackent = 1;
4358 if (pn == pn_ia32_l_FloattoLL_res_high) {
4359 add_ia32_am_offs_int(load, 4);
4361 assert(pn == pn_ia32_l_FloattoLL_res_low);
4364 proj = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4370 * Transform the Projs of an AddSP.
4372 static ir_node *gen_Proj_be_AddSP(ir_node *node)
4374 ir_node *pred = get_Proj_pred(node);
4375 ir_node *new_pred = be_transform_node(pred);
4376 dbg_info *dbgi = get_irn_dbg_info(node);
4377 long proj = get_Proj_proj(node);
4379 if (proj == pn_be_AddSP_sp) {
4380 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4381 pn_ia32_SubSP_stack);
4382 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4384 } else if (proj == pn_be_AddSP_res) {
4385 return new_rd_Proj(dbgi, new_pred, mode_Iu,
4386 pn_ia32_SubSP_addr);
4387 } else if (proj == pn_be_AddSP_M) {
4388 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_SubSP_M);
4391 panic("No idea how to transform proj->AddSP");
4395 * Transform the Projs of a SubSP.
4397 static ir_node *gen_Proj_be_SubSP(ir_node *node)
4399 ir_node *pred = get_Proj_pred(node);
4400 ir_node *new_pred = be_transform_node(pred);
4401 dbg_info *dbgi = get_irn_dbg_info(node);
4402 long proj = get_Proj_proj(node);
4404 if (proj == pn_be_SubSP_sp) {
4405 ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
4406 pn_ia32_AddSP_stack);
4407 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
4409 } else if (proj == pn_be_SubSP_M) {
4410 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
4413 panic("No idea how to transform proj->SubSP");
4417 * Transform and renumber the Projs from a Load.
4419 static ir_node *gen_Proj_Load(ir_node *node)
4422 ir_node *pred = get_Proj_pred(node);
4423 dbg_info *dbgi = get_irn_dbg_info(node);
4424 long proj = get_Proj_proj(node);
4426 /* loads might be part of source address mode matches, so we don't
4427 * transform the ProjMs yet (with the exception of loads whose result is
4430 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4433 /* this is needed, because sometimes we have loops that are only
4434 reachable through the ProjM */
4435 be_enqueue_preds(node);
4436 /* do it in 2 steps, to silence firm verifier */
4437 res = new_rd_Proj(dbgi, pred, mode_M, pn_Load_M);
4438 set_Proj_proj(res, pn_ia32_mem);
4442 /* renumber the proj */
4443 new_pred = be_transform_node(pred);
4444 if (is_ia32_Load(new_pred)) {
4445 switch ((pn_Load)proj) {
4447 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
4449 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
4450 case pn_Load_X_except:
4451 /* This Load might raise an exception. Mark it. */
4452 set_ia32_exc_label(new_pred, 1);
4453 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
4454 case pn_Load_X_regular:
4455 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
4457 } else if (is_ia32_Conv_I2I(new_pred) ||
4458 is_ia32_Conv_I2I8Bit(new_pred)) {
4459 set_irn_mode(new_pred, mode_T);
4460 switch ((pn_Load)proj) {
4462 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
4464 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
4465 case pn_Load_X_except:
4466 /* This Load might raise an exception. Mark it. */
4467 set_ia32_exc_label(new_pred, 1);
4468 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except);
4469 case pn_Load_X_regular:
4470 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular);
4472 } else if (is_ia32_xLoad(new_pred)) {
4473 switch ((pn_Load)proj) {
4475 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
4477 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
4478 case pn_Load_X_except:
4479 /* This Load might raise an exception. Mark it. */
4480 set_ia32_exc_label(new_pred, 1);
4481 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
4482 case pn_Load_X_regular:
4483 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
4485 } else if (is_ia32_fld(new_pred)) {
4486 switch ((pn_Load)proj) {
4488 return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fld_res);
4490 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fld_M);
4491 case pn_Load_X_except:
4492 /* This Load might raise an exception. Mark it. */
4493 set_ia32_exc_label(new_pred, 1);
4494 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_except);
4495 case pn_Load_X_regular:
4496 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_regular);
4499 /* can happen for ProJMs when source address mode happened for the
4502 /* however it should not be the result proj, as that would mean the
4503 load had multiple users and should not have been used for
4505 if (proj != pn_Load_M) {
4506 panic("internal error: transformed node not a Load");
4508 return new_rd_Proj(dbgi, new_pred, mode_M, 1);
4511 panic("No idea how to transform Proj(Load) %+F", node);
4514 static ir_node *gen_Proj_Store(ir_node *node)
4516 ir_node *pred = get_Proj_pred(node);
4517 ir_node *new_pred = be_transform_node(pred);
4518 dbg_info *dbgi = get_irn_dbg_info(node);
4519 long pn = get_Proj_proj(node);
4521 if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
4522 switch ((pn_Store)pn) {
4524 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
4525 case pn_Store_X_except:
4526 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except);
4527 case pn_Store_X_regular:
4528 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
4530 } else if (is_ia32_fist(new_pred)) {
4531 switch ((pn_Store)pn) {
4533 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fist_M);
4534 case pn_Store_X_except:
4535 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_except);
4536 case pn_Store_X_regular:
4537 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_regular);
4539 } else if (is_ia32_fisttp(new_pred)) {
4540 switch ((pn_Store)pn) {
4542 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fisttp_M);
4543 case pn_Store_X_except:
4544 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_except);
4545 case pn_Store_X_regular:
4546 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_regular);
4548 } else if (is_ia32_fst(new_pred)) {
4549 switch ((pn_Store)pn) {
4551 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fst_M);
4552 case pn_Store_X_except:
4553 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_except);
4554 case pn_Store_X_regular:
4555 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_regular);
4557 } else if (is_ia32_xStore(new_pred)) {
4558 switch ((pn_Store)pn) {
4560 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M);
4561 case pn_Store_X_except:
4562 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except);
4563 case pn_Store_X_regular:
4564 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular);
4566 } else if (is_Sync(new_pred)) {
4567 /* hack for the case that gen_float_const_Store produced a Sync */
4568 if (pn == pn_Store_M) {
4571 panic("exception control flow not implemented yet");
4572 } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
4573 /* destination address mode */
4574 if (pn == pn_Store_M) {
4577 panic("exception control flow for destination AM not implemented yet");
4580 panic("No idea how to transform Proj(Store) %+F", node);
4584 * Transform and renumber the Projs from a Div or Mod instruction.
4586 static ir_node *gen_Proj_Div(ir_node *node)
4588 ir_node *pred = get_Proj_pred(node);
4589 ir_node *new_pred = be_transform_node(pred);
4590 dbg_info *dbgi = get_irn_dbg_info(node);
4591 long proj = get_Proj_proj(node);
4593 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4594 assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res);
4596 switch ((pn_Div)proj) {
4598 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4599 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4600 } else if (is_ia32_xDiv(new_pred)) {
4601 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
4602 } else if (is_ia32_fdiv(new_pred)) {
4603 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fdiv_M);
4605 panic("Div transformed to unexpected thing %+F", new_pred);
4608 if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
4609 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
4610 } else if (is_ia32_xDiv(new_pred)) {
4611 return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
4612 } else if (is_ia32_fdiv(new_pred)) {
4613 return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fdiv_res);
4615 panic("Div transformed to unexpected thing %+F", new_pred);
4617 case pn_Div_X_except:
4618 set_ia32_exc_label(new_pred, 1);
4619 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4620 case pn_Div_X_regular:
4621 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4624 panic("No idea how to transform proj->Div");
4628 * Transform and renumber the Projs from a Div or Mod instruction.
4630 static ir_node *gen_Proj_Mod(ir_node *node)
4632 ir_node *pred = get_Proj_pred(node);
4633 ir_node *new_pred = be_transform_node(pred);
4634 dbg_info *dbgi = get_irn_dbg_info(node);
4635 long proj = get_Proj_proj(node);
4637 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4638 assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
4639 assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res);
4641 switch ((pn_Mod)proj) {
4643 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
4645 return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4646 case pn_Mod_X_except:
4647 set_ia32_exc_label(new_pred, 1);
4648 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
4649 case pn_Mod_X_regular:
4650 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
4652 panic("No idea how to transform proj->Mod");
4656 * Transform and renumber the Projs from a CopyB.
4658 static ir_node *gen_Proj_CopyB(ir_node *node)
4660 ir_node *pred = get_Proj_pred(node);
4661 ir_node *new_pred = be_transform_node(pred);
4662 dbg_info *dbgi = get_irn_dbg_info(node);
4663 long proj = get_Proj_proj(node);
4665 switch ((pn_CopyB)proj) {
4667 if (is_ia32_CopyB_i(new_pred)) {
4668 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
4669 } else if (is_ia32_CopyB(new_pred)) {
4670 return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
4673 case pn_CopyB_X_regular:
4674 if (is_ia32_CopyB_i(new_pred)) {
4675 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular);
4676 } else if (is_ia32_CopyB(new_pred)) {
4677 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular);
4680 case pn_CopyB_X_except:
4681 if (is_ia32_CopyB_i(new_pred)) {
4682 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except);
4683 } else if (is_ia32_CopyB(new_pred)) {
4684 return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except);
4689 panic("No idea how to transform proj->CopyB");
4692 static ir_node *gen_be_Call(ir_node *node)
4694 dbg_info *const dbgi = get_irn_dbg_info(node);
4695 ir_node *const src_block = get_nodes_block(node);
4696 ir_node *const block = be_transform_node(src_block);
4697 ir_node *const src_mem = get_irn_n(node, n_be_Call_mem);
4698 ir_node *const src_sp = get_irn_n(node, n_be_Call_sp);
4699 ir_node *const sp = be_transform_node(src_sp);
4700 ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr);
4701 ia32_address_mode_t am;
4702 ia32_address_t *const addr = &am.addr;
4707 ir_node * eax = noreg_GP;
4708 ir_node * ecx = noreg_GP;
4709 ir_node * edx = noreg_GP;
4710 unsigned const pop = be_Call_get_pop(node);
4711 ir_type *const call_tp = be_Call_get_type(node);
4712 int old_no_pic_adjust;
4713 int throws_exception = ir_throws_exception(node);
4715 /* Run the x87 simulator if the call returns a float value */
4716 if (get_method_n_ress(call_tp) > 0) {
4717 ir_type *const res_type = get_method_res_type(call_tp, 0);
4718 ir_mode *const res_mode = get_type_mode(res_type);
4720 if (res_mode != NULL && mode_is_float(res_mode)) {
4721 ir_graph *irg = get_Block_irg(block);
4722 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4723 irg_data->do_x87_sim = 1;
4727 /* We do not want be_Call direct calls */
4728 assert(be_Call_get_entity(node) == NULL);
4730 /* special case for PIC trampoline calls */
4731 old_no_pic_adjust = ia32_no_pic_adjust;
4732 ia32_no_pic_adjust = be_options.pic;
4734 match_arguments(&am, src_block, NULL, src_ptr, src_mem,
4735 match_am | match_immediate | match_upconv);
4737 ia32_no_pic_adjust = old_no_pic_adjust;
4739 i = get_irn_arity(node) - 1;
4740 fpcw = be_transform_node(get_irn_n(node, i--));
4741 for (; i >= n_be_Call_first_arg; --i) {
4742 arch_register_req_t const *const req
4743 = arch_get_irn_register_req_in(node, i);
4744 ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
4746 assert(req->type == arch_register_req_type_limited);
4747 assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
4749 switch (*req->limited) {
4750 case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
4751 case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
4752 case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
4753 default: panic("Invalid GP register for register parameter");
4757 mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
4758 call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
4759 am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
4760 ir_set_throws_exception(call, throws_exception);
4761 set_am_attributes(call, &am);
4762 call = fix_mem_proj(call, &am);
4764 if (get_irn_pinned(node) == op_pin_state_pinned)
4765 set_irn_pinned(call, op_pin_state_pinned);
4767 SET_IA32_ORIG_NODE(call, node);
4769 if (ia32_cg_config.use_sse2) {
4770 /* remember this call for post-processing */
4771 ARR_APP1(ir_node *, call_list, call);
4772 ARR_APP1(ir_type *, call_types, be_Call_get_type(node));
4779 * Transform Builtin trap
4781 static ir_node *gen_trap(ir_node *node)
4783 dbg_info *dbgi = get_irn_dbg_info(node);
4784 ir_node *block = be_transform_node(get_nodes_block(node));
4785 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4787 return new_bd_ia32_UD2(dbgi, block, mem);
4791 * Transform Builtin debugbreak
4793 static ir_node *gen_debugbreak(ir_node *node)
4795 dbg_info *dbgi = get_irn_dbg_info(node);
4796 ir_node *block = be_transform_node(get_nodes_block(node));
4797 ir_node *mem = be_transform_node(get_Builtin_mem(node));
4799 return new_bd_ia32_Breakpoint(dbgi, block, mem);
4803 * Transform Builtin return_address
4805 static ir_node *gen_return_address(ir_node *node)
4807 ir_node *param = get_Builtin_param(node, 0);
4808 ir_node *frame = get_Builtin_param(node, 1);
4809 dbg_info *dbgi = get_irn_dbg_info(node);
4810 ir_tarval *tv = get_Const_tarval(param);
4811 ir_graph *irg = get_irn_irg(node);
4812 unsigned long value = get_tarval_long(tv);
4814 ir_node *block = be_transform_node(get_nodes_block(node));
4815 ir_node *ptr = be_transform_node(frame);
4819 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4820 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4821 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4824 /* load the return address from this frame */
4825 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4827 set_irn_pinned(load, get_irn_pinned(node));
4828 set_ia32_op_type(load, ia32_AddrModeS);
4829 set_ia32_ls_mode(load, mode_Iu);
4831 set_ia32_am_offs_int(load, 0);
4832 set_ia32_use_frame(load);
4833 set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
4835 if (get_irn_pinned(node) == op_pin_state_floats) {
4836 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
4837 && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
4838 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4839 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4842 SET_IA32_ORIG_NODE(load, node);
4843 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4847 * Transform Builtin frame_address
4849 static ir_node *gen_frame_address(ir_node *node)
4851 ir_node *param = get_Builtin_param(node, 0);
4852 ir_node *frame = get_Builtin_param(node, 1);
4853 dbg_info *dbgi = get_irn_dbg_info(node);
4854 ir_tarval *tv = get_Const_tarval(param);
4855 ir_graph *irg = get_irn_irg(node);
4856 unsigned long value = get_tarval_long(tv);
4858 ir_node *block = be_transform_node(get_nodes_block(node));
4859 ir_node *ptr = be_transform_node(frame);
4864 ir_node *cnt = new_bd_ia32_ProduceVal(dbgi, block);
4865 ir_node *res = new_bd_ia32_ProduceVal(dbgi, block);
4866 ptr = new_bd_ia32_ClimbFrame(dbgi, block, ptr, cnt, res, value);
4869 /* load the frame address from this frame */
4870 load = new_bd_ia32_Load(dbgi, block, ptr, noreg_GP, nomem);
4872 set_irn_pinned(load, get_irn_pinned(node));
4873 set_ia32_op_type(load, ia32_AddrModeS);
4874 set_ia32_ls_mode(load, mode_Iu);
4876 ent = ia32_get_frame_address_entity(irg);
4878 set_ia32_am_offs_int(load, 0);
4879 set_ia32_use_frame(load);
4880 set_ia32_frame_ent(load, ent);
4882 /* will fail anyway, but gcc does this: */
4883 set_ia32_am_offs_int(load, 0);
4886 if (get_irn_pinned(node) == op_pin_state_floats) {
4887 assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
4888 && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
4889 && (int)pn_ia32_Load_res == (int)pn_ia32_res);
4890 arch_add_irn_flags(load, arch_irn_flags_rematerializable);
4893 SET_IA32_ORIG_NODE(load, node);
4894 return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
4898 * Transform Builtin frame_address
4900 static ir_node *gen_prefetch(ir_node *node)
4903 ir_node *ptr, *block, *mem, *base, *idx;
4904 ir_node *param, *new_node;
4907 ia32_address_t addr;
4909 if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
4910 /* no prefetch at all, route memory */
4911 return be_transform_node(get_Builtin_mem(node));
4914 param = get_Builtin_param(node, 1);
4915 tv = get_Const_tarval(param);
4916 rw = get_tarval_long(tv);
4918 /* construct load address */
4919 memset(&addr, 0, sizeof(addr));
4920 ptr = get_Builtin_param(node, 0);
4921 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
4928 base = be_transform_node(base);
4934 idx = be_transform_node(idx);
4937 dbgi = get_irn_dbg_info(node);
4938 block = be_transform_node(get_nodes_block(node));
4939 mem = be_transform_node(get_Builtin_mem(node));
4941 if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
4942 /* we have 3DNow!, this was already checked above */
4943 new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem);
4944 } else if (ia32_cg_config.use_sse_prefetch) {
4945 /* note: rw == 1 is IGNORED in that case */
4946 param = get_Builtin_param(node, 2);
4947 tv = get_Const_tarval(param);
4948 locality = get_tarval_long(tv);
4950 /* SSE style prefetch */
4953 new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
4956 new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
4959 new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
4962 new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
4966 assert(ia32_cg_config.use_3dnow_prefetch);
4967 /* 3DNow! style prefetch */
4968 new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem);
4971 set_irn_pinned(new_node, get_irn_pinned(node));
4972 set_ia32_op_type(new_node, ia32_AddrModeS);
4973 set_ia32_ls_mode(new_node, mode_Bu);
4974 set_address(new_node, &addr);
4976 SET_IA32_ORIG_NODE(new_node, node);
4978 return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
4982 * Transform bsf like node
4984 static ir_node *gen_unop_AM(ir_node *node, construct_binop_dest_func *func)
4986 ir_node *param = get_Builtin_param(node, 0);
4987 dbg_info *dbgi = get_irn_dbg_info(node);
4989 ir_node *block = get_nodes_block(node);
4990 ir_node *new_block = be_transform_node(block);
4992 ia32_address_mode_t am;
4993 ia32_address_t *addr = &am.addr;
4996 match_arguments(&am, block, NULL, param, NULL, match_am);
4998 cnt = func(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
4999 set_am_attributes(cnt, &am);
5000 set_ia32_ls_mode(cnt, get_irn_mode(param));
5002 SET_IA32_ORIG_NODE(cnt, node);
5003 return fix_mem_proj(cnt, &am);
5007 * Transform builtin ffs.
5009 static ir_node *gen_ffs(ir_node *node)
5011 ir_node *bsf = gen_unop_AM(node, new_bd_ia32_Bsf);
5012 ir_node *real = skip_Proj(bsf);
5013 dbg_info *dbgi = get_irn_dbg_info(real);
5014 ir_node *block = get_nodes_block(real);
5015 ir_node *flag, *set, *conv, *neg, *orn, *add;
5018 if (get_irn_mode(real) != mode_T) {
5019 set_irn_mode(real, mode_T);
5020 bsf = new_r_Proj(real, mode_Iu, pn_ia32_res);
5023 flag = new_r_Proj(real, mode_b, pn_ia32_flags);
5026 set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal);
5027 SET_IA32_ORIG_NODE(set, node);
5030 conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
5031 SET_IA32_ORIG_NODE(conv, node);
5034 neg = new_bd_ia32_Neg(dbgi, block, conv);
5037 orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
5038 set_ia32_ls_mode(orn, mode_Iu);
5039 set_ia32_commutative(orn);
5042 add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP);
5043 add_ia32_am_offs_int(add, 1);
5048 * Transform builtin clz.
5050 static ir_node *gen_clz(ir_node *node)
5052 ir_node *bsr = gen_unop_AM(node, new_bd_ia32_Bsr);
5053 ir_node *real = skip_Proj(bsr);
5054 dbg_info *dbgi = get_irn_dbg_info(real);
5055 ir_node *block = get_nodes_block(real);
5056 ir_graph *irg = get_Block_irg(block);
5057 ir_node *imm = ia32_create_Immediate(irg, NULL, 0, 31);
5059 return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
5063 * Transform builtin ctz.
5065 static ir_node *gen_ctz(ir_node *node)
5067 return gen_unop_AM(node, new_bd_ia32_Bsf);
5071 * Transform builtin parity.
5073 static ir_node *gen_parity(ir_node *node)
5075 dbg_info *dbgi = get_irn_dbg_info(node);
5076 ir_node *block = get_nodes_block(node);
5077 ir_node *new_block = be_transform_node(block);
5078 ir_node *param = get_Builtin_param(node, 0);
5079 ir_node *new_param = be_transform_node(param);
5082 /* the x86 parity bit is stupid: it only looks at the lowest byte,
5083 * so we have to do complicated xoring first.
5084 * (we should also better lower this before the backend so we still have a
5085 * chance for CSE, constant folding and other goodies for some of these
5088 ir_graph *const irg = get_Block_irg(new_block);
5089 ir_node *const count = ia32_create_Immediate(irg, NULL, 0, 16);
5090 ir_node *const shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
5091 ir_node *const xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, shr, new_param);
5092 ir_node *const xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
5095 set_ia32_ls_mode(xorn, mode_Iu);
5096 set_ia32_commutative(xorn);
5098 set_irn_mode(xor2, mode_T);
5099 flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
5102 new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity);
5103 SET_IA32_ORIG_NODE(new_node, node);
5106 new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
5107 nomem, new_node, mode_Bu);
5108 SET_IA32_ORIG_NODE(new_node, node);
5113 * Transform builtin popcount
5115 static ir_node *gen_popcount(ir_node *node)
5117 ir_node *param = get_Builtin_param(node, 0);
5118 dbg_info *dbgi = get_irn_dbg_info(node);
5120 ir_node *block = get_nodes_block(node);
5121 ir_node *new_block = be_transform_node(block);
5124 ir_node *imm, *simm, *m1, *s1, *s2, *s3, *s4, *s5, *m2, *m3, *m4, *m5, *m6, *m7, *m8, *m9, *m10, *m11, *m12, *m13;
5126 /* check for SSE4.2 or SSE4a and use the popcnt instruction */
5127 if (ia32_cg_config.use_popcnt) {
5128 ia32_address_mode_t am;
5129 ia32_address_t *addr = &am.addr;
5132 match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am | match_upconv);
5134 cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
5135 set_am_attributes(cnt, &am);
5136 set_ia32_ls_mode(cnt, get_irn_mode(param));
5138 SET_IA32_ORIG_NODE(cnt, node);
5139 return fix_mem_proj(cnt, &am);
5142 new_param = be_transform_node(param);
5144 /* do the standard popcount algo */
5145 /* TODO: This is stupid, we should transform this before the backend,
5146 * to get CSE, localopts, etc. for the operations
5147 * TODO: This is also not the optimal algorithm (it is just the starting
5148 * example in hackers delight, they optimize it more on the following page)
5149 * But I'm too lazy to fix this now, as the code should get lowered before
5150 * the backend anyway.
5152 ir_graph *const irg = get_Block_irg(new_block);
5154 /* m1 = x & 0x55555555 */
5155 imm = ia32_create_Immediate(irg, NULL, 0, 0x55555555);
5156 m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
5159 simm = ia32_create_Immediate(irg, NULL, 0, 1);
5160 s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
5162 /* m2 = s1 & 0x55555555 */
5163 m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
5166 m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
5168 /* m4 = m3 & 0x33333333 */
5169 imm = ia32_create_Immediate(irg, NULL, 0, 0x33333333);
5170 m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
5173 simm = ia32_create_Immediate(irg, NULL, 0, 2);
5174 s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
5176 /* m5 = s2 & 0x33333333 */
5177 m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
5180 m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
5182 /* m7 = m6 & 0x0F0F0F0F */
5183 imm = ia32_create_Immediate(irg, NULL, 0, 0x0F0F0F0F);
5184 m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
5187 simm = ia32_create_Immediate(irg, NULL, 0, 4);
5188 s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
5190 /* m8 = s3 & 0x0F0F0F0F */
5191 m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
5194 m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
5196 /* m10 = m9 & 0x00FF00FF */
5197 imm = ia32_create_Immediate(irg, NULL, 0, 0x00FF00FF);
5198 m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
5201 simm = ia32_create_Immediate(irg, NULL, 0, 8);
5202 s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
5204 /* m11 = s4 & 0x00FF00FF */
5205 m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
5207 /* m12 = m10 + m11 */
5208 m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
5210 /* m13 = m12 & 0x0000FFFF */
5211 imm = ia32_create_Immediate(irg, NULL, 0, 0x0000FFFF);
5212 m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
5214 /* s5 = m12 >> 16 */
5215 simm = ia32_create_Immediate(irg, NULL, 0, 16);
5216 s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
5218 /* res = m13 + s5 */
5219 return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
5223 * Transform builtin byte swap.
5225 static ir_node *gen_bswap(ir_node *node)
5227 ir_node *param = be_transform_node(get_Builtin_param(node, 0));
5228 dbg_info *dbgi = get_irn_dbg_info(node);
5230 ir_node *block = get_nodes_block(node);
5231 ir_node *new_block = be_transform_node(block);
5232 ir_mode *mode = get_irn_mode(param);
5233 unsigned size = get_mode_size_bits(mode);
5237 if (ia32_cg_config.use_bswap) {
5238 /* swap available */
5239 return new_bd_ia32_Bswap(dbgi, new_block, param);
5241 ir_graph *const irg = get_Block_irg(new_block);
5242 ir_node *const i8 = ia32_create_Immediate(irg, NULL, 0, 8);
5243 ir_node *const rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
5244 ir_node *const i16 = ia32_create_Immediate(irg, NULL, 0, 16);
5245 ir_node *const rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
5246 ir_node *const rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
5247 set_ia32_ls_mode(rol1, mode_Hu);
5248 set_ia32_ls_mode(rol2, mode_Iu);
5249 set_ia32_ls_mode(rol3, mode_Hu);
5254 /* swap16 always available */
5255 return new_bd_ia32_Bswap16(dbgi, new_block, param);
5258 panic("Invalid bswap size (%d)", size);
5263 * Transform builtin outport.
5265 static ir_node *gen_outport(ir_node *node)
5267 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
5268 ir_node *oldv = get_Builtin_param(node, 1);
5269 ir_mode *mode = get_irn_mode(oldv);
5270 ir_node *value = be_transform_node(oldv);
5271 ir_node *block = be_transform_node(get_nodes_block(node));
5272 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5273 dbg_info *dbgi = get_irn_dbg_info(node);
5275 ir_node *res = new_bd_ia32_Outport(dbgi, block, port, value, mem);
5276 set_ia32_ls_mode(res, mode);
5281 * Transform builtin inport.
5283 static ir_node *gen_inport(ir_node *node)
5285 ir_type *tp = get_Builtin_type(node);
5286 ir_type *rstp = get_method_res_type(tp, 0);
5287 ir_mode *mode = get_type_mode(rstp);
5288 ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
5289 ir_node *block = be_transform_node(get_nodes_block(node));
5290 ir_node *mem = be_transform_node(get_Builtin_mem(node));
5291 dbg_info *dbgi = get_irn_dbg_info(node);
5293 ir_node *res = new_bd_ia32_Inport(dbgi, block, port, mem);
5294 set_ia32_ls_mode(res, mode);
5296 /* check for missing Result Proj */
5301 * Transform a builtin inner trampoline
5303 static ir_node *gen_inner_trampoline(ir_node *node)
5305 ir_node *ptr = get_Builtin_param(node, 0);
5306 ir_node *callee = get_Builtin_param(node, 1);
5307 ir_node *env = be_transform_node(get_Builtin_param(node, 2));
5308 ir_node *mem = get_Builtin_mem(node);
5309 ir_node *block = get_nodes_block(node);
5310 ir_node *new_block = be_transform_node(block);
5314 ir_node *trampoline;
5316 dbg_info *dbgi = get_irn_dbg_info(node);
5317 ia32_address_t addr;
5319 /* construct store address */
5320 memset(&addr, 0, sizeof(addr));
5321 ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
5323 if (addr.base == NULL) {
5324 addr.base = noreg_GP;
5326 addr.base = be_transform_node(addr.base);
5329 if (addr.index == NULL) {
5330 addr.index = noreg_GP;
5332 addr.index = be_transform_node(addr.index);
5334 addr.mem = be_transform_node(mem);
5336 ir_graph *const irg = get_Block_irg(new_block);
5337 /* mov ecx, <env> */
5338 val = ia32_create_Immediate(irg, NULL, 0, 0xB9);
5339 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5340 addr.index, addr.mem, val);
5341 set_irn_pinned(store, get_irn_pinned(node));
5342 set_ia32_op_type(store, ia32_AddrModeD);
5343 set_ia32_ls_mode(store, mode_Bu);
5344 set_address(store, &addr);
5348 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5349 addr.index, addr.mem, env);
5350 set_irn_pinned(store, get_irn_pinned(node));
5351 set_ia32_op_type(store, ia32_AddrModeD);
5352 set_ia32_ls_mode(store, mode_Iu);
5353 set_address(store, &addr);
5357 /* jmp rel <callee> */
5358 val = ia32_create_Immediate(irg, NULL, 0, 0xE9);
5359 store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
5360 addr.index, addr.mem, val);
5361 set_irn_pinned(store, get_irn_pinned(node));
5362 set_ia32_op_type(store, ia32_AddrModeD);
5363 set_ia32_ls_mode(store, mode_Bu);
5364 set_address(store, &addr);
5368 trampoline = be_transform_node(ptr);
5370 /* the callee is typically an immediate */
5371 if (is_SymConst(callee)) {
5372 rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
5374 rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP);
5375 add_ia32_am_offs_int(rel, -10);
5377 rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
5379 store = new_bd_ia32_Store(dbgi, new_block, addr.base,
5380 addr.index, addr.mem, rel);
5381 set_irn_pinned(store, get_irn_pinned(node));
5382 set_ia32_op_type(store, ia32_AddrModeD);
5383 set_ia32_ls_mode(store, mode_Iu);
5384 set_address(store, &addr);
5389 return new_r_Tuple(new_block, 2, in);
5393 * Transform Builtin node.
5395 static ir_node *gen_Builtin(ir_node *node)
5397 ir_builtin_kind kind = get_Builtin_kind(node);
5401 return gen_trap(node);
5402 case ir_bk_debugbreak:
5403 return gen_debugbreak(node);
5404 case ir_bk_return_address:
5405 return gen_return_address(node);
5406 case ir_bk_frame_address:
5407 return gen_frame_address(node);
5408 case ir_bk_prefetch:
5409 return gen_prefetch(node);
5411 return gen_ffs(node);
5413 return gen_clz(node);
5415 return gen_ctz(node);
5417 return gen_parity(node);
5418 case ir_bk_popcount:
5419 return gen_popcount(node);
5421 return gen_bswap(node);
5423 return gen_outport(node);
5425 return gen_inport(node);
5426 case ir_bk_inner_trampoline:
5427 return gen_inner_trampoline(node);
5429 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
5433 * Transform Proj(Builtin) node.
5435 static ir_node *gen_Proj_Builtin(ir_node *proj)
5437 ir_node *node = get_Proj_pred(proj);
5438 ir_node *new_node = be_transform_node(node);
5439 ir_builtin_kind kind = get_Builtin_kind(node);
5442 case ir_bk_return_address:
5443 case ir_bk_frame_address:
5448 case ir_bk_popcount:
5450 assert(get_Proj_proj(proj) == pn_Builtin_max+1);
5453 case ir_bk_debugbreak:
5454 case ir_bk_prefetch:
5456 assert(get_Proj_proj(proj) == pn_Builtin_M);
5459 if (get_Proj_proj(proj) == pn_Builtin_max+1) {
5460 return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
5462 assert(get_Proj_proj(proj) == pn_Builtin_M);
5463 return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
5465 case ir_bk_inner_trampoline:
5466 if (get_Proj_proj(proj) == pn_Builtin_max+1) {
5467 return get_Tuple_pred(new_node, 1);
5469 assert(get_Proj_proj(proj) == pn_Builtin_M);
5470 return get_Tuple_pred(new_node, 0);
5473 panic("Builtin %s not implemented", get_builtin_kind_name(kind));
5476 static ir_node *gen_be_IncSP(ir_node *node)
5478 ir_node *res = be_duplicate_node(node);
5479 arch_add_irn_flags(res, arch_irn_flags_modify_flags);
5485 * Transform the Projs from a be_Call.
5487 static ir_node *gen_Proj_be_Call(ir_node *node)
5489 ir_node *call = get_Proj_pred(node);
5490 ir_node *new_call = be_transform_node(call);
5491 dbg_info *dbgi = get_irn_dbg_info(node);
5492 long proj = get_Proj_proj(node);
5493 ir_mode *mode = get_irn_mode(node);
5496 if (proj == pn_be_Call_M) {
5497 return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
5499 /* transform call modes */
5500 if (mode_is_data(mode)) {
5501 const arch_register_class_t *cls = arch_get_irn_reg_class(node);
5505 /* Map from be_Call to ia32_Call proj number */
5506 if (proj == pn_be_Call_sp) {
5507 proj = pn_ia32_Call_stack;
5508 } else if (proj == pn_be_Call_M) {
5509 proj = pn_ia32_Call_M;
5510 } else if (proj == pn_be_Call_X_except) {
5511 proj = pn_ia32_Call_X_except;
5512 } else if (proj == pn_be_Call_X_regular) {
5513 proj = pn_ia32_Call_X_regular;
5515 arch_register_req_t const *const req = arch_get_irn_register_req(node);
5517 assert(proj >= pn_be_Call_first_res);
5518 assert(arch_register_req_is(req, limited));
5520 be_foreach_out(new_call, i) {
5521 arch_register_req_t const *const new_req = arch_get_irn_register_req_out(new_call, i);
5522 if (!arch_register_req_is(new_req, limited) ||
5523 new_req->cls != req->cls ||
5524 *new_req->limited != *req->limited)
5530 panic("no matching out requirement found");
5534 res = new_rd_Proj(dbgi, new_call, mode, proj);
5536 /* TODO arch_set_irn_register() only operates on Projs, need variant with index */
5538 case pn_ia32_Call_stack:
5539 arch_set_irn_register(res, &ia32_registers[REG_ESP]);
5542 case pn_ia32_Call_fpcw:
5543 arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
5550 static ir_node *gen_Proj_ASM(ir_node *node)
5552 ir_mode *mode = get_irn_mode(node);
5553 ir_node *pred = get_Proj_pred(node);
5554 ir_node *new_pred = be_transform_node(pred);
5555 long pos = get_Proj_proj(node);
5557 if (mode == mode_M) {
5558 pos = arch_get_irn_n_outs(new_pred)-1;
5559 } else if (mode_is_int(mode) || mode_is_reference(mode)) {
5561 } else if (mode_is_float(mode)) {
5564 panic("unexpected proj mode at ASM");
5567 return new_r_Proj(new_pred, mode, pos);
5571 * Transform and potentially renumber Proj nodes.
5573 static ir_node *gen_Proj(ir_node *node)
5575 ir_node *pred = get_Proj_pred(node);
5578 switch (get_irn_opcode(pred)) {
5580 return gen_Proj_Load(node);
5582 return gen_Proj_Store(node);
5584 return gen_Proj_ASM(node);
5586 return gen_Proj_Builtin(node);
5588 return gen_Proj_Div(node);
5590 return gen_Proj_Mod(node);
5592 return gen_Proj_CopyB(node);
5594 return gen_Proj_be_SubSP(node);
5596 return gen_Proj_be_AddSP(node);
5598 return gen_Proj_be_Call(node);
5600 proj = get_Proj_proj(node);
5602 case pn_Start_X_initial_exec: {
5603 ir_node *block = get_nodes_block(pred);
5604 ir_node *new_block = be_transform_node(block);
5605 dbg_info *dbgi = get_irn_dbg_info(node);
5606 /* we exchange the ProjX with a jump */
5607 ir_node *jump = new_rd_Jmp(dbgi, new_block);
5615 if (is_ia32_l_FloattoLL(pred)) {
5616 return gen_Proj_l_FloattoLL(node);
5618 } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
5622 ir_mode *mode = get_irn_mode(node);
5623 if (ia32_mode_needs_gp_reg(mode)) {
5624 ir_node *new_pred = be_transform_node(pred);
5625 ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
5626 get_Proj_proj(node));
5627 new_proj->node_nr = node->node_nr;
5632 return be_duplicate_node(node);
5636 * Enters all transform functions into the generic pointer
5638 static void register_transformers(void)
5640 /* first clear the generic function pointer for all ops */
5641 be_start_transform_setup();
5643 be_set_transform_function(op_Add, gen_Add);
5644 be_set_transform_function(op_And, gen_And);
5645 be_set_transform_function(op_ASM, ia32_gen_ASM);
5646 be_set_transform_function(op_be_AddSP, gen_be_AddSP);
5647 be_set_transform_function(op_be_Call, gen_be_Call);
5648 be_set_transform_function(op_be_Copy, gen_be_Copy);
5649 be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
5650 be_set_transform_function(op_be_IncSP, gen_be_IncSP);
5651 be_set_transform_function(op_be_Return, gen_be_Return);
5652 be_set_transform_function(op_be_SubSP, gen_be_SubSP);
5653 be_set_transform_function(op_Builtin, gen_Builtin);
5654 be_set_transform_function(op_Cmp, gen_Cmp);
5655 be_set_transform_function(op_Cond, gen_Cond);
5656 be_set_transform_function(op_Const, gen_Const);
5657 be_set_transform_function(op_Conv, gen_Conv);
5658 be_set_transform_function(op_CopyB, ia32_gen_CopyB);
5659 be_set_transform_function(op_Div, gen_Div);
5660 be_set_transform_function(op_Eor, gen_Eor);
5661 be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc);
5662 be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add);
5663 be_set_transform_function(op_ia32_Leave, be_duplicate_node);
5664 be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL);
5665 be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
5666 be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
5667 be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
5668 be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
5669 be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
5670 be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
5671 be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
5672 be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
5673 be_set_transform_function(op_ia32_NoReg_FP, be_duplicate_node);
5674 be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
5675 be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
5676 be_set_transform_function(op_ia32_Push, be_duplicate_node);
5677 be_set_transform_function(op_IJmp, gen_IJmp);
5678 be_set_transform_function(op_Jmp, gen_Jmp);
5679 be_set_transform_function(op_Load, gen_Load);
5680 be_set_transform_function(op_Minus, gen_Minus);
5681 be_set_transform_function(op_Mod, gen_Mod);
5682 be_set_transform_function(op_Mul, gen_Mul);
5683 be_set_transform_function(op_Mulh, gen_Mulh);
5684 be_set_transform_function(op_Mux, gen_Mux);
5685 be_set_transform_function(op_Not, gen_Not);
5686 be_set_transform_function(op_Or, gen_Or);
5687 be_set_transform_function(op_Phi, gen_Phi);
5688 be_set_transform_function(op_Proj, gen_Proj);
5689 be_set_transform_function(op_Rotl, gen_Rotl);
5690 be_set_transform_function(op_Shl, gen_Shl);
5691 be_set_transform_function(op_Shr, gen_Shr);
5692 be_set_transform_function(op_Shrs, gen_Shrs);
5693 be_set_transform_function(op_Store, gen_Store);
5694 be_set_transform_function(op_Sub, gen_Sub);
5695 be_set_transform_function(op_Switch, gen_Switch);
5696 be_set_transform_function(op_SymConst, gen_SymConst);
5697 be_set_transform_function(op_Unknown, ia32_gen_Unknown);
5699 be_set_upper_bits_clean_function(op_Mux, ia32_mux_upper_bits_clean);
5703 * Pre-transform all unknown and noreg nodes.
5705 static void ia32_pretransform_node(void)
5707 ir_graph *irg = current_ir_graph;
5708 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
5710 irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
5711 irg_data->noreg_fp = be_pre_transform_node(irg_data->noreg_fp);
5712 irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
5713 irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
5714 irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
5716 nomem = get_irg_no_mem(irg);
5717 noreg_GP = ia32_new_NoReg_gp(irg);
5721 * Post-process all calls if we are in SSE mode.
5722 * The ABI requires that the results are in st0, copy them
5723 * to a xmm register.
5725 static void postprocess_fp_call_results(void)
5729 for (i = 0, n = ARR_LEN(call_list); i < n; ++i) {
5730 ir_node *call = call_list[i];
5731 ir_type *mtp = call_types[i];
5734 for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
5735 ir_type *res_tp = get_method_res_type(mtp, j);
5736 ir_node *res, *new_res;
5739 if (! is_atomic_type(res_tp)) {
5740 /* no floating point return */
5743 res_mode = get_type_mode(res_tp);
5744 if (! mode_is_float(res_mode)) {
5745 /* no floating point return */
5749 res = be_get_Proj_for_pn(call, pn_ia32_Call_st0 + j);
5752 /* now patch the users */
5753 foreach_out_edge_safe(res, edge) {
5754 ir_node *succ = get_edge_src_irn(edge);
5757 if (be_is_Keep(succ))
5760 if (is_ia32_xStore(succ)) {
5761 /* an xStore can be patched into an vfst */
5762 dbg_info *db = get_irn_dbg_info(succ);
5763 ir_node *block = get_nodes_block(succ);
5764 ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
5765 ir_node *idx = get_irn_n(succ, n_ia32_xStore_index);
5766 ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
5767 ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
5768 ir_mode *mode = get_ia32_ls_mode(succ);
5770 ir_node *st = new_bd_ia32_fst(db, block, base, idx, mem, value, mode);
5771 //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_fst_M);
5772 set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
5773 if (is_ia32_use_frame(succ))
5774 set_ia32_use_frame(st);
5775 set_ia32_frame_ent(st, get_ia32_frame_ent(succ));
5776 set_irn_pinned(st, get_irn_pinned(succ));
5777 set_ia32_op_type(st, ia32_AddrModeD);
5779 assert((long)pn_ia32_xStore_M == (long)pn_ia32_fst_M);
5780 assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_fst_X_regular);
5781 assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_fst_X_except);
5788 if (new_res == NULL) {
5789 dbg_info *db = get_irn_dbg_info(call);
5790 ir_node *block = get_nodes_block(call);
5791 ir_node *frame = get_irg_frame(current_ir_graph);
5792 ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
5793 ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
5794 ir_node *vfst, *xld, *new_mem;
5797 /* store st(0) on stack */
5798 vfst = new_bd_ia32_fst(db, block, frame, noreg_GP, call_mem,
5800 set_ia32_op_type(vfst, ia32_AddrModeD);
5801 set_ia32_use_frame(vfst);
5803 vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_fst_M);
5805 /* load into SSE register */
5806 xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
5808 set_ia32_op_type(xld, ia32_AddrModeS);
5809 set_ia32_use_frame(xld);
5811 new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res);
5812 new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
5814 if (old_mem != NULL) {
5815 edges_reroute(old_mem, new_mem);
5819 set_irn_n(succ, get_edge_src_pos(edge), new_res);
5825 /* do the transformation */
5826 void ia32_transform_graph(ir_graph *irg)
5830 register_transformers();
5831 initial_fpcw = NULL;
5832 ia32_no_pic_adjust = 0;
5834 old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]);
5836 be_timer_push(T_HEIGHTS);
5837 ia32_heights = heights_new(irg);
5838 be_timer_pop(T_HEIGHTS);
5839 ia32_calculate_non_address_mode_nodes(irg);
5841 /* the transform phase is not safe for CSE (yet) because several nodes get
5842 * attributes set after their creation */
5843 cse_last = get_opt_cse();
5846 call_list = NEW_ARR_F(ir_node *, 0);
5847 call_types = NEW_ARR_F(ir_type *, 0);
5848 be_transform_graph(irg, ia32_pretransform_node);
5850 if (ia32_cg_config.use_sse2)
5851 postprocess_fp_call_results();
5852 DEL_ARR_F(call_types);
5853 DEL_ARR_F(call_list);
5855 set_opt_cse(cse_last);
5857 ia32_free_non_address_mode_nodes();
5858 heights_free(ia32_heights);
5859 ia32_heights = NULL;
5862 void ia32_init_transform(void)
5864 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");