2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into ia32-Firm.
23 * @author Christian Wuerdig, Matthias Braun
34 #include "irgraph_t.h"
39 #include "iredges_t.h"
50 #include "../benode_t.h"
51 #include "../besched.h"
53 #include "../beutil.h"
54 #include "../beirg_t.h"
55 #include "../betranshlp.h"
57 #include "bearch_ia32_t.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_transform.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_dbg_stat.h"
63 #include "ia32_optimize.h"
64 #include "ia32_util.h"
66 #include "gen_ia32_regalloc_if.h"
68 #define SFP_SIGN "0x80000000"
69 #define DFP_SIGN "0x8000000000000000"
70 #define SFP_ABS "0x7FFFFFFF"
71 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
73 #define TP_SFP_SIGN "ia32_sfp_sign"
74 #define TP_DFP_SIGN "ia32_dfp_sign"
75 #define TP_SFP_ABS "ia32_sfp_abs"
76 #define TP_DFP_ABS "ia32_dfp_abs"
78 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
79 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
80 #define ENT_SFP_ABS "IA32_SFP_ABS"
81 #define ENT_DFP_ABS "IA32_DFP_ABS"
83 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
84 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
86 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
88 /** hold the current code generator during transformation */
89 static ia32_code_gen_t *env_cg = NULL;
91 extern ir_op *get_op_Mulh(void);
93 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
94 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
95 ir_node *op2, ir_node *mem);
97 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
98 ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
99 ir_node *op2, ir_node *mem, ir_node *fpcw);
101 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *op,
105 /****************************************************************************************************
107 * | | | | / _| | | (_)
108 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
109 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
110 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
111 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
113 ****************************************************************************************************/
115 static ir_node *try_create_Immediate(ir_node *node,
116 char immediate_constraint_type);
118 static ir_node *create_immediate_or_transform(ir_node *node,
119 char immediate_constraint_type);
122 * Return true if a mode can be stored in the GP register set
124 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
125 if(mode == mode_fpcw)
127 return mode_is_int(mode) || mode_is_character(mode)
128 || mode_is_reference(mode) || mode == mode_b;
132 * Returns 1 if irn is a Const representing 0, 0 otherwise
134 static INLINE int is_ia32_Const_0(ir_node *irn) {
135 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
136 && tarval_is_null(get_ia32_Immop_tarval(irn));
140 * Returns 1 if irn is a Const representing 1, 0 otherwise
142 static INLINE int is_ia32_Const_1(ir_node *irn) {
143 return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
144 && tarval_is_one(get_ia32_Immop_tarval(irn));
148 * Collects all Projs of a node into the node array. Index is the projnum.
149 * BEWARE: The caller has to assure the appropriate array size!
151 static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
152 const ir_edge_t *edge;
153 assert(get_irn_mode(irn) == mode_T && "need mode_T");
155 memset(projs, 0, size * sizeof(projs[0]));
157 foreach_out_edge(irn, edge) {
158 ir_node *proj = get_edge_src_irn(edge);
159 int proj_proj = get_Proj_proj(proj);
160 assert(proj_proj < size);
161 projs[proj_proj] = proj;
166 * Renumbers the proj having pn_old in the array tp pn_new
167 * and removes the proj from the array.
169 static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
170 fprintf(stderr, "Warning: renumber_Proj used!\n");
172 set_Proj_proj(projs[pn_old], pn_new);
173 projs[pn_old] = NULL;
178 * creates a unique ident by adding a number to a tag
180 * @param tag the tag string, must contain a %d if a number
183 static ident *unique_id(const char *tag)
185 static unsigned id = 0;
188 snprintf(str, sizeof(str), tag, ++id);
189 return new_id_from_str(str);
193 * Get a primitive type for a mode.
195 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
197 pmap_entry *e = pmap_find(types, mode);
202 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
203 res = new_type_primitive(new_id_from_str(buf), mode);
204 set_type_alignment_bytes(res, 16);
205 pmap_insert(types, mode, res);
213 * Get an entity that is initialized with a tarval
215 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
217 tarval *tv = get_Const_tarval(cnst);
218 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
223 ir_mode *mode = get_irn_mode(cnst);
224 ir_type *tp = get_Const_type(cnst);
225 if (tp == firm_unknown_type)
226 tp = get_prim_type(cg->isa->types, mode);
228 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
230 set_entity_ld_ident(res, get_entity_ident(res));
231 set_entity_visibility(res, visibility_local);
232 set_entity_variability(res, variability_constant);
233 set_entity_allocation(res, allocation_static);
235 /* we create a new entity here: It's initialization must resist on the
237 rem = current_ir_graph;
238 current_ir_graph = get_const_code_irg();
239 set_atomic_ent_value(res, new_Const_type(tv, tp));
240 current_ir_graph = rem;
242 pmap_insert(cg->isa->tv_ent, tv, res);
250 static int is_Const_0(ir_node *node) {
254 return classify_Const(node) == CNST_NULL;
257 static int is_Const_1(ir_node *node) {
261 return classify_Const(node) == CNST_ONE;
265 * Transforms a Const.
267 static ir_node *gen_Const(ir_node *node) {
268 ir_graph *irg = current_ir_graph;
269 ir_node *block = be_transform_node(get_nodes_block(node));
270 dbg_info *dbgi = get_irn_dbg_info(node);
271 ir_mode *mode = get_irn_mode(node);
273 if (mode_is_float(mode)) {
275 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
276 ir_node *nomem = new_NoMem();
280 if (! USE_SSE2(env_cg)) {
281 cnst_classify_t clss = classify_Const(node);
283 if (clss == CNST_NULL) {
284 load = new_rd_ia32_vfldz(dbgi, irg, block);
286 } else if (clss == CNST_ONE) {
287 load = new_rd_ia32_vfld1(dbgi, irg, block);
290 floatent = get_entity_for_tv(env_cg, node);
292 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
293 set_ia32_op_type(load, ia32_AddrModeS);
294 set_ia32_am_flavour(load, ia32_am_N);
295 set_ia32_am_sc(load, floatent);
296 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
297 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
299 set_ia32_ls_mode(load, mode);
301 floatent = get_entity_for_tv(env_cg, node);
303 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
304 set_ia32_op_type(load, ia32_AddrModeS);
305 set_ia32_am_flavour(load, ia32_am_N);
306 set_ia32_am_sc(load, floatent);
307 set_ia32_ls_mode(load, mode);
308 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
310 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
313 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
315 /* Const Nodes before the initial IncSP are a bad idea, because
316 * they could be spilled and we have no SP ready at that point yet.
317 * So add a dependency to the initial frame pointer calculation to
318 * avoid that situation.
320 if (get_irg_start_block(irg) == block) {
321 add_irn_dep(load, get_irg_frame(irg));
324 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
327 ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
330 if (get_irg_start_block(irg) == block) {
331 add_irn_dep(cnst, get_irg_frame(irg));
334 set_ia32_Const_attr(cnst, node);
335 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
340 return new_r_Bad(irg);
344 * Transforms a SymConst.
346 static ir_node *gen_SymConst(ir_node *node) {
347 ir_graph *irg = current_ir_graph;
348 ir_node *block = be_transform_node(get_nodes_block(node));
349 dbg_info *dbgi = get_irn_dbg_info(node);
350 ir_mode *mode = get_irn_mode(node);
353 if (mode_is_float(mode)) {
354 if (USE_SSE2(env_cg))
355 cnst = new_rd_ia32_xConst(dbgi, irg, block);
357 cnst = new_rd_ia32_vfConst(dbgi, irg, block);
358 //set_ia32_ls_mode(cnst, mode);
359 set_ia32_ls_mode(cnst, mode_E);
361 cnst = new_rd_ia32_Const(dbgi, irg, block);
364 /* Const Nodes before the initial IncSP are a bad idea, because
365 * they could be spilled and we have no SP ready at that point yet
367 if (get_irg_start_block(irg) == block) {
368 add_irn_dep(cnst, get_irg_frame(irg));
371 set_ia32_Const_attr(cnst, node);
372 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
377 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
378 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
379 static const struct {
381 const char *ent_name;
382 const char *cnst_str;
383 } names [ia32_known_const_max] = {
384 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
385 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
386 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
387 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
406 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
407 tp = new_type_primitive(new_id_from_str(tp_name), mode);
408 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
410 set_entity_ld_ident(ent, get_entity_ident(ent));
411 set_entity_visibility(ent, visibility_local);
412 set_entity_variability(ent, variability_constant);
413 set_entity_allocation(ent, allocation_static);
415 /* we create a new entity here: It's initialization must resist on the
417 rem = current_ir_graph;
418 current_ir_graph = get_const_code_irg();
419 cnst = new_Const(mode, tv);
420 current_ir_graph = rem;
422 set_atomic_ent_value(ent, cnst);
424 /* cache the entry */
425 ent_cache[kct] = ent;
428 return ent_cache[kct];
433 * Prints the old node name on cg obst and returns a pointer to it.
435 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
436 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
438 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
439 obstack_1grow(isa->name_obst, 0);
440 return obstack_finish(isa->name_obst);
444 /* determine if one operator is an Imm */
445 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
447 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
449 return is_ia32_Cnst(op2) ? op2 : NULL;
453 /* determine if one operator is not an Imm */
454 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
455 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
458 static void fold_immediate(ir_node *node, int in1, int in2) {
462 if (!(env_cg->opt & IA32_OPT_IMMOPS))
465 left = get_irn_n(node, in1);
466 right = get_irn_n(node, in2);
467 if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
468 /* we can only set right operand to immediate */
469 if(!is_ia32_commutative(node))
471 /* exchange left/right */
472 set_irn_n(node, in1, right);
473 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
474 copy_ia32_Immop_attr(node, left);
475 } else if(is_ia32_Cnst(right)) {
476 set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
477 copy_ia32_Immop_attr(node, right);
482 clear_ia32_commutative(node);
483 set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
484 get_ia32_am_arity(node));
488 * Construct a standard binary operation, set AM and immediate if required.
490 * @param op1 The first operand
491 * @param op2 The second operand
492 * @param func The node constructor function
493 * @return The constructed ia32 node.
495 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
496 construct_binop_func *func, int commutative)
498 ir_node *block = be_transform_node(get_nodes_block(node));
499 ir_graph *irg = current_ir_graph;
500 dbg_info *dbgi = get_irn_dbg_info(node);
501 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
502 ir_node *nomem = new_NoMem();
505 ir_node *new_op1 = be_transform_node(op1);
506 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
507 if (is_ia32_Immediate(new_op2)) {
511 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
512 if (func == new_rd_ia32_IMul) {
513 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
515 set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
518 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
520 set_ia32_commutative(new_node);
527 * Construct a standard binary operation, set AM and immediate if required.
529 * @param op1 The first operand
530 * @param op2 The second operand
531 * @param func The node constructor function
532 * @return The constructed ia32 node.
534 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
535 construct_binop_func *func)
537 ir_node *block = be_transform_node(get_nodes_block(node));
538 ir_node *new_op1 = be_transform_node(op1);
539 ir_node *new_op2 = be_transform_node(op2);
540 ir_node *new_node = NULL;
541 dbg_info *dbgi = get_irn_dbg_info(node);
542 ir_graph *irg = current_ir_graph;
543 ir_mode *mode = get_irn_mode(node);
544 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
545 ir_node *nomem = new_NoMem();
547 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
549 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
550 if (is_op_commutative(get_irn_op(node))) {
551 set_ia32_commutative(new_node);
553 set_ia32_ls_mode(new_node, mode);
555 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
561 * Construct a standard binary operation, set AM and immediate if required.
563 * @param op1 The first operand
564 * @param op2 The second operand
565 * @param func The node constructor function
566 * @return The constructed ia32 node.
568 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
569 construct_binop_float_func *func)
571 ir_node *block = be_transform_node(get_nodes_block(node));
572 ir_node *new_op1 = be_transform_node(op1);
573 ir_node *new_op2 = be_transform_node(op2);
574 ir_node *new_node = NULL;
575 dbg_info *dbgi = get_irn_dbg_info(node);
576 ir_graph *irg = current_ir_graph;
577 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
578 ir_node *nomem = new_NoMem();
579 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
580 &ia32_fp_cw_regs[REG_FPCW]);
582 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
584 set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
585 if (is_op_commutative(get_irn_op(node))) {
586 set_ia32_commutative(new_node);
589 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
595 * Construct a shift/rotate binary operation, sets AM and immediate if required.
597 * @param op1 The first operand
598 * @param op2 The second operand
599 * @param func The node constructor function
600 * @return The constructed ia32 node.
602 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
603 construct_binop_func *func)
605 ir_node *block = be_transform_node(get_nodes_block(node));
606 ir_node *new_op1 = be_transform_node(op1);
608 ir_node *new_op = NULL;
609 dbg_info *dbgi = get_irn_dbg_info(node);
610 ir_graph *irg = current_ir_graph;
611 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
612 ir_node *nomem = new_NoMem();
614 assert(! mode_is_float(get_irn_mode(node))
615 && "Shift/Rotate with float not supported");
617 new_op2 = create_immediate_or_transform(op2, 'N');
619 new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
622 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
624 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
626 set_ia32_emit_cl(new_op);
633 * Construct a standard unary operation, set AM and immediate if required.
635 * @param op The operand
636 * @param func The node constructor function
637 * @return The constructed ia32 node.
639 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
641 ir_node *block = be_transform_node(get_nodes_block(node));
642 ir_node *new_op = be_transform_node(op);
643 ir_node *new_node = NULL;
644 ir_graph *irg = current_ir_graph;
645 dbg_info *dbgi = get_irn_dbg_info(node);
646 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
647 ir_node *nomem = new_NoMem();
649 new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
650 DB((dbg, LEVEL_1, "INT unop ..."));
651 set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
653 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
659 * Creates an ia32 Add.
661 * @return the created ia32 Add node
663 static ir_node *gen_Add(ir_node *node) {
664 ir_node *block = be_transform_node(get_nodes_block(node));
665 ir_node *op1 = get_Add_left(node);
666 ir_node *new_op1 = be_transform_node(op1);
667 ir_node *op2 = get_Add_right(node);
668 ir_node *new_op2 = be_transform_node(op2);
669 ir_node *new_op = NULL;
670 ir_graph *irg = current_ir_graph;
671 dbg_info *dbgi = get_irn_dbg_info(node);
672 ir_mode *mode = get_irn_mode(node);
673 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
674 ir_node *nomem = new_NoMem();
675 ir_node *expr_op, *imm_op;
677 /* Check if immediate optimization is on and */
678 /* if it's an operation with immediate. */
679 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
680 expr_op = get_expr_op(new_op1, new_op2);
682 assert((expr_op || imm_op) && "invalid operands");
684 if (mode_is_float(mode)) {
685 if (USE_SSE2(env_cg))
686 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
688 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
693 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
694 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
696 /* No expr_op means, that we have two const - one symconst and */
697 /* one tarval or another symconst - because this case is not */
698 /* covered by constant folding */
699 /* We need to check for: */
700 /* 1) symconst + const -> becomes a LEA */
701 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
702 /* linker doesn't support two symconsts */
704 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
705 /* this is the 2nd case */
706 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
707 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
708 set_ia32_am_flavour(new_op, ia32_am_B);
709 set_ia32_op_type(new_op, ia32_AddrModeS);
711 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
712 } else if (tp1 == ia32_ImmSymConst) {
713 tarval *tv = get_ia32_Immop_tarval(new_op2);
714 long offs = get_tarval_long(tv);
716 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
717 add_irn_dep(new_op, get_irg_frame(irg));
718 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
720 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
721 add_ia32_am_offs_int(new_op, offs);
722 set_ia32_am_flavour(new_op, ia32_am_OB);
723 set_ia32_op_type(new_op, ia32_AddrModeS);
724 } else if (tp2 == ia32_ImmSymConst) {
725 tarval *tv = get_ia32_Immop_tarval(new_op1);
726 long offs = get_tarval_long(tv);
728 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
729 add_irn_dep(new_op, get_irg_frame(irg));
730 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
732 add_ia32_am_offs_int(new_op, offs);
733 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
734 set_ia32_am_flavour(new_op, ia32_am_OB);
735 set_ia32_op_type(new_op, ia32_AddrModeS);
737 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
738 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
739 tarval *restv = tarval_add(tv1, tv2);
741 DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
743 new_op = new_rd_ia32_Const(dbgi, irg, block);
744 set_ia32_Const_tarval(new_op, restv);
745 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
748 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
751 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
752 tarval_classification_t class_tv, class_negtv;
753 tarval *tv = get_ia32_Immop_tarval(imm_op);
755 /* optimize tarvals */
756 class_tv = classify_tarval(tv);
757 class_negtv = classify_tarval(tarval_neg(tv));
759 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
760 DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
761 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
762 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
764 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
765 DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
766 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
767 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
773 /* This is a normal add */
774 new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
777 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
778 set_ia32_commutative(new_op);
780 fold_immediate(new_op, 2, 3);
782 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
788 * Creates an ia32 Mul.
790 * @return the created ia32 Mul node
792 static ir_node *gen_Mul(ir_node *node) {
793 ir_node *op1 = get_Mul_left(node);
794 ir_node *op2 = get_Mul_right(node);
795 ir_mode *mode = get_irn_mode(node);
797 if (mode_is_float(mode)) {
798 if (USE_SSE2(env_cg))
799 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
801 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
805 for the lower 32bit of the result it doesn't matter whether we use
806 signed or unsigned multiplication so we use IMul as it has fewer
809 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
813 * Creates an ia32 Mulh.
814 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
815 * this result while Mul returns the lower 32 bit.
817 * @return the created ia32 Mulh node
819 static ir_node *gen_Mulh(ir_node *node) {
820 ir_node *block = be_transform_node(get_nodes_block(node));
821 ir_node *op1 = get_irn_n(node, 0);
822 ir_node *new_op1 = be_transform_node(op1);
823 ir_node *op2 = get_irn_n(node, 1);
824 ir_node *new_op2 = be_transform_node(op2);
825 ir_graph *irg = current_ir_graph;
826 dbg_info *dbgi = get_irn_dbg_info(node);
827 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
828 ir_mode *mode = get_irn_mode(node);
829 ir_node *proj_EDX, *res;
831 assert(!mode_is_float(mode) && "Mulh with float not supported");
832 if (mode_is_signed(mode)) {
833 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
834 new_op2, new_NoMem());
836 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
840 set_ia32_commutative(res);
841 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
843 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
851 * Creates an ia32 And.
853 * @return The created ia32 And node
855 static ir_node *gen_And(ir_node *node) {
856 ir_node *op1 = get_And_left(node);
857 ir_node *op2 = get_And_right(node);
859 assert (! mode_is_float(get_irn_mode(node)));
860 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
866 * Creates an ia32 Or.
868 * @return The created ia32 Or node
870 static ir_node *gen_Or(ir_node *node) {
871 ir_node *op1 = get_Or_left(node);
872 ir_node *op2 = get_Or_right(node);
874 assert (! mode_is_float(get_irn_mode(node)));
875 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
881 * Creates an ia32 Eor.
883 * @return The created ia32 Eor node
885 static ir_node *gen_Eor(ir_node *node) {
886 ir_node *op1 = get_Eor_left(node);
887 ir_node *op2 = get_Eor_right(node);
889 assert(! mode_is_float(get_irn_mode(node)));
890 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
895 * Creates an ia32 Sub.
897 * @return The created ia32 Sub node
899 static ir_node *gen_Sub(ir_node *node) {
900 ir_node *block = be_transform_node(get_nodes_block(node));
901 ir_node *op1 = get_Sub_left(node);
902 ir_node *new_op1 = be_transform_node(op1);
903 ir_node *op2 = get_Sub_right(node);
904 ir_node *new_op2 = be_transform_node(op2);
905 ir_node *new_op = NULL;
906 ir_graph *irg = current_ir_graph;
907 dbg_info *dbgi = get_irn_dbg_info(node);
908 ir_mode *mode = get_irn_mode(node);
909 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
910 ir_node *nomem = new_NoMem();
911 ir_node *expr_op, *imm_op;
913 /* Check if immediate optimization is on and */
914 /* if it's an operation with immediate. */
915 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
916 expr_op = get_expr_op(new_op1, new_op2);
918 assert((expr_op || imm_op) && "invalid operands");
920 if (mode_is_float(mode)) {
921 if (USE_SSE2(env_cg))
922 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
924 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
929 ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
930 ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
932 /* No expr_op means, that we have two const - one symconst and */
933 /* one tarval or another symconst - because this case is not */
934 /* covered by constant folding */
935 /* We need to check for: */
936 /* 1) symconst - const -> becomes a LEA */
937 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
938 /* linker doesn't support two symconsts */
939 if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
940 /* this is the 2nd case */
941 new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
942 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
943 set_ia32_am_sc_sign(new_op);
944 set_ia32_am_flavour(new_op, ia32_am_B);
946 DBG_OPT_LEA3(op1, op2, node, new_op);
947 } else if (tp1 == ia32_ImmSymConst) {
948 tarval *tv = get_ia32_Immop_tarval(new_op2);
949 long offs = get_tarval_long(tv);
951 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
952 add_irn_dep(new_op, get_irg_frame(irg));
953 DBG_OPT_LEA3(op1, op2, node, new_op);
955 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
956 add_ia32_am_offs_int(new_op, -offs);
957 set_ia32_am_flavour(new_op, ia32_am_OB);
958 set_ia32_op_type(new_op, ia32_AddrModeS);
959 } else if (tp2 == ia32_ImmSymConst) {
960 tarval *tv = get_ia32_Immop_tarval(new_op1);
961 long offs = get_tarval_long(tv);
963 new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
964 add_irn_dep(new_op, get_irg_frame(irg));
965 DBG_OPT_LEA3(op1, op2, node, new_op);
967 add_ia32_am_offs_int(new_op, offs);
968 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
969 set_ia32_am_sc_sign(new_op);
970 set_ia32_am_flavour(new_op, ia32_am_OB);
971 set_ia32_op_type(new_op, ia32_AddrModeS);
973 tarval *tv1 = get_ia32_Immop_tarval(new_op1);
974 tarval *tv2 = get_ia32_Immop_tarval(new_op2);
975 tarval *restv = tarval_sub(tv1, tv2);
977 DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
979 new_op = new_rd_ia32_Const(dbgi, irg, block);
980 set_ia32_Const_tarval(new_op, restv);
981 DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
984 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
987 if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
988 tarval_classification_t class_tv, class_negtv;
989 tarval *tv = get_ia32_Immop_tarval(imm_op);
991 /* optimize tarvals */
992 class_tv = classify_tarval(tv);
993 class_negtv = classify_tarval(tarval_neg(tv));
995 if (class_tv == TV_CLASSIFY_ONE) {
996 DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
997 new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
998 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1000 } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
1001 DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
1002 new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
1003 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1009 /* This is a normal sub */
1010 new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1012 /* set AM support */
1013 set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
1015 fold_immediate(new_op, 2, 3);
1017 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1025 * Generates an ia32 DivMod with additional infrastructure for the
1026 * register allocator if needed.
1028 * @param dividend -no comment- :)
1029 * @param divisor -no comment- :)
1030 * @param dm_flav flavour_Div/Mod/DivMod
1031 * @return The created ia32 DivMod node
1033 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1034 ir_node *divisor, ia32_op_flavour_t dm_flav)
1036 ir_node *block = be_transform_node(get_nodes_block(node));
1037 ir_node *new_dividend = be_transform_node(dividend);
1038 ir_node *new_divisor = be_transform_node(divisor);
1039 ir_graph *irg = current_ir_graph;
1040 dbg_info *dbgi = get_irn_dbg_info(node);
1041 ir_mode *mode = get_irn_mode(node);
1042 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1043 ir_node *res, *proj_div, *proj_mod;
1044 ir_node *sign_extension;
1045 ir_node *mem, *new_mem;
1046 ir_node *projs[pn_DivMod_max];
1049 ia32_collect_Projs(node, projs, pn_DivMod_max);
1051 proj_div = proj_mod = NULL;
1055 mem = get_Div_mem(node);
1056 mode = get_Div_resmode(node);
1057 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1058 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1061 mem = get_Mod_mem(node);
1062 mode = get_Mod_resmode(node);
1063 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1064 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1066 case flavour_DivMod:
1067 mem = get_DivMod_mem(node);
1068 mode = get_DivMod_resmode(node);
1069 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1070 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1071 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1074 panic("invalid divmod flavour!");
1076 new_mem = be_transform_node(mem);
1078 if (mode_is_signed(mode)) {
1079 /* in signed mode, we need to sign extend the dividend */
1080 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend);
1082 sign_extension = new_rd_ia32_Const(dbgi, irg, block);
1083 set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
1085 add_irn_dep(sign_extension, get_irg_frame(irg));
1088 if (mode_is_signed(mode)) {
1089 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
1090 sign_extension, new_divisor, new_mem, dm_flav);
1092 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
1093 sign_extension, new_divisor, new_mem, dm_flav);
1096 set_ia32_exc_label(res, has_exc);
1097 set_irn_pinned(res, get_irn_pinned(node));
1098 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1100 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1107 * Wrapper for generate_DivMod. Sets flavour_Mod.
1110 static ir_node *gen_Mod(ir_node *node) {
1111 return generate_DivMod(node, get_Mod_left(node),
1112 get_Mod_right(node), flavour_Mod);
1116 * Wrapper for generate_DivMod. Sets flavour_Div.
1119 static ir_node *gen_Div(ir_node *node) {
1120 return generate_DivMod(node, get_Div_left(node),
1121 get_Div_right(node), flavour_Div);
1125 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1127 static ir_node *gen_DivMod(ir_node *node) {
1128 return generate_DivMod(node, get_DivMod_left(node),
1129 get_DivMod_right(node), flavour_DivMod);
1135 * Creates an ia32 floating Div.
1137 * @return The created ia32 xDiv node
1139 static ir_node *gen_Quot(ir_node *node) {
1140 ir_node *block = be_transform_node(get_nodes_block(node));
1141 ir_node *op1 = get_Quot_left(node);
1142 ir_node *new_op1 = be_transform_node(op1);
1143 ir_node *op2 = get_Quot_right(node);
1144 ir_node *new_op2 = be_transform_node(op2);
1145 ir_graph *irg = current_ir_graph;
1146 dbg_info *dbgi = get_irn_dbg_info(node);
1147 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1148 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1151 if (USE_SSE2(env_cg)) {
1152 ir_mode *mode = get_irn_mode(op1);
1153 if (is_ia32_xConst(new_op2)) {
1154 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
1155 set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
1156 copy_ia32_Immop_attr(new_op, new_op2);
1158 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
1159 // Matze: disabled for now, spillslot coalescer fails
1160 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1162 set_ia32_ls_mode(new_op, mode);
1164 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
1165 &ia32_fp_cw_regs[REG_FPCW]);
1166 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
1167 new_op2, nomem, fpcw);
1168 // Matze: disabled for now (spillslot coalescer fails)
1169 //set_ia32_am_support(new_op, ia32_am_Source | ia32_am_binary);
1171 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1177 * Creates an ia32 Shl.
1179 * @return The created ia32 Shl node
1181 static ir_node *gen_Shl(ir_node *node) {
1182 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1189 * Creates an ia32 Shr.
1191 * @return The created ia32 Shr node
1193 static ir_node *gen_Shr(ir_node *node) {
1194 return gen_shift_binop(node, get_Shr_left(node),
1195 get_Shr_right(node), new_rd_ia32_Shr);
1201 * Creates an ia32 Sar.
1203 * @return The created ia32 Shrs node
1205 static ir_node *gen_Shrs(ir_node *node) {
1206 ir_node *left = get_Shrs_left(node);
1207 ir_node *right = get_Shrs_right(node);
1208 if(is_Const(right) && get_irn_mode(left) == mode_Is) {
1209 tarval *tv = get_Const_tarval(right);
1210 long val = get_tarval_long(tv);
1212 /* this is a sign extension */
1213 ir_graph *irg = current_ir_graph;
1214 dbg_info *dbgi = get_irn_dbg_info(node);
1215 ir_node *block = be_transform_node(get_nodes_block(node));
1217 ir_node *new_op = be_transform_node(op);
1219 return new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1223 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1229 * Creates an ia32 RotL.
1231 * @param op1 The first operator
1232 * @param op2 The second operator
1233 * @return The created ia32 RotL node
1235 static ir_node *gen_RotL(ir_node *node,
1236 ir_node *op1, ir_node *op2) {
1237 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1243 * Creates an ia32 RotR.
1244 * NOTE: There is no RotR with immediate because this would always be a RotL
1245 * "imm-mode_size_bits" which can be pre-calculated.
1247 * @param op1 The first operator
1248 * @param op2 The second operator
1249 * @return The created ia32 RotR node
1251 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1253 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1259 * Creates an ia32 RotR or RotL (depending on the found pattern).
1261 * @return The created ia32 RotL or RotR node
1263 static ir_node *gen_Rot(ir_node *node) {
1264 ir_node *rotate = NULL;
1265 ir_node *op1 = get_Rot_left(node);
1266 ir_node *op2 = get_Rot_right(node);
1268 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1269 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1270 that means we can create a RotR instead of an Add and a RotL */
1272 if (get_irn_op(op2) == op_Add) {
1274 ir_node *left = get_Add_left(add);
1275 ir_node *right = get_Add_right(add);
1276 if (is_Const(right)) {
1277 tarval *tv = get_Const_tarval(right);
1278 ir_mode *mode = get_irn_mode(node);
1279 long bits = get_mode_size_bits(mode);
1281 if (get_irn_op(left) == op_Minus &&
1282 tarval_is_long(tv) &&
1283 get_tarval_long(tv) == bits)
1285 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1286 rotate = gen_RotR(node, op1, get_Minus_op(left));
1291 if (rotate == NULL) {
1292 rotate = gen_RotL(node, op1, op2);
1301 * Transforms a Minus node.
1303 * @param op The Minus operand
1304 * @return The created ia32 Minus node
1306 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1307 ir_node *block = be_transform_node(get_nodes_block(node));
1308 ir_graph *irg = current_ir_graph;
1309 dbg_info *dbgi = get_irn_dbg_info(node);
1310 ir_mode *mode = get_irn_mode(node);
1315 if (mode_is_float(mode)) {
1316 ir_node *new_op = be_transform_node(op);
1317 if (USE_SSE2(env_cg)) {
1318 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1319 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1320 ir_node *nomem = new_rd_NoMem(irg);
1322 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1324 size = get_mode_size_bits(mode);
1325 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1327 set_ia32_am_sc(res, ent);
1328 set_ia32_op_type(res, ia32_AddrModeS);
1329 set_ia32_ls_mode(res, mode);
1331 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1334 res = gen_unop(node, op, new_rd_ia32_Neg);
1337 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1343 * Transforms a Minus node.
1345 * @return The created ia32 Minus node
1347 static ir_node *gen_Minus(ir_node *node) {
1348 return gen_Minus_ex(node, get_Minus_op(node));
1351 static ir_node *gen_bin_Not(ir_node *node)
1353 ir_graph *irg = current_ir_graph;
1354 dbg_info *dbgi = get_irn_dbg_info(node);
1355 ir_node *block = be_transform_node(get_nodes_block(node));
1356 ir_node *op = get_Not_op(node);
1357 ir_node *new_op = be_transform_node(op);
1358 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1359 ir_node *nomem = new_NoMem();
1360 ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
1361 arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
1363 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
1367 * Transforms a Not node.
1369 * @return The created ia32 Not node
1371 static ir_node *gen_Not(ir_node *node) {
1372 ir_node *op = get_Not_op(node);
1373 ir_mode *mode = get_irn_mode(node);
1375 if(mode == mode_b) {
1376 return gen_bin_Not(node);
1379 assert (! mode_is_float(get_irn_mode(node)));
1380 return gen_unop(node, op, new_rd_ia32_Not);
1386 * Transforms an Abs node.
1388 * @return The created ia32 Abs node
1390 static ir_node *gen_Abs(ir_node *node) {
1391 ir_node *block = be_transform_node(get_nodes_block(node));
1392 ir_node *op = get_Abs_op(node);
1393 ir_node *new_op = be_transform_node(op);
1394 ir_graph *irg = current_ir_graph;
1395 dbg_info *dbgi = get_irn_dbg_info(node);
1396 ir_mode *mode = get_irn_mode(node);
1397 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1398 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1399 ir_node *nomem = new_NoMem();
1404 if (mode_is_float(mode)) {
1405 if (USE_SSE2(env_cg)) {
1406 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
1408 size = get_mode_size_bits(mode);
1409 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1411 set_ia32_am_sc(res, ent);
1413 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1415 set_ia32_op_type(res, ia32_AddrModeS);
1416 set_ia32_ls_mode(res, mode);
1419 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1420 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1424 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op);
1425 SET_IA32_ORIG_NODE(sign_extension,
1426 ia32_get_old_node_name(env_cg, node));
1428 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
1429 sign_extension, nomem);
1430 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1432 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
1433 sign_extension, nomem);
1434 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1443 * Transforms a Load.
1445 * @return the created ia32 Load node
1447 static ir_node *gen_Load(ir_node *node) {
1448 ir_node *block = be_transform_node(get_nodes_block(node));
1449 ir_node *ptr = get_Load_ptr(node);
1450 ir_node *new_ptr = be_transform_node(ptr);
1451 ir_node *mem = get_Load_mem(node);
1452 ir_node *new_mem = be_transform_node(mem);
1453 ir_graph *irg = current_ir_graph;
1454 dbg_info *dbgi = get_irn_dbg_info(node);
1455 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1456 ir_mode *mode = get_Load_mode(node);
1458 ir_node *lptr = new_ptr;
1461 ia32_am_flavour_t am_flav = ia32_am_B;
1463 /* address might be a constant (symconst or absolute address) */
1464 if (is_ia32_Const(new_ptr)) {
1469 if (mode_is_float(mode)) {
1470 if (USE_SSE2(env_cg)) {
1471 new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
1472 res_mode = mode_xmm;
1474 new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
1475 res_mode = mode_vfp;
1478 new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
1482 /* base is a constant address */
1484 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1485 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1486 am_flav = ia32_am_N;
1488 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1489 long offs = get_tarval_long(tv);
1491 add_ia32_am_offs_int(new_op, offs);
1492 am_flav = ia32_am_O;
1496 set_irn_pinned(new_op, get_irn_pinned(node));
1497 set_ia32_op_type(new_op, ia32_AddrModeS);
1498 set_ia32_am_flavour(new_op, am_flav);
1499 set_ia32_ls_mode(new_op, mode);
1501 /* make sure we are scheduled behind the initial IncSP/Barrier
1502 * to avoid spills being placed before it
1504 if (block == get_irg_start_block(irg)) {
1505 add_irn_dep(new_op, get_irg_frame(irg));
1508 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1509 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1517 * Transforms a Store.
1519 * @return the created ia32 Store node
1521 static ir_node *gen_Store(ir_node *node) {
1522 ir_node *block = be_transform_node(get_nodes_block(node));
1523 ir_node *ptr = get_Store_ptr(node);
1524 ir_node *new_ptr = be_transform_node(ptr);
1525 ir_node *val = get_Store_value(node);
1527 ir_node *mem = get_Store_mem(node);
1528 ir_node *new_mem = be_transform_node(mem);
1529 ir_graph *irg = current_ir_graph;
1530 dbg_info *dbgi = get_irn_dbg_info(node);
1531 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1532 ir_node *sptr = new_ptr;
1533 ir_mode *mode = get_irn_mode(val);
1536 ia32_am_flavour_t am_flav = ia32_am_B;
1538 /* address might be a constant (symconst or absolute address) */
1539 if (is_ia32_Const(new_ptr)) {
1544 if (mode_is_float(mode)) {
1545 new_val = be_transform_node(val);
1546 if (USE_SSE2(env_cg)) {
1547 new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
1550 new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
1554 new_val = create_immediate_or_transform(val, 0);
1556 if (get_mode_size_bits(mode) == 8) {
1557 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
1560 new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
1565 /* base is an constant address */
1567 if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
1568 set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
1569 am_flav = ia32_am_N;
1571 tarval *tv = get_ia32_Immop_tarval(new_ptr);
1572 long offs = get_tarval_long(tv);
1574 add_ia32_am_offs_int(new_op, offs);
1575 am_flav = ia32_am_O;
1579 set_irn_pinned(new_op, get_irn_pinned(node));
1580 set_ia32_op_type(new_op, ia32_AddrModeD);
1581 set_ia32_am_flavour(new_op, am_flav);
1582 set_ia32_ls_mode(new_op, mode);
1584 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1585 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1590 static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
1591 ir_node *cmp_left, ir_node *cmp_right)
1593 ir_node *new_cmp_left;
1594 ir_node *new_cmp_right;
1600 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1602 if(cmp_right != NULL && !is_Const_0(cmp_right))
1605 if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1606 and_left = get_And_left(cmp_left);
1607 and_right = get_And_right(cmp_left);
1609 new_cmp_left = be_transform_node(and_left);
1610 new_cmp_right = create_immediate_or_transform(and_right, 0);
1612 new_cmp_left = be_transform_node(cmp_left);
1613 new_cmp_right = be_transform_node(cmp_left);
1616 noreg = ia32_new_NoReg_gp(env_cg);
1617 nomem = new_NoMem();
1619 res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
1620 new_cmp_left, new_cmp_right, nomem, pnc);
1621 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1626 static ir_node *create_Switch(ir_node *node)
1628 ir_graph *irg = current_ir_graph;
1629 dbg_info *dbgi = get_irn_dbg_info(node);
1630 ir_node *block = be_transform_node(get_nodes_block(node));
1631 ir_node *sel = get_Cond_selector(node);
1632 ir_node *new_sel = be_transform_node(sel);
1634 int switch_min = INT_MAX;
1635 const ir_edge_t *edge;
1637 /* determine the smallest switch case value */
1638 foreach_out_edge(node, edge) {
1639 ir_node *proj = get_edge_src_irn(edge);
1640 int pn = get_Proj_proj(proj);
1645 if (switch_min != 0) {
1646 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1648 /* if smallest switch case is not 0 we need an additional sub */
1649 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1650 add_ia32_am_offs_int(new_sel, -switch_min);
1651 set_ia32_am_flavour(new_sel, ia32_am_OB);
1652 set_ia32_op_type(new_sel, ia32_AddrModeS);
1654 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1657 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1658 set_ia32_pncode(res, get_Cond_defaultProj(node));
1660 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1666 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1668 * @return The transformed node.
1670 static ir_node *gen_Cond(ir_node *node) {
1671 ir_node *block = be_transform_node(get_nodes_block(node));
1672 ir_graph *irg = current_ir_graph;
1673 dbg_info *dbgi = get_irn_dbg_info(node);
1674 ir_node *sel = get_Cond_selector(node);
1675 ir_mode *sel_mode = get_irn_mode(sel);
1676 ir_node *res = NULL;
1677 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1684 ir_node *nomem = new_NoMem();
1687 if (sel_mode != mode_b) {
1688 return create_Switch(node);
1691 if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
1692 /* it's some mode_b value not a direct comparison -> create a testjmp */
1693 res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
1694 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1698 cmp = get_Proj_pred(sel);
1699 cmp_a = get_Cmp_left(cmp);
1700 cmp_b = get_Cmp_right(cmp);
1701 cmp_mode = get_irn_mode(cmp_a);
1702 pnc = get_Proj_proj(sel);
1703 if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
1704 pnc |= ia32_pn_Cmp_Unsigned;
1707 if(mode_needs_gp_reg(cmp_mode)) {
1708 res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
1710 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1715 new_cmp_a = be_transform_node(cmp_a);
1716 new_cmp_b = create_immediate_or_transform(cmp_b, 0);
1718 if (mode_is_float(cmp_mode)) {
1719 if (USE_SSE2(env_cg)) {
1720 res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
1722 set_ia32_commutative(res);
1723 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1724 set_ia32_ls_mode(res, cmp_mode);
1726 res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
1727 set_ia32_commutative(res);
1730 assert(get_mode_size_bits(cmp_mode) == 32);
1731 res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
1732 new_cmp_a, new_cmp_b, nomem, pnc);
1733 set_ia32_commutative(res);
1734 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1737 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1745 * Transforms a CopyB node.
1747 * @return The transformed node.
1749 static ir_node *gen_CopyB(ir_node *node) {
1750 ir_node *block = be_transform_node(get_nodes_block(node));
1751 ir_node *src = get_CopyB_src(node);
1752 ir_node *new_src = be_transform_node(src);
1753 ir_node *dst = get_CopyB_dst(node);
1754 ir_node *new_dst = be_transform_node(dst);
1755 ir_node *mem = get_CopyB_mem(node);
1756 ir_node *new_mem = be_transform_node(mem);
1757 ir_node *res = NULL;
1758 ir_graph *irg = current_ir_graph;
1759 dbg_info *dbgi = get_irn_dbg_info(node);
1760 int size = get_type_size_bytes(get_CopyB_type(node));
1763 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1764 /* then we need the size explicitly in ECX. */
1765 if (size >= 32 * 4) {
1766 rem = size & 0x3; /* size % 4 */
1769 res = new_rd_ia32_Const(dbgi, irg, block);
1770 add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
1771 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1773 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
1774 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1776 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
1777 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1780 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1786 ir_node *gen_be_Copy(ir_node *node)
1788 ir_node *result = be_duplicate_node(node);
1789 ir_mode *mode = get_irn_mode(result);
1791 if (mode_needs_gp_reg(mode)) {
1792 set_irn_mode(result, mode_Iu);
1799 static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1800 dbg_info *dbgi, ir_node *block)
1802 ir_graph *irg = current_ir_graph;
1803 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1804 ir_node *nomem = new_rd_NoMem(irg);
1805 ir_node *new_cmp_left;
1806 ir_node *new_cmp_right;
1809 /* can we use a test instruction? */
1810 if(cmp_right == NULL || is_Const_0(cmp_right)) {
1811 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1812 if(is_And(cmp_left) &&
1813 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1814 ir_node *and_left = get_And_left(cmp_left);
1815 ir_node *and_right = get_And_right(cmp_left);
1817 new_cmp_left = be_transform_node(and_left);
1818 new_cmp_right = create_immediate_or_transform(and_right, 0);
1820 new_cmp_left = be_transform_node(cmp_left);
1821 new_cmp_right = be_transform_node(cmp_left);
1824 res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
1825 new_cmp_left, new_cmp_right, nomem, pnc);
1826 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1831 new_cmp_left = be_transform_node(cmp_left);
1832 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1833 res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
1834 new_cmp_left, new_cmp_right, nomem, pnc);
1839 static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
1840 ir_node *val_true, ir_node *val_false,
1841 dbg_info *dbgi, ir_node *block)
1843 ir_graph *irg = current_ir_graph;
1844 ir_node *new_val_true = be_transform_node(val_true);
1845 ir_node *new_val_false = be_transform_node(val_false);
1846 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1847 ir_node *nomem = new_NoMem();
1848 ir_node *new_cmp_left;
1849 ir_node *new_cmp_right;
1852 /* cmovs with unknowns are pointless... */
1853 if(is_Unknown(val_true)) {
1854 #ifdef DEBUG_libfirm
1855 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1857 return new_val_false;
1859 if(is_Unknown(val_false)) {
1860 #ifdef DEBUG_libfirm
1861 ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
1863 return new_val_true;
1866 /* can we use a test instruction? */
1867 if(is_Const_0(cmp_right)) {
1868 long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
1869 if(is_And(cmp_left) &&
1870 (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
1871 ir_node *and_left = get_And_left(cmp_left);
1872 ir_node *and_right = get_And_right(cmp_left);
1874 new_cmp_left = be_transform_node(and_left);
1875 new_cmp_right = create_immediate_or_transform(and_right, 0);
1877 new_cmp_left = be_transform_node(cmp_left);
1878 new_cmp_right = be_transform_node(cmp_left);
1881 res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
1882 new_cmp_left, new_cmp_right, nomem,
1883 new_val_true, new_val_false, pnc);
1884 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1889 new_cmp_left = be_transform_node(cmp_left);
1890 new_cmp_right = create_immediate_or_transform(cmp_right, 0);
1892 res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
1893 new_cmp_right, nomem, new_val_true, new_val_false,
1895 set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
1902 * Transforms a Psi node into CMov.
1904 * @return The transformed node.
1906 static ir_node *gen_Psi(ir_node *node) {
1907 ir_node *psi_true = get_Psi_val(node, 0);
1908 ir_node *psi_default = get_Psi_default(node);
1909 ia32_code_gen_t *cg = env_cg;
1910 ir_node *cond = get_Psi_cond(node, 0);
1911 ir_node *block = be_transform_node(get_nodes_block(node));
1912 dbg_info *dbgi = get_irn_dbg_info(node);
1919 assert(get_Psi_n_conds(node) == 1);
1920 assert(get_irn_mode(cond) == mode_b);
1922 if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
1923 /* a mode_b value, we have to compare it against 0 */
1925 cmp_right = new_Const_long(mode_Iu, 0);
1929 ir_node *cmp = get_Proj_pred(cond);
1931 cmp_left = get_Cmp_left(cmp);
1932 cmp_right = get_Cmp_right(cmp);
1933 cmp_mode = get_irn_mode(cmp_left);
1934 pnc = get_Proj_proj(cond);
1936 assert(!mode_is_float(cmp_mode));
1938 if (!mode_is_signed(cmp_mode)) {
1939 pnc |= ia32_pn_Cmp_Unsigned;
1943 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
1944 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1945 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
1946 pnc = get_negated_pnc(pnc, cmp_mode);
1947 new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
1949 new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
1952 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1958 * Following conversion rules apply:
1962 * 1) n bit -> m bit n > m (downscale)
1964 * 2) n bit -> m bit n == m (sign change)
1966 * 3) n bit -> m bit n < m (upscale)
1967 * a) source is signed: movsx
1968 * b) source is unsigned: and with lower bits sets
1972 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1976 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1980 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1981 * x87 is mode_E internally, conversions happen only at load and store
1982 * in non-strict semantic
1986 * Create a conversion from x87 state register to general purpose.
1988 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
1989 ir_node *block = be_transform_node(get_nodes_block(node));
1990 ir_node *op = get_Conv_op(node);
1991 ir_node *new_op = be_transform_node(op);
1992 ia32_code_gen_t *cg = env_cg;
1993 ir_graph *irg = current_ir_graph;
1994 dbg_info *dbgi = get_irn_dbg_info(node);
1995 ir_node *noreg = ia32_new_NoReg_gp(cg);
1996 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
1997 ir_node *fist, *load;
2000 fist = new_rd_ia32_vfist(dbgi, irg, block,
2001 get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
2003 set_irn_pinned(fist, op_pin_state_floats);
2004 set_ia32_use_frame(fist);
2005 set_ia32_op_type(fist, ia32_AddrModeD);
2006 set_ia32_am_flavour(fist, ia32_am_B);
2007 set_ia32_ls_mode(fist, mode_Iu);
2008 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2011 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2013 set_irn_pinned(load, op_pin_state_floats);
2014 set_ia32_use_frame(load);
2015 set_ia32_op_type(load, ia32_AddrModeS);
2016 set_ia32_am_flavour(load, ia32_am_B);
2017 set_ia32_ls_mode(load, mode_Iu);
2018 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2020 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2024 * Create a conversion from general purpose to x87 register
2026 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2027 ir_node *block = be_transform_node(get_nodes_block(node));
2028 ir_node *op = get_Conv_op(node);
2029 ir_node *new_op = be_transform_node(op);
2030 ir_graph *irg = current_ir_graph;
2031 dbg_info *dbgi = get_irn_dbg_info(node);
2032 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2033 ir_node *nomem = new_NoMem();
2034 ir_node *fild, *store;
2037 /* first convert to 32 bit if necessary */
2038 src_bits = get_mode_size_bits(src_mode);
2039 if (src_bits == 8) {
2040 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2041 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2042 set_ia32_ls_mode(new_op, src_mode);
2043 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2044 } else if (src_bits < 32) {
2045 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2046 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
2047 set_ia32_ls_mode(new_op, src_mode);
2048 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2052 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
2054 set_ia32_use_frame(store);
2055 set_ia32_op_type(store, ia32_AddrModeD);
2056 set_ia32_am_flavour(store, ia32_am_OB);
2057 set_ia32_ls_mode(store, mode_Iu);
2060 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2062 set_ia32_use_frame(fild);
2063 set_ia32_op_type(fild, ia32_AddrModeS);
2064 set_ia32_am_flavour(fild, ia32_am_OB);
2065 set_ia32_ls_mode(fild, mode_Iu);
2067 return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2070 static ir_node *create_strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
2073 ir_node *block = get_nodes_block(node);
2074 ir_graph *irg = current_ir_graph;
2075 dbg_info *dbgi = get_irn_dbg_info(node);
2076 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2077 ir_node *nomem = new_NoMem();
2078 int src_bits = get_mode_size_bits(src_mode);
2079 int tgt_bits = get_mode_size_bits(tgt_mode);
2080 ir_node *frame = get_irg_frame(irg);
2081 ir_mode *smaller_mode;
2082 ir_node *store, *load;
2085 if(src_bits <= tgt_bits)
2086 smaller_mode = src_mode;
2088 smaller_mode = tgt_mode;
2090 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
2092 set_ia32_use_frame(store);
2093 set_ia32_op_type(store, ia32_AddrModeD);
2094 set_ia32_am_flavour(store, ia32_am_OB);
2096 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2098 set_ia32_use_frame(load);
2099 set_ia32_op_type(load, ia32_AddrModeS);
2100 set_ia32_am_flavour(load, ia32_am_OB);
2102 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2107 * Transforms a Conv node.
2109 * @return The created ia32 Conv node
2111 static ir_node *gen_Conv(ir_node *node) {
2112 ir_node *block = be_transform_node(get_nodes_block(node));
2113 ir_node *op = get_Conv_op(node);
2114 ir_node *new_op = be_transform_node(op);
2115 ir_graph *irg = current_ir_graph;
2116 dbg_info *dbgi = get_irn_dbg_info(node);
2117 ir_mode *src_mode = get_irn_mode(op);
2118 ir_mode *tgt_mode = get_irn_mode(node);
2119 int src_bits = get_mode_size_bits(src_mode);
2120 int tgt_bits = get_mode_size_bits(tgt_mode);
2121 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2122 ir_node *nomem = new_rd_NoMem(irg);
2125 if (src_mode == mode_b) {
2126 assert(mode_is_int(tgt_mode));
2127 /* nothing to do, we already model bools as 0/1 ints */
2131 if (src_mode == tgt_mode) {
2132 if (get_Conv_strict(node)) {
2133 if (USE_SSE2(env_cg)) {
2134 /* when we are in SSE mode, we can kill all strict no-op conversion */
2138 /* this should be optimized already, but who knows... */
2139 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2140 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2145 if (mode_is_float(src_mode)) {
2146 /* we convert from float ... */
2147 if (mode_is_float(tgt_mode)) {
2148 if(src_mode == mode_E && tgt_mode == mode_D
2149 && !get_Conv_strict(node)) {
2150 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2155 if (USE_SSE2(env_cg)) {
2156 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2157 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2158 set_ia32_ls_mode(res, tgt_mode);
2160 // Matze: TODO what about strict convs?
2161 if(get_Conv_strict(node)) {
2162 res = create_strict_conv(src_mode, tgt_mode, new_op);
2163 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2166 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2171 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2172 if (USE_SSE2(env_cg)) {
2173 res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2174 set_ia32_ls_mode(res, src_mode);
2176 return gen_x87_fp_to_gp(node);
2180 /* we convert from int ... */
2181 if (mode_is_float(tgt_mode)) {
2183 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2184 if (USE_SSE2(env_cg)) {
2185 res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
2186 set_ia32_ls_mode(res, tgt_mode);
2187 if(src_bits == 32) {
2188 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2191 return gen_x87_gp_to_fp(node, src_mode);
2193 } else if(tgt_mode == mode_b) {
2196 res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
2198 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
2203 ir_mode *smaller_mode;
2206 if (src_bits == tgt_bits) {
2207 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2208 src_mode, tgt_mode));
2212 if (src_bits < tgt_bits) {
2213 smaller_mode = src_mode;
2214 smaller_bits = src_bits;
2216 smaller_mode = tgt_mode;
2217 smaller_bits = tgt_bits;
2220 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2221 if (smaller_bits == 8) {
2222 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
2223 set_ia32_ls_mode(res, smaller_mode);
2225 res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
2226 set_ia32_ls_mode(res, smaller_mode);
2228 set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
2232 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2238 int check_immediate_constraint(long val, char immediate_constraint_type)
2240 switch (immediate_constraint_type) {
2244 return val >= 0 && val <= 32;
2246 return val >= 0 && val <= 63;
2248 return val >= -128 && val <= 127;
2250 return val == 0xff || val == 0xffff;
2252 return val >= 0 && val <= 3;
2254 return val >= 0 && val <= 255;
2256 return val >= 0 && val <= 127;
2260 panic("Invalid immediate constraint found");
2265 ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
2268 tarval *offset = NULL;
2269 int offset_sign = 0;
2271 ir_entity *symconst_ent = NULL;
2272 int symconst_sign = 0;
2274 ir_node *cnst = NULL;
2275 ir_node *symconst = NULL;
2281 mode = get_irn_mode(node);
2282 if(!mode_is_int(mode) && !mode_is_character(mode) &&
2283 !mode_is_reference(mode)) {
2287 if(is_Minus(node)) {
2289 node = get_Minus_op(node);
2292 if(is_Const(node)) {
2295 offset_sign = minus;
2296 } else if(is_SymConst(node)) {
2299 symconst_sign = minus;
2300 } else if(is_Add(node)) {
2301 ir_node *left = get_Add_left(node);
2302 ir_node *right = get_Add_right(node);
2303 if(is_Const(left) && is_SymConst(right)) {
2306 symconst_sign = minus;
2307 offset_sign = minus;
2308 } else if(is_SymConst(left) && is_Const(right)) {
2311 symconst_sign = minus;
2312 offset_sign = minus;
2314 } else if(is_Sub(node)) {
2315 ir_node *left = get_Sub_left(node);
2316 ir_node *right = get_Sub_right(node);
2317 if(is_Const(left) && is_SymConst(right)) {
2320 symconst_sign = !minus;
2321 offset_sign = minus;
2322 } else if(is_SymConst(left) && is_Const(right)) {
2325 symconst_sign = minus;
2326 offset_sign = !minus;
2333 offset = get_Const_tarval(cnst);
2334 if(tarval_is_long(offset)) {
2335 val = get_tarval_long(offset);
2336 } else if(tarval_is_null(offset)) {
2339 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2344 if(!check_immediate_constraint(val, immediate_constraint_type))
2347 if(symconst != NULL) {
2348 if(immediate_constraint_type != 0) {
2349 /* we need full 32bits for symconsts */
2353 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2355 symconst_ent = get_SymConst_entity(symconst);
2357 if(cnst == NULL && symconst == NULL)
2360 if(offset_sign && offset != NULL) {
2361 offset = tarval_neg(offset);
2364 irg = current_ir_graph;
2365 dbgi = get_irn_dbg_info(node);
2366 block = get_irg_start_block(irg);
2367 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent, symconst_sign,
2369 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2371 /* make sure we don't schedule stuff before the barrier */
2372 add_irn_dep(res, get_irg_frame(irg));
2378 ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
2380 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2381 if (new_node == NULL) {
2382 new_node = be_transform_node(node);
2387 typedef struct constraint_t constraint_t;
2388 struct constraint_t {
2391 const arch_register_req_t **out_reqs;
2393 const arch_register_req_t *req;
2394 unsigned immediate_possible;
2395 char immediate_type;
2398 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2400 int immediate_possible = 0;
2401 char immediate_type = 0;
2402 unsigned limited = 0;
2403 const arch_register_class_t *cls = NULL;
2405 struct obstack *obst;
2406 arch_register_req_t *req;
2407 unsigned *limited_ptr;
2411 /* TODO: replace all the asserts with nice error messages */
2413 printf("Constraint: %s\n", c);
2423 assert(cls == NULL ||
2424 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2425 cls = &ia32_reg_classes[CLASS_ia32_gp];
2426 limited |= 1 << REG_EAX;
2429 assert(cls == NULL ||
2430 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2431 cls = &ia32_reg_classes[CLASS_ia32_gp];
2432 limited |= 1 << REG_EBX;
2435 assert(cls == NULL ||
2436 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2437 cls = &ia32_reg_classes[CLASS_ia32_gp];
2438 limited |= 1 << REG_ECX;
2441 assert(cls == NULL ||
2442 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2443 cls = &ia32_reg_classes[CLASS_ia32_gp];
2444 limited |= 1 << REG_EDX;
2447 assert(cls == NULL ||
2448 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2449 cls = &ia32_reg_classes[CLASS_ia32_gp];
2450 limited |= 1 << REG_EDI;
2453 assert(cls == NULL ||
2454 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2455 cls = &ia32_reg_classes[CLASS_ia32_gp];
2456 limited |= 1 << REG_ESI;
2459 case 'q': /* q means lower part of the regs only, this makes no
2460 * difference to Q for us (we only assigne whole registers) */
2461 assert(cls == NULL ||
2462 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2463 cls = &ia32_reg_classes[CLASS_ia32_gp];
2464 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2468 assert(cls == NULL ||
2469 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2470 cls = &ia32_reg_classes[CLASS_ia32_gp];
2471 limited |= 1 << REG_EAX | 1 << REG_EDX;
2474 assert(cls == NULL ||
2475 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2476 cls = &ia32_reg_classes[CLASS_ia32_gp];
2477 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2478 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2485 assert(cls == NULL);
2486 cls = &ia32_reg_classes[CLASS_ia32_gp];
2492 /* TODO: mark values so the x87 simulator knows about t and u */
2493 assert(cls == NULL);
2494 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2499 assert(cls == NULL);
2500 /* TODO: check that sse2 is supported */
2501 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2511 assert(!immediate_possible);
2512 immediate_possible = 1;
2513 immediate_type = *c;
2517 assert(!immediate_possible);
2518 immediate_possible = 1;
2522 assert(!immediate_possible && cls == NULL);
2523 immediate_possible = 1;
2524 cls = &ia32_reg_classes[CLASS_ia32_gp];
2537 assert(constraint->is_in && "can only specify same constraint "
2540 sscanf(c, "%d%n", &same_as, &p);
2547 case 'E': /* no float consts yet */
2548 case 'F': /* no float consts yet */
2549 case 's': /* makes no sense on x86 */
2550 case 'X': /* we can't support that in firm */
2554 case '<': /* no autodecrement on x86 */
2555 case '>': /* no autoincrement on x86 */
2556 case 'C': /* sse constant not supported yet */
2557 case 'G': /* 80387 constant not supported yet */
2558 case 'y': /* we don't support mmx registers yet */
2559 case 'Z': /* not available in 32 bit mode */
2560 case 'e': /* not available in 32 bit mode */
2561 assert(0 && "asm constraint not supported");
2564 assert(0 && "unknown asm constraint found");
2571 const arch_register_req_t *other_constr;
2573 assert(cls == NULL && "same as and register constraint not supported");
2574 assert(!immediate_possible && "same as and immediate constraint not "
2576 assert(same_as < constraint->n_outs && "wrong constraint number in "
2577 "same_as constraint");
2579 other_constr = constraint->out_reqs[same_as];
2581 req = obstack_alloc(obst, sizeof(req[0]));
2582 req->cls = other_constr->cls;
2583 req->type = arch_register_req_type_should_be_same;
2584 req->limited = NULL;
2585 req->other_same = pos;
2586 req->other_different = -1;
2588 /* switch constraints. This is because in firm we have same_as
2589 * constraints on the output constraints while in the gcc asm syntax
2590 * they are specified on the input constraints */
2591 constraint->req = other_constr;
2592 constraint->out_reqs[same_as] = req;
2593 constraint->immediate_possible = 0;
2597 if(immediate_possible && cls == NULL) {
2598 cls = &ia32_reg_classes[CLASS_ia32_gp];
2600 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
2601 assert(cls != NULL);
2603 if(immediate_possible) {
2604 assert(constraint->is_in
2605 && "imeediates make no sense for output constraints");
2607 /* todo: check types (no float input on 'r' constrainted in and such... */
2609 irg = current_ir_graph;
2610 obst = get_irg_obstack(irg);
2613 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
2614 limited_ptr = (unsigned*) (req+1);
2616 req = obstack_alloc(obst, sizeof(req[0]));
2618 memset(req, 0, sizeof(req[0]));
2621 req->type = arch_register_req_type_limited;
2622 *limited_ptr = limited;
2623 req->limited = limited_ptr;
2625 req->type = arch_register_req_type_normal;
2629 constraint->req = req;
2630 constraint->immediate_possible = immediate_possible;
2631 constraint->immediate_type = immediate_type;
2635 void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
2642 panic("Clobbers not supported yet");
2645 ir_node *gen_ASM(ir_node *node)
2648 ir_graph *irg = current_ir_graph;
2649 ir_node *block = be_transform_node(get_nodes_block(node));
2650 dbg_info *dbgi = get_irn_dbg_info(node);
2657 ia32_asm_attr_t *attr;
2658 const arch_register_req_t **out_reqs;
2659 const arch_register_req_t **in_reqs;
2660 struct obstack *obst;
2661 constraint_t parsed_constraint;
2663 /* transform inputs */
2664 arity = get_irn_arity(node);
2665 in = alloca(arity * sizeof(in[0]));
2666 memset(in, 0, arity * sizeof(in[0]));
2668 n_outs = get_ASM_n_output_constraints(node);
2669 n_clobbers = get_ASM_n_clobbers(node);
2670 out_arity = n_outs + n_clobbers;
2672 /* construct register constraints */
2673 obst = get_irg_obstack(irg);
2674 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
2675 parsed_constraint.out_reqs = out_reqs;
2676 parsed_constraint.n_outs = n_outs;
2677 parsed_constraint.is_in = 0;
2678 for(i = 0; i < out_arity; ++i) {
2682 const ir_asm_constraint *constraint;
2683 constraint = & get_ASM_output_constraints(node) [i];
2684 c = get_id_str(constraint->constraint);
2685 parse_asm_constraint(i, &parsed_constraint, c);
2687 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
2688 c = get_id_str(glob_id);
2689 parse_clobber(node, i, &parsed_constraint, c);
2691 out_reqs[i] = parsed_constraint.req;
2694 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
2695 parsed_constraint.is_in = 1;
2696 for(i = 0; i < arity; ++i) {
2697 const ir_asm_constraint *constraint;
2701 constraint = & get_ASM_input_constraints(node) [i];
2702 constr_id = constraint->constraint;
2703 c = get_id_str(constr_id);
2704 parse_asm_constraint(i, &parsed_constraint, c);
2705 in_reqs[i] = parsed_constraint.req;
2707 if(parsed_constraint.immediate_possible) {
2708 ir_node *pred = get_irn_n(node, i);
2709 char imm_type = parsed_constraint.immediate_type;
2710 ir_node *immediate = try_create_Immediate(pred, imm_type);
2712 if(immediate != NULL) {
2718 /* transform inputs */
2719 for(i = 0; i < arity; ++i) {
2721 ir_node *transformed;
2726 pred = get_irn_n(node, i);
2727 transformed = be_transform_node(pred);
2728 in[i] = transformed;
2731 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
2733 generic_attr = get_irn_generic_attr(res);
2734 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
2735 attr->asm_text = get_ASM_text(node);
2736 set_ia32_out_req_all(res, out_reqs);
2737 set_ia32_in_req_all(res, in_reqs);
2739 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2744 /********************************************
2747 * | |__ ___ _ __ ___ __| | ___ ___
2748 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2749 * | |_) | __/ | | | (_) | (_| | __/\__ \
2750 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2752 ********************************************/
2754 static ir_node *gen_be_StackParam(ir_node *node) {
2755 ir_node *block = be_transform_node(get_nodes_block(node));
2756 ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
2757 ir_node *new_ptr = be_transform_node(ptr);
2758 ir_node *new_op = NULL;
2759 ir_graph *irg = current_ir_graph;
2760 dbg_info *dbgi = get_irn_dbg_info(node);
2761 ir_node *nomem = new_rd_NoMem(current_ir_graph);
2762 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2763 ir_mode *load_mode = get_irn_mode(node);
2764 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2768 if (mode_is_float(load_mode)) {
2769 if (USE_SSE2(env_cg)) {
2770 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
2771 pn_res = pn_ia32_xLoad_res;
2772 proj_mode = mode_xmm;
2774 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
2775 pn_res = pn_ia32_vfld_res;
2776 proj_mode = mode_vfp;
2779 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
2780 proj_mode = mode_Iu;
2781 pn_res = pn_ia32_Load_res;
2784 set_irn_pinned(new_op, op_pin_state_floats);
2785 set_ia32_frame_ent(new_op, ent);
2786 set_ia32_use_frame(new_op);
2788 set_ia32_op_type(new_op, ia32_AddrModeS);
2789 set_ia32_am_flavour(new_op, ia32_am_B);
2790 set_ia32_ls_mode(new_op, load_mode);
2791 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2793 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2795 return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
2799 * Transforms a FrameAddr into an ia32 Add.
2801 static ir_node *gen_be_FrameAddr(ir_node *node) {
2802 ir_node *block = be_transform_node(get_nodes_block(node));
2803 ir_node *op = be_get_FrameAddr_frame(node);
2804 ir_node *new_op = be_transform_node(op);
2805 ir_graph *irg = current_ir_graph;
2806 dbg_info *dbgi = get_irn_dbg_info(node);
2807 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2810 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
2811 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
2812 set_ia32_use_frame(res);
2813 set_ia32_am_flavour(res, ia32_am_OB);
2815 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2821 * Transforms a FrameLoad into an ia32 Load.
2823 static ir_node *gen_be_FrameLoad(ir_node *node) {
2824 ir_node *block = be_transform_node(get_nodes_block(node));
2825 ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
2826 ir_node *new_mem = be_transform_node(mem);
2827 ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
2828 ir_node *new_ptr = be_transform_node(ptr);
2829 ir_node *new_op = NULL;
2830 ir_graph *irg = current_ir_graph;
2831 dbg_info *dbgi = get_irn_dbg_info(node);
2832 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2833 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2834 ir_mode *mode = get_type_mode(get_entity_type(ent));
2835 ir_node *projs[pn_Load_max];
2837 ia32_collect_Projs(node, projs, pn_Load_max);
2839 if (mode_is_float(mode)) {
2840 if (USE_SSE2(env_cg)) {
2841 new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
2844 new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
2848 new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
2851 set_irn_pinned(new_op, op_pin_state_floats);
2852 set_ia32_frame_ent(new_op, ent);
2853 set_ia32_use_frame(new_op);
2855 set_ia32_op_type(new_op, ia32_AddrModeS);
2856 set_ia32_am_flavour(new_op, ia32_am_B);
2857 set_ia32_ls_mode(new_op, mode);
2858 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2860 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2867 * Transforms a FrameStore into an ia32 Store.
2869 static ir_node *gen_be_FrameStore(ir_node *node) {
2870 ir_node *block = be_transform_node(get_nodes_block(node));
2871 ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
2872 ir_node *new_mem = be_transform_node(mem);
2873 ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
2874 ir_node *new_ptr = be_transform_node(ptr);
2875 ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
2876 ir_node *new_val = be_transform_node(val);
2877 ir_node *new_op = NULL;
2878 ir_graph *irg = current_ir_graph;
2879 dbg_info *dbgi = get_irn_dbg_info(node);
2880 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2881 ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
2882 ir_mode *mode = get_irn_mode(val);
2884 if (mode_is_float(mode)) {
2885 if (USE_SSE2(env_cg)) {
2886 new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2888 new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
2890 } else if (get_mode_size_bits(mode) == 8) {
2891 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2893 new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
2896 set_ia32_frame_ent(new_op, ent);
2897 set_ia32_use_frame(new_op);
2899 set_ia32_op_type(new_op, ia32_AddrModeD);
2900 set_ia32_am_flavour(new_op, ia32_am_B);
2901 set_ia32_ls_mode(new_op, mode);
2903 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2909 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2911 static ir_node *gen_be_Return(ir_node *node) {
2912 ir_graph *irg = current_ir_graph;
2913 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
2914 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
2915 ir_entity *ent = get_irg_entity(irg);
2916 ir_type *tp = get_entity_type(ent);
2921 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
2922 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
2925 int pn_ret_val, pn_ret_mem, arity, i;
2927 assert(ret_val != NULL);
2928 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
2929 return be_duplicate_node(node);
2932 res_type = get_method_res_type(tp, 0);
2934 if (! is_Primitive_type(res_type)) {
2935 return be_duplicate_node(node);
2938 mode = get_type_mode(res_type);
2939 if (! mode_is_float(mode)) {
2940 return be_duplicate_node(node);
2943 assert(get_method_n_ress(tp) == 1);
2945 pn_ret_val = get_Proj_proj(ret_val);
2946 pn_ret_mem = get_Proj_proj(ret_mem);
2948 /* get the Barrier */
2949 barrier = get_Proj_pred(ret_val);
2951 /* get result input of the Barrier */
2952 ret_val = get_irn_n(barrier, pn_ret_val);
2953 new_ret_val = be_transform_node(ret_val);
2955 /* get memory input of the Barrier */
2956 ret_mem = get_irn_n(barrier, pn_ret_mem);
2957 new_ret_mem = be_transform_node(ret_mem);
2959 frame = get_irg_frame(irg);
2961 dbgi = get_irn_dbg_info(barrier);
2962 block = be_transform_node(get_nodes_block(barrier));
2964 noreg = ia32_new_NoReg_gp(env_cg);
2966 /* store xmm0 onto stack */
2967 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg, new_ret_val, new_ret_mem);
2968 set_ia32_ls_mode(sse_store, mode);
2969 set_ia32_op_type(sse_store, ia32_AddrModeD);
2970 set_ia32_use_frame(sse_store);
2971 set_ia32_am_flavour(sse_store, ia32_am_B);
2974 fld = new_rd_ia32_SetST0(dbgi, irg, block, frame, noreg, sse_store);
2975 set_ia32_ls_mode(fld, mode);
2976 set_ia32_op_type(fld, ia32_AddrModeS);
2977 set_ia32_use_frame(fld);
2978 set_ia32_am_flavour(fld, ia32_am_B);
2980 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
2981 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_SetST0_res);
2982 arch_set_irn_register(env_cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
2984 /* create a new barrier */
2985 arity = get_irn_arity(barrier);
2986 in = alloca(arity * sizeof(in[0]));
2987 for (i = 0; i < arity; ++i) {
2990 if (i == pn_ret_val) {
2992 } else if (i == pn_ret_mem) {
2995 ir_node *in = get_irn_n(barrier, i);
2996 new_in = be_transform_node(in);
3001 new_barrier = new_ir_node(dbgi, irg, block,
3002 get_irn_op(barrier), get_irn_mode(barrier),
3004 copy_node_attr(barrier, new_barrier);
3005 be_duplicate_deps(barrier, new_barrier);
3006 be_set_transformed_node(barrier, new_barrier);
3007 mark_irn_visited(barrier);
3009 /* transform normally */
3010 return be_duplicate_node(node);
3014 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3016 static ir_node *gen_be_AddSP(ir_node *node) {
3017 ir_node *block = be_transform_node(get_nodes_block(node));
3018 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3020 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3021 ir_node *new_sp = be_transform_node(sp);
3022 ir_graph *irg = current_ir_graph;
3023 dbg_info *dbgi = get_irn_dbg_info(node);
3024 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3025 ir_node *nomem = new_NoMem();
3028 new_sz = create_immediate_or_transform(sz, 0);
3030 /* ia32 stack grows in reverse direction, make a SubSP */
3031 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
3033 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3034 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3040 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3042 static ir_node *gen_be_SubSP(ir_node *node) {
3043 ir_node *block = be_transform_node(get_nodes_block(node));
3044 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3046 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3047 ir_node *new_sp = be_transform_node(sp);
3048 ir_graph *irg = current_ir_graph;
3049 dbg_info *dbgi = get_irn_dbg_info(node);
3050 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3051 ir_node *nomem = new_NoMem();
3054 new_sz = create_immediate_or_transform(sz, 0);
3056 /* ia32 stack grows in reverse direction, make an AddSP */
3057 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
3058 set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
3059 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3065 * This function just sets the register for the Unknown node
3066 * as this is not done during register allocation because Unknown
3067 * is an "ignore" node.
3069 static ir_node *gen_Unknown(ir_node *node) {
3070 ir_mode *mode = get_irn_mode(node);
3072 if (mode_is_float(mode)) {
3073 if (USE_SSE2(env_cg))
3074 return ia32_new_Unknown_xmm(env_cg);
3076 return ia32_new_Unknown_vfp(env_cg);
3077 } else if (mode_needs_gp_reg(mode)) {
3078 return ia32_new_Unknown_gp(env_cg);
3080 assert(0 && "unsupported Unknown-Mode");
3087 * Change some phi modes
3089 static ir_node *gen_Phi(ir_node *node) {
3090 ir_node *block = be_transform_node(get_nodes_block(node));
3091 ir_graph *irg = current_ir_graph;
3092 dbg_info *dbgi = get_irn_dbg_info(node);
3093 ir_mode *mode = get_irn_mode(node);
3096 if(mode_needs_gp_reg(mode)) {
3097 /* we shouldn't have any 64bit stuff around anymore */
3098 assert(get_mode_size_bits(mode) <= 32);
3099 /* all integer operations are on 32bit registers now */
3101 } else if(mode_is_float(mode)) {
3102 if (USE_SSE2(env_cg)) {
3109 /* phi nodes allow loops, so we use the old arguments for now
3110 * and fix this later */
3111 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
3112 copy_node_attr(node, phi);
3113 be_duplicate_deps(node, phi);
3115 be_set_transformed_node(node, phi);
3116 be_enqueue_preds(node);
3121 /**********************************************************************
3124 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3125 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3126 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3127 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3129 **********************************************************************/
3131 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3133 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3136 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3137 ir_node *val, ir_node *mem);
3140 * Transforms a lowered Load into a "real" one.
3142 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3144 ir_node *block = be_transform_node(get_nodes_block(node));
3145 ir_node *ptr = get_irn_n(node, 0);
3146 ir_node *new_ptr = be_transform_node(ptr);
3147 ir_node *mem = get_irn_n(node, 1);
3148 ir_node *new_mem = be_transform_node(mem);
3149 ir_graph *irg = current_ir_graph;
3150 dbg_info *dbgi = get_irn_dbg_info(node);
3151 ir_mode *mode = get_ia32_ls_mode(node);
3152 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3155 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3157 set_ia32_op_type(new_op, ia32_AddrModeS);
3158 set_ia32_am_flavour(new_op, ia32_am_OB);
3159 set_ia32_am_offs_int(new_op, 0);
3160 set_ia32_am_scale(new_op, 1);
3161 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3162 if (is_ia32_am_sc_sign(node))
3163 set_ia32_am_sc_sign(new_op);
3164 set_ia32_ls_mode(new_op, mode);
3165 if (is_ia32_use_frame(node)) {
3166 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3167 set_ia32_use_frame(new_op);
3170 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3176 * Transforms a lowered Store into a "real" one.
3178 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3180 ir_node *block = be_transform_node(get_nodes_block(node));
3181 ir_node *ptr = get_irn_n(node, 0);
3182 ir_node *new_ptr = be_transform_node(ptr);
3183 ir_node *val = get_irn_n(node, 1);
3184 ir_node *new_val = be_transform_node(val);
3185 ir_node *mem = get_irn_n(node, 2);
3186 ir_node *new_mem = be_transform_node(mem);
3187 ir_graph *irg = current_ir_graph;
3188 dbg_info *dbgi = get_irn_dbg_info(node);
3189 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3190 ir_mode *mode = get_ia32_ls_mode(node);
3193 ia32_am_flavour_t am_flav = ia32_B;
3195 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3197 if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
3199 add_ia32_am_offs_int(new_op, am_offs);
3202 set_ia32_op_type(new_op, ia32_AddrModeD);
3203 set_ia32_am_flavour(new_op, am_flav);
3204 set_ia32_ls_mode(new_op, mode);
3205 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3206 set_ia32_use_frame(new_op);
3208 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3215 * Transforms an ia32_l_XXX into a "real" XXX node
3217 * @param env The transformation environment
3218 * @return the created ia32 XXX node
3220 #define GEN_LOWERED_OP(op) \
3221 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3222 return gen_binop(node, get_binop_left(node), \
3223 get_binop_right(node), new_rd_ia32_##op,0); \
3226 #define GEN_LOWERED_x87_OP(op) \
3227 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3229 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3230 get_binop_right(node), new_rd_ia32_##op); \
3234 #define GEN_LOWERED_UNOP(op) \
3235 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3236 return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
3239 #define GEN_LOWERED_SHIFT_OP(op) \
3240 static ir_node *gen_ia32_l_##op(ir_node *node) {\
3241 return gen_shift_binop(node, get_binop_left(node), \
3242 get_binop_right(node), new_rd_ia32_##op); \
3245 #define GEN_LOWERED_LOAD(op) \
3246 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3247 return gen_lowered_Load(node, new_rd_ia32_##op); \
3250 #define GEN_LOWERED_STORE(op) \
3251 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3252 return gen_lowered_Store(node, new_rd_ia32_##op); \
3259 GEN_LOWERED_OP(IMul)
3261 GEN_LOWERED_x87_OP(vfprem)
3262 GEN_LOWERED_x87_OP(vfmul)
3263 GEN_LOWERED_x87_OP(vfsub)
3265 GEN_LOWERED_UNOP(Neg)
3267 GEN_LOWERED_LOAD(vfild)
3268 GEN_LOWERED_LOAD(Load)
3269 // GEN_LOWERED_STORE(vfist) TODO
3270 GEN_LOWERED_STORE(Store)
3272 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3273 ir_node *block = be_transform_node(get_nodes_block(node));
3274 ir_node *left = get_binop_left(node);
3275 ir_node *new_left = be_transform_node(left);
3276 ir_node *right = get_binop_right(node);
3277 ir_node *new_right = be_transform_node(right);
3278 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3279 ir_graph *irg = current_ir_graph;
3280 dbg_info *dbgi = get_irn_dbg_info(node);
3281 ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
3282 &ia32_fp_cw_regs[REG_FPCW]);
3285 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
3286 new_right, new_NoMem(), fpcw);
3287 clear_ia32_commutative(vfdiv);
3288 set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
3290 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3296 * Transforms a l_MulS into a "real" MulS node.
3298 * @param env The transformation environment
3299 * @return the created ia32 Mul node
3301 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3302 ir_node *block = be_transform_node(get_nodes_block(node));
3303 ir_node *left = get_binop_left(node);
3304 ir_node *new_left = be_transform_node(left);
3305 ir_node *right = get_binop_right(node);
3306 ir_node *new_right = be_transform_node(right);
3307 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3308 ir_graph *irg = current_ir_graph;
3309 dbg_info *dbgi = get_irn_dbg_info(node);
3311 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3312 /* and then skip the result Proj, because all needed Projs are already there. */
3313 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
3314 new_right, new_NoMem());
3315 clear_ia32_commutative(muls);
3316 set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
3318 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3323 GEN_LOWERED_SHIFT_OP(Shl)
3324 GEN_LOWERED_SHIFT_OP(Shr)
3325 GEN_LOWERED_SHIFT_OP(Sar)
3328 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3329 * op1 - target to be shifted
3330 * op2 - contains bits to be shifted into target
3332 * Only op3 can be an immediate.
3334 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3335 ir_node *op2, ir_node *count)
3337 ir_node *block = be_transform_node(get_nodes_block(node));
3338 ir_node *new_op1 = be_transform_node(op1);
3339 ir_node *new_op2 = be_transform_node(op2);
3340 ir_node *new_count = be_transform_node(count);
3341 ir_node *new_op = NULL;
3342 ir_graph *irg = current_ir_graph;
3343 dbg_info *dbgi = get_irn_dbg_info(node);
3344 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3345 ir_node *nomem = new_NoMem();
3349 assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
3351 /* Check if immediate optimization is on and */
3352 /* if it's an operation with immediate. */
3353 imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
3355 /* Limit imm_op within range imm8 */
3357 tv = get_ia32_Immop_tarval(imm_op);
3360 tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
3361 set_ia32_Immop_tarval(imm_op, tv);
3368 /* integer operations */
3370 /* This is ShiftD with const */
3371 DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
3373 if (is_ia32_l_ShlD(node))
3374 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3375 new_op1, new_op2, noreg, nomem);
3377 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3378 new_op1, new_op2, noreg, nomem);
3379 copy_ia32_Immop_attr(new_op, imm_op);
3382 /* This is a normal ShiftD */
3383 DB((dbg, LEVEL_1, "ShiftD binop ..."));
3384 if (is_ia32_l_ShlD(node))
3385 new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
3386 new_op1, new_op2, new_count, nomem);
3388 new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
3389 new_op1, new_op2, new_count, nomem);
3392 /* set AM support */
3393 set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
3395 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3397 set_ia32_emit_cl(new_op);
3402 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3403 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3404 get_irn_n(node, 1), get_irn_n(node, 2));
3407 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3408 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3409 get_irn_n(node, 1), get_irn_n(node, 2));
3413 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3415 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3416 ir_node *block = be_transform_node(get_nodes_block(node));
3417 ir_node *val = get_irn_n(node, 1);
3418 ir_node *new_val = be_transform_node(val);
3419 ia32_code_gen_t *cg = env_cg;
3420 ir_node *res = NULL;
3421 ir_graph *irg = current_ir_graph;
3423 ir_node *noreg, *new_ptr, *new_mem;
3430 mem = get_irn_n(node, 2);
3431 new_mem = be_transform_node(mem);
3432 ptr = get_irn_n(node, 0);
3433 new_ptr = be_transform_node(ptr);
3434 noreg = ia32_new_NoReg_gp(cg);
3435 dbgi = get_irn_dbg_info(node);
3437 /* Store x87 -> MEM */
3438 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
3439 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3440 set_ia32_use_frame(res);
3441 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3442 set_ia32_am_flavour(res, ia32_B);
3443 set_ia32_op_type(res, ia32_AddrModeD);
3445 /* Load MEM -> SSE */
3446 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
3447 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3448 set_ia32_use_frame(res);
3449 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3450 set_ia32_am_flavour(res, ia32_B);
3451 set_ia32_op_type(res, ia32_AddrModeS);
3452 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3458 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3460 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3461 ir_node *block = be_transform_node(get_nodes_block(node));
3462 ir_node *val = get_irn_n(node, 1);
3463 ir_node *new_val = be_transform_node(val);
3464 ia32_code_gen_t *cg = env_cg;
3465 ir_graph *irg = current_ir_graph;
3466 ir_node *res = NULL;
3467 ir_entity *fent = get_ia32_frame_ent(node);
3468 ir_mode *lsmode = get_ia32_ls_mode(node);
3470 ir_node *noreg, *new_ptr, *new_mem;
3474 if (! USE_SSE2(cg)) {
3475 /* SSE unit is not used -> skip this node. */
3479 ptr = get_irn_n(node, 0);
3480 new_ptr = be_transform_node(ptr);
3481 mem = get_irn_n(node, 2);
3482 new_mem = be_transform_node(mem);
3483 noreg = ia32_new_NoReg_gp(cg);
3484 dbgi = get_irn_dbg_info(node);
3486 /* Store SSE -> MEM */
3487 if (is_ia32_xLoad(skip_Proj(new_val))) {
3488 ir_node *ld = skip_Proj(new_val);
3490 /* we can vfld the value directly into the fpu */
3491 fent = get_ia32_frame_ent(ld);
3492 ptr = get_irn_n(ld, 0);
3493 offs = get_ia32_am_offs_int(ld);
3495 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3496 set_ia32_frame_ent(res, fent);
3497 set_ia32_use_frame(res);
3498 set_ia32_ls_mode(res, lsmode);
3499 set_ia32_am_flavour(res, ia32_B);
3500 set_ia32_op_type(res, ia32_AddrModeD);
3504 /* Load MEM -> x87 */
3505 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3506 set_ia32_frame_ent(res, fent);
3507 set_ia32_use_frame(res);
3508 add_ia32_am_offs_int(res, offs);
3509 set_ia32_am_flavour(res, ia32_B);
3510 set_ia32_op_type(res, ia32_AddrModeS);
3511 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3516 /*********************************************************
3519 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3520 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3521 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3522 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3524 *********************************************************/
3527 * the BAD transformer.
3529 static ir_node *bad_transform(ir_node *node) {
3530 panic("No transform function for %+F available.\n", node);
3535 * Transform the Projs of an AddSP.
3537 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3538 ir_node *block = be_transform_node(get_nodes_block(node));
3539 ir_node *pred = get_Proj_pred(node);
3540 ir_node *new_pred = be_transform_node(pred);
3541 ir_graph *irg = current_ir_graph;
3542 dbg_info *dbgi = get_irn_dbg_info(node);
3543 long proj = get_Proj_proj(node);
3545 if (proj == pn_be_AddSP_res) {
3546 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
3547 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3549 } else if (proj == pn_be_AddSP_M) {
3550 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
3554 return new_rd_Unknown(irg, get_irn_mode(node));
3558 * Transform the Projs of a SubSP.
3560 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
3561 ir_node *block = be_transform_node(get_nodes_block(node));
3562 ir_node *pred = get_Proj_pred(node);
3563 ir_node *new_pred = be_transform_node(pred);
3564 ir_graph *irg = current_ir_graph;
3565 dbg_info *dbgi = get_irn_dbg_info(node);
3566 long proj = get_Proj_proj(node);
3568 if (proj == pn_be_SubSP_res) {
3569 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_SubSP_stack);
3570 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3572 } else if (proj == pn_be_SubSP_M) {
3573 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
3577 return new_rd_Unknown(irg, get_irn_mode(node));
3581 * Transform and renumber the Projs from a Load.
3583 static ir_node *gen_Proj_Load(ir_node *node) {
3584 ir_node *block = be_transform_node(get_nodes_block(node));
3585 ir_node *pred = get_Proj_pred(node);
3586 ir_node *new_pred = be_transform_node(pred);
3587 ir_graph *irg = current_ir_graph;
3588 dbg_info *dbgi = get_irn_dbg_info(node);
3589 long proj = get_Proj_proj(node);
3591 /* renumber the proj */
3592 if (is_ia32_Load(new_pred)) {
3593 if (proj == pn_Load_res) {
3594 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
3595 } else if (proj == pn_Load_M) {
3596 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
3598 } else if (is_ia32_xLoad(new_pred)) {
3599 if (proj == pn_Load_res) {
3600 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
3601 } else if (proj == pn_Load_M) {
3602 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
3604 } else if (is_ia32_vfld(new_pred)) {
3605 if (proj == pn_Load_res) {
3606 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
3607 } else if (proj == pn_Load_M) {
3608 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
3613 return new_rd_Unknown(irg, get_irn_mode(node));
3617 * Transform and renumber the Projs from a DivMod like instruction.
3619 static ir_node *gen_Proj_DivMod(ir_node *node) {
3620 ir_node *block = be_transform_node(get_nodes_block(node));
3621 ir_node *pred = get_Proj_pred(node);
3622 ir_node *new_pred = be_transform_node(pred);
3623 ir_graph *irg = current_ir_graph;
3624 dbg_info *dbgi = get_irn_dbg_info(node);
3625 ir_mode *mode = get_irn_mode(node);
3626 long proj = get_Proj_proj(node);
3628 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
3630 switch (get_irn_opcode(pred)) {
3634 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3636 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3644 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3646 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3654 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
3655 case pn_DivMod_res_div:
3656 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
3657 case pn_DivMod_res_mod:
3658 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
3668 return new_rd_Unknown(irg, mode);
3672 * Transform and renumber the Projs from a CopyB.
3674 static ir_node *gen_Proj_CopyB(ir_node *node) {
3675 ir_node *block = be_transform_node(get_nodes_block(node));
3676 ir_node *pred = get_Proj_pred(node);
3677 ir_node *new_pred = be_transform_node(pred);
3678 ir_graph *irg = current_ir_graph;
3679 dbg_info *dbgi = get_irn_dbg_info(node);
3680 ir_mode *mode = get_irn_mode(node);
3681 long proj = get_Proj_proj(node);
3684 case pn_CopyB_M_regular:
3685 if (is_ia32_CopyB_i(new_pred)) {
3686 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
3687 } else if (is_ia32_CopyB(new_pred)) {
3688 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
3696 return new_rd_Unknown(irg, mode);
3700 * Transform and renumber the Projs from a vfdiv.
3702 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
3703 ir_node *block = be_transform_node(get_nodes_block(node));
3704 ir_node *pred = get_Proj_pred(node);
3705 ir_node *new_pred = be_transform_node(pred);
3706 ir_graph *irg = current_ir_graph;
3707 dbg_info *dbgi = get_irn_dbg_info(node);
3708 ir_mode *mode = get_irn_mode(node);
3709 long proj = get_Proj_proj(node);
3712 case pn_ia32_l_vfdiv_M:
3713 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3714 case pn_ia32_l_vfdiv_res:
3715 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3720 return new_rd_Unknown(irg, mode);
3724 * Transform and renumber the Projs from a Quot.
3726 static ir_node *gen_Proj_Quot(ir_node *node) {
3727 ir_node *block = be_transform_node(get_nodes_block(node));
3728 ir_node *pred = get_Proj_pred(node);
3729 ir_node *new_pred = be_transform_node(pred);
3730 ir_graph *irg = current_ir_graph;
3731 dbg_info *dbgi = get_irn_dbg_info(node);
3732 ir_mode *mode = get_irn_mode(node);
3733 long proj = get_Proj_proj(node);
3737 if (is_ia32_xDiv(new_pred)) {
3738 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
3739 } else if (is_ia32_vfdiv(new_pred)) {
3740 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
3744 if (is_ia32_xDiv(new_pred)) {
3745 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
3746 } else if (is_ia32_vfdiv(new_pred)) {
3747 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
3755 return new_rd_Unknown(irg, mode);
3759 * Transform the Thread Local Storage Proj.
3761 static ir_node *gen_Proj_tls(ir_node *node) {
3762 ir_node *block = be_transform_node(get_nodes_block(node));
3763 ir_graph *irg = current_ir_graph;
3764 dbg_info *dbgi = NULL;
3765 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
3771 * Transform the Projs from a be_Call.
3773 static ir_node *gen_Proj_be_Call(ir_node *node) {
3774 ir_node *block = be_transform_node(get_nodes_block(node));
3775 ir_node *call = get_Proj_pred(node);
3776 ir_node *new_call = be_transform_node(call);
3777 ir_graph *irg = current_ir_graph;
3778 dbg_info *dbgi = get_irn_dbg_info(node);
3779 long proj = get_Proj_proj(node);
3780 ir_mode *mode = get_irn_mode(node);
3782 const arch_register_class_t *cls;
3784 /* The following is kinda tricky: If we're using SSE, then we have to
3785 * move the result value of the call in floating point registers to an
3786 * xmm register, we therefore construct a GetST0 -> xLoad sequence
3787 * after the call, we have to make sure to correctly make the
3788 * MemProj and the result Proj use these 2 nodes
3790 if (proj == pn_be_Call_M_regular) {
3791 // get new node for result, are we doing the sse load/store hack?
3792 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
3793 ir_node *call_res_new;
3794 ir_node *call_res_pred = NULL;
3796 if (call_res != NULL) {
3797 call_res_new = be_transform_node(call_res);
3798 call_res_pred = get_Proj_pred(call_res_new);
3801 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
3802 return new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3804 assert(is_ia32_xLoad(call_res_pred));
3805 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
3808 if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
3810 ir_node *frame = get_irg_frame(irg);
3811 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3813 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
3815 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
3816 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M, pn_be_Call_M_regular);
3818 /* store st(0) onto stack */
3819 fstp = new_rd_ia32_GetST0(dbgi, irg, block, frame, noreg, call_mem);
3821 set_ia32_ls_mode(fstp, mode);
3822 set_ia32_op_type(fstp, ia32_AddrModeD);
3823 set_ia32_use_frame(fstp);
3824 set_ia32_am_flavour(fstp, ia32_am_B);
3826 /* load into SSE register */
3827 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
3828 set_ia32_ls_mode(sse_load, mode);
3829 set_ia32_op_type(sse_load, ia32_AddrModeS);
3830 set_ia32_use_frame(sse_load);
3831 set_ia32_am_flavour(sse_load, ia32_am_B);
3833 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm, pn_ia32_xLoad_res);
3835 /* now: create new Keep whith all former ins and one additional in - the result Proj */
3837 /* get a Proj representing a caller save register */
3838 p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
3839 assert(is_Proj(p) && "Proj expected.");
3841 /* user of the the proj is the Keep */
3842 p = get_edge_src_irn(get_irn_out_edge_first(p));
3843 assert(be_is_Keep(p) && "Keep expected.");
3848 /* transform call modes */
3849 if (mode_is_data(mode)) {
3850 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
3854 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
3858 * Transform the Projs from a Cmp.
3860 static ir_node *gen_Proj_Cmp(ir_node *node)
3862 /* normally Cmps are processed when looking at Cond nodes, but this case
3863 * can happen in complicated Psi conditions */
3865 ir_node *cmp = get_Proj_pred(node);
3866 long pnc = get_Proj_proj(node);
3867 ir_node *cmp_left = get_Cmp_left(cmp);
3868 ir_node *cmp_right = get_Cmp_right(cmp);
3869 ir_mode *cmp_mode = get_irn_mode(cmp_left);
3870 dbg_info *dbgi = get_irn_dbg_info(cmp);
3871 ir_node *block = be_transform_node(get_nodes_block(node));
3874 assert(!mode_is_float(cmp_mode));
3876 if(!mode_is_signed(cmp_mode)) {
3877 pnc |= ia32_pn_Cmp_Unsigned;
3880 res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
3881 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
3887 * Transform and potentially renumber Proj nodes.
3889 static ir_node *gen_Proj(ir_node *node) {
3890 ir_graph *irg = current_ir_graph;
3891 dbg_info *dbgi = get_irn_dbg_info(node);
3892 ir_node *pred = get_Proj_pred(node);
3893 long proj = get_Proj_proj(node);
3895 if (is_Store(pred) || be_is_FrameStore(pred)) {
3896 if (proj == pn_Store_M) {
3897 return be_transform_node(pred);
3900 return new_r_Bad(irg);
3902 } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
3903 return gen_Proj_Load(node);
3904 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
3905 return gen_Proj_DivMod(node);
3906 } else if (is_CopyB(pred)) {
3907 return gen_Proj_CopyB(node);
3908 } else if (is_Quot(pred)) {
3909 return gen_Proj_Quot(node);
3910 } else if (is_ia32_l_vfdiv(pred)) {
3911 return gen_Proj_l_vfdiv(node);
3912 } else if (be_is_SubSP(pred)) {
3913 return gen_Proj_be_SubSP(node);
3914 } else if (be_is_AddSP(pred)) {
3915 return gen_Proj_be_AddSP(node);
3916 } else if (be_is_Call(pred)) {
3917 return gen_Proj_be_Call(node);
3918 } else if (is_Cmp(pred)) {
3919 return gen_Proj_Cmp(node);
3920 } else if (get_irn_op(pred) == op_Start) {
3921 if (proj == pn_Start_X_initial_exec) {
3922 ir_node *block = get_nodes_block(pred);
3925 /* we exchange the ProjX with a jump */
3926 block = be_transform_node(block);
3927 jump = new_rd_Jmp(dbgi, irg, block);
3930 if (node == be_get_old_anchor(anchor_tls)) {
3931 return gen_Proj_tls(node);
3934 ir_node *new_pred = be_transform_node(pred);
3935 ir_node *block = be_transform_node(get_nodes_block(node));
3936 ir_mode *mode = get_irn_mode(node);
3937 if (mode_needs_gp_reg(mode)) {
3938 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
3939 get_Proj_proj(node));
3940 #ifdef DEBUG_libfirm
3941 new_proj->node_nr = node->node_nr;
3947 return be_duplicate_node(node);
3951 * Enters all transform functions into the generic pointer
3953 static void register_transformers(void)
3957 /* first clear the generic function pointer for all ops */
3958 clear_irp_opcodes_generic_func();
3960 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
3961 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
3997 /* transform ops from intrinsic lowering */
4017 /* GEN(ia32_l_vfist); TODO */
4019 GEN(ia32_l_X87toSSE);
4020 GEN(ia32_l_SSEtoX87);
4025 /* we should never see these nodes */
4040 /* handle generic backend nodes */
4051 /* set the register for all Unknown nodes */
4054 op_Mulh = get_op_Mulh();
4063 * Pre-transform all unknown and noreg nodes.
4065 static void ia32_pretransform_node(void *arch_cg) {
4066 ia32_code_gen_t *cg = arch_cg;
4068 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4069 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4070 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4071 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4072 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4073 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4077 void add_missing_keep_walker(ir_node *node, void *data)
4080 unsigned found_projs = 0;
4081 const ir_edge_t *edge;
4082 ir_mode *mode = get_irn_mode(node);
4087 if(!is_ia32_irn(node))
4090 n_outs = get_ia32_n_res(node);
4093 if(is_ia32_SwitchJmp(node))
4096 assert(n_outs < (int) sizeof(unsigned) * 8);
4097 foreach_out_edge(node, edge) {
4098 ir_node *proj = get_edge_src_irn(edge);
4099 int pn = get_Proj_proj(proj);
4101 assert(pn < n_outs);
4102 found_projs |= 1 << pn;
4106 /* are keeps missing? */
4108 for(i = 0; i < n_outs; ++i) {
4111 const arch_register_req_t *req;
4112 const arch_register_class_t *class;
4114 if(found_projs & (1 << i)) {
4118 req = get_ia32_out_req(node, i);
4124 block = get_nodes_block(node);
4125 in[0] = new_r_Proj(current_ir_graph, block, node,
4126 arch_register_class_mode(class), i);
4127 if(last_keep != NULL) {
4128 be_Keep_add_node(last_keep, class, in[0]);
4130 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4136 * Adds missing keeps to nodes
4139 void add_missing_keeps(ia32_code_gen_t *cg)
4141 ir_graph *irg = be_get_birg_irg(cg->birg);
4142 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4145 /* do the transformation */
4146 void ia32_transform_graph(ia32_code_gen_t *cg) {
4147 register_transformers();
4149 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4150 edges_verify(cg->irg);
4151 add_missing_keeps(cg);
4152 edges_verify(cg->irg);
4155 void ia32_init_transform(void)
4157 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");