2 * This file implements the IR transformation from firm into ia32-Firm.
3 * @author Christian Wuerdig
15 #include "irgraph_t.h"
20 #include "iredges_t.h"
30 #include "archop.h" /* we need this for Min and Max nodes */
32 #include "../benode_t.h"
33 #include "../besched.h"
36 #include "bearch_ia32_t.h"
37 #include "ia32_nodes_attr.h"
38 #include "ia32_transform.h"
39 #include "ia32_new_nodes.h"
40 #include "ia32_map_regs.h"
41 #include "ia32_dbg_stat.h"
42 #include "ia32_optimize.h"
43 #include "ia32_util.h"
45 #include "gen_ia32_regalloc_if.h"
47 #define SFP_SIGN "0x80000000"
48 #define DFP_SIGN "0x8000000000000000"
49 #define SFP_ABS "0x7FFFFFFF"
50 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
52 #define TP_SFP_SIGN "ia32_sfp_sign"
53 #define TP_DFP_SIGN "ia32_dfp_sign"
54 #define TP_SFP_ABS "ia32_sfp_abs"
55 #define TP_DFP_ABS "ia32_dfp_abs"
57 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
58 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
59 #define ENT_SFP_ABS "IA32_SFP_ABS"
60 #define ENT_DFP_ABS "IA32_DFP_ABS"
62 extern ir_op *get_op_Mulh(void);
64 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
65 ir_node *op1, ir_node *op2, ir_node *mem);
67 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
68 ir_node *op, ir_node *mem);
71 ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
74 /****************************************************************************************************
76 * | | | | / _| | | (_)
77 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
78 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
79 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
80 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
82 ****************************************************************************************************/
85 * Returns 1 if irn is a Const representing 0, 0 otherwise
87 static INLINE int is_ia32_Const_0(ir_node *irn) {
88 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
89 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
93 * Returns 1 if irn is a Const representing 1, 0 otherwise
95 static INLINE int is_ia32_Const_1(ir_node *irn) {
96 return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
97 classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
101 * Returns the Proj representing the UNKNOWN register for given mode.
103 static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
104 be_abi_irg_t *babi = cg->birg->abi;
105 const arch_register_t *unknwn_reg = NULL;
107 if (mode_is_float(mode)) {
108 unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
111 unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
114 return be_abi_get_callee_save_irn(babi, unknwn_reg);
118 * Gets the Proj with number pn from irn.
120 static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
121 const ir_edge_t *edge;
123 assert(get_irn_mode(irn) == mode_T && "need mode_T");
125 foreach_out_edge(irn, edge) {
126 proj = get_edge_src_irn(edge);
128 if (get_Proj_proj(proj) == pn)
136 * SSE convert of an integer node into a floating point node.
138 static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
139 ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
141 ir_node *noreg = ia32_new_NoReg_gp(cg);
142 ir_node *nomem = new_rd_NoMem(irg);
144 ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
145 set_ia32_src_mode(conv, get_irn_mode(in));
146 set_ia32_tgt_mode(conv, tgt_mode);
147 set_ia32_am_support(conv, ia32_am_Source);
148 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
150 return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
154 * SSE convert of an float node into a double node.
156 static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
157 ir_node *in, ir_node *old_node)
159 ir_node *noreg = ia32_new_NoReg_gp(cg);
160 ir_node *nomem = new_rd_NoMem(irg);
162 ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
163 set_ia32_src_mode(conv, mode_F);
164 set_ia32_tgt_mode(conv, mode_D);
165 set_ia32_am_support(conv, ia32_am_Source);
166 SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
168 return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res);
171 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
172 static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
173 static const struct {
175 const char *ent_name;
176 const char *cnst_str;
177 } names [ia32_known_const_max] = {
178 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
179 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
180 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
181 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
183 static struct entity *ent_cache[ia32_known_const_max];
185 const char *tp_name, *ent_name, *cnst_str;
192 ent_name = names[kct].ent_name;
193 if (! ent_cache[kct]) {
194 tp_name = names[kct].tp_name;
195 cnst_str = names[kct].cnst_str;
197 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
198 tp = new_type_primitive(new_id_from_str(tp_name), mode);
199 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
201 set_entity_ld_ident(ent, get_entity_ident(ent));
202 set_entity_visibility(ent, visibility_local);
203 set_entity_variability(ent, variability_constant);
204 set_entity_allocation(ent, allocation_static);
206 /* we create a new entity here: It's initialization must resist on the
208 rem = current_ir_graph;
209 current_ir_graph = get_const_code_irg();
210 cnst = new_Const(mode, tv);
211 current_ir_graph = rem;
213 set_atomic_ent_value(ent, cnst);
215 /* cache the entry */
216 ent_cache[kct] = ent;
219 return get_entity_ident(ent_cache[kct]);
224 * Prints the old node name on cg obst and returns a pointer to it.
226 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
227 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
229 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
230 obstack_1grow(isa->name_obst, 0);
231 isa->name_obst_size += obstack_object_size(isa->name_obst);
232 return obstack_finish(isa->name_obst);
236 /* determine if one operator is an Imm */
237 static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
239 return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
240 else return is_ia32_Cnst(op2) ? op2 : NULL;
243 /* determine if one operator is not an Imm */
244 static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
245 return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
250 * Construct a standard binary operation, set AM and immediate if required.
252 * @param env The transformation environment
253 * @param op1 The first operand
254 * @param op2 The second operand
255 * @param func The node constructor function
256 * @return The constructed ia32 node.
258 static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
259 ir_node *new_op = NULL;
260 ir_mode *mode = env->mode;
261 dbg_info *dbg = env->dbg;
262 ir_graph *irg = env->irg;
263 ir_node *block = env->block;
264 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
265 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
266 ir_node *nomem = new_NoMem();
268 ir_node *expr_op, *imm_op;
269 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
271 /* Check if immediate optimization is on and */
272 /* if it's an operation with immediate. */
273 /* Mul/MulS/Mulh don't support immediates */
274 if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
275 func == new_rd_ia32_Mul ||
276 func == new_rd_ia32_Mulh ||
277 func == new_rd_ia32_MulS)
281 /* immediate operations are requested, but we are here: it a mul */
282 if (env->cg->opt & IA32_OPT_IMMOPS)
285 else if (is_op_commutative(get_irn_op(env->irn))) {
286 imm_op = get_immediate_op(op1, op2);
287 expr_op = get_expr_op(op1, op2);
290 imm_op = get_immediate_op(NULL, op2);
291 expr_op = get_expr_op(op1, op2);
294 assert((expr_op || imm_op) && "invalid operands");
297 /* We have two consts here: not yet supported */
301 if (mode_is_float(mode)) {
302 /* floating point operations */
304 DB((mod, LEVEL_1, "FP with immediate ..."));
305 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem);
306 set_ia32_Immop_attr(new_op, imm_op);
307 set_ia32_am_support(new_op, ia32_am_None);
310 DB((mod, LEVEL_1, "FP binop ..."));
311 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
312 set_ia32_am_support(new_op, ia32_am_Source);
314 set_ia32_ls_mode(new_op, mode);
317 /* integer operations */
319 /* This is expr + const */
320 DB((mod, LEVEL_1, "INT with immediate ..."));
321 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem);
322 set_ia32_Immop_attr(new_op, imm_op);
325 set_ia32_am_support(new_op, ia32_am_Dest);
328 DB((mod, LEVEL_1, "INT binop ..."));
329 /* This is a normal operation */
330 new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
333 set_ia32_am_support(new_op, ia32_am_Full);
336 /* Muls can only have AM source */
338 set_ia32_am_support(new_op, ia32_am_Source);
341 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
343 set_ia32_res_mode(new_op, mode);
345 if (is_op_commutative(get_irn_op(env->irn))) {
346 set_ia32_commutative(new_op);
349 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
355 * Construct a shift/rotate binary operation, sets AM and immediate if required.
357 * @param env The transformation environment
358 * @param op1 The first operand
359 * @param op2 The second operand
360 * @param func The node constructor function
361 * @return The constructed ia32 node.
363 static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
364 ir_node *new_op = NULL;
365 ir_mode *mode = env->mode;
366 dbg_info *dbg = env->dbg;
367 ir_graph *irg = env->irg;
368 ir_node *block = env->block;
369 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
370 ir_node *nomem = new_NoMem();
371 ir_node *expr_op, *imm_op;
373 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
375 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
377 /* Check if immediate optimization is on and */
378 /* if it's an operation with immediate. */
379 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
380 expr_op = get_expr_op(op1, op2);
382 assert((expr_op || imm_op) && "invalid operands");
385 /* We have two consts here: not yet supported */
389 /* Limit imm_op within range imm8 */
391 tv = get_ia32_Immop_tarval(imm_op);
394 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
395 set_ia32_Immop_tarval(imm_op, tv);
402 /* integer operations */
404 /* This is shift/rot with const */
405 DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
407 new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
408 set_ia32_Immop_attr(new_op, imm_op);
411 /* This is a normal shift/rot */
412 DB((mod, LEVEL_1, "Shift/Rot binop ..."));
413 new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem);
417 set_ia32_am_support(new_op, ia32_am_Dest);
419 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
421 set_ia32_res_mode(new_op, mode);
422 set_ia32_emit_cl(new_op);
424 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
429 * Construct a standard unary operation, set AM and immediate if required.
431 * @param env The transformation environment
432 * @param op The operand
433 * @param func The node constructor function
434 * @return The constructed ia32 node.
436 static ir_node *gen_unop(ia32_transform_env_t *env, ir_node *op, construct_unop_func *func) {
437 ir_node *new_op = NULL;
438 ir_mode *mode = env->mode;
439 dbg_info *dbg = env->dbg;
440 ir_graph *irg = env->irg;
441 ir_node *block = env->block;
442 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
443 ir_node *nomem = new_NoMem();
444 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
446 new_op = func(dbg, irg, block, noreg, noreg, op, nomem);
448 if (mode_is_float(mode)) {
449 DB((mod, LEVEL_1, "FP unop ..."));
450 /* floating point operations don't support implicit store */
451 set_ia32_am_support(new_op, ia32_am_None);
454 DB((mod, LEVEL_1, "INT unop ..."));
455 set_ia32_am_support(new_op, ia32_am_Dest);
458 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
460 set_ia32_res_mode(new_op, mode);
462 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
468 * Creates an ia32 Add with immediate.
470 * @param env The transformation environment
471 * @param expr_op The expression operator
472 * @param const_op The constant
473 * @return the created ia32 Add node
475 static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
476 ir_node *new_op = NULL;
477 tarval *tv = get_ia32_Immop_tarval(const_op);
478 dbg_info *dbg = env->dbg;
479 ir_graph *irg = env->irg;
480 ir_node *block = env->block;
481 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
482 ir_node *nomem = new_NoMem();
484 tarval_classification_t class_tv, class_negtv;
485 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
487 /* try to optimize to inc/dec */
488 if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
489 /* optimize tarvals */
490 class_tv = classify_tarval(tv);
491 class_negtv = classify_tarval(tarval_neg(tv));
493 if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
494 DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
495 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
498 else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
499 DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
500 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
506 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
507 set_ia32_Immop_attr(new_op, const_op);
508 set_ia32_commutative(new_op);
515 * Creates an ia32 Add.
517 * @param env The transformation environment
518 * @return the created ia32 Add node
520 static ir_node *gen_Add(ia32_transform_env_t *env) {
521 ir_node *new_op = NULL;
522 dbg_info *dbg = env->dbg;
523 ir_mode *mode = env->mode;
524 ir_graph *irg = env->irg;
525 ir_node *block = env->block;
526 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
527 ir_node *nomem = new_NoMem();
528 ir_node *expr_op, *imm_op;
529 ir_node *op1 = get_Add_left(env->irn);
530 ir_node *op2 = get_Add_right(env->irn);
532 /* Check if immediate optimization is on and */
533 /* if it's an operation with immediate. */
534 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
535 expr_op = get_expr_op(op1, op2);
537 assert((expr_op || imm_op) && "invalid operands");
539 if (mode_is_float(mode)) {
541 if (USE_SSE2(env->cg))
542 return gen_binop(env, op1, op2, new_rd_ia32_xAdd);
544 return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
549 /* No expr_op means, that we have two const - one symconst and */
550 /* one tarval or another symconst - because this case is not */
551 /* covered by constant folding */
552 /* We need to check for: */
553 /* 1) symconst + const -> becomes a LEA */
554 /* 2) symconst + symconst -> becomes a const + LEA as the elf */
555 /* linker doesn't support two symconsts */
557 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
558 /* this is the 2nd case */
559 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
560 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
561 set_ia32_am_flavour(new_op, ia32_am_OB);
563 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
566 /* this is the 1st case */
567 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
569 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
571 if (get_ia32_op_type(op1) == ia32_SymConst) {
572 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
573 add_ia32_am_offs(new_op, get_ia32_cnst(op2));
576 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
577 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
579 set_ia32_am_flavour(new_op, ia32_am_O);
583 set_ia32_am_support(new_op, ia32_am_Source);
584 set_ia32_op_type(new_op, ia32_AddrModeS);
586 /* Lea doesn't need a Proj */
590 /* This is expr + const */
591 new_op = gen_imm_Add(env, expr_op, imm_op);
594 set_ia32_am_support(new_op, ia32_am_Dest);
597 /* This is a normal add */
598 new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, op1, op2, nomem);
601 set_ia32_am_support(new_op, ia32_am_Full);
602 set_ia32_commutative(new_op);
606 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
608 set_ia32_res_mode(new_op, mode);
610 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
616 * Creates an ia32 Mul.
618 * @param env The transformation environment
619 * @return the created ia32 Mul node
621 static ir_node *gen_Mul(ia32_transform_env_t *env) {
622 ir_node *op1 = get_Mul_left(env->irn);
623 ir_node *op2 = get_Mul_right(env->irn);
626 if (mode_is_float(env->mode)) {
628 if (USE_SSE2(env->cg))
629 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMul);
631 new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
634 new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
643 * Creates an ia32 Mulh.
644 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
645 * this result while Mul returns the lower 32 bit.
647 * @param env The transformation environment
648 * @return the created ia32 Mulh node
650 static ir_node *gen_Mulh(ia32_transform_env_t *env) {
651 ir_node *op1 = get_irn_n(env->irn, 0);
652 ir_node *op2 = get_irn_n(env->irn, 1);
653 ir_node *proj_EAX, *proj_EDX, *mulh;
656 assert(!mode_is_float(env->mode) && "Mulh with float not supported");
657 proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
658 mulh = get_Proj_pred(proj_EAX);
659 proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
661 /* to be on the save side */
662 set_Proj_proj(proj_EAX, pn_EAX);
664 if (is_ia32_ImmConst(mulh) || is_ia32_ImmSymConst(mulh)) {
665 /* Mulh with const cannot have AM */
666 set_ia32_am_support(mulh, ia32_am_None);
669 /* Mulh cannot have AM for destination */
670 set_ia32_am_support(mulh, ia32_am_Source);
676 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], env->irg, env->block, 1, in);
684 * Creates an ia32 And.
686 * @param env The transformation environment
687 * @return The created ia32 And node
689 static ir_node *gen_And(ia32_transform_env_t *env) {
690 ir_node *op1 = get_And_left(env->irn);
691 ir_node *op2 = get_And_right(env->irn);
693 assert (! mode_is_float(env->mode));
694 return gen_binop(env, op1, op2, new_rd_ia32_And);
700 * Creates an ia32 Or.
702 * @param env The transformation environment
703 * @return The created ia32 Or node
705 static ir_node *gen_Or(ia32_transform_env_t *env) {
706 ir_node *op1 = get_Or_left(env->irn);
707 ir_node *op2 = get_Or_right(env->irn);
709 assert (! mode_is_float(env->mode));
710 return gen_binop(env, op1, op2, new_rd_ia32_Or);
716 * Creates an ia32 Eor.
718 * @param env The transformation environment
719 * @return The created ia32 Eor node
721 static ir_node *gen_Eor(ia32_transform_env_t *env) {
722 ir_node *op1 = get_Eor_left(env->irn);
723 ir_node *op2 = get_Eor_right(env->irn);
725 assert(! mode_is_float(env->mode));
726 return gen_binop(env, op1, op2, new_rd_ia32_Eor);
732 * Creates an ia32 Max.
734 * @param env The transformation environment
735 * @return the created ia32 Max node
737 static ir_node *gen_Max(ia32_transform_env_t *env) {
738 ir_node *op1 = get_irn_n(env->irn, 0);
739 ir_node *op2 = get_irn_n(env->irn, 1);
742 if (mode_is_float(env->mode)) {
744 if (USE_SSE2(env->cg))
745 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMax);
751 new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
752 set_ia32_am_support(new_op, ia32_am_None);
753 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
762 * Creates an ia32 Min.
764 * @param env The transformation environment
765 * @return the created ia32 Min node
767 static ir_node *gen_Min(ia32_transform_env_t *env) {
768 ir_node *op1 = get_irn_n(env->irn, 0);
769 ir_node *op2 = get_irn_n(env->irn, 1);
772 if (mode_is_float(env->mode)) {
774 if (USE_SSE2(env->cg))
775 new_op = gen_binop(env, op1, op2, new_rd_ia32_xMin);
781 new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
782 set_ia32_am_support(new_op, ia32_am_None);
783 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
792 * Creates an ia32 Sub with immediate.
794 * @param env The transformation environment
795 * @param expr_op The first operator
796 * @param const_op The constant operator
797 * @return The created ia32 Sub node
799 static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
800 ir_node *new_op = NULL;
801 tarval *tv = get_ia32_Immop_tarval(const_op);
802 dbg_info *dbg = env->dbg;
803 ir_graph *irg = env->irg;
804 ir_node *block = env->block;
805 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
806 ir_node *nomem = new_NoMem();
808 tarval_classification_t class_tv, class_negtv;
809 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
811 /* try to optimize to inc/dec */
812 if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
813 /* optimize tarvals */
814 class_tv = classify_tarval(tv);
815 class_negtv = classify_tarval(tarval_neg(tv));
817 if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
818 DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
819 new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
822 else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
823 DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
824 new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
830 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
831 set_ia32_Immop_attr(new_op, const_op);
838 * Creates an ia32 Sub.
840 * @param env The transformation environment
841 * @return The created ia32 Sub node
843 static ir_node *gen_Sub(ia32_transform_env_t *env) {
844 ir_node *new_op = NULL;
845 dbg_info *dbg = env->dbg;
846 ir_mode *mode = env->mode;
847 ir_graph *irg = env->irg;
848 ir_node *block = env->block;
849 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
850 ir_node *nomem = new_NoMem();
851 ir_node *op1 = get_Sub_left(env->irn);
852 ir_node *op2 = get_Sub_right(env->irn);
853 ir_node *expr_op, *imm_op;
855 /* Check if immediate optimization is on and */
856 /* if it's an operation with immediate. */
857 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
858 expr_op = get_expr_op(op1, op2);
860 assert((expr_op || imm_op) && "invalid operands");
862 if (mode_is_float(mode)) {
864 if (USE_SSE2(env->cg))
865 return gen_binop(env, op1, op2, new_rd_ia32_xSub);
867 return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
872 /* No expr_op means, that we have two const - one symconst and */
873 /* one tarval or another symconst - because this case is not */
874 /* covered by constant folding */
875 /* We need to check for: */
876 /* 1) symconst - const -> becomes a LEA */
877 /* 2) symconst - symconst -> becomes a const - LEA as the elf */
878 /* linker doesn't support two symconsts */
880 if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
881 /* this is the 2nd case */
882 new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
883 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
884 set_ia32_am_sc_sign(new_op);
885 set_ia32_am_flavour(new_op, ia32_am_OB);
887 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
890 /* this is the 1st case */
891 new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
893 DBG_OPT_LEA3(op1, op2, env->irn, new_op);
895 if (get_ia32_op_type(op1) == ia32_SymConst) {
896 set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
897 sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
900 add_ia32_am_offs(new_op, get_ia32_cnst(op1));
901 set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
902 set_ia32_am_sc_sign(new_op);
904 set_ia32_am_flavour(new_op, ia32_am_O);
908 set_ia32_am_support(new_op, ia32_am_Source);
909 set_ia32_op_type(new_op, ia32_AddrModeS);
911 /* Lea doesn't need a Proj */
915 /* This is expr - const */
916 new_op = gen_imm_Sub(env, expr_op, imm_op);
919 set_ia32_am_support(new_op, ia32_am_Dest);
922 /* This is a normal sub */
923 new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, op1, op2, nomem);
926 set_ia32_am_support(new_op, ia32_am_Full);
930 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
932 set_ia32_res_mode(new_op, mode);
934 return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
940 * Generates an ia32 DivMod with additional infrastructure for the
941 * register allocator if needed.
943 * @param env The transformation environment
944 * @param dividend -no comment- :)
945 * @param divisor -no comment- :)
946 * @param dm_flav flavour_Div/Mod/DivMod
947 * @return The created ia32 DivMod node
949 static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, ia32_op_flavour_t dm_flav) {
951 ir_node *edx_node, *cltd;
953 dbg_info *dbg = env->dbg;
954 ir_graph *irg = env->irg;
955 ir_node *block = env->block;
956 ir_mode *mode = env->mode;
957 ir_node *irn = env->irn;
963 mem = get_Div_mem(irn);
964 mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
967 mem = get_Mod_mem(irn);
968 mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
971 mem = get_DivMod_mem(irn);
972 mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
978 if (mode_is_signed(mode)) {
979 /* in signed mode, we need to sign extend the dividend */
980 cltd = new_rd_ia32_Cdq(dbg, irg, block, dividend);
981 dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EAX);
982 edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
985 edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
986 set_ia32_Const_type(edx_node, ia32_Const);
987 set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
990 res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, dm_flav);
992 set_ia32_n_res(res, 2);
994 /* Only one proj is used -> We must add a second proj and */
995 /* connect this one to a Keep node to eat up the second */
996 /* destroyed register. */
997 n = get_irn_n_edges(irn);
1000 proj = ia32_get_proj_for_mode(irn, mode_M);
1002 /* in case of two projs, one must be the memory proj */
1003 if (n == 1 || (n == 2 && proj)) {
1004 proj = ia32_get_res_proj(irn);
1005 assert(proj && "Result proj expected");
1007 if (get_irn_op(irn) == op_Div) {
1008 set_Proj_proj(proj, pn_DivMod_res_div);
1009 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
1012 set_Proj_proj(proj, pn_DivMod_res_mod);
1013 in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
1016 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
1019 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1021 set_ia32_res_mode(res, mode);
1028 * Wrapper for generate_DivMod. Sets flavour_Mod.
1030 * @param env The transformation environment
1032 static ir_node *gen_Mod(ia32_transform_env_t *env) {
1033 return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
1037 * Wrapper for generate_DivMod. Sets flavour_Div.
1039 * @param env The transformation environment
1041 static ir_node *gen_Div(ia32_transform_env_t *env) {
1042 return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
1046 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1048 static ir_node *gen_DivMod(ia32_transform_env_t *env) {
1049 return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
1055 * Creates an ia32 floating Div.
1057 * @param env The transformation environment
1058 * @return The created ia32 xDiv node
1060 static ir_node *gen_Quot(ia32_transform_env_t *env) {
1061 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1063 ir_node *nomem = new_rd_NoMem(env->irg);
1064 ir_node *op1 = get_Quot_left(env->irn);
1065 ir_node *op2 = get_Quot_right(env->irn);
1068 if (USE_SSE2(env->cg)) {
1069 if (is_ia32_xConst(op2)) {
1070 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem);
1071 set_ia32_am_support(new_op, ia32_am_None);
1072 set_ia32_Immop_attr(new_op, op2);
1075 new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1076 set_ia32_am_support(new_op, ia32_am_Source);
1080 new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
1081 set_ia32_am_support(new_op, ia32_am_Source);
1083 set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
1084 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1092 * Creates an ia32 Shl.
1094 * @param env The transformation environment
1095 * @return The created ia32 Shl node
1097 static ir_node *gen_Shl(ia32_transform_env_t *env) {
1098 return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
1104 * Creates an ia32 Shr.
1106 * @param env The transformation environment
1107 * @return The created ia32 Shr node
1109 static ir_node *gen_Shr(ia32_transform_env_t *env) {
1110 return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
1116 * Creates an ia32 Shrs.
1118 * @param env The transformation environment
1119 * @return The created ia32 Shrs node
1121 static ir_node *gen_Shrs(ia32_transform_env_t *env) {
1122 return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
1128 * Creates an ia32 RotL.
1130 * @param env The transformation environment
1131 * @param op1 The first operator
1132 * @param op2 The second operator
1133 * @return The created ia32 RotL node
1135 static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1136 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotL);
1142 * Creates an ia32 RotR.
1143 * NOTE: There is no RotR with immediate because this would always be a RotL
1144 * "imm-mode_size_bits" which can be pre-calculated.
1146 * @param env The transformation environment
1147 * @param op1 The first operator
1148 * @param op2 The second operator
1149 * @return The created ia32 RotR node
1151 static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
1152 return gen_shift_binop(env, op1, op2, new_rd_ia32_RotR);
1158 * Creates an ia32 RotR or RotL (depending on the found pattern).
1160 * @param env The transformation environment
1161 * @return The created ia32 RotL or RotR node
1163 static ir_node *gen_Rot(ia32_transform_env_t *env) {
1164 ir_node *rotate = NULL;
1165 ir_node *op1 = get_Rot_left(env->irn);
1166 ir_node *op2 = get_Rot_right(env->irn);
1168 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1169 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1170 that means we can create a RotR instead of an Add and a RotL */
1173 ir_node *pred = get_Proj_pred(op2);
1175 if (is_ia32_Add(pred)) {
1176 ir_node *pred_pred = get_irn_n(pred, 2);
1177 tarval *tv = get_ia32_Immop_tarval(pred);
1178 long bits = get_mode_size_bits(env->mode);
1180 if (is_Proj(pred_pred)) {
1181 pred_pred = get_Proj_pred(pred_pred);
1184 if (is_ia32_Minus(pred_pred) &&
1185 tarval_is_long(tv) &&
1186 get_tarval_long(tv) == bits)
1188 DB((env->mod, LEVEL_1, "RotL into RotR ... "));
1189 rotate = gen_RotR(env, op1, get_irn_n(pred_pred, 2));
1196 rotate = gen_RotL(env, op1, op2);
1205 * Transforms a Minus node.
1207 * @param env The transformation environment
1208 * @param op The Minus operand
1209 * @return The created ia32 Minus node
1211 ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
1216 if (mode_is_float(env->mode)) {
1218 if (USE_SSE2(env->cg)) {
1219 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1220 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1221 ir_node *nomem = new_rd_NoMem(env->irg);
1223 new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1225 size = get_mode_size_bits(env->mode);
1226 name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
1228 set_ia32_am_sc(new_op, name);
1230 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1232 set_ia32_res_mode(new_op, env->mode);
1233 set_ia32_op_type(new_op, ia32_AddrModeS);
1234 set_ia32_ls_mode(new_op, env->mode);
1236 new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
1239 new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
1240 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1244 new_op = gen_unop(env, op, new_rd_ia32_Minus);
1251 * Transforms a Minus node.
1253 * @param env The transformation environment
1254 * @return The created ia32 Minus node
1256 static ir_node *gen_Minus(ia32_transform_env_t *env) {
1257 return gen_Minus_ex(env, get_Minus_op(env->irn));
1262 * Transforms a Not node.
1264 * @param env The transformation environment
1265 * @return The created ia32 Not node
1267 static ir_node *gen_Not(ia32_transform_env_t *env) {
1268 assert (! mode_is_float(env->mode));
1269 return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
1275 * Transforms an Abs node.
1277 * @param env The transformation environment
1278 * @return The created ia32 Abs node
1280 static ir_node *gen_Abs(ia32_transform_env_t *env) {
1281 ir_node *res, *p_eax, *p_edx;
1282 dbg_info *dbg = env->dbg;
1283 ir_mode *mode = env->mode;
1284 ir_graph *irg = env->irg;
1285 ir_node *block = env->block;
1286 ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
1287 ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
1288 ir_node *nomem = new_NoMem();
1289 ir_node *op = get_Abs_op(env->irn);
1293 if (mode_is_float(mode)) {
1295 if (USE_SSE2(env->cg)) {
1296 res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
1298 size = get_mode_size_bits(mode);
1299 name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
1301 set_ia32_am_sc(res, name);
1303 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1305 set_ia32_res_mode(res, mode);
1306 set_ia32_op_type(res, ia32_AddrModeS);
1307 set_ia32_ls_mode(res, env->mode);
1309 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
1312 res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
1313 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1317 res = new_rd_ia32_Cdq(dbg, irg, block, op);
1318 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1319 set_ia32_res_mode(res, mode);
1321 p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EAX);
1322 p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Cdq_EDX);
1324 res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
1325 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1326 set_ia32_res_mode(res, mode);
1328 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Eor_res);
1330 res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
1331 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1332 set_ia32_res_mode(res, mode);
1334 res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_Sub_res);
1343 * Transforms a Load.
1345 * @param env The transformation environment
1346 * @return the created ia32 Load node
1348 static ir_node *gen_Load(ia32_transform_env_t *env) {
1349 ir_node *node = env->irn;
1350 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1351 ir_node *ptr = get_Load_ptr(node);
1352 ir_node *lptr = ptr;
1353 ir_mode *mode = get_Load_mode(node);
1356 ia32_am_flavour_t am_flav = ia32_am_B;
1358 /* address might be a constant (symconst or absolute address) */
1359 if (is_ia32_Const(ptr)) {
1364 if (mode_is_float(mode)) {
1366 if (USE_SSE2(env->cg))
1367 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1369 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1372 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
1375 /* base is an constant address */
1377 if (get_ia32_op_type(ptr) == ia32_SymConst) {
1378 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1379 am_flav = ia32_am_N;
1382 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1383 am_flav = ia32_am_O;
1387 set_ia32_am_support(new_op, ia32_am_Source);
1388 set_ia32_op_type(new_op, ia32_AddrModeS);
1389 set_ia32_am_flavour(new_op, am_flav);
1390 set_ia32_ls_mode(new_op, mode);
1393 check for special case: the loaded value might not be used (optimized, volatile, ...)
1394 we add a Proj + Keep for volatile loads and ignore all other cases
1396 if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
1397 /* add a result proj and a Keep to produce a pseudo use */
1398 ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
1399 be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
1402 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1410 * Transforms a Store.
1412 * @param env The transformation environment
1413 * @return the created ia32 Store node
1415 static ir_node *gen_Store(ia32_transform_env_t *env) {
1416 ir_node *node = env->irn;
1417 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1418 ir_node *val = get_Store_value(node);
1419 ir_node *ptr = get_Store_ptr(node);
1420 ir_node *sptr = ptr;
1421 ir_node *mem = get_Store_mem(node);
1422 ir_mode *mode = get_irn_mode(val);
1423 ir_node *sval = val;
1426 ia32_am_flavour_t am_flav = ia32_am_B;
1427 ia32_immop_type_t immop = ia32_ImmNone;
1429 if (! mode_is_float(mode)) {
1430 /* in case of storing a const (but not a symconst) -> make it an attribute */
1431 if (is_ia32_Cnst(val)) {
1432 switch (get_ia32_op_type(val)) {
1434 immop = ia32_ImmConst;
1437 immop = ia32_ImmSymConst;
1440 assert(0 && "unsupported Const type");
1446 /* address might be a constant (symconst or absolute address) */
1447 if (is_ia32_Const(ptr)) {
1452 if (mode_is_float(mode)) {
1454 if (USE_SSE2(env->cg))
1455 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1457 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1459 else if (get_mode_size_bits(mode) == 8) {
1460 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1463 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
1466 /* stored const is an attribute (saves a register) */
1467 if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
1468 set_ia32_Immop_attr(new_op, val);
1471 /* base is an constant address */
1473 if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
1474 set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
1475 am_flav = ia32_am_N;
1478 add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
1479 am_flav = ia32_am_O;
1483 set_ia32_am_support(new_op, ia32_am_Dest);
1484 set_ia32_op_type(new_op, ia32_AddrModeD);
1485 set_ia32_am_flavour(new_op, am_flav);
1486 set_ia32_ls_mode(new_op, mode);
1487 set_ia32_immop_type(new_op, immop);
1489 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1497 * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
1499 * @param env The transformation environment
1500 * @return The transformed node.
1502 static ir_node *gen_Cond(ia32_transform_env_t *env) {
1503 dbg_info *dbg = env->dbg;
1504 ir_graph *irg = env->irg;
1505 ir_node *block = env->block;
1506 ir_node *node = env->irn;
1507 ir_node *sel = get_Cond_selector(node);
1508 ir_mode *sel_mode = get_irn_mode(sel);
1509 ir_node *res = NULL;
1510 ir_node *pred = NULL;
1511 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1512 ir_node *cmp_a, *cmp_b, *cnst, *expr;
1514 if (is_Proj(sel) && sel_mode == mode_b) {
1515 ir_node *nomem = new_NoMem();
1517 pred = get_Proj_pred(sel);
1519 /* get both compare operators */
1520 cmp_a = get_Cmp_left(pred);
1521 cmp_b = get_Cmp_right(pred);
1523 /* check if we can use a CondJmp with immediate */
1524 cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
1525 expr = get_expr_op(cmp_a, cmp_b);
1528 pn_Cmp pnc = get_Proj_proj(sel);
1530 if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
1531 if (get_ia32_op_type(cnst) == ia32_Const &&
1532 classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
1534 /* a Cmp A =/!= 0 */
1535 ir_node *op1 = expr;
1536 ir_node *op2 = expr;
1537 ir_node *and = skip_Proj(expr);
1538 const char *cnst = NULL;
1540 /* check, if expr is an only once used And operation */
1541 if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
1542 op1 = get_irn_n(and, 2);
1543 op2 = get_irn_n(and, 3);
1545 cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
1547 res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
1548 set_ia32_pncode(res, get_Proj_proj(sel));
1549 set_ia32_res_mode(res, get_irn_mode(op1));
1552 copy_ia32_Immop_attr(res, and);
1555 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1560 if (mode_is_float(get_irn_mode(expr))) {
1562 if (USE_SSE2(env->cg))
1563 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1569 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
1571 set_ia32_Immop_attr(res, cnst);
1572 set_ia32_res_mode(res, get_irn_mode(expr));
1575 if (mode_is_float(get_irn_mode(cmp_a))) {
1577 if (USE_SSE2(env->cg))
1578 res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1581 res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1582 proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
1583 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
1587 res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1588 set_ia32_commutative(res);
1590 set_ia32_res_mode(res, get_irn_mode(cmp_a));
1593 set_ia32_pncode(res, get_Proj_proj(sel));
1594 //set_ia32_am_support(res, ia32_am_Source);
1597 /* determine the smallest switch case value */
1598 int switch_min = INT_MAX;
1599 const ir_edge_t *edge;
1602 foreach_out_edge(node, edge) {
1603 int pn = get_Proj_proj(get_edge_src_irn(edge));
1604 switch_min = pn < switch_min ? pn : switch_min;
1608 /* if smallest switch case is not 0 we need an additional sub */
1609 snprintf(buf, sizeof(buf), "%d", switch_min);
1610 res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
1611 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1612 sub_ia32_am_offs(res, buf);
1613 set_ia32_am_flavour(res, ia32_am_OB);
1614 set_ia32_am_support(res, ia32_am_Source);
1615 set_ia32_op_type(res, ia32_AddrModeS);
1618 res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
1619 set_ia32_pncode(res, get_Cond_defaultProj(node));
1620 set_ia32_res_mode(res, get_irn_mode(sel));
1623 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1630 * Transforms a CopyB node.
1632 * @param env The transformation environment
1633 * @return The transformed node.
1635 static ir_node *gen_CopyB(ia32_transform_env_t *env) {
1636 ir_node *res = NULL;
1637 dbg_info *dbg = env->dbg;
1638 ir_graph *irg = env->irg;
1639 ir_node *block = env->block;
1640 ir_node *node = env->irn;
1641 ir_node *src = get_CopyB_src(node);
1642 ir_node *dst = get_CopyB_dst(node);
1643 ir_node *mem = get_CopyB_mem(node);
1644 int size = get_type_size_bytes(get_CopyB_type(node));
1645 ir_mode *dst_mode = get_irn_mode(dst);
1646 ir_mode *src_mode = get_irn_mode(src);
1648 ir_node *in[3], *tmp;
1650 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
1651 /* then we need the size explicitly in ECX. */
1652 if (size >= 32 * 4) {
1653 rem = size & 0x3; /* size % 4 */
1656 res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
1657 set_ia32_op_type(res, ia32_Const);
1658 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1660 res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
1661 set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
1663 /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
1664 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
1665 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
1666 in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
1667 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
1669 tmp = ia32_get_proj_for_mode(node, mode_M);
1670 set_Proj_proj(tmp, pn_ia32_CopyB_M);
1673 res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
1674 set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
1675 set_ia32_immop_type(res, ia32_ImmConst);
1677 /* ok: now attach Proj's because movsd will destroy esi and edi */
1678 in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
1679 in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
1680 be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
1682 tmp = ia32_get_proj_for_mode(node, mode_M);
1683 set_Proj_proj(tmp, pn_ia32_CopyB_i_M);
1686 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
1694 * Transforms a Mux node into CMov.
1696 * @param env The transformation environment
1697 * @return The transformed node.
1699 static ir_node *gen_Mux(ia32_transform_env_t *env) {
1701 ir_node *node = env->irn;
1702 ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
1703 get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
1705 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
1712 typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
1713 ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
1716 * Transforms a Psi node into CMov.
1718 * @param env The transformation environment
1719 * @return The transformed node.
1721 static ir_node *gen_Psi(ia32_transform_env_t *env) {
1722 ia32_code_gen_t *cg = env->cg;
1723 dbg_info *dbg = env->dbg;
1724 ir_graph *irg = env->irg;
1725 ir_mode *mode = env->mode;
1726 ir_node *block = env->block;
1727 ir_node *node = env->irn;
1728 ir_node *cmp_proj = get_Mux_sel(node);
1729 ir_node *psi_true = get_Psi_val(node, 0);
1730 ir_node *psi_default = get_Psi_default(node);
1731 ir_node *noreg = ia32_new_NoReg_gp(cg);
1732 ir_node *nomem = new_rd_NoMem(irg);
1733 ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
1736 assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
1738 cmp = get_Proj_pred(cmp_proj);
1739 cmp_a = get_Cmp_left(cmp);
1740 cmp_b = get_Cmp_right(cmp);
1741 pnc = get_Proj_proj(cmp_proj);
1743 if (mode_is_float(mode)) {
1744 /* floating point psi */
1747 /* 1st case: compare operands are float too */
1749 /* psi(cmp(a, b), t, f) can be done as: */
1750 /* tmp = cmp a, b */
1751 /* tmp2 = t and tmp */
1752 /* tmp3 = f and not tmp */
1753 /* res = tmp2 or tmp3 */
1755 /* in case the compare operands are int, we move them into xmm register */
1756 if (! mode_is_float(get_irn_mode(cmp_a))) {
1757 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
1758 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
1760 pnc |= 8; /* transform integer compare to fp compare */
1763 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
1764 set_ia32_pncode(new_op, pnc);
1765 set_ia32_am_support(new_op, ia32_am_Source);
1766 set_ia32_res_mode(new_op, mode);
1767 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1768 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
1770 and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
1771 set_ia32_am_support(and1, ia32_am_None);
1772 set_ia32_res_mode(and1, mode);
1773 set_ia32_commutative(and1);
1774 SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
1775 and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
1777 and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
1778 set_ia32_am_support(and2, ia32_am_None);
1779 set_ia32_res_mode(and2, mode);
1780 set_ia32_commutative(and2);
1781 SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
1782 and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
1784 new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
1785 set_ia32_am_support(new_op, ia32_am_None);
1786 set_ia32_res_mode(new_op, mode);
1787 set_ia32_commutative(new_op);
1788 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1789 new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
1793 new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1794 set_ia32_pncode(new_op, pnc);
1795 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
1800 construct_binop_func *set_func = NULL;
1801 cmov_func_t *cmov_func = NULL;
1803 if (mode_is_float(get_irn_mode(cmp_a))) {
1804 /* 1st case: compare operands are floats */
1809 set_func = new_rd_ia32_xCmpSet;
1810 cmov_func = new_rd_ia32_xCmpCMov;
1814 set_func = new_rd_ia32_vfCmpSet;
1815 cmov_func = new_rd_ia32_vfCmpCMov;
1818 pnc &= 7; /* fp compare -> int compare */
1821 /* 2nd case: compare operand are integer too */
1822 set_func = new_rd_ia32_CmpSet;
1823 cmov_func = new_rd_ia32_CmpCMov;
1826 /* create the nodes */
1828 /* check for special case first: And/Or -- Cmp with 0 -- Psi */
1829 if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
1830 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1831 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1832 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1833 set_ia32_pncode(new_op, pnc);
1835 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1836 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1837 /* we invert condition and set default to 0 */
1838 new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
1839 set_ia32_pncode(new_op, get_inversed_pnc(pnc));
1842 /* otherwise: use CMOVcc */
1843 new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
1844 set_ia32_pncode(new_op, pnc);
1847 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1851 if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
1852 /* first case for SETcc: default is 0, set to 1 iff condition is true */
1853 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1854 set_ia32_pncode(get_Proj_pred(new_op), pnc);
1855 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1857 else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
1858 /* second case for SETcc: default is 1, set to 0 iff condition is true: */
1859 /* we invert condition and set default to 0 */
1860 new_op = gen_binop(env, cmp_a, cmp_b, set_func);
1861 set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
1862 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
1865 /* otherwise: use CMOVcc */
1866 new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
1867 set_ia32_pncode(new_op, pnc);
1868 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
1878 * Following conversion rules apply:
1882 * 1) n bit -> m bit n > m (downscale)
1883 * a) target is signed: movsx
1884 * b) target is unsigned: and with lower bits sets
1885 * 2) n bit -> m bit n == m (sign change)
1887 * 3) n bit -> m bit n < m (upscale)
1888 * a) source is signed: movsx
1889 * b) source is unsigned: and with lower bits sets
1893 * SSE(1/2) convert to float or double (cvtsi2ss/sd)
1897 * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
1898 * if target mode < 32bit: additional INT -> INT conversion (see above)
1902 * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
1903 * x87 is mode_E internally, conversions happen only at load and store
1904 * in non-strict semantic
1908 * Create a conversion from x87 state register to general purpose.
1910 static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
1911 ia32_code_gen_t *cg = env->cg;
1912 entity *ent = cg->fp_to_gp;
1913 ir_graph *irg = env->irg;
1914 ir_node *block = env->block;
1915 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1916 ir_node *op = get_Conv_op(env->irn);
1917 ir_node *fist, *mem, *load;
1920 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
1921 ent = cg->fp_to_gp =
1922 frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
1926 fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg));
1928 set_ia32_frame_ent(fist, ent);
1929 set_ia32_use_frame(fist);
1930 set_ia32_am_support(fist, ia32_am_Dest);
1931 set_ia32_op_type(fist, ia32_AddrModeD);
1932 set_ia32_am_flavour(fist, ia32_B);
1933 set_ia32_ls_mode(fist, mode_F);
1935 mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
1938 load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1940 set_ia32_frame_ent(load, ent);
1941 set_ia32_use_frame(load);
1942 set_ia32_am_support(load, ia32_am_Source);
1943 set_ia32_op_type(load, ia32_AddrModeS);
1944 set_ia32_am_flavour(load, ia32_B);
1945 set_ia32_ls_mode(load, tgt_mode);
1947 return new_r_Proj(irg, block, load, tgt_mode, pn_ia32_Load_res);
1951 * Create a conversion from x87 state register to general purpose.
1953 static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
1954 ia32_code_gen_t *cg = env->cg;
1955 entity *ent = cg->gp_to_fp;
1956 ir_graph *irg = env->irg;
1957 ir_node *block = env->block;
1958 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
1959 ir_node *nomem = get_irg_no_mem(irg);
1960 ir_node *op = get_Conv_op(env->irn);
1961 ir_node *fild, *store, *mem;
1965 int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
1966 ent = cg->gp_to_fp =
1967 frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
1970 /* first convert to 32 bit */
1971 src_bits = get_mode_size_bits(src_mode);
1972 if (src_bits == 8) {
1973 op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem);
1974 op = new_r_Proj(irg, block, op, mode_Is, 0);
1976 else if (src_bits < 32) {
1977 op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem);
1978 op = new_r_Proj(irg, block, op, mode_Is, 0);
1982 store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem);
1984 set_ia32_frame_ent(store, ent);
1985 set_ia32_use_frame(store);
1987 set_ia32_am_support(store, ia32_am_Dest);
1988 set_ia32_op_type(store, ia32_AddrModeD);
1989 set_ia32_am_flavour(store, ia32_B);
1990 set_ia32_ls_mode(store, mode_Is);
1992 mem = new_r_Proj(irg, block, store, mode_M, 0);
1995 fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
1997 set_ia32_frame_ent(fild, ent);
1998 set_ia32_use_frame(fild);
1999 set_ia32_am_support(fild, ia32_am_Source);
2000 set_ia32_op_type(fild, ia32_AddrModeS);
2001 set_ia32_am_flavour(fild, ia32_B);
2002 set_ia32_ls_mode(fild, mode_F);
2004 return new_r_Proj(irg, block, fild, mode_F, 0);
2008 * Transforms a Conv node.
2010 * @param env The transformation environment
2011 * @return The created ia32 Conv node
2013 static ir_node *gen_Conv(ia32_transform_env_t *env) {
2014 dbg_info *dbg = env->dbg;
2015 ir_graph *irg = env->irg;
2016 ir_node *op = get_Conv_op(env->irn);
2017 ir_mode *src_mode = get_irn_mode(op);
2018 ir_mode *tgt_mode = env->mode;
2019 int src_bits = get_mode_size_bits(src_mode);
2020 int tgt_bits = get_mode_size_bits(tgt_mode);
2023 ir_node *block = env->block;
2024 ir_node *new_op = NULL;
2025 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2026 ir_node *nomem = new_rd_NoMem(irg);
2028 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2030 if (src_mode == tgt_mode) {
2031 /* this can happen when changing mode_P to mode_Is */
2032 DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
2033 edges_reroute(env->irn, op, irg);
2035 else if (mode_is_float(src_mode)) {
2036 /* we convert from float ... */
2037 if (mode_is_float(tgt_mode)) {
2039 if (USE_SSE2(env->cg)) {
2040 DB((mod, LEVEL_1, "create Conv(float, float) ..."));
2041 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2042 pn = pn_ia32_Conv_FP2FP_res;
2045 DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
2047 remark: we create a intermediate conv here, so modes will be spread correctly
2048 these convs will be killed later
2050 new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
2051 pn = pn_ia32_Conv_FP2FP_res;
2057 DB((mod, LEVEL_1, "create Conv(float, int) ..."));
2058 if (USE_SSE2(env->cg)) {
2059 new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
2060 pn = pn_ia32_Conv_FP2I_res;
2063 return gen_x87_fp_to_gp(env, tgt_mode);
2065 /* if target mode is not int: add an additional downscale convert */
2066 if (tgt_bits < 32) {
2067 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2068 set_ia32_am_support(new_op, ia32_am_Source);
2069 set_ia32_tgt_mode(new_op, tgt_mode);
2070 set_ia32_src_mode(new_op, src_mode);
2072 proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
2074 if (tgt_bits == 8 || src_bits == 8) {
2075 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
2076 pn = pn_ia32_Conv_I2I8Bit_res;
2079 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
2080 pn = pn_ia32_Conv_I2I_res;
2086 /* we convert from int ... */
2087 if (mode_is_float(tgt_mode)) {
2090 DB((mod, LEVEL_1, "create Conv(int, float) ..."));
2091 if (USE_SSE2(env->cg)) {
2092 new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
2093 pn = pn_ia32_Conv_I2FP_res;
2096 return gen_x87_gp_to_fp(env, src_mode);
2100 if (get_mode_size_bits(src_mode) == tgt_bits) {
2101 DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
2103 remark: we create a intermediate conv here, so modes will be spread correctly
2104 these convs will be killed later
2106 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2107 pn = pn_ia32_Conv_I2I_res;
2111 DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2112 if (tgt_bits == 8 || src_bits == 8) {
2113 new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
2114 pn = pn_ia32_Conv_I2I8Bit_res;
2117 new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
2118 pn = pn_ia32_Conv_I2I_res;
2125 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2126 set_ia32_tgt_mode(new_op, tgt_mode);
2127 set_ia32_src_mode(new_op, src_mode);
2129 set_ia32_am_support(new_op, ia32_am_Source);
2131 new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
2134 nodeset_insert(env->cg->kill_conv, new_op);
2142 /********************************************
2145 * | |__ ___ _ __ ___ __| | ___ ___
2146 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
2147 * | |_) | __/ | | | (_) | (_| | __/\__ \
2148 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
2150 ********************************************/
2154 * Decides in which block the transformed StackParam should be placed.
2155 * If the StackParam has more than one user, the dominator block of
2156 * the users will be returned. In case of only one user, this is either
2157 * the user block or, in case of a Phi, the predecessor block of the Phi.
2159 static ir_node *get_block_transformed_stack_param(ir_node *irn) {
2160 ir_node *dom_bl = NULL;
2162 if (get_irn_n_edges(irn) == 1) {
2163 ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
2165 if (! is_Phi(src)) {
2166 dom_bl = get_nodes_block(src);
2169 /* Determine on which in position of the Phi the irn is */
2170 /* and get the corresponding cfg predecessor block. */
2172 int i = get_irn_pred_pos(src, irn);
2173 assert(i >= 0 && "kaputt");
2174 dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
2178 dom_bl = node_users_smallest_common_dominator(irn, 1);
2181 assert(dom_bl && "dominator block not found");
2187 static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
2188 ir_node *new_op = NULL;
2189 ir_node *node = env->irn;
2190 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2191 ir_node *mem = new_rd_NoMem(env->irg);
2192 ir_node *ptr = get_irn_n(node, 0);
2193 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2194 ir_mode *mode = env->mode;
2196 /* choose the block where to place the load */
2197 //env->block = get_block_transformed_stack_param(node);
2199 if (mode_is_float(mode)) {
2201 if (USE_SSE2(env->cg))
2202 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2204 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2207 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2210 set_ia32_frame_ent(new_op, ent);
2211 set_ia32_use_frame(new_op);
2213 set_ia32_am_support(new_op, ia32_am_Source);
2214 set_ia32_op_type(new_op, ia32_AddrModeS);
2215 set_ia32_am_flavour(new_op, ia32_B);
2216 set_ia32_ls_mode(new_op, mode);
2217 set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
2219 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2221 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
2225 * Transforms a FrameAddr into an ia32 Add.
2227 static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
2228 ir_node *new_op = NULL;
2229 ir_node *node = env->irn;
2230 ir_node *op = get_irn_n(node, 0);
2231 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2232 ir_node *nomem = new_rd_NoMem(env->irg);
2234 new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
2235 set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node));
2236 set_ia32_am_support(new_op, ia32_am_Full);
2237 set_ia32_use_frame(new_op);
2238 set_ia32_immop_type(new_op, ia32_ImmConst);
2239 set_ia32_commutative(new_op);
2241 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2243 return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_Add_res);
2247 * Transforms a FrameLoad into an ia32 Load.
2249 static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
2250 ir_node *new_op = NULL;
2251 ir_node *node = env->irn;
2252 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2253 ir_node *mem = get_irn_n(node, 0);
2254 ir_node *ptr = get_irn_n(node, 1);
2255 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2256 ir_mode *mode = get_type_mode(get_entity_type(ent));
2258 if (mode_is_float(mode)) {
2260 if (USE_SSE2(env->cg))
2261 new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
2263 new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2266 new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
2268 set_ia32_frame_ent(new_op, ent);
2269 set_ia32_use_frame(new_op);
2271 set_ia32_am_support(new_op, ia32_am_Source);
2272 set_ia32_op_type(new_op, ia32_AddrModeS);
2273 set_ia32_am_flavour(new_op, ia32_B);
2274 set_ia32_ls_mode(new_op, mode);
2276 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2283 * Transforms a FrameStore into an ia32 Store.
2285 static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
2286 ir_node *new_op = NULL;
2287 ir_node *node = env->irn;
2288 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2289 ir_node *mem = get_irn_n(node, 0);
2290 ir_node *ptr = get_irn_n(node, 1);
2291 ir_node *val = get_irn_n(node, 2);
2292 entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
2293 ir_mode *mode = get_irn_mode(val);
2295 if (mode_is_float(mode)) {
2297 if (USE_SSE2(env->cg))
2298 new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2300 new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2302 else if (get_mode_size_bits(mode) == 8) {
2303 new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2306 new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2309 set_ia32_frame_ent(new_op, ent);
2310 set_ia32_use_frame(new_op);
2312 set_ia32_am_support(new_op, ia32_am_Dest);
2313 set_ia32_op_type(new_op, ia32_AddrModeD);
2314 set_ia32_am_flavour(new_op, ia32_B);
2315 set_ia32_ls_mode(new_op, mode);
2317 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2323 * In case SSE is used we need to copy the result from FPU TOS.
2325 static ir_node *gen_be_Call(ia32_transform_env_t *env) {
2326 ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
2327 ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
2330 if (! call_res || ! USE_SSE2(env->cg))
2333 mode = get_irn_mode(call_res);
2335 /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
2337 call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular);
2339 if (mode_is_float(mode)) {
2340 /* store st(0) onto stack */
2341 ir_node *frame = get_irg_frame(env->irg);
2342 ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
2343 ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
2344 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2347 set_ia32_ls_mode(fstp, mode);
2348 set_ia32_op_type(fstp, ia32_AddrModeD);
2349 set_ia32_use_frame(fstp);
2350 set_ia32_frame_ent(fstp, ent);
2351 set_ia32_am_flavour(fstp, ia32_B);
2352 set_ia32_am_support(fstp, ia32_am_Dest);
2354 /* load into SSE register */
2355 sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
2356 set_ia32_ls_mode(sse_load, mode);
2357 set_ia32_op_type(sse_load, ia32_AddrModeS);
2358 set_ia32_use_frame(sse_load);
2359 set_ia32_frame_ent(sse_load, ent);
2360 set_ia32_am_flavour(sse_load, ia32_B);
2361 set_ia32_am_support(sse_load, ia32_am_Source);
2362 sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
2364 /* reroute all users of the result proj to the sse load */
2365 edges_reroute(call_res, sse_load, env->irg);
2372 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
2374 static ir_node *gen_be_Return(ia32_transform_env_t *env) {
2375 ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
2376 ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
2377 entity *ent = get_irg_entity(get_irn_irg(ret_val));
2378 ir_type *tp = get_entity_type(ent);
2380 if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
2384 if (get_method_n_ress(tp) == 1) {
2385 ir_type *res_type = get_method_res_type(tp, 0);
2388 if(is_Primitive_type(res_type)) {
2389 mode = get_type_mode(res_type);
2390 if(mode_is_float(mode)) {
2391 ir_node *frame = get_irg_frame(env->irg);
2392 entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
2393 ir_node *sse_store, *fld, *mproj;
2395 /* store xmm0 onto stack */
2396 sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
2397 set_ia32_ls_mode(sse_store, mode);
2398 set_ia32_op_type(sse_store, ia32_AddrModeD);
2399 set_ia32_use_frame(sse_store);
2400 set_ia32_frame_ent(sse_store, ent);
2401 set_ia32_am_flavour(sse_store, ia32_B);
2402 set_ia32_am_support(sse_store, ia32_am_Dest);
2403 sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
2406 fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
2407 set_ia32_ls_mode(fld, mode);
2408 set_ia32_op_type(fld, ia32_AddrModeS);
2409 set_ia32_use_frame(fld);
2410 set_ia32_frame_ent(fld, ent);
2411 set_ia32_am_flavour(fld, ia32_B);
2412 set_ia32_am_support(fld, ia32_am_Source);
2413 mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
2414 fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
2416 /* set new return value */
2417 set_irn_n(env->irn, be_pos_Return_val, fld);
2418 set_irn_n(env->irn, be_pos_Return_mem, mproj);
2427 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
2429 static ir_node *gen_be_AddSP(ia32_transform_env_t *env) {
2431 const ir_edge_t *edge;
2432 ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size);
2433 ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp);
2435 new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz);
2437 if (is_ia32_Const(sz)) {
2438 set_ia32_Immop_attr(new_op, sz);
2439 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2441 else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
2442 set_ia32_immop_type(new_op, ia32_ImmSymConst);
2443 set_ia32_op_type(new_op, ia32_AddrModeS);
2444 set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
2445 add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
2446 set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
2450 foreach_out_edge(env->irn, edge) {
2451 ir_node *proj = get_edge_src_irn(edge);
2453 assert(is_Proj(proj));
2455 if (get_Proj_proj(proj) == pn_be_AddSP_res) {
2456 /* the node is not yet exchanged: we need to set the register manually */
2457 ia32_attr_t *attr = get_ia32_attr(new_op);
2458 attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP];
2459 set_Proj_proj(proj, pn_ia32_AddSP_stack);
2461 else if (get_Proj_proj(proj) == pn_be_AddSP_M) {
2462 set_Proj_proj(proj, pn_ia32_AddSP_M);
2469 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2475 * This function just sets the register for the Unknown node
2476 * as this is not done during register allocation because Unknown
2477 * is an "ignore" node.
2479 static ir_node *gen_Unknown(ia32_transform_env_t *env) {
2480 ir_mode *mode = env->mode;
2481 ir_node *irn = env->irn;
2483 if (mode_is_float(mode)) {
2484 if (USE_SSE2(env->cg))
2485 arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
2487 arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
2489 else if (mode_is_int(mode) || mode_is_reference(mode)) {
2490 arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
2493 assert(0 && "unsupported Unknown-Mode");
2499 /**********************************************************************
2502 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
2503 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
2504 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
2505 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
2507 **********************************************************************/
2509 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
2511 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2514 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
2515 ir_node *val, ir_node *mem);
2518 * Transforms a lowered Load into a "real" one.
2520 static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
2521 ir_node *node = env->irn;
2522 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2523 ir_mode *mode = get_ia32_ls_mode(node);
2526 ia32_am_flavour_t am_flav = ia32_B;
2529 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2530 lowering we have x87 nodes, so we need to enforce simulation.
2532 if (mode_is_float(mode)) {
2534 if (fp_unit == fp_x87)
2538 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
2539 am_offs = get_ia32_am_offs(node);
2543 add_ia32_am_offs(new_op, am_offs);
2546 set_ia32_am_support(new_op, ia32_am_Source);
2547 set_ia32_op_type(new_op, ia32_AddrModeS);
2548 set_ia32_am_flavour(new_op, am_flav);
2549 set_ia32_ls_mode(new_op, mode);
2550 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2551 set_ia32_use_frame(new_op);
2553 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2559 * Transforms a lowered Store into a "real" one.
2561 static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
2562 ir_node *node = env->irn;
2563 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2564 ir_mode *mode = get_ia32_ls_mode(node);
2567 ia32_am_flavour_t am_flav = ia32_B;
2570 Could be that we have SSE2 unit, but due to 64Bit Div/Conv
2571 lowering we have x87 nodes, so we need to enforce simulation.
2573 if (mode_is_float(mode)) {
2575 if (fp_unit == fp_x87)
2579 new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
2581 if ((am_offs = get_ia32_am_offs(node)) != NULL) {
2583 add_ia32_am_offs(new_op, am_offs);
2586 set_ia32_am_support(new_op, ia32_am_Dest);
2587 set_ia32_op_type(new_op, ia32_AddrModeD);
2588 set_ia32_am_flavour(new_op, am_flav);
2589 set_ia32_ls_mode(new_op, mode);
2590 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
2591 set_ia32_use_frame(new_op);
2593 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
2600 * Transforms an ia32_l_XXX into a "real" XXX node
2602 * @param env The transformation environment
2603 * @return the created ia32 XXX node
2605 #define GEN_LOWERED_OP(op) \
2606 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2607 if (mode_is_float(env->mode)) \
2609 return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2612 #define GEN_LOWERED_x87_OP(op) \
2613 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2615 FORCE_x87(env->cg); \
2616 new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2617 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
2621 #define GEN_LOWERED_UNOP(op) \
2622 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2623 return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
2626 #define GEN_LOWERED_SHIFT_OP(op) \
2627 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2628 return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
2631 #define GEN_LOWERED_LOAD(op, fp_unit) \
2632 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2633 return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
2636 #define GEN_LOWERED_STORE(op, fp_unit) \
2637 static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
2638 return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
2641 GEN_LOWERED_OP(AddC)
2643 GEN_LOWERED_OP(SubC)
2647 GEN_LOWERED_x87_OP(vfdiv)
2648 GEN_LOWERED_x87_OP(vfmul)
2649 GEN_LOWERED_x87_OP(vfsub)
2651 GEN_LOWERED_UNOP(Minus)
2653 GEN_LOWERED_LOAD(vfild, fp_x87)
2654 GEN_LOWERED_LOAD(Load, fp_none)
2655 GEN_LOWERED_STORE(vfist, fp_x87)
2656 GEN_LOWERED_STORE(Store, fp_none)
2659 * Transforms a l_MulS into a "real" MulS node.
2661 * @param env The transformation environment
2662 * @return the created ia32 MulS node
2664 static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env) {
2666 /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
2667 /* and then skip the result Proj, because all needed Projs are already there. */
2669 ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
2670 ir_node *muls = get_Proj_pred(new_op);
2672 /* MulS cannot have AM for destination */
2673 if (get_ia32_am_support(muls) != ia32_am_None)
2674 set_ia32_am_support(muls, ia32_am_Source);
2679 GEN_LOWERED_SHIFT_OP(Shl)
2680 GEN_LOWERED_SHIFT_OP(Shr)
2681 GEN_LOWERED_SHIFT_OP(Shrs)
2684 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
2685 * op1 - target to be shifted
2686 * op2 - contains bits to be shifted into target
2688 * Only op3 can be an immediate.
2690 static ir_node *gen_lowered_64bit_shifts(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, ir_node *count) {
2691 ir_node *new_op = NULL;
2692 ir_mode *mode = env->mode;
2693 dbg_info *dbg = env->dbg;
2694 ir_graph *irg = env->irg;
2695 ir_node *block = env->block;
2696 ir_node *noreg = ia32_new_NoReg_gp(env->cg);
2697 ir_node *nomem = new_NoMem();
2700 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
2702 assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
2704 /* Check if immediate optimization is on and */
2705 /* if it's an operation with immediate. */
2706 imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, count) : NULL;
2708 /* Limit imm_op within range imm8 */
2710 tv = get_ia32_Immop_tarval(imm_op);
2713 tv = tarval_mod(tv, new_tarval_from_long(32, mode_Iu));
2714 set_ia32_Immop_tarval(imm_op, tv);
2721 /* integer operations */
2723 /* This is ShiftD with const */
2724 DB((mod, LEVEL_1, "ShiftD with immediate ..."));
2726 if (is_ia32_l_ShlD(env->irn))
2727 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2729 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, noreg, nomem);
2730 set_ia32_Immop_attr(new_op, imm_op);
2733 /* This is a normal ShiftD */
2734 DB((mod, LEVEL_1, "ShiftD binop ..."));
2735 if (is_ia32_l_ShlD(env->irn))
2736 new_op = new_rd_ia32_ShlD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2738 new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg, op1, op2, count, nomem);
2741 /* set AM support */
2742 set_ia32_am_support(new_op, ia32_am_Dest);
2744 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
2746 set_ia32_res_mode(new_op, mode);
2747 set_ia32_emit_cl(new_op);
2749 return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
2752 static ir_node *gen_ia32_l_ShlD(ia32_transform_env_t *env) {
2753 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2756 static ir_node *gen_ia32_l_ShrD(ia32_transform_env_t *env) {
2757 return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
2761 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
2763 static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
2764 ia32_code_gen_t *cg = env->cg;
2765 ir_node *res = NULL;
2766 ir_node *ptr = get_irn_n(env->irn, 0);
2767 ir_node *val = get_irn_n(env->irn, 1);
2768 ir_node *mem = get_irn_n(env->irn, 2);
2771 ir_node *noreg = ia32_new_NoReg_gp(cg);
2773 /* Store x87 -> MEM */
2774 res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2775 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2776 set_ia32_use_frame(res);
2777 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2778 set_ia32_am_support(res, ia32_am_Dest);
2779 set_ia32_am_flavour(res, ia32_B);
2780 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
2782 /* Load MEM -> SSE */
2783 res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
2784 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2785 set_ia32_use_frame(res);
2786 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2787 set_ia32_am_support(res, ia32_am_Source);
2788 set_ia32_am_flavour(res, ia32_B);
2789 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
2792 /* SSE unit is not used -> skip this node. */
2795 edges_reroute(env->irn, val, env->irg);
2796 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2797 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2804 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
2806 static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
2807 ia32_code_gen_t *cg = env->cg;
2808 ir_node *res = NULL;
2809 ir_node *ptr = get_irn_n(env->irn, 0);
2810 ir_node *val = get_irn_n(env->irn, 1);
2811 ir_node *mem = get_irn_n(env->irn, 2);
2814 ir_node *noreg = ia32_new_NoReg_gp(cg);
2816 /* Store SSE -> MEM */
2817 res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
2818 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2819 set_ia32_use_frame(res);
2820 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2821 set_ia32_am_support(res, ia32_am_Dest);
2822 set_ia32_am_flavour(res, ia32_B);
2823 res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
2825 /* Load MEM -> x87 */
2826 res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
2827 set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
2828 set_ia32_use_frame(res);
2829 set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
2830 set_ia32_am_support(res, ia32_am_Source);
2831 set_ia32_am_flavour(res, ia32_B);
2832 res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
2835 /* SSE unit is not used -> skip this node. */
2838 edges_reroute(env->irn, val, env->irg);
2839 for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
2840 set_irn_n(env->irn, i, get_irg_bad(env->irg));
2846 /*********************************************************
2849 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
2850 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
2851 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
2852 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
2854 *********************************************************/
2857 * the BAD transformer.
2859 static ir_node *bad_transform(ia32_transform_env_t *env) {
2860 ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
2866 * Enters all transform functions into the generic pointer
2868 void ia32_register_transformers(void) {
2869 ir_op *op_Max, *op_Min, *op_Mulh;
2871 /* first clear the generic function pointer for all ops */
2872 clear_irp_opcodes_generic_func();
2874 #define GEN(a) op_##a->ops.generic = (op_func)gen_##a
2875 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
2909 /* transform ops from intrinsic lowering */
2930 GEN(ia32_l_X87toSSE);
2931 GEN(ia32_l_SSEtoX87);
2946 /* constant transformation happens earlier */
2951 /* we should never see these nodes */
2966 /* handle generic backend nodes */
2975 /* set the register for all Unknown nodes */
2978 op_Max = get_op_Max();
2981 op_Min = get_op_Min();
2984 op_Mulh = get_op_Mulh();
2993 typedef ir_node *(transform_func)(ia32_transform_env_t *env);
2996 * Transforms the given firm node (and maybe some other related nodes)
2997 * into one or more assembler nodes.
2999 * @param node the firm node
3000 * @param env the debug module
3002 void ia32_transform_node(ir_node *node, void *env) {
3003 ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
3004 ir_op *op = get_irn_op(node);
3005 ir_node *asm_node = NULL;
3011 /* link arguments pointing to Unknown to the UNKNOWN Proj */
3012 for (i = get_irn_arity(node) - 1; i >= 0; i--) {
3013 if (is_Unknown(get_irn_n(node, i)))
3014 set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
3017 DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
3018 if (op->ops.generic) {
3019 ia32_transform_env_t tenv;
3020 transform_func *transform = (transform_func *)op->ops.generic;
3022 tenv.block = get_nodes_block(node);
3023 tenv.dbg = get_irn_dbg_info(node);
3024 tenv.irg = current_ir_graph;
3026 tenv.mode = get_irn_mode(node);
3028 DEBUG_ONLY(tenv.mod = cg->mod;)
3030 asm_node = (*transform)(&tenv);
3033 /* exchange nodes if a new one was generated */
3035 exchange(node, asm_node);
3036 DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
3039 DB((cg->mod, LEVEL_1, "ignored\n"));
3044 * Transforms a psi condition.
3046 static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
3049 /* if the mode is target mode, we have already seen this part of the tree */
3050 if (get_irn_mode(cond) == mode)
3053 assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
3055 set_irn_mode(cond, mode);
3057 for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
3058 ir_node *in = get_irn_n(cond, i);
3060 /* if in is a compare: transform into Set/xCmp */
3062 ir_node *new_op = NULL;
3063 ir_node *cmp = get_Proj_pred(in);
3064 ir_node *cmp_a = get_Cmp_left(cmp);
3065 ir_node *cmp_b = get_Cmp_right(cmp);
3066 dbg_info *dbg = get_irn_dbg_info(cmp);
3067 ir_graph *irg = get_irn_irg(cmp);
3068 ir_node *block = get_nodes_block(cmp);
3069 ir_node *noreg = ia32_new_NoReg_gp(cg);
3070 ir_node *nomem = new_rd_NoMem(irg);
3071 int pnc = get_Proj_proj(in);
3073 /* this is a compare */
3074 if (mode_is_float(mode)) {
3075 /* Psi is float, we need a floating point compare */
3078 ir_mode *m = get_irn_mode(cmp_a);
3080 if (! mode_is_float(m)) {
3081 cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
3082 cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
3084 else if (m == mode_F) {
3085 /* we convert cmp values always to double, to get correct bitmask with cmpsd */
3086 cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
3087 cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
3090 new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
3091 set_ia32_pncode(new_op, pnc);
3092 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
3101 ia32_transform_env_t tenv;
3102 construct_binop_func *set_func = NULL;
3104 if (mode_is_float(get_irn_mode(cmp_a))) {
3105 /* 1st case: compare operands are floats */
3110 set_func = new_rd_ia32_xCmpSet;
3114 set_func = new_rd_ia32_vfCmpSet;
3117 pnc &= 7; /* fp compare -> int compare */
3120 /* 2nd case: compare operand are integer too */
3121 set_func = new_rd_ia32_CmpSet;
3132 new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
3133 set_ia32_pncode(get_Proj_pred(new_op), pnc);
3134 set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
3137 /* the the new compare as in */
3138 set_irn_n(cond, i, new_op);
3141 /* another complex condition */
3142 transform_psi_cond(in, mode, cg);
3148 * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
3149 * We create a Set node, respectively a xCmp in case the Psi is a float, for each
3150 * compare, which causes the compare result to be stores in a register. The
3151 * "And"s and "Or"s are transformed later, we just have to set their mode right.
3153 void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
3154 ia32_code_gen_t *cg = env;
3155 ir_node *psi_sel, *new_cmp, *block;
3160 if (get_irn_opcode(node) != iro_Psi)
3163 psi_sel = get_Psi_cond(node, 0);
3165 /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
3166 if (is_Proj(psi_sel))
3169 mode = get_irn_mode(node);
3171 transform_psi_cond(psi_sel, mode, cg);
3173 irg = get_irn_irg(node);
3174 block = get_nodes_block(node);
3176 /* we need to compare the evaluated condition tree with 0 */
3178 /* BEWARE: new_r_Const_long works for floating point as well */
3179 new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
3180 new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
3182 set_Psi_cond(node, 0, new_cmp);