2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the IR transformation from firm into
24 * @author Christian Wuerdig, Matthias Braun
35 #include "irgraph_t.h"
40 #include "iredges_t.h"
52 #include "../benode_t.h"
53 #include "../besched.h"
55 #include "../beutil.h"
56 #include "../beirg_t.h"
57 #include "../betranshlp.h"
59 #include "bearch_ia32_t.h"
60 #include "ia32_nodes_attr.h"
61 #include "ia32_transform.h"
62 #include "ia32_new_nodes.h"
63 #include "ia32_map_regs.h"
64 #include "ia32_dbg_stat.h"
65 #include "ia32_optimize.h"
66 #include "ia32_util.h"
67 #include "ia32_address_mode.h"
69 #include "gen_ia32_regalloc_if.h"
71 #define SFP_SIGN "0x80000000"
72 #define DFP_SIGN "0x8000000000000000"
73 #define SFP_ABS "0x7FFFFFFF"
74 #define DFP_ABS "0x7FFFFFFFFFFFFFFF"
75 #define DFP_INTMAX "9223372036854775807"
77 #define TP_SFP_SIGN "ia32_sfp_sign"
78 #define TP_DFP_SIGN "ia32_dfp_sign"
79 #define TP_SFP_ABS "ia32_sfp_abs"
80 #define TP_DFP_ABS "ia32_dfp_abs"
81 #define TP_INT_MAX "ia32_int_max"
83 #define ENT_SFP_SIGN "IA32_SFP_SIGN"
84 #define ENT_DFP_SIGN "IA32_DFP_SIGN"
85 #define ENT_SFP_ABS "IA32_SFP_ABS"
86 #define ENT_DFP_ABS "IA32_DFP_ABS"
87 #define ENT_INT_MAX "IA32_INT_MAX"
89 #define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
90 #define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
92 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
94 /** hold the current code generator during transformation */
95 static ia32_code_gen_t *env_cg = NULL;
96 static ir_node *initial_fpcw = NULL;
97 static heights_t *heights = NULL;
99 extern ir_op *get_op_Mulh(void);
101 typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
102 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
103 ir_node *op1, ir_node *op2);
105 typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
106 ir_node *block, ir_node *op1, ir_node *op2);
108 typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
109 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
112 typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
113 ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
115 typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
116 ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
117 ir_node *op1, ir_node *op2, ir_node *fpcw);
119 typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
120 ir_node *block, ir_node *op);
122 /****************************************************************************************************
124 * | | | | / _| | | (_)
125 * _ __ ___ __| | ___ | |_ _ __ __ _ _ __ ___| |_ ___ _ __ _ __ ___ __ _| |_ _ ___ _ __
126 * | '_ \ / _ \ / _` |/ _ \ | __| '__/ _` | '_ \/ __| _/ _ \| '__| '_ ` _ \ / _` | __| |/ _ \| '_ \
127 * | | | | (_) | (_| | __/ | |_| | | (_| | | | \__ \ || (_) | | | | | | | | (_| | |_| | (_) | | | |
128 * |_| |_|\___/ \__,_|\___| \__|_| \__,_|_| |_|___/_| \___/|_| |_| |_| |_|\__,_|\__|_|\___/|_| |_|
130 ****************************************************************************************************/
132 static ir_node *try_create_Immediate(ir_node *node,
133 char immediate_constraint_type);
135 static ir_node *create_immediate_or_transform(ir_node *node,
136 char immediate_constraint_type);
138 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
139 dbg_info *dbgi, ir_node *block,
140 ir_node *op, ir_node *orig_node);
143 * Return true if a mode can be stored in the GP register set
145 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
146 if(mode == mode_fpcw)
148 if(get_mode_size_bits(mode) > 32)
150 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
154 * creates a unique ident by adding a number to a tag
156 * @param tag the tag string, must contain a %d if a number
159 static ident *unique_id(const char *tag)
161 static unsigned id = 0;
164 snprintf(str, sizeof(str), tag, ++id);
165 return new_id_from_str(str);
169 * Get a primitive type for a mode.
171 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
173 pmap_entry *e = pmap_find(types, mode);
178 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
179 res = new_type_primitive(new_id_from_str(buf), mode);
180 set_type_alignment_bytes(res, 16);
181 pmap_insert(types, mode, res);
189 * Get an atomic entity that is initialized with a tarval
191 static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
193 tarval *tv = get_Const_tarval(cnst);
194 pmap_entry *e = pmap_find(isa->tv_ent, tv);
199 ir_mode *mode = get_irn_mode(cnst);
200 ir_type *tp = get_Const_type(cnst);
201 if (tp == firm_unknown_type)
202 tp = get_prim_type(isa->types, mode);
204 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
206 set_entity_ld_ident(res, get_entity_ident(res));
207 set_entity_visibility(res, visibility_local);
208 set_entity_variability(res, variability_constant);
209 set_entity_allocation(res, allocation_static);
211 /* we create a new entity here: It's initialization must resist on the
213 rem = current_ir_graph;
214 current_ir_graph = get_const_code_irg();
215 set_atomic_ent_value(res, new_Const_type(tv, tp));
216 current_ir_graph = rem;
218 pmap_insert(isa->tv_ent, tv, res);
226 static int is_Const_0(ir_node *node) {
227 return is_Const(node) && is_Const_null(node);
230 static int is_Const_1(ir_node *node) {
231 return is_Const(node) && is_Const_one(node);
234 static int is_Const_Minus_1(ir_node *node) {
235 return is_Const(node) && is_Const_all_one(node);
239 * Transforms a Const.
241 static ir_node *gen_Const(ir_node *node) {
242 ir_graph *irg = current_ir_graph;
243 ir_node *old_block = get_nodes_block(node);
244 ir_node *block = be_transform_node(old_block);
245 dbg_info *dbgi = get_irn_dbg_info(node);
246 ir_mode *mode = get_irn_mode(node);
248 if (mode_is_float(mode)) {
250 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
251 ir_node *nomem = new_NoMem();
255 if (USE_SSE2(env_cg)) {
256 if (is_Const_null(node)) {
257 load = new_rd_ia32_xZero(dbgi, irg, block);
258 set_ia32_ls_mode(load, mode);
261 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
263 load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
265 set_ia32_op_type(load, ia32_AddrModeS);
266 set_ia32_am_sc(load, floatent);
267 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
268 res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
271 if (is_Const_null(node)) {
272 load = new_rd_ia32_vfldz(dbgi, irg, block);
274 } else if (is_Const_one(node)) {
275 load = new_rd_ia32_vfld1(dbgi, irg, block);
278 floatent = ia32_get_entity_for_tv(env_cg->isa, node);
280 load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
281 set_ia32_op_type(load, ia32_AddrModeS);
282 set_ia32_am_sc(load, floatent);
283 set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
284 res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
286 set_ia32_ls_mode(load, mode);
289 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
291 /* Const Nodes before the initial IncSP are a bad idea, because
292 * they could be spilled and we have no SP ready at that point yet.
293 * So add a dependency to the initial frame pointer calculation to
294 * avoid that situation.
296 if (get_irg_start_block(irg) == block) {
297 add_irn_dep(load, get_irg_frame(irg));
300 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
304 tarval *tv = get_Const_tarval(node);
307 tv = tarval_convert_to(tv, mode_Iu);
309 if(tv == get_tarval_bad() || tv == get_tarval_undefined()
311 panic("couldn't convert constant tarval (%+F)", node);
313 val = get_tarval_long(tv);
315 cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
316 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
319 get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
323 if (get_irg_start_block(irg) == block) {
324 add_irn_dep(cnst, get_irg_frame(irg));
332 * Transforms a SymConst.
334 static ir_node *gen_SymConst(ir_node *node) {
335 ir_graph *irg = current_ir_graph;
336 ir_node *old_block = get_nodes_block(node);
337 ir_node *block = be_transform_node(old_block);
338 dbg_info *dbgi = get_irn_dbg_info(node);
339 ir_mode *mode = get_irn_mode(node);
342 if (mode_is_float(mode)) {
343 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
344 ir_node *nomem = new_NoMem();
346 if (USE_SSE2(env_cg))
347 cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
349 cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
350 set_ia32_am_sc(cnst, get_SymConst_entity(node));
351 set_ia32_use_frame(cnst);
355 if(get_SymConst_kind(node) != symconst_addr_ent) {
356 panic("backend only support symconst_addr_ent (at %+F)", node);
358 entity = get_SymConst_entity(node);
359 cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
362 /* Const Nodes before the initial IncSP are a bad idea, because
363 * they could be spilled and we have no SP ready at that point yet
365 if (get_irg_start_block(irg) == block) {
366 add_irn_dep(cnst, get_irg_frame(irg));
369 SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
374 /* Generates an entity for a known FP const (used for FP Neg + Abs) */
375 ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct) {
376 static const struct {
378 const char *ent_name;
379 const char *cnst_str;
382 } names [ia32_known_const_max] = {
383 { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
384 { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
385 { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
386 { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
387 { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
389 static ir_entity *ent_cache[ia32_known_const_max];
391 const char *tp_name, *ent_name, *cnst_str;
399 ent_name = names[kct].ent_name;
400 if (! ent_cache[kct]) {
401 tp_name = names[kct].tp_name;
402 cnst_str = names[kct].cnst_str;
404 switch (names[kct].mode) {
405 case 0: mode = mode_Iu; break;
406 case 1: mode = mode_Lu; break;
407 default: mode = mode_F; break;
409 tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
410 tp = new_type_primitive(new_id_from_str(tp_name), mode);
411 /* set the specified alignment */
412 set_type_alignment_bytes(tp, names[kct].align);
414 ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
416 set_entity_ld_ident(ent, get_entity_ident(ent));
417 set_entity_visibility(ent, visibility_local);
418 set_entity_variability(ent, variability_constant);
419 set_entity_allocation(ent, allocation_static);
421 /* we create a new entity here: It's initialization must resist on the
423 rem = current_ir_graph;
424 current_ir_graph = get_const_code_irg();
425 cnst = new_Const(mode, tv);
426 current_ir_graph = rem;
428 set_atomic_ent_value(ent, cnst);
430 /* cache the entry */
431 ent_cache[kct] = ent;
434 return ent_cache[kct];
439 * Prints the old node name on cg obst and returns a pointer to it.
441 const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
442 ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
444 lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
445 obstack_1grow(isa->name_obst, 0);
446 return obstack_finish(isa->name_obst);
450 static int use_source_address_mode(ir_node *block, ir_node *node,
459 load = get_Proj_pred(node);
460 pn = get_Proj_proj(node);
461 if(!is_Load(load) || pn != pn_Load_res)
463 if(get_nodes_block(load) != block)
465 /* we only use address mode if we're the only user of the load */
466 if(get_irn_n_edges(node) > 1)
469 mode = get_irn_mode(node);
470 if(!mode_needs_gp_reg(mode))
472 if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
475 /* don't do AM if other node inputs depend on the load (via mem-proj) */
476 if(other != NULL && get_nodes_block(other) == block
477 && heights_reachable_in_block(heights, other, load))
483 typedef struct ia32_address_mode_t ia32_address_mode_t;
484 struct ia32_address_mode_t {
488 ia32_op_type_t op_type;
495 static void build_address(ia32_address_mode_t *am, ir_node *node)
497 ia32_address_t *addr = &am->addr;
498 ir_node *load = get_Proj_pred(node);
499 ir_node *ptr = get_Load_ptr(load);
500 ir_node *mem = get_Load_mem(load);
501 ir_node *new_mem = be_transform_node(mem);
505 am->ls_mode = get_Load_mode(load);
506 am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
508 /* construct load address */
509 ia32_create_address_mode(addr, ptr, 0);
514 base = ia32_new_NoReg_gp(env_cg);
516 base = be_transform_node(base);
520 index = ia32_new_NoReg_gp(env_cg);
522 index = be_transform_node(index);
530 static void set_address(ir_node *node, ia32_address_t *addr)
532 set_ia32_am_scale(node, addr->scale);
533 set_ia32_am_sc(node, addr->symconst_ent);
534 set_ia32_am_offs_int(node, addr->offset);
535 if(addr->symconst_sign)
536 set_ia32_am_sc_sign(node);
538 set_ia32_use_frame(node);
539 set_ia32_frame_ent(node, addr->frame_entity);
542 static void set_am_attributes(ir_node *node, ia32_address_mode_t *am)
544 set_address(node, &am->addr);
546 set_ia32_op_type(node, am->op_type);
547 set_ia32_ls_mode(node, am->ls_mode);
549 set_ia32_commutative(node);
553 match_commutative = 1 << 0,
554 match_am_and_immediates = 1 << 1,
555 match_no_am = 1 << 2,
556 match_8_16_bit_am = 1 << 3
559 static void match_arguments(ia32_address_mode_t *am, ir_node *block,
560 ir_node *op1, ir_node *op2, match_flags_t flags)
562 ia32_address_t *addr = &am->addr;
563 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
568 int use_am_and_immediates;
570 memset(am, 0, sizeof(am[0]));
572 commutative = (flags & match_commutative) != 0;
573 use_am_and_immediates = (flags & match_am_and_immediates) != 0;
574 use_am = ! (flags & match_no_am);
575 if(!(flags & match_8_16_bit_am)
576 && get_mode_size_bits(get_irn_mode(op1)) < 32)
579 new_op2 = try_create_Immediate(op2, 0);
580 if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
581 build_address(am, op2);
582 new_op1 = be_transform_node(op1);
584 am->op_type = ia32_AddrModeS;
585 } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
586 use_am && use_source_address_mode(block, op1, op2)) {
587 build_address(am, op1);
588 if(new_op2 != NULL) {
591 new_op1 = be_transform_node(op2);
595 am->op_type = ia32_AddrModeS;
597 new_op1 = be_transform_node(op1);
599 new_op2 = be_transform_node(op2);
600 am->op_type = ia32_Normal;
602 if(addr->base == NULL)
603 addr->base = noreg_gp;
604 if(addr->index == NULL)
605 addr->index = noreg_gp;
606 if(addr->mem == NULL)
607 addr->mem = new_NoMem();
609 am->new_op1 = new_op1;
610 am->new_op2 = new_op2;
611 am->commutative = commutative;
614 static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
616 ir_graph *irg = current_ir_graph;
620 if(am->mem_proj == NULL)
623 /* we have to create a mode_T so the old MemProj can attach to us */
624 mode = get_irn_mode(node);
625 load = get_Proj_pred(am->mem_proj);
627 mark_irn_visited(load);
628 be_set_transformed_node(load, node);
631 set_irn_mode(node, mode_T);
632 return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
639 * Construct a standard binary operation, set AM and immediate if required.
641 * @param op1 The first operand
642 * @param op2 The second operand
643 * @param func The node constructor function
644 * @return The constructed ia32 node.
646 static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
647 construct_binop_func *func, int commutative)
649 ir_node *src_block = get_nodes_block(node);
650 ir_node *block = be_transform_node(src_block);
651 ir_graph *irg = current_ir_graph;
652 dbg_info *dbgi = get_irn_dbg_info(node);
654 ia32_address_mode_t am;
655 ia32_address_t *addr = &am.addr;
656 match_flags_t flags = 0;
659 flags |= match_commutative;
661 match_arguments(&am, src_block, op1, op2, flags);
663 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
664 am.new_op1, am.new_op2);
665 set_am_attributes(new_node, &am);
666 /* we can't use source address mode anymore when using immediates */
667 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
668 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
669 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
671 new_node = fix_mem_proj(new_node, &am);
677 * Construct a standard binary operation, set AM and immediate if required.
679 * @param op1 The first operand
680 * @param op2 The second operand
681 * @param func The node constructor function
682 * @return The constructed ia32 node.
684 static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
685 construct_binop_func *func)
687 ir_node *block = be_transform_node(get_nodes_block(node));
688 ir_node *new_op1 = be_transform_node(op1);
689 ir_node *new_op2 = be_transform_node(op2);
690 ir_node *new_node = NULL;
691 dbg_info *dbgi = get_irn_dbg_info(node);
692 ir_graph *irg = current_ir_graph;
693 ir_mode *mode = get_irn_mode(node);
694 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
695 ir_node *nomem = new_NoMem();
697 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
699 if (is_op_commutative(get_irn_op(node))) {
700 set_ia32_commutative(new_node);
702 set_ia32_ls_mode(new_node, mode);
704 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
709 static ir_node *get_fpcw(void)
712 if(initial_fpcw != NULL)
715 fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
716 &ia32_fp_cw_regs[REG_FPCW]);
717 initial_fpcw = be_transform_node(fpcw);
723 * Construct a standard binary operation, set AM and immediate if required.
725 * @param op1 The first operand
726 * @param op2 The second operand
727 * @param func The node constructor function
728 * @return The constructed ia32 node.
730 static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
731 construct_binop_float_func *func)
733 ir_node *block = be_transform_node(get_nodes_block(node));
734 ir_node *new_op1 = be_transform_node(op1);
735 ir_node *new_op2 = be_transform_node(op2);
736 ir_node *new_node = NULL;
737 dbg_info *dbgi = get_irn_dbg_info(node);
738 ir_graph *irg = current_ir_graph;
739 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
740 ir_node *nomem = new_NoMem();
742 new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
744 if (is_op_commutative(get_irn_op(node))) {
745 set_ia32_commutative(new_node);
748 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
754 * Construct a shift/rotate binary operation, sets AM and immediate if required.
756 * @param op1 The first operand
757 * @param op2 The second operand
758 * @param func The node constructor function
759 * @return The constructed ia32 node.
761 static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
762 construct_shift_func *func)
764 dbg_info *dbgi = get_irn_dbg_info(node);
765 ir_graph *irg = current_ir_graph;
766 ir_node *block = get_nodes_block(node);
767 ir_node *new_block = be_transform_node(block);
768 ir_node *new_op1 = be_transform_node(op1);
769 ir_node *new_op2 = create_immediate_or_transform(op2, 0);
772 assert(! mode_is_float(get_irn_mode(node))
773 && "Shift/Rotate with float not supported");
775 res = func(dbgi, irg, new_block, new_op1, new_op2);
776 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
778 /* lowered shift instruction may have a dependency operand, handle it here */
779 if (get_irn_arity(node) == 3) {
780 /* we have a dependency */
781 ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
782 add_irn_dep(res, new_dep);
790 * Construct a standard unary operation, set AM and immediate if required.
792 * @param op The operand
793 * @param func The node constructor function
794 * @return The constructed ia32 node.
796 static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
798 ir_node *block = be_transform_node(get_nodes_block(node));
799 ir_node *new_op = be_transform_node(op);
800 ir_node *new_node = NULL;
801 ir_graph *irg = current_ir_graph;
802 dbg_info *dbgi = get_irn_dbg_info(node);
804 new_node = func(dbgi, irg, block, new_op);
806 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
811 static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
812 ia32_address_t *addr)
814 ir_graph *irg = current_ir_graph;
815 ir_node *base = addr->base;
816 ir_node *index = addr->index;
820 base = ia32_new_NoReg_gp(env_cg);
822 base = be_transform_node(base);
826 index = ia32_new_NoReg_gp(env_cg);
828 index = be_transform_node(index);
831 res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
832 set_address(res, addr);
837 static int am_has_immediates(const ia32_address_t *addr)
839 return addr->offset != 0 || addr->symconst_ent != NULL
840 || addr->frame_entity || addr->use_frame;
844 * Creates an ia32 Add.
846 * @return the created ia32 Add node
848 static ir_node *gen_Add(ir_node *node) {
849 ir_node *block = be_transform_node(get_nodes_block(node));
850 ir_node *op1 = get_Add_left(node);
851 ir_node *op2 = get_Add_right(node);
854 ir_graph *irg = current_ir_graph;
855 dbg_info *dbgi = get_irn_dbg_info(node);
856 ir_mode *mode = get_irn_mode(node);
857 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
858 ir_node *src_block = get_nodes_block(node);
859 ir_node *add_immediate_op;
861 ia32_address_mode_t am;
863 if (mode_is_float(mode)) {
864 if (USE_SSE2(env_cg))
865 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
867 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
872 * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
873 * 1. Add with immediate -> Lea
874 * 2. Add with possible source address mode -> Add
875 * 3. Otherwise -> Lea
877 memset(&addr, 0, sizeof(addr));
878 ia32_create_address_mode(&addr, node, 1);
879 add_immediate_op = NULL;
881 if(addr.base == NULL && addr.index == NULL) {
882 new_op = new_rd_ia32_Const(dbgi, irg, block, addr.symconst_ent,
883 addr.symconst_sign, addr.offset);
884 add_irn_dep(new_op, get_irg_frame(irg));
885 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
888 /* add with immediate? */
889 if(addr.index == NULL) {
890 add_immediate_op = addr.base;
891 } else if(addr.base == NULL && addr.scale == 0) {
892 add_immediate_op = addr.index;
895 if(add_immediate_op != NULL) {
896 if(!am_has_immediates(&addr)) {
898 ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
901 return be_transform_node(add_immediate_op);
904 new_op = create_lea_from_address(dbgi, block, &addr);
905 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
909 /* test if we can use source address mode */
910 memset(&am, 0, sizeof(am));
912 if(use_source_address_mode(src_block, op2, op1)) {
913 build_address(&am, op2);
914 new_op1 = be_transform_node(op1);
915 } else if(use_source_address_mode(src_block, op1, op2)) {
916 build_address(&am, op1);
917 new_op1 = be_transform_node(op2);
919 /* construct an Add with source address mode */
920 if(new_op1 != NULL) {
921 ia32_address_t *am_addr = &am.addr;
922 new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
923 am_addr->mem, new_op1, noreg);
924 set_address(new_op, am_addr);
925 set_ia32_op_type(new_op, ia32_AddrModeS);
926 set_ia32_ls_mode(new_op, am.ls_mode);
927 set_ia32_commutative(new_op);
928 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
930 new_op = fix_mem_proj(new_op, &am);
935 /* otherwise construct a lea */
936 new_op = create_lea_from_address(dbgi, block, &addr);
937 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
942 * Creates an ia32 Mul.
944 * @return the created ia32 Mul node
946 static ir_node *gen_Mul(ir_node *node) {
947 ir_node *op1 = get_Mul_left(node);
948 ir_node *op2 = get_Mul_right(node);
949 ir_mode *mode = get_irn_mode(node);
951 if (mode_is_float(mode)) {
952 if (USE_SSE2(env_cg))
953 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
955 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
959 for the lower 32bit of the result it doesn't matter whether we use
960 signed or unsigned multiplication so we use IMul as it has fewer
963 return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
967 * Creates an ia32 Mulh.
968 * Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
969 * this result while Mul returns the lower 32 bit.
971 * @return the created ia32 Mulh node
973 static ir_node *gen_Mulh(ir_node *node) {
974 ir_node *block = be_transform_node(get_nodes_block(node));
975 ir_node *op1 = get_irn_n(node, 0);
976 ir_node *new_op1 = be_transform_node(op1);
977 ir_node *op2 = get_irn_n(node, 1);
978 ir_node *new_op2 = be_transform_node(op2);
979 ir_graph *irg = current_ir_graph;
980 dbg_info *dbgi = get_irn_dbg_info(node);
981 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
982 ir_mode *mode = get_irn_mode(node);
983 ir_node *proj_EDX, *res;
985 assert(!mode_is_float(mode) && "Mulh with float not supported");
986 if (mode_is_signed(mode)) {
987 res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
990 res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
994 set_ia32_commutative(res);
996 proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
1004 * Creates an ia32 And.
1006 * @return The created ia32 And node
1008 static ir_node *gen_And(ir_node *node) {
1009 ir_node *op1 = get_And_left(node);
1010 ir_node *op2 = get_And_right(node);
1011 assert(! mode_is_float(get_irn_mode(node)));
1013 /* is it a zero extension? */
1014 if (is_Const(op2)) {
1015 tarval *tv = get_Const_tarval(op2);
1016 long v = get_tarval_long(tv);
1018 if (v == 0xFF || v == 0xFFFF) {
1019 dbg_info *dbgi = get_irn_dbg_info(node);
1020 ir_node *block = get_nodes_block(node);
1027 assert(v == 0xFFFF);
1030 res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
1036 return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
1042 * Creates an ia32 Or.
1044 * @return The created ia32 Or node
1046 static ir_node *gen_Or(ir_node *node) {
1047 ir_node *op1 = get_Or_left(node);
1048 ir_node *op2 = get_Or_right(node);
1050 assert (! mode_is_float(get_irn_mode(node)));
1051 return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
1057 * Creates an ia32 Eor.
1059 * @return The created ia32 Eor node
1061 static ir_node *gen_Eor(ir_node *node) {
1062 ir_node *op1 = get_Eor_left(node);
1063 ir_node *op2 = get_Eor_right(node);
1065 assert(! mode_is_float(get_irn_mode(node)));
1066 return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
1071 * Creates an ia32 Sub.
1073 * @return The created ia32 Sub node
1075 static ir_node *gen_Sub(ir_node *node) {
1076 ir_node *op1 = get_Sub_left(node);
1077 ir_node *op2 = get_Sub_right(node);
1078 ir_mode *mode = get_irn_mode(node);
1080 if (mode_is_float(mode)) {
1081 if (USE_SSE2(env_cg))
1082 return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
1084 return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
1088 ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
1092 return gen_binop(node, op1, op2, new_rd_ia32_Sub, 0);
1098 * Generates an ia32 DivMod with additional infrastructure for the
1099 * register allocator if needed.
1101 * @param dividend -no comment- :)
1102 * @param divisor -no comment- :)
1103 * @param dm_flav flavour_Div/Mod/DivMod
1104 * @return The created ia32 DivMod node
1106 static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
1107 ir_node *divisor, ia32_op_flavour_t dm_flav)
1109 ir_node *block = be_transform_node(get_nodes_block(node));
1110 ir_node *new_dividend = be_transform_node(dividend);
1111 ir_node *new_divisor = be_transform_node(divisor);
1112 ir_graph *irg = current_ir_graph;
1113 dbg_info *dbgi = get_irn_dbg_info(node);
1114 ir_mode *mode = get_irn_mode(node);
1115 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1116 ir_node *res, *proj_div, *proj_mod;
1117 ir_node *sign_extension;
1118 ir_node *mem, *new_mem;
1121 proj_div = proj_mod = NULL;
1125 mem = get_Div_mem(node);
1126 mode = get_Div_resmode(node);
1127 proj_div = be_get_Proj_for_pn(node, pn_Div_res);
1128 has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
1131 mem = get_Mod_mem(node);
1132 mode = get_Mod_resmode(node);
1133 proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
1134 has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
1136 case flavour_DivMod:
1137 mem = get_DivMod_mem(node);
1138 mode = get_DivMod_resmode(node);
1139 proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
1140 proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
1141 has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
1144 panic("invalid divmod flavour!");
1146 new_mem = be_transform_node(mem);
1148 if (mode_is_signed(mode)) {
1149 /* in signed mode, we need to sign extend the dividend */
1150 ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1151 add_irn_dep(produceval, get_irg_frame(irg));
1152 sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
1155 sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
1156 set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
1157 add_irn_dep(sign_extension, get_irg_frame(irg));
1160 if (mode_is_signed(mode)) {
1161 res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
1162 new_dividend, sign_extension, new_divisor, dm_flav);
1164 res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
1165 sign_extension, new_divisor, dm_flav);
1168 set_ia32_exc_label(res, has_exc);
1169 set_irn_pinned(res, get_irn_pinned(node));
1171 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1178 * Wrapper for generate_DivMod. Sets flavour_Mod.
1181 static ir_node *gen_Mod(ir_node *node) {
1182 return generate_DivMod(node, get_Mod_left(node),
1183 get_Mod_right(node), flavour_Mod);
1187 * Wrapper for generate_DivMod. Sets flavour_Div.
1190 static ir_node *gen_Div(ir_node *node) {
1191 return generate_DivMod(node, get_Div_left(node),
1192 get_Div_right(node), flavour_Div);
1196 * Wrapper for generate_DivMod. Sets flavour_DivMod.
1198 static ir_node *gen_DivMod(ir_node *node) {
1199 return generate_DivMod(node, get_DivMod_left(node),
1200 get_DivMod_right(node), flavour_DivMod);
1206 * Creates an ia32 floating Div.
1208 * @return The created ia32 xDiv node
1210 static ir_node *gen_Quot(ir_node *node) {
1211 ir_node *block = be_transform_node(get_nodes_block(node));
1212 ir_node *op1 = get_Quot_left(node);
1213 ir_node *new_op1 = be_transform_node(op1);
1214 ir_node *op2 = get_Quot_right(node);
1215 ir_node *new_op2 = be_transform_node(op2);
1216 ir_graph *irg = current_ir_graph;
1217 dbg_info *dbgi = get_irn_dbg_info(node);
1218 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1219 ir_node *nomem = new_rd_NoMem(current_ir_graph);
1222 if (USE_SSE2(env_cg)) {
1223 ir_mode *mode = get_irn_mode(op1);
1224 new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1226 set_ia32_ls_mode(new_op, mode);
1228 new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
1229 new_op2, get_fpcw());
1231 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1237 * Creates an ia32 Shl.
1239 * @return The created ia32 Shl node
1241 static ir_node *gen_Shl(ir_node *node) {
1242 ir_node *right = get_Shl_right(node);
1244 /* test whether we can build a lea */
1245 if(is_Const(right)) {
1246 tarval *tv = get_Const_tarval(right);
1247 if(tarval_is_long(tv)) {
1248 long val = get_tarval_long(tv);
1249 if(val >= 0 && val <= 3) {
1250 ir_graph *irg = current_ir_graph;
1251 dbg_info *dbgi = get_irn_dbg_info(node);
1252 ir_node *block = be_transform_node(get_nodes_block(node));
1253 ir_node *base = ia32_new_NoReg_gp(env_cg);
1254 ir_node *index = be_transform_node(get_Shl_left(node));
1255 ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
1256 set_ia32_am_scale(res, val);
1257 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1263 return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
1270 * Creates an ia32 Shr.
1272 * @return The created ia32 Shr node
1274 static ir_node *gen_Shr(ir_node *node) {
1275 return gen_shift_binop(node, get_Shr_left(node),
1276 get_Shr_right(node), new_rd_ia32_Shr);
1282 * Creates an ia32 Sar.
1284 * @return The created ia32 Shrs node
1286 static ir_node *gen_Shrs(ir_node *node) {
1287 ir_node *left = get_Shrs_left(node);
1288 ir_node *right = get_Shrs_right(node);
1289 ir_mode *mode = get_irn_mode(node);
1290 if(is_Const(right) && mode == mode_Is) {
1291 tarval *tv = get_Const_tarval(right);
1292 long val = get_tarval_long(tv);
1294 /* this is a sign extension */
1295 ir_graph *irg = current_ir_graph;
1296 dbg_info *dbgi = get_irn_dbg_info(node);
1297 ir_node *block = be_transform_node(get_nodes_block(node));
1299 ir_node *new_op = be_transform_node(op);
1300 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1301 add_irn_dep(pval, get_irg_frame(irg));
1303 return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
1307 /* 8 or 16 bit sign extension? */
1308 if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
1309 ir_node *shl_left = get_Shl_left(left);
1310 ir_node *shl_right = get_Shl_right(left);
1311 if(is_Const(shl_right)) {
1312 tarval *tv1 = get_Const_tarval(right);
1313 tarval *tv2 = get_Const_tarval(shl_right);
1314 if(tv1 == tv2 && tarval_is_long(tv1)) {
1315 long val = get_tarval_long(tv1);
1316 if(val == 16 || val == 24) {
1317 dbg_info *dbgi = get_irn_dbg_info(node);
1318 ir_node *block = get_nodes_block(node);
1328 res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
1337 return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
1343 * Creates an ia32 RotL.
1345 * @param op1 The first operator
1346 * @param op2 The second operator
1347 * @return The created ia32 RotL node
1349 static ir_node *gen_RotL(ir_node *node,
1350 ir_node *op1, ir_node *op2) {
1351 return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
1357 * Creates an ia32 RotR.
1358 * NOTE: There is no RotR with immediate because this would always be a RotL
1359 * "imm-mode_size_bits" which can be pre-calculated.
1361 * @param op1 The first operator
1362 * @param op2 The second operator
1363 * @return The created ia32 RotR node
1365 static ir_node *gen_RotR(ir_node *node, ir_node *op1,
1367 return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
1373 * Creates an ia32 RotR or RotL (depending on the found pattern).
1375 * @return The created ia32 RotL or RotR node
1377 static ir_node *gen_Rot(ir_node *node) {
1378 ir_node *rotate = NULL;
1379 ir_node *op1 = get_Rot_left(node);
1380 ir_node *op2 = get_Rot_right(node);
1382 /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
1383 operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
1384 that means we can create a RotR instead of an Add and a RotL */
1386 if (get_irn_op(op2) == op_Add) {
1388 ir_node *left = get_Add_left(add);
1389 ir_node *right = get_Add_right(add);
1390 if (is_Const(right)) {
1391 tarval *tv = get_Const_tarval(right);
1392 ir_mode *mode = get_irn_mode(node);
1393 long bits = get_mode_size_bits(mode);
1395 if (get_irn_op(left) == op_Minus &&
1396 tarval_is_long(tv) &&
1397 get_tarval_long(tv) == bits)
1399 DB((dbg, LEVEL_1, "RotL into RotR ... "));
1400 rotate = gen_RotR(node, op1, get_Minus_op(left));
1405 if (rotate == NULL) {
1406 rotate = gen_RotL(node, op1, op2);
1415 * Transforms a Minus node.
1417 * @param op The Minus operand
1418 * @return The created ia32 Minus node
1420 ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
1421 ir_node *block = be_transform_node(get_nodes_block(node));
1422 ir_graph *irg = current_ir_graph;
1423 dbg_info *dbgi = get_irn_dbg_info(node);
1424 ir_mode *mode = get_irn_mode(node);
1429 if (mode_is_float(mode)) {
1430 ir_node *new_op = be_transform_node(op);
1431 if (USE_SSE2(env_cg)) {
1432 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1433 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1434 ir_node *nomem = new_rd_NoMem(irg);
1436 res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
1439 size = get_mode_size_bits(mode);
1440 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
1442 set_ia32_am_sc(res, ent);
1443 set_ia32_op_type(res, ia32_AddrModeS);
1444 set_ia32_ls_mode(res, mode);
1446 res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
1449 res = gen_unop(node, op, new_rd_ia32_Neg);
1452 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1458 * Transforms a Minus node.
1460 * @return The created ia32 Minus node
1462 static ir_node *gen_Minus(ir_node *node) {
1463 return gen_Minus_ex(node, get_Minus_op(node));
1466 static ir_node *create_Immediate_from_int(int val)
1468 ir_graph *irg = current_ir_graph;
1469 ir_node *start_block = get_irg_start_block(irg);
1470 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
1471 arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
1476 static ir_node *gen_bin_Not(ir_node *node)
1478 ir_graph *irg = current_ir_graph;
1479 dbg_info *dbgi = get_irn_dbg_info(node);
1480 ir_node *block = be_transform_node(get_nodes_block(node));
1481 ir_node *op = get_Not_op(node);
1482 ir_node *new_op = be_transform_node(op);
1483 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1484 ir_node *nomem = new_NoMem();
1485 ir_node *one = create_Immediate_from_int(1);
1487 return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
1491 * Transforms a Not node.
1493 * @return The created ia32 Not node
1495 static ir_node *gen_Not(ir_node *node) {
1496 ir_node *op = get_Not_op(node);
1497 ir_mode *mode = get_irn_mode(node);
1499 if(mode == mode_b) {
1500 return gen_bin_Not(node);
1503 assert (! mode_is_float(get_irn_mode(node)));
1504 return gen_unop(node, op, new_rd_ia32_Not);
1510 * Transforms an Abs node.
1512 * @return The created ia32 Abs node
1514 static ir_node *gen_Abs(ir_node *node) {
1515 ir_node *block = be_transform_node(get_nodes_block(node));
1516 ir_node *op = get_Abs_op(node);
1517 ir_node *new_op = be_transform_node(op);
1518 ir_graph *irg = current_ir_graph;
1519 dbg_info *dbgi = get_irn_dbg_info(node);
1520 ir_mode *mode = get_irn_mode(node);
1521 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1522 ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
1523 ir_node *nomem = new_NoMem();
1528 if (mode_is_float(mode)) {
1529 if (USE_SSE2(env_cg)) {
1530 res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
1532 size = get_mode_size_bits(mode);
1533 ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
1535 set_ia32_am_sc(res, ent);
1537 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1539 set_ia32_op_type(res, ia32_AddrModeS);
1540 set_ia32_ls_mode(res, mode);
1543 res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
1544 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1548 ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
1549 ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
1552 add_irn_dep(pval, get_irg_frame(irg));
1553 SET_IA32_ORIG_NODE(sign_extension,
1554 ia32_get_old_node_name(env_cg, node));
1556 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
1558 SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
1560 res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
1562 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1569 * Transforms a Load.
1571 * @return the created ia32 Load node
1573 static ir_node *gen_Load(ir_node *node) {
1574 ir_node *old_block = get_nodes_block(node);
1575 ir_node *block = be_transform_node(old_block);
1576 ir_node *ptr = get_Load_ptr(node);
1577 ir_node *mem = get_Load_mem(node);
1578 ir_node *new_mem = be_transform_node(mem);
1581 ir_graph *irg = current_ir_graph;
1582 dbg_info *dbgi = get_irn_dbg_info(node);
1583 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1584 ir_mode *mode = get_Load_mode(node);
1587 ia32_address_t addr;
1589 /* construct load address */
1590 memset(&addr, 0, sizeof(addr));
1591 ia32_create_address_mode(&addr, ptr, 0);
1598 base = be_transform_node(base);
1604 index = be_transform_node(index);
1607 if (mode_is_float(mode)) {
1608 if (USE_SSE2(env_cg)) {
1609 new_op = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
1611 res_mode = mode_xmm;
1613 new_op = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
1615 res_mode = mode_vfp;
1621 /* create a conv node with address mode for smaller modes */
1622 if(get_mode_size_bits(mode) < 32) {
1623 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem,
1626 new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
1631 set_irn_pinned(new_op, get_irn_pinned(node));
1632 set_ia32_op_type(new_op, ia32_AddrModeS);
1633 set_ia32_ls_mode(new_op, mode);
1634 set_address(new_op, &addr);
1636 /* make sure we are scheduled behind the initial IncSP/Barrier
1637 * to avoid spills being placed before it
1639 if (block == get_irg_start_block(irg)) {
1640 add_irn_dep(new_op, get_irg_frame(irg));
1643 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
1644 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1649 static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
1650 ir_node *ptr, ir_mode *mode, ir_node *other)
1657 /* we only use address mode if we're the only user of the load */
1658 if(get_irn_n_edges(node) > 1)
1661 load = get_Proj_pred(node);
1664 if(get_nodes_block(load) != block)
1667 /* Store should be attached to the load */
1668 if(!is_Proj(mem) || get_Proj_pred(mem) != load)
1670 /* store should have the same pointer as the load */
1671 if(get_Load_ptr(load) != ptr)
1674 /* don't do AM if other node inputs depend on the load (via mem-proj) */
1675 if(other != NULL && get_nodes_block(other) == block
1676 && heights_reachable_in_block(heights, other, load))
1679 assert(get_Load_mode(load) == mode);
1684 static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
1685 ir_node *mem, ir_node *ptr, ir_mode *mode,
1686 construct_binop_dest_func *func,
1687 construct_binop_dest_func *func8bit,
1690 ir_node *src_block = get_nodes_block(node);
1692 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1693 ir_graph *irg = current_ir_graph;
1697 ia32_address_mode_t am;
1698 ia32_address_t *addr = &am.addr;
1699 memset(&am, 0, sizeof(am));
1701 if(use_dest_am(src_block, op1, mem, ptr, mode, op2)) {
1702 build_address(&am, op1);
1703 new_op = create_immediate_or_transform(op2, 0);
1704 } else if(commutative && use_dest_am(src_block, op2, mem, ptr, mode, op1)) {
1705 build_address(&am, op2);
1706 new_op = create_immediate_or_transform(op1, 0);
1711 if(addr->base == NULL)
1712 addr->base = noreg_gp;
1713 if(addr->index == NULL)
1714 addr->index = noreg_gp;
1715 if(addr->mem == NULL)
1716 addr->mem = new_NoMem();
1718 dbgi = get_irn_dbg_info(node);
1719 block = be_transform_node(src_block);
1720 if(get_mode_size_bits(mode) == 8) {
1721 new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
1724 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
1727 set_address(new_node, addr);
1728 set_ia32_op_type(new_node, ia32_AddrModeD);
1729 set_ia32_ls_mode(new_node, mode);
1730 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1735 static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
1736 ir_node *ptr, ir_mode *mode,
1737 construct_unop_dest_func *func)
1739 ir_node *src_block = get_nodes_block(node);
1741 ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
1742 ir_graph *irg = current_ir_graph;
1745 ia32_address_mode_t am;
1746 ia32_address_t *addr = &am.addr;
1747 memset(&am, 0, sizeof(am));
1749 if(!use_dest_am(src_block, op, mem, ptr, mode, NULL))
1752 build_address(&am, op);
1754 if(addr->base == NULL)
1755 addr->base = noreg_gp;
1756 if(addr->index == NULL)
1757 addr->index = noreg_gp;
1758 if(addr->mem == NULL)
1759 addr->mem = new_NoMem();
1761 dbgi = get_irn_dbg_info(node);
1762 block = be_transform_node(src_block);
1763 new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
1764 set_address(new_node, addr);
1765 set_ia32_op_type(new_node, ia32_AddrModeD);
1766 set_ia32_ls_mode(new_node, mode);
1767 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
1772 static ir_node *try_create_dest_am(ir_node *node) {
1773 ir_node *val = get_Store_value(node);
1774 ir_node *mem = get_Store_mem(node);
1775 ir_node *ptr = get_Store_ptr(node);
1776 ir_mode *mode = get_irn_mode(val);
1781 /* handle only GP modes for now... */
1782 if(!mode_needs_gp_reg(mode))
1785 /* store must be the only user of the val node */
1786 if(get_irn_n_edges(val) > 1)
1789 switch(get_irn_opcode(val)) {
1791 op1 = get_Add_left(val);
1792 op2 = get_Add_right(val);
1793 if(is_Const_1(op2)) {
1794 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1795 new_rd_ia32_IncMem);
1797 } else if(is_Const_Minus_1(op2)) {
1798 new_node = dest_am_unop(val, op1, mem, ptr, mode,
1799 new_rd_ia32_DecMem);
1802 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1803 new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
1806 op1 = get_Sub_left(val);
1807 op2 = get_Sub_right(val);
1809 ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
1812 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1813 new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
1816 op1 = get_And_left(val);
1817 op2 = get_And_right(val);
1818 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1819 new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
1822 op1 = get_Or_left(val);
1823 op2 = get_Or_right(val);
1824 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1825 new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
1828 op1 = get_Eor_left(val);
1829 op2 = get_Eor_right(val);
1830 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1831 new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
1834 op1 = get_Shl_left(val);
1835 op2 = get_Shl_right(val);
1836 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1837 new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
1840 op1 = get_Shr_left(val);
1841 op2 = get_Shr_right(val);
1842 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1843 new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
1846 op1 = get_Shrs_left(val);
1847 op2 = get_Shrs_right(val);
1848 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1849 new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
1852 op1 = get_Rot_left(val);
1853 op2 = get_Rot_right(val);
1854 new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
1855 new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
1857 /* TODO: match ROR patterns... */
1859 op1 = get_Minus_op(val);
1860 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
1863 /* should be lowered already */
1864 assert(mode != mode_b);
1865 op1 = get_Not_op(val);
1866 new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
1876 * Transforms a Store.
1878 * @return the created ia32 Store node
1880 static ir_node *gen_Store(ir_node *node) {
1881 ir_node *block = be_transform_node(get_nodes_block(node));
1882 ir_node *ptr = get_Store_ptr(node);
1885 ir_node *val = get_Store_value(node);
1887 ir_node *mem = get_Store_mem(node);
1888 ir_node *new_mem = be_transform_node(mem);
1889 ir_graph *irg = current_ir_graph;
1890 dbg_info *dbgi = get_irn_dbg_info(node);
1891 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1892 ir_mode *mode = get_irn_mode(val);
1894 ia32_address_t addr;
1896 /* check for destination address mode */
1897 new_op = try_create_dest_am(node);
1901 /* construct store address */
1902 memset(&addr, 0, sizeof(addr));
1903 ia32_create_address_mode(&addr, ptr, 0);
1910 base = be_transform_node(base);
1916 index = be_transform_node(index);
1919 if (mode_is_float(mode)) {
1920 new_val = be_transform_node(val);
1921 if (USE_SSE2(env_cg)) {
1922 new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
1925 new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
1929 new_val = create_immediate_or_transform(val, 0);
1933 if (get_mode_size_bits(mode) == 8) {
1934 new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
1937 new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
1942 set_irn_pinned(new_op, get_irn_pinned(node));
1943 set_ia32_op_type(new_op, ia32_AddrModeD);
1944 set_ia32_ls_mode(new_op, mode);
1946 set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
1947 set_address(new_op, &addr);
1948 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
1953 static ir_node *create_Switch(ir_node *node)
1955 ir_graph *irg = current_ir_graph;
1956 dbg_info *dbgi = get_irn_dbg_info(node);
1957 ir_node *block = be_transform_node(get_nodes_block(node));
1958 ir_node *sel = get_Cond_selector(node);
1959 ir_node *new_sel = be_transform_node(sel);
1961 int switch_min = INT_MAX;
1962 const ir_edge_t *edge;
1964 assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
1966 /* determine the smallest switch case value */
1967 foreach_out_edge(node, edge) {
1968 ir_node *proj = get_edge_src_irn(edge);
1969 int pn = get_Proj_proj(proj);
1974 if (switch_min != 0) {
1975 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
1977 /* if smallest switch case is not 0 we need an additional sub */
1978 new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
1979 add_ia32_am_offs_int(new_sel, -switch_min);
1980 set_ia32_op_type(new_sel, ia32_AddrModeS);
1982 SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
1985 res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
1986 set_ia32_pncode(res, get_Cond_defaultProj(node));
1988 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
1993 static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
1995 ir_graph *irg = current_ir_graph;
2003 /* we have a Cmp as input */
2005 ir_node *pred = get_Proj_pred(node);
2007 flags = be_transform_node(pred);
2008 *pnc_out = get_Proj_proj(node);
2013 /* a mode_b value, we have to compare it against 0 */
2014 dbgi = get_irn_dbg_info(node);
2015 new_block = be_transform_node(get_nodes_block(node));
2016 new_op = be_transform_node(node);
2017 noreg = ia32_new_NoReg_gp(env_cg);
2018 nomem = new_NoMem();
2019 flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
2020 new_op, new_op, 0, 0);
2021 *pnc_out = pn_Cmp_Lg;
2025 static ir_node *gen_Cond(ir_node *node) {
2026 ir_node *block = get_nodes_block(node);
2027 ir_node *new_block = be_transform_node(block);
2028 ir_graph *irg = current_ir_graph;
2029 dbg_info *dbgi = get_irn_dbg_info(node);
2030 ir_node *sel = get_Cond_selector(node);
2031 ir_mode *sel_mode = get_irn_mode(sel);
2033 ir_node *flags = NULL;
2036 if (sel_mode != mode_b) {
2037 return create_Switch(node);
2040 /* we get flags from a cmp */
2041 flags = get_flags_node(sel, &pnc);
2043 res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
2044 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2052 * Transforms a CopyB node.
2054 * @return The transformed node.
2056 static ir_node *gen_CopyB(ir_node *node) {
2057 ir_node *block = be_transform_node(get_nodes_block(node));
2058 ir_node *src = get_CopyB_src(node);
2059 ir_node *new_src = be_transform_node(src);
2060 ir_node *dst = get_CopyB_dst(node);
2061 ir_node *new_dst = be_transform_node(dst);
2062 ir_node *mem = get_CopyB_mem(node);
2063 ir_node *new_mem = be_transform_node(mem);
2064 ir_node *res = NULL;
2065 ir_graph *irg = current_ir_graph;
2066 dbg_info *dbgi = get_irn_dbg_info(node);
2067 int size = get_type_size_bytes(get_CopyB_type(node));
2070 /* If we have to copy more than 32 bytes, we use REP MOVSx and */
2071 /* then we need the size explicitly in ECX. */
2072 if (size >= 32 * 4) {
2073 rem = size & 0x3; /* size % 4 */
2076 res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
2078 ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
2080 set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
2082 add_irn_dep(res, get_irg_frame(irg));
2084 res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
2085 /* we misuse the pncode field for the copyb size */
2086 set_ia32_pncode(res, rem);
2088 res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
2089 set_ia32_pncode(res, size);
2092 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2097 static ir_node *gen_be_Copy(ir_node *node)
2099 ir_node *result = be_duplicate_node(node);
2100 ir_mode *mode = get_irn_mode(result);
2102 if (mode_needs_gp_reg(mode)) {
2103 set_irn_mode(result, mode_Iu);
2110 * helper function: checks wether all Cmp projs are Lg or Eq which is needed
2111 * to fold an and into a test node
2113 static int can_fold_test_and(ir_node *node)
2115 const ir_edge_t *edge;
2117 /** we can only have eq and lg projs */
2118 foreach_out_edge(node, edge) {
2119 ir_node *proj = get_edge_src_irn(edge);
2120 pn_Cmp pnc = get_Proj_proj(proj);
2121 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
2128 static ir_node *try_create_Test(ir_node *node)
2130 ir_graph *irg = current_ir_graph;
2131 dbg_info *dbgi = get_irn_dbg_info(node);
2132 ir_node *block = get_nodes_block(node);
2133 ir_node *new_block = be_transform_node(block);
2134 ir_node *cmp_left = get_Cmp_left(node);
2135 ir_node *cmp_right = get_Cmp_right(node);
2140 ia32_address_mode_t am;
2141 ia32_address_t *addr = &am.addr;
2144 /* can we use a test instruction? */
2145 if(!is_Const_0(cmp_right))
2148 if(is_And(cmp_left) && can_fold_test_and(node)) {
2149 ir_node *and_left = get_And_left(cmp_left);
2150 ir_node *and_right = get_And_right(cmp_left);
2152 mode = get_irn_mode(and_left);
2156 mode = get_irn_mode(cmp_left);
2161 assert(get_mode_size_bits(mode) <= 32);
2163 match_arguments(&am, block, left, right, match_commutative |
2164 match_8_16_bit_am | match_am_and_immediates);
2166 cmp_unsigned = !mode_is_signed(mode);
2167 if(get_mode_size_bits(mode) == 8) {
2168 res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
2169 addr->index, addr->mem, am.new_op1,
2170 am.new_op2, am.flipped, cmp_unsigned);
2172 res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
2173 addr->mem, am.new_op1, am.new_op2, am.flipped,
2176 set_am_attributes(res, &am);
2177 assert(mode != NULL);
2178 set_ia32_ls_mode(res, mode);
2180 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2182 res = fix_mem_proj(res, &am);
2186 static ir_node *create_Fucom(ir_node *node)
2188 ir_graph *irg = current_ir_graph;
2189 dbg_info *dbgi = get_irn_dbg_info(node);
2190 ir_node *block = get_nodes_block(node);
2191 ir_node *new_block = be_transform_node(block);
2192 ir_node *left = get_Cmp_left(node);
2193 ir_node *new_left = be_transform_node(left);
2194 ir_node *right = get_Cmp_right(node);
2195 ir_node *new_right = be_transform_node(right);
2198 res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
2200 set_ia32_commutative(res);
2202 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2204 res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
2205 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2210 static ir_node *create_Ucomi(ir_node *node)
2212 ir_graph *irg = current_ir_graph;
2213 dbg_info *dbgi = get_irn_dbg_info(node);
2214 ir_node *block = get_nodes_block(node);
2215 ir_node *new_block = be_transform_node(block);
2216 ir_node *left = get_Cmp_left(node);
2217 ir_node *new_left = be_transform_node(left);
2218 ir_node *right = get_Cmp_right(node);
2219 ir_node *new_right = be_transform_node(right);
2220 ir_mode *mode = get_irn_mode(left);
2221 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2222 ir_node *nomem = new_NoMem();
2225 res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
2227 set_ia32_commutative(res);
2228 set_ia32_ls_mode(res, mode);
2230 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2235 static ir_node *gen_Cmp(ir_node *node)
2237 ir_graph *irg = current_ir_graph;
2238 dbg_info *dbgi = get_irn_dbg_info(node);
2239 ir_node *block = get_nodes_block(node);
2240 ir_node *new_block = be_transform_node(block);
2241 ir_node *left = get_Cmp_left(node);
2242 ir_node *right = get_Cmp_right(node);
2243 ir_mode *cmp_mode = get_irn_mode(left);
2245 ia32_address_mode_t am;
2246 ia32_address_t *addr = &am.addr;
2249 if(mode_is_float(cmp_mode)) {
2250 if (USE_SSE2(env_cg)) {
2251 return create_Ucomi(node);
2253 return create_Fucom(node);
2257 assert(mode_needs_gp_reg(cmp_mode));
2259 /* we prefer the Test instruction where possible except cases where
2260 * we can use SourceAM */
2261 if(!use_source_address_mode(block, left, right) &&
2262 !use_source_address_mode(block, right, left)) {
2263 res = try_create_Test(node);
2268 match_arguments(&am, block, left, right,
2269 match_commutative | match_8_16_bit_am |
2270 match_am_and_immediates);
2272 cmp_unsigned = !mode_is_signed(get_irn_mode(left));
2273 if(get_mode_size_bits(cmp_mode) == 8) {
2274 res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
2275 addr->mem, am.new_op1, am.new_op2,
2276 am.flipped, cmp_unsigned);
2278 res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
2279 addr->mem, am.new_op1, am.new_op2, am.flipped,
2282 set_am_attributes(res, &am);
2283 assert(cmp_mode != NULL);
2284 set_ia32_ls_mode(res, cmp_mode);
2286 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2288 res = fix_mem_proj(res, &am);
2293 static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
2295 ir_graph *irg = current_ir_graph;
2296 dbg_info *dbgi = get_irn_dbg_info(node);
2297 ir_node *block = get_nodes_block(node);
2298 ir_node *new_block = be_transform_node(block);
2299 ir_node *val_true = get_Psi_val(node, 0);
2300 ir_node *new_val_true = be_transform_node(val_true);
2301 ir_node *val_false = get_Psi_default(node);
2302 ir_node *new_val_false = be_transform_node(val_false);
2303 ir_mode *mode = get_irn_mode(node);
2304 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2305 ir_node *nomem = new_NoMem();
2308 assert(mode_needs_gp_reg(mode));
2310 res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
2311 new_val_false, new_val_true, new_flags, pnc);
2312 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2319 static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
2320 ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
2322 ir_graph *irg = current_ir_graph;
2323 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2324 ir_node *nomem = new_NoMem();
2327 res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
2328 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2329 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
2330 nomem, res, mode_Bu);
2331 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
2337 * Transforms a Psi node into CMov.
2339 * @return The transformed node.
2341 static ir_node *gen_Psi(ir_node *node)
2343 dbg_info *dbgi = get_irn_dbg_info(node);
2344 ir_node *block = get_nodes_block(node);
2345 ir_node *new_block = be_transform_node(block);
2346 ir_node *psi_true = get_Psi_val(node, 0);
2347 ir_node *psi_default = get_Psi_default(node);
2348 ir_node *cond = get_Psi_cond(node, 0);
2349 ir_node *flags = NULL;
2354 assert(get_Psi_n_conds(node) == 1);
2355 assert(get_irn_mode(cond) == mode_b);
2356 assert(mode_needs_gp_reg(get_irn_mode(node)));
2358 flags = get_flags_node(cond, &pnc);
2360 if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
2361 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2362 } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
2363 pnc = get_negated_pnc(pnc, cmp_mode);
2364 res = create_set_32bit(dbgi, new_block, flags, pnc, node);
2366 res = create_CMov(node, flags, pnc);
2373 * Create a conversion from x87 state register to general purpose.
2375 static ir_node *gen_x87_fp_to_gp(ir_node *node) {
2376 ir_node *block = be_transform_node(get_nodes_block(node));
2377 ir_node *op = get_Conv_op(node);
2378 ir_node *new_op = be_transform_node(op);
2379 ia32_code_gen_t *cg = env_cg;
2380 ir_graph *irg = current_ir_graph;
2381 dbg_info *dbgi = get_irn_dbg_info(node);
2382 ir_node *noreg = ia32_new_NoReg_gp(cg);
2383 ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
2384 ir_mode *mode = get_irn_mode(node);
2385 ir_node *fist, *load;
2388 fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
2389 new_NoMem(), new_op, trunc_mode);
2391 set_irn_pinned(fist, op_pin_state_floats);
2392 set_ia32_use_frame(fist);
2393 set_ia32_op_type(fist, ia32_AddrModeD);
2395 assert(get_mode_size_bits(mode) <= 32);
2396 /* exception we can only store signed 32 bit integers, so for unsigned
2397 we store a 64bit (signed) integer and load the lower bits */
2398 if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
2399 set_ia32_ls_mode(fist, mode_Ls);
2401 set_ia32_ls_mode(fist, mode_Is);
2403 SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
2406 load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
2408 set_irn_pinned(load, op_pin_state_floats);
2409 set_ia32_use_frame(load);
2410 set_ia32_op_type(load, ia32_AddrModeS);
2411 set_ia32_ls_mode(load, mode_Is);
2412 if(get_ia32_ls_mode(fist) == mode_Ls) {
2413 ia32_attr_t *attr = get_ia32_attr(load);
2414 attr->data.need_64bit_stackent = 1;
2416 ia32_attr_t *attr = get_ia32_attr(load);
2417 attr->data.need_32bit_stackent = 1;
2419 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
2421 return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
2425 * Creates a x87 strict Conv by placing a Sore and a Load
2427 static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
2429 ir_node *block = get_nodes_block(node);
2430 ir_graph *irg = current_ir_graph;
2431 dbg_info *dbgi = get_irn_dbg_info(node);
2432 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2433 ir_node *nomem = new_NoMem();
2434 ir_node *frame = get_irg_frame(irg);
2435 ir_node *store, *load;
2438 store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
2440 set_ia32_use_frame(store);
2441 set_ia32_op_type(store, ia32_AddrModeD);
2442 SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
2444 load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
2446 set_ia32_use_frame(load);
2447 set_ia32_op_type(load, ia32_AddrModeS);
2448 SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
2450 res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
2455 * Create a conversion from general purpose to x87 register
2457 static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
2458 ir_node *block = be_transform_node(get_nodes_block(node));
2459 ir_node *op = get_Conv_op(node);
2460 ir_node *new_op = be_transform_node(op);
2461 ir_graph *irg = current_ir_graph;
2462 dbg_info *dbgi = get_irn_dbg_info(node);
2463 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2464 ir_node *nomem = new_NoMem();
2465 ir_mode *mode = get_irn_mode(op);
2466 ir_mode *store_mode;
2467 ir_node *fild, *store;
2471 /* first convert to 32 bit signed if necessary */
2472 src_bits = get_mode_size_bits(src_mode);
2473 if (src_bits == 8) {
2474 new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
2476 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2478 } else if (src_bits < 32) {
2479 new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
2481 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
2485 assert(get_mode_size_bits(mode) == 32);
2488 store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
2491 set_ia32_use_frame(store);
2492 set_ia32_op_type(store, ia32_AddrModeD);
2493 set_ia32_ls_mode(store, mode_Iu);
2495 /* exception for 32bit unsigned, do a 64bit spill+load */
2496 if(!mode_is_signed(mode)) {
2499 ir_node *zero_const = create_Immediate_from_int(0);
2501 ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
2502 get_irg_frame(irg), noreg, nomem,
2505 set_ia32_use_frame(zero_store);
2506 set_ia32_op_type(zero_store, ia32_AddrModeD);
2507 add_ia32_am_offs_int(zero_store, 4);
2508 set_ia32_ls_mode(zero_store, mode_Iu);
2513 store = new_rd_Sync(dbgi, irg, block, 2, in);
2514 store_mode = mode_Ls;
2516 store_mode = mode_Is;
2520 fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
2522 set_ia32_use_frame(fild);
2523 set_ia32_op_type(fild, ia32_AddrModeS);
2524 set_ia32_ls_mode(fild, store_mode);
2526 res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
2532 * Crete a conversion from one integer mode into another one
2534 static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
2535 dbg_info *dbgi, ir_node *block, ir_node *op,
2538 ir_graph *irg = current_ir_graph;
2539 int src_bits = get_mode_size_bits(src_mode);
2540 int tgt_bits = get_mode_size_bits(tgt_mode);
2541 ir_node *new_block = be_transform_node(block);
2542 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2545 ir_mode *smaller_mode;
2547 ia32_address_mode_t am;
2548 ia32_address_t *addr = &am.addr;
2550 if (src_bits < tgt_bits) {
2551 smaller_mode = src_mode;
2552 smaller_bits = src_bits;
2554 smaller_mode = tgt_mode;
2555 smaller_bits = tgt_bits;
2558 memset(&am, 0, sizeof(am));
2559 if(use_source_address_mode(block, op, NULL)) {
2560 build_address(&am, op);
2562 am.op_type = ia32_AddrModeS;
2564 new_op = be_transform_node(op);
2565 am.op_type = ia32_Normal;
2567 if(addr->base == NULL)
2569 if(addr->index == NULL)
2570 addr->index = noreg;
2571 if(addr->mem == NULL)
2572 addr->mem = new_NoMem();
2574 DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
2575 if (smaller_bits == 8) {
2576 res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
2577 addr->index, addr->mem, new_op,
2580 res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
2581 addr->index, addr->mem, new_op,
2585 set_am_attributes(res, &am);
2586 set_ia32_ls_mode(res, smaller_mode);
2587 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
2588 res = fix_mem_proj(res, &am);
2594 * Transforms a Conv node.
2596 * @return The created ia32 Conv node
2598 static ir_node *gen_Conv(ir_node *node) {
2599 ir_node *block = get_nodes_block(node);
2600 ir_node *new_block = be_transform_node(block);
2601 ir_node *op = get_Conv_op(node);
2602 ir_node *new_op = NULL;
2603 ir_graph *irg = current_ir_graph;
2604 dbg_info *dbgi = get_irn_dbg_info(node);
2605 ir_mode *src_mode = get_irn_mode(op);
2606 ir_mode *tgt_mode = get_irn_mode(node);
2607 int src_bits = get_mode_size_bits(src_mode);
2608 int tgt_bits = get_mode_size_bits(tgt_mode);
2609 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
2610 ir_node *nomem = new_rd_NoMem(irg);
2611 ir_node *res = NULL;
2613 if (src_mode == mode_b) {
2614 assert(mode_is_int(tgt_mode));
2615 /* nothing to do, we already model bools as 0/1 ints */
2616 return be_transform_node(op);
2619 if (src_mode == tgt_mode) {
2620 if (get_Conv_strict(node)) {
2621 if (USE_SSE2(env_cg)) {
2622 /* when we are in SSE mode, we can kill all strict no-op conversion */
2623 return be_transform_node(op);
2626 /* this should be optimized already, but who knows... */
2627 DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
2628 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2629 return be_transform_node(op);
2633 if (mode_is_float(src_mode)) {
2634 new_op = be_transform_node(op);
2635 /* we convert from float ... */
2636 if (mode_is_float(tgt_mode)) {
2637 if(src_mode == mode_E && tgt_mode == mode_D
2638 && !get_Conv_strict(node)) {
2639 DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
2644 if (USE_SSE2(env_cg)) {
2645 DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
2646 res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
2648 set_ia32_ls_mode(res, tgt_mode);
2650 if(get_Conv_strict(node)) {
2651 res = gen_x87_strict_conv(tgt_mode, new_op);
2652 SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
2655 DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
2660 DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
2661 if (USE_SSE2(env_cg)) {
2662 res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
2664 set_ia32_ls_mode(res, src_mode);
2666 return gen_x87_fp_to_gp(node);
2670 /* we convert from int ... */
2671 if (mode_is_float(tgt_mode)) {
2673 DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
2674 if (USE_SSE2(env_cg)) {
2675 new_op = be_transform_node(op);
2676 res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
2678 set_ia32_ls_mode(res, tgt_mode);
2680 res = gen_x87_gp_to_fp(node, src_mode);
2681 if(get_Conv_strict(node)) {
2682 res = gen_x87_strict_conv(tgt_mode, res);
2683 SET_IA32_ORIG_NODE(get_Proj_pred(res),
2684 ia32_get_old_node_name(env_cg, node));
2688 } else if(tgt_mode == mode_b) {
2689 /* mode_b lowering already took care that we only have 0/1 values */
2690 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2691 src_mode, tgt_mode));
2692 return be_transform_node(op);
2695 if (src_bits == tgt_bits) {
2696 DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
2697 src_mode, tgt_mode));
2698 return be_transform_node(op);
2701 res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
2709 static int check_immediate_constraint(long val, char immediate_constraint_type)
2711 switch (immediate_constraint_type) {
2715 return val >= 0 && val <= 32;
2717 return val >= 0 && val <= 63;
2719 return val >= -128 && val <= 127;
2721 return val == 0xff || val == 0xffff;
2723 return val >= 0 && val <= 3;
2725 return val >= 0 && val <= 255;
2727 return val >= 0 && val <= 127;
2731 panic("Invalid immediate constraint found");
2735 static ir_node *try_create_Immediate(ir_node *node,
2736 char immediate_constraint_type)
2739 tarval *offset = NULL;
2740 int offset_sign = 0;
2742 ir_entity *symconst_ent = NULL;
2743 int symconst_sign = 0;
2745 ir_node *cnst = NULL;
2746 ir_node *symconst = NULL;
2752 mode = get_irn_mode(node);
2753 if(!mode_is_int(mode) && !mode_is_reference(mode)) {
2757 if(is_Minus(node)) {
2759 node = get_Minus_op(node);
2762 if(is_Const(node)) {
2765 offset_sign = minus;
2766 } else if(is_SymConst(node)) {
2769 symconst_sign = minus;
2770 } else if(is_Add(node)) {
2771 ir_node *left = get_Add_left(node);
2772 ir_node *right = get_Add_right(node);
2773 if(is_Const(left) && is_SymConst(right)) {
2776 symconst_sign = minus;
2777 offset_sign = minus;
2778 } else if(is_SymConst(left) && is_Const(right)) {
2781 symconst_sign = minus;
2782 offset_sign = minus;
2784 } else if(is_Sub(node)) {
2785 ir_node *left = get_Sub_left(node);
2786 ir_node *right = get_Sub_right(node);
2787 if(is_Const(left) && is_SymConst(right)) {
2790 symconst_sign = !minus;
2791 offset_sign = minus;
2792 } else if(is_SymConst(left) && is_Const(right)) {
2795 symconst_sign = minus;
2796 offset_sign = !minus;
2803 offset = get_Const_tarval(cnst);
2804 if(tarval_is_long(offset)) {
2805 val = get_tarval_long(offset);
2807 ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
2812 if(!check_immediate_constraint(val, immediate_constraint_type))
2815 if(symconst != NULL) {
2816 if(immediate_constraint_type != 0) {
2817 /* we need full 32bits for symconsts */
2821 /* unfortunately the assembler/linker doesn't support -symconst */
2825 if(get_SymConst_kind(symconst) != symconst_addr_ent)
2827 symconst_ent = get_SymConst_entity(symconst);
2829 if(cnst == NULL && symconst == NULL)
2832 if(offset_sign && offset != NULL) {
2833 offset = tarval_neg(offset);
2836 irg = current_ir_graph;
2837 dbgi = get_irn_dbg_info(node);
2838 block = get_irg_start_block(irg);
2839 res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
2840 symconst_sign, val);
2841 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
2846 static ir_node *create_immediate_or_transform(ir_node *node,
2847 char immediate_constraint_type)
2849 ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
2850 if (new_node == NULL) {
2851 new_node = be_transform_node(node);
2856 typedef struct constraint_t constraint_t;
2857 struct constraint_t {
2860 const arch_register_req_t **out_reqs;
2862 const arch_register_req_t *req;
2863 unsigned immediate_possible;
2864 char immediate_type;
2867 void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
2869 int immediate_possible = 0;
2870 char immediate_type = 0;
2871 unsigned limited = 0;
2872 const arch_register_class_t *cls = NULL;
2873 ir_graph *irg = current_ir_graph;
2874 struct obstack *obst = get_irg_obstack(irg);
2875 arch_register_req_t *req;
2876 unsigned *limited_ptr;
2880 /* TODO: replace all the asserts with nice error messages */
2882 printf("Constraint: %s\n", c);
2892 assert(cls == NULL ||
2893 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2894 cls = &ia32_reg_classes[CLASS_ia32_gp];
2895 limited |= 1 << REG_EAX;
2898 assert(cls == NULL ||
2899 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2900 cls = &ia32_reg_classes[CLASS_ia32_gp];
2901 limited |= 1 << REG_EBX;
2904 assert(cls == NULL ||
2905 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2906 cls = &ia32_reg_classes[CLASS_ia32_gp];
2907 limited |= 1 << REG_ECX;
2910 assert(cls == NULL ||
2911 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2912 cls = &ia32_reg_classes[CLASS_ia32_gp];
2913 limited |= 1 << REG_EDX;
2916 assert(cls == NULL ||
2917 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2918 cls = &ia32_reg_classes[CLASS_ia32_gp];
2919 limited |= 1 << REG_EDI;
2922 assert(cls == NULL ||
2923 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2924 cls = &ia32_reg_classes[CLASS_ia32_gp];
2925 limited |= 1 << REG_ESI;
2928 case 'q': /* q means lower part of the regs only, this makes no
2929 * difference to Q for us (we only assigne whole registers) */
2930 assert(cls == NULL ||
2931 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2932 cls = &ia32_reg_classes[CLASS_ia32_gp];
2933 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2937 assert(cls == NULL ||
2938 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2939 cls = &ia32_reg_classes[CLASS_ia32_gp];
2940 limited |= 1 << REG_EAX | 1 << REG_EDX;
2943 assert(cls == NULL ||
2944 (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
2945 cls = &ia32_reg_classes[CLASS_ia32_gp];
2946 limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
2947 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
2954 assert(cls == NULL);
2955 cls = &ia32_reg_classes[CLASS_ia32_gp];
2961 /* TODO: mark values so the x87 simulator knows about t and u */
2962 assert(cls == NULL);
2963 cls = &ia32_reg_classes[CLASS_ia32_vfp];
2968 assert(cls == NULL);
2969 /* TODO: check that sse2 is supported */
2970 cls = &ia32_reg_classes[CLASS_ia32_xmm];
2980 assert(!immediate_possible);
2981 immediate_possible = 1;
2982 immediate_type = *c;
2986 assert(!immediate_possible);
2987 immediate_possible = 1;
2991 assert(!immediate_possible && cls == NULL);
2992 immediate_possible = 1;
2993 cls = &ia32_reg_classes[CLASS_ia32_gp];
3006 assert(constraint->is_in && "can only specify same constraint "
3009 sscanf(c, "%d%n", &same_as, &p);
3016 case 'E': /* no float consts yet */
3017 case 'F': /* no float consts yet */
3018 case 's': /* makes no sense on x86 */
3019 case 'X': /* we can't support that in firm */
3023 case '<': /* no autodecrement on x86 */
3024 case '>': /* no autoincrement on x86 */
3025 case 'C': /* sse constant not supported yet */
3026 case 'G': /* 80387 constant not supported yet */
3027 case 'y': /* we don't support mmx registers yet */
3028 case 'Z': /* not available in 32 bit mode */
3029 case 'e': /* not available in 32 bit mode */
3030 assert(0 && "asm constraint not supported");
3033 assert(0 && "unknown asm constraint found");
3040 const arch_register_req_t *other_constr;
3042 assert(cls == NULL && "same as and register constraint not supported");
3043 assert(!immediate_possible && "same as and immediate constraint not "
3045 assert(same_as < constraint->n_outs && "wrong constraint number in "
3046 "same_as constraint");
3048 other_constr = constraint->out_reqs[same_as];
3050 req = obstack_alloc(obst, sizeof(req[0]));
3051 req->cls = other_constr->cls;
3052 req->type = arch_register_req_type_should_be_same;
3053 req->limited = NULL;
3054 req->other_same = pos;
3055 req->other_different = -1;
3057 /* switch constraints. This is because in firm we have same_as
3058 * constraints on the output constraints while in the gcc asm syntax
3059 * they are specified on the input constraints */
3060 constraint->req = other_constr;
3061 constraint->out_reqs[same_as] = req;
3062 constraint->immediate_possible = 0;
3066 if(immediate_possible && cls == NULL) {
3067 cls = &ia32_reg_classes[CLASS_ia32_gp];
3069 assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
3070 assert(cls != NULL);
3072 if(immediate_possible) {
3073 assert(constraint->is_in
3074 && "imeediates make no sense for output constraints");
3076 /* todo: check types (no float input on 'r' constrained in and such... */
3079 req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
3080 limited_ptr = (unsigned*) (req+1);
3082 req = obstack_alloc(obst, sizeof(req[0]));
3084 memset(req, 0, sizeof(req[0]));
3087 req->type = arch_register_req_type_limited;
3088 *limited_ptr = limited;
3089 req->limited = limited_ptr;
3091 req->type = arch_register_req_type_normal;
3095 constraint->req = req;
3096 constraint->immediate_possible = immediate_possible;
3097 constraint->immediate_type = immediate_type;
3100 static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
3107 panic("Clobbers not supported yet");
3111 * generates code for a ASM node
3113 static ir_node *gen_ASM(ir_node *node)
3116 ir_graph *irg = current_ir_graph;
3117 ir_node *block = be_transform_node(get_nodes_block(node));
3118 dbg_info *dbgi = get_irn_dbg_info(node);
3125 ia32_asm_attr_t *attr;
3126 const arch_register_req_t **out_reqs;
3127 const arch_register_req_t **in_reqs;
3128 struct obstack *obst;
3129 constraint_t parsed_constraint;
3131 /* transform inputs */
3132 arity = get_irn_arity(node);
3133 in = alloca(arity * sizeof(in[0]));
3134 memset(in, 0, arity * sizeof(in[0]));
3136 n_outs = get_ASM_n_output_constraints(node);
3137 n_clobbers = get_ASM_n_clobbers(node);
3138 out_arity = n_outs + n_clobbers;
3140 /* construct register constraints */
3141 obst = get_irg_obstack(irg);
3142 out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
3143 parsed_constraint.out_reqs = out_reqs;
3144 parsed_constraint.n_outs = n_outs;
3145 parsed_constraint.is_in = 0;
3146 for(i = 0; i < out_arity; ++i) {
3150 const ir_asm_constraint *constraint;
3151 constraint = & get_ASM_output_constraints(node) [i];
3152 c = get_id_str(constraint->constraint);
3153 parse_asm_constraint(i, &parsed_constraint, c);
3155 ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
3156 c = get_id_str(glob_id);
3157 parse_clobber(node, i, &parsed_constraint, c);
3159 out_reqs[i] = parsed_constraint.req;
3162 in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
3163 parsed_constraint.is_in = 1;
3164 for(i = 0; i < arity; ++i) {
3165 const ir_asm_constraint *constraint;
3169 constraint = & get_ASM_input_constraints(node) [i];
3170 constr_id = constraint->constraint;
3171 c = get_id_str(constr_id);
3172 parse_asm_constraint(i, &parsed_constraint, c);
3173 in_reqs[i] = parsed_constraint.req;
3175 if(parsed_constraint.immediate_possible) {
3176 ir_node *pred = get_irn_n(node, i);
3177 char imm_type = parsed_constraint.immediate_type;
3178 ir_node *immediate = try_create_Immediate(pred, imm_type);
3180 if(immediate != NULL) {
3186 /* transform inputs */
3187 for(i = 0; i < arity; ++i) {
3189 ir_node *transformed;
3194 pred = get_irn_n(node, i);
3195 transformed = be_transform_node(pred);
3196 in[i] = transformed;
3199 res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
3201 generic_attr = get_irn_generic_attr(res);
3202 attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
3203 attr->asm_text = get_ASM_text(node);
3204 set_ia32_out_req_all(res, out_reqs);
3205 set_ia32_in_req_all(res, in_reqs);
3207 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3212 /********************************************
3215 * | |__ ___ _ __ ___ __| | ___ ___
3216 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
3217 * | |_) | __/ | | | (_) | (_| | __/\__ \
3218 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
3220 ********************************************/
3223 * Transforms a FrameAddr into an ia32 Add.
3225 static ir_node *gen_be_FrameAddr(ir_node *node) {
3226 ir_node *block = be_transform_node(get_nodes_block(node));
3227 ir_node *op = be_get_FrameAddr_frame(node);
3228 ir_node *new_op = be_transform_node(op);
3229 ir_graph *irg = current_ir_graph;
3230 dbg_info *dbgi = get_irn_dbg_info(node);
3231 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3234 res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
3235 set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
3236 set_ia32_use_frame(res);
3238 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
3244 * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
3246 static ir_node *gen_be_Return(ir_node *node) {
3247 ir_graph *irg = current_ir_graph;
3248 ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
3249 ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
3250 ir_entity *ent = get_irg_entity(irg);
3251 ir_type *tp = get_entity_type(ent);
3256 ir_node *frame, *sse_store, *fld, *mproj, *barrier;
3257 ir_node *new_barrier, *new_ret_val, *new_ret_mem;
3260 int pn_ret_val, pn_ret_mem, arity, i;
3262 assert(ret_val != NULL);
3263 if (be_Return_get_n_rets(node) < 1 || ! USE_SSE2(env_cg)) {
3264 return be_duplicate_node(node);
3267 res_type = get_method_res_type(tp, 0);
3269 if (! is_Primitive_type(res_type)) {
3270 return be_duplicate_node(node);
3273 mode = get_type_mode(res_type);
3274 if (! mode_is_float(mode)) {
3275 return be_duplicate_node(node);
3278 assert(get_method_n_ress(tp) == 1);
3280 pn_ret_val = get_Proj_proj(ret_val);
3281 pn_ret_mem = get_Proj_proj(ret_mem);
3283 /* get the Barrier */
3284 barrier = get_Proj_pred(ret_val);
3286 /* get result input of the Barrier */
3287 ret_val = get_irn_n(barrier, pn_ret_val);
3288 new_ret_val = be_transform_node(ret_val);
3290 /* get memory input of the Barrier */
3291 ret_mem = get_irn_n(barrier, pn_ret_mem);
3292 new_ret_mem = be_transform_node(ret_mem);
3294 frame = get_irg_frame(irg);
3296 dbgi = get_irn_dbg_info(barrier);
3297 block = be_transform_node(get_nodes_block(barrier));
3299 noreg = ia32_new_NoReg_gp(env_cg);
3301 /* store xmm0 onto stack */
3302 sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
3303 new_ret_mem, new_ret_val);
3304 set_ia32_ls_mode(sse_store, mode);
3305 set_ia32_op_type(sse_store, ia32_AddrModeD);
3306 set_ia32_use_frame(sse_store);
3308 /* load into x87 register */
3309 fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
3310 set_ia32_op_type(fld, ia32_AddrModeS);
3311 set_ia32_use_frame(fld);
3313 mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
3314 fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
3316 /* create a new barrier */
3317 arity = get_irn_arity(barrier);
3318 in = alloca(arity * sizeof(in[0]));
3319 for (i = 0; i < arity; ++i) {
3322 if (i == pn_ret_val) {
3324 } else if (i == pn_ret_mem) {
3327 ir_node *in = get_irn_n(barrier, i);
3328 new_in = be_transform_node(in);
3333 new_barrier = new_ir_node(dbgi, irg, block,
3334 get_irn_op(barrier), get_irn_mode(barrier),
3336 copy_node_attr(barrier, new_barrier);
3337 be_duplicate_deps(barrier, new_barrier);
3338 be_set_transformed_node(barrier, new_barrier);
3339 mark_irn_visited(barrier);
3341 /* transform normally */
3342 return be_duplicate_node(node);
3346 * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
3348 static ir_node *gen_be_AddSP(ir_node *node) {
3349 ir_node *block = be_transform_node(get_nodes_block(node));
3350 ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
3352 ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
3353 ir_node *new_sp = be_transform_node(sp);
3354 ir_graph *irg = current_ir_graph;
3355 dbg_info *dbgi = get_irn_dbg_info(node);
3356 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3357 ir_node *nomem = new_NoMem();
3360 new_sz = create_immediate_or_transform(sz, 0);
3362 /* ia32 stack grows in reverse direction, make a SubSP */
3363 new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3365 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3371 * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
3373 static ir_node *gen_be_SubSP(ir_node *node) {
3374 ir_node *block = be_transform_node(get_nodes_block(node));
3375 ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
3377 ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
3378 ir_node *new_sp = be_transform_node(sp);
3379 ir_graph *irg = current_ir_graph;
3380 dbg_info *dbgi = get_irn_dbg_info(node);
3381 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3382 ir_node *nomem = new_NoMem();
3385 new_sz = create_immediate_or_transform(sz, 0);
3387 /* ia32 stack grows in reverse direction, make an AddSP */
3388 new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
3390 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3396 * This function just sets the register for the Unknown node
3397 * as this is not done during register allocation because Unknown
3398 * is an "ignore" node.
3400 static ir_node *gen_Unknown(ir_node *node) {
3401 ir_mode *mode = get_irn_mode(node);
3403 if (mode_is_float(mode)) {
3404 if (USE_SSE2(env_cg)) {
3405 return ia32_new_Unknown_xmm(env_cg);
3407 /* Unknown nodes are buggy in x87 sim, use zero for now... */
3408 ir_graph *irg = current_ir_graph;
3409 dbg_info *dbgi = get_irn_dbg_info(node);
3410 ir_node *block = get_irg_start_block(irg);
3411 return new_rd_ia32_vfldz(dbgi, irg, block);
3413 } else if (mode_needs_gp_reg(mode)) {
3414 return ia32_new_Unknown_gp(env_cg);
3416 assert(0 && "unsupported Unknown-Mode");
3423 * Change some phi modes
3425 static ir_node *gen_Phi(ir_node *node) {
3426 ir_node *block = be_transform_node(get_nodes_block(node));
3427 ir_graph *irg = current_ir_graph;
3428 dbg_info *dbgi = get_irn_dbg_info(node);
3429 ir_mode *mode = get_irn_mode(node);
3432 if(mode_needs_gp_reg(mode)) {
3433 /* we shouldn't have any 64bit stuff around anymore */
3434 assert(get_mode_size_bits(mode) <= 32);
3435 /* all integer operations are on 32bit registers now */
3437 } else if(mode_is_float(mode)) {
3438 if (USE_SSE2(env_cg)) {
3445 /* phi nodes allow loops, so we use the old arguments for now
3446 * and fix this later */
3447 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
3448 get_irn_in(node) + 1);
3449 copy_node_attr(node, phi);
3450 be_duplicate_deps(node, phi);
3452 be_set_transformed_node(node, phi);
3453 be_enqueue_preds(node);
3461 static ir_node *gen_IJmp(ir_node *node) {
3462 /* TODO: support AM */
3463 return gen_unop(node, get_IJmp_target(node), new_rd_ia32_IJmp);
3467 /**********************************************************************
3470 * | | _____ _____ _ __ ___ __| | _ __ ___ __| | ___ ___
3471 * | |/ _ \ \ /\ / / _ \ '__/ _ \/ _` | | '_ \ / _ \ / _` |/ _ \/ __|
3472 * | | (_) \ V V / __/ | | __/ (_| | | | | | (_) | (_| | __/\__ \
3473 * |_|\___/ \_/\_/ \___|_| \___|\__,_| |_| |_|\___/ \__,_|\___||___/
3475 **********************************************************************/
3477 /* These nodes are created in intrinsic lowering (64bit -> 32bit) */
3479 typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3482 typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
3483 ir_node *val, ir_node *mem);
3486 * Transforms a lowered Load into a "real" one.
3488 static ir_node *gen_lowered_Load(ir_node *node, construct_load_func func)
3490 ir_node *block = be_transform_node(get_nodes_block(node));
3491 ir_node *ptr = get_irn_n(node, 0);
3492 ir_node *new_ptr = be_transform_node(ptr);
3493 ir_node *mem = get_irn_n(node, 1);
3494 ir_node *new_mem = be_transform_node(mem);
3495 ir_graph *irg = current_ir_graph;
3496 dbg_info *dbgi = get_irn_dbg_info(node);
3497 ir_mode *mode = get_ia32_ls_mode(node);
3498 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3501 new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
3503 set_ia32_op_type(new_op, ia32_AddrModeS);
3504 set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
3505 set_ia32_am_scale(new_op, get_ia32_am_scale(node));
3506 set_ia32_am_sc(new_op, get_ia32_am_sc(node));
3507 if (is_ia32_am_sc_sign(node))
3508 set_ia32_am_sc_sign(new_op);
3509 set_ia32_ls_mode(new_op, mode);
3510 if (is_ia32_use_frame(node)) {
3511 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3512 set_ia32_use_frame(new_op);
3515 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3521 * Transforms a lowered Store into a "real" one.
3523 static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
3525 ir_node *block = be_transform_node(get_nodes_block(node));
3526 ir_node *ptr = get_irn_n(node, 0);
3527 ir_node *new_ptr = be_transform_node(ptr);
3528 ir_node *val = get_irn_n(node, 1);
3529 ir_node *new_val = be_transform_node(val);
3530 ir_node *mem = get_irn_n(node, 2);
3531 ir_node *new_mem = be_transform_node(mem);
3532 ir_graph *irg = current_ir_graph;
3533 dbg_info *dbgi = get_irn_dbg_info(node);
3534 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3535 ir_mode *mode = get_ia32_ls_mode(node);
3539 new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
3541 am_offs = get_ia32_am_offs_int(node);
3542 add_ia32_am_offs_int(new_op, am_offs);
3544 set_ia32_op_type(new_op, ia32_AddrModeD);
3545 set_ia32_ls_mode(new_op, mode);
3546 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3547 set_ia32_use_frame(new_op);
3549 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3556 * Transforms an ia32_l_XXX into a "real" XXX node
3558 * @param node The node to transform
3559 * @return the created ia32 XXX node
3561 #define GEN_LOWERED_OP(op) \
3562 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3563 return gen_binop(node, get_binop_left(node), \
3564 get_binop_right(node), new_rd_ia32_##op,0); \
3567 #define GEN_LOWERED_x87_OP(op) \
3568 static ir_node *gen_ia32_l_##op(ir_node *node) { \
3570 new_op = gen_binop_x87_float(node, get_binop_left(node), \
3571 get_binop_right(node), new_rd_ia32_##op); \
3575 #define GEN_LOWERED_SHIFT_OP(l_op, op) \
3576 static ir_node *gen_ia32_##l_op(ir_node *node) { \
3577 return gen_shift_binop(node, get_irn_n(node, 0), \
3578 get_irn_n(node, 1), new_rd_ia32_##op); \
3581 GEN_LOWERED_x87_OP(vfprem)
3582 GEN_LOWERED_x87_OP(vfmul)
3583 GEN_LOWERED_x87_OP(vfsub)
3584 GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
3585 GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
3586 GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
3587 GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
3589 static ir_node *gen_ia32_l_Add(ir_node *node) {
3590 ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
3591 ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
3592 ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
3594 if(is_Proj(lowered)) {
3595 lowered = get_Proj_pred(lowered);
3597 assert(is_ia32_Add(lowered));
3598 set_irn_mode(lowered, mode_T);
3604 static ir_node *gen_ia32_l_Adc(ir_node *node) {
3605 ir_node *src_block = get_nodes_block(node);
3606 ir_node *block = be_transform_node(src_block);
3607 ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
3608 ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
3609 ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
3610 ir_node *new_flags = be_transform_node(flags);
3611 ir_graph *irg = current_ir_graph;
3612 dbg_info *dbgi = get_irn_dbg_info(node);
3614 ia32_address_mode_t am;
3615 ia32_address_t *addr = &am.addr;
3617 match_arguments(&am, src_block, op1, op2, match_commutative);
3619 new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
3620 addr->mem, am.new_op1, am.new_op2, new_flags);
3621 set_am_attributes(new_node, &am);
3622 /* we can't use source address mode anymore when using immediates */
3623 if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
3624 set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
3625 SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
3627 new_node = fix_mem_proj(new_node, &am);
3633 * Transforms an ia32_l_Neg into a "real" ia32_Neg node
3635 * @param node The node to transform
3636 * @return the created ia32 Neg node
3638 static ir_node *gen_ia32_l_Neg(ir_node *node) {
3639 return gen_unop(node, get_unop_op(node), new_rd_ia32_Neg);
3643 * Transforms an ia32_l_vfild into a "real" ia32_vfild node
3645 * @param node The node to transform
3646 * @return the created ia32 vfild node
3648 static ir_node *gen_ia32_l_vfild(ir_node *node) {
3649 return gen_lowered_Load(node, new_rd_ia32_vfild);
3653 * Transforms an ia32_l_Load into a "real" ia32_Load node
3655 * @param node The node to transform
3656 * @return the created ia32 Load node
3658 static ir_node *gen_ia32_l_Load(ir_node *node) {
3659 return gen_lowered_Load(node, new_rd_ia32_Load);
3663 * Transforms an ia32_l_Store into a "real" ia32_Store node
3665 * @param node The node to transform
3666 * @return the created ia32 Store node
3668 static ir_node *gen_ia32_l_Store(ir_node *node) {
3669 return gen_lowered_Store(node, new_rd_ia32_Store);
3673 * Transforms a l_vfist into a "real" vfist node.
3675 * @param node The node to transform
3676 * @return the created ia32 vfist node
3678 static ir_node *gen_ia32_l_vfist(ir_node *node) {
3679 ir_node *block = be_transform_node(get_nodes_block(node));
3680 ir_node *ptr = get_irn_n(node, 0);
3681 ir_node *new_ptr = be_transform_node(ptr);
3682 ir_node *val = get_irn_n(node, 1);
3683 ir_node *new_val = be_transform_node(val);
3684 ir_node *mem = get_irn_n(node, 2);
3685 ir_node *new_mem = be_transform_node(mem);
3686 ir_graph *irg = current_ir_graph;
3687 dbg_info *dbgi = get_irn_dbg_info(node);
3688 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3689 ir_mode *mode = get_ia32_ls_mode(node);
3690 ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
3694 new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
3695 new_val, trunc_mode);
3697 am_offs = get_ia32_am_offs_int(node);
3698 add_ia32_am_offs_int(new_op, am_offs);
3700 set_ia32_op_type(new_op, ia32_AddrModeD);
3701 set_ia32_ls_mode(new_op, mode);
3702 set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
3703 set_ia32_use_frame(new_op);
3705 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3711 * Transforms a l_vfdiv into a "real" vfdiv node.
3713 * @param env The transformation environment
3714 * @return the created ia32 vfdiv node
3716 static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
3717 ir_node *block = be_transform_node(get_nodes_block(node));
3718 ir_node *left = get_binop_left(node);
3719 ir_node *new_left = be_transform_node(left);
3720 ir_node *right = get_binop_right(node);
3721 ir_node *new_right = be_transform_node(right);
3722 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3723 ir_graph *irg = current_ir_graph;
3724 dbg_info *dbgi = get_irn_dbg_info(node);
3725 ir_node *fpcw = get_fpcw();
3728 vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
3729 new_left, new_right, fpcw);
3730 clear_ia32_commutative(vfdiv);
3732 SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
3738 * Transforms a l_MulS into a "real" MulS node.
3740 * @param env The transformation environment
3741 * @return the created ia32 Mul node
3743 static ir_node *gen_ia32_l_Mul(ir_node *node) {
3744 ir_node *block = be_transform_node(get_nodes_block(node));
3745 ir_node *left = get_binop_left(node);
3746 ir_node *new_left = be_transform_node(left);
3747 ir_node *right = get_binop_right(node);
3748 ir_node *new_right = be_transform_node(right);
3749 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3750 ir_graph *irg = current_ir_graph;
3751 dbg_info *dbgi = get_irn_dbg_info(node);
3753 /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
3754 /* and then skip the result Proj, because all needed Projs are already there. */
3755 ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
3756 new_left, new_right);
3757 clear_ia32_commutative(muls);
3759 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3765 * Transforms a l_IMulS into a "real" IMul1OPS node.
3767 * @param env The transformation environment
3768 * @return the created ia32 IMul1OP node
3770 static ir_node *gen_ia32_l_IMul(ir_node *node) {
3771 ir_node *block = be_transform_node(get_nodes_block(node));
3772 ir_node *left = get_binop_left(node);
3773 ir_node *new_left = be_transform_node(left);
3774 ir_node *right = get_binop_right(node);
3775 ir_node *new_right = be_transform_node(right);
3776 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
3777 ir_graph *irg = current_ir_graph;
3778 dbg_info *dbgi = get_irn_dbg_info(node);
3780 /* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
3781 /* and then skip the result Proj, because all needed Projs are already there. */
3782 ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
3783 new_NoMem(), new_left, new_right);
3784 clear_ia32_commutative(muls);
3786 SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
3791 static ir_node *gen_ia32_Add64Bit(ir_node *node)
3793 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3794 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3795 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3796 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3797 ir_node *block = be_transform_node(get_nodes_block(node));
3798 dbg_info *dbgi = get_irn_dbg_info(node);
3799 ir_graph *irg = current_ir_graph;
3800 ir_node *new_op = new_rd_ia32_Add64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3801 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3805 static ir_node *gen_ia32_Sub64Bit(ir_node *node)
3807 ir_node *a_l = be_transform_node(get_irn_n(node, 0));
3808 ir_node *a_h = be_transform_node(get_irn_n(node, 1));
3809 ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
3810 ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
3811 ir_node *block = be_transform_node(get_nodes_block(node));
3812 dbg_info *dbgi = get_irn_dbg_info(node);
3813 ir_graph *irg = current_ir_graph;
3814 ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
3815 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3820 * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
3821 * op1 - target to be shifted
3822 * op2 - contains bits to be shifted into target
3824 * Only op3 can be an immediate.
3826 static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
3827 ir_node *op2, ir_node *count)
3829 ir_node *block = be_transform_node(get_nodes_block(node));
3830 ir_node *new_op = NULL;
3831 ir_graph *irg = current_ir_graph;
3832 dbg_info *dbgi = get_irn_dbg_info(node);
3833 ir_node *new_op1 = be_transform_node(op1);
3834 ir_node *new_op2 = be_transform_node(op2);
3835 ir_node *new_count = create_immediate_or_transform(count, 'I');
3837 /* TODO proper AM support */
3839 if (is_ia32_l_ShlD(node))
3840 new_op = new_rd_ia32_ShlD(dbgi, irg, block, new_op1, new_op2, new_count);
3842 new_op = new_rd_ia32_ShrD(dbgi, irg, block, new_op1, new_op2, new_count);
3844 SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
3849 static ir_node *gen_ia32_l_ShlD(ir_node *node) {
3850 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3851 get_irn_n(node, 1), get_irn_n(node, 2));
3854 static ir_node *gen_ia32_l_ShrD(ir_node *node) {
3855 return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
3856 get_irn_n(node, 1), get_irn_n(node, 2));
3860 * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
3862 static ir_node *gen_ia32_l_X87toSSE(ir_node *node) {
3863 ir_node *block = be_transform_node(get_nodes_block(node));
3864 ir_node *val = get_irn_n(node, 1);
3865 ir_node *new_val = be_transform_node(val);
3866 ia32_code_gen_t *cg = env_cg;
3867 ir_node *res = NULL;
3868 ir_graph *irg = current_ir_graph;
3870 ir_node *noreg, *new_ptr, *new_mem;
3877 mem = get_irn_n(node, 2);
3878 new_mem = be_transform_node(mem);
3879 ptr = get_irn_n(node, 0);
3880 new_ptr = be_transform_node(ptr);
3881 noreg = ia32_new_NoReg_gp(cg);
3882 dbgi = get_irn_dbg_info(node);
3884 /* Store x87 -> MEM */
3885 res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
3886 get_ia32_ls_mode(node));
3887 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3888 set_ia32_use_frame(res);
3889 set_ia32_ls_mode(res, get_ia32_ls_mode(node));
3890 set_ia32_op_type(res, ia32_AddrModeD);
3892 /* Load MEM -> SSE */
3893 res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
3894 get_ia32_ls_mode(node));
3895 set_ia32_frame_ent(res, get_ia32_frame_ent(node));
3896 set_ia32_use_frame(res);
3897 set_ia32_op_type(res, ia32_AddrModeS);
3898 res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
3904 * In case SSE Unit is used, the node is transformed into a xStore + vfld.
3906 static ir_node *gen_ia32_l_SSEtoX87(ir_node *node) {
3907 ir_node *block = be_transform_node(get_nodes_block(node));
3908 ir_node *val = get_irn_n(node, 1);
3909 ir_node *new_val = be_transform_node(val);
3910 ia32_code_gen_t *cg = env_cg;
3911 ir_graph *irg = current_ir_graph;
3912 ir_node *res = NULL;
3913 ir_entity *fent = get_ia32_frame_ent(node);
3914 ir_mode *lsmode = get_ia32_ls_mode(node);
3916 ir_node *noreg, *new_ptr, *new_mem;
3920 if (! USE_SSE2(cg)) {
3921 /* SSE unit is not used -> skip this node. */
3925 ptr = get_irn_n(node, 0);
3926 new_ptr = be_transform_node(ptr);
3927 mem = get_irn_n(node, 2);
3928 new_mem = be_transform_node(mem);
3929 noreg = ia32_new_NoReg_gp(cg);
3930 dbgi = get_irn_dbg_info(node);
3932 /* Store SSE -> MEM */
3933 if (is_ia32_xLoad(skip_Proj(new_val))) {
3934 ir_node *ld = skip_Proj(new_val);
3936 /* we can vfld the value directly into the fpu */
3937 fent = get_ia32_frame_ent(ld);
3938 ptr = get_irn_n(ld, 0);
3939 offs = get_ia32_am_offs_int(ld);
3941 res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
3943 set_ia32_frame_ent(res, fent);
3944 set_ia32_use_frame(res);
3945 set_ia32_ls_mode(res, lsmode);
3946 set_ia32_op_type(res, ia32_AddrModeD);
3950 /* Load MEM -> x87 */
3951 res = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, lsmode);
3952 set_ia32_frame_ent(res, fent);
3953 set_ia32_use_frame(res);
3954 add_ia32_am_offs_int(res, offs);
3955 set_ia32_op_type(res, ia32_AddrModeS);
3956 res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
3961 /*********************************************************
3964 * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
3965 * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
3966 * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
3967 * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
3969 *********************************************************/
3972 * the BAD transformer.
3974 static ir_node *bad_transform(ir_node *node) {
3975 panic("No transform function for %+F available.\n", node);
3980 * Transform the Projs of an AddSP.
3982 static ir_node *gen_Proj_be_AddSP(ir_node *node) {
3983 ir_node *block = be_transform_node(get_nodes_block(node));
3984 ir_node *pred = get_Proj_pred(node);
3985 ir_node *new_pred = be_transform_node(pred);
3986 ir_graph *irg = current_ir_graph;
3987 dbg_info *dbgi = get_irn_dbg_info(node);
3988 long proj = get_Proj_proj(node);
3990 if (proj == pn_be_AddSP_sp) {
3991 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3992 pn_ia32_SubSP_stack);
3993 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
3995 } else if(proj == pn_be_AddSP_res) {
3996 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
3997 pn_ia32_SubSP_addr);
3998 } else if (proj == pn_be_AddSP_M) {
3999 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_SubSP_M);
4003 return new_rd_Unknown(irg, get_irn_mode(node));
4007 * Transform the Projs of a SubSP.
4009 static ir_node *gen_Proj_be_SubSP(ir_node *node) {
4010 ir_node *block = be_transform_node(get_nodes_block(node));
4011 ir_node *pred = get_Proj_pred(node);
4012 ir_node *new_pred = be_transform_node(pred);
4013 ir_graph *irg = current_ir_graph;
4014 dbg_info *dbgi = get_irn_dbg_info(node);
4015 long proj = get_Proj_proj(node);
4017 if (proj == pn_be_SubSP_sp) {
4018 ir_node *res = new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4019 pn_ia32_AddSP_stack);
4020 arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_ESP]);
4022 } else if (proj == pn_be_SubSP_M) {
4023 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_AddSP_M);
4027 return new_rd_Unknown(irg, get_irn_mode(node));
4031 * Transform and renumber the Projs from a Load.
4033 static ir_node *gen_Proj_Load(ir_node *node) {
4035 ir_node *block = be_transform_node(get_nodes_block(node));
4036 ir_node *pred = get_Proj_pred(node);
4037 ir_graph *irg = current_ir_graph;
4038 dbg_info *dbgi = get_irn_dbg_info(node);
4039 long proj = get_Proj_proj(node);
4042 /* loads might be part of source address mode matches, so we don't
4043 transform the ProjMs yet (with the exception of loads whose result is
4046 if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
4049 assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
4051 /* this is needed, because sometimes we have loops that are only
4052 reachable through the ProjM */
4053 be_enqueue_preds(node);
4054 /* do it in 2 steps, to silence firm verifier */
4055 res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
4056 set_Proj_proj(res, pn_ia32_Load_M);
4060 /* renumber the proj */
4061 new_pred = be_transform_node(pred);
4062 if (is_ia32_Load(new_pred)) {
4063 if (proj == pn_Load_res) {
4064 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
4066 } else if (proj == pn_Load_M) {
4067 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4070 } else if(is_ia32_Conv_I2I(new_pred)) {
4071 set_irn_mode(new_pred, mode_T);
4072 if (proj == pn_Load_res) {
4073 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
4074 } else if (proj == pn_Load_M) {
4075 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
4077 } else if (is_ia32_xLoad(new_pred)) {
4078 if (proj == pn_Load_res) {
4079 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
4081 } else if (proj == pn_Load_M) {
4082 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4085 } else if (is_ia32_vfld(new_pred)) {
4086 if (proj == pn_Load_res) {
4087 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
4089 } else if (proj == pn_Load_M) {
4090 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
4094 /* can happen for ProJMs when source address mode happened for the
4097 /* however it should not be the result proj, as that would mean the
4098 load had multiple users and should not have been used for
4100 if(proj != pn_Load_M) {
4101 panic("internal error: transformed node not a Load");
4103 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
4107 return new_rd_Unknown(irg, get_irn_mode(node));
4111 * Transform and renumber the Projs from a DivMod like instruction.
4113 static ir_node *gen_Proj_DivMod(ir_node *node) {
4114 ir_node *block = be_transform_node(get_nodes_block(node));
4115 ir_node *pred = get_Proj_pred(node);
4116 ir_node *new_pred = be_transform_node(pred);
4117 ir_graph *irg = current_ir_graph;
4118 dbg_info *dbgi = get_irn_dbg_info(node);
4119 ir_mode *mode = get_irn_mode(node);
4120 long proj = get_Proj_proj(node);
4122 assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
4124 switch (get_irn_opcode(pred)) {
4128 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4130 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4138 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4140 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4148 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Div_M);
4149 case pn_DivMod_res_div:
4150 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
4151 case pn_DivMod_res_mod:
4152 return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
4162 return new_rd_Unknown(irg, mode);
4166 * Transform and renumber the Projs from a CopyB.
4168 static ir_node *gen_Proj_CopyB(ir_node *node) {
4169 ir_node *block = be_transform_node(get_nodes_block(node));
4170 ir_node *pred = get_Proj_pred(node);
4171 ir_node *new_pred = be_transform_node(pred);
4172 ir_graph *irg = current_ir_graph;
4173 dbg_info *dbgi = get_irn_dbg_info(node);
4174 ir_mode *mode = get_irn_mode(node);
4175 long proj = get_Proj_proj(node);
4178 case pn_CopyB_M_regular:
4179 if (is_ia32_CopyB_i(new_pred)) {
4180 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
4181 } else if (is_ia32_CopyB(new_pred)) {
4182 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_CopyB_M);
4190 return new_rd_Unknown(irg, mode);
4194 * Transform and renumber the Projs from a vfdiv.
4196 static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
4197 ir_node *block = be_transform_node(get_nodes_block(node));
4198 ir_node *pred = get_Proj_pred(node);
4199 ir_node *new_pred = be_transform_node(pred);
4200 ir_graph *irg = current_ir_graph;
4201 dbg_info *dbgi = get_irn_dbg_info(node);
4202 ir_mode *mode = get_irn_mode(node);
4203 long proj = get_Proj_proj(node);
4206 case pn_ia32_l_vfdiv_M:
4207 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4208 case pn_ia32_l_vfdiv_res:
4209 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4214 return new_rd_Unknown(irg, mode);
4218 * Transform and renumber the Projs from a Quot.
4220 static ir_node *gen_Proj_Quot(ir_node *node) {
4221 ir_node *block = be_transform_node(get_nodes_block(node));
4222 ir_node *pred = get_Proj_pred(node);
4223 ir_node *new_pred = be_transform_node(pred);
4224 ir_graph *irg = current_ir_graph;
4225 dbg_info *dbgi = get_irn_dbg_info(node);
4226 ir_mode *mode = get_irn_mode(node);
4227 long proj = get_Proj_proj(node);
4231 if (is_ia32_xDiv(new_pred)) {
4232 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xDiv_M);
4233 } else if (is_ia32_vfdiv(new_pred)) {
4234 return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
4238 if (is_ia32_xDiv(new_pred)) {
4239 return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
4240 } else if (is_ia32_vfdiv(new_pred)) {
4241 return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
4249 return new_rd_Unknown(irg, mode);
4253 * Transform the Thread Local Storage Proj.
4255 static ir_node *gen_Proj_tls(ir_node *node) {
4256 ir_node *block = be_transform_node(get_nodes_block(node));
4257 ir_graph *irg = current_ir_graph;
4258 dbg_info *dbgi = NULL;
4259 ir_node *res = new_rd_ia32_LdTls(dbgi, irg, block, mode_Iu);
4264 static ir_node *gen_be_Call(ir_node *node) {
4265 ir_node *res = be_duplicate_node(node);
4266 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4271 static ir_node *gen_be_IncSP(ir_node *node) {
4272 ir_node *res = be_duplicate_node(node);
4273 be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
4279 * Transform the Projs from a be_Call.
4281 static ir_node *gen_Proj_be_Call(ir_node *node) {
4282 ir_node *block = be_transform_node(get_nodes_block(node));
4283 ir_node *call = get_Proj_pred(node);
4284 ir_node *new_call = be_transform_node(call);
4285 ir_graph *irg = current_ir_graph;
4286 dbg_info *dbgi = get_irn_dbg_info(node);
4287 ir_type *method_type = be_Call_get_type(call);
4288 int n_res = get_method_n_ress(method_type);
4289 long proj = get_Proj_proj(node);
4290 ir_mode *mode = get_irn_mode(node);
4292 const arch_register_class_t *cls;
4294 /* The following is kinda tricky: If we're using SSE, then we have to
4295 * move the result value of the call in floating point registers to an
4296 * xmm register, we therefore construct a GetST0 -> xLoad sequence
4297 * after the call, we have to make sure to correctly make the
4298 * MemProj and the result Proj use these 2 nodes
4300 if (proj == pn_be_Call_M_regular) {
4301 // get new node for result, are we doing the sse load/store hack?
4302 ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
4303 ir_node *call_res_new;
4304 ir_node *call_res_pred = NULL;
4306 if (call_res != NULL) {
4307 call_res_new = be_transform_node(call_res);
4308 call_res_pred = get_Proj_pred(call_res_new);
4311 if (call_res_pred == NULL || be_is_Call(call_res_pred)) {
4312 return new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4313 pn_be_Call_M_regular);
4315 assert(is_ia32_xLoad(call_res_pred));
4316 return new_rd_Proj(dbgi, irg, block, call_res_pred, mode_M,
4320 if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
4321 && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
4322 && USE_SSE2(env_cg)) {
4324 ir_node *frame = get_irg_frame(irg);
4325 ir_node *noreg = ia32_new_NoReg_gp(env_cg);
4327 ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
4330 /* in case there is no memory output: create one to serialize the copy
4332 call_mem = new_rd_Proj(dbgi, irg, block, new_call, mode_M,
4333 pn_be_Call_M_regular);
4334 call_res = new_rd_Proj(dbgi, irg, block, new_call, mode,
4335 pn_be_Call_first_res);
4337 /* store st(0) onto stack */
4338 fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
4340 set_ia32_op_type(fstp, ia32_AddrModeD);
4341 set_ia32_use_frame(fstp);
4343 /* load into SSE register */
4344 sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
4346 set_ia32_op_type(sse_load, ia32_AddrModeS);
4347 set_ia32_use_frame(sse_load);
4349 sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
4355 /* transform call modes */
4356 if (mode_is_data(mode)) {
4357 cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
4361 return new_rd_Proj(dbgi, irg, block, new_call, mode, proj);
4365 * Transform the Projs from a Cmp.
4367 static ir_node *gen_Proj_Cmp(ir_node *node)
4369 /* normally Cmps are processed when looking at Cond nodes, but this case
4370 * can happen in complicated Psi conditions */
4371 dbg_info *dbgi = get_irn_dbg_info(node);
4372 ir_node *block = get_nodes_block(node);
4373 ir_node *new_block = be_transform_node(block);
4374 ir_node *cmp = get_Proj_pred(node);
4375 ir_node *new_cmp = be_transform_node(cmp);
4376 long pnc = get_Proj_proj(node);
4379 res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
4385 * Transform and potentially renumber Proj nodes.
4387 static ir_node *gen_Proj(ir_node *node) {
4388 ir_graph *irg = current_ir_graph;
4389 dbg_info *dbgi = get_irn_dbg_info(node);
4390 ir_node *pred = get_Proj_pred(node);
4391 long proj = get_Proj_proj(node);
4393 if (is_Store(pred)) {
4394 if (proj == pn_Store_M) {
4395 return be_transform_node(pred);
4398 return new_r_Bad(irg);
4400 } else if (is_Load(pred)) {
4401 return gen_Proj_Load(node);
4402 } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
4403 return gen_Proj_DivMod(node);
4404 } else if (is_CopyB(pred)) {
4405 return gen_Proj_CopyB(node);
4406 } else if (is_Quot(pred)) {
4407 return gen_Proj_Quot(node);
4408 } else if (is_ia32_l_vfdiv(pred)) {
4409 return gen_Proj_l_vfdiv(node);
4410 } else if (be_is_SubSP(pred)) {
4411 return gen_Proj_be_SubSP(node);
4412 } else if (be_is_AddSP(pred)) {
4413 return gen_Proj_be_AddSP(node);
4414 } else if (be_is_Call(pred)) {
4415 return gen_Proj_be_Call(node);
4416 } else if (is_Cmp(pred)) {
4417 return gen_Proj_Cmp(node);
4418 } else if (get_irn_op(pred) == op_Start) {
4419 if (proj == pn_Start_X_initial_exec) {
4420 ir_node *block = get_nodes_block(pred);
4423 /* we exchange the ProjX with a jump */
4424 block = be_transform_node(block);
4425 jump = new_rd_Jmp(dbgi, irg, block);
4428 if (node == be_get_old_anchor(anchor_tls)) {
4429 return gen_Proj_tls(node);
4432 } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
4436 ir_node *new_pred = be_transform_node(pred);
4437 ir_node *block = be_transform_node(get_nodes_block(node));
4438 ir_mode *mode = get_irn_mode(node);
4439 if (mode_needs_gp_reg(mode)) {
4440 ir_node *new_proj = new_r_Proj(irg, block, new_pred, mode_Iu,
4441 get_Proj_proj(node));
4442 #ifdef DEBUG_libfirm
4443 new_proj->node_nr = node->node_nr;
4449 return be_duplicate_node(node);
4453 * Enters all transform functions into the generic pointer
4455 static void register_transformers(void)
4459 /* first clear the generic function pointer for all ops */
4460 clear_irp_opcodes_generic_func();
4462 #define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
4463 #define BAD(a) op_##a->ops.generic = (op_func)bad_transform
4501 /* transform ops from intrinsic lowering */
4523 GEN(ia32_l_X87toSSE);
4524 GEN(ia32_l_SSEtoX87);
4530 /* we should never see these nodes */
4545 /* handle generic backend nodes */
4554 op_Mulh = get_op_Mulh();
4563 * Pre-transform all unknown and noreg nodes.
4565 static void ia32_pretransform_node(void *arch_cg) {
4566 ia32_code_gen_t *cg = arch_cg;
4568 cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
4569 cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
4570 cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
4571 cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
4572 cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
4573 cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
4578 * Walker, checks if all ia32 nodes producing more than one result have
4579 * its Projs, other wise creates new projs and keep them using a be_Keep node.
4581 static void add_missing_keep_walker(ir_node *node, void *data)
4584 unsigned found_projs = 0;
4585 const ir_edge_t *edge;
4586 ir_mode *mode = get_irn_mode(node);
4591 if(!is_ia32_irn(node))
4594 n_outs = get_ia32_n_res(node);
4597 if(is_ia32_SwitchJmp(node))
4600 assert(n_outs < (int) sizeof(unsigned) * 8);
4601 foreach_out_edge(node, edge) {
4602 ir_node *proj = get_edge_src_irn(edge);
4603 int pn = get_Proj_proj(proj);
4605 assert(get_irn_mode(proj) == mode_M || pn < n_outs);
4606 found_projs |= 1 << pn;
4610 /* are keeps missing? */
4612 for(i = 0; i < n_outs; ++i) {
4615 const arch_register_req_t *req;
4616 const arch_register_class_t *class;
4618 if(found_projs & (1 << i)) {
4622 req = get_ia32_out_req(node, i);
4627 if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
4631 block = get_nodes_block(node);
4632 in[0] = new_r_Proj(current_ir_graph, block, node,
4633 arch_register_class_mode(class), i);
4634 if(last_keep != NULL) {
4635 be_Keep_add_node(last_keep, class, in[0]);
4637 last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
4638 if(sched_is_scheduled(node)) {
4639 sched_add_after(node, last_keep);
4646 * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
4649 void ia32_add_missing_keeps(ia32_code_gen_t *cg)
4651 ir_graph *irg = be_get_birg_irg(cg->birg);
4652 irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
4655 /* do the transformation */
4656 void ia32_transform_graph(ia32_code_gen_t *cg) {
4657 register_transformers();
4659 initial_fpcw = NULL;
4661 heights = heights_new(cg->irg);
4663 be_transform_graph(cg->birg, ia32_pretransform_node, cg);
4665 heights_free(heights);
4669 void ia32_init_transform(void)
4671 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.transform");